1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2021 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### How to use this driver #####
27 ==============================================================================
28 [..]
29 The SPI HAL driver can be used as follows:
30
31 (#) Declare a SPI_HandleTypeDef handle structure, for example:
32 SPI_HandleTypeDef hspi;
33
34 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
35 (##) Enable the SPIx interface clock
36 (##) SPI pins configuration
37 (+++) Enable the clock for the SPI GPIOs
38 (+++) Configure these SPI pins as alternate function push-pull
39 (##) NVIC configuration if you need to use interrupt process or DMA process
40 (+++) Configure the SPIx interrupt priority
41 (+++) Enable the NVIC SPI IRQ handle
42 (##) DMA Configuration if you need to use DMA process
43 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
44 (+++) Enable the DMAx clock
45 (+++) Configure the DMA handle parameters
46 (+++) Configure the DMA Tx or Rx Stream/Channel
47 (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
48 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx
49 or Rx Stream/Channel
50
51 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
52 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
53
54 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
55 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
56 by calling the customized HAL_SPI_MspInit() API.
57 [..]
58 Callback registration:
59
60 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1UL
61 allows the user to configure dynamically the driver callbacks.
62 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
63
64 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
65 (+) TxCpltCallback : SPI Tx Completed callback
66 (+) RxCpltCallback : SPI Rx Completed callback
67 (+) TxRxCpltCallback : SPI TxRx Completed callback
68 (+) TxHalfCpltCallback : SPI Tx Half Completed callback
69 (+) RxHalfCpltCallback : SPI Rx Half Completed callback
70 (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
71 (+) ErrorCallback : SPI Error callback
72 (+) AbortCpltCallback : SPI Abort callback
73 (+) SuspendCallback : SPI Suspend callback
74 (+) MspInitCallback : SPI Msp Init callback
75 (+) MspDeInitCallback : SPI Msp DeInit callback
76 This function takes as parameters the HAL peripheral handle, the Callback ID
77 and a pointer to the user callback function.
78
79
80 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
81 weak function.
82 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
83 and the Callback ID.
84 This function allows to reset following callbacks:
85 (+) TxCpltCallback : SPI Tx Completed callback
86 (+) RxCpltCallback : SPI Rx Completed callback
87 (+) TxRxCpltCallback : SPI TxRx Completed callback
88 (+) TxHalfCpltCallback : SPI Tx Half Completed callback
89 (+) RxHalfCpltCallback : SPI Rx Half Completed callback
90 (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
91 (+) ErrorCallback : SPI Error callback
92 (+) AbortCpltCallback : SPI Abort callback
93 (+) SuspendCallback : SPI Suspend callback
94 (+) MspInitCallback : SPI Msp Init callback
95 (+) MspDeInitCallback : SPI Msp DeInit callback
96
97 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
98 all callbacks are set to the corresponding weak functions:
99 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
100 Exception done for MspInit and MspDeInit functions that are
101 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
102 these callbacks are null (not registered beforehand).
103 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
104 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
105
106 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
107 Exception done MspInit/MspDeInit functions that can be registered/unregistered
108 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
109 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
110 Then, the user first registers the MspInit/MspDeInit user callbacks
111 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
112 or HAL_SPI_Init() function.
113
114 When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or not defined,
115 the callback registering feature is not available and weak callbacks are used.
116
117 SuspendCallback restriction:
118 SuspendCallback is called only when MasterReceiverAutoSusp is enabled and
119 EOT interrupt is activated. SuspendCallback is used in relation with functions
120 HAL_SPI_Transmit_IT, HAL_SPI_Receive_IT and HAL_SPI_TransmitReceive_IT.
121
122 [..]
123 Circular mode restriction:
124 (+) The DMA circular mode cannot be used when the SPI is configured in these modes:
125 (++) Master 2Lines RxOnly
126 (++) Master 1Line Rx
127 (+) The CRC feature is not managed when the DMA circular mode is enabled
128 (+) The functions HAL_SPI_DMAPause()/ HAL_SPI_DMAResume() are not supported. Return always
129 HAL_ERROR with ErrorCode set to HAL_SPI_ERROR_NOT_SUPPORTED.
130 Those functions are maintained for backward compatibility reasons.
131
132 @endverbatim
133 */
134
135 /* Includes ------------------------------------------------------------------*/
136 #include "stm32u5xx_hal.h"
137
138 /** @addtogroup STM32U5xx_HAL_Driver
139 * @{
140 */
141
142 /** @defgroup SPI SPI
143 * @brief SPI HAL module driver
144 * @{
145 */
146 #ifdef HAL_SPI_MODULE_ENABLED
147
148 /* Private typedef -----------------------------------------------------------*/
149 /* Private defines -----------------------------------------------------------*/
150 /** @defgroup SPI_Private_Constants SPI Private Constants
151 * @{
152 */
153 #define SPI_DEFAULT_TIMEOUT 100UL
154 /**
155 * @}
156 */
157
158 /* Private macros ------------------------------------------------------------*/
159 /* Private variables ---------------------------------------------------------*/
160 /* Private function prototypes -----------------------------------------------*/
161 /** @defgroup SPI_Private_Functions SPI Private Functions
162 * @{
163 */
164 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
165 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
166 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
167 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
168 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
169 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
170 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
171 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
172 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
173 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
174 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag,
175 FlagStatus FlagStatus, uint32_t Timeout, uint32_t Tickstart);
176 static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi);
177 static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi);
178 static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi);
179 static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi);
180 static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi);
181 static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi);
182 static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi);
183 static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi);
184 static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi);
185
186
187 /**
188 * @}
189 */
190
191 /* Exported functions --------------------------------------------------------*/
192 /** @defgroup SPI_Exported_Functions SPI Exported Functions
193 * @{
194 */
195
196 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
197 * @brief Initialization and Configuration functions
198 *
199 @verbatim
200 ===============================================================================
201 ##### Initialization and de-initialization functions #####
202 ===============================================================================
203 [..] This subsection provides a set of functions allowing to initialize and
204 de-initialize the SPIx peripheral:
205
206 (+) User must implement HAL_SPI_MspInit() function in which he configures
207 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
208
209 (+) Call the function HAL_SPI_Init() to configure the selected device with
210 the selected configuration:
211 (++) Mode
212 (++) Direction
213 (++) Data Size
214 (++) Clock Polarity and Phase
215 (++) NSS Management
216 (++) BaudRate Prescaler
217 (++) FirstBit
218 (++) TIMode
219 (++) CRC Calculation
220 (++) CRC Polynomial if CRC enabled
221 (++) CRC Length, used only with Data8 and Data16
222 (++) FIFO reception threshold
223 (++) FIFO transmission threshold
224
225 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
226 of the selected SPIx peripheral.
227
228 @endverbatim
229 * @{
230 */
231
232 /**
233 * @brief Initialize the SPI according to the specified parameters
234 * in the SPI_InitTypeDef and initialize the associated handle.
235 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
236 * the configuration information for SPI module.
237 * @retval HAL status
238 */
HAL_SPI_Init(SPI_HandleTypeDef * hspi)239 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
240 {
241 uint32_t crc_length;
242 uint32_t packet_length;
243 #if (USE_SPI_CRC != 0UL)
244 uint32_t crc_poly_msb_mask;
245 #endif /* USE_SPI_CRC */
246
247 /* Check the SPI handle allocation */
248 if (hspi == NULL)
249 {
250 return HAL_ERROR;
251 }
252
253 /* Check the parameters */
254 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
255 assert_param(IS_SPI_MODE(hspi->Init.Mode));
256 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
257 if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
258 {
259 assert_param(IS_SPI_LIMITED_DATASIZE(hspi->Init.DataSize));
260 assert_param(IS_SPI_LIMITED_FIFOTHRESHOLD(hspi->Init.FifoThreshold));
261 }
262 else
263 {
264 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
265 assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold));
266 }
267 assert_param(IS_SPI_NSS(hspi->Init.NSS));
268 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
269 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
270 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
271 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
272 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
273 {
274 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
275 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
276 }
277 #if (USE_SPI_CRC != 0UL)
278 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
279 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
280 {
281 if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
282 {
283 assert_param(IS_SPI_LIMITED_CRC_LENGTH(hspi->Init.CRCLength));
284 }
285 else
286 {
287 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
288 }
289 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
290 assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern));
291 assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern));
292 }
293 #else
294 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
295 #endif /* USE_SPI_CRC */
296
297 assert_param(IS_SPI_RDY_MASTER_MANAGEMENT(hspi->Init.ReadyMasterManagement));
298 assert_param(IS_SPI_RDY_POLARITY(hspi->Init.ReadyPolarity));
299 assert_param(IS_SPI_MASTER_RX_AUTOSUSP(hspi->Init.MasterReceiverAutoSusp));
300
301 /* Verify that the SPI instance supports Data Size higher than 16bits */
302 if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT))
303 {
304 return HAL_ERROR;
305 }
306
307 /* Verify that the SPI instance supports requested data packing */
308 packet_length = SPI_GetPacketSize(hspi);
309 if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE)) ||
310 ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE)))
311 {
312 return HAL_ERROR;
313 }
314 #if (USE_SPI_CRC != 0UL)
315 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
316 {
317 /* Verify that the SPI instance supports CRC Length higher than 16bits */
318 if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.CRCLength > SPI_CRC_LENGTH_16BIT))
319 {
320 return HAL_ERROR;
321 }
322
323 /* Align the CRC Length on the data size */
324 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
325 {
326 crc_length = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) << SPI_CFG1_CRCSIZE_Pos;
327 }
328 else
329 {
330 crc_length = hspi->Init.CRCLength;
331 }
332
333 /* Verify the correctness of polynom size */
334 assert_param(IS_SPI_CRC_POLYNOMIAL_SIZE(hspi->Init.CRCPolynomial, crc_length));
335
336 /* Verify that the CRC Length is higher than DataSize */
337 if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos))
338 {
339 return HAL_ERROR;
340 }
341 }
342 else
343 {
344 crc_length = hspi->Init.DataSize << SPI_CFG1_CRCSIZE_Pos;
345 }
346 #endif /* USE_SPI_CRC */
347
348 if (hspi->State == HAL_SPI_STATE_RESET)
349 {
350 /* Allocate lock resource and initialize it */
351 hspi->Lock = HAL_UNLOCKED;
352
353 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
354 /* Init the SPI Callback settings */
355 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
356 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
357 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
358 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
359 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
360 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
361 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
362 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
363 hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */
364
365 if (hspi->MspInitCallback == NULL)
366 {
367 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
368 }
369
370 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
371 hspi->MspInitCallback(hspi);
372 #else
373 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
374 HAL_SPI_MspInit(hspi);
375 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
376 }
377
378 hspi->State = HAL_SPI_STATE_BUSY;
379
380 /* Disable the selected SPI peripheral */
381 __HAL_SPI_DISABLE(hspi);
382
383 #if (USE_SPI_CRC == 0)
384 /* Keep the default value of CRCSIZE in case of CRC is not used */
385 crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE;
386 #endif /* USE_SPI_CRC */
387
388 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
389 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
390 Communication speed, First bit, CRC calculation state, CRC Length */
391
392 /* SPIx NSS Software Management Configuration */
393 if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && \
394 (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \
395 ((hspi->Init.Mode == SPI_MODE_SLAVE) && \
396 (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH))))
397 {
398 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI);
399 }
400
401 /* SPIx Master Rx Auto Suspend Configuration */
402 if (((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) && (hspi->Init.DataSize >= SPI_DATASIZE_8BIT))
403 {
404 MODIFY_REG(hspi->Instance->CR1, SPI_CR1_MASRX, hspi->Init.MasterReceiverAutoSusp);
405 }
406 else
407 {
408 CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_MASRX);
409 }
410
411 /* SPIx CFG1 Configuration */
412 WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length |
413 hspi->Init.FifoThreshold | hspi->Init.DataSize));
414
415 /* SPIx CFG2 Configuration */
416 WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode |
417 hspi->Init.NSSPolarity | hspi->Init.NSS |
418 hspi->Init.CLKPolarity | hspi->Init.CLKPhase |
419 hspi->Init.FirstBit | hspi->Init.Mode |
420 hspi->Init.MasterInterDataIdleness | hspi->Init.Direction |
421 hspi->Init.MasterSSIdleness | hspi->Init.IOSwap |
422 hspi->Init.ReadyMasterManagement | hspi->Init.ReadyPolarity));
423
424 #if (USE_SPI_CRC != 0UL)
425 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
426 /* Configure : CRC Polynomial */
427 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
428 {
429 /* Initialize TXCRC Pattern Initial Value */
430 if (hspi->Init.TxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
431 {
432 SET_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
433 }
434 else
435 {
436 CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
437 }
438
439 /* Initialize RXCRC Pattern Initial Value */
440 if (hspi->Init.RxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
441 {
442 SET_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
443 }
444 else
445 {
446 CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
447 }
448
449 /* Enable 33/17 bits CRC computation */
450 if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) ||
451 ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT)))
452 {
453 /* Set SPI_CR1_CRC33_17 bit */
454 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
455 /* Write CRC polynomial in SPI Register */
456 WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial);
457 }
458 else
459 {
460 /* Clear SPI_CR1_CRC33_17 bit */
461 CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
462
463 /* Write CRC polynomial and set MSB bit at 1 in SPI Register */
464 /* Set MSB is mandatory for a correct CRC computation */
465 crc_poly_msb_mask = (0x1UL << ((crc_length >> SPI_CFG1_CRCSIZE_Pos) + 0x1U));
466 WRITE_REG(hspi->Instance->CRCPOLY, (hspi->Init.CRCPolynomial) | crc_poly_msb_mask);
467 }
468 }
469 #endif /* USE_SPI_CRC */
470
471 /* Insure that Underrun configuration is managed only by Salve */
472 if (hspi->Init.Mode == SPI_MODE_SLAVE)
473 {
474 #if (USE_SPI_CRC != 0UL)
475 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG);
476 #endif /* USE_SPI_CRC */
477 }
478
479 #if defined(SPI_I2SCFGR_I2SMOD)
480 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
481 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
482 #endif /* SPI_I2SCFGR_I2SMOD */
483
484 /* Insure that AFCNTR is managed only by Master */
485 if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER)
486 {
487 /* Alternate function GPIOs control */
488 MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState));
489 }
490
491 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
492 hspi->State = HAL_SPI_STATE_READY;
493
494 return HAL_OK;
495 }
496
497 /**
498 * @brief De-Initialize the SPI peripheral.
499 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
500 * the configuration information for SPI module.
501 * @retval HAL status
502 */
HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)503 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
504 {
505 /* Check the SPI handle allocation */
506 if (hspi == NULL)
507 {
508 return HAL_ERROR;
509 }
510
511 /* Check SPI Instance parameter */
512 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
513
514 hspi->State = HAL_SPI_STATE_BUSY;
515
516 /* Disable the SPI Peripheral Clock */
517 __HAL_SPI_DISABLE(hspi);
518
519 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
520 if (hspi->MspDeInitCallback == NULL)
521 {
522 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
523 }
524
525 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
526 hspi->MspDeInitCallback(hspi);
527 #else
528 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
529 HAL_SPI_MspDeInit(hspi);
530 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
531
532 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
533 hspi->State = HAL_SPI_STATE_RESET;
534
535 /* Release Lock */
536 __HAL_UNLOCK(hspi);
537
538 return HAL_OK;
539 }
540
541 /**
542 * @brief Initialize the SPI MSP.
543 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
544 * the configuration information for SPI module.
545 * @retval None
546 */
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)547 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
548 {
549 /* Prevent unused argument(s) compilation warning */
550 UNUSED(hspi);
551
552 /* NOTE : This function should not be modified, when the callback is needed,
553 the HAL_SPI_MspInit should be implemented in the user file
554 */
555 }
556
557 /**
558 * @brief De-Initialize the SPI MSP.
559 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
560 * the configuration information for SPI module.
561 * @retval None
562 */
HAL_SPI_MspDeInit(SPI_HandleTypeDef * hspi)563 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
564 {
565 /* Prevent unused argument(s) compilation warning */
566 UNUSED(hspi);
567
568 /* NOTE : This function should not be modified, when the callback is needed,
569 the HAL_SPI_MspDeInit should be implemented in the user file
570 */
571 }
572
573 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
574 /**
575 * @brief Register a User SPI Callback
576 * To be used instead of the weak predefined callback
577 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
578 * the configuration information for the specified SPI.
579 * @param CallbackID ID of the callback to be registered
580 * @param pCallback pointer to the Callback function
581 * @note The HAL_SPI_RegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET
582 * to register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID
583 * @retval HAL status
584 */
HAL_SPI_RegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID,pSPI_CallbackTypeDef pCallback)585 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
586 pSPI_CallbackTypeDef pCallback)
587 {
588 HAL_StatusTypeDef status = HAL_OK;
589
590 if (pCallback == NULL)
591 {
592 /* Update the error code */
593 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
594
595 return HAL_ERROR;
596 }
597
598 if (HAL_SPI_STATE_READY == hspi->State)
599 {
600 switch (CallbackID)
601 {
602 case HAL_SPI_TX_COMPLETE_CB_ID :
603 hspi->TxCpltCallback = pCallback;
604 break;
605
606 case HAL_SPI_RX_COMPLETE_CB_ID :
607 hspi->RxCpltCallback = pCallback;
608 break;
609
610 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
611 hspi->TxRxCpltCallback = pCallback;
612 break;
613
614 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
615 hspi->TxHalfCpltCallback = pCallback;
616 break;
617
618 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
619 hspi->RxHalfCpltCallback = pCallback;
620 break;
621
622 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
623 hspi->TxRxHalfCpltCallback = pCallback;
624 break;
625
626 case HAL_SPI_ERROR_CB_ID :
627 hspi->ErrorCallback = pCallback;
628 break;
629
630 case HAL_SPI_ABORT_CB_ID :
631 hspi->AbortCpltCallback = pCallback;
632 break;
633
634 case HAL_SPI_SUSPEND_CB_ID :
635 hspi->SuspendCallback = pCallback;
636 break;
637
638 case HAL_SPI_MSPINIT_CB_ID :
639 hspi->MspInitCallback = pCallback;
640 break;
641
642 case HAL_SPI_MSPDEINIT_CB_ID :
643 hspi->MspDeInitCallback = pCallback;
644 break;
645
646 default :
647 /* Update the error code */
648 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
649
650 /* Return error status */
651 status = HAL_ERROR;
652 break;
653 }
654 }
655 else if (HAL_SPI_STATE_RESET == hspi->State)
656 {
657 switch (CallbackID)
658 {
659 case HAL_SPI_MSPINIT_CB_ID :
660 hspi->MspInitCallback = pCallback;
661 break;
662
663 case HAL_SPI_MSPDEINIT_CB_ID :
664 hspi->MspDeInitCallback = pCallback;
665 break;
666
667 default :
668 /* Update the error code */
669 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
670
671 /* Return error status */
672 status = HAL_ERROR;
673 break;
674 }
675 }
676 else
677 {
678 /* Update the error code */
679 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
680
681 /* Return error status */
682 status = HAL_ERROR;
683 }
684
685 return status;
686 }
687
688 /**
689 * @brief Unregister an SPI Callback
690 * SPI callback is redirected to the weak predefined callback
691 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
692 * the configuration information for the specified SPI.
693 * @param CallbackID ID of the callback to be unregistered
694 * @note The HAL_SPI_UnRegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET
695 * to un-register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID
696 * @retval HAL status
697 */
HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID)698 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
699 {
700 HAL_StatusTypeDef status = HAL_OK;
701
702 if (HAL_SPI_STATE_READY == hspi->State)
703 {
704 switch (CallbackID)
705 {
706 case HAL_SPI_TX_COMPLETE_CB_ID :
707 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
708 break;
709
710 case HAL_SPI_RX_COMPLETE_CB_ID :
711 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
712 break;
713
714 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
715 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
716 break;
717
718 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
719 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
720 break;
721
722 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
723 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
724 break;
725
726 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
727 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
728 break;
729
730 case HAL_SPI_ERROR_CB_ID :
731 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
732 break;
733
734 case HAL_SPI_ABORT_CB_ID :
735 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
736 break;
737
738 case HAL_SPI_SUSPEND_CB_ID :
739 hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */
740 break;
741
742 case HAL_SPI_MSPINIT_CB_ID :
743 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
744 break;
745
746 case HAL_SPI_MSPDEINIT_CB_ID :
747 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
748 break;
749
750 default :
751 /* Update the error code */
752 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
753
754 /* Return error status */
755 status = HAL_ERROR;
756 break;
757 }
758 }
759 else if (HAL_SPI_STATE_RESET == hspi->State)
760 {
761 switch (CallbackID)
762 {
763 case HAL_SPI_MSPINIT_CB_ID :
764 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
765 break;
766
767 case HAL_SPI_MSPDEINIT_CB_ID :
768 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
769 break;
770
771 default :
772 /* Update the error code */
773 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
774
775 /* Return error status */
776 status = HAL_ERROR;
777 break;
778 }
779 }
780 else
781 {
782 /* Update the error code */
783 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
784
785 /* Return error status */
786 status = HAL_ERROR;
787 }
788
789 return status;
790 }
791 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
792 /**
793 * @}
794 */
795
796 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
797 * @brief Data transfers functions
798 *
799 @verbatim
800 ==============================================================================
801 ##### IO operation functions #####
802 ===============================================================================
803 [..]
804 This subsection provides a set of functions allowing to manage the SPI
805 data transfers.
806
807 [..] The SPI supports master and slave mode :
808
809 (#) There are two modes of transfer:
810 (##) Blocking mode: The communication is performed in polling mode.
811 The HAL status of all data processing is returned by the same function
812 after finishing transfer.
813 (##) No-Blocking mode: The communication is performed using Interrupts
814 or DMA, These APIs return the HAL status.
815 The end of the data processing will be indicated through the
816 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
817 using DMA mode.
818 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
819 will be executed respectively at the end of the transmit or Receive process
820 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
821
822 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
823 exist for 1Line (simplex) and 2Lines (full duplex) modes.
824
825 @endverbatim
826 * @{
827 */
828
829 /**
830 * @brief Transmit an amount of data in blocking mode.
831 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
832 * the configuration information for SPI module.
833 * @param pData : pointer to data buffer
834 * @param Size : amount of data to be sent
835 * @param Timeout: Timeout duration
836 * @retval HAL status
837 */
HAL_SPI_Transmit(SPI_HandleTypeDef * hspi,const uint8_t * pData,uint16_t Size,uint32_t Timeout)838 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
839 {
840 #if defined (__GNUC__)
841 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
842 #endif /* __GNUC__ */
843
844 uint32_t tickstart;
845
846 /* Check Direction parameter */
847 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
848
849 /* Check transfer size parameter */
850 if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
851 {
852 assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size));
853 }
854 else
855 {
856 assert_param(IS_SPI_TRANSFER_SIZE(Size));
857 }
858
859 /* Init tickstart for timeout management*/
860 tickstart = HAL_GetTick();
861
862 if (hspi->State != HAL_SPI_STATE_READY)
863 {
864 return HAL_BUSY;
865 }
866
867 if ((pData == NULL) || (Size == 0UL))
868 {
869 return HAL_ERROR;
870 }
871
872 /* Lock the process */
873 __HAL_LOCK(hspi);
874
875 /* Set the transaction information */
876 hspi->State = HAL_SPI_STATE_BUSY_TX;
877 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
878 hspi->pTxBuffPtr = (const uint8_t *)pData;
879 hspi->TxXferSize = Size;
880 hspi->TxXferCount = Size;
881
882 /*Init field not used in handle to zero */
883 hspi->pRxBuffPtr = NULL;
884 hspi->RxXferSize = (uint16_t) 0UL;
885 hspi->RxXferCount = (uint16_t) 0UL;
886 hspi->TxISR = NULL;
887 hspi->RxISR = NULL;
888
889 /* Configure communication direction : 1Line */
890 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
891 {
892 SPI_1LINE_TX(hspi);
893 }
894 else
895 {
896 SPI_2LINES_TX(hspi);
897 }
898
899 /* Set the number of data at current transfer */
900 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
901
902 /* Enable SPI peripheral */
903 __HAL_SPI_ENABLE(hspi);
904
905 if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
906 {
907 /* Master transfer start */
908 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
909 }
910
911 /* Transmit data in 32 Bit mode */
912 if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
913 {
914 /* Transmit data in 32 Bit mode */
915 while (hspi->TxXferCount > 0UL)
916 {
917 /* Wait until TXP flag is set to send data */
918 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
919 {
920 *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
921 hspi->pTxBuffPtr += sizeof(uint32_t);
922 hspi->TxXferCount--;
923 }
924 else
925 {
926 /* Timeout management */
927 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
928 {
929 /* Call standard close procedure with error check */
930 SPI_CloseTransfer(hspi);
931
932 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
933 hspi->State = HAL_SPI_STATE_READY;
934
935 /* Unlock the process */
936 __HAL_UNLOCK(hspi);
937
938 return HAL_TIMEOUT;
939 }
940 }
941 }
942 }
943 /* Transmit data in 16 Bit mode */
944 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
945 {
946 /* Transmit data in 16 Bit mode */
947 while (hspi->TxXferCount > 0UL)
948 {
949 /* Wait until TXP flag is set to send data */
950 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
951 {
952 if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
953 {
954 *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
955 hspi->pTxBuffPtr += sizeof(uint32_t);
956 hspi->TxXferCount -= (uint16_t)2UL;
957 }
958 else
959 {
960 #if defined (__GNUC__)
961 *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
962 #else
963 *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
964 #endif /* __GNUC__ */
965 hspi->pTxBuffPtr += sizeof(uint16_t);
966 hspi->TxXferCount--;
967 }
968 }
969 else
970 {
971 /* Timeout management */
972 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
973 {
974 /* Call standard close procedure with error check */
975 SPI_CloseTransfer(hspi);
976
977 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
978 hspi->State = HAL_SPI_STATE_READY;
979
980 /* Unlock the process */
981 __HAL_UNLOCK(hspi);
982
983 return HAL_TIMEOUT;
984 }
985 }
986 }
987 }
988 /* Transmit data in 8 Bit mode */
989 else
990 {
991 while (hspi->TxXferCount > 0UL)
992 {
993 /* Wait until TXP flag is set to send data */
994 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
995 {
996 if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
997 {
998 *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
999 hspi->pTxBuffPtr += sizeof(uint32_t);
1000 hspi->TxXferCount -= (uint16_t)4UL;
1001 }
1002 else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
1003 {
1004 #if defined (__GNUC__)
1005 *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
1006 #else
1007 *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
1008 #endif /* __GNUC__ */
1009 hspi->pTxBuffPtr += sizeof(uint16_t);
1010 hspi->TxXferCount -= (uint16_t)2UL;
1011 }
1012 else
1013 {
1014 *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr);
1015 hspi->pTxBuffPtr += sizeof(uint8_t);
1016 hspi->TxXferCount--;
1017 }
1018 }
1019 else
1020 {
1021 /* Timeout management */
1022 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1023 {
1024 /* Call standard close procedure with error check */
1025 SPI_CloseTransfer(hspi);
1026
1027 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
1028 hspi->State = HAL_SPI_STATE_READY;
1029
1030 /* Unlock the process */
1031 __HAL_UNLOCK(hspi);
1032
1033 return HAL_TIMEOUT;
1034 }
1035 }
1036 }
1037 }
1038
1039 /* Wait for Tx (and CRC) data to be sent */
1040 if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK)
1041 {
1042 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
1043 }
1044
1045 /* Call standard close procedure with error check */
1046 SPI_CloseTransfer(hspi);
1047
1048 hspi->State = HAL_SPI_STATE_READY;
1049
1050 /* Unlock the process */
1051 __HAL_UNLOCK(hspi);
1052
1053 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1054 {
1055 return HAL_ERROR;
1056 }
1057 else
1058 {
1059 return HAL_OK;
1060 }
1061 }
1062
1063 /**
1064 * @brief Receive an amount of data in blocking mode.
1065 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1066 * the configuration information for SPI module.
1067 * @param pData : pointer to data buffer
1068 * @param Size : amount of data to be received
1069 * @param Timeout: Timeout duration
1070 * @retval HAL status
1071 */
HAL_SPI_Receive(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)1072 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1073 {
1074 uint32_t tickstart;
1075 uint32_t temp_sr_reg;
1076 uint16_t init_max_data_in_fifo;
1077 init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U));
1078 #if defined (__GNUC__)
1079 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
1080 #endif /* __GNUC__ */
1081
1082 /* Check Direction parameter */
1083 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
1084
1085 /* Check transfer size parameter */
1086 if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
1087 {
1088 assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size));
1089 }
1090 else
1091 {
1092 assert_param(IS_SPI_TRANSFER_SIZE(Size));
1093 }
1094
1095 /* Init tickstart for timeout management*/
1096 tickstart = HAL_GetTick();
1097
1098 if (hspi->State != HAL_SPI_STATE_READY)
1099 {
1100 return HAL_BUSY;
1101 }
1102
1103 if ((pData == NULL) || (Size == 0UL))
1104 {
1105 return HAL_ERROR;
1106 }
1107
1108 /* Lock the process */
1109 __HAL_LOCK(hspi);
1110
1111 /* Set the transaction information */
1112 hspi->State = HAL_SPI_STATE_BUSY_RX;
1113 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1114 hspi->pRxBuffPtr = (uint8_t *)pData;
1115 hspi->RxXferSize = Size;
1116 hspi->RxXferCount = Size;
1117
1118 /*Init field not used in handle to zero */
1119 hspi->pTxBuffPtr = NULL;
1120 hspi->TxXferSize = (uint16_t) 0UL;
1121 hspi->TxXferCount = (uint16_t) 0UL;
1122 hspi->RxISR = NULL;
1123 hspi->TxISR = NULL;
1124
1125 /* Configure communication direction: 1Line */
1126 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1127 {
1128 SPI_1LINE_RX(hspi);
1129 }
1130 else
1131 {
1132 SPI_2LINES_RX(hspi);
1133 }
1134
1135 /* Set the number of data at current transfer */
1136 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
1137
1138 /* Enable SPI peripheral */
1139 __HAL_SPI_ENABLE(hspi);
1140
1141 if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
1142 {
1143 /* Master transfer start */
1144 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
1145 }
1146
1147 /* Receive data in 32 Bit mode */
1148 if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
1149 {
1150 /* Transfer loop */
1151 while (hspi->RxXferCount > 0UL)
1152 {
1153 /* Evaluate state of SR register */
1154 temp_sr_reg = hspi->Instance->SR;
1155
1156 /* Check the RXP flag */
1157 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
1158 {
1159 *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
1160 hspi->pRxBuffPtr += sizeof(uint32_t);
1161 hspi->RxXferCount--;
1162 }
1163 /* Check RXWNE flag if RXP cannot be reached */
1164 else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
1165 {
1166 *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
1167 hspi->pRxBuffPtr += sizeof(uint32_t);
1168 hspi->RxXferCount--;
1169 }
1170 /* Check if transfer is locked because of a suspend */
1171 else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP))
1172 {
1173 /* Verify suspend is triggered by hardware and not software */
1174 if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
1175 {
1176 __HAL_SPI_CLEAR_SUSPFLAG(hspi);
1177 }
1178 }
1179 else
1180 {
1181 /* Timeout management */
1182 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1183 {
1184 /* Call standard close procedure with error check */
1185 SPI_CloseTransfer(hspi);
1186
1187 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
1188 hspi->State = HAL_SPI_STATE_READY;
1189
1190 /* Unlock the process */
1191 __HAL_UNLOCK(hspi);
1192
1193 return HAL_TIMEOUT;
1194 }
1195 }
1196 }
1197 }
1198 /* Receive data in 16 Bit mode */
1199 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1200 {
1201 /* Transfer loop */
1202 while (hspi->RxXferCount > 0UL)
1203 {
1204 /* Evaluate state of SR register */
1205 temp_sr_reg = hspi->Instance->SR;
1206
1207 /* Check the RXP flag */
1208 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
1209 {
1210 #if defined (__GNUC__)
1211 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
1212 #else
1213 *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
1214 #endif /* __GNUC__ */
1215 hspi->pRxBuffPtr += sizeof(uint16_t);
1216 hspi->RxXferCount--;
1217 }
1218 /* Check RXWNE flag if RXP cannot be reached */
1219 else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
1220 {
1221 #if defined (__GNUC__)
1222 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
1223 #else
1224 *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
1225 #endif /* __GNUC__ */
1226 hspi->pRxBuffPtr += sizeof(uint16_t);
1227 #if defined (__GNUC__)
1228 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
1229 #else
1230 *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
1231 #endif /* __GNUC__ */
1232 hspi->pRxBuffPtr += sizeof(uint16_t);
1233 hspi->RxXferCount -= (uint16_t)2UL;
1234 }
1235 /* Check RXPLVL flags when RXWNE cannot be reached */
1236 else if ((hspi->RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL))
1237 {
1238 #if defined (__GNUC__)
1239 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
1240 #else
1241 *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
1242 #endif /* __GNUC__ */
1243 hspi->pRxBuffPtr += sizeof(uint16_t);
1244 hspi->RxXferCount--;
1245 }
1246 /* Check if transfer is locked because of a suspend */
1247 else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP))
1248 {
1249 /* Verify suspend is triggered by hardware and not software */
1250 if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
1251 {
1252 __HAL_SPI_CLEAR_SUSPFLAG(hspi);
1253 }
1254 }
1255 else
1256 {
1257 /* Timeout management */
1258 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1259 {
1260 /* Call standard close procedure with error check */
1261 SPI_CloseTransfer(hspi);
1262
1263 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
1264 hspi->State = HAL_SPI_STATE_READY;
1265
1266 /* Unlock the process */
1267 __HAL_UNLOCK(hspi);
1268
1269 return HAL_TIMEOUT;
1270 }
1271 }
1272 }
1273 }
1274 /* Receive data in 8 Bit mode */
1275 else
1276 {
1277 /* Transfer loop */
1278 while (hspi->RxXferCount > 0UL)
1279 {
1280 /* Evaluate state of SR register */
1281 temp_sr_reg = hspi->Instance->SR;
1282
1283 /* Check the RXP flag */
1284 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
1285 {
1286 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
1287 hspi->pRxBuffPtr += sizeof(uint8_t);
1288 hspi->RxXferCount--;
1289 }
1290 /* Check RXWNE flag if RXP cannot be reached */
1291 else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
1292 {
1293 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
1294 hspi->pRxBuffPtr += sizeof(uint8_t);
1295 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
1296 hspi->pRxBuffPtr += sizeof(uint8_t);
1297 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
1298 hspi->pRxBuffPtr += sizeof(uint8_t);
1299 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
1300 hspi->pRxBuffPtr += sizeof(uint8_t);
1301 hspi->RxXferCount -= (uint16_t)4UL;
1302 }
1303 /* Check RXPLVL flags when RXWNE cannot be reached */
1304 else if ((hspi->RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL))
1305 {
1306 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
1307 hspi->pRxBuffPtr += sizeof(uint8_t);
1308 hspi->RxXferCount--;
1309 }
1310 /* Check if transfer is locked because of a suspend */
1311 else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP))
1312 {
1313 /* Verify suspend is triggered by hardware and not software */
1314 if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
1315 {
1316 __HAL_SPI_CLEAR_SUSPFLAG(hspi);
1317 }
1318 }
1319 else
1320 {
1321 /* Timeout management */
1322 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1323 {
1324 /* Call standard close procedure with error check */
1325 SPI_CloseTransfer(hspi);
1326
1327 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
1328 hspi->State = HAL_SPI_STATE_READY;
1329
1330 /* Unlock the process */
1331 __HAL_UNLOCK(hspi);
1332
1333 return HAL_TIMEOUT;
1334 }
1335 }
1336 }
1337 }
1338
1339 #if (USE_SPI_CRC != 0UL)
1340 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1341 {
1342 /* Wait for crc data to be received */
1343 if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK)
1344 {
1345 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
1346 }
1347 }
1348 #endif /* USE_SPI_CRC */
1349
1350 /* Call standard close procedure with error check */
1351 SPI_CloseTransfer(hspi);
1352
1353 hspi->State = HAL_SPI_STATE_READY;
1354
1355 /* Unlock the process */
1356 __HAL_UNLOCK(hspi);
1357
1358
1359 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1360 {
1361 return HAL_ERROR;
1362 }
1363 else
1364 {
1365 return HAL_OK;
1366 }
1367 }
1368
1369 /**
1370 * @brief Transmit and Receive an amount of data in blocking mode.
1371 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1372 * the configuration information for SPI module.
1373 * @param pTxData: pointer to transmission data buffer
1374 * @param pRxData: pointer to reception data buffer
1375 * @param Size : amount of data to be sent and received
1376 * @param Timeout: Timeout duration
1377 * @retval HAL status
1378 */
HAL_SPI_TransmitReceive(SPI_HandleTypeDef * hspi,const uint8_t * pTxData,uint8_t * pRxData,uint16_t Size,uint32_t Timeout)1379 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
1380 uint16_t Size, uint32_t Timeout)
1381 {
1382 #if defined (__GNUC__)
1383 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
1384 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
1385 #endif /* __GNUC__ */
1386
1387 uint32_t tickstart;
1388 uint32_t fifo_length;
1389 uint32_t temp_sr_reg;
1390 uint16_t initial_TxXferCount;
1391 uint16_t initial_RxXferCount;
1392 uint16_t init_max_data_in_fifo;
1393 init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U));
1394
1395 /* Check Direction parameter */
1396 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1397
1398 /* Check transfer size parameter */
1399 if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
1400 {
1401 assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size));
1402 }
1403 else
1404 {
1405 assert_param(IS_SPI_TRANSFER_SIZE(Size));
1406 }
1407
1408 /* Init tickstart for timeout management*/
1409 tickstart = HAL_GetTick();
1410
1411 initial_TxXferCount = Size;
1412 initial_RxXferCount = Size;
1413
1414 if (hspi->State != HAL_SPI_STATE_READY)
1415 {
1416 return HAL_BUSY;
1417 }
1418
1419 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
1420 {
1421 return HAL_ERROR;
1422 }
1423
1424 /* Lock the process */
1425 __HAL_LOCK(hspi);
1426
1427 /* Set the transaction information */
1428 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1429 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1430 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1431 hspi->RxXferCount = Size;
1432 hspi->RxXferSize = Size;
1433 hspi->pTxBuffPtr = (const uint8_t *)pTxData;
1434 hspi->TxXferCount = Size;
1435 hspi->TxXferSize = Size;
1436
1437 /*Init field not used in handle to zero */
1438 hspi->RxISR = NULL;
1439 hspi->TxISR = NULL;
1440
1441 /* Set Full-Duplex mode */
1442 SPI_2LINES(hspi);
1443
1444 /* Initialize FIFO length */
1445 if (IS_SPI_FULL_INSTANCE(hspi->Instance))
1446 {
1447 fifo_length = SPI_HIGHEND_FIFO_SIZE;
1448 }
1449 else
1450 {
1451 fifo_length = SPI_LOWEND_FIFO_SIZE;
1452 }
1453
1454 /* Set the number of data at current transfer */
1455 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
1456
1457 __HAL_SPI_ENABLE(hspi);
1458
1459 if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
1460 {
1461 /* Master transfer start */
1462 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
1463 }
1464
1465 /* Transmit and Receive data in 32 Bit mode */
1466 if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
1467 {
1468 /* Adapt fifo length to 32bits data width */
1469 fifo_length = (fifo_length / 4UL);
1470
1471 while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
1472 {
1473 /* Check TXP flag */
1474 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) &&
1475 (initial_RxXferCount < (initial_TxXferCount + fifo_length)))
1476 {
1477 *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
1478 hspi->pTxBuffPtr += sizeof(uint32_t);
1479 hspi->TxXferCount --;
1480 initial_TxXferCount = hspi->TxXferCount;
1481 }
1482
1483 /* Evaluate state of SR register */
1484 temp_sr_reg = hspi->Instance->SR;
1485
1486 if (initial_RxXferCount > 0UL)
1487 {
1488 /* Check the RXP flag */
1489 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
1490 {
1491 *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
1492 hspi->pRxBuffPtr += sizeof(uint32_t);
1493 hspi->RxXferCount--;
1494 initial_RxXferCount = hspi->RxXferCount;
1495 }
1496 /* Check RXWNE flag if RXP cannot be reached */
1497 else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
1498 {
1499 *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
1500 hspi->pRxBuffPtr += sizeof(uint32_t);
1501 hspi->RxXferCount--;
1502 initial_RxXferCount = hspi->RxXferCount;
1503 }
1504 else
1505 {
1506 /* Timeout management */
1507 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1508 {
1509 /* Call standard close procedure with error check */
1510 SPI_CloseTransfer(hspi);
1511
1512 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
1513 hspi->State = HAL_SPI_STATE_READY;
1514
1515 /* Unlock the process */
1516 __HAL_UNLOCK(hspi);
1517
1518 return HAL_TIMEOUT;
1519 }
1520 }
1521 }
1522 }
1523 }
1524 /* Transmit and Receive data in 16 Bit mode */
1525 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1526 {
1527 /* Adapt fifo length to 16bits data width */
1528 fifo_length = (fifo_length / 2UL);
1529
1530 while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
1531 {
1532 /* Check the TXP flag */
1533 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) &&
1534 (initial_RxXferCount < (initial_TxXferCount + fifo_length)))
1535 {
1536 #if defined (__GNUC__)
1537 *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
1538 #else
1539 *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
1540 #endif /* __GNUC__ */
1541 hspi->pTxBuffPtr += sizeof(uint16_t);
1542 hspi->TxXferCount--;
1543 initial_TxXferCount = hspi->TxXferCount;
1544 }
1545
1546 /* Evaluate state of SR register */
1547 temp_sr_reg = hspi->Instance->SR;
1548
1549 if (initial_RxXferCount > 0UL)
1550 {
1551 /* Check the RXP flag */
1552 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
1553 {
1554 #if defined (__GNUC__)
1555 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
1556 #else
1557 *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
1558 #endif /* __GNUC__ */
1559 hspi->pRxBuffPtr += sizeof(uint16_t);
1560 hspi->RxXferCount--;
1561 initial_RxXferCount = hspi->RxXferCount;
1562 }
1563 /* Check RXWNE flag if RXP cannot be reached */
1564 else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
1565 {
1566 #if defined (__GNUC__)
1567 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
1568 #else
1569 *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
1570 #endif /* __GNUC__ */
1571 hspi->pRxBuffPtr += sizeof(uint16_t);
1572 #if defined (__GNUC__)
1573 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
1574 #else
1575 *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
1576 #endif /* __GNUC__ */
1577 hspi->pRxBuffPtr += sizeof(uint16_t);
1578 hspi->RxXferCount -= (uint16_t)2UL;
1579 initial_RxXferCount = hspi->RxXferCount;
1580 }
1581 /* Check RXPLVL flags when RXWNE cannot be reached */
1582 else if ((initial_RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL))
1583 {
1584 #if defined (__GNUC__)
1585 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
1586 #else
1587 *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
1588 #endif /* __GNUC__ */
1589 hspi->pRxBuffPtr += sizeof(uint16_t);
1590 hspi->RxXferCount--;
1591 initial_RxXferCount = hspi->RxXferCount;
1592 }
1593 else
1594 {
1595 /* Timeout management */
1596 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1597 {
1598 /* Call standard close procedure with error check */
1599 SPI_CloseTransfer(hspi);
1600
1601 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
1602 hspi->State = HAL_SPI_STATE_READY;
1603
1604 /* Unlock the process */
1605 __HAL_UNLOCK(hspi);
1606
1607 return HAL_TIMEOUT;
1608 }
1609 }
1610 }
1611 }
1612 }
1613 /* Transmit and Receive data in 8 Bit mode */
1614 else
1615 {
1616 while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
1617 {
1618 /* Check the TXP flag */
1619 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) &&
1620 (initial_RxXferCount < (initial_TxXferCount + fifo_length)))
1621 {
1622 *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr);
1623 hspi->pTxBuffPtr += sizeof(uint8_t);
1624 hspi->TxXferCount--;
1625 initial_TxXferCount = hspi->TxXferCount;
1626 }
1627
1628 /* Evaluate state of SR register */
1629 temp_sr_reg = hspi->Instance->SR;
1630
1631 if (initial_RxXferCount > 0UL)
1632 {
1633 /* Check the RXP flag */
1634 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
1635 {
1636 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
1637 hspi->pRxBuffPtr += sizeof(uint8_t);
1638 hspi->RxXferCount--;
1639 initial_RxXferCount = hspi->RxXferCount;
1640 }
1641 /* Check RXWNE flag if RXP cannot be reached */
1642 else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
1643 {
1644 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
1645 hspi->pRxBuffPtr += sizeof(uint8_t);
1646 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
1647 hspi->pRxBuffPtr += sizeof(uint8_t);
1648 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
1649 hspi->pRxBuffPtr += sizeof(uint8_t);
1650 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
1651 hspi->pRxBuffPtr += sizeof(uint8_t);
1652 hspi->RxXferCount -= (uint16_t)4UL;
1653 initial_RxXferCount = hspi->RxXferCount;
1654 }
1655 /* Check RXPLVL flags when RXWNE cannot be reached */
1656 else if ((initial_RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL))
1657 {
1658 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
1659 hspi->pRxBuffPtr += sizeof(uint8_t);
1660 hspi->RxXferCount--;
1661 initial_RxXferCount = hspi->RxXferCount;
1662 }
1663 else
1664 {
1665 /* Timeout management */
1666 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1667 {
1668 /* Call standard close procedure with error check */
1669 SPI_CloseTransfer(hspi);
1670
1671 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
1672 hspi->State = HAL_SPI_STATE_READY;
1673
1674 /* Unlock the process */
1675 __HAL_UNLOCK(hspi);
1676
1677 return HAL_TIMEOUT;
1678 }
1679 }
1680 }
1681 }
1682 }
1683
1684 /* Wait for Tx/Rx (and CRC) data to be sent/received */
1685 if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK)
1686 {
1687 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
1688 }
1689
1690 /* Call standard close procedure with error check */
1691 SPI_CloseTransfer(hspi);
1692
1693 hspi->State = HAL_SPI_STATE_READY;
1694
1695 /* Unlock the process */
1696 __HAL_UNLOCK(hspi);
1697
1698 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1699 {
1700 return HAL_ERROR;
1701 }
1702 else
1703 {
1704 return HAL_OK;
1705 }
1706 }
1707
1708 /**
1709 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1710 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1711 * the configuration information for SPI module.
1712 * @param pData: pointer to data buffer
1713 * @param Size : amount of data to be sent
1714 * @retval HAL status
1715 */
HAL_SPI_Transmit_IT(SPI_HandleTypeDef * hspi,const uint8_t * pData,uint16_t Size)1716 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
1717 {
1718 /* Check Direction parameter */
1719 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
1720
1721 /* Check transfer size parameter */
1722 if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
1723 {
1724 assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size));
1725 }
1726 else
1727 {
1728 assert_param(IS_SPI_TRANSFER_SIZE(Size));
1729 }
1730
1731 if ((pData == NULL) || (Size == 0UL))
1732 {
1733 return HAL_ERROR;
1734 }
1735
1736 if (hspi->State != HAL_SPI_STATE_READY)
1737 {
1738 return HAL_BUSY;
1739 }
1740
1741 /* Lock the process */
1742 __HAL_LOCK(hspi);
1743
1744 /* Set the transaction information */
1745 hspi->State = HAL_SPI_STATE_BUSY_TX;
1746 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1747 hspi->pTxBuffPtr = (const uint8_t *)pData;
1748 hspi->TxXferSize = Size;
1749 hspi->TxXferCount = Size;
1750
1751 /* Init field not used in handle to zero */
1752 hspi->pRxBuffPtr = NULL;
1753 hspi->RxXferSize = (uint16_t) 0UL;
1754 hspi->RxXferCount = (uint16_t) 0UL;
1755 hspi->RxISR = NULL;
1756
1757 /* Set the function for IT treatment */
1758 if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
1759 {
1760 hspi->TxISR = SPI_TxISR_32BIT;
1761 }
1762 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1763 {
1764 hspi->TxISR = SPI_TxISR_16BIT;
1765 }
1766 else
1767 {
1768 hspi->TxISR = SPI_TxISR_8BIT;
1769 }
1770
1771 /* Configure communication direction : 1Line */
1772 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1773 {
1774 SPI_1LINE_TX(hspi);
1775 }
1776 else
1777 {
1778 SPI_2LINES_TX(hspi);
1779 }
1780
1781 /* Set the number of data at current transfer */
1782 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
1783
1784 /* Enable SPI peripheral */
1785 __HAL_SPI_ENABLE(hspi);
1786
1787 /* Unlock the process */
1788 __HAL_UNLOCK(hspi);
1789
1790 /* Enable EOT, TXP, FRE, MODF and UDR interrupts */
1791 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
1792
1793 if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
1794 {
1795 /* Master transfer start */
1796 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
1797 }
1798
1799 return HAL_OK;
1800 }
1801
1802 /**
1803 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1804 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1805 * the configuration information for SPI module.
1806 * @param pData: pointer to data buffer
1807 * @param Size : amount of data to be sent
1808 * @retval HAL status
1809 */
HAL_SPI_Receive_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1810 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1811 {
1812 /* Check Direction parameter */
1813 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
1814
1815 /* Check transfer size parameter */
1816 if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
1817 {
1818 assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size));
1819 }
1820 else
1821 {
1822 assert_param(IS_SPI_TRANSFER_SIZE(Size));
1823 }
1824
1825 if (hspi->State != HAL_SPI_STATE_READY)
1826 {
1827 return HAL_BUSY;
1828 }
1829
1830 if ((pData == NULL) || (Size == 0UL))
1831 {
1832 return HAL_ERROR;
1833 }
1834
1835 /* Lock the process */
1836 __HAL_LOCK(hspi);
1837
1838 /* Set the transaction information */
1839 hspi->State = HAL_SPI_STATE_BUSY_RX;
1840 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1841 hspi->pRxBuffPtr = (uint8_t *)pData;
1842 hspi->RxXferSize = Size;
1843 hspi->RxXferCount = Size;
1844
1845 /* Init field not used in handle to zero */
1846 hspi->pTxBuffPtr = NULL;
1847 hspi->TxXferSize = (uint16_t) 0UL;
1848 hspi->TxXferCount = (uint16_t) 0UL;
1849 hspi->TxISR = NULL;
1850
1851 /* Set the function for IT treatment */
1852 if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
1853 {
1854 hspi->RxISR = SPI_RxISR_32BIT;
1855 }
1856 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1857 {
1858 hspi->RxISR = SPI_RxISR_16BIT;
1859 }
1860 else
1861 {
1862 hspi->RxISR = SPI_RxISR_8BIT;
1863 }
1864
1865 /* Configure communication direction : 1Line */
1866 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1867 {
1868 SPI_1LINE_RX(hspi);
1869 }
1870 else
1871 {
1872 SPI_2LINES_RX(hspi);
1873 }
1874
1875 /* Note : The SPI must be enabled after unlocking current process
1876 to avoid the risk of SPI interrupt handle execution before current
1877 process unlock */
1878
1879 /* Set the number of data at current transfer */
1880 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
1881
1882 /* Enable SPI peripheral */
1883 __HAL_SPI_ENABLE(hspi);
1884
1885 /* Unlock the process */
1886 __HAL_UNLOCK(hspi);
1887
1888 /* Enable EOT, RXP, OVR, FRE and MODF interrupts */
1889 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
1890
1891 if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
1892 {
1893 /* Master transfer start */
1894 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
1895 }
1896
1897 return HAL_OK;
1898 }
1899
1900 /**
1901 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1902 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
1903 * the configuration information for SPI module.
1904 * @param pTxData: pointer to transmission data buffer
1905 * @param pRxData: pointer to reception data buffer
1906 * @param Size : amount of data to be sent and received
1907 * @retval HAL status
1908 */
HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef * hspi,const uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1909 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
1910 uint16_t Size)
1911 {
1912 uint32_t tmp_TxXferCount;
1913 #if defined (__GNUC__)
1914 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
1915 #endif /* __GNUC__ */
1916
1917 /* Check Direction parameter */
1918 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1919
1920 /* Check transfer size parameter */
1921 if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
1922 {
1923 assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size));
1924 }
1925 else
1926 {
1927 assert_param(IS_SPI_TRANSFER_SIZE(Size));
1928 }
1929
1930 if (hspi->State != HAL_SPI_STATE_READY)
1931 {
1932 return HAL_BUSY;
1933 }
1934
1935 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
1936 {
1937 return HAL_ERROR;
1938 }
1939
1940 /* Lock the process */
1941 __HAL_LOCK(hspi);
1942
1943 /* Set the transaction information */
1944 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1945 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1946 hspi->pTxBuffPtr = (const uint8_t *)pTxData;
1947 hspi->TxXferSize = Size;
1948 hspi->TxXferCount = Size;
1949 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1950 hspi->RxXferSize = Size;
1951 hspi->RxXferCount = Size;
1952 tmp_TxXferCount = hspi->TxXferCount;
1953
1954 /* Set the function for IT treatment */
1955 if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance)))
1956 {
1957 hspi->TxISR = SPI_TxISR_32BIT;
1958 hspi->RxISR = SPI_RxISR_32BIT;
1959 }
1960 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1961 {
1962 hspi->RxISR = SPI_RxISR_16BIT;
1963 hspi->TxISR = SPI_TxISR_16BIT;
1964 }
1965 else
1966 {
1967 hspi->RxISR = SPI_RxISR_8BIT;
1968 hspi->TxISR = SPI_TxISR_8BIT;
1969 }
1970
1971 /* Set Full-Duplex mode */
1972 SPI_2LINES(hspi);
1973
1974 /* Set the number of data at current transfer */
1975 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
1976
1977 /* Enable SPI peripheral */
1978 __HAL_SPI_ENABLE(hspi);
1979
1980 /* Fill in the TxFIFO */
1981 while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL))
1982 {
1983 /* Transmit data in 32 Bit mode */
1984 if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
1985 {
1986 *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
1987 hspi->pTxBuffPtr += sizeof(uint32_t);
1988 hspi->TxXferCount--;
1989 tmp_TxXferCount = hspi->TxXferCount;
1990 }
1991 /* Transmit data in 16 Bit mode */
1992 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1993 {
1994 #if defined (__GNUC__)
1995 *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
1996 #else
1997 *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
1998 #endif /* __GNUC__ */
1999 hspi->pTxBuffPtr += sizeof(uint16_t);
2000 hspi->TxXferCount--;
2001 tmp_TxXferCount = hspi->TxXferCount;
2002 }
2003 /* Transmit data in 8 Bit mode */
2004 else
2005 {
2006 *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr);
2007 hspi->pTxBuffPtr += sizeof(uint8_t);
2008 hspi->TxXferCount--;
2009 tmp_TxXferCount = hspi->TxXferCount;
2010 }
2011 }
2012
2013 /* Unlock the process */
2014 __HAL_UNLOCK(hspi);
2015
2016 /* Enable EOT, DXP, UDR, OVR, FRE and MODF interrupts */
2017 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
2018
2019 if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
2020 {
2021 /* Start Master transfer */
2022 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
2023 }
2024
2025 return HAL_OK;
2026 }
2027
2028
2029
2030
2031 /**
2032 * @brief Transmit an amount of data in non-blocking mode with DMA.
2033 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2034 * the configuration information for SPI module.
2035 * @param pData: pointer to data buffer
2036 * @param Size : amount of data to be sent
2037 * @retval HAL status
2038 */
HAL_SPI_Transmit_DMA(SPI_HandleTypeDef * hspi,const uint8_t * pData,uint16_t Size)2039 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
2040 {
2041 HAL_StatusTypeDef status;
2042
2043 /* Check Direction parameter */
2044 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
2045
2046 /* Check transfer size parameter */
2047 if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
2048 {
2049 assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size));
2050 }
2051 else
2052 {
2053 assert_param(IS_SPI_TRANSFER_SIZE(Size));
2054 }
2055
2056 if (hspi->State != HAL_SPI_STATE_READY)
2057 {
2058 return HAL_BUSY;
2059 }
2060
2061 if ((pData == NULL) || (Size == 0UL))
2062 {
2063 return HAL_ERROR;
2064 }
2065
2066 /* Lock the process */
2067 __HAL_LOCK(hspi);
2068
2069 /* Set the transaction information */
2070 hspi->State = HAL_SPI_STATE_BUSY_TX;
2071 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2072 hspi->pTxBuffPtr = (const uint8_t *)pData;
2073 hspi->TxXferSize = Size;
2074 hspi->TxXferCount = Size;
2075
2076 /* Init field not used in handle to zero */
2077 hspi->pRxBuffPtr = NULL;
2078 hspi->TxISR = NULL;
2079 hspi->RxISR = NULL;
2080 hspi->RxXferSize = (uint16_t)0UL;
2081 hspi->RxXferCount = (uint16_t)0UL;
2082
2083 /* Configure communication direction : 1Line */
2084 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
2085 {
2086 SPI_1LINE_TX(hspi);
2087 }
2088 else
2089 {
2090 SPI_2LINES_TX(hspi);
2091 }
2092
2093 /* Packing mode management is enabled by the DMA settings */
2094 if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.SrcDataWidth != DMA_SRC_DATAWIDTH_WORD) && \
2095 (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \
2096 ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE)))
2097 {
2098 /* Restriction the DMA data received is not allowed in this mode */
2099 __HAL_UNLOCK(hspi);
2100 return HAL_ERROR;
2101 }
2102
2103 /* Adjust XferCount according to DMA alignment / Data size */
2104 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
2105 {
2106 if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
2107 {
2108 hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
2109 }
2110 if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
2111 {
2112 hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL;
2113 }
2114 }
2115 else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
2116 {
2117 if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
2118 {
2119 hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
2120 }
2121 }
2122 else
2123 {
2124 /* Adjustment done */
2125 }
2126
2127 /* Set the SPI TxDMA Half transfer complete callback */
2128 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
2129
2130 /* Set the SPI TxDMA transfer complete callback */
2131 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
2132
2133 /* Set the DMA error callback */
2134 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
2135
2136 /* Set the DMA AbortCpltCallback */
2137 hspi->hdmatx->XferAbortCallback = NULL;
2138
2139 /* Clear TXDMAEN bit*/
2140 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
2141
2142 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
2143 {
2144 hspi->TxXferCount = Size;
2145 }
2146 else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
2147 {
2148 hspi->TxXferCount = Size * 2U;
2149 }
2150 else
2151 {
2152 hspi->TxXferCount = Size * 4U;
2153 }
2154
2155 /* Enable the Tx DMA Stream/Channel */
2156 if ((hspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2157 {
2158 if (hspi->hdmatx->LinkedListQueue != NULL)
2159 {
2160 /* Set DMA data size */
2161 hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->TxXferCount;
2162
2163 /* Set DMA source address */
2164 hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hspi->pTxBuffPtr;
2165
2166 /* Set DMA destination address */
2167 hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR;
2168
2169 status = HAL_DMAEx_List_Start_IT(hspi->hdmatx);
2170 }
2171 else
2172 {
2173 status = HAL_ERROR;
2174 }
2175 }
2176 else
2177 {
2178 status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR,
2179 hspi->TxXferCount);
2180 }
2181
2182 /* Check status */
2183 if (status != HAL_OK)
2184 {
2185 /* Update SPI error code */
2186 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2187 hspi->State = HAL_SPI_STATE_READY;
2188
2189 /* Unlock the process */
2190 __HAL_UNLOCK(hspi);
2191
2192 return HAL_ERROR;
2193 }
2194
2195 /* Set the number of data at current transfer */
2196 if (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)
2197 {
2198 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
2199 }
2200 else
2201 {
2202 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
2203 }
2204
2205 /* Enable Tx DMA Request */
2206 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
2207
2208 /* Enable the SPI Error Interrupt Bit */
2209 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
2210
2211 /* Enable SPI peripheral */
2212 __HAL_SPI_ENABLE(hspi);
2213
2214 if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
2215 {
2216 /* Master transfer start */
2217 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
2218 }
2219
2220 /* Unlock the process */
2221 __HAL_UNLOCK(hspi);
2222
2223 return HAL_OK;
2224 }
2225
2226 /**
2227 * @brief Receive an amount of data in non-blocking mode with DMA.
2228 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2229 * the configuration information for SPI module.
2230 * @param pData: pointer to data buffer
2231 * @param Size : amount of data to be sent
2232 * @note When the CRC feature is enabled the pData Length must be Size + 1.
2233 * @retval HAL status
2234 */
HAL_SPI_Receive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)2235 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
2236 {
2237 HAL_StatusTypeDef status;
2238
2239 /* Check Direction parameter */
2240 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
2241
2242 /* Check transfer size parameter */
2243 if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
2244 {
2245 assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size));
2246 }
2247 else
2248 {
2249 assert_param(IS_SPI_TRANSFER_SIZE(Size));
2250 }
2251
2252 if (hspi->State != HAL_SPI_STATE_READY)
2253 {
2254 __HAL_UNLOCK(hspi);
2255 return HAL_BUSY;
2256 }
2257
2258 if ((pData == NULL) || (Size == 0UL))
2259 {
2260 __HAL_UNLOCK(hspi);
2261 return HAL_ERROR;
2262 }
2263
2264 /* Lock the process */
2265 __HAL_LOCK(hspi);
2266
2267 /* Set the transaction information */
2268 hspi->State = HAL_SPI_STATE_BUSY_RX;
2269 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2270 hspi->pRxBuffPtr = (uint8_t *)pData;
2271 hspi->RxXferSize = Size;
2272 hspi->RxXferCount = Size;
2273
2274 /*Init field not used in handle to zero */
2275 hspi->RxISR = NULL;
2276 hspi->TxISR = NULL;
2277 hspi->TxXferSize = (uint16_t) 0UL;
2278 hspi->TxXferCount = (uint16_t) 0UL;
2279
2280 /* Configure communication direction : 1Line */
2281 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
2282 {
2283 SPI_1LINE_RX(hspi);
2284 }
2285 else
2286 {
2287 SPI_2LINES_RX(hspi);
2288 }
2289
2290 /* Packing mode management is enabled by the DMA settings */
2291 if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \
2292 (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \
2293 ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE)))
2294 {
2295 /* Restriction the DMA data received is not allowed in this mode */
2296 __HAL_UNLOCK(hspi);
2297 return HAL_ERROR;
2298 }
2299
2300 /* Clear RXDMAEN bit */
2301 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
2302
2303 /* Adjust XferCount according to DMA alignment / Data size */
2304 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
2305 {
2306 if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_HALFWORD)
2307 {
2308 hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
2309 }
2310 if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD)
2311 {
2312 hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL;
2313 }
2314 }
2315 else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
2316 {
2317 if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD)
2318 {
2319 hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
2320 }
2321 }
2322 else
2323 {
2324 /* Adjustment done */
2325 }
2326
2327 /* Set the SPI RxDMA Half transfer complete callback */
2328 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2329
2330 /* Set the SPI Rx DMA transfer complete callback */
2331 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2332
2333 /* Set the DMA error callback */
2334 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2335
2336 /* Set the DMA AbortCpltCallback */
2337 hspi->hdmarx->XferAbortCallback = NULL;
2338
2339 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
2340 {
2341 hspi->RxXferCount = Size;
2342 }
2343 else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
2344 {
2345 hspi->RxXferCount = Size * 2U;
2346 }
2347 else
2348 {
2349 hspi->RxXferCount = Size * 4U;
2350 }
2351
2352 /* Enable the Rx DMA Stream/Channel */
2353 if ((hspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2354 {
2355 if (hspi->hdmarx->LinkedListQueue != NULL)
2356 {
2357 /* Set DMA data size */
2358 hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->RxXferCount;
2359
2360 /* Set DMA source address */
2361 hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->RXDR;
2362
2363 /* Set DMA destination address */
2364 hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr;
2365
2366 status = HAL_DMAEx_List_Start_IT(hspi->hdmarx);
2367 }
2368 else
2369 {
2370 status = HAL_ERROR;
2371 }
2372 }
2373 else
2374 {
2375 status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr,
2376 hspi->RxXferCount);
2377 }
2378
2379 /* Check status */
2380 if (status != HAL_OK)
2381 {
2382 /* Update SPI error code */
2383 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2384 hspi->State = HAL_SPI_STATE_READY;
2385
2386 /* Unlock the process */
2387 __HAL_UNLOCK(hspi);
2388
2389 return HAL_ERROR;
2390 }
2391
2392 /* Set the number of data at current transfer */
2393 if (hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR)
2394 {
2395 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
2396 }
2397 else
2398 {
2399 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
2400 }
2401
2402 /* Enable Rx DMA Request */
2403 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
2404
2405 /* Enable the SPI Error Interrupt Bit */
2406 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
2407
2408 /* Enable SPI peripheral */
2409 __HAL_SPI_ENABLE(hspi);
2410
2411 if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
2412 {
2413 /* Master transfer start */
2414 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
2415 }
2416
2417 /* Unlock the process */
2418 __HAL_UNLOCK(hspi);
2419
2420 return HAL_OK;
2421 }
2422
2423 /**
2424 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
2425 * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
2426 * the configuration information for SPI module.
2427 * @param pTxData: pointer to transmission data buffer
2428 * @param pRxData: pointer to reception data buffer
2429 * @param Size : amount of data to be sent
2430 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
2431 * @retval HAL status
2432 */
HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef * hspi,const uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)2433 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
2434 uint16_t Size)
2435 {
2436 HAL_StatusTypeDef status;
2437
2438 /* Check Direction parameter */
2439 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
2440
2441 /* Check transfer size parameter */
2442 if (IS_SPI_LIMITED_INSTANCE(hspi->Instance))
2443 {
2444 assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size));
2445 }
2446 else
2447 {
2448 assert_param(IS_SPI_TRANSFER_SIZE(Size));
2449 }
2450
2451 if (hspi->State != HAL_SPI_STATE_READY)
2452 {
2453 return HAL_BUSY;
2454 }
2455
2456 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
2457 {
2458 return HAL_ERROR;
2459 }
2460
2461 /* Lock the process */
2462 __HAL_LOCK(hspi);
2463
2464 /* Set the transaction information */
2465 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
2466 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2467 hspi->pTxBuffPtr = (const uint8_t *)pTxData;
2468 hspi->TxXferSize = Size;
2469 hspi->TxXferCount = Size;
2470 hspi->pRxBuffPtr = (uint8_t *)pRxData;
2471 hspi->RxXferSize = Size;
2472 hspi->RxXferCount = Size;
2473
2474 /* Init field not used in handle to zero */
2475 hspi->RxISR = NULL;
2476 hspi->TxISR = NULL;
2477
2478 /* Set Full-Duplex mode */
2479 SPI_2LINES(hspi);
2480
2481 /* Reset the Tx/Rx DMA bits */
2482 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
2483
2484 /* Packing mode management is enabled by the DMA settings */
2485 if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && \
2486 ((hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) || \
2487 (hspi->hdmatx->Init.SrcDataWidth != DMA_SRC_DATAWIDTH_WORD)) && \
2488 (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \
2489 ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && \
2490 ((hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE) || \
2491 (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE))))
2492 {
2493 /* Restriction the DMA data received is not allowed in this mode */
2494 /* Unlock the process */
2495 __HAL_UNLOCK(hspi);
2496 return HAL_ERROR;
2497 }
2498
2499 /* Adjust XferCount according to DMA alignment / Data size */
2500 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
2501 {
2502 if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
2503 {
2504 hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
2505 }
2506 if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
2507 {
2508 hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL;
2509 }
2510 if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_HALFWORD)
2511 {
2512 hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
2513 }
2514 if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD)
2515 {
2516 hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL;
2517 }
2518 }
2519 else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
2520 {
2521 if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
2522 {
2523 hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
2524 }
2525 if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD)
2526 {
2527 hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
2528 }
2529 }
2530 else
2531 {
2532 /* Adjustment done */
2533 }
2534
2535 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
2536 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
2537 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
2538
2539 /* Set the DMA error callback */
2540 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2541
2542 /* Set the DMA AbortCallback */
2543 hspi->hdmarx->XferAbortCallback = NULL;
2544
2545 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
2546 {
2547 hspi->RxXferCount = Size;
2548 }
2549 else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
2550 {
2551 hspi->RxXferCount = Size * 2U;
2552 }
2553 else
2554 {
2555 hspi->RxXferCount = Size * 4U;
2556 }
2557 /* Enable the Rx DMA Stream/Channel */
2558 if ((hspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2559 {
2560 if (hspi->hdmarx->LinkedListQueue != NULL)
2561 {
2562 /* Set DMA data size */
2563 hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->RxXferCount;
2564
2565 /* Set DMA source address */
2566 hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->RXDR;
2567
2568 /* Set DMA destination address */
2569 hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr;
2570
2571 status = HAL_DMAEx_List_Start_IT(hspi->hdmarx);
2572 }
2573 else
2574 {
2575 status = HAL_ERROR;
2576 }
2577 }
2578 else
2579 {
2580 status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr,
2581 hspi->RxXferCount);
2582 }
2583
2584 /* Check status */
2585 if (status != HAL_OK)
2586 {
2587 /* Update SPI error code */
2588 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2589 hspi->State = HAL_SPI_STATE_READY;
2590
2591 /* Unlock the process */
2592 __HAL_UNLOCK(hspi);
2593
2594 return HAL_ERROR;
2595 }
2596
2597 /* Enable Rx DMA Request */
2598 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
2599
2600 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2601 is performed in DMA reception complete callback */
2602 hspi->hdmatx->XferHalfCpltCallback = NULL;
2603 hspi->hdmatx->XferCpltCallback = NULL;
2604 hspi->hdmatx->XferAbortCallback = NULL;
2605
2606 /* Set the DMA error callback */
2607 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
2608
2609 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
2610 {
2611 hspi->TxXferCount = Size;
2612 }
2613 else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
2614 {
2615 hspi->TxXferCount = Size * 2U;
2616 }
2617 else
2618 {
2619 hspi->TxXferCount = Size * 4U;
2620 }
2621
2622 /* Enable the Tx DMA Stream/Channel */
2623 if ((hspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2624 {
2625 if (hspi->hdmatx->LinkedListQueue != NULL)
2626 {
2627 /* Set DMA data size */
2628 hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->TxXferCount;
2629
2630 /* Set DMA source address */
2631 hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hspi->pTxBuffPtr;
2632
2633 /* Set DMA destination address */
2634 hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR;
2635
2636 status = HAL_DMAEx_List_Start_IT(hspi->hdmatx);
2637 }
2638 else
2639 {
2640 status = HAL_ERROR;
2641 }
2642 }
2643 else
2644 {
2645 status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR,
2646 hspi->TxXferCount);
2647 }
2648
2649 /* Check status */
2650 if (status != HAL_OK)
2651 {
2652 /* Abort Rx DMA Channel already started */
2653 (void)HAL_DMA_Abort(hspi->hdmarx);
2654
2655 /* Update SPI error code */
2656 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2657 hspi->State = HAL_SPI_STATE_READY;
2658
2659 /* Unlock the process */
2660 __HAL_UNLOCK(hspi);
2661
2662 return HAL_ERROR;
2663 }
2664
2665 if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) && (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR))
2666 {
2667 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
2668 }
2669 else
2670 {
2671 MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
2672 }
2673
2674 /* Enable Tx DMA Request */
2675 SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
2676
2677 /* Enable the SPI Error Interrupt Bit */
2678 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
2679
2680 /* Enable SPI peripheral */
2681 __HAL_SPI_ENABLE(hspi);
2682
2683 if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER))
2684 {
2685 /* Master transfer start */
2686 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
2687 }
2688
2689 /* Unlock the process */
2690 __HAL_UNLOCK(hspi);
2691
2692 return HAL_OK;
2693 }
2694
2695 /**
2696 * @brief Abort ongoing transfer (blocking mode).
2697 * @param hspi SPI handle.
2698 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2699 * started in Interrupt or DMA mode.
2700 * @note This procedure performs following operations :
2701 * + Disable SPI Interrupts (depending of transfer direction)
2702 * + Disable the DMA transfer in the peripheral register (if enabled)
2703 * + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2704 * + Set handle State to READY.
2705 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2706 * @retval HAL status
2707 */
HAL_SPI_Abort(SPI_HandleTypeDef * hspi)2708 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2709 {
2710 HAL_StatusTypeDef errorcode;
2711
2712 __IO uint32_t count;
2713
2714 /* Lock the process */
2715 __HAL_LOCK(hspi);
2716
2717 /* Set hspi->state to aborting to avoid any interaction */
2718 hspi->State = HAL_SPI_STATE_ABORT;
2719
2720 /* Initialized local variable */
2721 errorcode = HAL_OK;
2722 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL);
2723
2724 /* If master communication on going, make sure current frame is done before closing the connection */
2725 if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
2726 {
2727 /* Disable EOT interrupt */
2728 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
2729 do
2730 {
2731 count--;
2732 if (count == 0UL)
2733 {
2734 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2735 break;
2736 }
2737 } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT));
2738
2739 /* Request a Suspend transfer */
2740 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
2741 do
2742 {
2743 count--;
2744 if (count == 0UL)
2745 {
2746 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2747 break;
2748 }
2749 } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
2750
2751 /* Clear SUSP flag */
2752 __HAL_SPI_CLEAR_SUSPFLAG(hspi);
2753 do
2754 {
2755 count--;
2756 if (count == 0UL)
2757 {
2758 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2759 break;
2760 }
2761 } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP));
2762 }
2763
2764 /* Disable the SPI DMA Tx request if enabled */
2765 if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
2766 {
2767 if (hspi->hdmatx != NULL)
2768 {
2769 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2770 hspi->hdmatx->XferAbortCallback = NULL;
2771
2772 /* Abort DMA Tx Handle linked to SPI Peripheral */
2773 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2774 {
2775 if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
2776 {
2777 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2778 }
2779 }
2780 }
2781 }
2782
2783 /* Disable the SPI DMA Rx request if enabled */
2784 if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
2785 {
2786 if (hspi->hdmarx != NULL)
2787 {
2788 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2789 hspi->hdmarx->XferAbortCallback = NULL;
2790
2791 /* Abort DMA Rx Handle linked to SPI Peripheral */
2792 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2793 {
2794 if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
2795 {
2796 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2797 }
2798 }
2799 }
2800 }
2801
2802 /* Proceed with abort procedure */
2803 SPI_AbortTransfer(hspi);
2804
2805 /* Check error during Abort procedure */
2806 if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT))
2807 {
2808 /* return HAL_Error in case of error during Abort procedure */
2809 errorcode = HAL_ERROR;
2810 }
2811 else
2812 {
2813 /* Reset errorCode */
2814 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2815 }
2816
2817 /* Restore hspi->state to ready */
2818 hspi->State = HAL_SPI_STATE_READY;
2819
2820 /* Unlock the process */
2821 __HAL_UNLOCK(hspi);
2822
2823 return errorcode;
2824 }
2825
2826 /**
2827 * @brief Abort ongoing transfer (Interrupt mode).
2828 * @param hspi SPI handle.
2829 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2830 * started in Interrupt or DMA mode.
2831 * @note This procedure performs following operations :
2832 * + Disable SPI Interrupts (depending of transfer direction)
2833 * + Disable the DMA transfer in the peripheral register (if enabled)
2834 * + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2835 * + Set handle State to READY
2836 * + At abort completion, call user abort complete callback.
2837 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2838 * considered as completed only when user abort complete callback is executed (not when exiting function).
2839 * @retval HAL status
2840 */
HAL_SPI_Abort_IT(SPI_HandleTypeDef * hspi)2841 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2842 {
2843 HAL_StatusTypeDef errorcode;
2844 __IO uint32_t count;
2845 uint32_t dma_tx_abort_done = 1UL;
2846 uint32_t dma_rx_abort_done = 1UL;
2847
2848 /* Set hspi->state to aborting to avoid any interaction */
2849 hspi->State = HAL_SPI_STATE_ABORT;
2850
2851 /* Initialized local variable */
2852 errorcode = HAL_OK;
2853 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL);
2854
2855 /* If master communication on going, make sure current frame is done before closing the connection */
2856 if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
2857 {
2858 /* Disable EOT interrupt */
2859 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
2860 do
2861 {
2862 count--;
2863 if (count == 0UL)
2864 {
2865 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2866 break;
2867 }
2868 } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT));
2869
2870 /* Request a Suspend transfer */
2871 SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
2872 do
2873 {
2874 count--;
2875 if (count == 0UL)
2876 {
2877 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2878 break;
2879 }
2880 } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
2881
2882 /* Clear SUSP flag */
2883 __HAL_SPI_CLEAR_SUSPFLAG(hspi);
2884 do
2885 {
2886 count--;
2887 if (count == 0UL)
2888 {
2889 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2890 break;
2891 }
2892 } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP));
2893 }
2894
2895 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized
2896 before any call to DMA Abort functions */
2897
2898 if (hspi->hdmarx != NULL)
2899 {
2900 if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
2901 {
2902 /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */
2903 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2904 }
2905 }
2906
2907 if (hspi->hdmatx != NULL)
2908 {
2909 if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
2910 {
2911 /* Set DMA Abort Complete callback if SPI DMA Tx request if enabled */
2912 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2913
2914 dma_tx_abort_done = 0UL;
2915
2916 /* Abort DMA Tx Handle linked to SPI Peripheral */
2917 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2918 {
2919 if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_NO_XFER)
2920 {
2921 dma_tx_abort_done = 1UL;
2922 hspi->hdmatx->XferAbortCallback = NULL;
2923 }
2924 }
2925 }
2926 else
2927 {
2928 hspi->hdmatx->XferAbortCallback = NULL;
2929 }
2930 }
2931
2932 if (hspi->hdmarx != NULL)
2933 {
2934 if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
2935 {
2936 /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */
2937 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2938
2939 dma_rx_abort_done = 0UL;
2940
2941 /* Abort DMA Rx Handle linked to SPI Peripheral */
2942 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2943 {
2944 if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_NO_XFER)
2945 {
2946 dma_rx_abort_done = 1UL;
2947 hspi->hdmarx->XferAbortCallback = NULL;
2948 }
2949 }
2950 }
2951 else
2952 {
2953 hspi->hdmarx->XferAbortCallback = NULL;
2954 }
2955 }
2956
2957 /* If no running DMA transfer, finish cleanup and call callbacks */
2958 if ((dma_tx_abort_done == 1UL) && (dma_rx_abort_done == 1UL))
2959 {
2960 /* Proceed with abort procedure */
2961 SPI_AbortTransfer(hspi);
2962
2963 /* Check error during Abort procedure */
2964 if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT))
2965 {
2966 /* return HAL_Error in case of error during Abort procedure */
2967 errorcode = HAL_ERROR;
2968 }
2969 else
2970 {
2971 /* Reset errorCode */
2972 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2973 }
2974
2975 /* Restore hspi->state to ready */
2976 hspi->State = HAL_SPI_STATE_READY;
2977
2978 /* Call user Abort complete callback */
2979 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
2980 hspi->AbortCpltCallback(hspi);
2981 #else
2982 HAL_SPI_AbortCpltCallback(hspi);
2983 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2984 }
2985
2986 return errorcode;
2987 }
2988
2989 /**
2990 * @brief Pause the DMA Transfer.
2991 * This API is not supported, it is maintained for backward compatibility.
2992 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
2993 * the configuration information for the specified SPI module.
2994 * @retval HAL_ERROR
2995 */
HAL_SPI_DMAPause(SPI_HandleTypeDef * hspi)2996 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2997 {
2998 /* Set error code to not supported */
2999 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
3000
3001 return HAL_ERROR;
3002 }
3003
3004 /**
3005 * @brief Resume the DMA Transfer.
3006 * This API is not supported, it is maintained for backward compatibility.
3007 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3008 * the configuration information for the specified SPI module.
3009 * @retval HAL_ERROR
3010 */
HAL_SPI_DMAResume(SPI_HandleTypeDef * hspi)3011 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
3012 {
3013 /* Set error code to not supported */
3014 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
3015
3016 return HAL_ERROR;
3017 }
3018
3019 /**
3020 * @brief Stop the DMA Transfer.
3021 * This API is not supported, it is maintained for backward compatibility.
3022 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3023 * the configuration information for the specified SPI module.
3024 * @retval HAL_ERROR
3025 */
HAL_SPI_DMAStop(SPI_HandleTypeDef * hspi)3026 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
3027 {
3028 /* Set error code to not supported */
3029 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
3030
3031 return HAL_ERROR;
3032 }
3033
3034 /**
3035 * @brief Handle SPI interrupt request.
3036 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3037 * the configuration information for the specified SPI module.
3038 * @retval None
3039 */
HAL_SPI_IRQHandler(SPI_HandleTypeDef * hspi)3040 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
3041 {
3042 uint32_t itsource = hspi->Instance->IER;
3043 uint32_t itflag = hspi->Instance->SR;
3044 uint32_t trigger = itsource & itflag;
3045 uint32_t cfg1 = hspi->Instance->CFG1;
3046 uint32_t handled = 0UL;
3047
3048 HAL_SPI_StateTypeDef State = hspi->State;
3049 #if defined (__GNUC__)
3050 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
3051 #endif /* __GNUC__ */
3052
3053 /* SPI in SUSPEND mode ----------------------------------------------------*/
3054 if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT))
3055 {
3056 /* Clear the Suspend flag */
3057 __HAL_SPI_CLEAR_SUSPFLAG(hspi);
3058
3059 /* Suspend on going, Call the Suspend callback */
3060 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3061 hspi->SuspendCallback(hspi);
3062 #else
3063 HAL_SPI_SuspendCallback(hspi);
3064 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3065 return;
3066 }
3067
3068 /* SPI in mode Transmitter and Receiver ------------------------------------*/
3069 if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \
3070 HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP))
3071 {
3072 hspi->TxISR(hspi);
3073 hspi->RxISR(hspi);
3074 handled = 1UL;
3075 }
3076
3077 /* SPI in mode Receiver ----------------------------------------------------*/
3078 if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && \
3079 HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
3080 {
3081 hspi->RxISR(hspi);
3082 handled = 1UL;
3083 }
3084
3085 /* SPI in mode Transmitter -------------------------------------------------*/
3086 if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && \
3087 HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
3088 {
3089 hspi->TxISR(hspi);
3090 handled = 1UL;
3091 }
3092
3093 if (handled != 0UL)
3094 {
3095 return;
3096 }
3097
3098 /* SPI End Of Transfer: DMA or IT based transfer */
3099 if (HAL_IS_BIT_SET(trigger, SPI_FLAG_EOT))
3100 {
3101 /* Clear EOT/TXTF/SUSP flag */
3102 __HAL_SPI_CLEAR_EOTFLAG(hspi);
3103 __HAL_SPI_CLEAR_TXTFFLAG(hspi);
3104 __HAL_SPI_CLEAR_SUSPFLAG(hspi);
3105
3106 /* Disable EOT interrupt */
3107 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
3108
3109 /* For the IT based receive extra polling maybe required for last packet */
3110 if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
3111 {
3112 /* Pooling remaining data */
3113 while (hspi->RxXferCount != 0UL)
3114 {
3115 /* Receive data in 32 Bit mode */
3116 if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
3117 {
3118 *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
3119 hspi->pRxBuffPtr += sizeof(uint32_t);
3120 }
3121 /* Receive data in 16 Bit mode */
3122 else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
3123 {
3124 #if defined (__GNUC__)
3125 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
3126 #else
3127 *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
3128 #endif /* __GNUC__ */
3129 hspi->pRxBuffPtr += sizeof(uint16_t);
3130 }
3131 /* Receive data in 8 Bit mode */
3132 else
3133 {
3134 *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
3135 hspi->pRxBuffPtr += sizeof(uint8_t);
3136 }
3137
3138 hspi->RxXferCount--;
3139 }
3140 }
3141
3142 /* Call SPI Standard close procedure */
3143 SPI_CloseTransfer(hspi);
3144
3145 hspi->State = HAL_SPI_STATE_READY;
3146 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3147 {
3148 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3149 hspi->ErrorCallback(hspi);
3150 #else
3151 HAL_SPI_ErrorCallback(hspi);
3152 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3153 return;
3154 }
3155
3156 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3157 /* Call appropriate user callback */
3158 if (State == HAL_SPI_STATE_BUSY_TX_RX)
3159 {
3160 hspi->TxRxCpltCallback(hspi);
3161 }
3162 else if (State == HAL_SPI_STATE_BUSY_RX)
3163 {
3164 hspi->RxCpltCallback(hspi);
3165 }
3166 else if (State == HAL_SPI_STATE_BUSY_TX)
3167 {
3168 hspi->TxCpltCallback(hspi);
3169 }
3170 #else
3171 /* Call appropriate user callback */
3172 if (State == HAL_SPI_STATE_BUSY_TX_RX)
3173 {
3174 HAL_SPI_TxRxCpltCallback(hspi);
3175 }
3176 else if (State == HAL_SPI_STATE_BUSY_RX)
3177 {
3178 HAL_SPI_RxCpltCallback(hspi);
3179 }
3180 else if (State == HAL_SPI_STATE_BUSY_TX)
3181 {
3182 HAL_SPI_TxCpltCallback(hspi);
3183 }
3184 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3185 else
3186 {
3187 /* End of the appropriate call */
3188 }
3189
3190 return;
3191 }
3192
3193 /* SPI in Error Treatment --------------------------------------------------*/
3194 if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL)
3195 {
3196 /* SPI Overrun error interrupt occurred ----------------------------------*/
3197 if ((trigger & SPI_FLAG_OVR) != 0UL)
3198 {
3199 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
3200 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3201 }
3202
3203 /* SPI Mode Fault error interrupt occurred -------------------------------*/
3204 if ((trigger & SPI_FLAG_MODF) != 0UL)
3205 {
3206 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
3207 __HAL_SPI_CLEAR_MODFFLAG(hspi);
3208 }
3209
3210 /* SPI Frame error interrupt occurred ------------------------------------*/
3211 if ((trigger & SPI_FLAG_FRE) != 0UL)
3212 {
3213 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
3214 __HAL_SPI_CLEAR_FREFLAG(hspi);
3215 }
3216
3217 /* SPI Underrun error interrupt occurred ------------------------------------*/
3218 if ((trigger & SPI_FLAG_UDR) != 0UL)
3219 {
3220 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
3221 __HAL_SPI_CLEAR_UDRFLAG(hspi);
3222 }
3223
3224 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3225 {
3226 /* Disable SPI peripheral */
3227 __HAL_SPI_DISABLE(hspi);
3228
3229 /* Disable all interrupts */
3230 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF |
3231 SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR));
3232
3233 /* Disable the SPI DMA requests if enabled */
3234 if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
3235 {
3236 /* Disable the SPI DMA requests */
3237 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
3238
3239 /* Abort the SPI DMA Rx channel */
3240 if (hspi->hdmarx != NULL)
3241 {
3242 /* Set the SPI DMA Abort callback :
3243 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
3244 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
3245 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
3246 {
3247 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
3248 }
3249 }
3250 /* Abort the SPI DMA Tx channel */
3251 if (hspi->hdmatx != NULL)
3252 {
3253 /* Set the SPI DMA Abort callback :
3254 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
3255 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
3256 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
3257 {
3258 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
3259 }
3260 }
3261 }
3262 else
3263 {
3264 /* Restore hspi->State to Ready */
3265 hspi->State = HAL_SPI_STATE_READY;
3266
3267 /* Call user error callback */
3268 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3269 hspi->ErrorCallback(hspi);
3270 #else
3271 HAL_SPI_ErrorCallback(hspi);
3272 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3273 }
3274 }
3275 return;
3276 }
3277 }
3278
3279 /**
3280 * @brief Tx Transfer completed callback.
3281 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3282 * the configuration information for SPI module.
3283 * @retval None
3284 */
HAL_SPI_TxCpltCallback(SPI_HandleTypeDef * hspi)3285 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
3286 {
3287 /* Prevent unused argument(s) compilation warning */
3288 UNUSED(hspi);
3289
3290 /* NOTE : This function should not be modified, when the callback is needed,
3291 the HAL_SPI_TxCpltCallback should be implemented in the user file
3292 */
3293 }
3294
3295 /**
3296 * @brief Rx Transfer completed callback.
3297 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3298 * the configuration information for SPI module.
3299 * @retval None
3300 */
HAL_SPI_RxCpltCallback(SPI_HandleTypeDef * hspi)3301 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
3302 {
3303 /* Prevent unused argument(s) compilation warning */
3304 UNUSED(hspi);
3305
3306 /* NOTE : This function should not be modified, when the callback is needed,
3307 the HAL_SPI_RxCpltCallback should be implemented in the user file
3308 */
3309 }
3310
3311 /**
3312 * @brief Tx and Rx Transfer completed callback.
3313 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3314 * the configuration information for SPI module.
3315 * @retval None
3316 */
HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef * hspi)3317 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
3318 {
3319 /* Prevent unused argument(s) compilation warning */
3320 UNUSED(hspi);
3321
3322 /* NOTE : This function should not be modified, when the callback is needed,
3323 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
3324 */
3325 }
3326
3327 /**
3328 * @brief Tx Half Transfer completed callback.
3329 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3330 * the configuration information for SPI module.
3331 * @retval None
3332 */
HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef * hspi)3333 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
3334 {
3335 /* Prevent unused argument(s) compilation warning */
3336 UNUSED(hspi);
3337
3338 /* NOTE : This function should not be modified, when the callback is needed,
3339 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
3340 */
3341 }
3342
3343 /**
3344 * @brief Rx Half Transfer completed callback.
3345 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3346 * the configuration information for SPI module.
3347 * @retval None
3348 */
HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef * hspi)3349 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
3350 {
3351 /* Prevent unused argument(s) compilation warning */
3352 UNUSED(hspi);
3353
3354 /* NOTE : This function should not be modified, when the callback is needed,
3355 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
3356 */
3357 }
3358
3359 /**
3360 * @brief Tx and Rx Half Transfer callback.
3361 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3362 * the configuration information for SPI module.
3363 * @retval None
3364 */
HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef * hspi)3365 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
3366 {
3367 /* Prevent unused argument(s) compilation warning */
3368 UNUSED(hspi);
3369
3370 /* NOTE : This function should not be modified, when the callback is needed,
3371 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
3372 */
3373 }
3374
3375 /**
3376 * @brief SPI error callback.
3377 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3378 * the configuration information for SPI module.
3379 * @retval None
3380 */
HAL_SPI_ErrorCallback(SPI_HandleTypeDef * hspi)3381 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
3382 {
3383 /* Prevent unused argument(s) compilation warning */
3384 UNUSED(hspi);
3385
3386 /* NOTE : This function should not be modified, when the callback is needed,
3387 the HAL_SPI_ErrorCallback should be implemented in the user file
3388 */
3389 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
3390 and user can use HAL_SPI_GetError() API to check the latest error occurred
3391 */
3392 }
3393
3394 /**
3395 * @brief SPI Abort Complete callback.
3396 * @param hspi SPI handle.
3397 * @retval None
3398 */
HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef * hspi)3399 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
3400 {
3401 /* Prevent unused argument(s) compilation warning */
3402 UNUSED(hspi);
3403
3404 /* NOTE : This function should not be modified, when the callback is needed,
3405 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
3406 */
3407 }
3408
3409 /**
3410 * @brief SPI Suspend callback.
3411 * @param hspi SPI handle.
3412 * @retval None
3413 */
HAL_SPI_SuspendCallback(SPI_HandleTypeDef * hspi)3414 __weak void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
3415 {
3416 /* Prevent unused argument(s) compilation warning */
3417 UNUSED(hspi);
3418
3419 /* NOTE : This function should not be modified, when the callback is needed,
3420 the HAL_SPI_SuspendCallback can be implemented in the user file.
3421 */
3422 }
3423
3424 /**
3425 * @}
3426 */
3427
3428 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
3429 * @brief SPI control functions
3430 *
3431 @verbatim
3432 ===============================================================================
3433 ##### Peripheral State and Errors functions #####
3434 ===============================================================================
3435 [..]
3436 This subsection provides a set of functions allowing to control the SPI.
3437 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
3438 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
3439 @endverbatim
3440 * @{
3441 */
3442
3443 /**
3444 * @brief Return the SPI handle state.
3445 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3446 * the configuration information for SPI module.
3447 * @retval SPI state
3448 */
HAL_SPI_GetState(const SPI_HandleTypeDef * hspi)3449 HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi)
3450 {
3451 /* Return SPI handle state */
3452 return hspi->State;
3453 }
3454
3455 /**
3456 * @brief Return the SPI error code.
3457 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3458 * the configuration information for SPI module.
3459 * @retval SPI error code in bitmap format
3460 */
HAL_SPI_GetError(const SPI_HandleTypeDef * hspi)3461 uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi)
3462 {
3463 /* Return SPI ErrorCode */
3464 return hspi->ErrorCode;
3465 }
3466
3467 /**
3468 * @}
3469 */
3470
3471 /**
3472 * @}
3473 */
3474
3475 /** @addtogroup SPI_Private_Functions
3476 * @brief Private functions
3477 * @{
3478 */
3479
3480 /**
3481 * @brief DMA SPI transmit process complete callback.
3482 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
3483 * the configuration information for the specified DMA module.
3484 * @retval None
3485 */
SPI_DMATransmitCplt(DMA_HandleTypeDef * hdma)3486 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
3487 {
3488 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3489
3490 if (hspi->State != HAL_SPI_STATE_ABORT)
3491 {
3492 if (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)
3493 {
3494 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3495 hspi->TxCpltCallback(hspi);
3496 #else
3497 HAL_SPI_TxCpltCallback(hspi);
3498 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3499 }
3500 else
3501 {
3502 /* Enable EOT interrupt */
3503 __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
3504 }
3505 }
3506 }
3507
3508 /**
3509 * @brief DMA SPI receive process complete callback.
3510 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
3511 * the configuration information for the specified DMA module.
3512 * @retval None
3513 */
SPI_DMAReceiveCplt(DMA_HandleTypeDef * hdma)3514 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
3515 {
3516 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3517
3518 if (hspi->State != HAL_SPI_STATE_ABORT)
3519 {
3520 if (hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR)
3521 {
3522 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3523 hspi->RxCpltCallback(hspi);
3524 #else
3525 HAL_SPI_RxCpltCallback(hspi);
3526 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3527 }
3528 else
3529 {
3530 /* Enable EOT interrupt */
3531 __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
3532 }
3533 }
3534 }
3535
3536 /**
3537 * @brief DMA SPI transmit receive process complete callback.
3538 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
3539 * the configuration information for the specified DMA module.
3540 * @retval None
3541 */
SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef * hdma)3542 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3543 {
3544 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3545
3546 if (hspi->State != HAL_SPI_STATE_ABORT)
3547 {
3548 if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) &&
3549 (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR))
3550 {
3551 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3552 hspi->TxRxCpltCallback(hspi);
3553 #else
3554 HAL_SPI_TxRxCpltCallback(hspi);
3555 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3556 }
3557 else
3558 {
3559 /* Enable EOT interrupt */
3560 __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
3561 }
3562 }
3563 }
3564
3565 /**
3566 * @brief DMA SPI half transmit process complete callback.
3567 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
3568 * the configuration information for the specified DMA module.
3569 * @retval None
3570 */
SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef * hdma)3571 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */
3572 {
3573 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)
3574 ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */
3575
3576 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3577 hspi->TxHalfCpltCallback(hspi);
3578 #else
3579 HAL_SPI_TxHalfCpltCallback(hspi);
3580 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3581 }
3582
3583 /**
3584 * @brief DMA SPI half receive process complete callback
3585 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
3586 * the configuration information for the specified DMA module.
3587 * @retval None
3588 */
SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef * hdma)3589 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */
3590 {
3591 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)
3592 ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */
3593
3594 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3595 hspi->RxHalfCpltCallback(hspi);
3596 #else
3597 HAL_SPI_RxHalfCpltCallback(hspi);
3598 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3599 }
3600
3601 /**
3602 * @brief DMA SPI half transmit receive process complete callback.
3603 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
3604 * the configuration information for the specified DMA module.
3605 * @retval None
3606 */
SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef * hdma)3607 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */
3608 {
3609 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)
3610 ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */
3611
3612 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3613 hspi->TxRxHalfCpltCallback(hspi);
3614 #else
3615 HAL_SPI_TxRxHalfCpltCallback(hspi);
3616 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3617 }
3618
3619 /**
3620 * @brief DMA SPI communication error callback.
3621 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
3622 * the configuration information for the specified DMA module.
3623 * @retval None
3624 */
SPI_DMAError(DMA_HandleTypeDef * hdma)3625 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3626 {
3627 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3628
3629 /* if DMA error is FIFO error ignore it */
3630 if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_NONE)
3631 {
3632 /* Call SPI standard close procedure */
3633 SPI_CloseTransfer(hspi);
3634
3635 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3636 hspi->State = HAL_SPI_STATE_READY;
3637 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3638 hspi->ErrorCallback(hspi);
3639 #else
3640 HAL_SPI_ErrorCallback(hspi);
3641 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3642 }
3643 }
3644
3645 /**
3646 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
3647 * (To be called at end of DMA Abort procedure following error occurrence).
3648 * @param hdma DMA handle.
3649 * @retval None
3650 */
SPI_DMAAbortOnError(DMA_HandleTypeDef * hdma)3651 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3652 {
3653 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3654 hspi->RxXferCount = (uint16_t) 0UL;
3655 hspi->TxXferCount = (uint16_t) 0UL;
3656
3657 /* Restore hspi->State to Ready */
3658 hspi->State = HAL_SPI_STATE_READY;
3659
3660 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3661 hspi->ErrorCallback(hspi);
3662 #else
3663 HAL_SPI_ErrorCallback(hspi);
3664 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3665 }
3666
3667 /**
3668 * @brief DMA SPI Tx communication abort callback, when initiated by user
3669 * (To be called at end of DMA Tx Abort procedure following user abort request).
3670 * @note When this callback is executed, User Abort complete call back is called only if no
3671 * Abort still ongoing for Rx DMA Handle.
3672 * @param hdma DMA handle.
3673 * @retval None
3674 */
SPI_DMATxAbortCallback(DMA_HandleTypeDef * hdma)3675 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3676 {
3677 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3678
3679 hspi->hdmatx->XferAbortCallback = NULL;
3680
3681 /* Check if an Abort process is still ongoing */
3682 if (hspi->hdmarx != NULL)
3683 {
3684 if (hspi->hdmarx->XferAbortCallback != NULL)
3685 {
3686 return;
3687 }
3688 }
3689
3690 /* Call the Abort procedure */
3691 SPI_AbortTransfer(hspi);
3692
3693 /* Restore hspi->State to Ready */
3694 hspi->State = HAL_SPI_STATE_READY;
3695
3696 /* Call user Abort complete callback */
3697 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3698 hspi->AbortCpltCallback(hspi);
3699 #else
3700 HAL_SPI_AbortCpltCallback(hspi);
3701 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3702 }
3703
3704 /**
3705 * @brief DMA SPI Rx communication abort callback, when initiated by user
3706 * (To be called at end of DMA Rx Abort procedure following user abort request).
3707 * @note When this callback is executed, User Abort complete call back is called only if no
3708 * Abort still ongoing for Tx DMA Handle.
3709 * @param hdma DMA handle.
3710 * @retval None
3711 */
SPI_DMARxAbortCallback(DMA_HandleTypeDef * hdma)3712 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3713 {
3714 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3715
3716 hspi->hdmarx->XferAbortCallback = NULL;
3717
3718 /* Check if an Abort process is still ongoing */
3719 if (hspi->hdmatx != NULL)
3720 {
3721 if (hspi->hdmatx->XferAbortCallback != NULL)
3722 {
3723 return;
3724 }
3725 }
3726
3727 /* Call the Abort procedure */
3728 SPI_AbortTransfer(hspi);
3729
3730 /* Restore hspi->State to Ready */
3731 hspi->State = HAL_SPI_STATE_READY;
3732
3733 /* Call user Abort complete callback */
3734 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
3735 hspi->AbortCpltCallback(hspi);
3736 #else
3737 HAL_SPI_AbortCpltCallback(hspi);
3738 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3739 }
3740
3741 /**
3742 * @brief Manage the receive 8-bit in Interrupt context.
3743 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3744 * the configuration information for SPI module.
3745 * @retval None
3746 */
SPI_RxISR_8BIT(SPI_HandleTypeDef * hspi)3747 static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi)
3748 {
3749 /* Receive data in 8 Bit mode */
3750 *((uint8_t *)hspi->pRxBuffPtr) = (*(__IO uint8_t *)&hspi->Instance->RXDR);
3751 hspi->pRxBuffPtr += sizeof(uint8_t);
3752 hspi->RxXferCount--;
3753
3754 /* Disable IT if no more data excepted */
3755 if (hspi->RxXferCount == 0UL)
3756 {
3757 /* Disable RXP interrupts */
3758 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
3759 }
3760 }
3761
3762
3763 /**
3764 * @brief Manage the 16-bit receive in Interrupt context.
3765 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3766 * the configuration information for SPI module.
3767 * @retval None
3768 */
SPI_RxISR_16BIT(SPI_HandleTypeDef * hspi)3769 static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi)
3770 {
3771 /* Receive data in 16 Bit mode */
3772 #if defined (__GNUC__)
3773 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
3774
3775 *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
3776 #else
3777 *((uint16_t *)hspi->pRxBuffPtr) = (*(__IO uint16_t *)&hspi->Instance->RXDR);
3778 #endif /* __GNUC__ */
3779 hspi->pRxBuffPtr += sizeof(uint16_t);
3780 hspi->RxXferCount--;
3781
3782 /* Disable IT if no more data excepted */
3783 if (hspi->RxXferCount == 0UL)
3784 {
3785 /* Disable RXP interrupts */
3786 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
3787 }
3788 }
3789
3790
3791 /**
3792 * @brief Manage the 32-bit receive in Interrupt context.
3793 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3794 * the configuration information for SPI module.
3795 * @retval None
3796 */
SPI_RxISR_32BIT(SPI_HandleTypeDef * hspi)3797 static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi)
3798 {
3799 /* Receive data in 32 Bit mode */
3800 *((uint32_t *)hspi->pRxBuffPtr) = (*(__IO uint32_t *)&hspi->Instance->RXDR);
3801 hspi->pRxBuffPtr += sizeof(uint32_t);
3802 hspi->RxXferCount--;
3803
3804 /* Disable IT if no more data excepted */
3805 if (hspi->RxXferCount == 0UL)
3806 {
3807 /* Disable RXP interrupts */
3808 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
3809 }
3810 }
3811
3812
3813 /**
3814 * @brief Handle the data 8-bit transmit in Interrupt mode.
3815 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3816 * the configuration information for SPI module.
3817 * @retval None
3818 */
SPI_TxISR_8BIT(SPI_HandleTypeDef * hspi)3819 static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi)
3820 {
3821 /* Transmit data in 8 Bit mode */
3822 *(__IO uint8_t *)&hspi->Instance->TXDR = *((const uint8_t *)hspi->pTxBuffPtr);
3823 hspi->pTxBuffPtr += sizeof(uint8_t);
3824 hspi->TxXferCount--;
3825
3826 /* Disable IT if no more data excepted */
3827 if (hspi->TxXferCount == 0UL)
3828 {
3829 /* Disable TXP interrupts */
3830 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
3831 }
3832 }
3833
3834 /**
3835 * @brief Handle the data 16-bit transmit in Interrupt mode.
3836 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3837 * the configuration information for SPI module.
3838 * @retval None
3839 */
SPI_TxISR_16BIT(SPI_HandleTypeDef * hspi)3840 static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi)
3841 {
3842 /* Transmit data in 16 Bit mode */
3843 #if defined (__GNUC__)
3844 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
3845
3846 *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
3847 #else
3848 *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
3849 #endif /* __GNUC__ */
3850 hspi->pTxBuffPtr += sizeof(uint16_t);
3851 hspi->TxXferCount--;
3852
3853 /* Disable IT if no more data excepted */
3854 if (hspi->TxXferCount == 0UL)
3855 {
3856 /* Disable TXP interrupts */
3857 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
3858 }
3859 }
3860
3861 /**
3862 * @brief Handle the data 32-bit transmit in Interrupt mode.
3863 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3864 * the configuration information for SPI module.
3865 * @retval None
3866 */
SPI_TxISR_32BIT(SPI_HandleTypeDef * hspi)3867 static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi)
3868 {
3869 /* Transmit data in 32 Bit mode */
3870 *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
3871 hspi->pTxBuffPtr += sizeof(uint32_t);
3872 hspi->TxXferCount--;
3873
3874 /* Disable IT if no more data excepted */
3875 if (hspi->TxXferCount == 0UL)
3876 {
3877 /* Disable TXP interrupts */
3878 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
3879 }
3880 }
3881
3882 /**
3883 * @brief Abort Transfer and clear flags.
3884 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3885 * the configuration information for SPI module.
3886 * @retval None
3887 */
SPI_AbortTransfer(SPI_HandleTypeDef * hspi)3888 static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi)
3889 {
3890 /* Disable SPI peripheral */
3891 __HAL_SPI_DISABLE(hspi);
3892
3893 /* Disable ITs */
3894 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \
3895 SPI_IT_FRE | SPI_IT_MODF));
3896
3897 /* Clear the Status flags in the SR register */
3898 __HAL_SPI_CLEAR_EOTFLAG(hspi);
3899 __HAL_SPI_CLEAR_TXTFFLAG(hspi);
3900
3901 /* Disable Tx DMA Request */
3902 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
3903
3904 /* Clear the Error flags in the SR register */
3905 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3906 __HAL_SPI_CLEAR_UDRFLAG(hspi);
3907 __HAL_SPI_CLEAR_FREFLAG(hspi);
3908 __HAL_SPI_CLEAR_MODFFLAG(hspi);
3909 __HAL_SPI_CLEAR_SUSPFLAG(hspi);
3910
3911 #if (USE_SPI_CRC != 0U)
3912 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3913 #endif /* USE_SPI_CRC */
3914
3915 hspi->TxXferCount = (uint16_t)0UL;
3916 hspi->RxXferCount = (uint16_t)0UL;
3917 }
3918
3919
3920 /**
3921 * @brief Close Transfer and clear flags.
3922 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3923 * the configuration information for SPI module.
3924 * @retval HAL_ERROR: if any error detected
3925 * HAL_OK: if nothing detected
3926 */
SPI_CloseTransfer(SPI_HandleTypeDef * hspi)3927 static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi)
3928 {
3929 uint32_t itflag = hspi->Instance->SR;
3930
3931 __HAL_SPI_CLEAR_EOTFLAG(hspi);
3932 __HAL_SPI_CLEAR_TXTFFLAG(hspi);
3933
3934 /* Disable SPI peripheral */
3935 __HAL_SPI_DISABLE(hspi);
3936
3937 /* Disable ITs */
3938 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \
3939 SPI_IT_FRE | SPI_IT_MODF));
3940
3941 /* Disable Tx DMA Request */
3942 CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
3943
3944 /* Report UnderRun error for non RX Only communication */
3945 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
3946 {
3947 if ((itflag & SPI_FLAG_UDR) != 0UL)
3948 {
3949 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
3950 __HAL_SPI_CLEAR_UDRFLAG(hspi);
3951 }
3952 }
3953
3954 /* Report OverRun error for non TX Only communication */
3955 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
3956 {
3957 if ((itflag & SPI_FLAG_OVR) != 0UL)
3958 {
3959 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
3960 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3961 }
3962
3963 #if (USE_SPI_CRC != 0UL)
3964 /* Check if CRC error occurred */
3965 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3966 {
3967 if ((itflag & SPI_FLAG_CRCERR) != 0UL)
3968 {
3969 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3970 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3971 }
3972 }
3973 #endif /* USE_SPI_CRC */
3974 }
3975
3976 /* SPI Mode Fault error interrupt occurred -------------------------------*/
3977 if ((itflag & SPI_FLAG_MODF) != 0UL)
3978 {
3979 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
3980 __HAL_SPI_CLEAR_MODFFLAG(hspi);
3981 }
3982
3983 /* SPI Frame error interrupt occurred ------------------------------------*/
3984 if ((itflag & SPI_FLAG_FRE) != 0UL)
3985 {
3986 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
3987 __HAL_SPI_CLEAR_FREFLAG(hspi);
3988 }
3989
3990 hspi->TxXferCount = (uint16_t)0UL;
3991 hspi->RxXferCount = (uint16_t)0UL;
3992 }
3993
3994 /**
3995 * @brief Handle SPI Communication Timeout.
3996 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
3997 * the configuration information for SPI module.
3998 * @param Flag: SPI flag to check
3999 * @param Status: flag state to check
4000 * @param Timeout: Timeout duration
4001 * @param Tickstart: Tick start value
4002 * @retval HAL status
4003 */
SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef * hspi,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)4004 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status,
4005 uint32_t Timeout, uint32_t Tickstart)
4006 {
4007 /* Wait until flag is set */
4008 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status)
4009 {
4010 /* Check for the Timeout */
4011 if ((((HAL_GetTick() - Tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
4012 {
4013 return HAL_TIMEOUT;
4014 }
4015 }
4016 return HAL_OK;
4017 }
4018
4019 /**
4020 * @brief Compute configured packet size from fifo perspective.
4021 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
4022 * the configuration information for SPI module.
4023 * @retval Packet size occupied in the fifo
4024 */
SPI_GetPacketSize(const SPI_HandleTypeDef * hspi)4025 static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi)
4026 {
4027 uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL;
4028 uint32_t data_size = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) + 1UL;
4029
4030 /* Convert data size to Byte */
4031 data_size = (data_size + 7UL) / 8UL;
4032
4033 return data_size * fifo_threashold;
4034 }
4035
4036 /**
4037 * @}
4038 */
4039
4040 #endif /* HAL_SPI_MODULE_ENABLED */
4041
4042 /**
4043 * @}
4044 */
4045
4046 /**
4047 * @}
4048 */
4049
