1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extended peripheral:
8 * + Extended Peripheral Control functions
9 * + Extended Clock management functions
10 * + Extended Clock Recovery System Control functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2021 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 */
24
25 /* Includes ------------------------------------------------------------------*/
26 #include "stm32u5xx_hal.h"
27
28 /** @addtogroup STM32U5xx_HAL_Driver
29 * @{
30 */
31
32 /** @defgroup RCCEx RCCEx
33 * @brief RCC Extended HAL module driver
34 * @{
35 */
36
37 #ifdef HAL_RCC_MODULE_ENABLED
38
39 /* Private typedef -----------------------------------------------------------*/
40 /* Private defines -----------------------------------------------------------*/
41 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
42 * @{
43 */
44 #define PLL1_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
45 #define PLL2_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
46 #define PLL3_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
47
48 /* Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. */
49 #if defined (STM32U585xx) || defined (STM32U575xx)
50 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM23 /*!< External interrupt line 23 connected to the LSE CSS interrupt Line */
51 #else
52 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM24 /*!< External interrupt line 24 connected to the LSE CSS interrupt Line */
53 #endif /* STM32U585xx || STM32U575xx */
54
55 /* Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. */
56 #define RCC_EXTI_LINE_MSIPLLUNLCK EXTI_IMR1_IM23 /*!< External interrupt line 23 connected to the MSI PLL UNLOCK interrupt Line */
57
58 /**
59 * @}
60 */
61
62 /* Private macros ------------------------------------------------------------*/
63 /** @addtogroup RCCEx_Private_Macros
64 * @{
65 */
66
67 #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U))
68
69 #define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U))
70
71 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
72 ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
73
74 #define IS_RCC_MSIPLLMODE_SELECT(__SOURCE__) (((__SOURCE__) == RCC_MSISPLL_MODE_SEL) || \
75 ((__SOURCE__) == RCC_MSIKPLL_MODE_SEL))
76
77 #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \
78 (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u))
79
80 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
81 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
82 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
83 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \
84 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE))
85
86 #if defined(USART2)
87 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
88 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
89 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
90 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \
91 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE))
92 #endif /* USART2 */
93
94 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
95 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
96 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
97 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \
98 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE))
99
100 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
101 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
102 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
103 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI) || \
104 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE))
105
106 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
107 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
108 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
109 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI) || \
110 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE))
111
112 #if defined(USART6)
113 #define IS_RCC_USART6CLKSOURCE(__SOURCE__) \
114 (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK1) || \
115 ((__SOURCE__) == RCC_USART6CLKSOURCE_SYSCLK) || \
116 ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI) || \
117 ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE))
118 #endif /* USART6 */
119
120 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
121 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \
122 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
123 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \
124 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
125 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_MSIK))
126
127 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
128 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
129 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
130 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)|| \
131 ((__SOURCE__) == RCC_I2C1CLKSOURCE_MSIK))
132
133 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
134 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
135 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
136 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)|| \
137 ((__SOURCE__) == RCC_I2C2CLKSOURCE_MSIK))
138
139 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
140 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK3) || \
141 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK ) || \
142 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI ) || \
143 ((__SOURCE__) == RCC_I2C3CLKSOURCE_MSIK))
144
145 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
146 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
147 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
148 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)|| \
149 ((__SOURCE__) == RCC_I2C4CLKSOURCE_MSIK))
150
151 #if defined(I2C5)
152 #define IS_RCC_I2C5CLKSOURCE(__SOURCE__) \
153 (((__SOURCE__) == RCC_I2C5CLKSOURCE_PCLK1) || \
154 ((__SOURCE__) == RCC_I2C5CLKSOURCE_SYSCLK)|| \
155 ((__SOURCE__) == RCC_I2C5CLKSOURCE_HSI)|| \
156 ((__SOURCE__) == RCC_I2C5CLKSOURCE_MSIK))
157 #endif /* I2C5 */
158
159 #if defined(I2C6)
160 #define IS_RCC_I2C6CLKSOURCE(__SOURCE__) \
161 (((__SOURCE__) == RCC_I2C6CLKSOURCE_PCLK1) || \
162 ((__SOURCE__) == RCC_I2C6CLKSOURCE_SYSCLK)|| \
163 ((__SOURCE__) == RCC_I2C6CLKSOURCE_HSI)|| \
164 ((__SOURCE__) == RCC_I2C6CLKSOURCE_MSIK))
165 #endif /* I2C6 */
166
167 #define IS_RCC_SAI1CLK(__SOURCE__) \
168 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
169 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
170 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1) || \
171 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \
172 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
173
174 #if defined(SAI2)
175 #define IS_RCC_SAI2CLK(__SOURCE__) \
176 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
177 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
178 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1) || \
179 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \
180 ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI))
181 #endif /* SAI2 */
182
183 #define IS_RCC_LPTIM1CLK(__SOURCE__) \
184 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_MSIK) || \
185 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
186 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
187 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
188
189 #define IS_RCC_LPTIM2CLK(__SOURCE__) \
190 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
191 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
192 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
193 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
194
195 #define IS_RCC_LPTIM34CLK(__SOURCE__) \
196 (((__SOURCE__) == RCC_LPTIM34CLKSOURCE_MSIK) || \
197 ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_LSI) || \
198 ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_HSI) || \
199 ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_LSE))
200
201 #define IS_RCC_FDCAN1CLK(__SOURCE__) \
202 (((__SOURCE__) == RCC_FDCAN1CLKSOURCE_HSE) || \
203 ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PLL1) || \
204 ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PLL2))
205
206 #define IS_RCC_SDMMCCLKSOURCE(__SOURCE__) \
207 (((__SOURCE__) == RCC_SDMMCCLKSOURCE_CLK48) || \
208 ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL1))
209
210 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
211 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
212 ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48_DIV2) || \
213 ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI))
214
215 #if defined(SAES)
216 #define IS_RCC_SAESCLKSOURCE(__SOURCE__) \
217 (((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI) || \
218 ((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI_DIV2))
219 #endif /* SAES */
220
221 #define IS_RCC_ADCDACCLKSOURCE(__SOURCE__) \
222 (((__SOURCE__) == RCC_ADCDACCLKSOURCE_HCLK) || \
223 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_SYSCLK) || \
224 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_PLL2) || \
225 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSE) || \
226 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSI) || \
227 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_MSIK))
228
229 #define IS_RCC_MDF1CLKSOURCE(__SOURCE__) \
230 (((__SOURCE__) == RCC_MDF1CLKSOURCE_HCLK) || \
231 ((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL1) || \
232 ((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL3) || \
233 ((__SOURCE__) == RCC_MDF1CLKSOURCE_PIN) || \
234 ((__SOURCE__) == RCC_MDF1CLKSOURCE_MSIK))
235
236 #define IS_RCC_ADF1CLKSOURCE(__SOURCE__) \
237 (((__SOURCE__) == RCC_ADF1CLKSOURCE_HCLK) || \
238 ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL1) || \
239 ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL3) || \
240 ((__SOURCE__) == RCC_ADF1CLKSOURCE_PIN) || \
241 ((__SOURCE__) == RCC_ADF1CLKSOURCE_MSIK))
242
243 #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \
244 (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \
245 ((__SOURCE__) == RCC_OSPICLKSOURCE_MSIK) || \
246 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL1) ||\
247 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2))
248
249 #if defined(HSPI1)
250 #define IS_RCC_HSPICLKSOURCE(__SOURCE__) \
251 (((__SOURCE__) == RCC_HSPICLKSOURCE_SYSCLK) || \
252 ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL1) || \
253 ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL2) || \
254 ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL3))
255 #endif /* HSPI1 */
256
257 #define IS_RCC_ICLKCLKSOURCE(__SOURCE__)\
258 (((__SOURCE__) == RCC_ICLK_CLKSOURCE_HSI48)|| \
259 ((__SOURCE__) == RCC_ICLK_CLKSOURCE_PLL2) || \
260 ((__SOURCE__) == RCC_ICLK_CLKSOURCE_PLL1) || \
261 ((__SOURCE__) == RCC_ICLK_CLKSOURCE_MSIK))
262
263 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \
264 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PCLK2) || \
265 ((__SOURCE__) == RCC_SPI1CLKSOURCE_SYSCLK) || \
266 ((__SOURCE__) == RCC_SPI1CLKSOURCE_HSI)|| \
267 ((__SOURCE__) == RCC_SPI1CLKSOURCE_MSIK))
268
269 #define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \
270 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PCLK1) || \
271 ((__SOURCE__) == RCC_SPI2CLKSOURCE_SYSCLK) || \
272 ((__SOURCE__) == RCC_SPI2CLKSOURCE_HSI)|| \
273 ((__SOURCE__) == RCC_SPI2CLKSOURCE_MSIK))
274
275 #define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \
276 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PCLK3) || \
277 ((__SOURCE__) == RCC_SPI3CLKSOURCE_SYSCLK) || \
278 ((__SOURCE__) == RCC_SPI3CLKSOURCE_HSI)|| \
279 ((__SOURCE__) == RCC_SPI3CLKSOURCE_MSIK))
280
281 #define IS_RCC_DAC1CLKSOURCE(__SOURCE__) \
282 (((__SOURCE__) == RCC_DAC1CLKSOURCE_LSE) || \
283 ((__SOURCE__) == RCC_DAC1CLKSOURCE_LSI))
284
285 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
286 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
287 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
288 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
289
290 #if defined(LTDC)
291
292 #define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \
293 (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL3) || \
294 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL2))
295
296 #endif /* LTDC */
297
298 #if defined(DSI)
299
300 #define IS_RCC_DSICLKSOURCE(__SOURCE__) \
301 (((__SOURCE__) == RCC_DSICLKSOURCE_PLL3) || \
302 ((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY))
303
304 #endif /* DSI */
305
306 #if defined(USB_OTG_HS)
307
308 #define IS_RCC_USBPHYCLKSOURCE(__SOURCE__) \
309 (((__SOURCE__) == RCC_USBPHYCLKSOURCE_HSE) || \
310 ((__SOURCE__) == RCC_USBPHYCLKSOURCE_HSE_DIV2) || \
311 ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1) || \
312 ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1_DIV2))
313
314 #endif /* USB_OTG_HS */
315
316 #if defined(CRS)
317
318 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
319 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
320 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
321
322 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
323 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
324 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
325 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
326
327 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
328 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
329
330 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
331
332 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
333
334 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU))
335
336 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
337 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
338
339 #endif /* CRS */
340
341 /**
342 * @}
343 */
344
345 /* Private variables ---------------------------------------------------------*/
346 /* Private function prototypes -----------------------------------------------*/
347 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
348 * @{
349 */
350 static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource);
351 static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *Pll2);
352 static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *Pll3);
353 /**
354 * @}
355 */
356
357 /* Exported functions --------------------------------------------------------*/
358
359 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
360 * @{
361 */
362
363 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
364 * @brief Extended Peripheral Control functions
365 *
366 @verbatim
367 ===============================================================================
368 ##### Extended Peripheral Control functions #####
369 ===============================================================================
370 [..]
371 This subsection provides a set of functions allowing to control the RCC Clocks
372 frequencies.
373 [..]
374 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
375 select the RTC clock source; in this case the Backup domain will be reset in
376 order to modify the RTC Clock source, as consequence RTC registers (including
377 the backup registers) are set to their reset values.
378
379 @endverbatim
380 * @{
381 */
382 /**
383 * @brief Initialize the RCC extended peripherals clocks according to the specified
384 * parameters in the RCC_PeriphCLKInitTypeDef.
385 * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
386 * contains a field PeriphClockSelection which can be a combination of the following values:
387 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
388 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
389 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
390 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
391 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
392 * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock
393 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
394 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
395 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
396 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
397 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock
398 * @arg @ref RCC_PERIPHCLK_I2C5 I2C5 peripheral clock
399 * @arg @ref RCC_PERIPHCLK_I2C6 I2C6 peripheral clock
400 * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock
401 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
402 * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock (*)
403 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
404 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock
405 * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1 ADC2 ADC4 DAC1 peripheral clock
406 * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock
407 * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock
408 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
409 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
410 * @arg @ref RCC_PERIPHCLK_ICLK ICLK peripheral clock
411 * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC1 peripheral clock
412 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
413 * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
414 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
415 * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock
416 * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock
417 * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock
418 * @arg @ref RCC_PERIPHCLK_HSPI HSPI peripheral clock
419 * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock
420 * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock
421 * @arg @ref RCC_PERIPHCLK_USBPHY USBPHY peripheral clock
422 *
423 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
424 * the RTC clock source: in this case the access to Backup domain is enabled.
425 *
426 * @retval HAL status
427 *
428 * (*) value not defined in all devices.
429 */
HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef * pPeriphClkInit)430 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
431 {
432 uint32_t tmpregister;
433 uint32_t tickstart;
434 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
435 HAL_StatusTypeDef status = HAL_OK; /* Final status */
436
437 /* Check the parameters */
438 assert_param(IS_RCC_PERIPHCLOCK(pPeriphClkInit->PeriphClockSelection));
439
440 /*-------------------------- USART1 clock source configuration -------------------*/
441 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
442 {
443 /* Check the parameters */
444 assert_param(IS_RCC_USART1CLKSOURCE(pPeriphClkInit->Usart1ClockSelection));
445
446 /* Configure the USART1 clock source */
447 __HAL_RCC_USART1_CONFIG(pPeriphClkInit->Usart1ClockSelection);
448 }
449
450 #if defined(USART2)
451 /*-------------------------- USART2 clock source configuration -------------------*/
452 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
453 {
454 /* Check the parameters */
455 assert_param(IS_RCC_USART2CLKSOURCE(pPeriphClkInit->Usart2ClockSelection));
456
457 /* Configure the USART2 clock source */
458 __HAL_RCC_USART2_CONFIG(pPeriphClkInit->Usart2ClockSelection);
459 }
460 #endif /* USART2 */
461
462 /*-------------------------- USART3 clock source configuration -------------------*/
463 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
464 {
465 /* Check the parameters */
466 assert_param(IS_RCC_USART3CLKSOURCE(pPeriphClkInit->Usart3ClockSelection));
467
468 /* Configure the USART3 clock source */
469 __HAL_RCC_USART3_CONFIG(pPeriphClkInit->Usart3ClockSelection);
470 }
471
472 /*-------------------------- UART4 clock source configuration --------------------*/
473 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
474 {
475 /* Check the parameters */
476 assert_param(IS_RCC_UART4CLKSOURCE(pPeriphClkInit->Uart4ClockSelection));
477
478 /* Configure the UART4 clock source */
479 __HAL_RCC_UART4_CONFIG(pPeriphClkInit->Uart4ClockSelection);
480 }
481
482 /*-------------------------- UART5 clock source configuration --------------------*/
483 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
484 {
485 /* Check the parameters */
486 assert_param(IS_RCC_UART5CLKSOURCE(pPeriphClkInit->Uart5ClockSelection));
487
488 /* Configure the UART5 clock source */
489 __HAL_RCC_UART5_CONFIG(pPeriphClkInit->Uart5ClockSelection);
490 }
491 #if defined(USART6)
492 /*-------------------------- USART6 clock source configuration -------------------*/
493 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
494 {
495 /* Check the parameters */
496 assert_param(IS_RCC_USART6CLKSOURCE(pPeriphClkInit->Usart6ClockSelection));
497
498 /* Configure the USART6 clock source */
499 __HAL_RCC_USART6_CONFIG(pPeriphClkInit->Usart6ClockSelection);
500 }
501 #endif /* USART6 */
502
503 /*-------------------------- LPUART1 clock source configuration ------------------*/
504 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
505 {
506 /* Check the parameters */
507 assert_param(IS_RCC_LPUART1CLKSOURCE(pPeriphClkInit->Lpuart1ClockSelection));
508
509 /* Configure the LPUART1 clock source */
510 __HAL_RCC_LPUART1_CONFIG(pPeriphClkInit->Lpuart1ClockSelection);
511 }
512
513 /*-------------------------- I2C1 clock source configuration ---------------------*/
514 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
515 {
516 /* Check the parameters */
517 assert_param(IS_RCC_I2C1CLKSOURCE(pPeriphClkInit->I2c1ClockSelection));
518
519 /* Configure the I2C1 clock source */
520 __HAL_RCC_I2C1_CONFIG(pPeriphClkInit->I2c1ClockSelection);
521 }
522
523 /*-------------------------- I2C2 clock source configuration ---------------------*/
524 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
525 {
526 /* Check the parameters */
527 assert_param(IS_RCC_I2C2CLKSOURCE(pPeriphClkInit->I2c2ClockSelection));
528
529 /* Configure the I2C2 clock source */
530 __HAL_RCC_I2C2_CONFIG(pPeriphClkInit->I2c2ClockSelection);
531 }
532
533 /*-------------------------- I2C3 clock source configuration ---------------------*/
534 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
535 {
536 /* Check the parameters */
537 assert_param(IS_RCC_I2C3CLKSOURCE(pPeriphClkInit->I2c3ClockSelection));
538
539 /* Configure the I2C3 clock source */
540 __HAL_RCC_I2C3_CONFIG(pPeriphClkInit->I2c3ClockSelection);
541 }
542
543 /*-------------------------- I2C4 clock source configuration ---------------------*/
544 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
545 {
546 /* Check the parameters */
547 assert_param(IS_RCC_I2C4CLKSOURCE(pPeriphClkInit->I2c4ClockSelection));
548
549 /* Configure the I2C4 clock source */
550 __HAL_RCC_I2C4_CONFIG(pPeriphClkInit->I2c4ClockSelection);
551 }
552
553 #if defined(I2C5)
554 /*-------------------------- I2C5 clock source configuration ---------------------*/
555 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C5) == RCC_PERIPHCLK_I2C5)
556 {
557 /* Check the parameters */
558 assert_param(IS_RCC_I2C5CLKSOURCE(pPeriphClkInit->I2c5ClockSelection));
559
560 /* Configure the I2C5 clock source */
561 __HAL_RCC_I2C5_CONFIG(pPeriphClkInit->I2c5ClockSelection);
562 }
563 #endif /* I2C5 */
564
565 #if defined(I2C6)
566 /*-------------------------- I2C6 clock source configuration ---------------------*/
567 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C6) == RCC_PERIPHCLK_I2C6)
568 {
569 /* Check the parameters */
570 assert_param(IS_RCC_I2C6CLKSOURCE(pPeriphClkInit->I2c6ClockSelection));
571
572 /* Configure the I2C6 clock source */
573 __HAL_RCC_I2C6_CONFIG(pPeriphClkInit->I2c6ClockSelection);
574 }
575 #endif /* I2C6 */
576
577 /*-------------------------- LPTIM1 clock source configuration -------------------*/
578 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
579 {
580 assert_param(IS_RCC_LPTIM1CLK(pPeriphClkInit->Lptim1ClockSelection));
581 __HAL_RCC_LPTIM1_CONFIG(pPeriphClkInit->Lptim1ClockSelection);
582 }
583
584 /*-------------------------- LPTIM2 clock source configuration -------------------*/
585 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
586 {
587 assert_param(IS_RCC_LPTIM2CLK(pPeriphClkInit->Lptim2ClockSelection));
588 __HAL_RCC_LPTIM2_CONFIG(pPeriphClkInit->Lptim2ClockSelection);
589 }
590
591 /*-------------------------- LPTIM34 clock source configuration -------------------*/
592 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM34) == (RCC_PERIPHCLK_LPTIM34))
593 {
594 assert_param(IS_RCC_LPTIM34CLK(pPeriphClkInit->Lptim34ClockSelection));
595 __HAL_RCC_LPTIM34_CONFIG(pPeriphClkInit->Lptim34ClockSelection);
596 }
597
598 /*-------------------------- SAI1 clock source configuration ---------------------*/
599 if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
600 {
601 /* Check the parameters */
602 assert_param(IS_RCC_SAI1CLK(pPeriphClkInit->Sai1ClockSelection));
603
604 switch (pPeriphClkInit->Sai1ClockSelection)
605 {
606 case RCC_SAI1CLKSOURCE_PLL1: /* PLL is used as clock source for SAI1*/
607 /* Enable SAI Clock output generated from System PLL */
608 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
609 /* SAI1 clock source config set later after clock selection check */
610 break;
611
612 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
613 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
614 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
615 /* SAI1 clock source config set later after clock selection check */
616 break;
617
618 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/
619 /* PLL3 P input clock, parameters M, N & P configuration clock output (PLL3ClockOut) */
620 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
621 /* SAI1 clock source config set later after clock selection check */
622 break;
623
624 case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/
625 /* SAI1 clock source configuration done later after clock selection check */
626 break;
627
628 case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/
629 /* SAI1 clock source config set later after clock selection check */
630 break;
631
632 default:
633 ret = HAL_ERROR;
634 break;
635 }
636
637 if (ret == HAL_OK)
638 {
639 /* Set the source of SAI1 clock*/
640 __HAL_RCC_SAI1_CONFIG(pPeriphClkInit->Sai1ClockSelection);
641 }
642 else
643 {
644 /* set overall return value */
645 status = ret;
646 }
647 }
648
649 #if defined(SAI2)
650 /*-------------------------- SAI2 clock source configuration ---------------------*/
651 if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
652 {
653 /* Check the parameters */
654 assert_param(IS_RCC_SAI2CLK(pPeriphClkInit->Sai2ClockSelection));
655
656 switch (pPeriphClkInit->Sai2ClockSelection)
657 {
658 case RCC_SAI2CLKSOURCE_PLL1: /* PLL is used as clock source for SAI2*/
659 /* Enable SAI Clock output generated from System PLL */
660 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
661 /* SAI2 clock source config set later after clock selection check */
662 break;
663
664 case RCC_SAI2CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
665 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
666 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
667 /* SAI2 clock source config set later after clock selection check */
668 break;
669
670 case RCC_SAI2CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
671 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
672 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
673 /* SAI2 clock source config set later after clock selection check */
674 break;
675
676 case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/
677 /* SAI2 clock source configuration done later after clock selection check */
678 break;
679 case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/
680 /* SAI2 clock source config set later after clock selection check */
681 break;
682
683 default:
684 ret = HAL_ERROR;
685 break;
686 }
687
688 if (ret == HAL_OK)
689 {
690 /* Set the source of SAI2 clock*/
691 __HAL_RCC_SAI2_CONFIG(pPeriphClkInit->Sai2ClockSelection);
692 }
693 else
694 {
695 /* set overall return value */
696 status = ret;
697 }
698 }
699 #endif /* SAI2 */
700
701 /*-------------------------- ADCDAC clock source configuration ----------------------*/
702 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADCDAC) == RCC_PERIPHCLK_ADCDAC)
703 {
704 /* Check the parameters */
705 assert_param(IS_RCC_ADCDACCLKSOURCE(pPeriphClkInit->AdcDacClockSelection));
706
707 switch (pPeriphClkInit->AdcDacClockSelection)
708 {
709 case RCC_ADCDACCLKSOURCE_PLL2:
710 /* PLL2 input clock, parameters M, N,P, & R configuration and clock output (PLL2ClockOut) */
711 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
712 break;
713
714 case RCC_ADCDACCLKSOURCE_SYSCLK:
715 case RCC_ADCDACCLKSOURCE_HCLK:
716 case RCC_ADCDACCLKSOURCE_HSE:
717 case RCC_ADCDACCLKSOURCE_HSI:
718 case RCC_ADCDACCLKSOURCE_MSIK:
719 break;
720 default:
721 ret = HAL_ERROR;
722 break;
723 }
724
725 if (ret == HAL_OK)
726 {
727 /* Configure the ADC1 interface clock source */
728 __HAL_RCC_ADCDAC_CONFIG(pPeriphClkInit->AdcDacClockSelection);
729 }
730 else
731 {
732 /* set overall return value */
733 status = ret;
734 }
735 }
736
737 /*-------------------------- MDF1 clock source configuration -------------------*/
738 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_MDF1) == RCC_PERIPHCLK_MDF1)
739 {
740 /* Check the parameters */
741 assert_param(IS_RCC_MDF1CLKSOURCE(pPeriphClkInit->Mdf1ClockSelection));
742
743 switch (pPeriphClkInit->Mdf1ClockSelection)
744 {
745 case RCC_MDF1CLKSOURCE_PLL1:
746 /* Enable PLL1 Clock output generated from System PLL */
747 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
748 break;
749 case RCC_MDF1CLKSOURCE_PLL3:
750 /* PLL3 Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */
751 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
752 break;
753 case RCC_MDF1CLKSOURCE_HCLK:
754 break;
755 case RCC_MDF1CLKSOURCE_PIN:
756 break;
757 case RCC_MDF1CLKSOURCE_MSIK:
758 break;
759 default:
760 ret = HAL_ERROR;
761 break;
762 }
763 if (ret == HAL_OK)
764 {
765 /* Configure the MDF1 interface clock source */
766 __HAL_RCC_MDF1_CONFIG(pPeriphClkInit->Mdf1ClockSelection);
767 }
768 else
769 {
770 /* set overall return value */
771 status = ret;
772 }
773 }
774
775 /*-------------------------- ADF1 clock source configuration -------------------*/
776 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1)
777 {
778 /* Check the parameters */
779 assert_param(IS_RCC_ADF1CLKSOURCE(pPeriphClkInit->Adf1ClockSelection));
780 switch (pPeriphClkInit->Adf1ClockSelection)
781 {
782 case RCC_ADF1CLKSOURCE_PLL1:
783 /* Enable PLL1 Clock output generated from System PLL */
784 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
785 break;
786 case RCC_ADF1CLKSOURCE_PLL3:
787 /* PLL3 Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */
788 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
789 break;
790 case RCC_ADF1CLKSOURCE_HCLK:
791 break;
792 case RCC_ADF1CLKSOURCE_PIN:
793 break;
794 case RCC_ADF1CLKSOURCE_MSIK:
795 break;
796 default:
797 ret = HAL_ERROR;
798 break;
799 }
800 if (ret == HAL_OK)
801 {
802 /* Configure the ADF1 interface clock source */
803 __HAL_RCC_ADF1_CONFIG(pPeriphClkInit->Adf1ClockSelection);
804 }
805 else
806 {
807 /* set overall return value */
808 status = ret;
809 }
810 }
811
812 /*-------------------------- RTC clock source configuration ----------------------*/
813 if ((pPeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
814 {
815 FlagStatus pwrclkchanged = RESET;
816 /* Check for RTC Parameters used to output RTCCLK */
817 assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection));
818 /* Enable Power Clock */
819 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
820 {
821 __HAL_RCC_PWR_CLK_ENABLE();
822 pwrclkchanged = SET;
823 }
824 /* Enable write access to Backup domain */
825 SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
826
827 /* Wait for Backup domain Write protection disable */
828 tickstart = HAL_GetTick();
829
830 while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
831 {
832 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
833 {
834 ret = HAL_TIMEOUT;
835 break;
836 }
837 }
838
839 if (ret == HAL_OK)
840 {
841 /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
842 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
843
844 if ((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != pPeriphClkInit->RTCClockSelection))
845 {
846 /* Store the content of BDCR register before the reset of Backup Domain */
847 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
848 /* RTC Clock selection can be changed only if the Backup Domain is reset */
849 __HAL_RCC_BACKUPRESET_FORCE();
850 __HAL_RCC_BACKUPRESET_RELEASE();
851 /* Restore the Content of BDCR register */
852 RCC->BDCR = tmpregister;
853 }
854
855 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
856 if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
857 {
858 /* Get Start Tick*/
859 tickstart = HAL_GetTick();
860
861 /* Wait till LSE is ready */
862 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
863 {
864 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
865 {
866 ret = HAL_TIMEOUT;
867 break;
868 }
869 }
870 }
871
872 if (ret == HAL_OK)
873 {
874 /* Apply new RTC clock source selection */
875 __HAL_RCC_RTC_CONFIG(pPeriphClkInit->RTCClockSelection);
876 }
877 else
878 {
879 /* set overall return value */
880 status = ret;
881 }
882 }
883 else
884 {
885 /* set overall return value */
886 status = ret;
887 }
888
889 /* Restore clock configuration if changed */
890 if (pwrclkchanged == SET)
891 {
892 __HAL_RCC_PWR_CLK_DISABLE();
893 }
894 }
895
896 /*-------------------------------------- ICLK Configuration -----------------------------------*/
897 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ICLK) == RCC_PERIPHCLK_ICLK)
898 {
899 /* Check the parameters */
900 assert_param(IS_RCC_ICLKCLKSOURCE(pPeriphClkInit->IclkClockSelection));
901
902 switch (pPeriphClkInit->IclkClockSelection)
903 {
904 case RCC_ICLK_CLKSOURCE_PLL2:
905 /* PLL2 input clock, parameters M, N,P,Q & R configuration and clock output (PLL2ClockOut) */
906 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
907 break;
908 case RCC_ICLK_CLKSOURCE_PLL1:
909 /* Enable ICLK Clock output generated from System PLL */
910 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
911 break;
912 case RCC_ICLK_CLKSOURCE_HSI48:
913 break;
914 case RCC_ICLK_CLKSOURCE_MSIK:
915 break;
916 default:
917 ret = HAL_ERROR;
918 break;
919 }
920 if (ret == HAL_OK)
921 {
922 /* Configure the CLK48 source */
923 __HAL_RCC_CLK48_CONFIG(pPeriphClkInit->IclkClockSelection);
924 }
925 else
926 {
927 /* set overall return value */
928 status = ret;
929 }
930 }
931
932 /*------------------------------ RNG Configuration -------------------------*/
933 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
934 {
935
936 /* Check the parameters */
937 assert_param(IS_RCC_RNGCLKSOURCE(pPeriphClkInit->RngClockSelection));
938
939 switch (pPeriphClkInit->RngClockSelection)
940 {
941 case RCC_RNGCLKSOURCE_HSI48_DIV2: /* HSI48/2 is used as clock source for RNG*/
942 /* RNG clock source configuration done later after clock selection check */
943 break;
944 case RCC_RNGCLKSOURCE_HSI: /* HSI is used as clock source for RNG*/
945 /* RNG clock source configuration done later after clock selection check */
946 break;
947 case RCC_RNGCLKSOURCE_HSI48:
948 /* HSI48 oscillator is used as source of RNG clock */
949 /* RNG clock source configuration done later after clock selection check */
950 break;
951 default:
952 ret = HAL_ERROR;
953 break;
954 }
955 if (ret == HAL_OK)
956 {
957 /* Set the source of RNG clock*/
958 __HAL_RCC_RNG_CONFIG(pPeriphClkInit->RngClockSelection);
959 }
960 else
961 {
962 /* set overall return value */
963 status = ret;
964 }
965 }
966
967 #if defined(SAES)
968 /*-------------------------- SAES clock source configuration ----------------*/
969 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAES) == RCC_PERIPHCLK_SAES)
970 {
971 /* Check the parameters */
972 assert_param(IS_RCC_SAESCLKSOURCE(pPeriphClkInit->SaesClockSelection));
973
974 /* Configure the SAES clock source */
975 __HAL_RCC_SAES_CONFIG(pPeriphClkInit->SaesClockSelection);
976 }
977 #endif /* SAES */
978
979 /*-------------------------- SDMMC1/2 clock source configuration -------------------*/
980 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == (RCC_PERIPHCLK_SDMMC))
981 {
982 /* Check the parameters */
983 assert_param(IS_RCC_SDMMCCLKSOURCE(pPeriphClkInit->SdmmcClockSelection));
984
985 if (pPeriphClkInit->SdmmcClockSelection == RCC_SDMMCCLKSOURCE_PLL1)
986 {
987 /* Enable PLL1 P CLK output */
988 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
989 }
990
991 /* Configure the SDMMC1/2 clock source */
992 __HAL_RCC_SDMMC_CONFIG(pPeriphClkInit->SdmmcClockSelection);
993 }
994
995 /*-------------------------- SPI1 clock source configuration ----------------*/
996 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1)
997 {
998 /* Check the parameters */
999 assert_param(IS_RCC_SPI1CLKSOURCE(pPeriphClkInit->Spi1ClockSelection));
1000
1001 /* Configure the SPI1 clock source */
1002 __HAL_RCC_SPI1_CONFIG(pPeriphClkInit->Spi1ClockSelection);
1003 }
1004
1005 /*-------------------------- SPI2 clock source configuration ----------------*/
1006 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2)
1007 {
1008 /* Check the parameters */
1009 assert_param(IS_RCC_SPI2CLKSOURCE(pPeriphClkInit->Spi2ClockSelection));
1010
1011 /* Configure the SPI2 clock source */
1012 __HAL_RCC_SPI2_CONFIG(pPeriphClkInit->Spi2ClockSelection);
1013 }
1014
1015 /*-------------------------- SPI3 clock source configuration ----------------*/
1016 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3)
1017 {
1018 /* Check the parameters */
1019 assert_param(IS_RCC_SPI3CLKSOURCE(pPeriphClkInit->Spi3ClockSelection));
1020
1021 /* Configure the SPI3 clock source */
1022 __HAL_RCC_SPI3_CONFIG(pPeriphClkInit->Spi3ClockSelection);
1023 }
1024
1025 /*-------------------------- OctoSPIx clock source configuration ----------------*/
1026 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
1027 {
1028 /* Check the parameters */
1029 assert_param(IS_RCC_OSPICLKSOURCE(pPeriphClkInit->OspiClockSelection));
1030
1031 if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL1)
1032 {
1033 /* Enable PLL1 Q CLK output */
1034 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1035 }
1036 if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL2)
1037 {
1038 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
1039 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1040 }
1041 if (ret == HAL_OK)
1042 {
1043 /* Configure the OctoSPI clock source */
1044 __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection);
1045 }
1046 else
1047 {
1048 /* set overall return value */
1049 status = ret;
1050 }
1051 }
1052
1053 #if defined(HSPI1)
1054 /*-------------------------- HSPIx kernel clock source configuration ----------------*/
1055 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSPI) == RCC_PERIPHCLK_HSPI)
1056 {
1057
1058 /* Check the parameters */
1059 assert_param(IS_RCC_HSPICLKSOURCE(pPeriphClkInit->HspiClockSelection));
1060
1061 switch (pPeriphClkInit->HspiClockSelection)
1062 {
1063 case RCC_HSPICLKSOURCE_SYSCLK: /* SYSCLK is used as clock source for HSPI kernel clock*/
1064 /* HSPI kernel clock source config set later after clock selection check */
1065 break;
1066
1067 case RCC_HSPICLKSOURCE_PLL1: /* PLL1 is used as clock source for HSPI kernel clock*/
1068 /* Enable 48M2 Clock output generated from System PLL . */
1069 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1070 /* HSPI kernel clock source config set later after clock selection check */
1071 break;
1072
1073 case RCC_HSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for HSPI kernel clock*/
1074 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
1075 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1076 /* HSPI kernel clock source config set later after clock selection check */
1077 break;
1078
1079 case RCC_HSPICLKSOURCE_PLL3: /* PLL3 is used as clock source for HSPI kernel clock*/
1080 /* PLL3 input clock, parameters M, N & R configuration and clock output (PLL3ClockOut) */
1081 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1082 /* HSPI kernel clock source config set later after clock selection check */
1083 break;
1084
1085 default:
1086 ret = HAL_ERROR;
1087 break;
1088 }
1089
1090 if (ret == HAL_OK)
1091 {
1092 /* Set the source of HSPI kernel clock*/
1093 __HAL_RCC_HSPI_CONFIG(pPeriphClkInit->HspiClockSelection);
1094 }
1095 else
1096 {
1097 /* set overall return value */
1098 status = ret;
1099 }
1100 }
1101 #endif /* defined(HSPI1) */
1102
1103 /*-------------------------- FDCAN1 kernel clock source configuration -------------*/
1104 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN1) == (RCC_PERIPHCLK_FDCAN1))
1105 {
1106 assert_param(IS_RCC_FDCAN1CLK(pPeriphClkInit->Fdcan1ClockSelection));
1107
1108 switch (pPeriphClkInit->Fdcan1ClockSelection)
1109 {
1110 case RCC_FDCAN1CLKSOURCE_HSE: /* HSE is used as source of FDCAN1 kernel clock*/
1111 /* FDCAN1 kernel clock source config set later after clock selection check */
1112 break;
1113 case RCC_FDCAN1CLKSOURCE_PLL1: /* PLL1 is used as clock source for FDCAN1 kernel clock*/
1114 /* Enable 48M2 Clock output generated from System PLL */
1115 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1116 /* FDCAN1 kernel clock source config set later after clock selection check */
1117 break;
1118 case RCC_FDCAN1CLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN1 kernel clock*/
1119 /* PLL2 input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1120 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1121 /* FDCAN1 kernel clock source config set later after clock selection check */
1122 break;
1123 default:
1124 ret = HAL_ERROR;
1125 break;
1126 }
1127 if (ret == HAL_OK)
1128 {
1129 /* Set the source of FDCAN1 kernel clock*/
1130 __HAL_RCC_FDCAN1_CONFIG(pPeriphClkInit->Fdcan1ClockSelection);
1131 }
1132 else
1133 {
1134 /* set overall return value */
1135 status = ret;
1136 }
1137 }
1138
1139 /*-------------------------- DAC1 clock source configuration ----------------*/
1140 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DAC1) == RCC_PERIPHCLK_DAC1)
1141 {
1142
1143 /* Check the parameters */
1144 assert_param(IS_RCC_DAC1CLKSOURCE(pPeriphClkInit->Dac1ClockSelection));
1145
1146 /* Configure the DAC1 clock source */
1147 __HAL_RCC_DAC1_CONFIG(pPeriphClkInit->Dac1ClockSelection);
1148 }
1149
1150 #if defined(LTDC)
1151
1152 /*-------------------------- LTDC clock source configuration ----------------*/
1153 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
1154 {
1155
1156 /* Check the parameters */
1157 assert_param(IS_RCC_LTDCCLKSOURCE(pPeriphClkInit->LtdcClockSelection));
1158
1159 switch (pPeriphClkInit->LtdcClockSelection)
1160 {
1161 case RCC_LTDCCLKSOURCE_PLL2: /* PLL2 is used as clock source for LTDC clock*/
1162 /* PLL2 input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1163 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1164 /* LTDC clock source config set later after clock selection check */
1165 break;
1166
1167 case RCC_LTDCCLKSOURCE_PLL3: /* PLL3 is used as clock source for LTDC clock*/
1168 /* PLL3 input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
1169 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1170 /* LTDC clock source config set later after clock selection check */
1171 break;
1172
1173 default:
1174 ret = HAL_ERROR;
1175 break;
1176 }
1177
1178 if (ret == HAL_OK)
1179 {
1180 /* Set the source of LTDC clock*/
1181 __HAL_RCC_LTDC_CONFIG(pPeriphClkInit->LtdcClockSelection);
1182 }
1183 else
1184 {
1185 /* set overall return value */
1186 status = ret;
1187 }
1188 }
1189
1190 #endif /* defined(LTDC) */
1191
1192 #if defined(DSI)
1193
1194 /*-------------------------- DSI clock source configuration ----------------*/
1195 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
1196 {
1197
1198 /* Check the parameters */
1199 assert_param(IS_RCC_DSICLKSOURCE(pPeriphClkInit->DsiClockSelection));
1200
1201 if (pPeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLL3)
1202 {
1203 /* PLL3 is used as clock source for DSI clock*/
1204 /* PLL3 input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
1205 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1206 }
1207
1208 if (ret == HAL_OK)
1209 {
1210 /* Set the source of DSI clock*/
1211 __HAL_RCC_DSI_CONFIG(pPeriphClkInit->DsiClockSelection);
1212 }
1213 else
1214 {
1215 /* set overall return value */
1216 status = ret;
1217 }
1218 }
1219
1220 #endif /* defined(DSI) */
1221
1222 #if defined(USB_OTG_HS)
1223
1224 /*-------------------------- USB PHY clock source configuration ----------------*/
1225 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USBPHY) == RCC_PERIPHCLK_USBPHY)
1226 {
1227
1228 /* Check the parameters */
1229 assert_param(IS_RCC_USBPHYCLKSOURCE(pPeriphClkInit->UsbPhyClockSelection));
1230
1231 switch (pPeriphClkInit->UsbPhyClockSelection)
1232 {
1233 case RCC_USBPHYCLKSOURCE_HSE: /* HSE is used as clock source for USB PHY clock*/
1234 case RCC_USBPHYCLKSOURCE_HSE_DIV2: /* HSE div 2 is used as clock source for USB PHY clock*/
1235 /* USB-PHY clock source config set later after clock selection check */
1236 break;
1237
1238 case RCC_USBPHYCLKSOURCE_PLL1: /* PLL1 P divider clock selected as USB PHY clock */
1239 case RCC_USBPHYCLKSOURCE_PLL1_DIV2: /* PLL1 P divider clock div 2 selected as USB PHY clock */
1240 /* Enable P Clock output generated from System PLL . */
1241 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
1242 /* USB-PHY clock source config set later after clock selection check */
1243 break;
1244
1245 default:
1246 ret = HAL_ERROR;
1247 break;
1248 }
1249
1250 if (ret == HAL_OK)
1251 {
1252 /* Set the source of USBPHY clock*/
1253 __HAL_RCC_USBPHY_CONFIG(pPeriphClkInit->UsbPhyClockSelection);
1254 }
1255 else
1256 {
1257 /* set overall return value */
1258 status = ret;
1259 }
1260 }
1261
1262 #endif /* defined(USB_OTG_HS) */
1263
1264 return status;
1265 }
1266
1267
1268 /**
1269 * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
1270 * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
1271 * returns the configuration information for the Extended Peripherals
1272 * clocks(USART1, USART2, USART3, UART4, UART5, LPUART, I2C1, I2C2, I2C3, LPTIM1, LPTIM2, SAI1, SAI2,
1273 * ADC1, ADC2, MDF1, MDF2, RTC, CLK48, SDMMC1, I2C4, SPI12, SPI3, OSPI, FDCAN1, DAC1).
1274 * @retval None
1275 */
HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef * pPeriphClkInit)1276 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
1277 {
1278 /* Set all possible values for the extended clock type parameter------------*/
1279 #if (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx))
1280 pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1281 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \
1282 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
1283 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \
1284 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
1285 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \
1286 RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \
1287 RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \
1288 RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
1289 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \
1290 RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \
1291 RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_USBPHY;
1292 #elif (defined(STM32U595xx) || defined(STM32U5A5xx))
1293 pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1294 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \
1295 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
1296 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \
1297 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
1298 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \
1299 RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \
1300 RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \
1301 RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
1302 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \
1303 RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_USBPHY;
1304 #elif (defined(STM32U585xx) || defined(STM32U575xx))
1305 pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1306 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \
1307 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
1308 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
1309 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
1310 RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \
1311 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | \
1312 RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \
1313 RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | \
1314 RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1;
1315
1316 #else
1317 pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \
1318 RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \
1319 RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \
1320 RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
1321 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \
1322 RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ICLK | \
1323 RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | \
1324 RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \
1325 RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1;
1326 #endif /* (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) */
1327
1328 #if defined(SAES)
1329 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAES;
1330 #endif /* SAES */
1331
1332 /* Get the PLL2 Clock configuration -----------------------------------------------*/
1333 pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFGR_PLL2SRC_Pos);
1334 pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U;
1335 pPeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1U;
1336 pPeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1U;
1337 pPeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1U;
1338 pPeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + 1U;
1339 pPeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2RGE) >> RCC_PLL2CFGR_PLL2RGE_Pos);
1340 pPeriphClkInit->PLL2.PLL2FRACN = (uint32_t)((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
1341 RCC_PLL2FRACR_PLL2FRACN_Pos);
1342
1343 /* Get the PLL3 Clock configuration -----------------------------------------------*/
1344 pPeriphClkInit->PLL3.PLL3Source = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC) >> RCC_PLL3CFGR_PLL3SRC_Pos);
1345 pPeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U;
1346 pPeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1U;
1347 pPeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1U;
1348 pPeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1U;
1349 pPeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1U;
1350 pPeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3RGE) >> RCC_PLL3CFGR_PLL3RGE_Pos);
1351 pPeriphClkInit->PLL3.PLL3FRACN = (uint32_t)((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
1352 RCC_PLL3FRACR_PLL3FRACN_Pos);
1353
1354 /* Get the USART1 clock source ---------------------------------------------*/
1355 pPeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
1356
1357 #if defined(USART2)
1358 /* Get the USART2 clock source ---------------------------------------------*/
1359 pPeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
1360 #endif /* USART2 */
1361
1362 /* Get the USART3 clock source ---------------------------------------------*/
1363 pPeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
1364
1365 /* Get the UART4 clock source ----------------------------------------------*/
1366 pPeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
1367
1368 /* Get the UART5 clock source ----------------------------------------------*/
1369 pPeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
1370
1371 /* Get the LPUART1 clock source --------------------------------------------*/
1372 pPeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
1373
1374 #if defined(USART6)
1375 /* Get the UART6 clock source ---------------------------------------------*/
1376 pPeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
1377 #endif /* defined(USART6) */
1378
1379 /* Get the I2C1 clock source -----------------------------------------------*/
1380 pPeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
1381
1382 /* Get the I2C2 clock source -----------------------------------------------*/
1383 pPeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
1384
1385 /* Get the I2C3 clock source -----------------------------------------------*/
1386 pPeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
1387
1388 /* Get the I2C4 clock source -----------------------------------------------*/
1389 pPeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
1390
1391 #if defined(I2C5)
1392 /* Get the clock source ---------------------------------------------*/
1393 pPeriphClkInit->I2c5ClockSelection = __HAL_RCC_GET_I2C5_SOURCE();
1394 #endif /* defined(I2C5) */
1395
1396 #if defined(I2C6)
1397 /* Get the clock source ---------------------------------------------*/
1398 pPeriphClkInit->I2c6ClockSelection = __HAL_RCC_GET_I2C6_SOURCE();
1399 #endif /* defined(I2C6) */
1400
1401 /* Get the LPTIM1 clock source ---------------------------------------------*/
1402 pPeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
1403
1404 /* Get the LPTIM2 clock source ---------------------------------------------*/
1405 pPeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
1406
1407 /* Get the LPTIM34 clock source --------------------------------------------*/
1408 pPeriphClkInit->Lptim34ClockSelection = __HAL_RCC_GET_LPTIM34_SOURCE();
1409
1410 /* Get the FDCAN1 clock source ---------------------------------------------*/
1411 pPeriphClkInit->Fdcan1ClockSelection = __HAL_RCC_GET_FDCAN1_SOURCE();
1412
1413 /* Get the MDF1 clock source -----------------------------------------------*/
1414 pPeriphClkInit->Mdf1ClockSelection = __HAL_RCC_GET_MDF1_SOURCE();
1415
1416 /* Get the ADF1 clock source -----------------------------------------------*/
1417 pPeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE();
1418
1419 #if defined(SAES)
1420 /* Get the SAES clock source -----------------------------------------------*/
1421 pPeriphClkInit->SaesClockSelection = __HAL_RCC_GET_SAES_SOURCE();
1422 #endif /* SAES */
1423
1424 /* Get the SAI1 clock source -----------------------------------------------*/
1425 pPeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
1426
1427 #if defined(SAI2)
1428 /* Get the SAI2 clock source -----------------------------------------------*/
1429 pPeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
1430 #endif /* SAI2 */
1431
1432 /* Get the CLK48 clock source ----------------------------------------------*/
1433 pPeriphClkInit->IclkClockSelection = __HAL_RCC_GET_ICLK_SOURCE();
1434
1435 /* Get the SDMMC clock source ----------------------------------------------*/
1436 pPeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE();
1437
1438 /* Get the ADCDAC clock source ---------------------------------------------*/
1439 pPeriphClkInit->AdcDacClockSelection = __HAL_RCC_GET_ADCDAC_SOURCE();
1440
1441 /* Get the DAC1 clock source -----------------------------------------------*/
1442 pPeriphClkInit->Dac1ClockSelection = __HAL_RCC_GET_DAC1_SOURCE();
1443
1444 /* Get the OSPI clock source -----------------------------------------------*/
1445 pPeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();
1446
1447 /* Get the SPI1 clock source -----------------------------------------------*/
1448 pPeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE();
1449
1450 /* Get the SPI2 clock source -----------------------------------------------*/
1451 pPeriphClkInit->Spi2ClockSelection = __HAL_RCC_GET_SPI2_SOURCE();
1452
1453 /* Get the SPI3 clock source -----------------------------------------------*/
1454 pPeriphClkInit->Spi3ClockSelection = __HAL_RCC_GET_SPI3_SOURCE();
1455
1456 /* Get the RTC clock source ------------------------------------------------*/
1457 pPeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
1458
1459 /* Get the RNG clock source ------------------------------------------------*/
1460 pPeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
1461
1462 #if defined(HSPI1)
1463 /* Get the HSPI kernel clock source ------------------------------------------------*/
1464 pPeriphClkInit->HspiClockSelection = __HAL_RCC_GET_HSPI_SOURCE();
1465 #endif /* defined(HSPI1) */
1466
1467 #if defined(LTDC)
1468 /* Get the LTDC clock source ------------------------------------------------*/
1469 pPeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE();
1470 #endif /* defined(LTDC) */
1471
1472 #if defined(DSI)
1473 /* Get the DSI clock source ------------------------------------------------*/
1474 pPeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();
1475 #endif /* defined(DSI) */
1476
1477 #if defined(USB_OTG_HS)
1478 /* Get the USB PHY clock source ------------------------------------------------*/
1479 pPeriphClkInit->UsbPhyClockSelection = __HAL_RCC_GET_USBPHY_SOURCE();
1480 #endif /* defined(USB_OTG_HS) */
1481 }
1482
1483 /**
1484 * @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
1485 * @note The PLL1 clock frequencies computed by this function is not the real
1486 * frequency in the chip. It is calculated based on the predefined
1487 * constant and the selected clock source:
1488 * @note The function returns values based on HSE_VALUE, HSI_VALUE or MSI Value multiplied/divided by the PLL
1489 * factors.
1490 * @note This function can be used by the user application to compute the
1491 * baud-rate for the communication peripherals or configure other parameters.
1492 *
1493 * @note Each time PLL1CLK changes, this function must be called to update the
1494 * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
1495 * @param PLL1_Clocks structure.
1496 * @retval None
1497 */
HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef * PLL1_Clocks)1498 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
1499 {
1500 uint32_t pll1source;
1501 uint32_t pll1m;
1502 uint32_t pll1n;
1503 uint32_t pll1fracen;
1504 float_t fracn1;
1505 float_t pll1vco;
1506
1507 pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N);
1508 pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
1509 pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
1510 pll1fracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos);
1511 fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
1512 RCC_PLL1FRACR_PLL1FRACN_Pos));
1513
1514 switch (pll1source)
1515 {
1516
1517 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1518 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
1519 (fracn1 / (float_t)0x2000) + (float_t)1);
1520 break;
1521 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1522 pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \
1523 ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1);
1524 break;
1525 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1526 pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
1527 (fracn1 / (float_t)0x2000) + (float_t)1);
1528 break;
1529 default:
1530 pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \
1531 ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1);
1532 break;
1533 }
1534
1535 if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVP) != 0U)
1536 {
1537 PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
1538 RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + \
1539 (float_t)1));
1540 }
1541 else
1542 {
1543 PLL1_Clocks->PLL1_P_Frequency = 0U;
1544 }
1545
1546 if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVQ) != 0U)
1547 {
1548 PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
1549 RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + \
1550 (float_t)1));
1551 }
1552 else
1553 {
1554 PLL1_Clocks->PLL1_Q_Frequency = 0U;
1555 }
1556
1557 if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVR) != 0U)
1558 {
1559 PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
1560 RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + \
1561 (float_t)1));
1562 }
1563 else
1564 {
1565 PLL1_Clocks->PLL1_R_Frequency = 0U;
1566 }
1567
1568 }
1569
1570 /**
1571 * @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
1572 * @note The PLL2 clock frequencies computed by this function is not the real
1573 * frequency in the chip. It is calculated based on the predefined
1574 * constant and the selected clock source:
1575 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL
1576 * factors.
1577 * @note This function can be used by the user application to compute the
1578 * baud-rate for the communication peripherals or configure other parameters.
1579 *
1580 * @note Each time PLL2CLK changes, this function must be called to update the
1581 * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
1582 * @param PLL2_Clocks structure.
1583 * @retval None
1584 */
HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef * PLL2_Clocks)1585 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
1586 {
1587 uint32_t pll2source;
1588 uint32_t pll2m;
1589 uint32_t pll2n;
1590 uint32_t pll2fracen;
1591 float_t fracn2;
1592 float_t pll2vco;
1593
1594 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
1595 PLL2xCLK = PLL2_VCO / PLL2x */
1596 pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N);
1597 pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC);
1598 pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U;
1599 pll2fracen = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN) >> RCC_PLL2CFGR_PLL2FRACEN_Pos);
1600 fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
1601 RCC_PLL2FRACR_PLL2FRACN_Pos));
1602
1603 switch (pll2source)
1604 {
1605 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1606 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \
1607 (fracn2 / (float_t)0x2000) + (float_t)1);
1608 break;
1609
1610 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1611 pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll2m) * \
1612 ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1);
1613 break;
1614
1615 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1616 pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \
1617 (fracn2 / (float_t)0x2000) + (float_t)1);
1618 break;
1619
1620 default:
1621 pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t) pll2m) \
1622 * ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1);
1623 break;
1624 }
1625 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U)
1626 {
1627 PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
1628 RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + \
1629 (float_t)1));
1630 }
1631 else
1632 {
1633 PLL2_Clocks->PLL2_P_Frequency = 0U;
1634 }
1635 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVQ) != 0U)
1636 {
1637 PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
1638 RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + \
1639 (float_t)1));
1640 }
1641 else
1642 {
1643 PLL2_Clocks->PLL2_Q_Frequency = 0U;
1644 }
1645 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVR) != 0U)
1646 {
1647 PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
1648 RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + \
1649 (float_t)1));
1650 }
1651 else
1652 {
1653 PLL2_Clocks->PLL2_R_Frequency = 0U;
1654 }
1655 }
1656
1657 /**
1658 * @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
1659 * @note The PLL3 clock frequencies computed by this function is not the real
1660 * frequency in the chip. It is calculated based on the predefined
1661 * constant and the selected clock source:
1662 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL
1663 * factors.
1664 * @note This function can be used by the user application to compute the
1665 * baud-rate for the communication peripherals or configure other parameters.
1666 *
1667 * @note Each time PLL3CLK changes, this function must be called to update the
1668 * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
1669 * @param PLL3_Clocks structure.
1670 * @retval None
1671 */
HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef * PLL3_Clocks)1672 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
1673 {
1674 uint32_t pll3source;
1675 uint32_t pll3m;
1676 uint32_t pll3n;
1677 uint32_t pll3fracen;
1678 float_t fracn3;
1679 float_t pll3vco;
1680
1681 /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
1682 PLL3xCLK = PLL3_VCO / PLLxR
1683 */
1684
1685 pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N);
1686 pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC);
1687 pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U;
1688 pll3fracen = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN) >> RCC_PLL3CFGR_PLL3FRACEN_Pos);
1689 fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
1690 RCC_PLL3FRACR_PLL3FRACN_Pos));
1691
1692 switch (pll3source)
1693 {
1694 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1695 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \
1696 (fracn3 / (float_t)0x2000) + (float_t)1);
1697
1698 break;
1699 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1700 pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \
1701 ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1);
1702 break;
1703
1704 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1705 pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \
1706 (fracn3 / (float_t)0x2000) + (float_t)1);
1707 break;
1708
1709 default:
1710 pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \
1711 ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1);
1712 break;
1713 }
1714
1715 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVP) != 0U)
1716 {
1717 PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
1718 RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + \
1719 (float_t)1));
1720 }
1721 else
1722 {
1723 PLL3_Clocks->PLL3_P_Frequency = 0U;
1724 }
1725
1726 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVQ) != 0U)
1727 {
1728 PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
1729 RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + \
1730 (float_t)1));
1731 }
1732 else
1733 {
1734 PLL3_Clocks->PLL3_Q_Frequency = 0U;
1735 }
1736
1737 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVR) != 0U)
1738 {
1739 PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
1740 RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + \
1741 (float_t)1));
1742 }
1743 else
1744 {
1745 PLL3_Clocks->PLL3_R_Frequency = 0U;
1746 }
1747
1748 }
1749
1750 /**
1751 * @brief Return the peripheral clock frequency for peripherals
1752 * @note Return 0 if peripheral clock identifier not managed by this API
1753 * @param PeriphClk Peripheral clock identifier
1754 * This parameter can be one of the following values:
1755 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
1756 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
1757 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
1758 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
1759 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
1760 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
1761 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
1762 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock
1763 * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
1764 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
1765 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
1766 * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock
1767 * @arg @ref RCC_PERIPHCLK_ICLK ICLK peripheral clock
1768 * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock
1769 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
1770 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock
1771 * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock (*)
1772 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
1773 * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC peripheral clock
1774 * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*)
1775 * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (*)
1776 * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock
1777 * @arg @ref RCC_PERIPHCLK_HSPI HSPI peripheral clock (*)
1778 * @arg @ref RCC_PERIPHCLK_I2C5 I2C5 peripheral clock (*)
1779 * @arg @ref RCC_PERIPHCLK_I2C6 I2C6 peripheral clock (*)
1780 * @arg @ref RCC_PERIPHCLK_USBPHY USB_OTG_HS peripheral clock (*)
1781 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
1782 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
1783 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
1784 * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock
1785 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
1786 * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1 ADC2 ADC4 DAC1 peripheral clock
1787 * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock
1788 * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock
1789 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
1790 * @retval Frequency in Hz
1791 *
1792 * (*) value not defined in all devices.
1793 */
HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)1794 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
1795 {
1796 PLL1_ClocksTypeDef pll1_clocks;
1797 PLL2_ClocksTypeDef pll2_clocks;
1798 PLL3_ClocksTypeDef pll3_clocks;
1799
1800 uint32_t frequency;
1801 uint32_t srcclk;
1802
1803 /* Check the parameters */
1804 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
1805
1806 if (PeriphClk == RCC_PERIPHCLK_RTC)
1807 {
1808 /* Get the current RTC source */
1809 srcclk = __HAL_RCC_GET_RTC_SOURCE();
1810
1811 /* Check if LSE is ready and if RTC clock selection is LSE */
1812 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
1813 {
1814 frequency = LSE_VALUE;
1815 }
1816 /* Check if LSI is ready and if RTC clock selection is LSI */
1817 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
1818 {
1819 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
1820 {
1821 frequency = LSI_VALUE / 128U;
1822 }
1823 else
1824 {
1825 frequency = LSI_VALUE;
1826 }
1827 }
1828 /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
1829 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32))
1830 {
1831 frequency = HSE_VALUE / 32U;
1832 }
1833 /* Clock not enabled for RTC*/
1834 else
1835 {
1836 frequency = 0U;
1837 }
1838 }
1839 else if (PeriphClk == RCC_PERIPHCLK_SAI1)
1840 {
1841 srcclk = __HAL_RCC_GET_SAI1_SOURCE();
1842
1843 switch (srcclk)
1844 {
1845 case RCC_SAI1CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */
1846
1847 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1848 frequency = pll1_clocks.PLL1_P_Frequency;
1849 break;
1850
1851 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */
1852
1853 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1854 frequency = pll2_clocks.PLL2_P_Frequency;
1855 break;
1856
1857 case RCC_SAI1CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */
1858
1859 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
1860 frequency = pll3_clocks.PLL3_P_Frequency;
1861 break;
1862
1863 case RCC_SAI1CLKSOURCE_PIN:
1864
1865 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
1866 break;
1867
1868 case RCC_SAI1CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */
1869
1870 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1871 {
1872 frequency = HSI_VALUE;
1873 }
1874 else
1875 {
1876 frequency = 0U;
1877 }
1878 break;
1879
1880 default :
1881 {
1882 frequency = 0U;
1883 break;
1884 }
1885 }
1886 }
1887 #if defined(SAI2)
1888 else if (PeriphClk == RCC_PERIPHCLK_SAI2)
1889 {
1890 srcclk = __HAL_RCC_GET_SAI2_SOURCE();
1891
1892 switch (srcclk)
1893 {
1894 case RCC_SAI2CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */
1895
1896 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1897 frequency = pll1_clocks.PLL1_P_Frequency;
1898 break;
1899
1900 case RCC_SAI2CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */
1901
1902 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1903 frequency = pll2_clocks.PLL2_P_Frequency;
1904 break;
1905
1906 case RCC_SAI2CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */
1907
1908 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
1909 frequency = pll3_clocks.PLL3_P_Frequency;
1910 break;
1911
1912 case RCC_SAI2CLKSOURCE_PIN:
1913
1914 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
1915 break;
1916
1917 case RCC_SAI2CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */
1918
1919 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1920 {
1921 frequency = HSI_VALUE;
1922 }
1923 else
1924 {
1925 frequency = 0U;
1926 }
1927 break;
1928
1929 default :
1930
1931 frequency = 0U;
1932 break;
1933 }
1934 }
1935 #endif /* SAI2 */
1936 #if defined(SAES)
1937 else if (PeriphClk == RCC_PERIPHCLK_SAES)
1938 {
1939 /* Get the current SAES source */
1940 srcclk = __HAL_RCC_GET_SAES_SOURCE();
1941
1942 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI))
1943 {
1944 frequency = HSI_VALUE;
1945 }
1946 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI_DIV2))
1947 {
1948 frequency = HSI_VALUE >> 1U;
1949 }
1950 /* Clock not enabled for SAES */
1951 else
1952 {
1953 frequency = 0U;
1954 }
1955 }
1956 #endif /* SAES */
1957 else if (PeriphClk == RCC_PERIPHCLK_ICLK)
1958 {
1959 srcclk = __HAL_RCC_GET_ICLK_SOURCE();
1960
1961 switch (srcclk)
1962 {
1963 case RCC_ICLK_CLKSOURCE_PLL1: /* PLL1Q */
1964
1965 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1966 frequency = pll1_clocks.PLL1_Q_Frequency;
1967 break;
1968
1969 case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2Q */
1970
1971 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1972 frequency = pll2_clocks.PLL2_Q_Frequency;
1973 break;
1974
1975 case RCC_ICLK_CLKSOURCE_HSI48: /* HSI48 */
1976
1977 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY))
1978 {
1979 frequency = HSI48_VALUE;
1980 }
1981 else
1982 {
1983 frequency = 0U;
1984 }
1985 break;
1986
1987 case RCC_ICLK_CLKSOURCE_MSIK: /* MSIK frequency range in HZ */
1988
1989 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
1990 {
1991 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
1992 }
1993 else
1994 {
1995 frequency = 0U;
1996 }
1997 break;
1998
1999 default :
2000
2001 frequency = 0U;
2002 break;
2003 }
2004 }
2005 else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
2006 {
2007 srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
2008 if (srcclk == RCC_SDMMCCLKSOURCE_CLK48)
2009 {
2010 srcclk = __HAL_RCC_GET_ICLK_SOURCE();
2011
2012 switch (srcclk)
2013 {
2014 case RCC_ICLK_CLKSOURCE_PLL1: /* PLL1Q */
2015 {
2016 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2017 frequency = pll1_clocks.PLL1_Q_Frequency;
2018 break;
2019 }
2020 case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2Q */
2021 {
2022 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2023 frequency = pll2_clocks.PLL2_Q_Frequency;
2024 break;
2025 }
2026 case RCC_ICLK_CLKSOURCE_HSI48: /* HSI48 */
2027 {
2028 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY))
2029 {
2030 frequency = HSI48_VALUE;
2031 }
2032 else
2033 {
2034 frequency = 0U;
2035 }
2036 break;
2037 }
2038 case RCC_ICLK_CLKSOURCE_MSIK: /* MSIK frequency range in HZ */
2039 {
2040 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2041 {
2042 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2043 }
2044 else
2045 {
2046 frequency = 0U;
2047 }
2048 break;
2049 }
2050 default :
2051 {
2052 frequency = 0U;
2053 break;
2054 }
2055 }
2056 }
2057 else if (srcclk == RCC_SDMMCCLKSOURCE_PLL1)
2058 {
2059 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2060 frequency = pll1_clocks.PLL1_P_Frequency;
2061 }
2062 else
2063 {
2064 frequency = 0U;
2065 }
2066 }
2067 else if (PeriphClk == RCC_PERIPHCLK_USART1)
2068 {
2069 /* Get the current USART1 source */
2070 srcclk = __HAL_RCC_GET_USART1_SOURCE();
2071
2072 if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
2073 {
2074 frequency = HAL_RCC_GetPCLK2Freq();
2075 }
2076 else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
2077 {
2078 frequency = HAL_RCC_GetSysClockFreq();
2079 }
2080 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI))
2081 {
2082 frequency = HSI_VALUE;
2083 }
2084 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
2085 {
2086 frequency = LSE_VALUE;
2087 }
2088 /* Clock not enabled for USART1 */
2089 else
2090 {
2091 frequency = 0U;
2092 }
2093 }
2094 #if defined(USART2)
2095 else if (PeriphClk == RCC_PERIPHCLK_USART2)
2096 {
2097 /* Get the current USART2 source */
2098 srcclk = __HAL_RCC_GET_USART2_SOURCE();
2099
2100 if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
2101 {
2102 frequency = HAL_RCC_GetPCLK1Freq();
2103 }
2104 else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
2105 {
2106 frequency = HAL_RCC_GetSysClockFreq();
2107 }
2108 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
2109 {
2110 frequency = HSI_VALUE;
2111 }
2112 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE))
2113 {
2114 frequency = LSE_VALUE;
2115 }
2116 /* Clock not enabled for USART2 */
2117 else
2118 {
2119 frequency = 0U;
2120 }
2121 }
2122 #endif /* USART2 */
2123 else if (PeriphClk == RCC_PERIPHCLK_USART3)
2124 {
2125 /* Get the current USART3 source */
2126 srcclk = __HAL_RCC_GET_USART3_SOURCE();
2127
2128 if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
2129 {
2130 frequency = HAL_RCC_GetPCLK1Freq();
2131 }
2132 else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
2133 {
2134 frequency = HAL_RCC_GetSysClockFreq();
2135 }
2136 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI))
2137 {
2138 frequency = HSI_VALUE;
2139 }
2140 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE))
2141 {
2142 frequency = LSE_VALUE;
2143 }
2144 /* Clock not enabled for USART3 */
2145 else
2146 {
2147 frequency = 0U;
2148 }
2149 }
2150 else if (PeriphClk == RCC_PERIPHCLK_UART4)
2151 {
2152 /* Get the current UART4 source */
2153 srcclk = __HAL_RCC_GET_UART4_SOURCE();
2154
2155 if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
2156 {
2157 frequency = HAL_RCC_GetPCLK1Freq();
2158 }
2159 else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK)
2160 {
2161 frequency = HAL_RCC_GetSysClockFreq();
2162 }
2163 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI))
2164 {
2165 frequency = HSI_VALUE;
2166 }
2167 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE))
2168 {
2169 frequency = LSE_VALUE;
2170 }
2171 /* Clock not enabled for UART4 */
2172 else
2173 {
2174 frequency = 0U;
2175 }
2176 }
2177 else if (PeriphClk == RCC_PERIPHCLK_UART5)
2178 {
2179 /* Get the current UART5 source */
2180 srcclk = __HAL_RCC_GET_UART5_SOURCE();
2181
2182 if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
2183 {
2184 frequency = HAL_RCC_GetPCLK1Freq();
2185 }
2186 else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK)
2187 {
2188 frequency = HAL_RCC_GetSysClockFreq();
2189 }
2190 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI))
2191 {
2192 frequency = HSI_VALUE;
2193 }
2194 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE))
2195 {
2196 frequency = LSE_VALUE;
2197 }
2198 /* Clock not enabled for UART5 */
2199 else
2200 {
2201 frequency = 0U;
2202 }
2203 }
2204 #if defined(USART6)
2205 else if (PeriphClk == RCC_PERIPHCLK_USART6)
2206 {
2207 /* Get the current USART6 source */
2208 srcclk = __HAL_RCC_GET_USART6_SOURCE();
2209
2210 if (srcclk == RCC_USART6CLKSOURCE_PCLK1)
2211 {
2212 frequency = HAL_RCC_GetPCLK1Freq();
2213 }
2214 else if (srcclk == RCC_USART6CLKSOURCE_SYSCLK)
2215 {
2216 frequency = HAL_RCC_GetSysClockFreq();
2217 }
2218 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_HSI))
2219 {
2220 frequency = HSI_VALUE;
2221 }
2222 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART6CLKSOURCE_LSE))
2223 {
2224 frequency = LSE_VALUE;
2225 }
2226 /* Clock not enabled for UART5 */
2227 else
2228 {
2229 frequency = 0U;
2230 }
2231 }
2232 #endif /* USART6 */
2233 else if (PeriphClk == RCC_PERIPHCLK_LPUART1)
2234 {
2235 /* Get the current LPUART1 source */
2236 srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
2237
2238 if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3)
2239 {
2240 frequency = HAL_RCC_GetPCLK3Freq();
2241 }
2242 else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
2243 {
2244 frequency = HAL_RCC_GetSysClockFreq();
2245 }
2246 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
2247 {
2248 frequency = HSI_VALUE;
2249 }
2250 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
2251 {
2252 frequency = LSE_VALUE;
2253 }
2254 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_MSIK))
2255 {
2256 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2257 }
2258 /* Clock not enabled for LPUART1 */
2259 else
2260 {
2261 frequency = 0U;
2262 }
2263 }
2264 else if (PeriphClk == RCC_PERIPHCLK_ADCDAC)
2265 {
2266 srcclk = __HAL_RCC_GET_ADCDAC_SOURCE();
2267
2268 if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK)
2269 {
2270 frequency = HAL_RCC_GetSysClockFreq();
2271 }
2272 else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2)
2273 {
2274 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2275 frequency = pll2_clocks.PLL2_R_Frequency;
2276 }
2277 else if (srcclk == RCC_ADCDACCLKSOURCE_HCLK)
2278 {
2279 frequency = HAL_RCC_GetHCLKFreq();
2280 }
2281 else if (srcclk == RCC_ADCDACCLKSOURCE_MSIK)
2282 {
2283 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2284 {
2285 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2286 }
2287 else
2288 {
2289 frequency = 0U;
2290 }
2291 }
2292 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE))
2293 {
2294 frequency = HSE_VALUE;
2295 }
2296 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI))
2297 {
2298 frequency = HSI_VALUE;
2299 }
2300 /* Clock not enabled for ADC */
2301 else
2302 {
2303 frequency = 0U;
2304 }
2305 }
2306 else if (PeriphClk == RCC_PERIPHCLK_MDF1)
2307 {
2308 /* Get the current MDF1 source */
2309 srcclk = __HAL_RCC_GET_MDF1_SOURCE();
2310
2311 switch (srcclk)
2312 {
2313 case RCC_MDF1CLKSOURCE_PLL1:
2314
2315 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2316 frequency = pll1_clocks.PLL1_P_Frequency;
2317 break;
2318
2319 case RCC_MDF1CLKSOURCE_PLL3:
2320
2321 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2322 frequency = pll3_clocks.PLL3_Q_Frequency;
2323 break;
2324
2325 case RCC_MDF1CLKSOURCE_HCLK:
2326
2327 frequency = HAL_RCC_GetHCLKFreq();
2328 break;
2329
2330 case RCC_MDF1CLKSOURCE_PIN:
2331
2332 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
2333 break;
2334
2335 case RCC_MDF1CLKSOURCE_MSIK:
2336
2337 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2338 {
2339 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2340 }
2341 else
2342 {
2343 frequency = 0U;
2344 }
2345 break;
2346
2347 default:
2348
2349 frequency = 0U;
2350 break;
2351 }
2352 }
2353 else if (PeriphClk == RCC_PERIPHCLK_ADF1)
2354 {
2355 /* Get the current ADF1 source */
2356 srcclk = __HAL_RCC_GET_ADF1_SOURCE();
2357
2358 switch (srcclk)
2359 {
2360 case RCC_ADF1CLKSOURCE_PLL1:
2361
2362 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2363 frequency = pll1_clocks.PLL1_P_Frequency;
2364 break;
2365
2366 case RCC_ADF1CLKSOURCE_PLL3:
2367
2368 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2369 frequency = pll3_clocks.PLL3_Q_Frequency;
2370 break;
2371
2372 case RCC_ADF1CLKSOURCE_HCLK:
2373
2374 frequency = HAL_RCC_GetHCLKFreq();
2375 break;
2376
2377 case RCC_ADF1CLKSOURCE_PIN:
2378
2379 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
2380 break;
2381
2382 case RCC_ADF1CLKSOURCE_MSIK:
2383
2384 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2385 {
2386 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2387 }
2388 else
2389 {
2390 frequency = 0U;
2391 }
2392 break;
2393
2394 default:
2395
2396 frequency = 0U;
2397 break;
2398 }
2399 }
2400 else if (PeriphClk == RCC_PERIPHCLK_I2C1)
2401 {
2402 /* Get the current I2C1 source */
2403 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
2404
2405 if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
2406 {
2407 frequency = HAL_RCC_GetPCLK1Freq();
2408 }
2409 else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
2410 {
2411 frequency = HAL_RCC_GetSysClockFreq();
2412 }
2413 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
2414 {
2415 frequency = HSI_VALUE;
2416 }
2417 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C1CLKSOURCE_MSIK))
2418 {
2419 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2420 }
2421 /* Clock not enabled for I2C1 */
2422 else
2423 {
2424 frequency = 0U;
2425 }
2426 }
2427 else if (PeriphClk == RCC_PERIPHCLK_I2C2)
2428 {
2429 /* Get the current I2C2 source */
2430 srcclk = __HAL_RCC_GET_I2C2_SOURCE();
2431
2432 if (srcclk == RCC_I2C2CLKSOURCE_PCLK1)
2433 {
2434 frequency = HAL_RCC_GetPCLK1Freq();
2435 }
2436 else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
2437 {
2438 frequency = HAL_RCC_GetSysClockFreq();
2439 }
2440 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI))
2441 {
2442 frequency = HSI_VALUE;
2443 }
2444 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C2CLKSOURCE_MSIK))
2445 {
2446 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2447 }
2448 /* Clock not enabled for I2C2 */
2449 else
2450 {
2451 frequency = 0U;
2452 }
2453 }
2454 else if (PeriphClk == RCC_PERIPHCLK_I2C3)
2455 {
2456 /* Get the current I2C3 source */
2457 srcclk = __HAL_RCC_GET_I2C3_SOURCE();
2458
2459 switch (srcclk)
2460 {
2461 case RCC_I2C3CLKSOURCE_PCLK3:
2462 {
2463 frequency = HAL_RCC_GetPCLK3Freq();
2464 break;
2465 }
2466 case RCC_I2C3CLKSOURCE_HSI:
2467 {
2468 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2469 {
2470 frequency = HSI_VALUE;
2471 }
2472 else
2473 {
2474 frequency = 0U;
2475 }
2476 break;
2477 }
2478 case RCC_I2C3CLKSOURCE_SYSCLK:
2479 {
2480 frequency = HAL_RCC_GetSysClockFreq();
2481 break;
2482 }
2483 case RCC_I2C3CLKSOURCE_MSIK:
2484 {
2485 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2486 {
2487 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2488 }
2489 else
2490 {
2491 frequency = 0U;
2492 }
2493 break;
2494 }
2495 default:
2496 {
2497 frequency = 0U;
2498 break;
2499 }
2500 }
2501 }
2502 else if (PeriphClk == RCC_PERIPHCLK_I2C4)
2503 {
2504 /* Get the current I2C4 source */
2505 srcclk = __HAL_RCC_GET_I2C4_SOURCE();
2506
2507 if (srcclk == RCC_I2C4CLKSOURCE_PCLK1)
2508 {
2509 frequency = HAL_RCC_GetPCLK1Freq();
2510 }
2511 else if (srcclk == RCC_I2C4CLKSOURCE_SYSCLK)
2512 {
2513 frequency = HAL_RCC_GetSysClockFreq();
2514 }
2515 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI))
2516 {
2517 frequency = HSI_VALUE;
2518 }
2519 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C4CLKSOURCE_MSIK))
2520 {
2521 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2522 }
2523 /* Clock not enabled for I2C4 */
2524 else
2525 {
2526 frequency = 0U;
2527 }
2528 }
2529 #if defined (I2C5)
2530 else if (PeriphClk == RCC_PERIPHCLK_I2C5)
2531 {
2532 /* Get the current I2C5 source */
2533 srcclk = __HAL_RCC_GET_I2C5_SOURCE();
2534
2535 if (srcclk == RCC_I2C5CLKSOURCE_PCLK1)
2536 {
2537 frequency = HAL_RCC_GetPCLK1Freq();
2538 }
2539 else if (srcclk == RCC_I2C5CLKSOURCE_SYSCLK)
2540 {
2541 frequency = HAL_RCC_GetSysClockFreq();
2542 }
2543 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C5CLKSOURCE_HSI))
2544 {
2545 frequency = HSI_VALUE;
2546 }
2547 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C5CLKSOURCE_MSIK))
2548 {
2549 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2550 }
2551 /* Clock not enabled for I2C5 */
2552 else
2553 {
2554 frequency = 0U;
2555 }
2556 }
2557 #endif /* I2C5 */
2558 #if defined (I2C6)
2559 else if (PeriphClk == RCC_PERIPHCLK_I2C6)
2560 {
2561 /* Get the current I2C6 source */
2562 srcclk = __HAL_RCC_GET_I2C6_SOURCE();
2563
2564 if (srcclk == RCC_I2C6CLKSOURCE_PCLK1)
2565 {
2566 frequency = HAL_RCC_GetPCLK1Freq();
2567 }
2568 else if (srcclk == RCC_I2C6CLKSOURCE_SYSCLK)
2569 {
2570 frequency = HAL_RCC_GetSysClockFreq();
2571 }
2572 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C6CLKSOURCE_HSI))
2573 {
2574 frequency = HSI_VALUE;
2575 }
2576 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C6CLKSOURCE_MSIK))
2577 {
2578 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2579 }
2580 /* Clock not enabled for I2C6 */
2581 else
2582 {
2583 frequency = 0U;
2584 }
2585 }
2586 #endif /* I2C6 */
2587 else if (PeriphClk == RCC_PERIPHCLK_LPTIM34)
2588 {
2589 /* Get the current LPTIM34 source */
2590 srcclk = __HAL_RCC_GET_LPTIM34_SOURCE();
2591
2592 if (srcclk == RCC_LPTIM34CLKSOURCE_MSIK)
2593 {
2594 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2595 {
2596 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2597 }
2598 else
2599 {
2600 frequency = 0U;
2601 }
2602 }
2603 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSI))
2604 {
2605 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
2606 {
2607 frequency = LSI_VALUE / 128U;
2608 }
2609 else
2610 {
2611 frequency = LSI_VALUE;
2612 }
2613 }
2614 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_HSI))
2615 {
2616 frequency = HSI_VALUE;
2617 }
2618 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSE))
2619 {
2620 frequency = LSE_VALUE;
2621 }
2622 /* Clock not enabled for LPTIM34 */
2623 else
2624 {
2625 frequency = 0U;
2626 }
2627 }
2628 else if (PeriphClk == RCC_PERIPHCLK_LPTIM1)
2629 {
2630 /* Get the current LPTIM1 source */
2631 srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
2632
2633 if (srcclk == RCC_LPTIM1CLKSOURCE_MSIK)
2634 {
2635 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2636 {
2637 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2638 }
2639 else
2640 {
2641 frequency = 0U;
2642 }
2643 }
2644 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI))
2645 {
2646 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
2647 {
2648 frequency = LSI_VALUE / 128U;
2649 }
2650 else
2651 {
2652 frequency = LSI_VALUE;
2653 }
2654 }
2655 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI))
2656 {
2657 frequency = HSI_VALUE;
2658 }
2659 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE))
2660 {
2661 frequency = LSE_VALUE;
2662 }
2663 /* Clock not enabled for LPTIM1 */
2664 else
2665 {
2666 frequency = 0U;
2667 }
2668 }
2669 else if (PeriphClk == RCC_PERIPHCLK_LPTIM2)
2670 {
2671 /* Get the current LPTIM2 source */
2672 srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
2673
2674 if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1)
2675 {
2676 frequency = HAL_RCC_GetPCLK1Freq();
2677 }
2678 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI))
2679 {
2680 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
2681 {
2682 frequency = LSI_VALUE / 128U;
2683 }
2684 else
2685 {
2686 frequency = LSI_VALUE;
2687 }
2688 }
2689 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI))
2690 {
2691 frequency = HSI_VALUE;
2692 }
2693 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE))
2694 {
2695 frequency = LSE_VALUE;
2696 }
2697 /* Clock not enabled for LPTIM2 */
2698 else
2699 {
2700 frequency = 0U;
2701 }
2702 }
2703 else if (PeriphClk == RCC_PERIPHCLK_FDCAN1)
2704 {
2705 /* Get the current FDCAN1 kernel source */
2706 srcclk = __HAL_RCC_GET_FDCAN1_SOURCE();
2707
2708 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSE))
2709 {
2710 frequency = HSE_VALUE;
2711 }
2712 else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL1) /* PLL1 ? */
2713 {
2714 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2715 frequency = pll1_clocks.PLL1_Q_Frequency;
2716 }
2717 else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL2) /* PLL2 ? */
2718 {
2719 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2720 frequency = pll2_clocks.PLL2_P_Frequency;
2721 }
2722 /* Clock not enabled for FDCAN1 */
2723 else
2724 {
2725 frequency = 0U;
2726 }
2727 }
2728 else if (PeriphClk == RCC_PERIPHCLK_SPI1)
2729 {
2730 /* Get the current SPI1 kernel source */
2731 srcclk = __HAL_RCC_GET_SPI1_SOURCE();
2732 switch (srcclk)
2733 {
2734 case RCC_SPI1CLKSOURCE_PCLK2:
2735
2736 frequency = HAL_RCC_GetPCLK2Freq();
2737 break;
2738
2739 case RCC_SPI1CLKSOURCE_SYSCLK:
2740
2741 frequency = HAL_RCC_GetSysClockFreq();
2742 break;
2743
2744 case RCC_SPI1CLKSOURCE_HSI:
2745
2746 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2747 {
2748 frequency = HSI_VALUE;
2749 }
2750 else
2751 {
2752 frequency = 0U;
2753 }
2754 break;
2755
2756 case RCC_SPI1CLKSOURCE_MSIK:
2757
2758 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2759 {
2760 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2761 }
2762 else
2763 {
2764 frequency = 0U;
2765 }
2766 break;
2767
2768 default:
2769
2770 frequency = 0U;
2771 break;
2772 }
2773 }
2774 else if (PeriphClk == RCC_PERIPHCLK_SPI2)
2775 {
2776 /* Get the current SPI2 kernel source */
2777 srcclk = __HAL_RCC_GET_SPI2_SOURCE();
2778 switch (srcclk)
2779 {
2780 case RCC_SPI2CLKSOURCE_PCLK1:
2781
2782 frequency = HAL_RCC_GetPCLK1Freq();
2783 break;
2784
2785 case RCC_SPI2CLKSOURCE_SYSCLK:
2786
2787 frequency = HAL_RCC_GetSysClockFreq();
2788 break;
2789
2790 case RCC_SPI2CLKSOURCE_HSI:
2791
2792 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2793 {
2794 frequency = HSI_VALUE;
2795 }
2796 else
2797 {
2798 frequency = 0U;
2799 }
2800 break;
2801
2802 case RCC_SPI2CLKSOURCE_MSIK:
2803
2804 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2805 {
2806 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2807 }
2808 else
2809 {
2810 frequency = 0U;
2811 }
2812 break;
2813
2814 default:
2815
2816 frequency = 0U;
2817 break;
2818 }
2819 }
2820 else if (PeriphClk == RCC_PERIPHCLK_SPI3)
2821 {
2822 /* Get the current SPI3 kernel source */
2823 srcclk = __HAL_RCC_GET_SPI3_SOURCE();
2824 switch (srcclk)
2825 {
2826 case RCC_SPI3CLKSOURCE_PCLK3:
2827
2828 frequency = HAL_RCC_GetPCLK3Freq();
2829 break;
2830
2831 case RCC_SPI3CLKSOURCE_SYSCLK:
2832
2833 frequency = HAL_RCC_GetSysClockFreq();
2834 break;
2835
2836 case RCC_SPI3CLKSOURCE_HSI:
2837
2838 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2839 {
2840 frequency = HSI_VALUE;
2841 }
2842 else
2843 {
2844 frequency = 0U;
2845 }
2846 break;
2847
2848 case RCC_SPI3CLKSOURCE_MSIK:
2849
2850 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2851 {
2852 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2853 }
2854 else
2855 {
2856 frequency = 0U;
2857 }
2858 break;
2859
2860 default:
2861
2862 frequency = 0U;
2863 break;
2864 }
2865 }
2866 else if (PeriphClk == RCC_PERIPHCLK_OSPI)
2867 {
2868 /* Get the current OSPI kernel source */
2869 srcclk = __HAL_RCC_GET_OSPI_SOURCE();
2870
2871 switch (srcclk)
2872 {
2873 case RCC_OSPICLKSOURCE_PLL2:
2874
2875 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2876 frequency = pll2_clocks.PLL2_Q_Frequency;
2877 break;
2878
2879 case RCC_OSPICLKSOURCE_PLL1:
2880
2881 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2882 frequency = pll1_clocks.PLL1_Q_Frequency;
2883 break;
2884
2885 case RCC_OSPICLKSOURCE_SYSCLK:
2886
2887 frequency = HAL_RCC_GetSysClockFreq();
2888 break;
2889
2890 case RCC_OSPICLKSOURCE_MSIK:
2891
2892 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2893 {
2894 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2895 }
2896 else
2897 {
2898 frequency = 0U;
2899 }
2900 break;
2901
2902 default:
2903
2904 frequency = 0U;
2905 break;
2906 }
2907 }
2908 #if defined(HSPI1)
2909
2910 else if (PeriphClk == RCC_PERIPHCLK_HSPI)
2911 {
2912 /* Get the current HSPI kernel source */
2913 srcclk = __HAL_RCC_GET_HSPI_SOURCE();
2914
2915 switch (srcclk)
2916 {
2917 case RCC_HSPICLKSOURCE_SYSCLK:
2918
2919 frequency = HAL_RCC_GetSysClockFreq();
2920 break;
2921
2922 case RCC_HSPICLKSOURCE_PLL1:
2923
2924 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2925 frequency = pll1_clocks.PLL1_Q_Frequency;
2926 break;
2927
2928 case RCC_HSPICLKSOURCE_PLL2:
2929
2930 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2931 frequency = pll2_clocks.PLL2_Q_Frequency;
2932 break;
2933 case RCC_HSPICLKSOURCE_PLL3:
2934
2935 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2936 frequency = pll3_clocks.PLL3_R_Frequency;
2937 break;
2938
2939 default:
2940
2941 frequency = 0U;
2942 break;
2943 }
2944 }
2945 #endif /* defined(HSPI1) */
2946 else if (PeriphClk == RCC_PERIPHCLK_DAC1)
2947 {
2948 /* Get the current DAC1 kernel source */
2949 srcclk = __HAL_RCC_GET_DAC1_SOURCE();
2950
2951 /* Check if LSE is ready and if DAC1 clock selection is LSE */
2952 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSE))
2953 {
2954 frequency = LSE_VALUE;
2955 }
2956 /* Check if LSI is ready and if DAC1 clock selection is LSI */
2957 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSI))
2958 {
2959 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
2960 {
2961 frequency = LSI_VALUE / 128U;
2962 }
2963 else
2964 {
2965 frequency = LSI_VALUE;
2966 }
2967 }
2968 /* Clock not enabled for DAC1*/
2969 else
2970 {
2971 frequency = 0U;
2972 }
2973
2974 }
2975 else if (PeriphClk == RCC_PERIPHCLK_RNG)
2976 {
2977 /* Get the current RNG kernel source */
2978 srcclk = __HAL_RCC_GET_RNG_SOURCE();
2979
2980 /* Check if HSI48 is ready and if RNG clock selection is HSI48 */
2981 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48))
2982 {
2983 frequency = HSI48_VALUE;
2984 }
2985
2986 /* Check if HSI48 is ready and if RNG clock selection is HSI48_DIV2 */
2987 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48_DIV2))
2988 {
2989 frequency = HSI48_VALUE >> 1U ;
2990 }
2991
2992 /* Check if HSI is ready and if RNG clock selection is HSI */
2993 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI))
2994 {
2995 frequency = HSI_VALUE;
2996 }
2997 /* Clock not enabled for RNG */
2998 else
2999 {
3000 frequency = 0U;
3001 }
3002 }
3003 #if defined(LTDC)
3004 else if (PeriphClk == RCC_PERIPHCLK_LTDC)
3005 {
3006 /* Get the current LTDC kernel source */
3007 srcclk = __HAL_RCC_GET_LTDC_SOURCE();
3008
3009 switch (srcclk)
3010 {
3011 case RCC_LTDCCLKSOURCE_PLL3: /* PLL3R is the clock source for LTDC */
3012
3013 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3014 frequency = pll3_clocks.PLL3_R_Frequency;
3015 break;
3016
3017 case RCC_LTDCCLKSOURCE_PLL2: /* PLL2R is the clock source for LTDC */
3018
3019 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3020 frequency = pll2_clocks.PLL2_R_Frequency;
3021 break;
3022
3023 default:
3024
3025 frequency = 0U;
3026 break;
3027 }
3028 }
3029 #endif /* defined(LTDC) */
3030
3031 #if defined(USB_OTG_HS)
3032
3033 else if (PeriphClk == RCC_PERIPHCLK_USBPHY)
3034 {
3035 /* Get the current USB_OTG_HS kernel source */
3036 srcclk = __HAL_RCC_GET_USBPHY_SOURCE();
3037
3038 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBPHYCLKSOURCE_HSE))
3039 {
3040 frequency = HSE_VALUE;
3041 }
3042 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBPHYCLKSOURCE_HSE_DIV2))
3043 {
3044 frequency = HSE_VALUE >> 1U ;
3045 }
3046 else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1) /* PLL1P */
3047 {
3048 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3049 frequency = pll1_clocks.PLL1_P_Frequency;
3050 }
3051 else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1_DIV2) /* PLL1P_DIV2 */
3052 {
3053 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3054 frequency = (pll1_clocks.PLL1_P_Frequency) / 2U;
3055 }
3056 /* Clock not enabled for USB_OTG_HS */
3057 else
3058 {
3059 frequency = 0U;
3060 }
3061 }
3062 #endif /* defined(USB_OTG_HS) */
3063
3064 else
3065 {
3066 frequency = 0;
3067 }
3068 return (frequency);
3069 }
3070
3071
3072 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
3073 * @brief Extended Clock management functions
3074 *
3075 @verbatim
3076 ===============================================================================
3077 ##### Extended clock management functions #####
3078 ===============================================================================
3079 [..]
3080 This subsection provides a set of functions allowing to control the
3081 activation or deactivation of MSI PLL-mode, PLL2, PLL3, LSE CSS,
3082 Low speed clock output and clock after wake-up from STOP mode.
3083 @endverbatim
3084 * @{
3085 */
3086
3087 /**
3088 * @brief Enable PLL2.
3089 * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
3090 * contains the configuration information for the PLL2
3091 * @retval HAL status
3092 */
HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef * PLL2Init)3093 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef *PLL2Init)
3094 {
3095 uint32_t tickstart;
3096 HAL_StatusTypeDef status = HAL_OK;
3097
3098 /* check for PLL2 Parameters used to output PLL2CLK */
3099 assert_param(IS_RCC_PLLSOURCE(PLL2Init->PLL2Source));
3100 assert_param(IS_RCC_PLLM_VALUE(PLL2Init->PLL2M));
3101 assert_param(IS_RCC_PLLN_VALUE(PLL2Init->PLL2N));
3102 assert_param(IS_RCC_PLLP_VALUE(PLL2Init->PLL2P));
3103 assert_param(IS_RCC_PLLQ_VALUE(PLL2Init->PLL2Q));
3104 assert_param(IS_RCC_PLLR_VALUE(PLL2Init->PLL2R));
3105 assert_param(IS_RCC_PLL2CLOCKOUT_VALUE(PLL2Init->PLL2ClockOut));
3106
3107 /* Disable the PLL2 */
3108 __HAL_RCC_PLL2_DISABLE();
3109
3110 /* Get Start Tick*/
3111 tickstart = HAL_GetTick();
3112
3113 /* Wait till PLL2 is ready to be updated */
3114 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
3115 {
3116 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
3117 {
3118 status = HAL_TIMEOUT;
3119 break;
3120 }
3121 }
3122
3123 if (status == HAL_OK)
3124 {
3125 /* Make sure PLL2Source is ready */
3126 status = RCCEx_PLLSource_Enable(PLL2Init->PLL2Source);
3127
3128 if (status == HAL_OK)
3129 {
3130 /* Configure the PLL2 clock source, multiplication factor N, */
3131 /* and division factors M, P, Q and R */
3132 __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2Source, PLL2Init->PLL2M, PLL2Init->PLL2N,
3133 PLL2Init->PLL2P, PLL2Init->PLL2Q, PLL2Init->PLL2R);
3134
3135 /* Disable PLL2FRACN */
3136 __HAL_RCC_PLL2FRACN_DISABLE();
3137
3138 /* Configure PLL PLL2FRACN */
3139 __HAL_RCC_PLL2FRACN_CONFIG(PLL2Init->PLL2FRACN);
3140
3141 /* Enable PLL2FRACN */
3142 __HAL_RCC_PLL2FRACN_ENABLE();
3143
3144 /* Select PLL2 input reference frequency range: VCI */
3145 __HAL_RCC_PLL2_VCIRANGE(PLL2Init->PLL2RGE);
3146
3147 /* Configure the PLL2 Clock output(s) */
3148 __HAL_RCC_PLL2CLKOUT_ENABLE(PLL2Init->PLL2ClockOut);
3149
3150 /* Enable the PLL2 again by setting PLL2ON to 1*/
3151 __HAL_RCC_PLL2_ENABLE();
3152
3153 /* Get Start Tick*/
3154 tickstart = HAL_GetTick();
3155
3156 /* Wait till PLL2 is ready */
3157 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == 0U)
3158 {
3159 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
3160 {
3161 status = HAL_TIMEOUT;
3162 break;
3163 }
3164 }
3165 }
3166 }
3167
3168 return status;
3169 }
3170
3171 /**
3172 * @brief Disable PLL2.
3173 * @retval HAL status
3174 */
HAL_RCCEx_DisablePLL2(void)3175 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
3176 {
3177 uint32_t tickstart;
3178 HAL_StatusTypeDef status = HAL_OK;
3179
3180 /* Disable the PLL2 */
3181 __HAL_RCC_PLL2_DISABLE();
3182
3183 /* Get Start Tick*/
3184 tickstart = HAL_GetTick();
3185
3186 /* Wait till PLL2 is ready */
3187 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
3188 {
3189 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
3190 {
3191 status = HAL_TIMEOUT;
3192 break;
3193 }
3194 }
3195
3196 /* To save power disable the PLL2 Source, FRACN and Clock outputs */
3197 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN | RCC_PLL2CFGR_PLL2QEN | RCC_PLL2CFGR_PLL2REN | RCC_PLL2CFGR_PLL2SRC | \
3198 RCC_PLL2CFGR_PLL2FRACEN);
3199
3200 return status;
3201 }
3202
3203 /**
3204 * @brief Enable PLL3.
3205 * @param PLL3Init pointer to an RCC_PLL3InitTypeDef structure that
3206 * contains the configuration information for the PLL3
3207 * @retval HAL status
3208 */
HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef * PLL3Init)3209 HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef *PLL3Init)
3210 {
3211 uint32_t tickstart;
3212 HAL_StatusTypeDef status = HAL_OK;
3213
3214 /* check for PLL3 Parameters used to output PLL3CLK */
3215 assert_param(IS_RCC_PLLSOURCE(PLL3Init->PLL3Source));
3216 assert_param(IS_RCC_PLLM_VALUE(PLL3Init->PLL3M));
3217 assert_param(IS_RCC_PLLN_VALUE(PLL3Init->PLL3N));
3218 assert_param(IS_RCC_PLLP_VALUE(PLL3Init->PLL3P));
3219 assert_param(IS_RCC_PLL3CLOCKOUT_VALUE(PLL3Init->PLL3ClockOut));
3220
3221 /* Disable the PLL3 */
3222 __HAL_RCC_PLL3_DISABLE();
3223
3224 /* Get Start Tick*/
3225 tickstart = HAL_GetTick();
3226
3227 /* Wait till PLL3 is ready to be updated */
3228 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
3229 {
3230 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
3231 {
3232 status = HAL_TIMEOUT;
3233 break;
3234 }
3235 }
3236
3237 if (status == HAL_OK)
3238 {
3239 /* Make sure PLL3Source is ready */
3240 status = RCCEx_PLLSource_Enable(PLL3Init->PLL3Source);
3241
3242 if (status == HAL_OK)
3243 {
3244 /* Configure the PLL3 clock source, multiplication factor N, */
3245 /* and division factors M and P */
3246 __HAL_RCC_PLL3_CONFIG(PLL3Init->PLL3Source, PLL3Init->PLL3M, PLL3Init->PLL3N, PLL3Init->PLL3P, PLL3Init->PLL3Q, \
3247 PLL3Init->PLL3R);
3248
3249 /* Disable PLL3FRACN . */
3250 __HAL_RCC_PLL3FRACN_DISABLE();
3251
3252 /* Configure PLL PLL3FRACN */
3253 __HAL_RCC_PLL3FRACN_CONFIG(PLL3Init->PLL3FRACN);
3254
3255 /* Enable PLL3FRACN . */
3256 __HAL_RCC_PLL3FRACN_ENABLE();
3257
3258 /* Select PLL3 input reference frequency range: VCI */
3259 __HAL_RCC_PLL3_VCIRANGE(PLL3Init->PLL3RGE);
3260
3261 /* Configure the PLL3 Clock output(s) */
3262 __HAL_RCC_PLL3CLKOUT_ENABLE(PLL3Init->PLL3ClockOut);
3263
3264 /* Enable the PLL3 again by setting PLL3ON to 1*/
3265 __HAL_RCC_PLL3_ENABLE();
3266
3267 /* Get Start Tick*/
3268 tickstart = HAL_GetTick();
3269
3270 /* Wait till PLL3 is ready */
3271 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == 0U)
3272 {
3273 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
3274 {
3275 status = HAL_TIMEOUT;
3276 break;
3277 }
3278 }
3279 }
3280 }
3281
3282 return status;
3283 }
3284
3285 /**
3286 * @brief Disable PLL3.
3287 * @retval HAL status
3288 */
HAL_RCCEx_DisablePLL3(void)3289 HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void)
3290 {
3291 uint32_t tickstart;
3292 HAL_StatusTypeDef status = HAL_OK;
3293
3294 /* Disable the PLL3 */
3295 __HAL_RCC_PLL3_DISABLE();
3296
3297 /* Get Start Tick*/
3298 tickstart = HAL_GetTick();
3299
3300 /* Wait till PLL3 is ready */
3301 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
3302 {
3303 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
3304 {
3305 status = HAL_TIMEOUT;
3306 break;
3307 }
3308 }
3309
3310 /* To save power disable the PLL3 Source and Clock outputs */
3311 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN | RCC_PLL3CFGR_PLL3QEN | RCC_PLL3CFGR_PLL3REN | RCC_PLL3CFGR_PLL3SRC | \
3312 RCC_PLL3CFGR_PLL3FRACEN);
3313
3314 return status;
3315 }
3316
3317 /**
3318 * @brief Select which MSI output clock uses the PLL mode.
3319 * @note Prior to disable PLL-mode (MSIPLLEN = 0) before call HAL_RCCEx_EnableMSIPLLModeSelection.
3320 * @note The MSI kernel clock output uses the same oscillator source than the MSI system
3321 * clock output, then the PLL mode is applied to the both clocks outputs.
3322 * @param MSIPLLModeSelection specifies which MSI output clock uses the PLL mode.
3323 * This parameter can be one of the following values:
3324 * @arg @ref RCC_MSISPLL_MODE_SEL PLL mode applied to MSIS (MSI system) clock output
3325 * @arg @ref RCC_MSIKPLL_MODE_SEL PLL mode applied to MSIK (MSI kernel) clock output
3326 * @retval HAL status
3327 */
HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelection)3328 HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelection)
3329 {
3330 HAL_StatusTypeDef status = HAL_ERROR;
3331
3332 assert_param(IS_RCC_MSIPLLMODE_SELECT(MSIPLLModeSelection));
3333 if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == 0U)
3334 {
3335 /* This bit is used only if PLL mode is disabled (MSIPLLEN = 0) */
3336 if (MSIPLLModeSelection == RCC_MSISPLL_MODE_SEL)
3337 {
3338 SET_BIT(RCC->CR, RCC_CR_MSIPLLSEL);
3339 }
3340 else
3341 {
3342 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLSEL);
3343 }
3344 status = HAL_OK;
3345 }
3346
3347 return status;
3348 }
3349
3350 /**
3351 * @brief Enable the fast PLL mode start-up of the MSI clock
3352 * @note Prior to enable PLL-mode (MSIPLLEN = 1) before call HAL_RCCEx_EnableMSIPLLFastStartup.
3353 * @note The fast start-up feature is not active the first time the PLL mode is selected. The
3354 * fast start-up is active when the MSI in PLL mode returns from switch off.
3355 * @retval HAL status
3356 */
HAL_RCCEx_EnableMSIPLLFastStartup(void)3357 HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLFastStartup(void)
3358 {
3359 HAL_StatusTypeDef status = HAL_ERROR;
3360
3361 if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN)
3362 {
3363 /* This bit is used only if PLL mode is selected (MSIPLLEN = 1) */
3364 SET_BIT(RCC->CR, RCC_CR_MSIPLLFAST);
3365 status = HAL_OK;
3366 }
3367
3368 return status;
3369 }
3370
3371 /**
3372 * @brief Disable the fast PLL mode start-up of the MSI clock
3373 * @note the MSI fast startup mode disabled only when PLL-mode is enabled
3374 * @retval HAL status
3375 */
HAL_RCCEx_DisableMSIPLLFastStartup(void)3376 HAL_StatusTypeDef HAL_RCCEx_DisableMSIPLLFastStartup(void)
3377 {
3378 HAL_StatusTypeDef status = HAL_ERROR;
3379
3380 if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN)
3381 {
3382 /* This bit is used only if PLL mode is selected (MSIPLLEN = 1) */
3383 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLFAST);
3384 status = HAL_OK;
3385 }
3386 return status;
3387 }
3388
3389 /**
3390 * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
3391 * @param WakeUpClk Wakeup clock
3392 * This parameter can be one of the following values:
3393 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection
3394 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection
3395 * @note This function shall not be called after the Clock Security System on HSE has been
3396 * enabled.
3397 * @retval None
3398 */
HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)3399 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
3400 {
3401 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
3402
3403 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
3404 }
3405
3406 /**
3407 * @brief Configure the oscillator Kernel clock source for wakeup from Stop
3408 * @param WakeUpClk: Kernel Wakeup clock
3409 * This parameter can be one of the following values:
3410 * @arg RCC_STOP_KERWAKEUPCLOCK_MSI: MSI oscillator selection
3411 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
3412 * @retval None
3413 */
HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)3414 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
3415 {
3416 assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
3417
3418 __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
3419 }
3420
3421 /**
3422 * @brief Configure the MSI range after standby mode.
3423 * @note After Standby its frequency can be selected between 3 possible values (1, 3.072 or 4 MHz).
3424 * @param MSIRange MSI range
3425 * This parameter can be one of the following values:
3426 * @arg @ref RCC_MSIRANGE_4 Range 4 around 4 MHz (reset value)
3427 * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz
3428 * @arg @ref RCC_MSIRANGE_6 Range 6 around 1.33 MHz
3429 * @arg @ref RCC_MSIRANGE_7 Range 7 around 1 MHz
3430 * @arg @ref RCC_MSIRANGE_8 Range 8 around 3.072 MHz
3431 * @retval None
3432 */
HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)3433 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)
3434 {
3435 assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange));
3436
3437 __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange);
3438 }
3439
3440 /**
3441 * @brief Configure the MSIK range after standby mode.
3442 * @note After Standby its frequency can be selected between 5 possible values (1, 1.33, 2, 3.072 or 4 MHz).
3443 * @param MSIKRange MSIK range
3444 * This parameter can be one of the following values:
3445 * @arg @ref RCC_MSIKRANGE_4 Range 4 around 4 MHz (reset value)
3446 * @arg @ref RCC_MSIKRANGE_5 Range 5 around 2 MHz
3447 * @arg @ref RCC_MSIKRANGE_6 Range 6 around 1.33 MHz
3448 * @arg @ref RCC_MSIKRANGE_7 Range 7 around 1 MHz
3449 * @arg @ref RCC_MSIKRANGE_8 Range 8 around 3.072 MHz
3450 * @retval None
3451 */
HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange)3452 void HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange)
3453 {
3454 assert_param(IS_RCC_MSIK_STANDBY_CLOCK_RANGE(MSIKRange));
3455
3456 __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(MSIKRange);
3457 }
3458
3459 /**
3460 * @brief Enable the LSE Clock Security System.
3461 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
3462 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
3463 * clock with HAL_RCCEx_PeriphCLKConfig().
3464 * @retval None
3465 */
HAL_RCCEx_EnableLSECSS(void)3466 void HAL_RCCEx_EnableLSECSS(void)
3467 {
3468 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
3469 }
3470
3471 /**
3472 * @brief Disable the LSE Clock Security System.
3473 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
3474 * @retval None
3475 */
HAL_RCCEx_DisableLSECSS(void)3476 void HAL_RCCEx_DisableLSECSS(void)
3477 {
3478 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
3479 }
3480
3481 /**
3482 * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
3483 * @note LSE Clock Security System Interrupt is mapped on EXTI line
3484 * Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
3485 * @retval None
3486 */
HAL_RCCEx_EnableLSECSS_IT(void)3487 void HAL_RCCEx_EnableLSECSS_IT(void)
3488 {
3489 /* Enable LSE CSS */
3490 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
3491
3492 /* Enable IT on LSECSS EXTI Line */
3493 SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS);
3494 /* Enable the RCC LSECSS EXTI Interrupt Rising Edge */
3495 SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS);
3496 }
3497
3498 /**
3499 * @brief Handle the RCC LSE Clock Security System interrupt request.
3500 * @note LSECSS EXTI is not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
3501 * @retval None
3502 */
HAL_RCCEx_LSECSS_IRQHandler(void)3503 void HAL_RCCEx_LSECSS_IRQHandler(void)
3504 {
3505 uint32_t falling_edge_flag;
3506 uint32_t rising_edge_flag;
3507
3508 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) != 0U)
3509 {
3510 /* Read Falling Edge flag on LSECSS EXTI interrupt */
3511 falling_edge_flag = READ_BIT(EXTI->FPR1, RCC_EXTI_LINE_LSECSS);
3512
3513 /* Read Rising Edge flag on LSECSS EXTI interrupt */
3514 rising_edge_flag = READ_BIT(EXTI->RPR1, RCC_EXTI_LINE_LSECSS);
3515
3516 /* Check Rising/falling Edge flag on LSECSS EXTI interrupt */
3517 if ((falling_edge_flag == RCC_EXTI_LINE_LSECSS) || \
3518 (rising_edge_flag == RCC_EXTI_LINE_LSECSS))
3519 {
3520 if (rising_edge_flag == RCC_EXTI_LINE_LSECSS)
3521 {
3522 /* Clear the RCC LSECSS EXTI Rising Edge flag */
3523 WRITE_REG(EXTI->RPR1, RCC_EXTI_LINE_LSECSS);
3524 }
3525 if (falling_edge_flag == RCC_EXTI_LINE_LSECSS)
3526 {
3527 /* Clear the RCC LSECSS EXTI Falling Edge flag */
3528 WRITE_REG(EXTI->FPR1, RCC_EXTI_LINE_LSECSS);
3529 }
3530 }
3531 /* RCC LSECSS interrupt user callback */
3532 HAL_RCCEx_LSECSS_Callback();
3533 }
3534 }
3535
3536 /**
3537 * @brief RCCEx LSE Clock Security System interrupt callback.
3538 * @retval none
3539 */
HAL_RCCEx_LSECSS_Callback(void)3540 __weak void HAL_RCCEx_LSECSS_Callback(void)
3541 {
3542 /* NOTE : This function should not be modified, when the callback is needed,
3543 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
3544 */
3545 }
3546
3547 /**
3548 * @brief Enable the MSI PLL Unlock Interrupt & corresponding EXTI line.
3549 * @note MSI PLL Unlock Interrupt is mapped on EXTI line
3550 * Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
3551 * @retval None
3552 */
HAL_RCCEx_EnableMSIPLLUNLCK_IT(void)3553 void HAL_RCCEx_EnableMSIPLLUNLCK_IT(void)
3554 {
3555 /* Enable IT on MSI PLL Unlock EXTI Line */
3556 SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_MSIPLLUNLCK);
3557 /* Enable the RCC MSI PLL UNLOCK EXTI Interrupt Rising Edge */
3558 SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_MSIPLLUNLCK);
3559 }
3560
3561 /**
3562 * @brief Handle the RCC MSI PLL Unlock interrupt request.
3563 * @note Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
3564 * @retval None
3565 */
HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void)3566 void HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void)
3567 {
3568 uint32_t rising_edge_flag = READ_BIT(EXTI->RPR1, RCC_EXTI_LINE_MSIPLLUNLCK);
3569 uint32_t falling_edge_flag = READ_BIT(EXTI->FPR1, RCC_EXTI_LINE_MSIPLLUNLCK);
3570
3571 /* Check Rising/falling Edge flag on MSI PLL UNLOCK EXTI interrupt */
3572 if ((rising_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) || \
3573 (falling_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK))
3574 {
3575 if (rising_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK)
3576 {
3577 /* Clear the RCC MSI PLL UNLOCK EXTI Rising Edge flag */
3578 WRITE_REG(EXTI->RPR1, RCC_EXTI_LINE_MSIPLLUNLCK);
3579 }
3580 if (falling_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK)
3581 {
3582 /* Clear the RCC MSI PLL UNLOCK EXTI Falling Edge flag */
3583 WRITE_REG(EXTI->FPR1, RCC_EXTI_LINE_MSIPLLUNLCK);
3584 }
3585 /* RCC MSI PLL Unlock interrupt user callback */
3586 HAL_RCCEx_MSIPLLUNLCK_Callback();
3587 }
3588 }
3589
3590 /**
3591 * @brief RCCEx RCC MSI PLL Unlock interrupt callback.
3592 * @note Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
3593 * @retval none
3594 */
HAL_RCCEx_MSIPLLUNLCK_Callback(void)3595 __weak void HAL_RCCEx_MSIPLLUNLCK_Callback(void)
3596 {
3597 /* NOTE : This function should not be modified, when the callback is needed,
3598 the @ref HAL_RCCEx_MSIPLLUNLCK_Callback should be implemented in the user file
3599 */
3600 }
3601
3602 /**
3603 * @brief Select the Low Speed clock source to output on LSCO pin (PA2).
3604 * @param LSCOSource specifies the Low Speed clock source to output.
3605 * This parameter can be one of the following values:
3606 * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
3607 * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
3608 * @retval None
3609 */
HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)3610 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
3611 {
3612 FlagStatus pwrclkchanged = RESET;
3613 FlagStatus backupchanged = RESET;
3614
3615 /* Check the parameters */
3616 assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
3617
3618 /* Update LSCOSEL clock source in Backup Domain control register */
3619 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
3620 {
3621 __HAL_RCC_PWR_CLK_ENABLE();
3622 pwrclkchanged = SET;
3623 }
3624 if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
3625 {
3626 HAL_PWR_EnableBkUpAccess();
3627 backupchanged = SET;
3628 }
3629
3630 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
3631
3632 if (backupchanged == SET)
3633 {
3634 HAL_PWR_DisableBkUpAccess();
3635 }
3636 if (pwrclkchanged == SET)
3637 {
3638 __HAL_RCC_PWR_CLK_DISABLE();
3639 }
3640 }
3641
3642 /**
3643 * @brief Disable the Low Speed clock output.
3644 * @retval None
3645 */
HAL_RCCEx_DisableLSCO(void)3646 void HAL_RCCEx_DisableLSCO(void)
3647 {
3648 FlagStatus pwrclkchanged = RESET;
3649 FlagStatus backupchanged = RESET;
3650
3651 /* Update LSCOEN bit in Backup Domain control register */
3652 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
3653 {
3654 __HAL_RCC_PWR_CLK_ENABLE();
3655 pwrclkchanged = SET;
3656 }
3657 if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
3658 {
3659 /* Enable access to the backup domain */
3660 HAL_PWR_EnableBkUpAccess();
3661 backupchanged = SET;
3662 }
3663
3664 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
3665
3666 /* Restore previous configuration */
3667 if (backupchanged == SET)
3668 {
3669 /* Disable access to the backup domain */
3670 HAL_PWR_DisableBkUpAccess();
3671 }
3672 if (pwrclkchanged == SET)
3673 {
3674 __HAL_RCC_PWR_CLK_DISABLE();
3675 }
3676 }
3677
3678 /**
3679 * @brief Enable the PLL-mode of the MSI.
3680 * @note Prior to enable the PLL-mode of the MSI for automatic hardware
3681 * calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
3682 * @retval None
3683 */
HAL_RCCEx_EnableMSIPLLMode(void)3684 void HAL_RCCEx_EnableMSIPLLMode(void)
3685 {
3686 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
3687 }
3688
3689 /**
3690 * @brief Disable the PLL-mode of the MSI.
3691 * @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.
3692 * @retval None
3693 */
HAL_RCCEx_DisableMSIPLLMode(void)3694 void HAL_RCCEx_DisableMSIPLLMode(void)
3695 {
3696 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
3697 }
3698 /**
3699 * @}
3700 */
3701
3702 #if defined(CRS)
3703
3704 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
3705 * @brief Extended Clock Recovery System Control functions
3706 *
3707 @verbatim
3708 ===============================================================================
3709 ##### Extended Clock Recovery System Control functions #####
3710 ===============================================================================
3711 [..]
3712 For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
3713
3714 (#) In System clock config, HSI48 needs to be enabled
3715
3716 (#) Enable CRS clock in IP MSP init which will use CRS functions
3717
3718 (#) Call CRS functions as follows:
3719 (##) Prepare synchronization configuration necessary for HSI48 calibration
3720 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
3721 and also HSI48 oscillator smooth trimming.
3722 (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
3723 directly reload value with target and synchronization frequencies values
3724 (##) Call function HAL_RCCEx_CRSConfig which
3725 (+++) Resets CRS registers to their default values.
3726 (+++) Configures CRS registers with synchronization configuration
3727 (+++) Enables automatic calibration and frequency error counter feature
3728 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
3729 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
3730 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
3731 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
3732 should be used as SYNC signal.
3733
3734 (##) A polling function is provided to wait for complete synchronization
3735 (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
3736 (+++) According to CRS status, user can decide to adjust again the calibration or continue
3737 application if synchronization is OK
3738
3739 (#) User can retrieve information related to synchronization in calling function
3740 HAL_RCCEx_CRSGetSynchronizationInfo()
3741
3742 (#) Regarding synchronization status and synchronization information, user can try a new calibration
3743 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
3744 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
3745 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
3746 incremented), while when it is detected during the upcounting phase it means that the actual frequency
3747 is higher (and that the TRIM value should be decremented).
3748
3749 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
3750 through CRS Handler (CRS_IRQn/CRS_IRQHandler)
3751 (++) Call function HAL_RCCEx_CRSConfig()
3752 (++) Enable CRS_IRQn (thanks to NVIC functions)
3753 (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
3754 (++) Implement CRS status management in the following user callbacks called from
3755 HAL_RCCEx_CRS_IRQHandler():
3756 (+++) HAL_RCCEx_CRS_SyncOkCallback()
3757 (+++) HAL_RCCEx_CRS_SyncWarnCallback()
3758 (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
3759 (+++) HAL_RCCEx_CRS_ErrorCallback()
3760
3761 (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
3762 This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
3763
3764 @endverbatim
3765 * @{
3766 */
3767
3768 /**
3769 * @brief Start automatic synchronization for polling mode
3770 * @param pInit Pointer on RCC_CRSInitTypeDef structure
3771 * @retval None
3772 */
HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef * const pInit)3773 void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *const pInit)
3774 {
3775 uint32_t value;
3776
3777 /* Check the parameters */
3778 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
3779 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
3780 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
3781 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
3782 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
3783 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
3784
3785 /* CONFIGURATION */
3786
3787 /* Before configuration, reset CRS registers to their default values*/
3788 __HAL_RCC_CRS_FORCE_RESET();
3789 __HAL_RCC_CRS_RELEASE_RESET();
3790
3791 /* Set the SYNCDIV[2:0] bits according to Prescaler value */
3792 /* Set the SYNCSRC[1:0] bits according to Source value */
3793 /* Set the SYNCSPOL bit according to Polarity value */
3794 value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
3795 /* Set the RELOAD[15:0] bits according to ReloadValue value */
3796 value |= pInit->ReloadValue;
3797 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
3798 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
3799 WRITE_REG(CRS->CFGR, value);
3800
3801 /* Adjust HSI48 oscillator smooth trimming */
3802 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
3803 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
3804
3805 /* START AUTOMATIC SYNCHRONIZATION*/
3806
3807 /* Enable Automatic trimming & Frequency error counter */
3808 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
3809 }
3810
3811 /**
3812 * @brief Generate the software synchronization event
3813 * @retval None
3814 */
HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)3815 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
3816 {
3817 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
3818 }
3819
3820 /**
3821 * @brief Return synchronization info
3822 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
3823 * @retval None
3824 */
HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef * pSynchroInfo)3825 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
3826 {
3827 /* Check the parameter */
3828 assert_param(pSynchroInfo != (void *) NULL);
3829
3830 /* Get the reload value */
3831 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
3832
3833 /* Get HSI48 oscillator smooth trimming */
3834 pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
3835
3836 /* Get Frequency error capture */
3837 pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
3838
3839 /* Get Frequency error direction */
3840 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
3841 }
3842
3843 /**
3844 * @brief Wait for CRS Synchronization status.
3845 * @param Timeout Duration of the timeout
3846 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
3847 * frequency.
3848 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
3849 * @retval Combination of Synchronization status
3850 * This parameter can be a combination of the following values:
3851 * @arg @ref RCC_CRS_TIMEOUT
3852 * @arg @ref RCC_CRS_SYNCOK
3853 * @arg @ref RCC_CRS_SYNCWARN
3854 * @arg @ref RCC_CRS_SYNCERR
3855 * @arg @ref RCC_CRS_SYNCMISS
3856 * @arg @ref RCC_CRS_TRIMOVF
3857 */
HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)3858 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
3859 {
3860 uint32_t crsstatus = RCC_CRS_NONE;
3861 uint32_t tickstart;
3862
3863 /* Get timeout */
3864 tickstart = HAL_GetTick();
3865
3866 /* Wait for CRS flag or timeout detection */
3867 do
3868 {
3869 if (Timeout != HAL_MAX_DELAY)
3870 {
3871 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3872 {
3873 crsstatus = RCC_CRS_TIMEOUT;
3874 }
3875 }
3876 /* Check CRS SYNCOK flag */
3877 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
3878 {
3879 /* CRS SYNC event OK */
3880 crsstatus |= RCC_CRS_SYNCOK;
3881
3882 /* Clear CRS SYNC event OK bit */
3883 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
3884 }
3885
3886 /* Check CRS SYNCWARN flag */
3887 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
3888 {
3889 /* CRS SYNC warning */
3890 crsstatus |= RCC_CRS_SYNCWARN;
3891
3892 /* Clear CRS SYNCWARN bit */
3893 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
3894 }
3895
3896 /* Check CRS TRIM overflow flag */
3897 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
3898 {
3899 /* CRS SYNC Error */
3900 crsstatus |= RCC_CRS_TRIMOVF;
3901
3902 /* Clear CRS Error bit */
3903 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
3904 }
3905
3906 /* Check CRS Error flag */
3907 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
3908 {
3909 /* CRS SYNC Error */
3910 crsstatus |= RCC_CRS_SYNCERR;
3911
3912 /* Clear CRS Error bit */
3913 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
3914 }
3915
3916 /* Check CRS SYNC Missed flag */
3917 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
3918 {
3919 /* CRS SYNC Missed */
3920 crsstatus |= RCC_CRS_SYNCMISS;
3921
3922 /* Clear CRS SYNC Missed bit */
3923 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
3924 }
3925
3926 /* Check CRS Expected SYNC flag */
3927 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
3928 {
3929 /* frequency error counter reached a zero value */
3930 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
3931 }
3932 } while (RCC_CRS_NONE == crsstatus);
3933
3934 return crsstatus;
3935 }
3936
3937 /**
3938 * @brief Handle the Clock Recovery System interrupt request.
3939 * @retval None
3940 */
HAL_RCCEx_CRS_IRQHandler(void)3941 void HAL_RCCEx_CRS_IRQHandler(void)
3942 {
3943 uint32_t crserror = RCC_CRS_NONE;
3944 /* Get current IT flags and IT sources values */
3945 uint32_t itflags = READ_REG(CRS->ISR);
3946 uint32_t itsources = READ_REG(CRS->CR);
3947
3948 /* Check CRS SYNCOK flag */
3949 if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
3950 {
3951 /* Clear CRS SYNC event OK flag */
3952 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
3953
3954 /* user callback */
3955 HAL_RCCEx_CRS_SyncOkCallback();
3956 }
3957 /* Check CRS SYNCWARN flag */
3958 else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
3959 {
3960 /* Clear CRS SYNCWARN flag */
3961 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
3962
3963 /* user callback */
3964 HAL_RCCEx_CRS_SyncWarnCallback();
3965 }
3966 /* Check CRS Expected SYNC flag */
3967 else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
3968 {
3969 /* frequency error counter reached a zero value */
3970 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
3971
3972 /* user callback */
3973 HAL_RCCEx_CRS_ExpectedSyncCallback();
3974 }
3975 /* Check CRS Error flags */
3976 else
3977 {
3978 if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
3979 {
3980 if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
3981 {
3982 crserror |= RCC_CRS_SYNCERR;
3983 }
3984 if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
3985 {
3986 crserror |= RCC_CRS_SYNCMISS;
3987 }
3988 if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
3989 {
3990 crserror |= RCC_CRS_TRIMOVF;
3991 }
3992
3993 /* Clear CRS Error flags */
3994 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
3995
3996 /* user error callback */
3997 HAL_RCCEx_CRS_ErrorCallback(crserror);
3998 }
3999 }
4000 }
4001
4002 /**
4003 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
4004 * @retval none
4005 */
HAL_RCCEx_CRS_SyncOkCallback(void)4006 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
4007 {
4008 /* NOTE : This function should not be modified, when the callback is needed,
4009 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
4010 */
4011 }
4012
4013 /**
4014 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
4015 * @retval none
4016 */
HAL_RCCEx_CRS_SyncWarnCallback(void)4017 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
4018 {
4019 /* NOTE : This function should not be modified, when the callback is needed,
4020 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
4021 */
4022 }
4023
4024 /**
4025 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
4026 * @retval none
4027 */
HAL_RCCEx_CRS_ExpectedSyncCallback(void)4028 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
4029 {
4030 /* NOTE : This function should not be modified, when the callback is needed,
4031 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
4032 */
4033 }
4034
4035 /**
4036 * @brief RCCEx Clock Recovery System Error interrupt callback.
4037 * @param Error Combination of Error status.
4038 * This parameter can be a combination of the following values:
4039 * @arg @ref RCC_CRS_SYNCERR
4040 * @arg @ref RCC_CRS_SYNCMISS
4041 * @arg @ref RCC_CRS_TRIMOVF
4042 * @retval none
4043 */
HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)4044 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
4045 {
4046 /* Prevent unused argument(s) compilation warning */
4047 UNUSED(Error);
4048
4049 /* NOTE : This function should not be modified, when the callback is needed,
4050 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
4051 */
4052 }
4053
4054 /**
4055 * @}
4056 */
4057
4058 #endif /* CRS */
4059
4060 /**
4061 * @}
4062 */
4063
4064 /** @addtogroup RCCEx_Private_Functions
4065 * @{
4066 */
4067 /**
4068 * @brief Configure the PLL 1 source clock.
4069 * @param PllSource PLL1 source clock it can be :
4070 * RCC_PLLSOURCE_NONE
4071 * RCC_PLLSOURCE_MSI
4072 * RCC_PLLSOURCE_HSI
4073 * RCC_PLLSOURCE_HSE
4074 *
4075 * @retval HAL status
4076 */
RCCEx_PLLSource_Enable(uint32_t PllSource)4077 static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource)
4078 {
4079 uint32_t tickstart;
4080 HAL_StatusTypeDef status = HAL_OK;
4081
4082 switch (PllSource)
4083 {
4084 case RCC_PLLSOURCE_MSI:
4085 /* Check whether MSI in not ready and enable it */
4086 if (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
4087 {
4088 /* Enable the Internal Multi Speed oscillator (MSI). */
4089 __HAL_RCC_MSI_ENABLE();
4090
4091 /* Get timeout */
4092 tickstart = HAL_GetTick();
4093
4094 /* Wait till MSI is ready */
4095 while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
4096 {
4097 if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
4098 {
4099 status = HAL_TIMEOUT;
4100 break;
4101 }
4102 }
4103 }
4104 break;
4105
4106 case RCC_PLLSOURCE_HSI:
4107 /* Check whether HSI in not ready and enable it */
4108 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
4109 {
4110 /* Enable the Internal High Speed oscillator (HSI) */
4111 __HAL_RCC_HSI_ENABLE();
4112
4113 /* Get timeout */
4114 tickstart = HAL_GetTick();
4115
4116 /* Wait till MSI is ready */
4117 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
4118 {
4119 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
4120 {
4121 status = HAL_TIMEOUT;
4122 break;
4123 }
4124 }
4125 }
4126 break;
4127
4128 case RCC_PLLSOURCE_HSE:
4129 /* Check whether HSE in not ready and enable it */
4130 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
4131 {
4132 /* Enable the External High Speed oscillator (HSE) */
4133 SET_BIT(RCC->CR, RCC_CR_HSEON);
4134
4135 /* Get Start Tick*/
4136 tickstart = HAL_GetTick();
4137
4138 /* Wait till HSE is ready */
4139 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
4140 {
4141 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
4142 {
4143 status = HAL_TIMEOUT;
4144 break;
4145 }
4146 }
4147 }
4148 break;
4149
4150 default:
4151 status = HAL_ERROR;
4152 break;
4153 }
4154
4155 return status;
4156 }
4157
4158 /**
4159 * @brief Configure the PLL2 VCI ranges, multiplication and division factors and enable it
4160 * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that
4161 * contains the configuration parameters as well as VCI clock ranges.
4162 * @note PLL2 is temporary disabled to apply new parameters
4163 *
4164 * @retval HAL status
4165 */
RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef * pll2)4166 static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2)
4167 {
4168
4169 uint32_t tickstart;
4170 assert_param(IS_RCC_PLLSOURCE(pll2->PLL2Source));
4171 assert_param(IS_RCC_PLLM_VALUE(pll2->PLL2M));
4172 assert_param(IS_RCC_PLLN_VALUE(pll2->PLL2N));
4173 assert_param(IS_RCC_PLLP_VALUE(pll2->PLL2P));
4174 assert_param(IS_RCC_PLLQ_VALUE(pll2->PLL2Q));
4175 assert_param(IS_RCC_PLLR_VALUE(pll2->PLL2R));
4176
4177 /* Disable PLL2 */
4178 __HAL_RCC_PLL2_DISABLE();
4179
4180 /* Get Start Tick*/
4181 tickstart = HAL_GetTick();
4182
4183 /* Wait till PLL is ready */
4184 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
4185 {
4186 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
4187 {
4188 return HAL_TIMEOUT;
4189 }
4190 }
4191
4192 /* Configure PLL2 multiplication and division factors */
4193 __HAL_RCC_PLL2_CONFIG(pll2->PLL2Source,
4194 pll2->PLL2M,
4195 pll2->PLL2N,
4196 pll2->PLL2P,
4197 pll2->PLL2Q,
4198 pll2->PLL2R);
4199
4200 /* Select PLL2 input reference frequency range: VCI */
4201 __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE);
4202
4203 /* Configure the PLL2 Clock output(s) */
4204 __HAL_RCC_PLL2CLKOUT_ENABLE(pll2->PLL2ClockOut);
4205
4206 /* Disable PLL2FRACN */
4207 __HAL_RCC_PLL2FRACN_DISABLE();
4208
4209 /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
4210 __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
4211
4212 /* Enable PLL2FRACN */
4213 __HAL_RCC_PLL2FRACN_ENABLE();
4214
4215 /* Enable PLL2 */
4216 __HAL_RCC_PLL2_ENABLE();
4217
4218 /* Get Start Tick*/
4219 tickstart = HAL_GetTick();
4220
4221 /* Wait till PLL2 is ready */
4222 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
4223 {
4224 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
4225 {
4226 return HAL_TIMEOUT;
4227 }
4228 }
4229 return HAL_OK;
4230
4231 }
4232
4233 /**
4234 * @brief Configure the PLL3 VCI ranges, multiplication and division factors and enable it
4235 * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that
4236 * contains the configuration parameters as well as VCI clock ranges.
4237 * @note PLL3 is temporary disabled to apply new parameters
4238 * @retval HAL status
4239 */
RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef * pll3)4240 static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3)
4241 {
4242 uint32_t tickstart;
4243 assert_param(IS_RCC_PLLSOURCE(pll3->PLL3Source));
4244 assert_param(IS_RCC_PLLM_VALUE(pll3->PLL3M));
4245 assert_param(IS_RCC_PLLN_VALUE(pll3->PLL3N));
4246 assert_param(IS_RCC_PLLP_VALUE(pll3->PLL3P));
4247 assert_param(IS_RCC_PLLQ_VALUE(pll3->PLL3Q));
4248 assert_param(IS_RCC_PLLR_VALUE(pll3->PLL3R));
4249
4250 /* Disable PLL3 */
4251 __HAL_RCC_PLL3_DISABLE();
4252
4253 /* Get Start Tick*/
4254 tickstart = HAL_GetTick();
4255
4256 /* Wait till PLL is ready */
4257 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
4258 {
4259 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
4260 {
4261 return HAL_TIMEOUT;
4262 }
4263 }
4264
4265 /* Configure PLL3 multiplication and division factors */
4266 __HAL_RCC_PLL3_CONFIG(pll3->PLL3Source,
4267 pll3->PLL3M,
4268 pll3->PLL3N,
4269 pll3->PLL3P,
4270 pll3->PLL3Q,
4271 pll3->PLL3R);
4272
4273 /* Select PLL3 input reference frequency range: VCI */
4274 __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE);
4275
4276 /* Configure the PLL3 Clock output(s) */
4277 __HAL_RCC_PLL3CLKOUT_ENABLE(pll3->PLL3ClockOut);
4278
4279 /* Disable PLL3FRACN */
4280 __HAL_RCC_PLL3FRACN_DISABLE();
4281
4282 /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
4283 __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
4284
4285 /* Enable PLL3FRACN */
4286 __HAL_RCC_PLL3FRACN_ENABLE();
4287
4288 /* Enable PLL3 */
4289 __HAL_RCC_PLL3_ENABLE();
4290
4291 /* Get Start Tick*/
4292 tickstart = HAL_GetTick();
4293
4294 /* Wait till PLL3 is ready */
4295 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
4296 {
4297 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
4298 {
4299 return HAL_TIMEOUT;
4300 }
4301 }
4302 return HAL_OK;
4303 }
4304
4305 /**
4306 * @}
4307 */
4308
4309 #endif /* HAL_RCC_MODULE_ENABLED */
4310 /**
4311 * @}
4312 */
4313
4314 /**
4315 * @}
4316 */
4317
4318 /**
4319 * @}
4320 */
4321
4322
