1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_dac.c
4 * @author MCD Application Team
5 * @brief DAC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Digital to Analog Converter (DAC) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 *
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2021 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### DAC Peripheral features #####
28 ==============================================================================
29 [..]
30 *** DAC Channels ***
31 ====================
32 [..]
33 STM32U5 devices integrate two 12-bit Digital Analog Converters
34
35 The 2 converters (i.e. channel1 & channel2)
36 can be used independently or simultaneously (dual mode):
37 (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
38 peripherals (ex. ADC).
39 (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
40 peripherals (ex. ADC).
41
42 *** DAC Triggers ***
43 ====================
44 [..]
45 Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
46 and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
47 [..]
48 Digital to Analog conversion can be triggered by:
49 (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
50 The used pin (GPIOx_PIN_9) must be configured in input mode.
51
52 (#) Timers TRGO: TIM1, TIM2, TIM4, TIM5, TIM6, TIM7, TIM8 and TIM15
53 (DAC_TRIGGER_T1_TRGO, DAC_TRIGGER_T2_TRGO...)
54
55 (#) Low Power Timers TRGO: LPTIM1 and LPTIM3
56 (DAC_TRIGGER_LPTIM1_CH1, DAC_TRIGGER_LPTIM3_CH1)
57
58 (#) Software using DAC_TRIGGER_SOFTWARE
59 [..]
60 The trigger selection depends on the PWR mode:
61 in stop0, stop1 and stop2 we should select DAC_TRIGGER_EXT_IT9,
62 DAC_TRIGGER_LPTIM1_CH1 or DAC_TRIGGER_LPTIM3_CH1.The other triggers
63 are not functional.
64
65 *** DAC Buffer mode feature ***
66 ===============================
67 [..]
68 Each DAC channel integrates an output buffer that can be used to
69 reduce the output impedance, and to drive external loads directly
70 without having to add an external operational amplifier.
71 To enable, the output buffer use
72 sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
73 [..]
74 (@) Refer to the device datasheet for more details about output
75 impedance value with and without output buffer.
76
77 *** GPIO configurations guidelines ***
78 =====================
79 [..]
80 When a DAC channel is used (ex channel1 on PA4) and the other is not
81 (ex channel2 on PA5 is configured in Analog and disabled).
82 Channel1 may disturb channel2 as coupling effect.
83 Note that there is no coupling on channel2 as soon as channel2 is turned on.
84 Coupling on adjacent channel could be avoided as follows:
85 when unused PA5 is configured as INPUT PULL-UP or DOWN.
86 PA5 is configured in ANALOG just before it is turned on.
87
88 *** DAC Sample and Hold feature ***
89 ========================
90 [..]
91 For each converter, 2 modes are supported: normal mode and
92 "sample and hold" mode (i.e. low power mode).
93 In the sample and hold mode, the DAC core converts data, then holds the
94 converted voltage on a capacitor. When not converting, the DAC cores and
95 buffer are completely turned off between samples and the DAC output is
96 tri-stated, therefore reducing the overall power consumption. A new
97 stabilization period is needed before each new conversion.
98
99 The sample and hold allow setting internal or external voltage @
100 low power consumption cost (output value can be at any given rate either
101 by CPU or DMA).
102
103 The Sample and hold block and registers uses either LSI & run in
104 several power modes: run mode, sleep mode, low power run, low power sleep
105 mode & stop1 mode.
106
107 Low power stop1 mode allows only static conversion.
108
109 To enable Sample and Hold mode
110 Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
111 RCC_LSI_ON parameters.
112
113 Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
114 & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
115 DAC_HoldTime & DAC_RefreshTime;
116
117 *** DAC calibration feature ***
118 ===================================
119 [..]
120 (#) The 2 converters (channel1 & channel2) provide calibration capabilities.
121 (++) Calibration aims at correcting some offset of output buffer.
122 (++) The DAC uses either factory calibration settings OR user defined
123 calibration (trimming) settings (i.e. trimming mode).
124 (++) The user defined settings can be figured out using self calibration
125 handled by HAL_DACEx_SelfCalibrate.
126 (++) HAL_DACEx_SelfCalibrate:
127 (+++) Runs automatically the calibration.
128 (+++) Enables the user trimming mode
129 (+++) Updates a structure with trimming values with fresh calibration
130 results.
131 The user may store the calibration results for larger
132 (ex monitoring the trimming as a function of temperature
133 for instance)
134
135 *** DAC wave generation feature ***
136 ===================================
137 [..]
138 Both DAC channels can be used to generate
139 (#) Noise wave
140 (#) Triangle wave
141
142 *** DAC data format ***
143 =======================
144 [..]
145 The DAC data format can be:
146 (#) 8-bit right alignment using DAC_ALIGN_8B_R
147 (#) 12-bit left alignment using DAC_ALIGN_12B_L
148 (#) 12-bit right alignment using DAC_ALIGN_12B_R
149
150 *** DAC data value to voltage correspondence ***
151 ================================================
152 [..]
153 The analog output voltage on each DAC channel pin is determined
154 by the following equation:
155 [..]
156 DAC_OUTx = VREF+ * DOR / 4095
157 (+) with DOR is the Data Output Register
158 [..]
159 VREF+ is the input voltage reference (refer to the device datasheet)
160 [..]
161 e.g. To set DAC_OUT1 to 0.7V, use
162 (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
163
164 *** DMA requests ***
165 =====================
166 [..]
167 A DMA request can be generated when an external trigger (but not a software trigger)
168 occurs if DMA requests are enabled using HAL_DAC_Start_DMA().
169 DMA requests are mapped as following:
170 GPDMA requests are mapped as following:
171 (+) DAC channel1 mapped on GPDMA request 2 (can be any GPDMA channel)
172 (+) DAC channel2 mapped on GPDMA request 3 (can be any GPDMA channel)
173 LPDMA requests are mapped as following:
174 (+) DAC channel1 mapped on LPDMA request 8 (can be any LPDMA channel)
175 (+) DAC channel2 mapped on LPDMA request 9 (can be any LPDMA channel)
176
177 *** High frequency interface mode ***
178 =====================================
179 [..]
180 The high frequency interface informs DAC instance about the bus frequency in use.
181 It is mandatory information for DAC (as internal timing of DAC is bus frequency dependent)
182 provided thanks to parameter DAC_HighFrequency handled in HAL_DAC_ConfigChannel () function.
183 Use of DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC value of DAC_HighFrequency is recommended
184 function figured out the correct setting.
185 The high frequency mode is same for all converters of a same DAC instance. Either same
186 parameter DAC_HighFrequency is used for all DAC converters or again self
187 DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC detection parameter.
188
189 [..]
190 (@) For Dual mode and specific signal (Triangle and noise) generation please
191 refer to Extended Features Driver description
192
193 ##### How to use this driver #####
194 ==============================================================================
195 [..]
196 (+) DAC APB clock must be enabled to get write access to DAC
197 registers using HAL_DAC_Init()
198 (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
199 (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
200 (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
201
202 *** Calibration mode IO operation ***
203 ======================================
204 [..]
205 (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
206 (+) Run the calibration using HAL_DACEx_SelfCalibrate()
207 (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
208
209 *** Polling mode IO operation ***
210 =================================
211 [..]
212 (+) Start the DAC peripheral using HAL_DAC_Start()
213 (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
214 (+) Stop the DAC peripheral using HAL_DAC_Stop()
215
216 *** DMA mode IO operation ***
217 ==============================
218 [..]
219 (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
220 of data to be transferred at each end of conversion
221 First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
222 (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
223 function is executed and user can add his own code by customization of function pointer
224 HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
225 (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
226 function is executed and user can add his own code by customization of function pointer
227 HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
228 (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
229 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
230 (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
231 HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
232 function is executed and user can add his own code by customization of function pointer
233 HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
234 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
235 (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
236
237 *** Callback registration ***
238 =============================================
239 [..]
240 The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
241 allows the user to configure dynamically the driver callbacks.
242
243 Use Functions HAL_DAC_RegisterCallback() to register a user callback,
244 it allows to register following callbacks:
245 (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
246 (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
247 (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
248 (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
249 (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
250 (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
251 (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
252 (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
253 (+) MspInitCallback : DAC MspInit.
254 (+) MspDeInitCallback : DAC MspdeInit.
255 This function takes as parameters the HAL peripheral handle, the Callback ID
256 and a pointer to the user callback function.
257
258 Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
259 weak (overridden) function. It allows to reset following callbacks:
260 (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
261 (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
262 (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
263 (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
264 (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
265 (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
266 (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
267 (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
268 (+) MspInitCallback : DAC MspInit.
269 (+) MspDeInitCallback : DAC MspdeInit.
270 (+) All Callbacks
271 This function) takes as parameters the HAL peripheral handle and the Callback ID.
272
273 By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
274 all callbacks are reset to the corresponding legacy weak (overridden) functions.
275 Exception done for MspInit and MspDeInit callbacks that are respectively
276 reset to the legacy weak (overridden) functions in the HAL_DAC_Init
277 and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
278 If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
279 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
280
281 Callbacks can be registered/unregistered in READY state only.
282 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
283 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
284 during the Init/DeInit.
285 In that case first register the MspInit/MspDeInit user callbacks
286 using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
287 or HAL_DAC_Init function.
288
289 When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
290 not defined, the callback registering feature is not available
291 and weak (overridden) callbacks are used.
292
293 *** DAC HAL driver macros list ***
294 =============================================
295 [..]
296 Below the list of most used macros in DAC HAL driver.
297
298 (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
299 (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
300 (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
301 (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
302
303 [..]
304 (@) You can refer to the DAC HAL driver header file for more useful macros
305
306 @endverbatim
307 ******************************************************************************
308 */
309
310 /* Includes ------------------------------------------------------------------*/
311 #include "stm32u5xx_hal.h"
312
313 /** @addtogroup STM32U5xx_HAL_Driver
314 * @{
315 */
316
317 #ifdef HAL_DAC_MODULE_ENABLED
318 #if defined(DAC1)
319
320 /** @defgroup DAC DAC
321 * @brief DAC driver modules
322 * @{
323 */
324
325 /* Private typedef -----------------------------------------------------------*/
326 /* Private define ------------------------------------------------------------*/
327 /* Private constants ---------------------------------------------------------*/
328 /** @addtogroup DAC_Private_Constants DAC Private Constants
329 * @{
330 */
331 #define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */
332 #define HFSEL_ENABLE_THRESHOLD_80MHZ 80000000U /* 80 MHz */
333 #define HFSEL_ENABLE_THRESHOLD_160MHZ 160000000U /* 160 MHz */
334
335 /**
336 * @}
337 */
338
339 /* Private macro -------------------------------------------------------------*/
340 /* Private variables ---------------------------------------------------------*/
341 /* Private function prototypes -----------------------------------------------*/
342 /* Exported functions -------------------------------------------------------*/
343
344 /** @defgroup DAC_Exported_Functions DAC Exported Functions
345 * @{
346 */
347
348 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
349 * @brief Initialization and Configuration functions
350 *
351 @verbatim
352 ==============================================================================
353 ##### Initialization and de-initialization functions #####
354 ==============================================================================
355 [..] This section provides functions allowing to:
356 (+) Initialize and configure the DAC.
357 (+) De-initialize the DAC.
358
359 @endverbatim
360 * @{
361 */
362
363 /**
364 * @brief Initialize the DAC peripheral according to the specified parameters
365 * in the DAC_InitStruct and initialize the associated handle.
366 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
367 * the configuration information for the specified DAC.
368 * @retval HAL status
369 */
HAL_DAC_Init(DAC_HandleTypeDef * hdac)370 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
371 {
372 /* Check the DAC peripheral handle */
373 if (hdac == NULL)
374 {
375 return HAL_ERROR;
376 }
377 /* Check the parameters */
378 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
379
380 if (hdac->State == HAL_DAC_STATE_RESET)
381 {
382 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
383 /* Init the DAC Callback settings */
384 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
385 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
386 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
387 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
388
389 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
390 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
391 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
392 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
393
394 if (hdac->MspInitCallback == NULL)
395 {
396 hdac->MspInitCallback = HAL_DAC_MspInit;
397 }
398 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
399
400 /* Allocate lock resource and initialize it */
401 hdac->Lock = HAL_UNLOCKED;
402
403 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
404 /* Init the low level hardware */
405 hdac->MspInitCallback(hdac);
406 #else
407 /* Init the low level hardware */
408 HAL_DAC_MspInit(hdac);
409 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
410 }
411
412 /* Initialize the DAC state*/
413 hdac->State = HAL_DAC_STATE_BUSY;
414
415 /* Set DAC error code to none */
416 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
417
418 /* Initialize the DAC state*/
419 hdac->State = HAL_DAC_STATE_READY;
420
421 /* Return function status */
422 return HAL_OK;
423 }
424
425 /**
426 * @brief Deinitialize the DAC peripheral registers to their default reset values.
427 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
428 * the configuration information for the specified DAC.
429 * @retval HAL status
430 */
HAL_DAC_DeInit(DAC_HandleTypeDef * hdac)431 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
432 {
433 /* Check the DAC peripheral handle */
434 if (hdac == NULL)
435 {
436 return HAL_ERROR;
437 }
438
439 /* Check the parameters */
440 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
441
442 /* Change DAC state */
443 hdac->State = HAL_DAC_STATE_BUSY;
444
445 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
446 if (hdac->MspDeInitCallback == NULL)
447 {
448 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
449 }
450 /* DeInit the low level hardware */
451 hdac->MspDeInitCallback(hdac);
452 #else
453 /* DeInit the low level hardware */
454 HAL_DAC_MspDeInit(hdac);
455 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
456
457 /* Set DAC error code to none */
458 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
459
460 /* Change DAC state */
461 hdac->State = HAL_DAC_STATE_RESET;
462
463 /* Release Lock */
464 __HAL_UNLOCK(hdac);
465
466 /* Return function status */
467 return HAL_OK;
468 }
469
470 /**
471 * @brief Initialize the DAC MSP.
472 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
473 * the configuration information for the specified DAC.
474 * @retval None
475 */
HAL_DAC_MspInit(DAC_HandleTypeDef * hdac)476 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
477 {
478 /* Prevent unused argument(s) compilation warning */
479 UNUSED(hdac);
480
481 /* NOTE : This function should not be modified, when the callback is needed,
482 the HAL_DAC_MspInit could be implemented in the user file
483 */
484 }
485
486 /**
487 * @brief DeInitialize the DAC MSP.
488 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
489 * the configuration information for the specified DAC.
490 * @retval None
491 */
HAL_DAC_MspDeInit(DAC_HandleTypeDef * hdac)492 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
493 {
494 /* Prevent unused argument(s) compilation warning */
495 UNUSED(hdac);
496
497 /* NOTE : This function should not be modified, when the callback is needed,
498 the HAL_DAC_MspDeInit could be implemented in the user file
499 */
500 }
501
502 /**
503 * @}
504 */
505
506 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
507 * @brief IO operation functions
508 *
509 @verbatim
510 ==============================================================================
511 ##### IO operation functions #####
512 ==============================================================================
513 [..] This section provides functions allowing to:
514 (+) Start conversion.
515 (+) Stop conversion.
516 (+) Start conversion and enable DMA transfer.
517 (+) Stop conversion and disable DMA transfer.
518 (+) Get result of conversion.
519
520 @endverbatim
521 * @{
522 */
523
524 /**
525 * @brief Enables DAC and starts conversion of channel.
526 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
527 * the configuration information for the specified DAC.
528 * @param Channel The selected DAC channel.
529 * This parameter can be one of the following values:
530 * @arg DAC_CHANNEL_1: DAC Channel1 selected
531 * @arg DAC_CHANNEL_2: DAC Channel2 selected
532 * @retval HAL status
533 */
HAL_DAC_Start(DAC_HandleTypeDef * hdac,uint32_t Channel)534 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
535 {
536 __IO uint32_t wait_loop_index;
537
538 /* Check the DAC peripheral handle */
539 if (hdac == NULL)
540 {
541 return HAL_ERROR;
542 }
543
544 /* Check the parameters */
545 assert_param(IS_DAC_CHANNEL(Channel));
546
547 /* Process locked */
548 __HAL_LOCK(hdac);
549
550 /* Change DAC state */
551 hdac->State = HAL_DAC_STATE_BUSY;
552
553 /* Enable the Peripheral */
554 __HAL_DAC_ENABLE(hdac, Channel);
555 /* Ensure minimum wait before using peripheral after enabling it */
556 /* Wait loop initialization and execution */
557 /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed 32 */
558 /* bits register capacity and handle low frequency. */
559 wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
560 while (wait_loop_index != 0UL)
561 {
562 wait_loop_index--;
563 }
564
565 if (Channel == DAC_CHANNEL_1)
566 {
567 /* Check if software trigger enabled */
568 if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
569 {
570 /* Enable the selected DAC software conversion */
571 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
572 }
573 }
574
575 else
576 {
577 /* Check if software trigger enabled */
578 if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
579 {
580 /* Enable the selected DAC software conversion*/
581 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
582 }
583 }
584
585
586 /* Change DAC state */
587 hdac->State = HAL_DAC_STATE_READY;
588
589 /* Process unlocked */
590 __HAL_UNLOCK(hdac);
591
592 /* Return function status */
593 return HAL_OK;
594 }
595
596 /**
597 * @brief Disables DAC and stop conversion of channel.
598 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
599 * the configuration information for the specified DAC.
600 * @param Channel The selected DAC channel.
601 * This parameter can be one of the following values:
602 * @arg DAC_CHANNEL_1: DAC Channel1 selected
603 * @arg DAC_CHANNEL_2: DAC Channel2 selected
604 * @retval HAL status
605 */
HAL_DAC_Stop(DAC_HandleTypeDef * hdac,uint32_t Channel)606 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
607 {
608 /* Check the DAC peripheral handle */
609 if (hdac == NULL)
610 {
611 return HAL_ERROR;
612 }
613
614 /* Check the parameters */
615 assert_param(IS_DAC_CHANNEL(Channel));
616
617 /* Disable the Peripheral */
618 __HAL_DAC_DISABLE(hdac, Channel);
619
620 /* Change DAC state */
621 hdac->State = HAL_DAC_STATE_READY;
622
623 /* Return function status */
624 return HAL_OK;
625 }
626
627 /**
628 * @brief Enables DAC and starts conversion of channel.
629 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
630 * the configuration information for the specified DAC.
631 * @param Channel The selected DAC channel.
632 * This parameter can be one of the following values:
633 * @arg DAC_CHANNEL_1: DAC Channel1 selected
634 * @arg DAC_CHANNEL_2: DAC Channel2 selected
635 * @param pData The source Buffer address.
636 * @param Length The length of data to be transferred from memory to DAC peripheral
637 * @param Alignment Specifies the data alignment for DAC channel.
638 * This parameter can be one of the following values:
639 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
640 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
641 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
642 * @retval HAL status
643 */
HAL_DAC_Start_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel,const uint32_t * pData,uint32_t Length,uint32_t Alignment)644 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
645 uint32_t Alignment)
646 {
647 HAL_StatusTypeDef status;
648 uint32_t tmpreg;
649 uint32_t LengthInBytes;
650 DMA_NodeConfTypeDef node_conf;
651 __IO uint32_t wait_loop_index;
652
653 /* Check the DAC peripheral handle */
654 if (hdac == NULL)
655 {
656 return HAL_ERROR;
657 }
658
659 /* Check the parameters */
660 assert_param(IS_DAC_CHANNEL(Channel));
661 assert_param(IS_DAC_ALIGN(Alignment));
662
663 /* Process locked */
664 __HAL_LOCK(hdac);
665
666 /* Change DAC state */
667 hdac->State = HAL_DAC_STATE_BUSY;
668
669 if (Channel == DAC_CHANNEL_1)
670 {
671 /* Set the DMA transfer complete callback for channel1 */
672 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
673
674 /* Set the DMA half transfer complete callback for channel1 */
675 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
676
677 /* Set the DMA error callback for channel1 */
678 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
679
680 /* Enable the selected DAC channel1 DMA request */
681 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
682
683 /* Case of use of channel 1 */
684 switch (Alignment)
685 {
686 case DAC_ALIGN_12B_R:
687 /* Get DHR12R1 address */
688 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
689 break;
690 case DAC_ALIGN_12B_L:
691 /* Get DHR12L1 address */
692 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
693 break;
694 default: /* case DAC_ALIGN_8B_R */
695 /* Get DHR8R1 address */
696 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
697 break;
698 }
699 }
700
701 else
702 {
703 /* Set the DMA transfer complete callback for channel2 */
704 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
705
706 /* Set the DMA half transfer complete callback for channel2 */
707 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
708
709 /* Set the DMA error callback for channel2 */
710 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
711
712 /* Enable the selected DAC channel2 DMA request */
713 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
714
715 /* Case of use of channel 2 */
716 switch (Alignment)
717 {
718 case DAC_ALIGN_12B_R:
719 /* Get DHR12R2 address */
720 tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
721 break;
722 case DAC_ALIGN_12B_L:
723 /* Get DHR12L2 address */
724 tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
725 break;
726 default: /* case DAC_ALIGN_8B_R */
727 /* Get DHR8R2 address */
728 tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
729 break;
730 }
731 }
732
733 if (Channel == DAC_CHANNEL_1)
734 {
735 /* Enable the DAC DMA underrun interrupt */
736 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
737
738 /* Enable the DMA channel */
739 /* Check linkedlist mode */
740 if ((hdac->DMA_Handle1->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
741 {
742 if ((hdac->DMA_Handle1->LinkedListQueue != NULL) && (hdac->DMA_Handle1->LinkedListQueue->Head != NULL))
743 {
744 /* Length should be converted to number of bytes */
745 if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hdac->DMA_Handle1->LinkedListQueue->Head) != HAL_OK)
746 {
747 return HAL_ERROR;
748 }
749
750 /* Length should be converted to number of bytes */
751 if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
752 {
753 /* Word -> Bytes */
754 LengthInBytes = Length * 4U;
755 }
756 else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
757 {
758 /* Halfword -> Bytes */
759 LengthInBytes = Length * 2U;
760 }
761 else /* Bytes */
762 {
763 /* Same size already expressed in Bytes */
764 LengthInBytes = Length;
765 }
766
767 /* Set DMA data size */
768 hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = LengthInBytes;
769
770 /* Set DMA source address */
771 hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
772
773 /* Set DMA destination address */
774 hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = tmpreg;
775
776 /* Enable the DMA channel */
777 status = HAL_DMAEx_List_Start_IT(hdac->DMA_Handle1);
778 }
779 else
780 {
781 /* Return error status */
782 return HAL_ERROR;
783 }
784 }
785 else
786 {
787 /* Length should be converted to number of bytes */
788 if (hdac->DMA_Handle1->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
789 {
790 /* Word -> Bytes */
791 LengthInBytes = Length * 4U;
792 }
793 else if (hdac->DMA_Handle1->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
794 {
795 /* Halfword -> Bytes */
796 LengthInBytes = Length * 2U;
797 }
798 else /* Bytes */
799 {
800 /* Same size already expressed in Bytes */
801 LengthInBytes = Length;
802 }
803
804 /* Enable the DMA channel */
805 status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, LengthInBytes);
806 }
807 }
808
809 else
810 {
811 /* Enable the DAC DMA underrun interrupt */
812 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
813
814 /* Enable the DMA channel */
815 /* Check linkedlist mode */
816 if ((hdac->DMA_Handle2->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
817 {
818 if ((hdac->DMA_Handle2->LinkedListQueue != NULL) && (hdac->DMA_Handle2->LinkedListQueue->Head != NULL))
819 {
820 /* Length should be converted to number of bytes */
821 if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hdac->DMA_Handle2->LinkedListQueue->Head) != HAL_OK)
822 {
823 return HAL_ERROR;
824 }
825
826 /* Length should be converted to number of bytes */
827 if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
828 {
829 /* Word -> Bytes */
830 LengthInBytes = Length * 4U;
831 }
832 else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
833 {
834 /* Halfword -> Bytes */
835 LengthInBytes = Length * 2U;
836 }
837 else /* Bytes */
838 {
839 /* Same size already expressed in Bytes */
840 LengthInBytes = Length;
841 }
842
843 /* Set DMA data size */
844 hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = LengthInBytes;
845
846 /* Set DMA source address */
847 hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
848
849 /* Set DMA destination address */
850 hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = tmpreg;
851
852 /* Enable the DMA channel */
853 status = HAL_DMAEx_List_Start_IT(hdac->DMA_Handle2);
854 }
855 else
856 {
857 /* Return error status */
858 return HAL_ERROR;
859 }
860 }
861 else
862 {
863 /* Length should be converted to number of bytes */
864 if (hdac->DMA_Handle2->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
865 {
866 /* Word -> Bytes */
867 LengthInBytes = Length * 4U;
868 }
869 else if (hdac->DMA_Handle2->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
870 {
871 /* Halfword -> Bytes */
872 LengthInBytes = Length * 2U;
873 }
874 else /* Bytes */
875 {
876 /* Same size already expressed in Bytes */
877 LengthInBytes = Length;
878 }
879
880 /* Enable the DMA channel */
881 status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, LengthInBytes);
882 }
883 }
884
885
886 /* Process Unlocked */
887 __HAL_UNLOCK(hdac);
888
889 if (status == HAL_OK)
890 {
891 /* Enable the Peripheral */
892 __HAL_DAC_ENABLE(hdac, Channel);
893 /* Ensure minimum wait before using peripheral after enabling it */
894 /* Wait loop initialization and execution */
895 /* Note: Variable divided by 2 to compensate partially */
896 /* CPU processing cycles, scaling in us split to not */
897 /* exceed 32 bits register capacity and handle low frequency. */
898 wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
899 while (wait_loop_index != 0UL)
900 {
901 wait_loop_index--;
902 }
903 }
904 else
905 {
906 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
907 }
908
909 /* Return function status */
910 return status;
911 }
912
913 /**
914 * @brief Disables DAC and stop conversion of channel.
915 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
916 * the configuration information for the specified DAC.
917 * @param Channel The selected DAC channel.
918 * This parameter can be one of the following values:
919 * @arg DAC_CHANNEL_1: DAC Channel1 selected
920 * @arg DAC_CHANNEL_2: DAC Channel2 selected
921 * @retval HAL status
922 */
HAL_DAC_Stop_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel)923 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
924 {
925 /* Check the DAC peripheral handle */
926 if (hdac == NULL)
927 {
928 return HAL_ERROR;
929 }
930
931 /* Check the parameters */
932 assert_param(IS_DAC_CHANNEL(Channel));
933
934 /* Disable the selected DAC channel DMA request */
935 hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
936
937 /* Disable the Peripheral */
938 __HAL_DAC_DISABLE(hdac, Channel);
939
940 /* Disable the DMA channel */
941
942 /* Channel1 is used */
943 if (Channel == DAC_CHANNEL_1)
944 {
945 /* Disable the DMA channel */
946 (void)HAL_DMA_Abort(hdac->DMA_Handle1);
947
948 /* Disable the DAC DMA underrun interrupt */
949 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
950 }
951
952 else /* Channel2 is used for */
953 {
954 /* Disable the DMA channel */
955 (void)HAL_DMA_Abort(hdac->DMA_Handle2);
956
957 /* Disable the DAC DMA underrun interrupt */
958 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
959 }
960
961
962 /* Change DAC state */
963 hdac->State = HAL_DAC_STATE_READY;
964
965 /* Return function status */
966 return HAL_OK;
967 }
968
969 /**
970 * @brief Handles DAC interrupt request
971 * This function uses the interruption of DMA
972 * underrun.
973 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
974 * the configuration information for the specified DAC.
975 * @retval None
976 */
HAL_DAC_IRQHandler(DAC_HandleTypeDef * hdac)977 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
978 {
979 uint32_t itsource = hdac->Instance->CR;
980 uint32_t itflag = hdac->Instance->SR;
981
982 if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1)
983 {
984 /* Check underrun flag of DAC channel 1 */
985 if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1)
986 {
987 /* Change DAC state to error state */
988 hdac->State = HAL_DAC_STATE_ERROR;
989
990 /* Set DAC error code to channel1 DMA underrun error */
991 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
992
993 /* Clear the underrun flag */
994 __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
995
996 /* Disable the selected DAC channel1 DMA request */
997 __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1);
998
999 /* Error callback */
1000 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1001 hdac->DMAUnderrunCallbackCh1(hdac);
1002 #else
1003 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
1004 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1005 }
1006 }
1007
1008
1009 if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2)
1010 {
1011 /* Check underrun flag of DAC channel 2 */
1012 if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2)
1013 {
1014 /* Change DAC state to error state */
1015 hdac->State = HAL_DAC_STATE_ERROR;
1016
1017 /* Set DAC error code to channel2 DMA underrun error */
1018 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
1019
1020 /* Clear the underrun flag */
1021 __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
1022
1023 /* Disable the selected DAC channel2 DMA request */
1024 __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2);
1025
1026 /* Error callback */
1027 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1028 hdac->DMAUnderrunCallbackCh2(hdac);
1029 #else
1030 HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
1031 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1032 }
1033 }
1034
1035 }
1036
1037 /**
1038 * @brief Set the specified data holding register value for DAC channel.
1039 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1040 * the configuration information for the specified DAC.
1041 * @param Channel The selected DAC channel.
1042 * This parameter can be one of the following values:
1043 * @arg DAC_CHANNEL_1: DAC Channel1 selected
1044 * @arg DAC_CHANNEL_2: DAC Channel2 selected
1045 * @param Alignment Specifies the data alignment.
1046 * This parameter can be one of the following values:
1047 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
1048 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
1049 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
1050 * @param Data Data to be loaded in the selected data holding register.
1051 * @retval HAL status
1052 */
HAL_DAC_SetValue(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t Alignment,uint32_t Data)1053 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
1054 {
1055 __IO uint32_t tmp = 0UL;
1056
1057 /* Check the DAC peripheral handle */
1058 if (hdac == NULL)
1059 {
1060 return HAL_ERROR;
1061 }
1062
1063 /* Check the parameters */
1064 assert_param(IS_DAC_CHANNEL(Channel));
1065 assert_param(IS_DAC_ALIGN(Alignment));
1066 /* In case DMA Double data mode is activated, DATA range is almost full uin32_t one: no check */
1067 if ((hdac->Instance->MCR & (DAC_MCR_DMADOUBLE1 << (Channel & 0x10UL))) == 0UL)
1068 {
1069 assert_param(IS_DAC_DATA(Data));
1070 }
1071
1072 tmp = (uint32_t)hdac->Instance;
1073 if (Channel == DAC_CHANNEL_1)
1074 {
1075 tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
1076 }
1077
1078 else
1079 {
1080 tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
1081 }
1082
1083
1084 /* Set the DAC channel selected data holding register */
1085 *(__IO uint32_t *) tmp = Data;
1086
1087 /* Return function status */
1088 return HAL_OK;
1089 }
1090
1091 /**
1092 * @brief Conversion complete callback in non-blocking mode for Channel1
1093 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1094 * the configuration information for the specified DAC.
1095 * @retval None
1096 */
HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef * hdac)1097 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac)
1098 {
1099 /* Prevent unused argument(s) compilation warning */
1100 UNUSED(hdac);
1101
1102 /* NOTE : This function should not be modified, when the callback is needed,
1103 the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
1104 */
1105 }
1106
1107 /**
1108 * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1
1109 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1110 * the configuration information for the specified DAC.
1111 * @retval None
1112 */
HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef * hdac)1113 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac)
1114 {
1115 /* Prevent unused argument(s) compilation warning */
1116 UNUSED(hdac);
1117
1118 /* NOTE : This function should not be modified, when the callback is needed,
1119 the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
1120 */
1121 }
1122
1123 /**
1124 * @brief Error DAC callback for Channel1.
1125 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1126 * the configuration information for the specified DAC.
1127 * @retval None
1128 */
HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef * hdac)1129 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
1130 {
1131 /* Prevent unused argument(s) compilation warning */
1132 UNUSED(hdac);
1133
1134 /* NOTE : This function should not be modified, when the callback is needed,
1135 the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
1136 */
1137 }
1138
1139 /**
1140 * @brief DMA underrun DAC callback for channel1.
1141 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1142 * the configuration information for the specified DAC.
1143 * @retval None
1144 */
HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef * hdac)1145 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
1146 {
1147 /* Prevent unused argument(s) compilation warning */
1148 UNUSED(hdac);
1149
1150 /* NOTE : This function should not be modified, when the callback is needed,
1151 the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
1152 */
1153 }
1154
1155 /**
1156 * @}
1157 */
1158
1159 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
1160 * @brief Peripheral Control functions
1161 *
1162 @verbatim
1163 ==============================================================================
1164 ##### Peripheral Control functions #####
1165 ==============================================================================
1166 [..] This section provides functions allowing to:
1167 (+) Configure channels.
1168 (+) Set the specified data holding register value for DAC channel.
1169
1170 @endverbatim
1171 * @{
1172 */
1173
1174 /**
1175 * @brief Returns the last data output value of the selected DAC channel.
1176 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1177 * the configuration information for the specified DAC.
1178 * @param Channel The selected DAC channel.
1179 * This parameter can be one of the following values:
1180 * @arg DAC_CHANNEL_1: DAC Channel1 selected
1181 * @arg DAC_CHANNEL_2: DAC Channel2 selected
1182 * @retval The selected DAC channel data output value.
1183 */
HAL_DAC_GetValue(const DAC_HandleTypeDef * hdac,uint32_t Channel)1184 uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel)
1185 {
1186 uint32_t result;
1187
1188 /* Check the DAC peripheral handle */
1189 assert_param(hdac != NULL);
1190
1191 /* Check the parameters */
1192 assert_param(IS_DAC_CHANNEL(Channel));
1193
1194 if (Channel == DAC_CHANNEL_1)
1195 {
1196 result = hdac->Instance->DOR1;
1197 }
1198
1199 else
1200 {
1201 result = hdac->Instance->DOR2;
1202 }
1203
1204 /* Returns the DAC channel data output register value */
1205 return result;
1206 }
1207
1208 /**
1209 * @brief Configures the selected DAC channel.
1210 * @note By calling this function, if the application will be run in stop
1211 * mode, the DAC_Trigger field of the structure sConfig
1212 * should be one of the following values:
1213 * - DAC_TRIGGER_STOP_LPTIM1_OUT
1214 * - DAC_TRIGGER_STOP_LPTIM3_OUT
1215 * - DAC_TRIGGER_STOP_EXT_IT9
1216 * For application where DAC is not run in stop mode, the DAC trigger
1217 * should be a value of @ref DAC_trigger_selection
1218 * @note By calling this function, the high frequency interface mode (HFSEL bits)
1219 * will be set. This parameter scope is the DAC instance. As the function
1220 * is called for each channel, the @ref DAC_HighFrequency of @arg sConfig
1221 * must be the same at each call.
1222 * (or DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC self detect).
1223 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1224 * the configuration information for the specified DAC.
1225 * @param sConfig DAC configuration structure.
1226 * @param Channel The selected DAC channel.
1227 * This parameter can be one of the following values:
1228 * @arg DAC_CHANNEL_1: DAC Channel1 selected
1229 * @arg DAC_CHANNEL_2: DAC Channel2 selected
1230 * @retval HAL status
1231 */
HAL_DAC_ConfigChannel(DAC_HandleTypeDef * hdac,const DAC_ChannelConfTypeDef * sConfig,uint32_t Channel)1232 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
1233 const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
1234 {
1235 HAL_StatusTypeDef status = HAL_OK;
1236 uint32_t tmpreg1;
1237 uint32_t tmpreg2;
1238 uint32_t tickstart;
1239 uint32_t hclkfreq;
1240 uint32_t connectOnChip;
1241
1242 /* Check the DAC peripheral handle and channel configuration struct */
1243 if ((hdac == NULL) || (sConfig == NULL))
1244 {
1245 return HAL_ERROR;
1246 }
1247
1248 /* Check the DAC parameters */
1249 assert_param(IS_DAC_AUTONOMOUS(sConfig->DAC_AutonomousMode));
1250 assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency));
1251 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
1252 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
1253 assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
1254 assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
1255 if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
1256 {
1257 assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
1258 }
1259 assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
1260 if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
1261 {
1262 assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
1263 assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
1264 assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
1265 }
1266 else
1267 {
1268 /* In case of mode normal and buffer disabled, connection to both on chip periph and external pin is not possible */
1269 if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_DISABLE)
1270 {
1271 assert_param(sConfig->DAC_ConnectOnChipPeripheral != DAC_CHIPCONNECT_BOTH);
1272 }
1273 }
1274 assert_param(IS_DAC_CHANNEL(Channel));
1275 assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode));
1276 assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat));
1277
1278 /* Process locked */
1279 __HAL_LOCK(hdac);
1280
1281 /* Change DAC state */
1282 hdac->State = HAL_DAC_STATE_BUSY;
1283
1284 /* Sample and hold configuration */
1285 if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
1286 {
1287 /* Get timeout */
1288 tickstart = HAL_GetTick();
1289
1290 if (Channel == DAC_CHANNEL_1)
1291 {
1292 /* SHSR1 can be written when BWST1 is cleared */
1293 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
1294 {
1295 /* Check for the Timeout */
1296 if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
1297 {
1298 /* New check to avoid false timeout detection in case of preemption */
1299 if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
1300 {
1301 /* Update error code */
1302 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
1303
1304 /* Change the DMA state */
1305 hdac->State = HAL_DAC_STATE_TIMEOUT;
1306
1307 return HAL_TIMEOUT;
1308 }
1309 }
1310 }
1311 hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
1312 }
1313
1314 else /* Channel 2 */
1315 {
1316 /* SHSR2 can be written when BWST2 is cleared */
1317 while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
1318 {
1319 /* Check for the Timeout */
1320 if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
1321 {
1322 /* New check to avoid false timeout detection in case of preemption */
1323 if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
1324 {
1325 /* Update error code */
1326 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
1327
1328 /* Change the DMA state */
1329 hdac->State = HAL_DAC_STATE_TIMEOUT;
1330
1331 return HAL_TIMEOUT;
1332 }
1333 }
1334 }
1335 hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
1336 }
1337
1338
1339 /* HoldTime */
1340 MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
1341 (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
1342 /* RefreshTime */
1343 MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
1344 (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
1345 }
1346
1347 /* Autonomous mode configuration */
1348 MODIFY_REG(hdac->Instance->AUTOCR, DAC_AUTOCR_AUTOMODE, sConfig->DAC_AutonomousMode);
1349
1350 if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
1351 /* USER TRIMMING */
1352 {
1353 /* Get the DAC CCR value */
1354 tmpreg1 = hdac->Instance->CCR;
1355 /* Clear trimming value */
1356 tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
1357 /* Configure for the selected trimming offset */
1358 tmpreg2 = sConfig->DAC_TrimmingValue;
1359 /* Calculate CCR register value depending on DAC_Channel */
1360 tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
1361 /* Write to DAC CCR */
1362 hdac->Instance->CCR = tmpreg1;
1363 }
1364 /* else factory trimming is used (factory setting are available at reset)*/
1365 /* SW Nothing has nothing to do */
1366
1367 /* Get the DAC MCR value */
1368 tmpreg1 = hdac->Instance->MCR;
1369 /* Clear DAC_MCR_MODEx bits */
1370 tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
1371 /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
1372
1373
1374 if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
1375 {
1376 connectOnChip = 0x00000000UL;
1377 }
1378 else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
1379 {
1380 connectOnChip = DAC_MCR_MODE1_0;
1381 }
1382 else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
1383 {
1384 if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
1385 {
1386 connectOnChip = DAC_MCR_MODE1_0;
1387 }
1388 else
1389 {
1390 connectOnChip = 0x00000000UL;
1391 }
1392 }
1393 tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip);
1394 /* Clear DAC_MCR_DMADOUBLEx */
1395 tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL));
1396 /* Configure for the selected DAC channel: DMA double data mode */
1397 tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL;
1398 /* Clear DAC_MCR_SINFORMATx */
1399 tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL));
1400 /* Configure for the selected DAC channel: Signed format */
1401 tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL;
1402 /* Clear DAC_MCR_HFSEL bits */
1403 tmpreg1 &= ~(DAC_MCR_HFSEL);
1404 /* Configure for both DAC channels: high frequency mode */
1405 if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency)
1406 {
1407 hclkfreq = HAL_RCC_GetHCLKFreq();
1408 if (hclkfreq > HFSEL_ENABLE_THRESHOLD_160MHZ)
1409 {
1410 tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ;
1411 }
1412 else if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ)
1413 {
1414 tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ;
1415 }
1416 else
1417 {
1418 tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE;
1419 }
1420 }
1421 else
1422 {
1423 tmpreg1 |= sConfig->DAC_HighFrequency;
1424 }
1425 /* Calculate MCR register value depending on DAC_Channel */
1426 tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
1427 /* Write to DAC MCR */
1428 hdac->Instance->MCR = tmpreg1;
1429
1430 /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
1431 CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
1432
1433 /* Get the DAC CR value */
1434 tmpreg1 = hdac->Instance->CR;
1435 /* Clear TENx, TSELx, WAVEx and MAMPx bits */
1436 tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
1437 /* Configure for the selected DAC channel: trigger */
1438 /* Set TSELx and TENx bits according to DAC_Trigger value */
1439 tmpreg2 = sConfig->DAC_Trigger;
1440 /* Calculate CR register value depending on DAC_Channel */
1441 tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
1442 /* Write to DAC CR */
1443 hdac->Instance->CR = tmpreg1;
1444 /* Disable wave generation */
1445 CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
1446
1447 /* Change DAC state */
1448 hdac->State = HAL_DAC_STATE_READY;
1449
1450 /* Process unlocked */
1451 __HAL_UNLOCK(hdac);
1452
1453 /* Return function status */
1454 return status;
1455 }
1456
1457 /**
1458 * @}
1459 */
1460
1461 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
1462 * @brief Peripheral State and Errors functions
1463 *
1464 @verbatim
1465 ==============================================================================
1466 ##### Peripheral State and Errors functions #####
1467 ==============================================================================
1468 [..]
1469 This subsection provides functions allowing to
1470 (+) Check the DAC state.
1471 (+) Check the DAC Errors.
1472
1473 @endverbatim
1474 * @{
1475 */
1476
1477 /**
1478 * @brief return the DAC handle state
1479 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1480 * the configuration information for the specified DAC.
1481 * @retval HAL state
1482 */
HAL_DAC_GetState(const DAC_HandleTypeDef * hdac)1483 HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac)
1484 {
1485 /* Return DAC handle state */
1486 return hdac->State;
1487 }
1488
1489
1490 /**
1491 * @brief Return the DAC error code
1492 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1493 * the configuration information for the specified DAC.
1494 * @retval DAC Error Code
1495 */
HAL_DAC_GetError(const DAC_HandleTypeDef * hdac)1496 uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac)
1497 {
1498 return hdac->ErrorCode;
1499 }
1500
1501 /**
1502 * @}
1503 */
1504
1505 /**
1506 * @}
1507 */
1508
1509 /** @addtogroup DAC_Exported_Functions
1510 * @{
1511 */
1512
1513 /** @addtogroup DAC_Exported_Functions_Group1
1514 * @{
1515 */
1516 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1517 /**
1518 * @brief Register a User DAC Callback
1519 * To be used instead of the weak (overridden) predefined callback
1520 * @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register
1521 * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
1522 * @param hdac DAC handle
1523 * @param CallbackID ID of the callback to be registered
1524 * This parameter can be one of the following values:
1525 * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
1526 * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
1527 * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
1528 * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
1529 * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
1530 * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
1531 * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
1532 * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
1533 * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
1534 * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
1535 * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
1536 *
1537 * @param pCallback pointer to the Callback function
1538 * @retval status
1539 */
HAL_DAC_RegisterCallback(DAC_HandleTypeDef * hdac,HAL_DAC_CallbackIDTypeDef CallbackID,pDAC_CallbackTypeDef pCallback)1540 HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
1541 pDAC_CallbackTypeDef pCallback)
1542 {
1543 HAL_StatusTypeDef status = HAL_OK;
1544
1545 /* Check the DAC peripheral handle */
1546 if (hdac == NULL)
1547 {
1548 return HAL_ERROR;
1549 }
1550
1551 if (pCallback == NULL)
1552 {
1553 /* Update the error code */
1554 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1555 return HAL_ERROR;
1556 }
1557
1558 if (hdac->State == HAL_DAC_STATE_READY)
1559 {
1560 switch (CallbackID)
1561 {
1562 case HAL_DAC_CH1_COMPLETE_CB_ID :
1563 hdac->ConvCpltCallbackCh1 = pCallback;
1564 break;
1565 case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
1566 hdac->ConvHalfCpltCallbackCh1 = pCallback;
1567 break;
1568 case HAL_DAC_CH1_ERROR_ID :
1569 hdac->ErrorCallbackCh1 = pCallback;
1570 break;
1571 case HAL_DAC_CH1_UNDERRUN_CB_ID :
1572 hdac->DMAUnderrunCallbackCh1 = pCallback;
1573 break;
1574
1575 case HAL_DAC_CH2_COMPLETE_CB_ID :
1576 hdac->ConvCpltCallbackCh2 = pCallback;
1577 break;
1578 case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
1579 hdac->ConvHalfCpltCallbackCh2 = pCallback;
1580 break;
1581 case HAL_DAC_CH2_ERROR_ID :
1582 hdac->ErrorCallbackCh2 = pCallback;
1583 break;
1584 case HAL_DAC_CH2_UNDERRUN_CB_ID :
1585 hdac->DMAUnderrunCallbackCh2 = pCallback;
1586 break;
1587
1588 case HAL_DAC_MSPINIT_CB_ID :
1589 hdac->MspInitCallback = pCallback;
1590 break;
1591 case HAL_DAC_MSPDEINIT_CB_ID :
1592 hdac->MspDeInitCallback = pCallback;
1593 break;
1594 default :
1595 /* Update the error code */
1596 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1597 /* update return status */
1598 status = HAL_ERROR;
1599 break;
1600 }
1601 }
1602 else if (hdac->State == HAL_DAC_STATE_RESET)
1603 {
1604 switch (CallbackID)
1605 {
1606 case HAL_DAC_MSPINIT_CB_ID :
1607 hdac->MspInitCallback = pCallback;
1608 break;
1609 case HAL_DAC_MSPDEINIT_CB_ID :
1610 hdac->MspDeInitCallback = pCallback;
1611 break;
1612 default :
1613 /* Update the error code */
1614 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1615 /* update return status */
1616 status = HAL_ERROR;
1617 break;
1618 }
1619 }
1620 else
1621 {
1622 /* Update the error code */
1623 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1624 /* update return status */
1625 status = HAL_ERROR;
1626 }
1627
1628 return status;
1629 }
1630
1631 /**
1632 * @brief Unregister a User DAC Callback
1633 * DAC Callback is redirected to the weak (overridden) predefined callback
1634 * @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register
1635 * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
1636 * @param hdac DAC handle
1637 * @param CallbackID ID of the callback to be unregistered
1638 * This parameter can be one of the following values:
1639 * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
1640 * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
1641 * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
1642 * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
1643 * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
1644 * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
1645 * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
1646 * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
1647 * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
1648 * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
1649 * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks
1650 * @retval status
1651 */
HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef * hdac,HAL_DAC_CallbackIDTypeDef CallbackID)1652 HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
1653 {
1654 HAL_StatusTypeDef status = HAL_OK;
1655
1656 /* Check the DAC peripheral handle */
1657 if (hdac == NULL)
1658 {
1659 return HAL_ERROR;
1660 }
1661
1662 if (hdac->State == HAL_DAC_STATE_READY)
1663 {
1664 switch (CallbackID)
1665 {
1666 case HAL_DAC_CH1_COMPLETE_CB_ID :
1667 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
1668 break;
1669 case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
1670 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
1671 break;
1672 case HAL_DAC_CH1_ERROR_ID :
1673 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
1674 break;
1675 case HAL_DAC_CH1_UNDERRUN_CB_ID :
1676 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
1677 break;
1678
1679 case HAL_DAC_CH2_COMPLETE_CB_ID :
1680 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
1681 break;
1682 case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
1683 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
1684 break;
1685 case HAL_DAC_CH2_ERROR_ID :
1686 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
1687 break;
1688 case HAL_DAC_CH2_UNDERRUN_CB_ID :
1689 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
1690 break;
1691
1692 case HAL_DAC_MSPINIT_CB_ID :
1693 hdac->MspInitCallback = HAL_DAC_MspInit;
1694 break;
1695 case HAL_DAC_MSPDEINIT_CB_ID :
1696 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
1697 break;
1698 case HAL_DAC_ALL_CB_ID :
1699 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
1700 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
1701 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
1702 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
1703
1704 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
1705 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
1706 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
1707 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
1708
1709 hdac->MspInitCallback = HAL_DAC_MspInit;
1710 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
1711 break;
1712 default :
1713 /* Update the error code */
1714 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1715 /* update return status */
1716 status = HAL_ERROR;
1717 break;
1718 }
1719 }
1720 else if (hdac->State == HAL_DAC_STATE_RESET)
1721 {
1722 switch (CallbackID)
1723 {
1724 case HAL_DAC_MSPINIT_CB_ID :
1725 hdac->MspInitCallback = HAL_DAC_MspInit;
1726 break;
1727 case HAL_DAC_MSPDEINIT_CB_ID :
1728 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
1729 break;
1730 default :
1731 /* Update the error code */
1732 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1733 /* update return status */
1734 status = HAL_ERROR;
1735 break;
1736 }
1737 }
1738 else
1739 {
1740 /* Update the error code */
1741 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1742 /* update return status */
1743 status = HAL_ERROR;
1744 }
1745
1746 return status;
1747 }
1748 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1749
1750 /**
1751 * @}
1752 */
1753
1754 /**
1755 * @}
1756 */
1757
1758 /** @addtogroup DAC_Private_Functions
1759 * @{
1760 */
1761
1762 /**
1763 * @brief DMA conversion complete callback.
1764 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1765 * the configuration information for the specified DMA module.
1766 * @retval None
1767 */
DAC_DMAConvCpltCh1(DMA_HandleTypeDef * hdma)1768 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
1769 {
1770 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1771
1772 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1773 hdac->ConvCpltCallbackCh1(hdac);
1774 #else
1775 HAL_DAC_ConvCpltCallbackCh1(hdac);
1776 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1777
1778 hdac->State = HAL_DAC_STATE_READY;
1779 }
1780
1781 /**
1782 * @brief DMA half transfer complete callback.
1783 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1784 * the configuration information for the specified DMA module.
1785 * @retval None
1786 */
DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef * hdma)1787 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
1788 {
1789 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1790 /* Conversion complete callback */
1791 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1792 hdac->ConvHalfCpltCallbackCh1(hdac);
1793 #else
1794 HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
1795 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1796 }
1797
1798 /**
1799 * @brief DMA error callback
1800 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1801 * the configuration information for the specified DMA module.
1802 * @retval None
1803 */
DAC_DMAErrorCh1(DMA_HandleTypeDef * hdma)1804 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
1805 {
1806 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1807
1808 /* Set DAC error code to DMA error */
1809 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
1810
1811 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1812 hdac->ErrorCallbackCh1(hdac);
1813 #else
1814 HAL_DAC_ErrorCallbackCh1(hdac);
1815 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1816
1817 hdac->State = HAL_DAC_STATE_READY;
1818 }
1819
1820 /**
1821 * @}
1822 */
1823
1824 /**
1825 * @}
1826 */
1827
1828 #endif /* DAC1 */
1829
1830 #endif /* HAL_DAC_MODULE_ENABLED */
1831 /**
1832 * @}
1833 */
1834
