1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_adc_ex.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Converter (ADC)
7 * peripheral:
8 * + Operation functions
9 * ++ Start, stop, get result of conversions of ADC group injected,
10 * using 2 possible modes: polling, interruption.
11 * ++ Calibration
12 * +++ ADC automatic self-calibration
13 * +++ Calibration factors get or set
14 * ++ Multimode feature when available
15 * + Control functions
16 * ++ Channels configuration on ADC group injected
17 * + State functions
18 * ++ ADC group injected contexts queue management
19 * Other functions (generic functions) are available in file
20 * "stm32u5xx_hal_adc.c".
21 *
22 ******************************************************************************
23 * @attention
24 *
25 * Copyright (c) 2021 STMicroelectronics.
26 * All rights reserved.
27 *
28 * This software is licensed under terms that can be found in the LICENSE file
29 * in the root directory of this software component.
30 * If no LICENSE file comes with this software, it is provided AS-IS.
31 *
32 ******************************************************************************
33 @verbatim
34 [..]
35 (@) Sections "ADC peripheral features" and "How to use this driver" are
36 available in file of generic functions "stm32u5xx_hal_adc.c".
37 [..]
38 @endverbatim
39 ******************************************************************************
40 */
41
42 /* Includes ------------------------------------------------------------------*/
43 #include "stm32u5xx_hal.h"
44
45 /** @addtogroup STM32U5xx_HAL_Driver
46 * @{
47 */
48
49 /** @defgroup ADCEx ADCEx
50 * @brief ADC Extended HAL module driver
51 * @{
52 */
53
54 #ifdef HAL_ADC_MODULE_ENABLED
55
56 /* Private typedef -----------------------------------------------------------*/
57 /* Private define ------------------------------------------------------------*/
58
59 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
60 * @{
61 */
62
63 #define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
64 ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
65 ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
66 once the ADC is enabled */
67
68 /* Fixed timeout value for ADC calibration. */
69 /* Values defined to be higher than worst cases: maximum ratio between ADC */
70 /* and CPU clock frequencies. */
71 /* Example of profile low frequency : ADC frequency minimum 140kHz (cf */
72 /* datasheet for ADC4), CPU frequency 160MHz. */
73 /* Calibration time max = 31849 / fADC (refer to datasheet) */
74 /* = 36M CPU cycles */
75 #define ADC_CALIBRATION_TIMEOUT (36400000U) /*!< ADC calibration time-out value */
76
77 /**
78 * @}
79 */
80
81 /* Private macro -------------------------------------------------------------*/
82 /* Private variables ---------------------------------------------------------*/
83 /* Private function prototypes -----------------------------------------------*/
84 /* Exported functions --------------------------------------------------------*/
85
86 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
87 * @{
88 */
89
90 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
91 * @brief Extended IO operation functions
92 *
93 @verbatim
94 ===============================================================================
95 ##### IO operation functions #####
96 ===============================================================================
97 [..] This section provides functions allowing to:
98
99 (+) Perform the ADC self-calibration for single or differential ending.
100 (+) Get calibration factors for single or differential ending.
101 (+) Set calibration factors for single or differential ending.
102
103 (+) Start conversion of ADC group injected.
104 (+) Stop conversion of ADC group injected.
105 (+) Poll for conversion complete on ADC group injected.
106 (+) Get result of ADC group injected channel conversion.
107 (+) Start conversion of ADC group injected and enable interruptions.
108 (+) Stop conversion of ADC group injected and disable interruptions.
109
110 (+) When multimode feature is available, start multimode and enable DMA transfer.
111 (+) Stop multimode and disable ADC DMA transfer.
112 (+) Get result of multimode conversion.
113
114 @endverbatim
115 * @{
116 */
117
118 /**
119 * @brief Perform an ADC automatic self-calibration
120 * Calibration prerequisite: ADC must be disabled (execute this
121 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
122 * @param hadc ADC handle
123 * @param CalibrationMode Selection of calibration offset or
124 * linear calibration offset.
125 * @arg ADC_CALIB_OFFSET Channel in mode calibration offset
126 * @arg ADC_CALIB_OFFSET_LINEARITY Channel in mode linear calibration offset
127 * @param SingleDiff Selection of single-ended or differential input
128 * This parameter can be one of the following values:
129 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
130 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
131 * @retval HAL status
132 */
HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef * hadc,uint32_t CalibrationMode,uint32_t SingleDiff)133 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
134 {
135 HAL_StatusTypeDef tmp_hal_status;
136 __IO uint32_t wait_loop_index = 0UL;
137 uint32_t backup_setting_cfgr1;
138 uint32_t backup_setting_pwrr;
139
140 UNUSED(SingleDiff); /* STM32U5 calibration is not making difference between Single and Diff ended */
141 /* We keep this to be inligne with old products API and for any further use */
142
143 /* Check the parameters */
144 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
145 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
146
147 __HAL_LOCK(hadc);
148
149 /* Calibration prerequisite: ADC must be disabled. */
150
151 /* Disable the ADC (if not already disabled) */
152 tmp_hal_status = ADC_Disable(hadc);
153
154 /* Check if ADC is effectively disabled */
155 if (tmp_hal_status == HAL_OK)
156 {
157 /* Set ADC state */
158 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL);
159
160 if (hadc->Instance == ADC4)
161 {
162 /* Manage settings impacting calibration */
163 /* - Disable ADC mode auto power-off */
164 /* - Disable ADC DMA transfer request during calibration */
165 /* Note: Specificity of this STM32 series: Calibration factor is */
166 /* available in data register and also transferred by DMA. */
167 /* To not insert ADC calibration factor among ADC conversion data */
168 /* in array variable, DMA transfer must be disabled during */
169 /* calibration. */
170 backup_setting_pwrr = READ_BIT(hadc->Instance->PWRR, ADC4_PWRR_AUTOFF);
171 backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG);
172 CLEAR_BIT(hadc->Instance->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG);
173 CLEAR_BIT(hadc->Instance->PWRR, ADC4_PWRR_AUTOFF);
174
175 /* Start ADC calibration in mode single-ended */
176 LL_ADC_StartCalibration(hadc->Instance, LL_ADC_CALIB_OFFSET);
177
178 /* Wait for calibration completion */
179 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
180 {
181 wait_loop_index++;
182 if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
183 {
184 /* Update ADC state machine to error */
185 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
186
187 __HAL_UNLOCK(hadc);
188
189 return HAL_ERROR;
190 }
191 }
192
193 /* Restore configuration after calibration */
194 SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1);
195 SET_BIT(hadc->Instance->PWRR, backup_setting_pwrr);
196 }
197 else /* ADC instance ADC1 or ADC2 */
198 {
199 /* Get device information */
200 uint32_t dev_id = READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID);
201 uint32_t rev_id = READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos;
202
203 /* Assess whether extended calibration is available on the selected device */
204 if ((dev_id == 0x455UL) || (dev_id == 0x476UL)
205 || (((dev_id == 0x481UL) || (dev_id == 0x482UL)) && (rev_id >= 0x3000UL)))
206 {
207 /* Perform extended calibration */
208 /* Refer to ref manual for extended calibration procedure details */
209 tmp_hal_status = ADC_Enable(hadc);
210
211 if (tmp_hal_status == HAL_OK)
212 {
213 /* Use a Data Memory Barrier instruction to avoid synchronization issues when accessing ADC registers */
214 MODIFY_REG(hadc->Instance->CR, ADC_CR_CALINDEX, 0x9UL << ADC_CR_CALINDEX_Pos);
215 __DMB();
216 MODIFY_REG(hadc->Instance->CALFACT2, 0xFFFFFF00UL, 0x03021100UL);
217 __DMB();
218 SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF);
219
220 tmp_hal_status = ADC_Disable(hadc);
221
222 if (CalibrationMode == ADC_CALIB_OFFSET_LINEARITY)
223 {
224 MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALLIN | ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADCALLIN);
225 }
226
227 MODIFY_REG(hadc->Instance->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADCAL);
228
229 /* Wait for calibration completion */
230 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
231 {
232 wait_loop_index++;
233 if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
234 {
235 /* Update ADC state machine to error */
236 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
237
238 __HAL_UNLOCK(hadc);
239
240 return HAL_ERROR;
241 }
242 }
243 }
244 }
245 else
246 {
247 /* Start ADC calibration in mode single-ended or differential */
248 LL_ADC_StartCalibration(hadc->Instance, CalibrationMode);
249
250 /* Wait for calibration completion */
251 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
252 {
253 wait_loop_index++;
254 if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
255 {
256 /* Update ADC state machine to error */
257 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
258
259 __HAL_UNLOCK(hadc);
260
261 return HAL_ERROR;
262 }
263 }
264 }
265 }
266
267 /* Set ADC state */
268 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
269 }
270 else /* ADC not disabled */
271 {
272 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
273
274 /* Note: No need to update variable "tmp_hal_status" here: already set */
275 /* to state "HAL_ERROR" by function disabling the ADC. */
276 }
277
278 __HAL_UNLOCK(hadc);
279
280 return tmp_hal_status;
281 }
282
283 /**
284 * @brief Get the calibration factor.
285 * @param hadc ADC handle.
286 * @param SingleDiff This parameter can be only:
287 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
288 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
289 * @retval Calibration value.
290 */
HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef * hadc,uint32_t SingleDiff)291 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
292 {
293 uint32_t Calib_Val = 0UL;
294 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
295
296 /* Check the parameters */
297 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
298 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
299
300 if (hadc->Instance != ADC4)
301 {
302 tmp_hal_status = ADC_Enable(hadc); /* ADC need to be enabled to perform calibration for ADC1/2 and not for ADC4 */
303 }
304
305 if (tmp_hal_status == HAL_OK)
306 {
307 /* Return the selected ADC calibration value */
308 Calib_Val = LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff);
309 }
310
311 if (hadc->Instance != ADC4)
312 {
313 tmp_hal_status = ADC_Disable(hadc);
314 UNUSED(tmp_hal_status);
315 }
316 return Calib_Val;
317 }
318
319 /**
320 * @brief Get the calibration factor from automatic conversion result
321 * @param hadc ADC handle
322 * @param pLinearCalib_Buffer Linear calibration factor (table of 9 elements)
323 * @retval HAL state
324 */
HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef * hadc,uint32_t * pLinearCalib_Buffer)325 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *pLinearCalib_Buffer)
326 {
327 uint32_t cnt;
328 HAL_StatusTypeDef tmp_hal_status;
329
330 /* Check the parameters */
331 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
332
333 if (hadc->Instance != ADC4)
334 {
335 /* Enable the ADC to be able to read the linear calibration factor */
336 tmp_hal_status = ADC_Enable(hadc);
337
338 if (tmp_hal_status == HAL_OK)
339 {
340 /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1",
341 therefore they are not cleared in this function. */
342 SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF);
343
344 for (cnt = 0UL; cnt <= 8UL; cnt++)
345 {
346 MODIFY_REG(hadc->Instance->CR,
347 (ADC_CR_CALINDEX),
348 (cnt << ADC_CR_CALINDEX_Pos));
349 pLinearCalib_Buffer[cnt] = (uint32_t)(READ_BIT(hadc->Instance->CALFACT2, ADC_CALFACT2_CALFACT_Msk));
350 }
351 }
352
353 tmp_hal_status = ADC_Disable(hadc);
354 }
355 else
356 {
357 /* ADC linear calibration not available on ADC4 */
358 tmp_hal_status = HAL_ERROR;
359 }
360
361 return tmp_hal_status;
362 }
363
364 /**
365 * @brief Set the calibration factor to overwrite automatic conversion result.
366 * ADC must be enabled and no conversion is ongoing.
367 * @param hadc ADC handle
368 * @param SingleDiff This parameter can be only:
369 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
370 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
371 * @param CalibrationFactor Calibration factor (range 0xFFFF for ADC1 and ADC2, range 0x7F for ADC4)
372 * @retval HAL state
373 */
HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef * hadc,uint32_t SingleDiff,uint32_t CalibrationFactor)374 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
375 uint32_t CalibrationFactor)
376 {
377 HAL_StatusTypeDef tmp_hal_status;
378 uint32_t tmp_adc_is_conversion_on_going_regular;
379 uint32_t tmp_adc_is_conversion_on_going_injected;
380
381 /* Check the parameters */
382 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
383 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
384 assert_param(IS_ADC_CALFACT(CalibrationFactor));
385
386 __HAL_LOCK(hadc);
387
388 /* Verification of hardware constraints before modifying the calibration */
389 /* factors register: ADC must be enabled, no conversion on going. */
390 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
391 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
392
393 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
394 && (tmp_adc_is_conversion_on_going_injected == 0UL)
395 )
396 {
397 /* Enable the ADC to be able to set the calibration factor */
398 tmp_hal_status = ADC_Enable(hadc);
399
400 if (tmp_hal_status == HAL_OK)
401 {
402 /* Set the selected ADC calibration value */
403 LL_ADC_SetCalibrationOffsetFactor(hadc->Instance, SingleDiff, CalibrationFactor);
404
405 tmp_hal_status = ADC_Disable(hadc);
406 }
407 }
408 else
409 {
410 /* Update ADC state machine */
411 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
412 /* Update ADC error code */
413 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
414
415 /* Update ADC state machine to error */
416 tmp_hal_status = HAL_ERROR;
417 }
418
419 __HAL_UNLOCK(hadc);
420
421 return tmp_hal_status;
422 }
423
424 /**
425 * @brief Set the linear calibration factor
426 * @param hadc ADC handle
427 * @param pLinearCalib_Buffer Linear calibration factor (table of 9 elements)
428 * @retval HAL state
429 */
HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef * hadc,uint32_t * pLinearCalib_Buffer)430 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *pLinearCalib_Buffer)
431 {
432 uint32_t cnt;
433 HAL_StatusTypeDef tmp_hal_status;
434
435 /* Check the parameters */
436 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
437
438 if (hadc->Instance != ADC4)
439 {
440 tmp_hal_status = ADC_Enable(hadc);
441
442 if (tmp_hal_status == HAL_OK)
443 {
444 /* Note: Bitfields ADC_CALFACT_LATCH_COEF and ADC_CALFACT_CAPTURE_COEF have property "wr1",
445 therefore they are not cleared in this function. */
446 for (cnt = 0UL; cnt <= 7UL; cnt++)
447 {
448 MODIFY_REG(hadc->Instance->CR,
449 (ADC_CR_CALINDEX),
450 (cnt << ADC_CR_CALINDEX_Pos));
451
452 if (cnt == 7UL)
453 {
454 /* Specific case for linearity factor 7 and internal offset: must be concatenated */
455 MODIFY_REG(hadc->Instance->CALFACT2,
456 ADC_CALFACT2_CALFACT,
457 pLinearCalib_Buffer[cnt] | ((pLinearCalib_Buffer[cnt + 1UL] & 0xFF000000UL) >> 8UL));
458 }
459 else
460 {
461 MODIFY_REG(hadc->Instance->CALFACT2, ADC_CALFACT2_CALFACT, pLinearCalib_Buffer[cnt]);
462 }
463 }
464
465 SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF);
466 CLEAR_BIT(hadc->Instance->CR, ADC_CR_CALINDEX);
467
468 tmp_hal_status = ADC_Disable(hadc);
469 }
470 }
471 else
472 {
473 /* ADC linear calibration not available on ADC4 */
474 tmp_hal_status = HAL_ERROR;
475 }
476
477 return tmp_hal_status;
478 }
479
480 /**
481 * @brief Enable ADC, start conversion of injected group.
482 * @note Interruptions enabled in this function: None.
483 * @note Case of multimode enabled when multimode feature is available:
484 * HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
485 * then for ADC master.
486 * For ADC slave, ADC is enabled only (conversion is not started).
487 * For ADC master, ADC is enabled and multimode conversion is started.
488 * @param hadc ADC handle.
489 * @retval HAL status
490 */
HAL_ADCEx_InjectedStart(ADC_HandleTypeDef * hadc)491 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
492 {
493 HAL_StatusTypeDef tmp_hal_status;
494 #if defined(ADC_MULTIMODE_SUPPORT)
495 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
496 #endif /* ADC_MULTIMODE_SUPPORT */
497
498 /* Check the parameters */
499 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
500
501 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
502 {
503 tmp_hal_status = HAL_BUSY;
504 }
505 else
506 {
507 /* In case of software trigger detection enabled, JQDIS must be set
508 (which can be done only if ADSTART and JADSTART are both cleared).
509 If JQDIS is not set at that point, returns an error
510 - since software trigger detection is disabled. User needs to
511 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
512 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
513 the queue is empty */
514
515 __HAL_LOCK(hadc);
516
517 /* Enable the ADC peripheral */
518 tmp_hal_status = ADC_Enable(hadc);
519
520 /* Start conversion if ADC is effectively enabled */
521 if (tmp_hal_status == HAL_OK)
522 {
523 /* Clear ADC error code */
524 ADC_CLEAR_ERRORCODE(hadc);
525
526 /* Set ADC state */
527 /* - Clear state bitfield related to injected group conversion results */
528 /* - Set state bitfield related to injected operation */
529 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
530
531 #if defined(ADC_MULTIMODE_SUPPORT)
532 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
533 - if ADC instance is master or if multimode feature is not available
534 - if multimode setting is disabled (ADC instance slave in independent mode) */
535 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
536 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
537 )
538 {
539 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
540 }
541 #endif /* ADC_MULTIMODE_SUPPORT */
542
543 /* Clear ADC group injected group conversion flag */
544 /* (To ensure of no unknown state from potential previous ADC operations) */
545 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
546
547 /* Unlock before starting ADC conversions: in case of potential */
548 /* interruption, to let the process to ADC IRQ Handler. */
549 __HAL_UNLOCK(hadc);
550
551 /* Enable conversion of injected group, if automatic injected conversion */
552 /* is disabled. */
553 /* If software start has been selected, conversion starts immediately. */
554 /* If external trigger has been selected, conversion will start at next */
555 /* trigger event. */
556 /* Case of multimode enabled (when multimode feature is available): */
557 /* if ADC is slave, */
558 /* - ADC is enabled only (conversion is not started), */
559 /* - if multimode only concerns regular conversion, ADC is enabled */
560 /* and conversion is started. */
561 /* If ADC is master or independent, */
562 /* - ADC is enabled and conversion is started. */
563 #if defined(ADC_MULTIMODE_SUPPORT)
564 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
565 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
566 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
567 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
568 )
569 {
570 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
571 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
572 {
573 LL_ADC_INJ_StartConversion(hadc->Instance);
574 }
575 }
576 else
577 {
578 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
579 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
580 }
581 #else
582 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
583 {
584 LL_ADC_INJ_StartConversion(hadc->Instance);
585 }
586 #endif /* ADC_MULTIMODE_SUPPORT */
587
588 }
589 else
590 {
591 __HAL_UNLOCK(hadc);
592 }
593 }
594
595 return tmp_hal_status;
596 }
597
598 /**
599 * @brief Stop conversion of injected channels. Disable ADC peripheral if
600 * no regular conversion is on going.
601 * @note If ADC must be disabled and if conversion is on going on
602 * regular group, function HAL_ADC_Stop must be used to stop both
603 * injected and regular groups, and disable the ADC.
604 * @note If injected group mode auto-injection is enabled,
605 * function HAL_ADC_Stop must be used.
606 * @note In case of multimode enabled (when multimode feature is available),
607 * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
608 * For ADC master, conversion is stopped and ADC is disabled.
609 * For ADC slave, ADC is disabled only (conversion stop of ADC master
610 * has already stopped conversion of ADC slave).
611 * @param hadc ADC handle.
612 * @retval HAL status
613 */
HAL_ADCEx_InjectedStop(ADC_HandleTypeDef * hadc)614 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
615 {
616 HAL_StatusTypeDef tmp_hal_status;
617
618 /* Check the parameters */
619 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
620
621 __HAL_LOCK(hadc);
622
623 /* 1. Stop potential conversion on going on injected group only. */
624 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
625
626 /* Disable ADC peripheral if injected conversions are effectively stopped */
627 /* and if no conversion on regular group is on-going */
628 if (tmp_hal_status == HAL_OK)
629 {
630 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
631 {
632 /* 2. Disable the ADC peripheral */
633 tmp_hal_status = ADC_Disable(hadc);
634
635 /* Check if ADC is effectively disabled */
636 if (tmp_hal_status == HAL_OK)
637 {
638 /* Set ADC state */
639 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
640 }
641 }
642 /* Conversion on injected group is stopped, but ADC not disabled since */
643 /* conversion on regular group is still running. */
644 else
645 {
646 /* Set ADC state */
647 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
648 }
649 }
650
651 __HAL_UNLOCK(hadc);
652
653 return tmp_hal_status;
654 }
655
656 /**
657 * @brief Wait for injected group conversion to be completed.
658 * @param hadc ADC handle
659 * @param Timeout Timeout value in millisecond.
660 * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
661 * checked and cleared depending on AUTDLY bit status.
662 * @retval HAL status
663 */
HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)664 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
665 {
666 uint32_t tickstart;
667 uint32_t tmp_flag_end;
668 uint32_t tmp_adc_inj_is_trigger_source_sw_start;
669 uint32_t tmp_adc_reg_is_trigger_source_sw_start;
670 uint32_t tmp_cfgr;
671 #if defined(ADC_MULTIMODE_SUPPORT)
672 const ADC_TypeDef *tmp_adc_master;
673 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
674 #endif /* ADC_MULTIMODE_SUPPORT */
675
676 /* Check the parameters */
677 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
678
679 /* If end of sequence selected */
680 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
681 {
682 tmp_flag_end = ADC_FLAG_JEOS;
683 }
684 else /* end of conversion selected */
685 {
686 tmp_flag_end = ADC_FLAG_JEOC;
687 }
688
689 tickstart = HAL_GetTick();
690
691 /* Wait until End of Conversion or Sequence flag is raised */
692 while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
693 {
694 /* Check if timeout is disabled (set to infinite wait) */
695 if (Timeout != HAL_MAX_DELAY)
696 {
697 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
698 {
699 if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
700 {
701 /* Update ADC state machine to timeout */
702 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
703
704 /* Process unlocked */
705 __HAL_UNLOCK(hadc);
706
707 return HAL_TIMEOUT;
708 }
709 }
710 }
711 }
712
713 /* Retrieve ADC configuration */
714 tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
715 tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
716 /* Get relevant register CFGR in ADC instance of ADC master or slave */
717 /* in function of multimode state (for devices with multimode */
718 /* available). */
719 #if defined(ADC_MULTIMODE_SUPPORT)
720 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
721 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
722 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
723 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
724 )
725 {
726 tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
727 }
728 else
729 {
730 tmp_adc_master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
731 tmp_cfgr = READ_REG(tmp_adc_master->CFGR1);
732 }
733 #else
734 tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
735 #endif /* ADC_MULTIMODE_SUPPORT */
736
737 /* Update ADC state machine */
738 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
739
740 /* Determine whether any further conversion upcoming on group injected */
741 /* by external trigger or by automatic injected conversion */
742 /* from group regular. */
743 if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
744 ((READ_BIT(tmp_cfgr, ADC_CFGR1_JAUTO) == 0UL) &&
745 ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
746 (READ_BIT(tmp_cfgr, ADC_CFGR1_CONT) == 0UL))))
747 {
748 /* Check whether end of sequence is reached */
749 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
750 {
751 /* Particular case if injected contexts queue is enabled: */
752 /* when the last context has been fully processed, JSQR is reset */
753 /* by the hardware. Even if no injected conversion is planned to come */
754 /* (queue empty, triggers are ignored), it can start again */
755 /* immediately after setting a new context (JADSTART is still set). */
756 /* Therefore, state of HAL ADC injected group is kept to busy. */
757
758 /* Set ADC state */
759 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
760
761 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
762 {
763 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
764 }
765 }
766 }
767
768 /* Clear polled flag */
769 if (tmp_flag_end == ADC_FLAG_JEOS)
770 {
771 /* Clear end of sequence JEOS flag of injected group if low power feature */
772 /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
773 /* For injected groups, no new conversion will start before JEOS is */
774 /* cleared. */
775 if (READ_BIT(tmp_cfgr, ADC_CFGR1_AUTDLY) == 0UL)
776 {
777 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
778 }
779 }
780 else
781 {
782 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
783 }
784
785 return HAL_OK;
786 }
787
788 /**
789 * @brief Enable ADC, start conversion of injected group with interruption.
790 * @note Interruptions enabled in this function according to initialization
791 * setting : JEOC (end of conversion) or JEOS (end of sequence)
792 * @note Case of multimode enabled (when multimode feature is enabled):
793 * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
794 * then for ADC master.
795 * For ADC slave, ADC is enabled only (conversion is not started).
796 * For ADC master, ADC is enabled and multimode conversion is started.
797 * @param hadc ADC handle.
798 * @retval HAL status.
799 */
HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef * hadc)800 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
801 {
802 HAL_StatusTypeDef tmp_hal_status;
803 #if defined(ADC_MULTIMODE_SUPPORT)
804 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
805 #endif /* ADC_MULTIMODE_SUPPORT */
806
807 /* Check the parameters */
808 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
809
810 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
811 {
812 tmp_hal_status = HAL_BUSY;
813 }
814 else
815 {
816 /* In case of software trigger detection enabled, JQDIS must be set
817 (which can be done only if ADSTART and JADSTART are both cleared).
818 If JQDIS is not set at that point, returns an error
819 - since software trigger detection is disabled. User needs to
820 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
821 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
822 the queue is empty */
823
824 __HAL_LOCK(hadc);
825
826 /* Enable the ADC peripheral */
827 tmp_hal_status = ADC_Enable(hadc);
828
829 /* Start conversion if ADC is effectively enabled */
830 if (tmp_hal_status == HAL_OK)
831 {
832 /* Clear ADC error code */
833 ADC_CLEAR_ERRORCODE(hadc);
834
835 /* Set ADC state */
836 /* - Clear state bitfield related to injected group conversion results */
837 /* - Set state bitfield related to injected operation */
838 ADC_STATE_CLR_SET(hadc->State,
839 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
840 HAL_ADC_STATE_INJ_BUSY);
841
842 #if defined(ADC_MULTIMODE_SUPPORT)
843 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
844 - if ADC instance is master or if multimode feature is not available
845 - if multimode setting is disabled (ADC instance slave in independent mode) */
846 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
847 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
848 )
849 {
850 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
851 }
852 #endif /* ADC_MULTIMODE_SUPPORT */
853
854 /* Clear ADC group injected group conversion flag */
855 /* (To ensure of no unknown state from potential previous ADC operations) */
856 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
857
858 /* Unlock before starting ADC conversions: in case of potential */
859 /* interruption, to let the process to ADC IRQ Handler. */
860 __HAL_UNLOCK(hadc);
861
862 /* Enable ADC end of conversion interrupt */
863 switch (hadc->Init.EOCSelection)
864 {
865 case ADC_EOC_SEQ_CONV:
866 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
867 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
868 break;
869 /* case ADC_EOC_SINGLE_CONV */
870 default:
871 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
872 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
873 break;
874 }
875
876 /* Enable conversion of injected group, if automatic injected conversion */
877 /* is disabled. */
878 /* If software start has been selected, conversion starts immediately. */
879 /* If external trigger has been selected, conversion will start at next */
880 /* trigger event. */
881 /* Case of multimode enabled (when multimode feature is available): */
882 /* if ADC is slave, */
883 /* - ADC is enabled only (conversion is not started), */
884 /* - if multimode only concerns regular conversion, ADC is enabled */
885 /* and conversion is started. */
886 /* If ADC is master or independent, */
887 /* - ADC is enabled and conversion is started. */
888 #if defined(ADC_MULTIMODE_SUPPORT)
889 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
890 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
891 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
892 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
893 )
894 {
895 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
896 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
897 {
898 LL_ADC_INJ_StartConversion(hadc->Instance);
899 }
900 }
901 else
902 {
903 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
904 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
905 }
906 #else
907 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
908 {
909 LL_ADC_INJ_StartConversion(hadc->Instance);
910 }
911 #endif /* ADC_MULTIMODE_SUPPORT */
912
913 }
914 else
915 {
916 __HAL_UNLOCK(hadc);
917 }
918 }
919
920 return tmp_hal_status;
921 }
922
923 /**
924 * @brief Stop conversion of injected channels, disable interruption of
925 * end-of-conversion. Disable ADC peripheral if no regular conversion
926 * is on going.
927 * @note If ADC must be disabled and if conversion is on going on
928 * regular group, function HAL_ADC_Stop must be used to stop both
929 * injected and regular groups, and disable the ADC.
930 * @note If injected group mode auto-injection is enabled,
931 * function HAL_ADC_Stop must be used.
932 * @note Case of multimode enabled (when multimode feature is available):
933 * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
934 * then for ADC slave.
935 * For ADC master, conversion is stopped and ADC is disabled.
936 * For ADC slave, ADC is disabled only (conversion stop of ADC master
937 * has already stopped conversion of ADC slave).
938 * @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
939 * @param hadc ADC handle
940 * @retval HAL status
941 */
HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef * hadc)942 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
943 {
944 HAL_StatusTypeDef tmp_hal_status;
945
946 /* Check the parameters */
947 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
948
949 __HAL_LOCK(hadc);
950
951 /* 1. Stop potential conversion on going on injected group only. */
952 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
953
954 /* Disable ADC peripheral if injected conversions are effectively stopped */
955 /* and if no conversion on the other group (regular group) is intended to */
956 /* continue. */
957 if (tmp_hal_status == HAL_OK)
958 {
959 /* Disable ADC end of conversion interrupt for injected channels */
960 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS));
961
962 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
963 {
964 /* 2. Disable the ADC peripheral */
965 tmp_hal_status = ADC_Disable(hadc);
966
967 /* Check if ADC is effectively disabled */
968 if (tmp_hal_status == HAL_OK)
969 {
970 /* Set ADC state */
971 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
972 }
973 }
974 /* Conversion on injected group is stopped, but ADC not disabled since */
975 /* conversion on regular group is still running. */
976 else
977 {
978 /* Set ADC state */
979 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
980 }
981 }
982
983 __HAL_UNLOCK(hadc);
984
985 return tmp_hal_status;
986 }
987
988 #if defined(ADC_MULTIMODE_SUPPORT)
989 /**
990 * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
991 * @note Multimode must have been previously configured using
992 * HAL_ADCEx_MultiModeConfigChannel() function.
993 * Interruptions enabled in this function:
994 * overrun, DMA half transfer, DMA transfer complete.
995 * Each of these interruptions has its dedicated callback function.
996 * @note State field of Slave ADC handle is not updated in this configuration:
997 * user should not rely on it for information related to Slave regular
998 * conversions.
999 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
1000 * @param pData Destination Buffer address.
1001 * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
1002 * @retval HAL status
1003 */
HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef * hadc,const uint32_t * pData,uint32_t Length)1004 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length)
1005 {
1006 HAL_StatusTypeDef tmp_hal_status;
1007 ADC_HandleTypeDef tmp_hadc_slave;
1008 ADC_Common_TypeDef *tmp_adc_common;
1009 uint32_t LengthInBytes;
1010 DMA_NodeConfTypeDef node_conf;
1011
1012 /* Check the parameters */
1013 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1014 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1015 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
1016
1017 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
1018 {
1019 tmp_hal_status = HAL_BUSY;
1020 }
1021 else
1022 {
1023 __HAL_LOCK(hadc);
1024
1025 /* Temporary handle minimum initialization */
1026 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
1027 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
1028
1029 /* Set a temporary handle of the ADC slave associated to the ADC master */
1030 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
1031
1032 if (tmp_hadc_slave.Instance == NULL)
1033 {
1034 /* Set ADC state */
1035 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1036 __HAL_UNLOCK(hadc);
1037 return HAL_ERROR;
1038 }
1039
1040 /* Enable the ADC peripherals: master and slave (in case if not already */
1041 /* enabled previously) */
1042 tmp_hal_status = ADC_Enable(hadc);
1043 if (tmp_hal_status == HAL_OK)
1044 {
1045 /* Reinitialize the LowPowerAutoPowerOff parameter from master to slave */
1046 tmp_hadc_slave.Init.LowPowerAutoPowerOff = hadc->Init.LowPowerAutoPowerOff;
1047 tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
1048 }
1049
1050 /* Start multimode conversion of ADCs pair */
1051 if (tmp_hal_status == HAL_OK)
1052 {
1053 /* Set ADC state */
1054 ADC_STATE_CLR_SET(hadc->State,
1055 (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR \
1056 | HAL_ADC_STATE_REG_EOSMP),
1057 HAL_ADC_STATE_REG_BUSY);
1058
1059 ADC_CLEAR_ERRORCODE(hadc);
1060
1061 /* Set the DMA transfer complete callback */
1062 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
1063
1064 /* Set the DMA half transfer complete callback */
1065 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
1066
1067 /* Set the DMA error callback */
1068 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
1069
1070 /* Pointer to the common control register */
1071 tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
1072
1073 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
1074 /* start (in case of SW start): */
1075
1076 /* Clear regular group conversion flag and overrun flag */
1077 /* (To ensure of no unknown state from potential previous ADC operations) */
1078 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1079
1080 /* Unlock before starting ADC conversions: in case of potential */
1081 /* interruption, to let the process to ADC IRQ Handler. */
1082 __HAL_UNLOCK(hadc);
1083
1084 /* Enable ADC overrun interrupt */
1085 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1086
1087 /* Start the DMA channel */
1088 /* Check linkedlist mode */
1089 if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1090 {
1091 if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
1092 {
1093 /* Length should be converted to number of bytes */
1094 if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK)
1095 {
1096 return HAL_ERROR;
1097 }
1098
1099 /* Length should be converted to number of bytes */
1100 if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
1101 {
1102 /* Word -> Bytes */
1103 LengthInBytes = Length * 4U;
1104 }
1105 else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
1106 {
1107 /* Halfword -> Bytes */
1108 LengthInBytes = Length * 2U;
1109 }
1110 else /* Bytes */
1111 {
1112 /* Same size already expressed in Bytes */
1113 LengthInBytes = Length;
1114 }
1115
1116 hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes;
1117 hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
1118 (uint32_t)&tmp_adc_common->CDR;
1119 hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
1120 tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
1121 }
1122 else
1123 {
1124 tmp_hal_status = HAL_ERROR;
1125 }
1126 }
1127 else
1128 {
1129 /* Length should be converted to number of bytes */
1130 if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
1131 {
1132 /* Word -> Bytes */
1133 LengthInBytes = Length * 4U;
1134 }
1135 else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
1136 {
1137 /* Halfword -> Bytes */
1138 LengthInBytes = Length * 2U;
1139 }
1140 else /* Bytes */
1141 {
1142 /* Same size already expressed in Bytes */
1143 LengthInBytes = Length;
1144 }
1145
1146 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmp_adc_common->CDR, (uint32_t)pData, \
1147 LengthInBytes);
1148 }
1149
1150 /* Enable conversion of regular group. */
1151 /* If software start has been selected, conversion starts immediately. */
1152 /* If external trigger has been selected, conversion will start at next */
1153 /* trigger event. */
1154 /* Start ADC group regular conversion */
1155 LL_ADC_REG_StartConversion(hadc->Instance);
1156 }
1157 else
1158 {
1159 __HAL_UNLOCK(hadc);
1160 }
1161 }
1162
1163 return tmp_hal_status;
1164 }
1165
1166 /**
1167 * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
1168 * @note Multimode is kept enabled after this function. MultiMode DMA bits
1169 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
1170 * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
1171 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
1172 * resort to HAL_ADCEx_DisableMultiMode() API.
1173 * @note In case of DMA configured in circular mode, function
1174 * HAL_ADC_Stop_DMA() must be called after this function with handle of
1175 * ADC slave, to properly disable the DMA channel.
1176 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
1177 * @retval HAL status
1178 */
HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef * hadc)1179 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
1180 {
1181 HAL_StatusTypeDef tmp_hal_status;
1182 uint32_t tickstart;
1183 ADC_HandleTypeDef tmp_hadc_slave;
1184 uint32_t tmp_hadc_slave_conversion_on_going;
1185 HAL_StatusTypeDef tmp_hadc_slave_disable_status;
1186
1187 /* Check the parameters */
1188 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1189
1190 __HAL_LOCK(hadc);
1191
1192 /* 1. Stop potential multimode conversion on going, on regular and injected groups */
1193 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1194
1195 /* Disable ADC peripheral if conversions are effectively stopped */
1196 if (tmp_hal_status == HAL_OK)
1197 {
1198 /* Temporary handle minimum initialization */
1199 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
1200 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
1201
1202 /* Set a temporary handle of the ADC slave associated to the ADC master */
1203 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
1204
1205 if (tmp_hadc_slave.Instance == NULL)
1206 {
1207 /* Update ADC state machine to error */
1208 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1209
1210 __HAL_UNLOCK(hadc);
1211
1212 return HAL_ERROR;
1213 }
1214
1215 /* Procedure to disable the ADC peripheral: wait for conversions */
1216 /* effectively stopped (ADC master and ADC slave), then disable ADC */
1217
1218 /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
1219 tickstart = HAL_GetTick();
1220
1221 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1222 while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1223 || (tmp_hadc_slave_conversion_on_going == 1UL)
1224 )
1225 {
1226 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
1227 {
1228 /* New check to avoid false timeout detection in case of preemption */
1229 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1230
1231 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1232 || (tmp_hadc_slave_conversion_on_going == 1UL)
1233 )
1234 {
1235 /* Update ADC state machine to error */
1236 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1237
1238 /* Process unlocked */
1239 __HAL_UNLOCK(hadc);
1240
1241 return HAL_ERROR;
1242 }
1243 }
1244
1245 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1246 }
1247
1248 /* Disable the DMA channel (in case of DMA in circular mode or stop */
1249 /* while DMA transfer is on going) */
1250 /* Note: DMA channel of ADC slave should be stopped after this function */
1251 /* with HAL_ADC_Stop_DMA() API. */
1252 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1253
1254 /* Check if DMA channel effectively disabled */
1255 if (tmp_hal_status == HAL_ERROR)
1256 {
1257 /* Update ADC state machine to error */
1258 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1259 }
1260
1261 /* Disable ADC overrun interrupt */
1262 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1263
1264 /* 2. Disable the ADC peripherals: master and slave */
1265 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
1266 /* memory a potential failing status. */
1267 if (tmp_hal_status == HAL_OK)
1268 {
1269 tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave);
1270 if ((ADC_Disable(hadc) == HAL_OK) &&
1271 (tmp_hadc_slave_disable_status == HAL_OK))
1272 {
1273 tmp_hal_status = HAL_OK;
1274 }
1275 }
1276 else
1277 {
1278 /* In case of error, attempt to disable ADC master and slave without status assert */
1279 (void) ADC_Disable(hadc);
1280 (void) ADC_Disable(&tmp_hadc_slave);
1281 }
1282
1283 /* Set ADC state (ADC master) */
1284 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
1285 }
1286
1287 __HAL_UNLOCK(hadc);
1288
1289 return tmp_hal_status;
1290 }
1291
1292 /**
1293 * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
1294 * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
1295 * @retval The converted data values.
1296 */
HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef * hadc)1297 uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc)
1298 {
1299 const ADC_Common_TypeDef *tmp_adc_common;
1300
1301 /* Check the parameters */
1302 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1303
1304 /* Prevent unused argument(s) compilation warning if no assert_param check */
1305 /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
1306 UNUSED(hadc);
1307
1308 /* Pointer to the common control register */
1309 tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
1310
1311 /* Return the multi mode conversion value */
1312 return tmp_adc_common->CDR;
1313 }
1314
1315 /**
1316 * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
1317 * @note Multimode must have been previously configured using
1318 * HAL_ADCEx_MultiModeConfigChannel() function.
1319 * Interruptions enabled in this function:
1320 * overrun, DMA half transfer, DMA transfer complete.
1321 * Each of these interruptions has its dedicated callback function.
1322 * @note State field of Slave ADC handle is not updated in this configuration:
1323 * user should not rely on it for information related to Slave regular
1324 * conversions.
1325 * @param hadc ADC handle of ADC
1326 * @note - Only ADC master could start the conversion.
1327 * - Two ADC conversions (Master & Slave) per external trig and so two DMA requests.
1328 * @param pData Destination Buffer address.
1329 * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
1330 * @retval HAL status
1331 */
HAL_ADCEx_MultiModeStart_DMA_Data32(ADC_HandleTypeDef * hadc,const uint32_t * pData,uint32_t Length)1332 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA_Data32(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length)
1333 {
1334 HAL_StatusTypeDef tmp_hal_status;
1335 ADC_HandleTypeDef tmp_hadc_slave;
1336 ADC_Common_TypeDef *tmp_adc_common;
1337 uint32_t LengthInBytes;
1338
1339 /* Check the parameters */
1340 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1341 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1342 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
1343
1344 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
1345 {
1346 return HAL_BUSY;
1347 }
1348 else
1349 {
1350 __HAL_LOCK(hadc);
1351
1352 /* Temporary handle minimum initialization */
1353 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
1354 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
1355
1356 /* Set a temporary handle of the ADC slave associated to the ADC master */
1357 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
1358
1359 if (tmp_hadc_slave.Instance == NULL)
1360 {
1361 /* Set ADC state */
1362 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1363
1364 /* Process unlocked */
1365 __HAL_UNLOCK(hadc);
1366
1367 return HAL_ERROR;
1368 }
1369
1370 /* Enable the ADC peripherals: master and slave (in case if not already */
1371 /* enabled previously) */
1372 tmp_hal_status = ADC_Enable(hadc);
1373 if (tmp_hal_status == HAL_OK)
1374 {
1375 /* Reinitialize the LowPowerAutoPowerOff parameter from master to slave */
1376 tmp_hadc_slave.Init.LowPowerAutoPowerOff = hadc->Init.LowPowerAutoPowerOff;
1377 tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
1378 }
1379
1380 /* Start multimode conversion of ADCs pair */
1381 if (tmp_hal_status == HAL_OK)
1382 {
1383 /* Set ADC state */
1384 ADC_STATE_CLR_SET(hadc->State,
1385 (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR \
1386 | HAL_ADC_STATE_REG_EOSMP),
1387 HAL_ADC_STATE_REG_BUSY);
1388
1389 /* Set ADC error code to none */
1390 ADC_CLEAR_ERRORCODE(hadc);
1391
1392 /* Set the DMA transfer complete callback */
1393 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
1394
1395 /* Set the DMA half transfer complete callback */
1396 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
1397
1398 /* Set the DMA error callback */
1399 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
1400
1401 /* Pointer to the common control register */
1402 tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
1403
1404 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
1405 /* start (in case of SW start): */
1406
1407 /* Clear regular group conversion flag and overrun flag */
1408 /* (To ensure of no unknown state from potential previous ADC operations) */
1409 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1410
1411 /* Process unlocked */
1412 /* Unlock before starting ADC conversions: in case of potential */
1413 /* interruption, to let the process to ADC IRQ Handler. */
1414 __HAL_UNLOCK(hadc);
1415
1416 /* Enable ADC overrun interrupt */
1417 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1418
1419 /* Length should be converted to number of bytes */
1420 LengthInBytes = (uint32_t)(Length * 4U);
1421
1422 /* Start the DMA channel */
1423 if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1424 {
1425 if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
1426 {
1427 hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (LengthInBytes * 2U);
1428 hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
1429 (uint32_t)&tmp_adc_common->CDR2;
1430 hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
1431 tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
1432 }
1433 else
1434 {
1435 tmp_hal_status = HAL_ERROR;
1436 };
1437 }
1438 else
1439 {
1440 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmp_adc_common->CDR2, (uint32_t)pData, \
1441 (LengthInBytes * 2U));
1442 }
1443
1444 /* Enable conversion of regular group. */
1445 /* If software start has been selected, conversion starts immediately. */
1446 /* If external trigger has been selected, conversion will start at next */
1447 /* trigger event. */
1448 /* Start ADC group regular conversion */
1449 LL_ADC_REG_StartConversion(hadc->Instance);
1450 }
1451 else
1452 {
1453 /* Process unlocked */
1454 __HAL_UNLOCK(hadc);
1455 }
1456
1457 /* Return function status */
1458 return tmp_hal_status;
1459 }
1460 }
1461
1462 /**
1463 * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
1464 * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
1465 * @retval The converted data values.
1466 */
HAL_ADCEx_MultiModeGetValue_Data32(const ADC_HandleTypeDef * hadc)1467 uint32_t HAL_ADCEx_MultiModeGetValue_Data32(const ADC_HandleTypeDef *hadc)
1468 {
1469 const ADC_Common_TypeDef *tmpADC_Common;
1470
1471 /* Check the parameters */
1472 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1473
1474 /* Prevent unused argument(s) compilation warning if no assert_param check */
1475 /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
1476 UNUSED(hadc);
1477
1478 /* Pointer to the common control register */
1479 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
1480
1481 /* Return the multi mode conversion value */
1482 return tmpADC_Common->CDR2;
1483 }
1484 #endif /* ADC_MULTIMODE_SUPPORT */
1485
1486 /**
1487 * @brief Get ADC injected group conversion result.
1488 * @note Reading register JDRx automatically clears ADC flag JEOC
1489 * (ADC group injected end of unitary conversion).
1490 * @note This function does not clear ADC flag JEOS
1491 * (ADC group injected end of sequence conversion)
1492 * Occurrence of flag JEOS rising:
1493 * - If sequencer is composed of 1 rank, flag JEOS is equivalent
1494 * to flag JEOC.
1495 * - If sequencer is composed of several ranks, during the scan
1496 * sequence flag JEOC only is raised, at the end of the scan sequence
1497 * both flags JEOC and EOS are raised.
1498 * Flag JEOS must not be cleared by this function because
1499 * it would not be compliant with low power features
1500 * (feature low power auto-wait, not available on all STM32 families).
1501 * To clear this flag, either use function:
1502 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
1503 * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
1504 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
1505 * @param hadc ADC handle
1506 * @param InjectedRank the converted ADC injected rank.
1507 * This parameter can be one of the following values:
1508 * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
1509 * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
1510 * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
1511 * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
1512 * @retval ADC group injected conversion data
1513 */
HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef * hadc,uint32_t InjectedRank)1514 uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
1515 {
1516 uint32_t tmp_jdr;
1517
1518 /* Check the parameters */
1519 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1520 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
1521
1522 /* Get ADC converted value */
1523 switch (InjectedRank)
1524 {
1525 case ADC_INJECTED_RANK_4:
1526 tmp_jdr = hadc->Instance->JDR4;
1527 break;
1528 case ADC_INJECTED_RANK_3:
1529 tmp_jdr = hadc->Instance->JDR3;
1530 break;
1531 case ADC_INJECTED_RANK_2:
1532 tmp_jdr = hadc->Instance->JDR2;
1533 break;
1534 case ADC_INJECTED_RANK_1:
1535 default:
1536 tmp_jdr = hadc->Instance->JDR1;
1537 break;
1538 }
1539
1540 return tmp_jdr;
1541 }
1542
1543 /**
1544 * @brief Injected conversion complete callback in non-blocking mode.
1545 * @param hadc ADC handle
1546 * @retval None
1547 */
HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef * hadc)1548 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
1549 {
1550 /* Prevent unused argument(s) compilation warning */
1551 UNUSED(hadc);
1552
1553 /* NOTE : This function should not be modified. When the callback is needed,
1554 function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
1555 */
1556 }
1557
1558 /**
1559 * @brief Injected context queue overflow callback.
1560 * @note This callback is called if injected context queue is enabled
1561 (parameter "QueueInjectedContext" in injected channel configuration)
1562 and if a new injected context is set when queue is full (maximum 2
1563 contexts).
1564 * @param hadc ADC handle
1565 * @retval None
1566 */
HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef * hadc)1567 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
1568 {
1569 /* Prevent unused argument(s) compilation warning */
1570 UNUSED(hadc);
1571
1572 /* NOTE : This function should not be modified. When the callback is needed,
1573 function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
1574 */
1575 }
1576
1577 /**
1578 * @brief Analog watchdog 2 callback in non-blocking mode.
1579 * @param hadc ADC handle
1580 * @retval None
1581 */
HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef * hadc)1582 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
1583 {
1584 /* Prevent unused argument(s) compilation warning */
1585 UNUSED(hadc);
1586
1587 /* NOTE : This function should not be modified. When the callback is needed,
1588 function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
1589 */
1590 }
1591
1592 /**
1593 * @brief Analog watchdog 3 callback in non-blocking mode.
1594 * @param hadc ADC handle
1595 * @retval None
1596 */
HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef * hadc)1597 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
1598 {
1599 /* Prevent unused argument(s) compilation warning */
1600 UNUSED(hadc);
1601
1602 /* NOTE : This function should not be modified. When the callback is needed,
1603 function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
1604 */
1605 }
1606
1607
1608 /**
1609 * @brief End Of Sampling callback in non-blocking mode.
1610 * @param hadc ADC handle
1611 * @retval None
1612 */
HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef * hadc)1613 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
1614 {
1615 /* Prevent unused argument(s) compilation warning */
1616 UNUSED(hadc);
1617
1618 /* NOTE : This function should not be modified. When the callback is needed,
1619 function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
1620 */
1621 }
1622
1623
1624 /**
1625 * @brief Stop ADC conversion of regular group (and injected channels in
1626 * case of auto_injection mode), disable ADC peripheral if no
1627 * conversion is on going on injected group.
1628 * @param hadc ADC handle
1629 * @retval HAL status.
1630 */
HAL_ADCEx_RegularStop(ADC_HandleTypeDef * hadc)1631 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
1632 {
1633 HAL_StatusTypeDef tmp_hal_status;
1634
1635 /* Check the parameters */
1636 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1637
1638 __HAL_LOCK(hadc);
1639
1640 /* 1. Stop potential regular conversion on going */
1641 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1642
1643 /* Disable ADC peripheral if regular conversions are effectively stopped
1644 and if no injected conversions are on-going */
1645 if (tmp_hal_status == HAL_OK)
1646 {
1647 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1648 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1649
1650 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1651 {
1652 /* 2. Disable the ADC peripheral */
1653 tmp_hal_status = ADC_Disable(hadc);
1654
1655 /* Check if ADC is effectively disabled */
1656 if (tmp_hal_status == HAL_OK)
1657 {
1658 /* Set ADC state */
1659 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
1660 }
1661 }
1662 /* Conversion on injected group is stopped, but ADC not disabled since */
1663 /* conversion on regular group is still running. */
1664 else
1665 {
1666 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1667 }
1668 }
1669
1670 __HAL_UNLOCK(hadc);
1671
1672 return tmp_hal_status;
1673 }
1674
1675
1676 /**
1677 * @brief Stop ADC conversion of ADC groups regular and injected,
1678 * disable interrution of end-of-conversion,
1679 * disable ADC peripheral if no conversion is on going
1680 * on injected group.
1681 * @param hadc ADC handle
1682 * @retval HAL status.
1683 */
HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef * hadc)1684 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
1685 {
1686 HAL_StatusTypeDef tmp_hal_status;
1687
1688 /* Check the parameters */
1689 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1690
1691 __HAL_LOCK(hadc);
1692
1693 /* 1. Stop potential regular conversion on going */
1694 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1695
1696 /* Disable ADC peripheral if conversions are effectively stopped
1697 and if no injected conversion is on-going */
1698 if (tmp_hal_status == HAL_OK)
1699 {
1700 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1701 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1702
1703 /* Disable all regular-related interrupts */
1704 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1705
1706 /* 2. Disable ADC peripheral if no injected conversions are on-going */
1707 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1708 {
1709 tmp_hal_status = ADC_Disable(hadc);
1710 /* if no issue reported */
1711 if (tmp_hal_status == HAL_OK)
1712 {
1713 /* Set ADC state */
1714 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
1715 }
1716 }
1717 else
1718 {
1719 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1720 }
1721 }
1722
1723 __HAL_UNLOCK(hadc);
1724
1725 return tmp_hal_status;
1726 }
1727
1728 /**
1729 * @brief Stop ADC conversion of regular group (and injected group in
1730 * case of auto_injection mode), disable ADC DMA transfer, disable
1731 * ADC peripheral if no conversion is on going
1732 * on injected group.
1733 * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
1734 * For multimode (when multimode feature is available),
1735 * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
1736 * @param hadc ADC handle
1737 * @retval HAL status.
1738 */
HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef * hadc)1739 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
1740 {
1741 HAL_StatusTypeDef tmp_hal_status;
1742
1743 /* Check the parameters */
1744 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1745
1746 __HAL_LOCK(hadc);
1747
1748 /* 1. Stop potential regular conversion on going */
1749 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1750
1751 /* Disable ADC peripheral if conversions are effectively stopped
1752 and if no injected conversion is on-going */
1753 if (tmp_hal_status == HAL_OK)
1754 {
1755 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1756 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1757
1758 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
1759 MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0 | ADC_CFGR1_DMNGT_1, 0UL);
1760
1761 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
1762 /* while DMA transfer is on going) */
1763 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1764
1765 /* Check if DMA channel effectively disabled */
1766 if (tmp_hal_status != HAL_OK)
1767 {
1768 /* Update ADC state machine to error */
1769 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1770 }
1771
1772 /* Disable ADC overrun interrupt */
1773 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1774
1775 /* 2. Disable the ADC peripheral */
1776 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
1777 /* to keep in memory a potential failing status. */
1778 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1779 {
1780 if (tmp_hal_status == HAL_OK)
1781 {
1782 tmp_hal_status = ADC_Disable(hadc);
1783 }
1784 else
1785 {
1786 (void)ADC_Disable(hadc);
1787 }
1788
1789 /* Check if ADC is effectively disabled */
1790 if (tmp_hal_status == HAL_OK)
1791 {
1792 /* Set ADC state */
1793 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
1794 }
1795 }
1796 else
1797 {
1798 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1799 }
1800 }
1801
1802 __HAL_UNLOCK(hadc);
1803
1804 return tmp_hal_status;
1805 }
1806
1807 #if defined(ADC_MULTIMODE_SUPPORT)
1808 /**
1809 * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected
1810 * conversion is on-going.
1811 * @note Multimode is kept enabled after this function. Multimode DMA bits
1812 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
1813 * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
1814 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
1815 * resort to HAL_ADCEx_DisableMultiMode() API.
1816 * @note In case of DMA configured in circular mode, function
1817 * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
1818 * ADC slave, to properly disable the DMA channel.
1819 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
1820 * @retval HAL status
1821 */
HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef * hadc)1822 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
1823 {
1824 HAL_StatusTypeDef tmp_hal_status;
1825 ADC_HandleTypeDef tmp_hadc_slave;
1826 uint32_t tmp_hadc_slave_conversion_on_going;
1827 uint32_t tickstart;
1828
1829 /* Check the parameters */
1830 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1831
1832 __HAL_LOCK(hadc);
1833
1834 /* 1. Stop potential multimode conversion on going, on regular groups */
1835 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1836
1837 /* Disable ADC peripheral if conversions are effectively stopped */
1838 if (tmp_hal_status == HAL_OK)
1839 {
1840 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1841 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1842
1843 /* Temporary handle minimum initialization */
1844 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
1845 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
1846
1847 /* Set a temporary handle of the ADC slave associated to the ADC master */
1848 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
1849
1850 if (tmp_hadc_slave.Instance == NULL)
1851 {
1852 /* Update ADC state machine to error */
1853 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1854 __HAL_UNLOCK(hadc);
1855 return HAL_ERROR;
1856 }
1857
1858 /* Procedure to disable the ADC peripheral: wait for conversions */
1859 /* effectively stopped (ADC master and ADC slave), then disable ADC */
1860
1861 /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
1862 tickstart = HAL_GetTick();
1863
1864 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1865 while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1866 || (tmp_hadc_slave_conversion_on_going == 1UL)
1867 )
1868 {
1869 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
1870 {
1871 /* Update ADC state machine to error */
1872 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1873
1874 __HAL_UNLOCK(hadc);
1875 return HAL_ERROR;
1876 }
1877
1878 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1879 }
1880
1881 /* Disable the DMA channel (in case of DMA in circular mode or stop */
1882 /* while DMA transfer is on going) */
1883 /* Note: DMA channel of ADC slave should be stopped after this function */
1884 /* with HAL_ADCEx_RegularStop_DMA() API. */
1885 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1886
1887 /* Check if DMA channel effectively disabled */
1888 if (tmp_hal_status != HAL_OK)
1889 {
1890 /* Update ADC state machine to error */
1891 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1892 }
1893
1894 /* Disable ADC overrun interrupt */
1895 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1896
1897 /* 2. Disable the ADC peripherals: master and slave if no injected */
1898 /* conversion is on-going. */
1899 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
1900 /* memory a potential failing status. */
1901 if (tmp_hal_status == HAL_OK)
1902 {
1903 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1904 {
1905 tmp_hal_status = ADC_Disable(hadc);
1906 if (tmp_hal_status == HAL_OK)
1907 {
1908 if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) == 0UL)
1909 {
1910 tmp_hal_status = ADC_Disable(&tmp_hadc_slave);
1911 }
1912 }
1913 }
1914
1915 if (tmp_hal_status == HAL_OK)
1916 {
1917 /* Both Master and Slave ADC's could be disabled. Update Master State */
1918 /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
1919 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
1920 }
1921 else
1922 {
1923 /* injected (Master or Slave) conversions are still on-going,
1924 no Master State change */
1925 }
1926 }
1927 }
1928
1929 __HAL_UNLOCK(hadc);
1930
1931 return tmp_hal_status;
1932 }
1933 #endif /* ADC_MULTIMODE_SUPPORT */
1934
1935 /**
1936 * @}
1937 */
1938
1939 /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
1940 * @brief ADC Extended Peripheral Control functions
1941 *
1942 @verbatim
1943 ===============================================================================
1944 ##### Peripheral Control functions #####
1945 ===============================================================================
1946 [..] This section provides functions allowing to:
1947 (+) Configure channels on injected group
1948 (+) Configure multimode when multimode feature is available
1949 (+) Enable or Disable Injected Queue
1950 (+) Disable ADC voltage regulator
1951 (+) Enter ADC deep-power-down mode
1952
1953 @endverbatim
1954 * @{
1955 */
1956
1957 /**
1958 * @brief Configure a channel to be assigned to ADC group injected.
1959 * @note Possibility to update parameters on the fly:
1960 * This function initializes injected group, following calls to this
1961 * function can be used to reconfigure some parameters of structure
1962 * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
1963 * The setting of these parameters is conditioned to ADC state:
1964 * Refer to comments of structure "ADC_InjectionConfTypeDef".
1965 * @note In case of usage of internal measurement channels:
1966 * Vbat/VrefInt/TempSensor.
1967 * These internal paths can be disabled using function
1968 * HAL_ADC_DeInit().
1969 * @note Caution: For Injected Context Queue use, a context must be fully
1970 * defined before start of injected conversion. All channels are configured
1971 * consecutively for the same ADC instance. Therefore, the number of calls to
1972 * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
1973 * InjectedNbrOfConversion for each context.
1974 * - Example 1: If 1 context is intended to be used (or if there is no use of the
1975 * Injected Queue Context feature) and if the context contains 3 injected ranks
1976 * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
1977 * called once for each channel (i.e. 3 times) before starting a conversion.
1978 * This function must not be called to configure a 4th injected channel:
1979 * it would start a new context into context queue.
1980 * - Example 2: If 2 contexts are intended to be used and each of them contains
1981 * 3 injected ranks (InjectedNbrOfConversion = 3),
1982 * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
1983 * for each context (3 channels x 2 contexts = 6 calls). Conversion can
1984 * start once the 1st context is set, that is after the first three
1985 * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
1986 * @param hadc ADC handle
1987 * @param pConfigInjected Structure of ADC injected group and ADC channel for
1988 * injected group.
1989 * @retval HAL status
1990 */
HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef * hadc,ADC_InjectionConfTypeDef * pConfigInjected)1991 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *pConfigInjected)
1992 {
1993 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1994 uint32_t tmp_offset_shifted;
1995 uint32_t tmp_config_internal_channel;
1996 uint32_t tmp_adc_is_conversion_on_going_regular;
1997 uint32_t tmp_adc_is_conversion_on_going_injected;
1998 __IO uint32_t wait_loop_index;
1999 uint32_t tmp_jsqr_context_queue_being_built = 0U;
2000 uint32_t tmp_channel;
2001
2002 /* Check the parameters */
2003 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2004 assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime));
2005 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff));
2006 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv));
2007 assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge));
2008 assert_param(IS_ADC_EXTTRIGINJEC(pConfigInjected->ExternalTrigInjecConv));
2009 assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber));
2010 assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign));
2011 assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
2012 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode));
2013
2014 if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
2015 {
2016 assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank));
2017 assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion));
2018 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode));
2019 }
2020
2021 /* Check offset range according to oversampling setting */
2022 if (hadc->Init.OversamplingMode == ENABLE)
2023 {
2024 assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc),
2025 pConfigInjected->InjectedOffset / (hadc->Init.Oversampling.Ratio + 1U)));
2026 }
2027 else
2028 {
2029 assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
2030 }
2031
2032 /* JDISCEN and JAUTO bits can't be set at the same time */
2033 assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE) \
2034 && (pConfigInjected->AutoInjectedConv == ENABLE)));
2035
2036 /* DISCEN and JAUTO bits can't be set at the same time */
2037 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE)));
2038
2039 /* Verification of channel number */
2040 if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
2041 {
2042 assert_param(IS_ADC_CHANNEL(pConfigInjected->InjectedChannel));
2043 }
2044 else
2045 {
2046 if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
2047 {
2048 #if defined (ADC2)
2049 assert_param(IS_ADC12_DIFF_CHANNEL(pConfigInjected->InjectedChannel));
2050 #else
2051 assert_param(IS_ADC1_DIFF_CHANNEL(pConfigInjected->InjectedChannel));
2052 #endif /* ADC2 */
2053 }
2054 }
2055
2056 __HAL_LOCK(hadc);
2057
2058 /* Configuration of injected group sequencer: */
2059 /* Hardware constraint: Must fully define injected context register JSQR */
2060 /* before make it entering into injected sequencer queue. */
2061 /* */
2062 /* - if scan mode is disabled: */
2063 /* * Injected channels sequence length is set to 0x00: 1 channel */
2064 /* converted (channel on injected rank 1) */
2065 /* Parameter "InjectedNbrOfConversion" is discarded. */
2066 /* * Injected context register JSQR setting is simple: register is fully */
2067 /* defined on one call of this function (for injected rank 1) and can */
2068 /* be entered into queue directly. */
2069 /* - if scan mode is enabled: */
2070 /* * Injected channels sequence length is set to parameter */
2071 /* "InjectedNbrOfConversion". */
2072 /* * Injected context register JSQR setting more complex: register is */
2073 /* fully defined over successive calls of this function, for each */
2074 /* injected channel rank. It is entered into queue only when all */
2075 /* injected ranks have been set. */
2076 /* Note: Scan mode is not present by hardware on this device, but used */
2077 /* by software for alignment over all STM32 devices. */
2078
2079 if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
2080 (pConfigInjected->InjectedNbrOfConversion == 1U))
2081 {
2082 /* Configuration of context register JSQR: */
2083 /* - number of ranks in injected group sequencer: fixed to 1st rank */
2084 /* (scan mode disabled, only rank 1 used) */
2085 /* - external trigger to start conversion */
2086 /* - external trigger polarity */
2087 /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
2088
2089 if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
2090 {
2091 /* Enable external trigger if trigger selection is different of */
2092 /* software start. */
2093 /* Note: This configuration keeps the hardware feature of parameter */
2094 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
2095 /* software start. */
2096 if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
2097 {
2098 tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
2099 | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
2100 | pConfigInjected->ExternalTrigInjecConvEdge
2101 );
2102 }
2103 else
2104 {
2105 tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
2106 }
2107
2108 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_jsqr_context_queue_being_built);
2109 /* For debug and informative reasons, hadc handle saves JSQR setting */
2110 hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built;
2111 }
2112 }
2113 else
2114 {
2115 /* Case of scan mode enabled, several channels to set into injected group */
2116 /* sequencer. */
2117 /* */
2118 /* Procedure to define injected context register JSQR over successive */
2119 /* calls of this function, for each injected channel rank: */
2120 /* 1. Start new context and set parameters related to all injected */
2121 /* channels: injected sequence length and trigger. */
2122
2123 /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
2124 /* call of the context under setting */
2125 if (hadc->InjectionConfig.ChannelCount == 0U)
2126 {
2127 /* Initialize number of channels that will be configured on the context */
2128 /* being built */
2129 hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion;
2130 /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
2131 call, this context will be written in JSQR register at the last call.
2132 At this point, the context is merely reset */
2133 hadc->InjectionConfig.ContextQueue = 0x00000000U;
2134
2135 /* Configuration of context register JSQR: */
2136 /* - number of ranks in injected group sequencer */
2137 /* - external trigger to start conversion */
2138 /* - external trigger polarity */
2139
2140 /* Enable external trigger if trigger selection is different of */
2141 /* software start. */
2142 /* Note: This configuration keeps the hardware feature of parameter */
2143 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
2144 /* software start. */
2145 if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
2146 {
2147 tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U)
2148 | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
2149 | pConfigInjected->ExternalTrigInjecConvEdge
2150 );
2151 }
2152 else
2153 {
2154 tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U));
2155 }
2156 }
2157
2158 /* 2. Continue setting of context under definition with parameter */
2159 /* related to each channel: channel rank sequence */
2160 /* Clear the old JSQx bits for the selected rank */
2161 tmp_jsqr_context_queue_being_built &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank);
2162
2163 /* Set the JSQx bits for the selected rank */
2164 tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank);
2165
2166 /* Decrease channel count */
2167 hadc->InjectionConfig.ChannelCount--;
2168
2169 /* 3. tmp_jsqr_context_queue_being_built is fully built for this HAL_ADCEx_InjectedConfigChannel()
2170 call, aggregate the setting to those already built during the previous
2171 HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
2172 hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built;
2173
2174 /* 4. End of context setting: if this is the last channel set, then write context
2175 into register JSQR and make it enter into queue */
2176 if (hadc->InjectionConfig.ChannelCount == 0U)
2177 {
2178 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
2179 }
2180 }
2181
2182 /* Parameters update conditioned to ADC state: */
2183 /* Parameters that can be updated when ADC is disabled or enabled without */
2184 /* conversion on going on injected group: */
2185 /* - Injected context queue: Queue disable (active context is kept) or */
2186 /* enable (context decremented, up to 2 contexts queued) */
2187 /* - Injected discontinuous mode: can be enabled only if auto-injected */
2188 /* mode is disabled. */
2189 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
2190 {
2191 /* ADC channels preselection */
2192 hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel) & 0x1FUL));
2193
2194 /* If auto-injected mode is disabled: no constraint */
2195 if (pConfigInjected->AutoInjectedConv == DISABLE)
2196 {
2197 MODIFY_REG(hadc->Instance->CFGR1,
2198 ADC_CFGR1_JDISCEN,
2199 ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
2200 }
2201 /* If auto-injected mode is enabled: Injected discontinuous setting is */
2202 /* discarded. */
2203 else
2204 {
2205 MODIFY_REG(hadc->Instance->CFGR1,
2206 ADC_CFGR1_JDISCEN,
2207 ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
2208 }
2209 }
2210
2211 /* Parameters update conditioned to ADC state: */
2212 /* Parameters that can be updated when ADC is disabled or enabled without */
2213 /* conversion on going on regular and injected groups: */
2214 /* - Automatic injected conversion: can be enabled if injected group */
2215 /* external triggers are disabled. */
2216 /* - Channel sampling time */
2217 /* - Channel offset */
2218 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2219 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2220
2221 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2222 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2223 )
2224 {
2225 /* If injected group external triggers are disabled (set to injected */
2226 /* software start): no constraint */
2227 if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
2228 || (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
2229 {
2230 if (pConfigInjected->AutoInjectedConv == ENABLE)
2231 {
2232 SET_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
2233 }
2234 else
2235 {
2236 CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
2237 }
2238 }
2239 /* If Automatic injected conversion was intended to be set and could not */
2240 /* due to injected group external triggers enabled, error is reported. */
2241 else
2242 {
2243 if (pConfigInjected->AutoInjectedConv == ENABLE)
2244 {
2245 /* Update ADC state machine to error */
2246 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2247
2248 tmp_hal_status = HAL_ERROR;
2249 }
2250 else
2251 {
2252 CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
2253 }
2254 }
2255
2256 if (pConfigInjected->InjecOversamplingMode == ENABLE)
2257 {
2258 assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
2259 assert_param(IS_ADC12_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
2260
2261 /* JOVSE must be reset in case of triggered regular mode */
2262 assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) ==
2263 (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
2264
2265 /* Configuration of Injected Oversampler: */
2266 /* - Oversampling Ratio */
2267 /* - Right bit shift */
2268
2269 /* Enable OverSampling mode */
2270 MODIFY_REG(hadc->Instance->CFGR2,
2271 ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR | ADC_CFGR2_OVSS,
2272 ADC_CFGR2_JOVSE | (pConfigInjected->InjecOversampling.Ratio << ADC_CFGR2_OVSR_Pos) |
2273 pConfigInjected->InjecOversampling.RightBitShift);
2274 }
2275 else
2276 {
2277 /* Disable Regular OverSampling */
2278 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
2279 }
2280
2281 /* Set sampling time of the selected ADC channel */
2282 LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
2283 pConfigInjected->InjectedSamplingTime);
2284
2285 /* Configure the offset: offset enable/disable, channel, offset value */
2286
2287 /* Shift the offset with respect to the selected ADC resolution. */
2288 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
2289 tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset);
2290
2291 if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
2292 {
2293 /* Set ADC selected offset number */
2294 LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel,
2295 tmp_offset_shifted);
2296 /* Set ADC selected offset sign */
2297 LL_ADC_SetOffsetSign(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedOffsetSign);
2298
2299 /* Configure offset saturation */
2300 if (pConfigInjected->InjectedOffsetSaturation == ENABLE)
2301 {
2302 /* Set ADC selected offset unsigned/signed saturation */
2303 LL_ADC_SetOffsetUnsignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
2304 (pConfigInjected->InjectedOffsetSignedSaturation == DISABLE)
2305 ? LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE \
2306 : LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE);
2307
2308 LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
2309 (pConfigInjected->InjectedOffsetSignedSaturation == ENABLE)
2310 ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE \
2311 : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
2312 }
2313 else
2314 {
2315 /* Disable ADC offset signed saturation */
2316 LL_ADC_SetOffsetUnsignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
2317 LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE);
2318 LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
2319 LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
2320 }
2321 }
2322 else
2323 {
2324 /* Scan each offset register to check if the selected channel is targeted. */
2325 /* If this is the case, the corresponding offset number is disabled. */
2326 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
2327 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
2328 {
2329 LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, pConfigInjected->InjectedChannel, 0x0);
2330 }
2331 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
2332 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
2333 {
2334 LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, pConfigInjected->InjectedChannel, 0x0);
2335 }
2336 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
2337 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
2338 {
2339 LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_3, pConfigInjected->InjectedChannel, 0x0);
2340 }
2341 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
2342 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
2343 {
2344 LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, pConfigInjected->InjectedChannel, 0x0);
2345 }
2346 }
2347 }
2348
2349 /* Parameters update conditioned to ADC state: */
2350 /* Parameters that can be updated only when ADC is disabled: */
2351 /* - Single or differential mode */
2352 /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
2353 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2354 {
2355 /* Set mode single-ended or differential input of the selected ADC channel */
2356 LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff);
2357
2358 /* Configuration of differential mode */
2359 /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
2360 if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
2361 {
2362 /* Set sampling time of the selected ADC channel */
2363 tmp_channel = __LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel) \
2364 + 1UL) & 0x1FUL);
2365 LL_ADC_SetChannelSamplingTime(hadc->Instance, tmp_channel, pConfigInjected->InjectedSamplingTime);
2366 }
2367
2368 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
2369 /* internal measurement paths enable: If internal channel selected, */
2370 /* enable dedicated internal buffers and path. */
2371 /* Note: these internal measurement paths can be disabled using */
2372 /* HAL_ADC_DeInit(). */
2373
2374 if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel))
2375 {
2376 /* Configuration of common ADC parameters (continuation) */
2377 /* Software is allowed to change common parameters only when all ADCs */
2378 /* of the common group are disabled. */
2379 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2380 {
2381 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2382
2383 /* If the requested internal measurement path has already been enabled, */
2384 /* bypass the configuration processing. */
2385 if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
2386 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
2387 {
2388 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
2389 {
2390 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2391 LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
2392
2393 /* Delay for temperature sensor stabilization time */
2394 /* Wait loop initialization and execution */
2395 /* Note: Variable divided by 2 to compensate partially */
2396 /* CPU processing cycles, scaling in us split to not */
2397 /* exceed 32 bits register capacity and handle low frequency. */
2398 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
2399 while (wait_loop_index != 0UL)
2400 {
2401 wait_loop_index--;
2402 }
2403 }
2404 }
2405 else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
2406 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
2407 {
2408 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
2409 {
2410 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2411 LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
2412 }
2413 }
2414 else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
2415 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
2416 {
2417 if (ADC_VREFINT_INSTANCE(hadc))
2418 {
2419 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2420 LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
2421 }
2422 }
2423 else
2424 {
2425 /* nothing to do */
2426 }
2427 }
2428 /* If the requested internal measurement path has already been enabled */
2429 /* and other ADC of the common group are enabled, internal */
2430 /* measurement paths cannot be enabled. */
2431 else
2432 {
2433 /* Update ADC state machine to error */
2434 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2435
2436 tmp_hal_status = HAL_ERROR;
2437 }
2438 }
2439 }
2440
2441 __HAL_UNLOCK(hadc);
2442
2443 return tmp_hal_status;
2444 }
2445
2446 #if defined(ADC_MULTIMODE_SUPPORT)
2447 /**
2448 * @brief Enable ADC multimode and configure multimode parameters
2449 * @note Possibility to update parameters on the fly:
2450 * This function initializes multimode parameters, following
2451 * calls to this function can be used to reconfigure some parameters
2452 * of structure "ADC_MultiModeTypeDef" on the fly, without resetting
2453 * the ADCs.
2454 * The setting of these parameters is conditioned to ADC state.
2455 * For parameters constraints, see comments of structure
2456 * "ADC_MultiModeTypeDef".
2457 * @note To move back configuration from multimode to single mode, ADC must
2458 * be reset (using function HAL_ADC_Init() ).
2459 * @param hadc Master ADC handle
2460 * @param pMultimode Structure of ADC multimode configuration
2461 * @retval HAL status
2462 */
HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef * hadc,ADC_MultiModeTypeDef * pMultimode)2463 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *pMultimode)
2464 {
2465 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2466 ADC_Common_TypeDef *tmp_adc_common;
2467 ADC_HandleTypeDef tmp_hadc_slave;
2468 uint32_t tmp_hadc_slave_conversion_on_going;
2469
2470 /* Check the parameters */
2471 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
2472 assert_param(IS_ADC_MULTIMODE(pMultimode->Mode));
2473 if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
2474 {
2475 assert_param(IS_ADC_DUAL_DATA_MODE(pMultimode->DualModeData));
2476 assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
2477 }
2478
2479 __HAL_LOCK(hadc);
2480
2481 /* Temporary handle minimum initialization */
2482 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
2483 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
2484
2485 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
2486
2487 if (tmp_hadc_slave.Instance == NULL)
2488 {
2489 /* Update ADC state machine to error */
2490 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2491
2492 __HAL_UNLOCK(hadc);
2493
2494 return HAL_ERROR;
2495 }
2496
2497 /* Parameters update conditioned to ADC state: */
2498 /* Parameters that can be updated when ADC is disabled or enabled without */
2499 /* conversion on going on regular group: */
2500 /* - Multimode DMA configuration */
2501 /* - Multimode DMA mode */
2502 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
2503 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2504 && (tmp_hadc_slave_conversion_on_going == 0UL))
2505 {
2506 /* Pointer to the common control register */
2507 tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
2508
2509 /* If multimode is selected, configure all pMultimode parameters. */
2510 /* Otherwise, reset pMultimode parameters (can be used in case of */
2511 /* transition from multimode to independent mode). */
2512 if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
2513 {
2514 MODIFY_REG(tmp_adc_common->CCR, ADC_CCR_DAMDF, pMultimode->DualModeData);
2515
2516 /* Parameters that can be updated only when ADC is disabled: */
2517 /* - Multimode mode selection */
2518 /* - Multimode delay */
2519 /* Note: Delay range depends on selected resolution: */
2520 /* from 1 to 12 clock cycles for 12 bits */
2521 /* from 1 to 10 clock cycles for 10 bits, */
2522 /* from 1 to 8 clock cycles for 8 bits */
2523 /* from 1 to 6 clock cycles for 6 bits */
2524 /* If a higher delay is selected, it will be clipped to maximum delay */
2525 /* range */
2526 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2527 {
2528 MODIFY_REG(tmp_adc_common->CCR, (ADC_CCR_DUAL | ADC_CCR_DELAY), \
2529 (pMultimode->Mode | pMultimode->TwoSamplingDelay));
2530 }
2531 }
2532 else /* ADC_MODE_INDEPENDENT */
2533 {
2534 CLEAR_BIT(tmp_adc_common->CCR, ADC_CCR_DAMDF);
2535
2536 /* Parameters that can be updated only when ADC is disabled: */
2537 /* - Multimode mode selection */
2538 /* - Multimode delay */
2539 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2540 {
2541 CLEAR_BIT(tmp_adc_common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
2542 }
2543 }
2544 }
2545 /* If one of the ADC sharing the same common group is enabled, no update */
2546 /* could be done on neither of the multimode structure parameters. */
2547 else
2548 {
2549 /* Update ADC state machine to error */
2550 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2551 tmp_hal_status = HAL_ERROR;
2552 }
2553
2554 __HAL_UNLOCK(hadc);
2555
2556 return tmp_hal_status;
2557 }
2558 #endif /* ADC_MULTIMODE_SUPPORT */
2559
2560 /**
2561 * @brief Disable ADC voltage regulator.
2562 * @note Disabling voltage regulator allows to save power. This operation can
2563 * be carried out only when ADC is disabled.
2564 * @note To enable again the voltage regulator, the user is expected to
2565 * resort to HAL_ADC_Init() API.
2566 * @param hadc ADC handle
2567 * @retval HAL status
2568 */
HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef * hadc)2569 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
2570 {
2571 HAL_StatusTypeDef tmp_hal_status;
2572
2573 /* Check the parameters */
2574 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2575
2576 /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
2577 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2578 {
2579 LL_ADC_DisableInternalRegulator(hadc->Instance);
2580 tmp_hal_status = HAL_OK;
2581 }
2582 else
2583 {
2584 tmp_hal_status = HAL_ERROR;
2585 }
2586
2587 return tmp_hal_status;
2588 }
2589
2590 /**
2591 * @brief Enter ADC deep-power-down mode
2592 * @note This mode is achieved in setting DEEPPWD bit and allows to save power
2593 * in reducing leakage currents. It is particularly interesting before
2594 * entering stop modes.
2595 * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
2596 * ADC voltage regulator. This means that this API encompasses
2597 * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
2598 * calibration is lost.
2599 * @note To exit the ADC deep-power-down mode, the user is expected to
2600 * resort to HAL_ADC_Init() API as well as to relaunch a calibration
2601 * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
2602 * saved calibration factor.
2603 * @param hadc ADC handle
2604 * @retval HAL status
2605 */
HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef * hadc)2606 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
2607 {
2608 HAL_StatusTypeDef tmp_hal_status;
2609
2610 /* Check the parameters */
2611 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2612
2613 /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
2614 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2615 {
2616 LL_ADC_EnableDeepPowerDown(hadc->Instance);
2617 tmp_hal_status = HAL_OK;
2618 }
2619 else
2620 {
2621 tmp_hal_status = HAL_ERROR;
2622 }
2623
2624 return tmp_hal_status;
2625 }
2626
2627 /**
2628 * @}
2629 */
2630
2631 /**
2632 * @}
2633 */
2634
2635 #endif /* HAL_ADC_MODULE_ENABLED */
2636 /**
2637 * @}
2638 */
2639
2640 /**
2641 * @}
2642 */
2643
