1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32u0xx_ll_tim.h"
22 #include "stm32u0xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32U0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) \
35 || defined (TIM2) \
36 || defined (TIM3) \
37 || defined (TIM6) \
38 || defined (TIM7) \
39 || defined (TIM15) \
40 || defined (TIM16)
41
42 /** @addtogroup TIM_LL
43 * @{
44 */
45
46 /* Private types -------------------------------------------------------------*/
47 /* Private variables ---------------------------------------------------------*/
48 /* Private constants ---------------------------------------------------------*/
49 /* Private macros ------------------------------------------------------------*/
50 /** @addtogroup TIM_LL_Private_Macros
51 * @{
52 */
53 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
54 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
55 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
56 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
57 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
58
59 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
60 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
61 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
62
63 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
64 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
65 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
66 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
67 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
68 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
69 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
71 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
72 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
73 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
74 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
75 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
76 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
77
78 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
79 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
80
81 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
82 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
83
84 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
85 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
86
87 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
88 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
89 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
90
91 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
92 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
93 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
94 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
95
96 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
107 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
108 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
109 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
110 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
111 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
112
113 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
114 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
115 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
116
117 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
118 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
119 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
120
121 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
122 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
123
124 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
125 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
126
127 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
128 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
129
130 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
131 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
132 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
133 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
134
135 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
136 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
137
138 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
139 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
140
141 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
142 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
143 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
151 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
152 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
153 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
154 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
155 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
156 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
157
158 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
159 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
160
161 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
162 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
163
164 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
165 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
166
167 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
168 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
169 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
177 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
178 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
179 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
180 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
181 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
182 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
183
184 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
185 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
186
187 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
188 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
189 /**
190 * @}
191 */
192
193
194 /* Private function prototypes -----------------------------------------------*/
195 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
196 * @{
197 */
198 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
199 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
200 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
201 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
202 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
203 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
204 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
205 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
206 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
207 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
208 /**
209 * @}
210 */
211
212 /* Exported functions --------------------------------------------------------*/
213 /** @addtogroup TIM_LL_Exported_Functions
214 * @{
215 */
216
217 /** @addtogroup TIM_LL_EF_Init
218 * @{
219 */
220
221 /**
222 * @brief Set TIMx registers to their reset values.
223 * @param TIMx Timer instance
224 * @retval An ErrorStatus enumeration value:
225 * - SUCCESS: TIMx registers are de-initialized
226 * - ERROR: invalid TIMx instance
227 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)228 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
229 {
230 ErrorStatus result = SUCCESS;
231
232 /* Check the parameters */
233 assert_param(IS_TIM_INSTANCE(TIMx));
234
235 if (TIMx == TIM1)
236 {
237 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM1);
238 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM1);
239 }
240 else if (TIMx == TIM2)
241 {
242 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
243 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
244 }
245 else if (TIMx == TIM3)
246 {
247 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
248 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
249 }
250 else if (TIMx == TIM6)
251 {
252 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
253 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
254 }
255 else if (TIMx == TIM7)
256 {
257 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
258 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
259 }
260 else if (TIMx == TIM15)
261 {
262 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM15);
263 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM15);
264 }
265 else if (TIMx == TIM16)
266 {
267 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM16);
268 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM16);
269 }
270 else
271 {
272 result = ERROR;
273 }
274
275 return result;
276 }
277
278 /**
279 * @brief Set the fields of the time base unit configuration data structure
280 * to their default values.
281 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
282 * @retval None
283 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)284 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
285 {
286 /* Set the default configuration */
287 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
288 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
289 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
290 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
291 TIM_InitStruct->RepetitionCounter = 0x00000000U;
292 }
293
294 /**
295 * @brief Configure the TIMx time base unit.
296 * @param TIMx Timer Instance
297 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
298 * (TIMx time base unit configuration data structure)
299 * @retval An ErrorStatus enumeration value:
300 * - SUCCESS: TIMx registers are de-initialized
301 * - ERROR: not applicable
302 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)303 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
304 {
305 uint32_t tmpcr1;
306
307 /* Check the parameters */
308 assert_param(IS_TIM_INSTANCE(TIMx));
309 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
310 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
311
312 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
313
314 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
315 {
316 /* Select the Counter Mode */
317 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
318 }
319
320 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
321 {
322 /* Set the clock division */
323 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
324 }
325
326 /* Write to TIMx CR1 */
327 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
328
329 /* Set the Autoreload value */
330 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
331
332 /* Set the Prescaler value */
333 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
334
335 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
336 {
337 /* Set the Repetition Counter value */
338 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
339 }
340
341 /* Generate an update event to reload the Prescaler
342 and the repetition counter value (if applicable) immediately */
343 LL_TIM_GenerateEvent_UPDATE(TIMx);
344
345 return SUCCESS;
346 }
347
348 /**
349 * @brief Set the fields of the TIMx output channel configuration data
350 * structure to their default values.
351 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
352 * (the output channel configuration data structure)
353 * @retval None
354 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)355 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
356 {
357 /* Set the default configuration */
358 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
359 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
360 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
361 TIM_OC_InitStruct->CompareValue = 0x00000000U;
362 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
363 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
364 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
365 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
366 }
367
368 /**
369 * @brief Configure the TIMx output channel.
370 * @param TIMx Timer Instance
371 * @param Channel This parameter can be one of the following values:
372 * @arg @ref LL_TIM_CHANNEL_CH1
373 * @arg @ref LL_TIM_CHANNEL_CH2
374 * @arg @ref LL_TIM_CHANNEL_CH3
375 * @arg @ref LL_TIM_CHANNEL_CH4
376 * @arg @ref LL_TIM_CHANNEL_CH5
377 * @arg @ref LL_TIM_CHANNEL_CH6
378 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
379 * data structure)
380 * @retval An ErrorStatus enumeration value:
381 * - SUCCESS: TIMx output channel is initialized
382 * - ERROR: TIMx output channel is not initialized
383 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)384 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
385 {
386 ErrorStatus result = ERROR;
387
388 switch (Channel)
389 {
390 case LL_TIM_CHANNEL_CH1:
391 result = OC1Config(TIMx, TIM_OC_InitStruct);
392 break;
393 case LL_TIM_CHANNEL_CH2:
394 result = OC2Config(TIMx, TIM_OC_InitStruct);
395 break;
396 case LL_TIM_CHANNEL_CH3:
397 result = OC3Config(TIMx, TIM_OC_InitStruct);
398 break;
399 case LL_TIM_CHANNEL_CH4:
400 result = OC4Config(TIMx, TIM_OC_InitStruct);
401 break;
402 case LL_TIM_CHANNEL_CH5:
403 result = OC5Config(TIMx, TIM_OC_InitStruct);
404 break;
405 case LL_TIM_CHANNEL_CH6:
406 result = OC6Config(TIMx, TIM_OC_InitStruct);
407 break;
408 default:
409 break;
410 }
411
412 return result;
413 }
414
415 /**
416 * @brief Set the fields of the TIMx input channel configuration data
417 * structure to their default values.
418 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
419 * data structure)
420 * @retval None
421 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)422 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
423 {
424 /* Set the default configuration */
425 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
426 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
427 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
428 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
429 }
430
431 /**
432 * @brief Configure the TIMx input channel.
433 * @param TIMx Timer Instance
434 * @param Channel This parameter can be one of the following values:
435 * @arg @ref LL_TIM_CHANNEL_CH1
436 * @arg @ref LL_TIM_CHANNEL_CH2
437 * @arg @ref LL_TIM_CHANNEL_CH3
438 * @arg @ref LL_TIM_CHANNEL_CH4
439 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
440 * structure)
441 * @retval An ErrorStatus enumeration value:
442 * - SUCCESS: TIMx output channel is initialized
443 * - ERROR: TIMx output channel is not initialized
444 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)445 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
446 {
447 ErrorStatus result = ERROR;
448
449 switch (Channel)
450 {
451 case LL_TIM_CHANNEL_CH1:
452 result = IC1Config(TIMx, TIM_IC_InitStruct);
453 break;
454 case LL_TIM_CHANNEL_CH2:
455 result = IC2Config(TIMx, TIM_IC_InitStruct);
456 break;
457 case LL_TIM_CHANNEL_CH3:
458 result = IC3Config(TIMx, TIM_IC_InitStruct);
459 break;
460 case LL_TIM_CHANNEL_CH4:
461 result = IC4Config(TIMx, TIM_IC_InitStruct);
462 break;
463 default:
464 break;
465 }
466
467 return result;
468 }
469
470 /**
471 * @brief Fills each TIM_EncoderInitStruct field with its default value
472 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
473 * configuration data structure)
474 * @retval None
475 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)476 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
477 {
478 /* Set the default configuration */
479 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
480 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
481 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
482 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
483 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
484 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
485 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
486 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
487 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
488 }
489
490 /**
491 * @brief Configure the encoder interface of the timer instance.
492 * @param TIMx Timer Instance
493 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
494 * configuration data structure)
495 * @retval An ErrorStatus enumeration value:
496 * - SUCCESS: TIMx registers are de-initialized
497 * - ERROR: not applicable
498 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)499 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
500 {
501 uint32_t tmpccmr1;
502 uint32_t tmpccer;
503
504 /* Check the parameters */
505 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
506 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
507 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
508 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
509 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
510 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
511 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
512 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
513 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
514 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
515
516 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
517 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
518
519 /* Get the TIMx CCMR1 register value */
520 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
521
522 /* Get the TIMx CCER register value */
523 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
524
525 /* Configure TI1 */
526 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
527 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
528 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
529 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
530
531 /* Configure TI2 */
532 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
533 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
534 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
535 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
536
537 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
538 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
539 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
540 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
541 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
542
543 /* Set encoder mode */
544 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
545
546 /* Write to TIMx CCMR1 */
547 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
548
549 /* Write to TIMx CCER */
550 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
551
552 return SUCCESS;
553 }
554
555 /**
556 * @brief Set the fields of the TIMx Hall sensor interface configuration data
557 * structure to their default values.
558 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
559 * configuration data structure)
560 * @retval None
561 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)562 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
563 {
564 /* Set the default configuration */
565 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
566 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
567 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
568 TIM_HallSensorInitStruct->CommutationDelay = 0U;
569 }
570
571 /**
572 * @brief Configure the Hall sensor interface of the timer instance.
573 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
574 * to the TI1 input channel
575 * @note TIMx slave mode controller is configured in reset mode.
576 Selected internal trigger is TI1F_ED.
577 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
578 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
579 * between 2 changes on the inputs. It gives information about motor speed.
580 * @note Channel 2 is configured in output PWM 2 mode.
581 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
582 * @note OC2REF is selected as trigger output on TRGO.
583 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
584 * when TIMx operates in Hall sensor interface mode.
585 * @param TIMx Timer Instance
586 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
587 * interface configuration data structure)
588 * @retval An ErrorStatus enumeration value:
589 * - SUCCESS: TIMx registers are de-initialized
590 * - ERROR: not applicable
591 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)592 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
593 {
594 uint32_t tmpcr2;
595 uint32_t tmpccmr1;
596 uint32_t tmpccer;
597 uint32_t tmpsmcr;
598
599 /* Check the parameters */
600 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
601 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
602 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
603 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
604
605 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
606 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
607
608 /* Get the TIMx CR2 register value */
609 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
610
611 /* Get the TIMx CCMR1 register value */
612 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
613
614 /* Get the TIMx CCER register value */
615 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
616
617 /* Get the TIMx SMCR register value */
618 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
619
620 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
621 tmpcr2 |= TIM_CR2_TI1S;
622
623 /* OC2REF signal is used as trigger output (TRGO) */
624 tmpcr2 |= LL_TIM_TRGO_OC2REF;
625
626 /* Configure the slave mode controller */
627 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
628 tmpsmcr |= LL_TIM_TS_TI1F_ED;
629 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
630
631 /* Configure input channel 1 */
632 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
633 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
634 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
635 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
636
637 /* Configure input channel 2 */
638 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
639 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
640
641 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
642 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
643 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
644 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
645
646 /* Write to TIMx CR2 */
647 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
648
649 /* Write to TIMx SMCR */
650 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
651
652 /* Write to TIMx CCMR1 */
653 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
654
655 /* Write to TIMx CCER */
656 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
657
658 /* Write to TIMx CCR2 */
659 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
660
661 return SUCCESS;
662 }
663
664 /**
665 * @brief Set the fields of the Break and Dead Time configuration data structure
666 * to their default values.
667 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
668 * data structure)
669 * @retval None
670 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)671 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
672 {
673 /* Set the default configuration */
674 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
675 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
676 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
677 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
678 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
679 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
680 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
681 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
682 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
683 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
684 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
685 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
686 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
687 }
688
689 /**
690 * @brief Configure the Break and Dead Time feature of the timer instance.
691 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
692 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
693 * can be necessary to configure all of them during the first write access to
694 * the TIMx_BDTR register.
695 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
696 * a timer instance provides a break input.
697 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
698 * a timer instance provides a second break input.
699 * @param TIMx Timer Instance
700 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
701 * data structure)
702 * @retval An ErrorStatus enumeration value:
703 * - SUCCESS: Break and Dead Time is initialized
704 * - ERROR: not applicable
705 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)706 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
707 {
708 uint32_t tmpbdtr = 0;
709
710 /* Check the parameters */
711 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
712 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
713 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
714 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
715 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
716 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
717 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
718 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
719 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
720
721 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
722 the OSSI State, the dead time value and the Automatic Output Enable Bit */
723
724 /* Set the BDTR bits */
725 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
726 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
727 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
728 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
729 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
730 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
731 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
732 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
733 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
734
735 if (IS_TIM_BKIN2_INSTANCE(TIMx))
736 {
737 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
738 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
739 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
740 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
741
742 /* Set the BREAK2 input related BDTR bit-fields */
743 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
744 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
745 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
746 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
747 }
748
749 /* Set TIMx_BDTR */
750 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
751
752 return SUCCESS;
753 }
754 /**
755 * @}
756 */
757
758 /**
759 * @}
760 */
761
762 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
763 * @brief Private functions
764 * @{
765 */
766 /**
767 * @brief Configure the TIMx output channel 1.
768 * @param TIMx Timer Instance
769 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
770 * @retval An ErrorStatus enumeration value:
771 * - SUCCESS: TIMx registers are de-initialized
772 * - ERROR: not applicable
773 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)774 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
775 {
776 uint32_t tmpccmr1;
777 uint32_t tmpccer;
778 uint32_t tmpcr2;
779
780 /* Check the parameters */
781 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
782 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
783 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
784 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
785
786 /* Disable the Channel 1: Reset the CC1E Bit */
787 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
788
789 /* Get the TIMx CCER register value */
790 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
791
792 /* Get the TIMx CR2 register value */
793 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
794
795 /* Get the TIMx CCMR1 register value */
796 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
797
798 /* Reset Capture/Compare selection Bits */
799 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
800
801 /* Set the Output Compare Mode */
802 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
803
804 /* Set the Output Compare Polarity */
805 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
806
807 /* Set the Output State */
808 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
809
810 if (IS_TIM_BREAK_INSTANCE(TIMx))
811 {
812 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
813 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
814 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
815 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
816
817 /* Set the complementary output Polarity */
818 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
819
820 /* Set the complementary output State */
821 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
822
823 /* Set the Output Idle state */
824 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
825
826 /* Set the complementary output Idle state */
827 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
828 }
829
830 /* Write to TIMx CR2 */
831 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
832
833 /* Write to TIMx CCMR1 */
834 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
835
836 /* Set the Capture Compare Register value */
837 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
838
839 /* Write to TIMx CCER */
840 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
841
842 return SUCCESS;
843 }
844
845 /**
846 * @brief Configure the TIMx output channel 2.
847 * @param TIMx Timer Instance
848 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
849 * @retval An ErrorStatus enumeration value:
850 * - SUCCESS: TIMx registers are de-initialized
851 * - ERROR: not applicable
852 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)853 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
854 {
855 uint32_t tmpccmr1;
856 uint32_t tmpccer;
857 uint32_t tmpcr2;
858
859 /* Check the parameters */
860 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
861 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
862 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
863 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
864
865 /* Disable the Channel 2: Reset the CC2E Bit */
866 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
867
868 /* Get the TIMx CCER register value */
869 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
870
871 /* Get the TIMx CR2 register value */
872 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
873
874 /* Get the TIMx CCMR1 register value */
875 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
876
877 /* Reset Capture/Compare selection Bits */
878 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
879
880 /* Select the Output Compare Mode */
881 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
882
883 /* Set the Output Compare Polarity */
884 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
885
886 /* Set the Output State */
887 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
888
889 if (IS_TIM_BREAK_INSTANCE(TIMx))
890 {
891 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
892 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
893 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
894 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
895
896 /* Set the complementary output Polarity */
897 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
898
899 /* Set the complementary output State */
900 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
901
902 /* Set the Output Idle state */
903 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
904
905 /* Set the complementary output Idle state */
906 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
907 }
908
909 /* Write to TIMx CR2 */
910 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
911
912 /* Write to TIMx CCMR1 */
913 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
914
915 /* Set the Capture Compare Register value */
916 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
917
918 /* Write to TIMx CCER */
919 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
920
921 return SUCCESS;
922 }
923
924 /**
925 * @brief Configure the TIMx output channel 3.
926 * @param TIMx Timer Instance
927 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
928 * @retval An ErrorStatus enumeration value:
929 * - SUCCESS: TIMx registers are de-initialized
930 * - ERROR: not applicable
931 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)932 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
933 {
934 uint32_t tmpccmr2;
935 uint32_t tmpccer;
936 uint32_t tmpcr2;
937
938 /* Check the parameters */
939 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
940 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
941 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
942 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
943
944 /* Disable the Channel 3: Reset the CC3E Bit */
945 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
946
947 /* Get the TIMx CCER register value */
948 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
949
950 /* Get the TIMx CR2 register value */
951 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
952
953 /* Get the TIMx CCMR2 register value */
954 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
955
956 /* Reset Capture/Compare selection Bits */
957 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
958
959 /* Select the Output Compare Mode */
960 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
961
962 /* Set the Output Compare Polarity */
963 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
964
965 /* Set the Output State */
966 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
967
968 if (IS_TIM_BREAK_INSTANCE(TIMx))
969 {
970 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
971 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
972 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
973 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
974
975 /* Set the complementary output Polarity */
976 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
977
978 /* Set the complementary output State */
979 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
980
981 /* Set the Output Idle state */
982 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
983
984 /* Set the complementary output Idle state */
985 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
986 }
987
988 /* Write to TIMx CR2 */
989 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
990
991 /* Write to TIMx CCMR2 */
992 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
993
994 /* Set the Capture Compare Register value */
995 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
996
997 /* Write to TIMx CCER */
998 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
999
1000 return SUCCESS;
1001 }
1002
1003 /**
1004 * @brief Configure the TIMx output channel 4.
1005 * @param TIMx Timer Instance
1006 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1007 * @retval An ErrorStatus enumeration value:
1008 * - SUCCESS: TIMx registers are de-initialized
1009 * - ERROR: not applicable
1010 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1011 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1012 {
1013 uint32_t tmpccmr2;
1014 uint32_t tmpccer;
1015 uint32_t tmpcr2;
1016
1017 /* Check the parameters */
1018 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1019 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1020 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1021 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1022
1023 /* Disable the Channel 4: Reset the CC4E Bit */
1024 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1025
1026 /* Get the TIMx CCER register value */
1027 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1028
1029 /* Get the TIMx CR2 register value */
1030 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1031
1032 /* Get the TIMx CCMR2 register value */
1033 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1034
1035 /* Reset Capture/Compare selection Bits */
1036 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1037
1038 /* Select the Output Compare Mode */
1039 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1040
1041 /* Set the Output Compare Polarity */
1042 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1043
1044 /* Set the Output State */
1045 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1046
1047 if (IS_TIM_BREAK_INSTANCE(TIMx))
1048 {
1049 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1050
1051 /* Set the Output Idle state */
1052 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1053 }
1054
1055 /* Write to TIMx CR2 */
1056 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1057
1058 /* Write to TIMx CCMR2 */
1059 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1060
1061 /* Set the Capture Compare Register value */
1062 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1063
1064 /* Write to TIMx CCER */
1065 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1066
1067 return SUCCESS;
1068 }
1069
1070 /**
1071 * @brief Configure the TIMx output channel 5.
1072 * @param TIMx Timer Instance
1073 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1074 * @retval An ErrorStatus enumeration value:
1075 * - SUCCESS: TIMx registers are de-initialized
1076 * - ERROR: not applicable
1077 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1078 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1079 {
1080 uint32_t tmpccmr3;
1081 uint32_t tmpccer;
1082
1083 /* Check the parameters */
1084 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1085 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1086 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1087 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1088 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1089 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1090
1091 /* Disable the Channel 5: Reset the CC5E Bit */
1092 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1093
1094 /* Get the TIMx CCER register value */
1095 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1096
1097 /* Get the TIMx CCMR3 register value */
1098 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1099
1100 /* Select the Output Compare Mode */
1101 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1102
1103 /* Set the Output Compare Polarity */
1104 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1105
1106 /* Set the Output State */
1107 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1108
1109 if (IS_TIM_BREAK_INSTANCE(TIMx))
1110 {
1111 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1112 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1113
1114 /* Set the Output Idle state */
1115 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1116
1117 }
1118
1119 /* Write to TIMx CCMR3 */
1120 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1121
1122 /* Set the Capture Compare Register value */
1123 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1124
1125 /* Write to TIMx CCER */
1126 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1127
1128 return SUCCESS;
1129 }
1130
1131 /**
1132 * @brief Configure the TIMx output channel 6.
1133 * @param TIMx Timer Instance
1134 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1135 * @retval An ErrorStatus enumeration value:
1136 * - SUCCESS: TIMx registers are de-initialized
1137 * - ERROR: not applicable
1138 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1139 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1140 {
1141 uint32_t tmpccmr3;
1142 uint32_t tmpccer;
1143
1144 /* Check the parameters */
1145 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1146 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1147 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1148 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1149 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1150 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1151
1152 /* Disable the Channel 5: Reset the CC6E Bit */
1153 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1154
1155 /* Get the TIMx CCER register value */
1156 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1157
1158 /* Get the TIMx CCMR3 register value */
1159 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1160
1161 /* Select the Output Compare Mode */
1162 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1163
1164 /* Set the Output Compare Polarity */
1165 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1166
1167 /* Set the Output State */
1168 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1169
1170 if (IS_TIM_BREAK_INSTANCE(TIMx))
1171 {
1172 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1173 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1174
1175 /* Set the Output Idle state */
1176 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1177 }
1178
1179 /* Write to TIMx CCMR3 */
1180 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1181
1182 /* Set the Capture Compare Register value */
1183 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1184
1185 /* Write to TIMx CCER */
1186 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1187
1188 return SUCCESS;
1189 }
1190
1191 /**
1192 * @brief Configure the TIMx input channel 1.
1193 * @param TIMx Timer Instance
1194 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1195 * @retval An ErrorStatus enumeration value:
1196 * - SUCCESS: TIMx registers are de-initialized
1197 * - ERROR: not applicable
1198 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1199 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1200 {
1201 /* Check the parameters */
1202 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1203 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1204 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1205 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1206 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1207
1208 /* Disable the Channel 1: Reset the CC1E Bit */
1209 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1210
1211 /* Select the Input and set the filter and the prescaler value */
1212 MODIFY_REG(TIMx->CCMR1,
1213 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1214 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1215
1216 /* Select the Polarity and set the CC1E Bit */
1217 MODIFY_REG(TIMx->CCER,
1218 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1219 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1220
1221 return SUCCESS;
1222 }
1223
1224 /**
1225 * @brief Configure the TIMx input channel 2.
1226 * @param TIMx Timer Instance
1227 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1228 * @retval An ErrorStatus enumeration value:
1229 * - SUCCESS: TIMx registers are de-initialized
1230 * - ERROR: not applicable
1231 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1232 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1233 {
1234 /* Check the parameters */
1235 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1236 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1237 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1238 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1239 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1240
1241 /* Disable the Channel 2: Reset the CC2E Bit */
1242 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1243
1244 /* Select the Input and set the filter and the prescaler value */
1245 MODIFY_REG(TIMx->CCMR1,
1246 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1247 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1248
1249 /* Select the Polarity and set the CC2E Bit */
1250 MODIFY_REG(TIMx->CCER,
1251 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1252 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1253
1254 return SUCCESS;
1255 }
1256
1257 /**
1258 * @brief Configure the TIMx input channel 3.
1259 * @param TIMx Timer Instance
1260 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1261 * @retval An ErrorStatus enumeration value:
1262 * - SUCCESS: TIMx registers are de-initialized
1263 * - ERROR: not applicable
1264 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1265 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1266 {
1267 /* Check the parameters */
1268 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1269 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1270 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1271 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1272 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1273
1274 /* Disable the Channel 3: Reset the CC3E Bit */
1275 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1276
1277 /* Select the Input and set the filter and the prescaler value */
1278 MODIFY_REG(TIMx->CCMR2,
1279 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1280 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1281
1282 /* Select the Polarity and set the CC3E Bit */
1283 MODIFY_REG(TIMx->CCER,
1284 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1285 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1286
1287 return SUCCESS;
1288 }
1289
1290 /**
1291 * @brief Configure the TIMx input channel 4.
1292 * @param TIMx Timer Instance
1293 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1294 * @retval An ErrorStatus enumeration value:
1295 * - SUCCESS: TIMx registers are de-initialized
1296 * - ERROR: not applicable
1297 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1298 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1299 {
1300 /* Check the parameters */
1301 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1302 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1303 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1304 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1305 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1306
1307 /* Disable the Channel 4: Reset the CC4E Bit */
1308 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1309
1310 /* Select the Input and set the filter and the prescaler value */
1311 MODIFY_REG(TIMx->CCMR2,
1312 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1313 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1314
1315 /* Select the Polarity and set the CC4E Bit */
1316 MODIFY_REG(TIMx->CCER,
1317 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1318 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1319
1320 return SUCCESS;
1321 }
1322
1323
1324 /**
1325 * @}
1326 */
1327
1328 /**
1329 * @}
1330 */
1331
1332 #endif /* TIM1 || TIM2 || TIM3 || TIM6 || TIM7 || TIM15 || TIM16 */
1333
1334 /**
1335 * @}
1336 */
1337
1338 #endif /* USE_FULL_LL_DRIVER */
1339
1340
