1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32u0xx_ll_rcc.h"
22 #ifdef USE_FULL_ASSERT
23 #include "stm32_assert.h"
24 #else
25 #define assert_param(expr) ((void)0U)
26 #endif /* USE_FULL_LL_DRIVER */
27 /** @addtogroup STM32U0xx_LL_Driver
28 * @{
29 */
30
31 #if defined(RCC)
32
33 /** @addtogroup RCC_LL
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /* Private constants ---------------------------------------------------------*/
40 /* Private macros ------------------------------------------------------------*/
41 /** @addtogroup RCC_LL_Private_Macros
42 * @{
43 */
44 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
45 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
46 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \
47 || ((__VALUE__) == LL_RCC_USART4_CLKSOURCE))
48 #if defined (LPUART3)
49 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) \
50 || ((__VALUE__) == LL_RCC_LPUART2_CLKSOURCE) \
51 || ((__VALUE__) == LL_RCC_LPUART3_CLKSOURCE))
52 #else
53 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) \
54 || ((__VALUE__) == LL_RCC_LPUART2_CLKSOURCE))
55 #endif /* LPUART3 */
56 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
57 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
58 #if defined (LPTIM3)
59 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
60 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
61 || ((__VALUE__) == LL_RCC_LPTIM3_CLKSOURCE))
62 #else
63 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
64 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))
65 #endif /* LPTIM3 */
66 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
67 || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE))
68
69 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
70 #if defined (USB)
71 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
72 #endif /* USB */
73 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
74
75
76 /**
77 * @}
78 */
79
80 /* Private function prototypes -----------------------------------------------*/
81 /** @defgroup RCC_LL_Private_Functions RCC Private functions
82 * @{
83 */
84 uint32_t RCC_GetSystemClockFreq(void);
85 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
86 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
87 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
88 uint32_t RCC_PLL_GetFreqDomain_PLLP(void);
89 uint32_t RCC_PLL_GetFreqDomain_PLLQ(void);
90 /**
91 * @}
92 */
93
94
95 /* Exported functions --------------------------------------------------------*/
96 /** @addtogroup RCC_LL_Exported_Functions
97 * @{
98 */
99
100 /** @addtogroup RCC_LL_EF_Init
101 * @{
102 */
103
104 /**
105 * @brief Reset the RCC clock configuration to the default reset state.
106 * @note The default reset state of the clock configuration is given below:
107 * - MSI ON and used as system clock source
108 * - HSE, HSI, PLL and PLLSAIxSource OFF
109 * - AHB, APB prescaler set to 1.
110 * - CSS, MCO OFF
111 * - All interrupts disabled
112 * @note This function doesn't modify the configuration of the
113 * - Peripheral clocks
114 * - LSI, LSE and RTC clocks
115 * @retval An ErrorStatus enumeration value:
116 * - SUCCESS: RCC registers are de-initialized
117 * - ERROR: not applicable
118 */
LL_RCC_DeInit(void)119 ErrorStatus LL_RCC_DeInit(void)
120 {
121 uint32_t vl_mask = 0U;
122
123 /* Set MSION bit */
124 LL_RCC_MSI_Enable();
125
126 /* Insure MSIRDY bit is set before writing default MSIRANGE value */
127 while (LL_RCC_MSI_IsReady() == 0U)
128 {
129 __NOP();
130 }
131
132 /* Set MSIRANGE default value */
133 LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
134 /* Set MSITRIM bits to the reset value*/
135 LL_RCC_MSI_SetCalibTrimming(0);
136
137 /* Set HSITRIM bits to the reset value*/
138 LL_RCC_HSI_SetCalibTrimming(0x10U);
139
140 /* Reset CFGR register */
141 LL_RCC_WriteReg(CFGR, 0x00000000U);
142
143 vl_mask = 0xFFFFFFFFU;
144 #if defined(RCC_CRRCR_HSI48ON)
145 /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLSYSON bits */
146 CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CRRCR_HSI48ON |
147 RCC_CR_PLLON));
148 #else
149 CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_PLLON));
150 #endif /* RCC_CRRCR_HSI48ON */
151 /* Write new mask in CR register */
152 LL_RCC_WriteReg(CR, vl_mask);
153
154 /* Reset PLLCFGR register */
155 LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);
156
157 /* Reset HSEBYP bit */
158 LL_RCC_HSE_DisableBypass();
159
160 /* Disable all interrupts */
161 LL_RCC_WriteReg(CIER, 0x00000000U);
162
163 return SUCCESS;
164 }
165
166 /**
167 * @}
168 */
169
170 /** @addtogroup RCC_LL_EF_Get_Freq
171 * @brief Return the frequencies of different on chip clocks; System, AHB, APB buses clocks
172 * and different peripheral clocks available on the device.
173 * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*)
174 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
175 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
176 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
177 * or HSI_VALUE(**) or MSI_VALUE(*) multiplied/divided by the PLL factors.
178 * @note (*) MSI_VALUE is a constant defined in this file (default value
179 * 4 MHz) but the real value may vary depending on the variations
180 * in voltage and temperature.
181 * @note (**) HSI_VALUE is a constant defined in this file (default value
182 * 16 MHz) but the real value may vary depending on the variations
183 * in voltage and temperature.
184 * @note (***) HSE_VALUE is a constant defined in this file (default value
185 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
186 * frequency of the crystal used. Otherwise, this function may
187 * have wrong result.
188 * @note The result of this function could be incorrect when using fractional
189 * value for HSE crystal.
190 * @note This function can be used by the user application to compute the
191 * baud-rate for the communication peripherals or configure other parameters.
192 * @{
193 */
194
195 /**
196 * @brief Return the frequencies of different on chip clocks; System, AHB, APB buses clocks
197 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
198 * must be called to update structure fields. Otherwise, any
199 * configuration based on this function will be incorrect.
200 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
201 * @retval None
202 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)203 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
204 {
205 /* Get SYSCLK frequency */
206 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
207
208 /* HCLK clock frequency */
209 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
210
211 /* PCLK1 clock frequency */
212 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
213
214 }
215
216 /**
217 * @brief Return USARTx clock frequency
218 * @param USARTxSource This parameter can be one of the following values:
219 * @arg @ref LL_RCC_USART1_CLKSOURCE
220 * @arg @ref LL_RCC_USART2_CLKSOURCE
221 * @arg @ref LL_RCC_USART3_CLKSOURCE
222 * @arg @ref LL_RCC_USART4_CLKSOURCE
223 *
224 * @retval USART clock frequency (in Hz)
225 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
226 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)227 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
228 {
229 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
230
231 /* Check parameter */
232 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
233
234 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
235 {
236 /* USART1CLK clock frequency */
237 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
238 {
239 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
240 usart_frequency = RCC_GetSystemClockFreq();
241 break;
242
243 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
244 if (LL_RCC_HSI_IsReady())
245 {
246 usart_frequency = HSI_VALUE;
247 }
248 break;
249
250 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
251 if (LL_RCC_LSE_IsReady())
252 {
253 usart_frequency = LSE_VALUE;
254 }
255 break;
256
257 case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */
258 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
259 break;
260
261 default:
262 break;
263 }
264 }
265 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
266 {
267 /* USART2CLK clock frequency */
268 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
269 {
270 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
271 usart_frequency = RCC_GetSystemClockFreq();
272 break;
273
274 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
275 if (LL_RCC_HSI_IsReady())
276 {
277 usart_frequency = HSI_VALUE;
278 }
279 break;
280
281 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
282 if (LL_RCC_LSE_IsReady())
283 {
284 usart_frequency = LSE_VALUE;
285 }
286 break;
287
288 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
289 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
290 break;
291
292 default:
293 break;
294 }
295 }
296 else if ((USARTxSource == LL_RCC_USART3_CLKSOURCE) || (USARTxSource == LL_RCC_USART4_CLKSOURCE))
297 {
298 /* USART3 or USART4 clock frequency : PCLK */
299 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
300 }
301 return usart_frequency;
302 }
303
304 /**
305 * @brief Return TIMx clock frequency
306 * @param TIMxSource This parameter can be one of the following values:
307 * @arg @ref LL_RCC_TIM1_CLKSOURCE
308 * @arg @ref LL_RCC_TIM15_CLKSOURCE
309 *
310 * (*) value not defined in all devices.
311 * @retval USART clock frequency (in Hz)
312 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
313 */
LL_RCC_GetTIMClockFreq(uint32_t TIMxSource)314 uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource)
315 {
316 uint32_t tim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
317
318 /* Check parameter */
319 assert_param(IS_LL_RCC_TIM_CLKSOURCE(TIMxSource));
320
321 if (TIMxSource == LL_RCC_TIM1_CLKSOURCE)
322 {
323 /* TIM1CLK clock frequency */
324 switch (LL_RCC_GetTIMClockSource(TIMxSource))
325 {
326 case LL_RCC_TIM1_CLKSOURCE_PCLK1: /* TIM1 Clock is System Clock */
327 if (LL_RCC_GetAPB1Prescaler() == LL_RCC_APB1_DIV_1)
328 {
329 tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
330 }
331 else
332 {
333 tim_frequency = 2 * (RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())));
334 }
335 break;
336
337 case LL_RCC_TIM1_CLKSOURCE_PLLQ: /* TIM1 Clock is PLLQ Osc. */
338 if (LL_RCC_PLL_IsReady())
339 {
340 tim_frequency = RCC_PLL_GetFreqDomain_PLLQ();
341 }
342 break;
343
344 default:
345 break;
346 }
347 }
348 else if (TIMxSource == LL_RCC_TIM15_CLKSOURCE)
349 {
350 switch (LL_RCC_GetTIMClockSource(TIMxSource))
351 {
352 case LL_RCC_TIM15_CLKSOURCE_PCLK1: /* TIM15 Clock is System Clock */
353 if (LL_RCC_GetAPB1Prescaler() == LL_RCC_APB1_DIV_1)
354 {
355 tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
356 }
357 else
358 {
359 tim_frequency = 2 * (RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())));
360 }
361 break;
362
363 case LL_RCC_TIM15_CLKSOURCE_PLLQ: /* TIM15 Clock is PLLQ Osc. */
364 if (LL_RCC_PLL_IsReady())
365 {
366 tim_frequency = RCC_PLL_GetFreqDomain_PLLQ();
367 }
368 break;
369
370 default:
371 break;
372 }
373 }
374 return tim_frequency;
375 }
376
377 /**
378 * @brief Return LPUARTx clock frequency
379 * @param LPUARTxSource This parameter can be one of the following values:
380 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
381 * @retval LPUART clock frequency (in Hz)
382 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
383 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)384 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
385 {
386 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
387
388 /* Check parameter */
389 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
390
391 if (LPUARTxSource == LL_RCC_LPUART1_CLKSOURCE)
392 {
393 /* LPUART1CLK clock frequency */
394 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
395 {
396 case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
397 lpuart_frequency = RCC_GetSystemClockFreq();
398 break;
399
400 case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */
401 lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
402 break;
403
404 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
405 if (LL_RCC_HSI_IsReady())
406 {
407 lpuart_frequency = HSI_VALUE;
408 }
409 break;
410
411 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
412 if (LL_RCC_LSE_IsReady() == 1)
413 {
414 lpuart_frequency = LSE_VALUE;
415 }
416 break;
417
418 default:
419 break;
420 }
421 }
422 else if (LPUARTxSource == LL_RCC_LPUART2_CLKSOURCE)
423 {
424 /* LPUART1CLK clock frequency */
425 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
426 {
427 case LL_RCC_LPUART2_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
428 lpuart_frequency = RCC_GetSystemClockFreq();
429 break;
430
431 case LL_RCC_LPUART2_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
432 if (LL_RCC_HSI_IsReady())
433 {
434 lpuart_frequency = HSI_VALUE;
435 }
436 break;
437
438 case LL_RCC_LPUART2_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
439 if (LL_RCC_LSE_IsReady())
440 {
441 lpuart_frequency = LSE_VALUE;
442 }
443 break;
444
445 case LL_RCC_LPUART2_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */
446 lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
447 break;
448
449 default:
450 break;
451 }
452 }
453 #if defined (LPUART3)
454 else if (LPUARTxSource == LL_RCC_LPUART3_CLKSOURCE)
455 {
456 /* LPUART1CLK clock frequency */
457 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
458 {
459 case LL_RCC_LPUART3_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
460 lpuart_frequency = RCC_GetSystemClockFreq();
461 break;
462
463 case LL_RCC_LPUART3_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
464 if (LL_RCC_HSI_IsReady())
465 {
466 lpuart_frequency = HSI_VALUE;
467 }
468 break;
469
470 case LL_RCC_LPUART3_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
471 if (LL_RCC_LSE_IsReady())
472 {
473 lpuart_frequency = LSE_VALUE;
474 }
475 break;
476
477 case LL_RCC_LPUART3_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */
478 lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
479 break;
480
481 default:
482 break;
483 }
484 }
485 #endif /* LPUART3 */
486 return lpuart_frequency;
487 }
488
489 /**
490 * @brief Return RTC clock frequency
491 * @retval RTC clock frequency (in Hz)
492 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready
493 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
494 */
LL_RCC_GetRTCClockFreq(void)495 uint32_t LL_RCC_GetRTCClockFreq(void)
496 {
497 uint32_t rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
498
499 /* RTCCLK clock frequency */
500 switch (LL_RCC_GetRTCClockSource())
501 {
502 case LL_RCC_RTC_CLKSOURCE_LSE: /* LSE clock used as RTC clock source */
503 if (LL_RCC_LSE_IsReady() == 1U)
504 {
505 rtc_frequency = LSE_VALUE;
506 }
507 break;
508
509 case LL_RCC_RTC_CLKSOURCE_LSI: /* LSI clock used as RTC clock source */
510 if (LL_RCC_LSI_IsReady() == 1U)
511 {
512 if (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV) == RCC_CSR_LSIPREDIV)
513 {
514 rtc_frequency = LSI_VALUE / 128U;
515 }
516 else
517 {
518 rtc_frequency = LSI_VALUE;
519 }
520 }
521 break;
522
523 case LL_RCC_RTC_CLKSOURCE_HSE_DIV32: /* HSE clock used as ADC clock source */
524 rtc_frequency = HSE_VALUE / 32U;
525 break;
526
527 case LL_RCC_RTC_CLKSOURCE_NONE: /* No clock used as RTC clock source */
528 rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
529 break;
530
531 default:
532 break;
533 }
534
535 return rtc_frequency;
536 }
537
538 /**
539 * @brief Return I2Cx clock frequency
540 * @param I2CxSource This parameter can be one of the following values:
541 * @arg @ref LL_RCC_I2C1_CLKSOURCE
542 * @arg @ref LL_RCC_I2C3_CLKSOURCE
543 *
544 * (*) value not defined in all devices.
545 * @retval I2C clock frequency (in Hz)
546 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
547 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)548 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
549 {
550 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
551
552 /* Check parameter */
553 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
554
555 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
556 {
557 /* I2C1 CLK clock frequency */
558 switch (LL_RCC_GetI2CClockSource(I2CxSource))
559 {
560 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
561 i2c_frequency = RCC_GetSystemClockFreq();
562 break;
563
564 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
565 if (LL_RCC_HSI_IsReady())
566 {
567 i2c_frequency = HSI_VALUE;
568 }
569 break;
570
571 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
572 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
573 break;
574
575 default:
576 break;
577 }
578 }
579 else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
580 {
581 /* I2C3 CLK clock frequency */
582 switch (LL_RCC_GetI2CClockSource(I2CxSource))
583 {
584 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
585 i2c_frequency = RCC_GetSystemClockFreq();
586 break;
587
588 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
589 if (LL_RCC_HSI_IsReady())
590 {
591 i2c_frequency = HSI_VALUE;
592 }
593 break;
594
595 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
596 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
597 break;
598
599 default:
600 break;
601 }
602 }
603
604 return i2c_frequency;
605 }
606
607 /**
608 * @brief Return LPTIMx clock frequency
609 * @param LPTIMxSource This parameter can be one of the following values:
610 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
611 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
612 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE (*)
613 *
614 * (*) value not defined in all devices.
615 * @retval LPTIM clock frequency (in Hz)
616 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
617 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)618 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
619 {
620 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
621
622 /* Check parameter */
623 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
624
625 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
626 {
627 /* LPTIM1CLK clock frequency */
628 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
629 {
630 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
631 if (LL_RCC_LSI_IsReady() == 1U)
632 {
633 if (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV) == RCC_CSR_LSIPREDIV)
634 {
635 lptim_frequency = LSI_VALUE / 128U;
636 }
637 else
638 {
639 lptim_frequency = LSI_VALUE;
640 }
641 }
642 break;
643 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
644 if (LL_RCC_HSI_IsReady())
645 {
646 lptim_frequency = HSI_VALUE;
647 }
648 break;
649
650 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
651 if (LL_RCC_LSE_IsReady())
652 {
653 lptim_frequency = LSE_VALUE;
654 }
655 break;
656
657 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
658 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
659 break;
660
661 default:
662 break;
663 }
664 }
665 else if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE)
666 {
667 /* LPTIM2CLK clock frequency */
668 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
669 {
670 case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */
671 if (LL_RCC_LSI_IsReady() == 1U)
672 {
673 if (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV) == RCC_CSR_LSIPREDIV)
674 {
675 lptim_frequency = LSI_VALUE / 128U;
676 }
677 else
678 {
679 lptim_frequency = LSI_VALUE;
680 }
681 }
682 break;
683
684 case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */
685 if (LL_RCC_HSI_IsReady())
686 {
687 lptim_frequency = HSI_VALUE;
688 }
689 break;
690
691 case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */
692 if (LL_RCC_LSE_IsReady())
693 {
694 lptim_frequency = LSE_VALUE;
695 }
696 break;
697
698 case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */
699 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
700 break;
701
702 default:
703 break;
704 }
705 }
706 #if defined (LPTIM3)
707 else
708 {
709 if (LPTIMxSource == LL_RCC_LPTIM3_CLKSOURCE)
710 {
711 /* LPTIM2CLK clock frequency */
712 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
713 {
714 case LL_RCC_LPTIM3_CLKSOURCE_LSI: /* LPTIM3 Clock is LSI Osc. */
715 if (LL_RCC_LSI_IsReady() == 1U)
716 {
717 if (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV) == RCC_CSR_LSIPREDIV)
718 {
719 lptim_frequency = LSI_VALUE / 128U;
720 }
721 else
722 {
723 lptim_frequency = LSI_VALUE;
724 }
725 }
726 break;
727
728 case LL_RCC_LPTIM3_CLKSOURCE_HSI: /* LPTIM3 Clock is HSI Osc. */
729 if (LL_RCC_HSI_IsReady())
730 {
731 lptim_frequency = HSI_VALUE;
732 }
733 break;
734
735 case LL_RCC_LPTIM3_CLKSOURCE_LSE: /* LPTIM3 Clock is LSE Osc. */
736 if (LL_RCC_LSE_IsReady())
737 {
738 lptim_frequency = LSE_VALUE;
739 }
740 break;
741
742 case LL_RCC_LPTIM3_CLKSOURCE_PCLK1: /* LPTIM3 Clock is PCLK1 */
743 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
744 break;
745
746 default:
747 break;
748 }
749 }
750 }
751 #endif /* LPTIM3 */
752 return lptim_frequency;
753 }
754
755 /**
756 * @brief Return RNGx clock frequency
757 * @param RNGxSource This parameter can be one of the following values:
758 * @arg @ref LL_RCC_RNG_CLKSOURCE
759 * @retval RNG clock frequency (in Hz)
760 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
761 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
762 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)763 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
764 {
765 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
766
767 /* Check parameter */
768 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
769
770 /* RNGCLK clock frequency */
771 switch (LL_RCC_GetRNGClockSource(RNGxSource))
772 {
773 case LL_RCC_RNG_CLKSOURCE_PLLQ: /* PLL clock used as RNG clock source */
774 if (LL_RCC_PLL_IsReady())
775 {
776 rng_frequency = RCC_PLL_GetFreqDomain_PLLQ();
777 }
778 break;
779
780 case LL_RCC_RNG_CLKSOURCE_MSI: /* MSI clock used as RNG clock source */
781 if (LL_RCC_MSI_IsReady())
782 {
783 rng_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
784 (LL_RCC_MSI_IsEnabledRangeSelect() ?
785 LL_RCC_MSI_GetRange() :
786 LL_RCC_MSI_GetRangeAfterStandby()));
787 }
788 break;
789
790 case LL_RCC_RNG_CLKSOURCE_NONE: /* No clock used as RNG clock source */
791 rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
792 break;
793
794 default:
795 break;
796
797 }
798
799 return rng_frequency;
800 }
801
802 #if defined (USB)
803 /**
804 * @brief Return USBx clock frequency
805 * @param USBxSource This parameter can be one of the following values:
806 * @arg @ref LL_RCC_USB_CLKSOURCE
807 * @retval USB clock frequency (in Hz)
808 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
809 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
810 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)811 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
812 {
813 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
814
815 /* Check parameter */
816 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
817
818 /* USBCLK clock frequency */
819 switch (LL_RCC_GetUSBClockSource(USBxSource))
820 {
821 case LL_RCC_USB_CLKSOURCE_PLLQ: /* PLL clock used as USB clock source */
822 if (LL_RCC_PLL_IsReady())
823 {
824 usb_frequency = RCC_PLL_GetFreqDomain_PLLQ();
825 }
826 break;
827
828 case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */
829 if (LL_RCC_MSI_IsReady())
830 {
831 usb_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
832 (LL_RCC_MSI_IsEnabledRangeSelect() ?
833 LL_RCC_MSI_GetRange() :
834 LL_RCC_MSI_GetRangeAfterStandby()));
835 }
836 break;
837
838 case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */
839 usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
840 break;
841
842 default:
843 break;
844 }
845
846 return usb_frequency;
847 }
848 #endif /* USB */
849 /**
850 * @brief Return ADCx clock frequency
851 * @param ADCxSource This parameter can be one of the following values:
852 * @arg @ref LL_RCC_ADC_CLKSOURCE
853 * @retval ADC clock frequency (in Hz)
854 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
855 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
856 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)857 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
858 {
859 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
860
861 /* Check parameter */
862 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
863
864 /* ADCCLK clock frequency */
865 switch (LL_RCC_GetADCClockSource(ADCxSource))
866 {
867 case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */
868 adc_frequency = RCC_GetSystemClockFreq();
869 break;
870 case LL_RCC_ADC_CLKSOURCE_HSI: /* ADC Clock is HSI Osc. */
871 if (LL_RCC_HSI_IsReady())
872 {
873 adc_frequency = HSI_VALUE;
874 }
875 break;
876 case LL_RCC_ADC_CLKSOURCE_PLLP: /* ADC Clock is HSI Osc. */
877 if (LL_RCC_PLL_IsReady() == 1U)
878 {
879 if (LL_RCC_PLL_IsEnabledDomain_PLLP() == 1U)
880 {
881 adc_frequency = RCC_PLL_GetFreqDomain_PLLP();
882 }
883 }
884 break;
885 case LL_RCC_ADC_CLKSOURCE_NONE: /* No clock used as ADC clock source */
886 adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
887 break;
888
889 default:
890 break;
891 }
892
893 return adc_frequency;
894 }
895
896 /**
897 * @}
898 */
899
900 /**
901 * @}
902 */
903
904 /** @addtogroup RCC_LL_Private_Functions
905 * @{
906 */
907
908 /**
909 * @brief Return SYSTEM clock frequency
910 * @retval SYSTEM clock frequency (in Hz)
911 */
RCC_GetSystemClockFreq(void)912 uint32_t RCC_GetSystemClockFreq(void)
913 {
914 uint32_t frequency = 0U;
915
916 /* Get SYSCLK source -------------------------------------------------------*/
917 switch (LL_RCC_GetSysClkSource())
918 {
919 case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
920 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
921 (LL_RCC_MSI_IsEnabledRangeSelect() ?
922 LL_RCC_MSI_GetRange() :
923 LL_RCC_MSI_GetRangeAfterStandby()));
924 break;
925
926 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
927 frequency = HSI_VALUE;
928 break;
929
930 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
931 frequency = HSE_VALUE;
932 break;
933
934 case LL_RCC_SYS_CLKSOURCE_STATUS_LSI: /* LSI used as system clock source */
935 if (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV) == RCC_CSR_LSIPREDIV)
936 {
937 frequency = LSI_VALUE / 128U;
938 }
939 else
940 {
941 frequency = LSI_VALUE;
942 }
943 break;
944
945 case LL_RCC_SYS_CLKSOURCE_STATUS_LSE: /* LSE used as system clock source */
946 frequency = LSE_VALUE;
947 break;
948
949 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
950 frequency = RCC_PLL_GetFreqDomain_SYS();
951 break;
952
953 default:
954 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
955 (LL_RCC_MSI_IsEnabledRangeSelect() ?
956 LL_RCC_MSI_GetRange() :
957 LL_RCC_MSI_GetRangeAfterStandby()));
958 break;
959 }
960
961 return frequency;
962 }
963
964 /**
965 * @brief Return HCLK clock frequency
966 * @param SYSCLK_Frequency SYSCLK clock frequency
967 * @retval HCLK clock frequency (in Hz)
968 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)969 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
970 {
971 /* HCLK clock frequency */
972 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
973 }
974
975 /**
976 * @brief Return PCLK1 clock frequency
977 * @param HCLK_Frequency HCLK clock frequency
978 * @retval PCLK1 clock frequency (in Hz)
979 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)980 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
981 {
982 /* PCLK1 clock frequency */
983 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
984 }
985
986 /**
987 * @brief Return PLLR clock frequency used for system domain
988 * @retval PLL clock frequency (in Hz)
989 */
RCC_PLL_GetFreqDomain_SYS(void)990 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
991 {
992 uint32_t pllinputfreq = 0U;
993 uint32_t pllsource = 0U;
994
995 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
996 SYSCLK = PLL_VCO / PLLR
997 */
998 pllsource = LL_RCC_PLL_GetMainSource();
999
1000 switch (pllsource)
1001 {
1002 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1003 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1004 (LL_RCC_MSI_IsEnabledRangeSelect() ?
1005 LL_RCC_MSI_GetRange() :
1006 LL_RCC_MSI_GetRangeAfterStandby()));
1007 break;
1008
1009 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1010 pllinputfreq = HSI_VALUE;
1011 break;
1012
1013 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1014 pllinputfreq = HSE_VALUE;
1015 break;
1016
1017 default:
1018 pllinputfreq = 0U;
1019 break;
1020 }
1021 return __LL_RCC_CALC_PLLCLK_R_FREQ(pllinputfreq, LL_RCC_PLL_GetM(),
1022 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1023 }
1024
1025 /**
1026 * @brief Return PLLP clock frequency used for ADC domain
1027 * @retval PLL clock frequency (in Hz)
1028 */
RCC_PLL_GetFreqDomain_PLLP(void)1029 uint32_t RCC_PLL_GetFreqDomain_PLLP(void)
1030 {
1031 uint32_t pllinputfreq = 0U;
1032 uint32_t pllsource = 0U;
1033
1034 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1035 PLLP clock = PLL_VCO / PLLP
1036 */
1037 pllsource = LL_RCC_PLL_GetMainSource();
1038
1039 switch (pllsource)
1040 {
1041 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1042 pllinputfreq = HSE_VALUE;
1043 break;
1044
1045 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1046 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1047 (LL_RCC_MSI_IsEnabledRangeSelect() ?
1048 LL_RCC_MSI_GetRange() :
1049 LL_RCC_MSI_GetRangeAfterStandby()));
1050 break;
1051
1052 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1053 pllinputfreq = HSI_VALUE;
1054 break;
1055
1056 default:
1057 pllinputfreq = 0U;
1058 break;
1059 }
1060 return __LL_RCC_CALC_PLLCLK_P_FREQ(pllinputfreq, LL_RCC_PLL_GetM(),
1061 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1062 }
1063
1064 /**
1065 * @brief Return PLLQ clock frequency used for 48 MHz domain
1066 * @retval PLL clock frequency (in Hz)
1067 */
RCC_PLL_GetFreqDomain_PLLQ(void)1068 uint32_t RCC_PLL_GetFreqDomain_PLLQ(void)
1069 {
1070 uint32_t pllinputfreq = 0U;
1071 uint32_t pllsource = 0U;
1072
1073 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
1074 PLLQ clock = PLL_VCO / PLLQ
1075 */
1076 pllsource = LL_RCC_PLL_GetMainSource();
1077
1078 switch (pllsource)
1079 {
1080 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1081 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1082 (LL_RCC_MSI_IsEnabledRangeSelect() ?
1083 LL_RCC_MSI_GetRange() :
1084 LL_RCC_MSI_GetRangeAfterStandby()));
1085 break;
1086
1087 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1088 pllinputfreq = HSI_VALUE;
1089 break;
1090
1091 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1092 pllinputfreq = HSE_VALUE;
1093 break;
1094
1095 default:
1096 pllinputfreq = 0U;
1097 break;
1098 }
1099 return __LL_RCC_CALC_PLLCLK_Q_FREQ(pllinputfreq, LL_RCC_PLL_GetM(),
1100 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1101 }
1102 /**
1103 * @}
1104 */
1105
1106 /**
1107 * @}
1108 */
1109
1110 #endif /* defined(RCC) */
1111
1112 /**
1113 * @}
1114 */
1115
1116 #endif /* USE_FULL_LL_DRIVER */
1117
