1 /**
2 ******************************************************************************
3 * @file stm32u0xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32u0xx_ll_adc.h"
22 #include "stm32u0xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32U0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* APB prescaler 16, ADC prescaler 4. */
62 /* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
63 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
64 /* CPU clock frequency max 48MHz, HSI frequency 16MHz: ratio 4. */
65 /* Unit: CPU cycles. */
66 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
67 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
69 /* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */
70 /* after the channel configuration has been changed. */
71 /* Driver timeout is approximated to 6 CPU cycles. */
72 #define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
73
74 /**
75 * @}
76 */
77
78 /* Private macros ------------------------------------------------------------*/
79
80 /** @addtogroup ADC_LL_Private_Macros
81 * @{
82 */
83
84 /* Check of parameters for configuration of ADC hierarchical scope: */
85 /* common to several ADC instances. */
86 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
87 (((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
98 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
99 )
100
101 #define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__) \
102 (((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH) \
103 || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW) \
104 )
105
106 /* Check of parameters for configuration of ADC hierarchical scope: */
107 /* ADC instance. */
108 #define IS_LL_ADC_CLOCK(__CLOCK__) \
109 (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
110 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
111 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
112 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
113 )
114
115 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
116 (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
117 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
118 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
119 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
120 )
121
122 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
123 (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
124 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
125 )
126
127 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
128 (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
129 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
130 || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
131 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
132 )
133
134 /* Check of parameters for configuration of ADC hierarchical scope: */
135 /* ADC group regular */
136 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
137 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
145 )
146
147 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
148 (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
149 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
150 )
151
152 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
153 (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
154 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
155 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
156 )
157
158 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
159 (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
160 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
161 )
162
163 #define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
164 (((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
165 || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
166 )
167
168 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
169 (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
170 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
171 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
172 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
173 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
174 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
175 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
176 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
177 )
178
179 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
180 (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
181 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
182 )
183
184 /**
185 * @}
186 */
187
188
189 /* Private function prototypes -----------------------------------------------*/
190
191 /* Exported functions --------------------------------------------------------*/
192 /** @addtogroup ADC_LL_Exported_Functions
193 * @{
194 */
195
196 /** @addtogroup ADC_LL_EF_Init
197 * @{
198 */
199
200 /**
201 * @brief De-initialize registers of all ADC instances belonging to
202 * the same ADC common instance to their default reset values.
203 * @note This function is performing a hard reset, using high level
204 * clock source RCC ADC reset.
205 * @param ADCxy_COMMON ADC common instance
206 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
207 * @retval An ErrorStatus enumeration value:
208 * - SUCCESS: ADC common registers are de-initialized
209 * - ERROR: not applicable
210 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)211 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
212 {
213 /* Check the parameters */
214 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
215
216 /* Prevent unused argument(s) compilation warning if no assert_param check */
217 (void)(ADCxy_COMMON);
218
219 /* Force reset of ADC clock (core clock) */
220 LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC);
221
222 /* Release reset of ADC clock (core clock) */
223 LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC);
224
225 return SUCCESS;
226 }
227
228 /**
229 * @brief Initialize some features of ADC common parameters
230 * (all ADC instances belonging to the same ADC common instance)
231 * and multimode (for devices with several ADC instances available).
232 * @note The setting of ADC common parameters is conditioned to
233 * ADC instances state:
234 * All ADC instances belonging to the same ADC common instance
235 * must be disabled.
236 * @param ADCxy_COMMON ADC common instance
237 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
238 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
239 * @retval An ErrorStatus enumeration value:
240 * - SUCCESS: ADC common registers are initialized
241 * - ERROR: ADC common registers are not initialized
242 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,const LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)243 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
244 {
245 ErrorStatus status = SUCCESS;
246
247 /* Check the parameters */
248 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
249 assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
250
251 /* Note: Hardware constraint (refer to description of functions */
252 /* "LL_ADC_SetCommonXXX()": */
253 /* On this STM32 series, setting of these features is conditioned to */
254 /* ADC state: */
255 /* All ADC instances of the ADC common group must be disabled. */
256 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
257 {
258 /* Configuration of ADC hierarchical scope: */
259 /* - common to several ADC */
260 /* (all ADC instances belonging to the same ADC common instance) */
261 /* - Set ADC clock (conversion clock) */
262 LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
263 }
264 else
265 {
266 /* Initialization error: One or several ADC instances belonging to */
267 /* the same ADC common instance are not disabled. */
268 status = ERROR;
269 }
270
271 return status;
272 }
273
274 /**
275 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
276 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
277 * whose fields will be set to default values.
278 * @retval None
279 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)280 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
281 {
282 /* Set pADC_CommonInitStruct fields to default values */
283 /* Set fields of ADC common */
284 /* (all ADC instances belonging to the same ADC common instance) */
285 pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
286
287 }
288
289 /**
290 * @brief De-initialize registers of the selected ADC instance
291 * to their default reset values.
292 * @note To reset all ADC instances quickly (perform a hard reset),
293 * use function @ref LL_ADC_CommonDeInit().
294 * @note If this functions returns error status, it means that ADC instance
295 * is in an unknown state.
296 * In this case, perform a hard reset using high level
297 * clock source RCC ADC reset.
298 * Refer to function @ref LL_ADC_CommonDeInit().
299 * @param ADCx ADC instance
300 * @retval An ErrorStatus enumeration value:
301 * - SUCCESS: ADC registers are de-initialized
302 * - ERROR: ADC registers are not de-initialized
303 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)304 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
305 {
306 ErrorStatus status = SUCCESS;
307
308 __IO uint32_t timeout_cpu_cycles = 0UL;
309
310 /* Check the parameters */
311 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
312
313 /* Disable ADC instance if not already disabled. */
314 if (LL_ADC_IsEnabled(ADCx) == 1UL)
315 {
316 /* Stop potential ADC conversion on going on ADC group regular. */
317 LL_ADC_REG_StopConversion(ADCx);
318
319 /* Wait for ADC conversions are effectively stopped */
320 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
321 while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
322 {
323 timeout_cpu_cycles--;
324 if (timeout_cpu_cycles == 0UL)
325 {
326 /* Time-out error */
327 status = ERROR;
328 break;
329 }
330 }
331
332 /* Disable the ADC instance */
333 LL_ADC_Disable(ADCx);
334
335 /* Wait for ADC instance is effectively disabled */
336 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
337 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
338 {
339 timeout_cpu_cycles--;
340 if (timeout_cpu_cycles == 0UL)
341 {
342 /* Time-out error */
343 status = ERROR;
344 break;
345 }
346 }
347 }
348
349 /* Check whether ADC state is compliant with expected state */
350 if (READ_BIT(ADCx->CR,
351 (ADC_CR_ADSTP | ADC_CR_ADSTART
352 | ADC_CR_ADDIS | ADC_CR_ADEN)
353 )
354 == 0UL)
355 {
356 /* ========== Reset ADC registers ========== */
357 /* Reset register IER */
358 CLEAR_BIT(ADCx->IER,
359 (LL_ADC_IT_ADRDY
360 | LL_ADC_IT_EOC
361 | LL_ADC_IT_EOS
362 | LL_ADC_IT_OVR
363 | LL_ADC_IT_EOSMP
364 | LL_ADC_IT_AWD1
365 | LL_ADC_IT_AWD2
366 | LL_ADC_IT_AWD3
367 | LL_ADC_IT_EOCAL
368 | LL_ADC_IT_CCRDY
369 )
370 );
371
372 /* Reset register ISR */
373 SET_BIT(ADCx->ISR,
374 (LL_ADC_FLAG_ADRDY
375 | LL_ADC_FLAG_EOC
376 | LL_ADC_FLAG_EOS
377 | LL_ADC_FLAG_OVR
378 | LL_ADC_FLAG_EOSMP
379 | LL_ADC_FLAG_AWD1
380 | LL_ADC_FLAG_AWD2
381 | LL_ADC_FLAG_AWD3
382 | LL_ADC_FLAG_EOCAL
383 | LL_ADC_FLAG_CCRDY
384 )
385 );
386
387 /* Reset register CR */
388 /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
389 /* "read-set": no direct reset applicable. */
390 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
391
392 /* Reset register CFGR1 */
393 CLEAR_BIT(ADCx->CFGR1,
394 (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
395 | ADC_CFGR1_CHSELRMOD | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
396 | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
397 | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)
398 );
399
400 /* Reset register SMPR */
401 CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
402
403 /* Reset register CHSELR */
404 CLEAR_BIT(ADCx->CHSELR,
405 (ADC_CHSELR_CHSEL19 | ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
406 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
407 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
408 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
409 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0)
410 );
411
412 /* Reset register AWD1TR */
413 MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1);
414
415 /* Reset register AWD2TR */
416 MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2);
417
418 /* Reset register AWD3TR */
419 MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3);
420
421 /* Wait for ADC channel configuration ready */
422 timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
423 while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
424 {
425 timeout_cpu_cycles--;
426 if (timeout_cpu_cycles == 0UL)
427 {
428 /* Time-out error */
429 status = ERROR;
430 break;
431 }
432 }
433
434 /* Clear flag ADC channel configuration ready */
435 LL_ADC_ClearFlag_CCRDY(ADCx);
436
437 /* Reset register DR */
438 /* bits in access mode read only, no direct reset applicable */
439
440 /* Reset register CALFACT */
441 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
442
443 /* Reset register CFGR2 */
444 /* Note: CFGR2 reset done at the end of de-initialization due to */
445 /* clock source reset */
446 /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
447 /* already done above. */
448 CLEAR_BIT(ADCx->CFGR2,
449 (ADC_CFGR2_CKMODE
450 | ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR
451 | ADC_CFGR2_OVSE)
452 );
453
454 }
455 else
456 {
457 /* ADC instance is in an unknown state */
458 /* Need to performing a hard reset of ADC instance, using high level */
459 /* clock source RCC ADC reset. */
460 /* Caution: On this STM32 series, if several ADC instances are available */
461 /* on the selected device, RCC ADC reset will reset */
462 /* all ADC instances belonging to the common ADC instance. */
463 status = ERROR;
464 }
465
466 return status;
467 }
468
469 /**
470 * @brief Initialize some features of ADC instance.
471 * @note These parameters have an impact on ADC scope: ADC instance.
472 * Refer to corresponding unitary functions into
473 * @ref ADC_LL_EF_Configuration_ADC_Instance .
474 * @note The setting of these parameters by function @ref LL_ADC_Init()
475 * is conditioned to ADC state:
476 * ADC instance must be disabled.
477 * This condition is applied to all ADC features, for efficiency
478 * and compatibility over all STM32 series. However, the different
479 * features can be set under different ADC state conditions
480 * (setting possible with ADC enabled without conversion on going,
481 * ADC enabled with conversion on going, ...)
482 * Each feature can be updated afterwards with a unitary function
483 * and potentially with ADC in a different state than disabled,
484 * refer to description of each function for setting
485 * conditioned to ADC state.
486 * @note After using this function, some other features must be configured
487 * using LL unitary functions.
488 * The minimum configuration remaining to be done is:
489 * - Set ADC group regular sequencer:
490 * Depending on the sequencer mode (refer to
491 * function @ref LL_ADC_REG_SetSequencerConfigurable() ):
492 * - map channel on the selected sequencer rank.
493 * Refer to function @ref LL_ADC_REG_SetSequencerRanks();
494 * - map channel on rank corresponding to channel number.
495 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
496 * - Set ADC channel sampling time
497 * Refer to function LL_ADC_SetSamplingTimeCommonChannels();
498 * Refer to function LL_ADC_SetChannelSamplingTime();
499 * @param ADCx ADC instance
500 * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
501 * @retval An ErrorStatus enumeration value:
502 * - SUCCESS: ADC registers are initialized
503 * - ERROR: ADC registers are not initialized
504 */
LL_ADC_Init(ADC_TypeDef * ADCx,const LL_ADC_InitTypeDef * pADC_InitStruct)505 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct)
506 {
507 ErrorStatus status = SUCCESS;
508
509 /* Check the parameters */
510 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
511
512 assert_param(IS_LL_ADC_CLOCK(pADC_InitStruct->Clock));
513 assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
514 assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
515 assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
516
517 /* Note: Hardware constraint (refer to description of this function): */
518 /* ADC instance must be disabled. */
519 if (LL_ADC_IsEnabled(ADCx) == 0UL)
520 {
521 /* Configuration of ADC hierarchical scope: */
522 /* - ADC instance */
523 /* - Set ADC data resolution */
524 /* - Set ADC conversion data alignment */
525 /* - Set ADC low power mode */
526 MODIFY_REG(ADCx->CFGR1,
527 ADC_CFGR1_RES
528 | ADC_CFGR1_ALIGN
529 | ADC_CFGR1_WAIT
530 | ADC_CFGR1_AUTOFF
531 ,
532 pADC_InitStruct->Resolution
533 | pADC_InitStruct->DataAlignment
534 | pADC_InitStruct->LowPowerMode
535 );
536
537 MODIFY_REG(ADCx->CFGR2,
538 ADC_CFGR2_CKMODE
539 ,
540 pADC_InitStruct->Clock
541 );
542 }
543 else
544 {
545 /* Initialization error: ADC instance is not disabled. */
546 status = ERROR;
547 }
548
549 return status;
550 }
551
552 /**
553 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
554 * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
555 * whose fields will be set to default values.
556 * @retval None
557 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * pADC_InitStruct)558 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
559 {
560 /* Set pADC_InitStruct fields to default values */
561 /* Set fields of ADC instance */
562 pADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
563 pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
564 pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
565 pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
566
567 }
568
569 /**
570 * @brief Initialize some features of ADC group regular.
571 * @note These parameters have an impact on ADC scope: ADC group regular.
572 * Refer to corresponding unitary functions into
573 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
574 * (functions with prefix "REG").
575 * @note The setting of these parameters by function @ref LL_ADC_Init()
576 * is conditioned to ADC state:
577 * ADC instance must be disabled.
578 * This condition is applied to all ADC features, for efficiency
579 * and compatibility over all STM32 series. However, the different
580 * features can be set under different ADC state conditions
581 * (setting possible with ADC enabled without conversion on going,
582 * ADC enabled with conversion on going, ...)
583 * Each feature can be updated afterwards with a unitary function
584 * and potentially with ADC in a different state than disabled,
585 * refer to description of each function for setting
586 * conditioned to ADC state.
587 * @note Before using this function, ADC group regular sequencer
588 * must be configured: refer to function
589 * @ref LL_ADC_REG_SetSequencerConfigurable().
590 * @note After using this function, other features must be configured
591 * using LL unitary functions.
592 * The minimum configuration remaining to be done is:
593 * - Set ADC group regular sequencer:
594 * Depending on the sequencer mode (refer to
595 * function @ref LL_ADC_REG_SetSequencerConfigurable() ):
596 * - map channel on the selected sequencer rank.
597 * Refer to function @ref LL_ADC_REG_SetSequencerRanks();
598 * - map channel on rank corresponding to channel number.
599 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
600 * - Set ADC channel sampling time
601 * Refer to function LL_ADC_SetSamplingTimeCommonChannels();
602 * Refer to function LL_ADC_SetChannelSamplingTime();
603 * @param ADCx ADC instance
604 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
605 * @retval An ErrorStatus enumeration value:
606 * - SUCCESS: ADC registers are initialized
607 * - ERROR: ADC registers are not initialized
608 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,const LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)609 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
610 {
611 ErrorStatus status = SUCCESS;
612
613 /* Check the parameters */
614 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
615 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
616 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
617 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
618 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
619
620 if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
621 {
622 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
623 }
624
625 if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
626 || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
627 )
628 {
629 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
630
631 /* ADC group regular continuous mode and discontinuous mode */
632 /* can not be enabled simultenaeously */
633 assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
634 || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
635 }
636
637 /* Note: Hardware constraint (refer to description of this function): */
638 /* ADC instance must be disabled. */
639 if (LL_ADC_IsEnabled(ADCx) == 0UL)
640 {
641 /* Configuration of ADC hierarchical scope: */
642 /* - ADC group regular */
643 /* - Set ADC group regular trigger source */
644 /* - Set ADC group regular sequencer length */
645 /* - Set ADC group regular sequencer discontinuous mode */
646 /* - Set ADC group regular continuous mode */
647 /* - Set ADC group regular conversion data transfer: no transfer or */
648 /* transfer by DMA, and DMA requests mode */
649 /* - Set ADC group regular overrun behavior */
650 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
651 /* setting of trigger source to SW start. */
652 if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
653 || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
654 )
655 {
656 /* Case of sequencer mode fixed
657 or sequencer length >= 2 ranks with sequencer mode fully configurable:
658 discontinuous mode configured */
659 MODIFY_REG(ADCx->CFGR1,
660 ADC_CFGR1_EXTSEL
661 | ADC_CFGR1_EXTEN
662 | ADC_CFGR1_DISCEN
663 | ADC_CFGR1_CONT
664 | ADC_CFGR1_DMAEN
665 | ADC_CFGR1_DMACFG
666 | ADC_CFGR1_OVRMOD
667 ,
668 pADC_RegInitStruct->TriggerSource
669 | pADC_RegInitStruct->SequencerDiscont
670 | pADC_RegInitStruct->ContinuousMode
671 | pADC_RegInitStruct->DMATransfer
672 | pADC_RegInitStruct->Overrun
673 );
674 }
675 else
676 {
677 /* Case of sequencer mode fully configurable
678 and sequencer length 1 rank (sequencer disabled):
679 discontinuous mode discarded (fixed to disable) */
680 MODIFY_REG(ADCx->CFGR1,
681 ADC_CFGR1_EXTSEL
682 | ADC_CFGR1_EXTEN
683 | ADC_CFGR1_DISCEN
684 | ADC_CFGR1_CONT
685 | ADC_CFGR1_DMAEN
686 | ADC_CFGR1_DMACFG
687 | ADC_CFGR1_OVRMOD
688 ,
689 pADC_RegInitStruct->TriggerSource
690 | LL_ADC_REG_SEQ_DISCONT_DISABLE
691 | pADC_RegInitStruct->ContinuousMode
692 | pADC_RegInitStruct->DMATransfer
693 | pADC_RegInitStruct->Overrun
694 );
695 }
696
697 /* Set ADC group regular sequencer length */
698 if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
699 {
700 LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
701 }
702 }
703 else
704 {
705 /* Initialization error: ADC instance is not disabled. */
706 status = ERROR;
707 }
708 return status;
709 }
710
711 /**
712 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
713 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
714 * whose fields will be set to default values.
715 * @retval None
716 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)717 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
718 {
719 /* Set pADC_RegInitStruct fields to default values */
720 /* Set fields of ADC group regular */
721 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
722 /* setting of trigger source to SW start. */
723 pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
724 pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
725 pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
726 pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
727 pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
728 pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
729 }
730
731 /**
732 * @}
733 */
734
735 /**
736 * @}
737 */
738
739 /**
740 * @}
741 */
742
743 #endif /* ADC1 */
744
745 /**
746 * @}
747 */
748
749 #endif /* USE_FULL_LL_DRIVER */
750
