1 /**
2 ******************************************************************************
3 * @file stm32u0xx_hal_tim_ex.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer Extended peripheral:
8 * + Time Hall Sensor Interface Initialization
9 * + Time Hall Sensor Interface Start
10 * + Time Complementary signal break and dead time configuration
11 * + Time Master and Slave synchronization configuration
12 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
13 * + Time OCRef clear configuration
14 * + Timer remapping capabilities configuration
15 ******************************************************************************
16 * @attention
17 *
18 * Copyright (c) 2023 STMicroelectronics.
19 * All rights reserved.
20 *
21 * This software is licensed under terms that can be found in the LICENSE file
22 * in the root directory of this software component.
23 * If no LICENSE file comes with this software, it is provided AS-IS.
24 *
25 ******************************************************************************
26 @verbatim
27 ==============================================================================
28 ##### TIMER Extended features #####
29 ==============================================================================
30 [..]
31 The Timer Extended features include:
32 (#) Complementary outputs with programmable dead-time for :
33 (++) Output Compare
34 (++) PWM generation (Edge and Center-aligned Mode)
35 (++) One-pulse mode output
36 (#) Synchronization circuit to control the timer with external signals and to
37 interconnect several timers together.
38 (#) Break input to put the timer output signals in reset state or in a known state.
39 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
40 positioning purposes
41
42 ##### How to use this driver #####
43 ==============================================================================
44 [..]
45 (#) Initialize the TIM low level resources by implementing the following functions
46 depending on the selected feature:
47 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
48
49 (#) Initialize the TIM low level resources :
50 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
51 (##) TIM pins configuration
52 (+++) Enable the clock for the TIM GPIOs using the following function:
53 __HAL_RCC_GPIOx_CLK_ENABLE();
54 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
55
56 (#) The external Clock can be configured, if needed (the default clock is the
57 internal clock from the APBx), using the following function:
58 HAL_TIM_ConfigClockSource, the clock configuration should be done before
59 any start function.
60
61 (#) Configure the TIM in the desired functioning mode using one of the
62 initialization function of this driver:
63 (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
64 Timer Hall Sensor Interface and the commutation event with the corresponding
65 Interrupt and DMA request if needed (Note that One Timer is used to interface
66 with the Hall sensor Interface and another Timer should be used to use
67 the commutation event).
68
69 (#) Activate the TIM peripheral using one of the start functions:
70 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
71 HAL_TIMEx_OCN_Start_IT()
72 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
73 HAL_TIMEx_PWMN_Start_IT()
74 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
75 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
76 HAL_TIMEx_HallSensor_Start_IT().
77
78 @endverbatim
79 ******************************************************************************
80 */
81
82 /* Includes ------------------------------------------------------------------*/
83 #include "stm32u0xx_hal.h"
84
85 /** @addtogroup STM32U0xx_HAL_Driver
86 * @{
87 */
88
89 /** @defgroup TIMEx TIMEx
90 * @brief TIM Extended HAL module driver
91 * @{
92 */
93
94 #ifdef HAL_TIM_MODULE_ENABLED
95
96 /* Private typedef -----------------------------------------------------------*/
97 /* Private define ------------------------------------------------------------*/
98 /* Private constants ---------------------------------------------------------*/
99 /** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
100 * @{
101 */
102 /* Timeout for break input rearm */
103 #define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */
104 /**
105 * @}
106 */
107 /* End of private constants --------------------------------------------------*/
108
109 /* Private macros ------------------------------------------------------------*/
110 /* Private variables ---------------------------------------------------------*/
111 /* Private function prototypes -----------------------------------------------*/
112 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
113 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
114 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
115
116 /* Exported functions --------------------------------------------------------*/
117 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
118 * @{
119 */
120
121 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
122 * @brief Timer Hall Sensor functions
123 *
124 @verbatim
125 ==============================================================================
126 ##### Timer Hall Sensor functions #####
127 ==============================================================================
128 [..]
129 This section provides functions allowing to:
130 (+) Initialize and configure TIM HAL Sensor.
131 (+) De-initialize TIM HAL Sensor.
132 (+) Start the Hall Sensor Interface.
133 (+) Stop the Hall Sensor Interface.
134 (+) Start the Hall Sensor Interface and enable interrupts.
135 (+) Stop the Hall Sensor Interface and disable interrupts.
136 (+) Start the Hall Sensor Interface and enable DMA transfers.
137 (+) Stop the Hall Sensor Interface and disable DMA transfers.
138
139 @endverbatim
140 * @{
141 */
142 /**
143 * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
144 * @note When the timer instance is initialized in Hall Sensor Interface mode,
145 * timer channels 1 and channel 2 are reserved and cannot be used for
146 * other purpose.
147 * @param htim TIM Hall Sensor Interface handle
148 * @param sConfig TIM Hall Sensor configuration structure
149 * @retval HAL status
150 */
HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef * htim,const TIM_HallSensor_InitTypeDef * sConfig)151 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
152 {
153 TIM_OC_InitTypeDef OC_Config;
154
155 /* Check the TIM handle allocation */
156 if (htim == NULL)
157 {
158 return HAL_ERROR;
159 }
160
161 /* Check the parameters */
162 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
163 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
164 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
165 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
166 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
167 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
168 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
169 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
170
171 if (htim->State == HAL_TIM_STATE_RESET)
172 {
173 /* Allocate lock resource and initialize it */
174 htim->Lock = HAL_UNLOCKED;
175
176 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
177 /* Reset interrupt callbacks to legacy week callbacks */
178 TIM_ResetCallback(htim);
179
180 if (htim->HallSensor_MspInitCallback == NULL)
181 {
182 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
183 }
184 /* Init the low level hardware : GPIO, CLOCK, NVIC */
185 htim->HallSensor_MspInitCallback(htim);
186 #else
187 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
188 HAL_TIMEx_HallSensor_MspInit(htim);
189 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
190 }
191
192 /* Set the TIM state */
193 htim->State = HAL_TIM_STATE_BUSY;
194
195 /* Configure the Time base in the Encoder Mode */
196 TIM_Base_SetConfig(htim->Instance, &htim->Init);
197
198 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
199 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
200
201 /* Reset the IC1PSC Bits */
202 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
203 /* Set the IC1PSC value */
204 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
205
206 /* Enable the Hall sensor interface (XOR function of the three inputs) */
207 htim->Instance->CR2 |= TIM_CR2_TI1S;
208
209 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
210 htim->Instance->SMCR &= ~TIM_SMCR_TS;
211 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
212
213 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
214 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
215 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
216
217 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
218 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
219 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
220 OC_Config.OCMode = TIM_OCMODE_PWM2;
221 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
222 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
223 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
224 OC_Config.Pulse = sConfig->Commutation_Delay;
225
226 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
227
228 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
229 register to 101 */
230 htim->Instance->CR2 &= ~TIM_CR2_MMS;
231 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
232
233 /* Initialize the DMA burst operation state */
234 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
235
236 /* Initialize the TIM channels state */
237 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
238 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
239 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
240 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
241
242 /* Initialize the TIM state*/
243 htim->State = HAL_TIM_STATE_READY;
244
245 return HAL_OK;
246 }
247
248 /**
249 * @brief DeInitializes the TIM Hall Sensor interface
250 * @param htim TIM Hall Sensor Interface handle
251 * @retval HAL status
252 */
HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef * htim)253 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
254 {
255 /* Check the parameters */
256 assert_param(IS_TIM_INSTANCE(htim->Instance));
257
258 htim->State = HAL_TIM_STATE_BUSY;
259
260 /* Disable the TIM Peripheral Clock */
261 __HAL_TIM_DISABLE(htim);
262
263 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
264 if (htim->HallSensor_MspDeInitCallback == NULL)
265 {
266 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
267 }
268 /* DeInit the low level hardware */
269 htim->HallSensor_MspDeInitCallback(htim);
270 #else
271 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
272 HAL_TIMEx_HallSensor_MspDeInit(htim);
273 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
274
275 /* Change the DMA burst operation state */
276 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
277
278 /* Change the TIM channels state */
279 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
280 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
281 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
282 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
283
284 /* Change TIM state */
285 htim->State = HAL_TIM_STATE_RESET;
286
287 /* Release Lock */
288 __HAL_UNLOCK(htim);
289
290 return HAL_OK;
291 }
292
293 /**
294 * @brief Initializes the TIM Hall Sensor MSP.
295 * @param htim TIM Hall Sensor Interface handle
296 * @retval None
297 */
HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef * htim)298 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
299 {
300 /* Prevent unused argument(s) compilation warning */
301 UNUSED(htim);
302
303 /* NOTE : This function should not be modified, when the callback is needed,
304 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
305 */
306 }
307
308 /**
309 * @brief DeInitializes TIM Hall Sensor MSP.
310 * @param htim TIM Hall Sensor Interface handle
311 * @retval None
312 */
HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef * htim)313 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
314 {
315 /* Prevent unused argument(s) compilation warning */
316 UNUSED(htim);
317
318 /* NOTE : This function should not be modified, when the callback is needed,
319 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
320 */
321 }
322
323 /**
324 * @brief Starts the TIM Hall Sensor Interface.
325 * @param htim TIM Hall Sensor Interface handle
326 * @retval HAL status
327 */
HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef * htim)328 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
329 {
330 uint32_t tmpsmcr;
331 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
332 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
333 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
334 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
335
336 /* Check the parameters */
337 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
338
339 /* Check the TIM channels state */
340 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
341 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
342 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
343 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
344 {
345 return HAL_ERROR;
346 }
347
348 /* Set the TIM channels state */
349 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
350 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
351 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
352 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
353
354 /* Enable the Input Capture channel 1
355 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
356 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
357 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
358
359 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
360 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
361 {
362 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
363 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
364 {
365 __HAL_TIM_ENABLE(htim);
366 }
367 }
368 else
369 {
370 __HAL_TIM_ENABLE(htim);
371 }
372
373 /* Return function status */
374 return HAL_OK;
375 }
376
377 /**
378 * @brief Stops the TIM Hall sensor Interface.
379 * @param htim TIM Hall Sensor Interface handle
380 * @retval HAL status
381 */
HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef * htim)382 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
383 {
384 /* Check the parameters */
385 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
386
387 /* Disable the Input Capture channels 1, 2 and 3
388 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
389 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
390 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
391
392 /* Disable the Peripheral */
393 __HAL_TIM_DISABLE(htim);
394
395 /* Set the TIM channels state */
396 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
397 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
398 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
399 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
400
401 /* Return function status */
402 return HAL_OK;
403 }
404
405 /**
406 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
407 * @param htim TIM Hall Sensor Interface handle
408 * @retval HAL status
409 */
HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef * htim)410 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
411 {
412 uint32_t tmpsmcr;
413 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
414 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
415 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
416 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
417
418 /* Check the parameters */
419 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
420
421 /* Check the TIM channels state */
422 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
423 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
424 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
425 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
426 {
427 return HAL_ERROR;
428 }
429
430 /* Set the TIM channels state */
431 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
432 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
433 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
434 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
435
436 /* Enable the capture compare Interrupts 1 event */
437 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
438
439 /* Enable the Input Capture channel 1
440 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
441 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
442 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
443
444 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
445 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
446 {
447 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
448 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
449 {
450 __HAL_TIM_ENABLE(htim);
451 }
452 }
453 else
454 {
455 __HAL_TIM_ENABLE(htim);
456 }
457
458 /* Return function status */
459 return HAL_OK;
460 }
461
462 /**
463 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
464 * @param htim TIM Hall Sensor Interface handle
465 * @retval HAL status
466 */
HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef * htim)467 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
468 {
469 /* Check the parameters */
470 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
471
472 /* Disable the Input Capture channel 1
473 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
474 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
475 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
476
477 /* Disable the capture compare Interrupts event */
478 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
479
480 /* Disable the Peripheral */
481 __HAL_TIM_DISABLE(htim);
482
483 /* Set the TIM channels state */
484 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
485 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
486 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
487 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
488
489 /* Return function status */
490 return HAL_OK;
491 }
492
493 /**
494 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
495 * @param htim TIM Hall Sensor Interface handle
496 * @param pData The destination Buffer address.
497 * @param Length The length of data to be transferred from TIM peripheral to memory.
498 * @retval HAL status
499 */
HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)500 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
501 {
502 uint32_t tmpsmcr;
503 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
504 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
505
506 /* Check the parameters */
507 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
508
509 /* Set the TIM channel state */
510 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
511 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
512 {
513 return HAL_BUSY;
514 }
515 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
516 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
517 {
518 if ((pData == NULL) || (Length == 0U))
519 {
520 return HAL_ERROR;
521 }
522 else
523 {
524 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
525 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
526 }
527 }
528 else
529 {
530 return HAL_ERROR;
531 }
532
533 /* Enable the Input Capture channel 1
534 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
535 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
536 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
537
538 /* Set the DMA Input Capture 1 Callbacks */
539 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
540 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
541 /* Set the DMA error callback */
542 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
543
544 /* Enable the DMA channel for Capture 1*/
545 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
546 {
547 /* Return error status */
548 return HAL_ERROR;
549 }
550 /* Enable the capture compare 1 Interrupt */
551 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
552
553 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
554 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
555 {
556 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
557 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
558 {
559 __HAL_TIM_ENABLE(htim);
560 }
561 }
562 else
563 {
564 __HAL_TIM_ENABLE(htim);
565 }
566
567 /* Return function status */
568 return HAL_OK;
569 }
570
571 /**
572 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
573 * @param htim TIM Hall Sensor Interface handle
574 * @retval HAL status
575 */
HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef * htim)576 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
577 {
578 /* Check the parameters */
579 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
580
581 /* Disable the Input Capture channel 1
582 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
583 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
584 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
585
586
587 /* Disable the capture compare Interrupts 1 event */
588 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
589
590 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
591
592 /* Disable the Peripheral */
593 __HAL_TIM_DISABLE(htim);
594
595 /* Set the TIM channel state */
596 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
597 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
598
599 /* Return function status */
600 return HAL_OK;
601 }
602
603 /**
604 * @}
605 */
606
607 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
608 * @brief Timer Complementary Output Compare functions
609 *
610 @verbatim
611 ==============================================================================
612 ##### Timer Complementary Output Compare functions #####
613 ==============================================================================
614 [..]
615 This section provides functions allowing to:
616 (+) Start the Complementary Output Compare/PWM.
617 (+) Stop the Complementary Output Compare/PWM.
618 (+) Start the Complementary Output Compare/PWM and enable interrupts.
619 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
620 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
621 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
622
623 @endverbatim
624 * @{
625 */
626
627 /**
628 * @brief Starts the TIM Output Compare signal generation on the complementary
629 * output.
630 * @param htim TIM Output Compare handle
631 * @param Channel TIM Channel to be enabled
632 * This parameter can be one of the following values:
633 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
634 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
635 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
636 * @retval HAL status
637 */
HAL_TIMEx_OCN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)638 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
639 {
640 uint32_t tmpsmcr;
641
642 /* Check the parameters */
643 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
644
645 /* Check the TIM complementary channel state */
646 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
647 {
648 return HAL_ERROR;
649 }
650
651 /* Set the TIM complementary channel state */
652 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
653
654 /* Enable the Capture compare channel N */
655 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
656
657 /* Enable the Main Output */
658 __HAL_TIM_MOE_ENABLE(htim);
659
660 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
661 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
662 {
663 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
664 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
665 {
666 __HAL_TIM_ENABLE(htim);
667 }
668 }
669 else
670 {
671 __HAL_TIM_ENABLE(htim);
672 }
673
674 /* Return function status */
675 return HAL_OK;
676 }
677
678 /**
679 * @brief Stops the TIM Output Compare signal generation on the complementary
680 * output.
681 * @param htim TIM handle
682 * @param Channel TIM Channel to be disabled
683 * This parameter can be one of the following values:
684 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
685 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
686 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
687 * @retval HAL status
688 */
HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)689 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
690 {
691 /* Check the parameters */
692 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
693
694 /* Disable the Capture compare channel N */
695 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
696
697 /* Disable the Main Output */
698 __HAL_TIM_MOE_DISABLE(htim);
699
700 /* Disable the Peripheral */
701 __HAL_TIM_DISABLE(htim);
702
703 /* Set the TIM complementary channel state */
704 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
705
706 /* Return function status */
707 return HAL_OK;
708 }
709
710 /**
711 * @brief Starts the TIM Output Compare signal generation in interrupt mode
712 * on the complementary output.
713 * @param htim TIM OC handle
714 * @param Channel TIM Channel to be enabled
715 * This parameter can be one of the following values:
716 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
717 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
718 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
719 * @retval HAL status
720 */
HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)721 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
722 {
723 HAL_StatusTypeDef status = HAL_OK;
724 uint32_t tmpsmcr;
725
726 /* Check the parameters */
727 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
728
729 /* Check the TIM complementary channel state */
730 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
731 {
732 return HAL_ERROR;
733 }
734
735 /* Set the TIM complementary channel state */
736 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
737
738 switch (Channel)
739 {
740 case TIM_CHANNEL_1:
741 {
742 /* Enable the TIM Output Compare interrupt */
743 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
744 break;
745 }
746
747 case TIM_CHANNEL_2:
748 {
749 /* Enable the TIM Output Compare interrupt */
750 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
751 break;
752 }
753
754 case TIM_CHANNEL_3:
755 {
756 /* Enable the TIM Output Compare interrupt */
757 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
758 break;
759 }
760
761
762 default:
763 status = HAL_ERROR;
764 break;
765 }
766
767 if (status == HAL_OK)
768 {
769 /* Enable the TIM Break interrupt */
770 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
771
772 /* Enable the Capture compare channel N */
773 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
774
775 /* Enable the Main Output */
776 __HAL_TIM_MOE_ENABLE(htim);
777
778 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
779 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
780 {
781 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
782 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
783 {
784 __HAL_TIM_ENABLE(htim);
785 }
786 }
787 else
788 {
789 __HAL_TIM_ENABLE(htim);
790 }
791 }
792
793 /* Return function status */
794 return status;
795 }
796
797 /**
798 * @brief Stops the TIM Output Compare signal generation in interrupt mode
799 * on the complementary output.
800 * @param htim TIM Output Compare handle
801 * @param Channel TIM Channel to be disabled
802 * This parameter can be one of the following values:
803 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
804 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
805 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
806 * @retval HAL status
807 */
HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)808 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
809 {
810 HAL_StatusTypeDef status = HAL_OK;
811 uint32_t tmpccer;
812
813 /* Check the parameters */
814 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
815
816 switch (Channel)
817 {
818 case TIM_CHANNEL_1:
819 {
820 /* Disable the TIM Output Compare interrupt */
821 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
822 break;
823 }
824
825 case TIM_CHANNEL_2:
826 {
827 /* Disable the TIM Output Compare interrupt */
828 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
829 break;
830 }
831
832 case TIM_CHANNEL_3:
833 {
834 /* Disable the TIM Output Compare interrupt */
835 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
836 break;
837 }
838
839 default:
840 status = HAL_ERROR;
841 break;
842 }
843
844 if (status == HAL_OK)
845 {
846 /* Disable the Capture compare channel N */
847 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
848
849 /* Disable the TIM Break interrupt (only if no more channel is active) */
850 tmpccer = htim->Instance->CCER;
851 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
852 {
853 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
854 }
855
856 /* Disable the Main Output */
857 __HAL_TIM_MOE_DISABLE(htim);
858
859 /* Disable the Peripheral */
860 __HAL_TIM_DISABLE(htim);
861
862 /* Set the TIM complementary channel state */
863 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
864 }
865
866 /* Return function status */
867 return status;
868 }
869
870 /**
871 * @brief Starts the TIM Output Compare signal generation in DMA mode
872 * on the complementary output.
873 * @param htim TIM Output Compare handle
874 * @param Channel TIM Channel to be enabled
875 * This parameter can be one of the following values:
876 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
877 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
878 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
879 * @param pData The source Buffer address.
880 * @param Length The length of data to be transferred from memory to TIM peripheral
881 * @retval HAL status
882 */
HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)883 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
884 uint16_t Length)
885 {
886 HAL_StatusTypeDef status = HAL_OK;
887 uint32_t tmpsmcr;
888
889 /* Check the parameters */
890 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
891
892 /* Set the TIM complementary channel state */
893 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
894 {
895 return HAL_BUSY;
896 }
897 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
898 {
899 if ((pData == NULL) || (Length == 0U))
900 {
901 return HAL_ERROR;
902 }
903 else
904 {
905 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
906 }
907 }
908 else
909 {
910 return HAL_ERROR;
911 }
912
913 switch (Channel)
914 {
915 case TIM_CHANNEL_1:
916 {
917 /* Set the DMA compare callbacks */
918 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
919 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
920
921 /* Set the DMA error callback */
922 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
923
924 /* Enable the DMA channel */
925 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
926 Length) != HAL_OK)
927 {
928 /* Return error status */
929 return HAL_ERROR;
930 }
931 /* Enable the TIM Output Compare DMA request */
932 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
933 break;
934 }
935
936 case TIM_CHANNEL_2:
937 {
938 /* Set the DMA compare callbacks */
939 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
940 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
941
942 /* Set the DMA error callback */
943 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
944
945 /* Enable the DMA channel */
946 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
947 Length) != HAL_OK)
948 {
949 /* Return error status */
950 return HAL_ERROR;
951 }
952 /* Enable the TIM Output Compare DMA request */
953 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
954 break;
955 }
956
957 case TIM_CHANNEL_3:
958 {
959 /* Set the DMA compare callbacks */
960 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
961 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
962
963 /* Set the DMA error callback */
964 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
965
966 /* Enable the DMA channel */
967 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
968 Length) != HAL_OK)
969 {
970 /* Return error status */
971 return HAL_ERROR;
972 }
973 /* Enable the TIM Output Compare DMA request */
974 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
975 break;
976 }
977
978 default:
979 status = HAL_ERROR;
980 break;
981 }
982
983 if (status == HAL_OK)
984 {
985 /* Enable the Capture compare channel N */
986 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
987
988 /* Enable the Main Output */
989 __HAL_TIM_MOE_ENABLE(htim);
990
991 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
992 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
993 {
994 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
995 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
996 {
997 __HAL_TIM_ENABLE(htim);
998 }
999 }
1000 else
1001 {
1002 __HAL_TIM_ENABLE(htim);
1003 }
1004 }
1005
1006 /* Return function status */
1007 return status;
1008 }
1009
1010 /**
1011 * @brief Stops the TIM Output Compare signal generation in DMA mode
1012 * on the complementary output.
1013 * @param htim TIM Output Compare handle
1014 * @param Channel TIM Channel to be disabled
1015 * This parameter can be one of the following values:
1016 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1017 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1018 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1019 * @retval HAL status
1020 */
HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1021 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1022 {
1023 HAL_StatusTypeDef status = HAL_OK;
1024
1025 /* Check the parameters */
1026 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1027
1028 switch (Channel)
1029 {
1030 case TIM_CHANNEL_1:
1031 {
1032 /* Disable the TIM Output Compare DMA request */
1033 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1034 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1035 break;
1036 }
1037
1038 case TIM_CHANNEL_2:
1039 {
1040 /* Disable the TIM Output Compare DMA request */
1041 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1042 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1043 break;
1044 }
1045
1046 case TIM_CHANNEL_3:
1047 {
1048 /* Disable the TIM Output Compare DMA request */
1049 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1050 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1051 break;
1052 }
1053
1054 default:
1055 status = HAL_ERROR;
1056 break;
1057 }
1058
1059 if (status == HAL_OK)
1060 {
1061 /* Disable the Capture compare channel N */
1062 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1063
1064 /* Disable the Main Output */
1065 __HAL_TIM_MOE_DISABLE(htim);
1066
1067 /* Disable the Peripheral */
1068 __HAL_TIM_DISABLE(htim);
1069
1070 /* Set the TIM complementary channel state */
1071 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1072 }
1073
1074 /* Return function status */
1075 return status;
1076 }
1077
1078 /**
1079 * @}
1080 */
1081
1082 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
1083 * @brief Timer Complementary PWM functions
1084 *
1085 @verbatim
1086 ==============================================================================
1087 ##### Timer Complementary PWM functions #####
1088 ==============================================================================
1089 [..]
1090 This section provides functions allowing to:
1091 (+) Start the Complementary PWM.
1092 (+) Stop the Complementary PWM.
1093 (+) Start the Complementary PWM and enable interrupts.
1094 (+) Stop the Complementary PWM and disable interrupts.
1095 (+) Start the Complementary PWM and enable DMA transfers.
1096 (+) Stop the Complementary PWM and disable DMA transfers.
1097 @endverbatim
1098 * @{
1099 */
1100
1101 /**
1102 * @brief Starts the PWM signal generation on the complementary output.
1103 * @param htim TIM handle
1104 * @param Channel TIM Channel to be enabled
1105 * This parameter can be one of the following values:
1106 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1107 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1108 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1109 * @retval HAL status
1110 */
HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1111 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1112 {
1113 uint32_t tmpsmcr;
1114
1115 /* Check the parameters */
1116 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1117
1118 /* Check the TIM complementary channel state */
1119 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1120 {
1121 return HAL_ERROR;
1122 }
1123
1124 /* Set the TIM complementary channel state */
1125 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1126
1127 /* Enable the complementary PWM output */
1128 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1129
1130 /* Enable the Main Output */
1131 __HAL_TIM_MOE_ENABLE(htim);
1132
1133 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1134 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1135 {
1136 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1137 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1138 {
1139 __HAL_TIM_ENABLE(htim);
1140 }
1141 }
1142 else
1143 {
1144 __HAL_TIM_ENABLE(htim);
1145 }
1146
1147 /* Return function status */
1148 return HAL_OK;
1149 }
1150
1151 /**
1152 * @brief Stops the PWM signal generation on the complementary output.
1153 * @param htim TIM handle
1154 * @param Channel TIM Channel to be disabled
1155 * This parameter can be one of the following values:
1156 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1157 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1158 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1159 * @retval HAL status
1160 */
HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1161 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1162 {
1163 /* Check the parameters */
1164 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1165
1166 /* Disable the complementary PWM output */
1167 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1168
1169 /* Disable the Main Output */
1170 __HAL_TIM_MOE_DISABLE(htim);
1171
1172 /* Disable the Peripheral */
1173 __HAL_TIM_DISABLE(htim);
1174
1175 /* Set the TIM complementary channel state */
1176 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1177
1178 /* Return function status */
1179 return HAL_OK;
1180 }
1181
1182 /**
1183 * @brief Starts the PWM signal generation in interrupt mode on the
1184 * complementary output.
1185 * @param htim TIM handle
1186 * @param Channel TIM Channel to be disabled
1187 * This parameter can be one of the following values:
1188 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1189 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1190 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1191 * @retval HAL status
1192 */
HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1193 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1194 {
1195 HAL_StatusTypeDef status = HAL_OK;
1196 uint32_t tmpsmcr;
1197
1198 /* Check the parameters */
1199 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1200
1201 /* Check the TIM complementary channel state */
1202 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1203 {
1204 return HAL_ERROR;
1205 }
1206
1207 /* Set the TIM complementary channel state */
1208 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1209
1210 switch (Channel)
1211 {
1212 case TIM_CHANNEL_1:
1213 {
1214 /* Enable the TIM Capture/Compare 1 interrupt */
1215 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1216 break;
1217 }
1218
1219 case TIM_CHANNEL_2:
1220 {
1221 /* Enable the TIM Capture/Compare 2 interrupt */
1222 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1223 break;
1224 }
1225
1226 case TIM_CHANNEL_3:
1227 {
1228 /* Enable the TIM Capture/Compare 3 interrupt */
1229 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1230 break;
1231 }
1232
1233 default:
1234 status = HAL_ERROR;
1235 break;
1236 }
1237
1238 if (status == HAL_OK)
1239 {
1240 /* Enable the TIM Break interrupt */
1241 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1242
1243 /* Enable the complementary PWM output */
1244 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1245
1246 /* Enable the Main Output */
1247 __HAL_TIM_MOE_ENABLE(htim);
1248
1249 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1250 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1251 {
1252 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1253 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1254 {
1255 __HAL_TIM_ENABLE(htim);
1256 }
1257 }
1258 else
1259 {
1260 __HAL_TIM_ENABLE(htim);
1261 }
1262 }
1263
1264 /* Return function status */
1265 return status;
1266 }
1267
1268 /**
1269 * @brief Stops the PWM signal generation in interrupt mode on the
1270 * complementary output.
1271 * @param htim TIM handle
1272 * @param Channel TIM Channel to be disabled
1273 * This parameter can be one of the following values:
1274 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1275 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1276 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1277 * @retval HAL status
1278 */
HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1279 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1280 {
1281 HAL_StatusTypeDef status = HAL_OK;
1282 uint32_t tmpccer;
1283
1284 /* Check the parameters */
1285 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1286
1287 switch (Channel)
1288 {
1289 case TIM_CHANNEL_1:
1290 {
1291 /* Disable the TIM Capture/Compare 1 interrupt */
1292 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1293 break;
1294 }
1295
1296 case TIM_CHANNEL_2:
1297 {
1298 /* Disable the TIM Capture/Compare 2 interrupt */
1299 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1300 break;
1301 }
1302
1303 case TIM_CHANNEL_3:
1304 {
1305 /* Disable the TIM Capture/Compare 3 interrupt */
1306 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1307 break;
1308 }
1309
1310 default:
1311 status = HAL_ERROR;
1312 break;
1313 }
1314
1315 if (status == HAL_OK)
1316 {
1317 /* Disable the complementary PWM output */
1318 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1319
1320 /* Disable the TIM Break interrupt (only if no more channel is active) */
1321 tmpccer = htim->Instance->CCER;
1322 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
1323 {
1324 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
1325 }
1326
1327 /* Disable the Main Output */
1328 __HAL_TIM_MOE_DISABLE(htim);
1329
1330 /* Disable the Peripheral */
1331 __HAL_TIM_DISABLE(htim);
1332
1333 /* Set the TIM complementary channel state */
1334 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1335 }
1336
1337 /* Return function status */
1338 return status;
1339 }
1340
1341 /**
1342 * @brief Starts the TIM PWM signal generation in DMA mode on the
1343 * complementary output
1344 * @param htim TIM handle
1345 * @param Channel TIM Channel to be enabled
1346 * This parameter can be one of the following values:
1347 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1348 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1349 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1350 * @param pData The source Buffer address.
1351 * @param Length The length of data to be transferred from memory to TIM peripheral
1352 * @retval HAL status
1353 */
HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1354 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1355 uint16_t Length)
1356 {
1357 HAL_StatusTypeDef status = HAL_OK;
1358 uint32_t tmpsmcr;
1359
1360 /* Check the parameters */
1361 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1362
1363 /* Set the TIM complementary channel state */
1364 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1365 {
1366 return HAL_BUSY;
1367 }
1368 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1369 {
1370 if ((pData == NULL) || (Length == 0U))
1371 {
1372 return HAL_ERROR;
1373 }
1374 else
1375 {
1376 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1377 }
1378 }
1379 else
1380 {
1381 return HAL_ERROR;
1382 }
1383
1384 switch (Channel)
1385 {
1386 case TIM_CHANNEL_1:
1387 {
1388 /* Set the DMA compare callbacks */
1389 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1390 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1391
1392 /* Set the DMA error callback */
1393 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
1394
1395 /* Enable the DMA channel */
1396 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1397 Length) != HAL_OK)
1398 {
1399 /* Return error status */
1400 return HAL_ERROR;
1401 }
1402 /* Enable the TIM Capture/Compare 1 DMA request */
1403 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1404 break;
1405 }
1406
1407 case TIM_CHANNEL_2:
1408 {
1409 /* Set the DMA compare callbacks */
1410 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1411 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1412
1413 /* Set the DMA error callback */
1414 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
1415
1416 /* Enable the DMA channel */
1417 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1418 Length) != HAL_OK)
1419 {
1420 /* Return error status */
1421 return HAL_ERROR;
1422 }
1423 /* Enable the TIM Capture/Compare 2 DMA request */
1424 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1425 break;
1426 }
1427
1428 case TIM_CHANNEL_3:
1429 {
1430 /* Set the DMA compare callbacks */
1431 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1432 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1433
1434 /* Set the DMA error callback */
1435 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
1436
1437 /* Enable the DMA channel */
1438 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1439 Length) != HAL_OK)
1440 {
1441 /* Return error status */
1442 return HAL_ERROR;
1443 }
1444 /* Enable the TIM Capture/Compare 3 DMA request */
1445 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1446 break;
1447 }
1448
1449 default:
1450 status = HAL_ERROR;
1451 break;
1452 }
1453
1454 if (status == HAL_OK)
1455 {
1456 /* Enable the complementary PWM output */
1457 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1458
1459 /* Enable the Main Output */
1460 __HAL_TIM_MOE_ENABLE(htim);
1461
1462 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1463 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1464 {
1465 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1466 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1467 {
1468 __HAL_TIM_ENABLE(htim);
1469 }
1470 }
1471 else
1472 {
1473 __HAL_TIM_ENABLE(htim);
1474 }
1475 }
1476
1477 /* Return function status */
1478 return status;
1479 }
1480
1481 /**
1482 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
1483 * output
1484 * @param htim TIM handle
1485 * @param Channel TIM Channel to be disabled
1486 * This parameter can be one of the following values:
1487 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1488 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1489 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1490 * @retval HAL status
1491 */
HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1492 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1493 {
1494 HAL_StatusTypeDef status = HAL_OK;
1495
1496 /* Check the parameters */
1497 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1498
1499 switch (Channel)
1500 {
1501 case TIM_CHANNEL_1:
1502 {
1503 /* Disable the TIM Capture/Compare 1 DMA request */
1504 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1505 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1506 break;
1507 }
1508
1509 case TIM_CHANNEL_2:
1510 {
1511 /* Disable the TIM Capture/Compare 2 DMA request */
1512 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1513 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1514 break;
1515 }
1516
1517 case TIM_CHANNEL_3:
1518 {
1519 /* Disable the TIM Capture/Compare 3 DMA request */
1520 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1521 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1522 break;
1523 }
1524
1525 default:
1526 status = HAL_ERROR;
1527 break;
1528 }
1529
1530 if (status == HAL_OK)
1531 {
1532 /* Disable the complementary PWM output */
1533 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1534
1535 /* Disable the Main Output */
1536 __HAL_TIM_MOE_DISABLE(htim);
1537
1538 /* Disable the Peripheral */
1539 __HAL_TIM_DISABLE(htim);
1540
1541 /* Set the TIM complementary channel state */
1542 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1543 }
1544
1545 /* Return function status */
1546 return status;
1547 }
1548
1549 /**
1550 * @}
1551 */
1552
1553 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
1554 * @brief Timer Complementary One Pulse functions
1555 *
1556 @verbatim
1557 ==============================================================================
1558 ##### Timer Complementary One Pulse functions #####
1559 ==============================================================================
1560 [..]
1561 This section provides functions allowing to:
1562 (+) Start the Complementary One Pulse generation.
1563 (+) Stop the Complementary One Pulse.
1564 (+) Start the Complementary One Pulse and enable interrupts.
1565 (+) Stop the Complementary One Pulse and disable interrupts.
1566
1567 @endverbatim
1568 * @{
1569 */
1570
1571 /**
1572 * @brief Starts the TIM One Pulse signal generation on the complementary
1573 * output.
1574 * @note OutputChannel must match the pulse output channel chosen when calling
1575 * @ref HAL_TIM_OnePulse_ConfigChannel().
1576 * @param htim TIM One Pulse handle
1577 * @param OutputChannel pulse output channel to enable
1578 * This parameter can be one of the following values:
1579 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1580 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1581 * @retval HAL status
1582 */
HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1583 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1584 {
1585 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1586 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1587 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1588 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1589 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1590
1591 /* Check the parameters */
1592 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1593
1594 /* Check the TIM channels state */
1595 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1596 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1597 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1598 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1599 {
1600 return HAL_ERROR;
1601 }
1602
1603 /* Set the TIM channels state */
1604 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1605 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1606 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1607 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1608
1609 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1610 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1611 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1612
1613 /* Enable the Main Output */
1614 __HAL_TIM_MOE_ENABLE(htim);
1615
1616 /* Return function status */
1617 return HAL_OK;
1618 }
1619
1620 /**
1621 * @brief Stops the TIM One Pulse signal generation on the complementary
1622 * output.
1623 * @note OutputChannel must match the pulse output channel chosen when calling
1624 * @ref HAL_TIM_OnePulse_ConfigChannel().
1625 * @param htim TIM One Pulse handle
1626 * @param OutputChannel pulse output channel to disable
1627 * This parameter can be one of the following values:
1628 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1629 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1630 * @retval HAL status
1631 */
HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1632 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1633 {
1634 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1635
1636 /* Check the parameters */
1637 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1638
1639 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1640 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1641 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1642
1643 /* Disable the Main Output */
1644 __HAL_TIM_MOE_DISABLE(htim);
1645
1646 /* Disable the Peripheral */
1647 __HAL_TIM_DISABLE(htim);
1648
1649 /* Set the TIM channels state */
1650 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1651 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1652 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1653 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1654
1655 /* Return function status */
1656 return HAL_OK;
1657 }
1658
1659 /**
1660 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
1661 * complementary channel.
1662 * @note OutputChannel must match the pulse output channel chosen when calling
1663 * @ref HAL_TIM_OnePulse_ConfigChannel().
1664 * @param htim TIM One Pulse handle
1665 * @param OutputChannel pulse output channel to enable
1666 * This parameter can be one of the following values:
1667 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1668 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1669 * @retval HAL status
1670 */
HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1671 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1672 {
1673 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1674 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1675 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1676 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1677 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1678
1679 /* Check the parameters */
1680 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1681
1682 /* Check the TIM channels state */
1683 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1684 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1685 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1686 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1687 {
1688 return HAL_ERROR;
1689 }
1690
1691 /* Set the TIM channels state */
1692 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1693 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1694 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1695 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1696
1697 /* Enable the TIM Capture/Compare 1 interrupt */
1698 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1699
1700 /* Enable the TIM Capture/Compare 2 interrupt */
1701 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1702
1703 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1704 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1705 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1706
1707 /* Enable the Main Output */
1708 __HAL_TIM_MOE_ENABLE(htim);
1709
1710 /* Return function status */
1711 return HAL_OK;
1712 }
1713
1714 /**
1715 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
1716 * complementary channel.
1717 * @note OutputChannel must match the pulse output channel chosen when calling
1718 * @ref HAL_TIM_OnePulse_ConfigChannel().
1719 * @param htim TIM One Pulse handle
1720 * @param OutputChannel pulse output channel to disable
1721 * This parameter can be one of the following values:
1722 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1723 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1724 * @retval HAL status
1725 */
HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1726 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1727 {
1728 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1729
1730 /* Check the parameters */
1731 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1732
1733 /* Disable the TIM Capture/Compare 1 interrupt */
1734 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1735
1736 /* Disable the TIM Capture/Compare 2 interrupt */
1737 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1738
1739 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1740 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1741 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1742
1743 /* Disable the Main Output */
1744 __HAL_TIM_MOE_DISABLE(htim);
1745
1746 /* Disable the Peripheral */
1747 __HAL_TIM_DISABLE(htim);
1748
1749 /* Set the TIM channels state */
1750 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1751 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1752 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1753 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1754
1755 /* Return function status */
1756 return HAL_OK;
1757 }
1758
1759 /**
1760 * @}
1761 */
1762
1763 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
1764 * @brief Peripheral Control functions
1765 *
1766 @verbatim
1767 ==============================================================================
1768 ##### Peripheral Control functions #####
1769 ==============================================================================
1770 [..]
1771 This section provides functions allowing to:
1772 (+) Configure the commutation event in case of use of the Hall sensor interface.
1773 (+) Configure Output channels for OC and PWM mode.
1774
1775 (+) Configure Complementary channels, break features and dead time.
1776 (+) Configure Master synchronization.
1777 (+) Configure timer remapping capabilities.
1778 (+) Select timer input source.
1779 (+) Enable or disable channel grouping.
1780
1781 @endverbatim
1782 * @{
1783 */
1784
1785 /**
1786 * @brief Configure the TIM commutation event sequence.
1787 * @note This function is mandatory to use the commutation event in order to
1788 * update the configuration at each commutation detection on the TRGI input of the Timer,
1789 * the typical use of this feature is with the use of another Timer(interface Timer)
1790 * configured in Hall sensor interface, this interface Timer will generate the
1791 * commutation at its TRGO output (connected to Timer used in this function) each time
1792 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1793 * @param htim TIM handle
1794 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1795 * This parameter can be one of the following values:
1796 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1797 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1798 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1799 * @arg TIM_TS_ITR7: Internal trigger 7 selected
1800 * @arg TIM_TS_NONE: No trigger is needed
1801 * @param CommutationSource the Commutation Event source
1802 * This parameter can be one of the following values:
1803 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1804 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1805 * @retval HAL status
1806 */
HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1807 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1808 uint32_t CommutationSource)
1809 {
1810 /* Check the parameters */
1811 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1812 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1813
1814 __HAL_LOCK(htim);
1815
1816 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1817 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR7))
1818 {
1819 /* Select the Input trigger */
1820 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1821 htim->Instance->SMCR |= InputTrigger;
1822 }
1823
1824 /* Select the Capture Compare preload feature */
1825 htim->Instance->CR2 |= TIM_CR2_CCPC;
1826 /* Select the Commutation event source */
1827 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1828 htim->Instance->CR2 |= CommutationSource;
1829
1830 /* Disable Commutation Interrupt */
1831 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
1832
1833 /* Disable Commutation DMA request */
1834 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1835
1836 __HAL_UNLOCK(htim);
1837
1838 return HAL_OK;
1839 }
1840
1841 /**
1842 * @brief Configure the TIM commutation event sequence with interrupt.
1843 * @note This function is mandatory to use the commutation event in order to
1844 * update the configuration at each commutation detection on the TRGI input of the Timer,
1845 * the typical use of this feature is with the use of another Timer(interface Timer)
1846 * configured in Hall sensor interface, this interface Timer will generate the
1847 * commutation at its TRGO output (connected to Timer used in this function) each time
1848 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1849 * @param htim TIM handle
1850 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1851 * This parameter can be one of the following values:
1852 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1853 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1854 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1855 * @arg TIM_TS_ITR7: Internal trigger 7 selected
1856 * @arg TIM_TS_NONE: No trigger is needed
1857 * @param CommutationSource the Commutation Event source
1858 * This parameter can be one of the following values:
1859 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1860 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1861 * @retval HAL status
1862 */
HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1863 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1864 uint32_t CommutationSource)
1865 {
1866 /* Check the parameters */
1867 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1868 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1869
1870 __HAL_LOCK(htim);
1871
1872 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1873 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR7))
1874 {
1875 /* Select the Input trigger */
1876 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1877 htim->Instance->SMCR |= InputTrigger;
1878 }
1879
1880 /* Select the Capture Compare preload feature */
1881 htim->Instance->CR2 |= TIM_CR2_CCPC;
1882 /* Select the Commutation event source */
1883 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1884 htim->Instance->CR2 |= CommutationSource;
1885
1886 /* Disable Commutation DMA request */
1887 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1888
1889 /* Enable the Commutation Interrupt */
1890 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
1891
1892 __HAL_UNLOCK(htim);
1893
1894 return HAL_OK;
1895 }
1896
1897 /**
1898 * @brief Configure the TIM commutation event sequence with DMA.
1899 * @note This function is mandatory to use the commutation event in order to
1900 * update the configuration at each commutation detection on the TRGI input of the Timer,
1901 * the typical use of this feature is with the use of another Timer(interface Timer)
1902 * configured in Hall sensor interface, this interface Timer will generate the
1903 * commutation at its TRGO output (connected to Timer used in this function) each time
1904 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1905 * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
1906 * @param htim TIM handle
1907 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1908 * This parameter can be one of the following values:
1909 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1910 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1911 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1912 * @arg TIM_TS_ITR7: Internal trigger 7 selected
1913 * @arg TIM_TS_NONE: No trigger is needed
1914 * @param CommutationSource the Commutation Event source
1915 * This parameter can be one of the following values:
1916 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1917 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1918 * @retval HAL status
1919 */
HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1920 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1921 uint32_t CommutationSource)
1922 {
1923 /* Check the parameters */
1924 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1925 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
1926
1927 __HAL_LOCK(htim);
1928
1929 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
1930 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR7))
1931 {
1932 /* Select the Input trigger */
1933 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1934 htim->Instance->SMCR |= InputTrigger;
1935 }
1936
1937 /* Select the Capture Compare preload feature */
1938 htim->Instance->CR2 |= TIM_CR2_CCPC;
1939 /* Select the Commutation event source */
1940 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1941 htim->Instance->CR2 |= CommutationSource;
1942
1943 /* Enable the Commutation DMA Request */
1944 /* Set the DMA Commutation Callback */
1945 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
1946 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
1947 /* Set the DMA error callback */
1948 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
1949
1950 /* Disable Commutation Interrupt */
1951 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
1952
1953 /* Enable the Commutation DMA Request */
1954 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
1955
1956 __HAL_UNLOCK(htim);
1957
1958 return HAL_OK;
1959 }
1960
1961 /**
1962 * @brief Configures the TIM in master mode.
1963 * @param htim TIM handle.
1964 * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
1965 * contains the selected trigger output (TRGO) and the Master/Slave
1966 * mode.
1967 * @retval HAL status
1968 */
HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef * htim,const TIM_MasterConfigTypeDef * sMasterConfig)1969 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
1970 const TIM_MasterConfigTypeDef *sMasterConfig)
1971 {
1972 uint32_t tmpcr2;
1973 uint32_t tmpsmcr;
1974
1975 /* Check the parameters */
1976 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
1977 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
1978 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
1979
1980 /* Check input state */
1981 __HAL_LOCK(htim);
1982
1983 /* Change the handler state */
1984 htim->State = HAL_TIM_STATE_BUSY;
1985
1986 /* Get the TIMx CR2 register value */
1987 tmpcr2 = htim->Instance->CR2;
1988
1989 /* Get the TIMx SMCR register value */
1990 tmpsmcr = htim->Instance->SMCR;
1991
1992 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
1993 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
1994 {
1995 /* Check the parameters */
1996 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
1997
1998 /* Clear the MMS2 bits */
1999 tmpcr2 &= ~TIM_CR2_MMS2;
2000 /* Select the TRGO2 source*/
2001 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
2002 }
2003
2004 /* Reset the MMS Bits */
2005 tmpcr2 &= ~TIM_CR2_MMS;
2006 /* Select the TRGO source */
2007 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
2008
2009 /* Update TIMx CR2 */
2010 htim->Instance->CR2 = tmpcr2;
2011
2012 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2013 {
2014 /* Reset the MSM Bit */
2015 tmpsmcr &= ~TIM_SMCR_MSM;
2016 /* Set master mode */
2017 tmpsmcr |= sMasterConfig->MasterSlaveMode;
2018
2019 /* Update TIMx SMCR */
2020 htim->Instance->SMCR = tmpsmcr;
2021 }
2022
2023 /* Change the htim state */
2024 htim->State = HAL_TIM_STATE_READY;
2025
2026 __HAL_UNLOCK(htim);
2027
2028 return HAL_OK;
2029 }
2030
2031 /**
2032 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2033 * and the AOE(automatic output enable).
2034 * @param htim TIM handle
2035 * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
2036 * contains the BDTR Register configuration information for the TIM peripheral.
2037 * @note Interrupts can be generated when an active level is detected on the
2038 * break input, the break 2 input or the system break input. Break
2039 * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
2040 * @retval HAL status
2041 */
HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef * htim,const TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)2042 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2043 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
2044 {
2045 /* Keep this variable initialized to 0 as it is used to configure BDTR register */
2046 uint32_t tmpbdtr = 0U;
2047
2048 /* Check the parameters */
2049 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2050 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2051 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2052 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2053 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2054 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2055 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2056 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
2057 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2058 assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
2059
2060 /* Check input state */
2061 __HAL_LOCK(htim);
2062
2063 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2064 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2065
2066 /* Set the BDTR bits */
2067 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
2068 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
2069 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
2070 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
2071 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
2072 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
2073 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
2074 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
2075 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
2076
2077 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
2078 {
2079 /* Check the parameters */
2080 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
2081 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
2082 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
2083 assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
2084
2085 /* Set the BREAK2 input related BDTR bits */
2086 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
2087 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
2088 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
2089 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
2090 }
2091
2092 /* Set TIMx_BDTR */
2093 htim->Instance->BDTR = tmpbdtr;
2094
2095 __HAL_UNLOCK(htim);
2096
2097 return HAL_OK;
2098 }
2099
2100 /**
2101 * @brief Configures the break input source.
2102 * @param htim TIM handle.
2103 * @param BreakInput Break input to configure
2104 * This parameter can be one of the following values:
2105 * @arg TIM_BREAKINPUT_BRK: Timer break input
2106 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2107 * @param sBreakInputConfig Break input source configuration
2108 * @retval HAL status
2109 */
HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput,const TIMEx_BreakInputConfigTypeDef * sBreakInputConfig)2110 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
2111 uint32_t BreakInput,
2112 const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
2113 {
2114 HAL_StatusTypeDef status = HAL_OK;
2115 uint32_t tmporx;
2116 uint32_t bkin_enable_mask;
2117 uint32_t bkin_polarity_mask;
2118 uint32_t bkin_enable_bitpos;
2119 uint32_t bkin_polarity_bitpos;
2120
2121 /* Check the parameters */
2122 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2123 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2124 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
2125 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
2126 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
2127
2128 /* Check input state */
2129 __HAL_LOCK(htim);
2130
2131 switch (sBreakInputConfig->Source)
2132 {
2133 case TIM_BREAKINPUTSOURCE_BKIN:
2134 {
2135 bkin_enable_mask = TIM_AF1_BKINE;
2136 bkin_enable_bitpos = TIM_AF1_BKINE_Pos;
2137 bkin_polarity_mask = TIM_AF1_BKINP;
2138 bkin_polarity_bitpos = TIM_AF1_BKINP_Pos;
2139 break;
2140 }
2141 case TIM_BREAKINPUTSOURCE_COMP1:
2142 {
2143 bkin_enable_mask = TIM_AF1_BKCMP1E;
2144 bkin_enable_bitpos = TIM_AF1_BKCMP1E_Pos;
2145 bkin_polarity_mask = TIM_AF1_BKCMP1P;
2146 bkin_polarity_bitpos = TIM_AF1_BKCMP1P_Pos;
2147 break;
2148 }
2149 #if defined(COMP2)
2150 case TIM_BREAKINPUTSOURCE_COMP2:
2151 {
2152 bkin_enable_mask = TIM_AF1_BKCMP2E;
2153 bkin_enable_bitpos = TIM_AF1_BKCMP2E_Pos;
2154 bkin_polarity_mask = TIM_AF1_BKCMP2P;
2155 bkin_polarity_bitpos = TIM_AF1_BKCMP2P_Pos;
2156 break;
2157 }
2158 #endif /* COMP2 */
2159
2160 default:
2161 {
2162 bkin_enable_mask = 0U;
2163 bkin_polarity_mask = 0U;
2164 bkin_enable_bitpos = 0U;
2165 bkin_polarity_bitpos = 0U;
2166 break;
2167 }
2168 }
2169
2170 switch (BreakInput)
2171 {
2172 case TIM_BREAKINPUT_BRK:
2173 {
2174 /* Get the TIMx_AF1 register value */
2175 tmporx = htim->Instance->AF1;
2176
2177 /* Enable the break input */
2178 tmporx &= ~bkin_enable_mask;
2179 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2180
2181 /* Set the break input polarity */
2182 tmporx &= ~bkin_polarity_mask;
2183 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2184
2185 /* Set TIMx_AF1 */
2186 htim->Instance->AF1 = tmporx;
2187 break;
2188 }
2189 case TIM_BREAKINPUT_BRK2:
2190 {
2191 /* Get the TIMx_AF2 register value */
2192 tmporx = htim->Instance->AF2;
2193
2194 /* Enable the break input */
2195 tmporx &= ~bkin_enable_mask;
2196 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2197
2198 /* Set the break input polarity */
2199 tmporx &= ~bkin_polarity_mask;
2200 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2201
2202 /* Set TIMx_AF2 */
2203 htim->Instance->AF2 = tmporx;
2204 break;
2205 }
2206 default:
2207 status = HAL_ERROR;
2208 break;
2209 }
2210
2211 __HAL_UNLOCK(htim);
2212
2213 return status;
2214 }
2215
2216 /**
2217 * @brief Configures the TIMx Remapping input capabilities.
2218 * @param htim TIM handle.
2219 * @param Remap specifies the TIM remapping source.
2220 * For TIM1, the parameter can take one of the following values:
2221 * @arg TIM_TIM1_ETR_GPIO: TIM1 ETR is is connected to GPIO
2222 * @arg TIM_TIM1_ETR_COMP1: TIM1 ETR is connected to COMP1 output
2223 * @arg TIM_TIM1_ETR_COMP2: TIM1 ETR is connected to COMP2 output (*)
2224 * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1 ETR is connected to ADC1 AWD1
2225 * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1 ETR is connected to ADC1 AWD2
2226 * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1 ETR is connected to ADC1 AWD3
2227 *
2228 * For TIM2, the parameter can take one of the following values:
2229 * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO
2230 * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output
2231 * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output (*)
2232 * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
2233 * @arg TIM_TIM2_ETR_MCO: TIM2_ETR is connected to MCO
2234 * @arg TIM_TIM2_ETR_MCO2: TIM2_ETR is connected to MCO2
2235 *
2236 * For TIM3, the parameter can take one of the following values:
2237 * @arg TIM_TIM3_ETR_GPIO TIM3_ETR is connected to GPIO
2238 * @arg TIM_TIM3_ETR_COMP1 TIM3_ETR is connected to COMP1 output
2239 * @arg TIM_TIM3_ETR_COMP2 TIM3_ETR is connected to COMP2 output (*)
2240 *
2241 * (*) Value not defined in all devices.
2242 *
2243 * @retval HAL status
2244 */
HAL_TIMEx_RemapConfig(TIM_HandleTypeDef * htim,uint32_t Remap)2245 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
2246 {
2247 /* Check parameters */
2248 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2249 assert_param(IS_TIM_REMAP(Remap));
2250
2251 __HAL_LOCK(htim);
2252
2253 MODIFY_REG(htim->Instance->AF1, TIM_AF1_ETRSEL_Msk, Remap);
2254
2255 __HAL_UNLOCK(htim);
2256
2257 return HAL_OK;
2258 }
2259
2260 /**
2261 * @brief Select the timer input source
2262 * @param htim TIM handle.
2263 * @param Channel specifies the TIM Channel
2264 * This parameter can be one of the following values:
2265 * @arg TIM_CHANNEL_1: TI1 input channel
2266 * @arg TIM_CHANNEL_2: TI2 input channel
2267 * @param TISelection specifies the timer input source
2268 *
2269 * For TIM1 this parameter can be one of the following values:
2270 * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
2271 * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output
2272 * @arg TIM_TIM1_TI2_GPIO: TIM1 TI2 is connected to GPIO
2273 * @arg TIM_TIM1_TI2_COMP2: TIM1 TI2 is connected to COMP2 output (*)
2274 *
2275 * For TIM2, the parameter is one of the following values:
2276 * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO
2277 * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output
2278 * @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO
2279 * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP2 output (*)
2280 *
2281 * For TIM3, the parameter is one of the following values:
2282 * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
2283 * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output
2284 * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO
2285 * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP2 output (*)
2286 *
2287 * For TIM15, the parameter is one of the following values:
2288 * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
2289 * @arg TIM_TIM15_TI1_TIM2_CH1: TIM15 TI1 is connected to TIM2 CH1
2290 * @arg TIM_TIM15_TI1_TIM3_CH1: TIM15 TI1 is connected to TIM3 CH1
2291 * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
2292 * @arg TIM_TIM15_TI2_TIM2_CH2: TIM15 TI2 is connected to TIM2 CH2
2293 * @arg TIM_TIM15_TI2_TIM3_CH2: TIM15 TI2 is connected to TIM3 CH2
2294 *
2295 * For TIM16, the parameter can have the following values:
2296 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
2297 * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
2298 * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
2299 * @arg TIM_TIM16_TI1_RTC_WAKEUP: TIM16 TI1 is connected to TRC wakeup interrupt
2300 * @arg TIM_TIM16_TI1_MCO2: TIM16 TI1 is connected to MCO2
2301 *
2302 * (*) Value not defined in all devices.
2303 *
2304 * @retval HAL status
2305 */
HAL_TIMEx_TISelection(TIM_HandleTypeDef * htim,uint32_t TISelection,uint32_t Channel)2306 HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
2307 {
2308 HAL_StatusTypeDef status = HAL_OK;
2309
2310 /* Check parameters */
2311 assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
2312 assert_param(IS_TIM_TISEL(TISelection));
2313
2314 __HAL_LOCK(htim);
2315
2316 switch (Channel)
2317 {
2318 case TIM_CHANNEL_1:
2319 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
2320 break;
2321 case TIM_CHANNEL_2:
2322 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
2323 break;
2324 default:
2325 status = HAL_ERROR;
2326 break;
2327 }
2328
2329 __HAL_UNLOCK(htim);
2330
2331 return status;
2332 }
2333
2334 /**
2335 * @brief Group channel 5 and channel 1, 2 or 3
2336 * @param htim TIM handle.
2337 * @param Channels specifies the reference signal(s) the OC5REF is combined with.
2338 * This parameter can be any combination of the following values:
2339 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
2340 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
2341 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
2342 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
2343 * @retval HAL status
2344 */
HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef * htim,uint32_t Channels)2345 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
2346 {
2347 /* Check parameters */
2348 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
2349 assert_param(IS_TIM_GROUPCH5(Channels));
2350
2351 /* Process Locked */
2352 __HAL_LOCK(htim);
2353
2354 htim->State = HAL_TIM_STATE_BUSY;
2355
2356 /* Clear GC5Cx bit fields */
2357 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
2358
2359 /* Set GC5Cx bit fields */
2360 htim->Instance->CCR5 |= Channels;
2361
2362 /* Change the htim state */
2363 htim->State = HAL_TIM_STATE_READY;
2364
2365 __HAL_UNLOCK(htim);
2366
2367 return HAL_OK;
2368 }
2369
2370 /**
2371 * @brief Disarm the designated break input (when it operates in bidirectional mode).
2372 * @param htim TIM handle.
2373 * @param BreakInput Break input to disarm
2374 * This parameter can be one of the following values:
2375 * @arg TIM_BREAKINPUT_BRK: Timer break input
2376 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2377 * @note The break input can be disarmed only when it is configured in
2378 * bidirectional mode and when when MOE is reset.
2379 * @note Purpose is to be able to have the input voltage back to high-state,
2380 * whatever the time constant on the output .
2381 * @retval HAL status
2382 */
HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput)2383 HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
2384 {
2385 HAL_StatusTypeDef status = HAL_OK;
2386 uint32_t tmpbdtr;
2387
2388 /* Check the parameters */
2389 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2390 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2391
2392 switch (BreakInput)
2393 {
2394 case TIM_BREAKINPUT_BRK:
2395 {
2396 /* Check initial conditions */
2397 tmpbdtr = READ_REG(htim->Instance->BDTR);
2398 if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
2399 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2400 {
2401 /* Break input BRK is disarmed */
2402 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
2403 }
2404 break;
2405 }
2406 case TIM_BREAKINPUT_BRK2:
2407 {
2408 /* Check initial conditions */
2409 tmpbdtr = READ_REG(htim->Instance->BDTR);
2410 if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
2411 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2412 {
2413 /* Break input BRK is disarmed */
2414 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
2415 }
2416 break;
2417 }
2418 default:
2419 status = HAL_ERROR;
2420 break;
2421 }
2422
2423 return status;
2424 }
2425
2426 /**
2427 * @brief Arm the designated break input (when it operates in bidirectional mode).
2428 * @param htim TIM handle.
2429 * @param BreakInput Break input to arm
2430 * This parameter can be one of the following values:
2431 * @arg TIM_BREAKINPUT_BRK: Timer break input
2432 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2433 * @note Arming is possible at anytime, even if fault is present.
2434 * @note Break input is automatically armed as soon as MOE bit is set.
2435 * @retval HAL status
2436 */
HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef * htim,uint32_t BreakInput)2437 HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput)
2438 {
2439 HAL_StatusTypeDef status = HAL_OK;
2440 uint32_t tickstart;
2441
2442 /* Check the parameters */
2443 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2444 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2445
2446 switch (BreakInput)
2447 {
2448 case TIM_BREAKINPUT_BRK:
2449 {
2450 /* Check initial conditions */
2451 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
2452 {
2453 /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2454 /* Init tickstart for timeout management */
2455 tickstart = HAL_GetTick();
2456 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2457 {
2458 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2459 {
2460 /* New check to avoid false timeout detection in case of preemption */
2461 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2462 {
2463 return HAL_TIMEOUT;
2464 }
2465 }
2466 }
2467 }
2468 break;
2469 }
2470
2471 case TIM_BREAKINPUT_BRK2:
2472 {
2473 /* Check initial conditions */
2474 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
2475 {
2476 /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2477 /* Init tickstart for timeout management */
2478 tickstart = HAL_GetTick();
2479 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2480 {
2481 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2482 {
2483 /* New check to avoid false timeout detection in case of preemption */
2484 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2485 {
2486 return HAL_TIMEOUT;
2487 }
2488 }
2489 }
2490 }
2491 break;
2492 }
2493 default:
2494 status = HAL_ERROR;
2495 break;
2496 }
2497
2498 return status;
2499 }
2500
2501 /**
2502 * @}
2503 */
2504
2505 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
2506 * @brief Extended Callbacks functions
2507 *
2508 @verbatim
2509 ==============================================================================
2510 ##### Extended Callbacks functions #####
2511 ==============================================================================
2512 [..]
2513 This section provides Extended TIM callback functions:
2514 (+) Timer Commutation callback
2515 (+) Timer Break callback
2516
2517 @endverbatim
2518 * @{
2519 */
2520
2521 /**
2522 * @brief Commutation callback in non-blocking mode
2523 * @param htim TIM handle
2524 * @retval None
2525 */
HAL_TIMEx_CommutCallback(TIM_HandleTypeDef * htim)2526 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
2527 {
2528 /* Prevent unused argument(s) compilation warning */
2529 UNUSED(htim);
2530
2531 /* NOTE : This function should not be modified, when the callback is needed,
2532 the HAL_TIMEx_CommutCallback could be implemented in the user file
2533 */
2534 }
2535 /**
2536 * @brief Commutation half complete callback in non-blocking mode
2537 * @param htim TIM handle
2538 * @retval None
2539 */
HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef * htim)2540 __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
2541 {
2542 /* Prevent unused argument(s) compilation warning */
2543 UNUSED(htim);
2544
2545 /* NOTE : This function should not be modified, when the callback is needed,
2546 the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
2547 */
2548 }
2549
2550 /**
2551 * @brief Break detection callback in non-blocking mode
2552 * @param htim TIM handle
2553 * @retval None
2554 */
HAL_TIMEx_BreakCallback(TIM_HandleTypeDef * htim)2555 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
2556 {
2557 /* Prevent unused argument(s) compilation warning */
2558 UNUSED(htim);
2559
2560 /* NOTE : This function should not be modified, when the callback is needed,
2561 the HAL_TIMEx_BreakCallback could be implemented in the user file
2562 */
2563 }
2564
2565 /**
2566 * @brief Break2 detection callback in non blocking mode
2567 * @param htim: TIM handle
2568 * @retval None
2569 */
HAL_TIMEx_Break2Callback(TIM_HandleTypeDef * htim)2570 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
2571 {
2572 /* Prevent unused argument(s) compilation warning */
2573 UNUSED(htim);
2574
2575 /* NOTE : This function Should not be modified, when the callback is needed,
2576 the HAL_TIMEx_Break2Callback could be implemented in the user file
2577 */
2578 }
2579 /**
2580 * @}
2581 */
2582
2583 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
2584 * @brief Extended Peripheral State functions
2585 *
2586 @verbatim
2587 ==============================================================================
2588 ##### Extended Peripheral State functions #####
2589 ==============================================================================
2590 [..]
2591 This subsection permits to get in run-time the status of the peripheral
2592 and the data flow.
2593
2594 @endverbatim
2595 * @{
2596 */
2597
2598 /**
2599 * @brief Return the TIM Hall Sensor interface handle state.
2600 * @param htim TIM Hall Sensor handle
2601 * @retval HAL state
2602 */
HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef * htim)2603 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
2604 {
2605 return htim->State;
2606 }
2607
2608 /**
2609 * @brief Return actual state of the TIM complementary channel.
2610 * @param htim TIM handle
2611 * @param ChannelN TIM Complementary channel
2612 * This parameter can be one of the following values:
2613 * @arg TIM_CHANNEL_1: TIM Channel 1
2614 * @arg TIM_CHANNEL_2: TIM Channel 2
2615 * @arg TIM_CHANNEL_3: TIM Channel 3
2616 * @retval TIM Complementary channel state
2617 */
HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef * htim,uint32_t ChannelN)2618 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN)
2619 {
2620 HAL_TIM_ChannelStateTypeDef channel_state;
2621
2622 /* Check the parameters */
2623 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
2624
2625 channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
2626
2627 return channel_state;
2628 }
2629 /**
2630 * @}
2631 */
2632
2633 /**
2634 * @}
2635 */
2636
2637 /* Private functions ---------------------------------------------------------*/
2638 /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
2639 * @{
2640 */
2641
2642 /**
2643 * @brief TIM DMA Commutation callback.
2644 * @param hdma pointer to DMA handle.
2645 * @retval None
2646 */
TIMEx_DMACommutationCplt(DMA_HandleTypeDef * hdma)2647 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
2648 {
2649 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2650
2651 /* Change the htim state */
2652 htim->State = HAL_TIM_STATE_READY;
2653
2654 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2655 htim->CommutationCallback(htim);
2656 #else
2657 HAL_TIMEx_CommutCallback(htim);
2658 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2659 }
2660
2661 /**
2662 * @brief TIM DMA Commutation half complete callback.
2663 * @param hdma pointer to DMA handle.
2664 * @retval None
2665 */
TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef * hdma)2666 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
2667 {
2668 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2669
2670 /* Change the htim state */
2671 htim->State = HAL_TIM_STATE_READY;
2672
2673 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2674 htim->CommutationHalfCpltCallback(htim);
2675 #else
2676 HAL_TIMEx_CommutHalfCpltCallback(htim);
2677 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2678 }
2679
2680
2681 /**
2682 * @brief TIM DMA Delay Pulse complete callback (complementary channel).
2683 * @param hdma pointer to DMA handle.
2684 * @retval None
2685 */
TIM_DMADelayPulseNCplt(DMA_HandleTypeDef * hdma)2686 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
2687 {
2688 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2689
2690 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
2691 {
2692 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2693
2694 if (hdma->Init.Mode == DMA_NORMAL)
2695 {
2696 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2697 }
2698 }
2699 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
2700 {
2701 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2702
2703 if (hdma->Init.Mode == DMA_NORMAL)
2704 {
2705 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2706 }
2707 }
2708 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
2709 {
2710 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2711
2712 if (hdma->Init.Mode == DMA_NORMAL)
2713 {
2714 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
2715 }
2716 }
2717 else
2718 {
2719 /* nothing to do */
2720 }
2721
2722 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2723 htim->PWM_PulseFinishedCallback(htim);
2724 #else
2725 HAL_TIM_PWM_PulseFinishedCallback(htim);
2726 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2727
2728 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2729 }
2730
2731 /**
2732 * @brief TIM DMA error callback (complementary channel)
2733 * @param hdma pointer to DMA handle.
2734 * @retval None
2735 */
TIM_DMAErrorCCxN(DMA_HandleTypeDef * hdma)2736 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
2737 {
2738 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2739
2740 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
2741 {
2742 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2743 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2744 }
2745 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
2746 {
2747 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2748 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2749 }
2750 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
2751 {
2752 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2753 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
2754 }
2755 else
2756 {
2757 /* nothing to do */
2758 }
2759
2760 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2761 htim->ErrorCallback(htim);
2762 #else
2763 HAL_TIM_ErrorCallback(htim);
2764 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2765
2766 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2767 }
2768
2769 /**
2770 * @brief Enables or disables the TIM Capture Compare Channel xN.
2771 * @param TIMx to select the TIM peripheral
2772 * @param Channel specifies the TIM Channel
2773 * This parameter can be one of the following values:
2774 * @arg TIM_CHANNEL_1: TIM Channel 1
2775 * @arg TIM_CHANNEL_2: TIM Channel 2
2776 * @arg TIM_CHANNEL_3: TIM Channel 3
2777 * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
2778 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
2779 * @retval None
2780 */
TIM_CCxNChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelNState)2781 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
2782 {
2783 uint32_t tmp;
2784
2785 tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
2786
2787 /* Reset the CCxNE Bit */
2788 TIMx->CCER &= ~tmp;
2789
2790 /* Set or reset the CCxNE Bit */
2791 TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
2792 }
2793 /**
2794 * @}
2795 */
2796
2797 #endif /* HAL_TIM_MODULE_ENABLED */
2798 /**
2799 * @}
2800 */
2801
2802 /**
2803 * @}
2804 */
2805
