1 /**
2 ******************************************************************************
3 * @file stm32u0xx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @brief Extended PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller extension peripheral :
8 * + Power Supply Control Functions
9 * + Low Power Control Functions
10 * + Voltage Monitoring Functions
11 * + Memories Retention Functions
12 * + I/O Pull-Up Pull-Down Configuration Functions
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2023 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### How to use this driver #####
28 ==============================================================================
29 [..]
30 (#) Call HAL_PWREx_ControlVoltageScaling() and HAL_PWREx_GetVoltageRange() to
31 set / get the voltage scaling range.
32 (+) Voltage scaling can be one of the following values :
33 (++) voltage output scale 1 : 1V2
34 => Used when system clock frequency is up to 160 MHz
35 (++) voltage output scale 2 : 1V1
36 => Used when system clock frequency is up to 100 MHz
37
38 (#) Call HAL_PWREx_EnterSTOP1Mode() function to enter the whole system to
39 Stop 1 mode. Wake-up from Stop 1 mode could be following to an event or
40 an interrupt according to low power mode intrinsic request called
41 (__WFI() or __WFE()). (Regulator state on U0 devices is managed
42 internally but regulator parameter is kept for product compatibility).
43
44 (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the whole system to
45 Stop 2 mode. Wake-up from Stop 2 mode could be following to an event or
46 an interrupt according to low power mode intrinsic request called
47 (__WFI() or __WFE()). (Regulator state on U0 devices is managed
48 internally but regulator parameter is kept for product compatibility).
49
50 (#) Call HAL_PWREx_EnableBatteryCharging() and
51 HAL_PWREx_DisableBatteryCharging() to enable / disable the battery
52 charging capability when VDD alimentation is available.
53
54 (#) Call HAL_PWREx_ConfigPVM() after setting parameters to be configured
55 (event mode and PVD type) in order to set up the Peripheral Voltage use
56 HAL_PWREx_EnablePVM1(),HAL_PWREx_EnablePVM3() and HAL_PWREx_EnablePVM4()
57 functions and use HAL_PWREx_DisablePVM1(),HAL_PWREx_EnablePVM3()
58 and HAL_PWREx_EnablePVM4() to stop the PVM VDDx monitoring.
59 (+) PVM monitored voltages are :
60 (++) VDDUSB versus 1V2
61 (++) VDDADC versus 1V62
62 (++) VDDDAC versus 2V2
63
64 (#) Call HAL_PWREx_PVD_PVM_IRQHandler() function to handle the PWR PVD and
65 PVM interrupt request.
66
67 (#) Call HAL_PWREx_EnablePullUpPullDownConfig() and
68 HAL_PWREx_DisablePullUpPullDownConfig() to I/O enable / disable pull-up
69 and pull-down configuration.
70
71 (#) Call HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() to
72 apply respectively pull-up and pull-down to selected I/O.
73 Call HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() to
74 disable applied respectively pull-up and pull-down to selected I/O.
75
76 @endverbatim
77 ******************************************************************************
78 */
79
80 /* Includes ------------------------------------------------------------------*/
81 #include "stm32u0xx_hal.h"
82
83 /** @addtogroup STM32U0xx_HAL_Driver
84 * @{
85 */
86
87 /** @defgroup PWREx PWREx
88 * @brief PWR Extended HAL module driver
89 * @{
90 */
91
92 #ifdef HAL_PWR_MODULE_ENABLED
93
94 /* Private typedef -----------------------------------------------------------*/
95 /* Private define ------------------------------------------------------------*/
96
97 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
98 * @{
99 */
100 #if defined (GPIOE)
101 /* PORTE pins mask */
102 #define PWR_PORTE_AVAILABLE_PINS 0x00000388U /* PE3, PE7..PE9 */
103 #endif /* GPIOE */
104 #if defined (PWR_PDCRD_PD0)
105 #define PWR_PORTD_AVAILABLE_PINS 0x00003F7FU /* PD0..PD6, PD8..PD13 */
106 #else
107 #define PWR_PORTD_AVAILABLE_PINS 0x00000004U /* PD2 */
108 #endif /* PWR_PDCRD_PD0 */
109 /* PORTF pins mask */
110 #define PWR_PORTF_AVAILABLE_PINS 0x0000000FU /* PF0..PF3 */
111
112 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
113 * @{
114 */
115 #define PVM_MODE_IT 0x00010000U /*!< Mask for interruption yielded by PVM threshold crossing */
116 #define PVM_MODE_EVT 0x00020000U /*!< Mask for event yielded by PVM threshold crossing */
117 #define PVM_RISING_EDGE 0x00000001U /*!< Mask for rising edge set as PVM trigger */
118 #define PVM_FALLING_EDGE 0x00000002U /*!< Mask for falling edge set as PVM trigger */
119 /**
120 * @}
121 */
122
123 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
124 * @{
125 */
126 #define PWR_FLAG_SETTING_DELAY_US 50UL /*!< Time out value for REGLPF and VOSF flags setting */
127 /**
128 * @}
129 */
130
131 /**
132 * @}
133 */
134
135 /* Private macro -------------------------------------------------------------*/
136 /* Private variables ---------------------------------------------------------*/
137 /* Private function prototypes -----------------------------------------------*/
138 /* Exported functions --------------------------------------------------------*/
139
140 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
141 * @{
142 */
143
144 /** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
145 * @brief Power supply control functions
146 *
147 @verbatim
148 ===============================================================================
149 ##### Power supply control functions #####
150 ===============================================================================
151 [..]
152 This section provides functions allowing to control power supply.
153
154 [..]
155 (+) When exiting the Stop or Standby modes, the regulator is the same than
156 when entering low power modes. The voltage range is the Range 2.
157
158 (+) Both regulators can provide four different voltages (voltage scaling)
159 and can operate in Stop modes.
160 Voltage scaling ranges can be one of the following values :
161 (++) voltage output scale 1 : 1V2
162 => Used when system clock frequency is up to 160 MHz
163 (++) voltage output scale 2 : 1V1
164 => Used when system clock frequency is up to 100 MHz
165
166 @endverbatim
167 * @{
168 */
169
170 /**
171 * @brief Configure the main internal regulator output voltage.
172 * @param VoltageScaling specifies the regulator output voltage to achieve
173 * a tradeoff between performance and power consumption.
174 * This parameter can be one of the following values:
175
176 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
177 * typical output voltage at 1.2 V,
178 * system frequency up to 80 MHz.
179 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
180 * typical output voltage at 1.0 V,
181 * system frequency up to 26 MHz.
182 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
183 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
184 * When moving from Range 2 to Range 1, the system frequency can be increased to
185 * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. For
186 * some devices, the system frequency can be increased up to 120 MHz.
187 * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be
188 * cleared before returning the status. If the flag is not cleared within
189 * 50 microseconds, HAL_TIMEOUT status is reported.
190 * @retval HAL Status
191 */
HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)192 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
193 {
194 uint32_t wait_loop_index;
195 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
196
197 /* If Set Range 1 */
198 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
199 {
200 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
201 {
202 /* Set Range 1 */
203 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
204 /* Wait until VOSF is cleared */
205 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
206 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
207 {
208 wait_loop_index--;
209 }
210 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
211 {
212 return HAL_TIMEOUT;
213 }
214 }
215 }
216 else
217 {
218 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
219 {
220 /* Set Range 2 */
221 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
222 /* No need to wait for VOSF to be cleared for this transition */
223 }
224 }
225 return HAL_OK;
226 }
227
228 /**
229 * @brief Return Voltage Scaling Range.
230 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2)
231 *
232 */
HAL_PWREx_GetVoltageRange(void)233 uint32_t HAL_PWREx_GetVoltageRange(void)
234 {
235 return (PWR->CR1 & PWR_CR1_VOS);
236 }
237
238 /**
239 * @}
240 */
241
242 /** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
243 * @brief Low power control functions
244 *
245 @verbatim
246 ===============================================================================
247 ##### Low power control functions #####
248 ===============================================================================
249 [..]
250 This section provides functions allowing to control low power modes.
251
252 *** Low Power modes configuration ***
253 =====================================
254 [..]
255 This section presents 3 principles low power modes :
256
257 (+) Stop 1 mode : Cortex-M4 is stopped, clocks are stopped and the
258 regulator is in low power mode. Only autonomous
259 peripherals can operate in this mode.
260
261 (+) Stop 2 mode : Cortex-M4 is stopped, clocks are stopped and the
262 regulator is in low power mode. No peripheral can
263 operate in this mode. Only RAMs content is preserved.
264
265 (+) Shutdown mode : All PWR domains enter Shutdown mode and the VCORE
266 supply regulator is powered off. The SRAMs and
267 register contents are lost except for registers in the
268 Backup domain.
269
270 *** Stop 1 mode ***
271 ===================
272 [..]
273 The Stop 1 mode is based on the Cortex-M4 Deepsleep mode combined with
274 peripheral clock gating. In Stop 1 mode, all clocks in the VCORE domain
275 are stopped.
276 The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
277 Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or
278 MSIK for transferring data. All SRAMs and register contents are preserved,
279 but the SRAMs can be totally or partially switched off to further reduce
280 consumption.
281 The BOR is always available in Stop 1 mode.
282
283 (+) Entry:
284 The Stop 1 mode is entered by using the HAL_PWREx_EnterSTOP1Mode()
285 function.
286
287 (++) PWR_STOPENTRY_WFI: enter Stop 1 mode with WFI instruction.
288 (++) PWR_STOPENTRY_WFE: enter Stop 1 mode with WFE instruction.
289
290 (+) Exit:
291 Any EXTI line configured in interrupt mode (the corresponding EXTI
292 interrupt vector must be enabled in the NVIC). The interrupt source
293 can be external interrupts or peripherals with wakeup capability.
294 Any peripheral interrupt occurring when the AHB/APB clocks are present
295 due to an autonomous peripheral clock request (the peripheral vector
296 must be enabled in the NVIC)
297 Any EXTI line configured in event mode.
298
299 *** Stop 2 mode ***
300 ===================
301 [..]
302 The Stop 2 mode is based on the Cortex-M4 Deepsleep mode combined with
303 peripheral clock gating. In Stop 2 mode, all clocks in the VCORE domain
304 are stopped.
305 The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
306 All SRAMs and register contents are preserved, but the SRAMs can be
307 totally or partially switched off to further reduce consumption.
308 The BOR is always available in Stop 2 mode.
309
310 (+) Entry:
311 The Stop 2 mode is entered by using the HAL_PWREx_EnterSTOP2Mode()
312 function.
313
314 (++) PWR_STOPENTRY_WFI: enter Stop 2 mode with WFI instruction.
315 (++) PWR_STOPENTRY_WFE: enter Stop 23 mode with WFE instruction.
316
317 (+) Exit:
318 WKUPx pin edge, RTC or TAMP event, external Reset in NRST pin, IWDG
319 Reset, BOR reset.
320
321 *** Shutdown mode ***
322 ====================
323 [..]
324 The lowest power consumption is reached in Shutdown mode. It is based on
325 the Deepsleep mode with the voltage regulator disabled. The VCORE domain
326 is consequently powered off.
327 The PLL, HSI16, MSIS, MSIK and HSE oscillators are also switched off.
328 The SRAMs and register contents are lost except for registers in the
329 Backup domain.
330 The BOR is not available in Shutdown mode.
331 No power voltage monitoring is possible in this mode, therefore the switch
332 to Backup domain is not supported.
333
334 (+) Entry:
335 The Shutdown mode is entered by using the HAL_PWREx_EnterSHUTDOWNMode()
336 function.
337
338 (+) Exit:
339 WKUPx pin edge, RTC/TAMP event, external Reset in NRST pin.
340
341 @endverbatim
342 * @{
343 */
344
345 /**
346 * @brief Enter Low-power Run mode
347 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
348 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
349 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
350 * Additionally, the clock frequency must be reduced below 2 MHz.
351 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
352 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
353 * @retval None
354 */
HAL_PWREx_EnableLowPowerRunMode(void)355 void HAL_PWREx_EnableLowPowerRunMode(void)
356 {
357 /* Set Regulator parameter */
358 SET_BIT(PWR->CR1, PWR_CR1_LPR);
359 }
360
361 /**
362 * @brief Exit Low-power Run mode.
363 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
364 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
365 * returns HAL_TIMEOUT status). The system clock frequency can then be
366 * increased above 2 MHz.
367 * @retval HAL Status
368 */
HAL_PWREx_DisableLowPowerRunMode(void)369 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
370 {
371 uint32_t wait_loop_index;
372
373 /* Clear LPR bit */
374 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
375
376 /* Wait until REGLPF is reset */
377 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
378 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
379 {
380 wait_loop_index--;
381 }
382 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
383 {
384 return HAL_TIMEOUT;
385 }
386
387 return HAL_OK;
388 }
389
390 /**
391 * @brief Enter Stop 1 mode.
392 * @note In Stop 1 mode, only low power voltage regulator is ON.
393 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
394 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
395 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
396 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
397 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
398 * only to the peripheral requesting it.
399 * SRAM and register contents are preserved.
400 * The BOR is available.
401 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
402 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
403 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
404 * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
405 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
406 * This parameter can be one of the following values:
407 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
408 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
409 * @retval None
410 */
HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)411 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
412 {
413 /* Check the parameters */
414 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
415
416 /* Stop 1 mode with Low-Power Regulator */
417 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_0);
418
419 /* Set SLEEPDEEP bit of Cortex System Control Register */
420 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
421
422 /* Select Stop mode entry --------------------------------------------------*/
423 if (STOPEntry == PWR_STOPENTRY_WFI)
424 {
425 /* Request Wait For Interrupt */
426 __WFI();
427 }
428 else
429 {
430 /* Request Wait For Event */
431 __SEV();
432 __WFE();
433 __WFE();
434 }
435
436 /* Reset SLEEPDEEP bit of Cortex System Control Register */
437 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
438 }
439
440 /**
441 * @brief Enter Stop 2 mode.
442 * @note In Stop 2 mode, only low power voltage regulator is ON.
443 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode.
444 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI,
445 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
446 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
447 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
448 * to the peripheral requesting it.
449 * SRAM and register contents are preserved.
450 * The BOR is available.
451 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
452 * Otherwise, Stop 1 mode is entered.
453 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
454 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
455 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
456 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
457 * This parameter can be one of the following values:
458 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
459 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
460 * @retval None
461 */
HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)462 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
463 {
464 /* Check the parameter */
465 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
466 /* Clear LPR Bit */
467 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
468 /* Set Stop mode 2 */
469 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_1);
470
471 /* Set SLEEPDEEP bit of Cortex System Control Register */
472 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
473
474 /* Select Stop mode entry --------------------------------------------------*/
475 if (STOPEntry == PWR_STOPENTRY_WFI)
476 {
477 /* Request Wait For Interrupt */
478 __WFI();
479 }
480 else
481 {
482 /* Request Wait For Event */
483 __SEV();
484 __WFE();
485 __WFE();
486 }
487
488 /* Reset SLEEPDEEP bit of Cortex System Control Register */
489 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
490 }
491 /**
492 * @}
493 */
494
495 /** @defgroup PWREx_Exported_Functions_Group3 Voltage Monitoring Functions
496 * @brief Voltage monitoring functions
497 *
498 @verbatim
499 ===============================================================================
500 ##### Voltage Monitoring Functions #####
501 ===============================================================================
502 [..]
503 This section provides functions allowing voltage monitoring.
504
505 *** PVM configuration ***
506 =========================
507 [..]
508 (+) The supplies (VDDADC, VDDDAC and VDDUSB) can be independent from VDD and
509 can be monitored with three peripheral voltage monitoring (PVM).
510
511 (+) Each PVM output is connected to an EXTI line and can generate an
512 interrupt if enabled through the EXTI registers. The PVMx output
513 interrupt is generated when the independent power supply drops below
514 the PVM threshold and/or when it rises above the PVM threshold,
515 depending on EXTI line rising/falling edge configuration.
516
517 (+) Each PVM can remain active in Stop 0, Stop 1, Stop 2 modes, and the
518 PVM interrupt can wake up from the Stop mode.
519
520 *** VBAT charging ***
521 =====================
522 [..]
523 When VDD is present, it is possible to charge the external battery on VBAT
524 through an internal resistance.
525 The VBAT charging is done either through a 5 kOhm resistor or through a 1.5
526 kOhm resistor depending on the VBRS bit value in the PWR_BDCR2 register.
527 The battery charging is enabled by setting VBE bit in the PWR_BDCR2
528 register. It is automatically disabled in VBAT mode.
529
530 *** Backup domain monitoring ***
531 ================================
532 [..]
533 When the Backup domain voltage and temperature monitoring is enabled
534 (MONEN = 1 in the PWR_BDCR1 register), the Backup domain voltage and the
535 temperature are monitored.
536 If the Backup domain voltage monitoring internal tamper is enabled in the
537 TAMP peripheral (ITAMP1E = 1 in the TAMP_CR1 register), a tamper event is
538 generated when the Backup domain voltage is above the functional range.
539 In case the Backup domain voltage is below the functional range,
540 a Brownout reset is generated, erasing all device including Backup domain.
541
542 *** Backup domain battery ***
543 =============================
544 [..]
545 (+) To retain the content of the backup registers and supply the RTC
546 function when VDD is turned off, the VBAT pin can be connected to an
547 optional backup voltage supplied by a battery or by another source.
548 The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to
549 PC15 I/Os, allowing the RTC to operate even when the main power supply
550 is turned off. The backup SRAM is optionally powered by VBAT pin when
551 the BREN bit is set in the PWR Backup domain control register 1
552 (PWR_BDCR1).
553 The switch to the VBAT supply is controlled by the power down reset
554 embedded in the Reset block.
555
556 @endverbatim
557 * @{
558 */
559 #if defined(USB_DRD_FS)
560 /**
561 * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
562 * @retval None
563 */
HAL_PWREx_EnablePVM1(void)564 void HAL_PWREx_EnablePVM1(void)
565 {
566 SET_BIT(PWR->CR2, PWR_PVM_1);
567 }
568
569 /**
570 * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
571 * @retval None
572 */
HAL_PWREx_DisablePVM1(void)573 void HAL_PWREx_DisablePVM1(void)
574 {
575 CLEAR_BIT(PWR->CR2, PWR_PVM_1);
576 }
577 #endif /* USB_DRD_FS */
578 /**
579 * @brief Enable the Power Voltage Monitoring 2: VDDA versus 1.62V.
580 * @retval None
581 */
HAL_PWREx_EnablePVM3(void)582 void HAL_PWREx_EnablePVM3(void)
583 {
584 SET_BIT(PWR->CR2, PWR_PVM_3);
585 }
586
587 /**
588 * @brief Disable the Power Voltage Monitoring 2: VDDA versus 1.62V.
589 * @retval None
590 */
HAL_PWREx_DisablePVM3(void)591 void HAL_PWREx_DisablePVM3(void)
592 {
593 CLEAR_BIT(PWR->CR2, PWR_PVM_3);
594 }
595
596 /**
597 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 2.2V.
598 * @retval None
599 */
HAL_PWREx_EnablePVM4(void)600 void HAL_PWREx_EnablePVM4(void)
601 {
602 SET_BIT(PWR->CR2, PWR_PVM_4);
603 }
604
605 /**
606 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 2.2V.
607 * @retval None
608 */
HAL_PWREx_DisablePVM4(void)609 void HAL_PWREx_DisablePVM4(void)
610 {
611 CLEAR_BIT(PWR->CR2, PWR_PVM_4);
612 }
613
614 /**
615 * @brief Configure the Peripheral Voltage Monitoring (PVM).
616 * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
617 * PVM configuration information.
618 * @note The API configures a single PVM according to the information contained
619 * in the input structure. To configure several PVMs, the API must be singly
620 * called for each PVM used.
621 * @note Refer to the electrical characteristics of your device datasheet for
622 * more details about the voltage thresholds corresponding to each
623 * detection level and to each monitored supply.
624 * @retval HAL status
625 */
HAL_PWREx_ConfigPVM(const PWR_PVMTypeDef * sConfigPVM)626 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(const PWR_PVMTypeDef *sConfigPVM)
627 {
628 HAL_StatusTypeDef status = HAL_OK;
629
630 /* Check the parameters */
631 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
632 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
633
634 /* Configure EXTI 35 to 38 interrupts if so required:
635 scan through PVMType to detect which PVMx is set and
636 configure the corresponding EXTI line accordingly. */
637 switch (sConfigPVM->PVMType)
638 {
639 #if defined(USB_DRD_FS)
640 case PWR_PVM_1:
641 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
642 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
643 __HAL_PWR_PVM1_EXTI_DISABLE_IT();
644 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
645 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
646
647 /* Configure interrupt mode */
648 if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
649 {
650 __HAL_PWR_PVM1_EXTI_ENABLE_IT();
651 }
652
653 /* Configure event mode */
654 if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
655 {
656 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
657 }
658
659 /* Configure the edge */
660 if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
661 {
662 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
663 }
664
665 if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
666 {
667 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
668 }
669 break;
670 #endif /* USB_DRD_FS */
671 case PWR_PVM_3:
672 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
673 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
674 __HAL_PWR_PVM3_EXTI_DISABLE_IT();
675 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
676 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
677
678 /* Configure interrupt mode */
679 if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
680 {
681 __HAL_PWR_PVM3_EXTI_ENABLE_IT();
682 }
683
684 /* Configure event mode */
685 if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
686 {
687 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
688 }
689
690 /* Configure the edge */
691 if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
692 {
693 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
694 }
695
696 if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
697 {
698 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
699 }
700 break;
701 case PWR_PVM_4:
702 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
703 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
704 __HAL_PWR_PVM4_EXTI_DISABLE_IT();
705 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
706 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
707
708 /* Configure interrupt mode */
709 if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
710 {
711 __HAL_PWR_PVM4_EXTI_ENABLE_IT();
712 }
713
714 /* Configure event mode */
715 if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
716 {
717 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
718 }
719
720 /* Configure the edge */
721 if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
722 {
723 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
724 }
725
726 if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
727 {
728 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
729 }
730 break;
731
732 default:
733 status = HAL_ERROR;
734 break;
735 }
736
737 return status;
738 }
739
740 #if defined(USB_DRD_FS)
741 /**
742 * @brief Enable VDDUSB supply.
743 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
744 * @retval None
745 */
HAL_PWREx_EnableVddUSB(void)746 void HAL_PWREx_EnableVddUSB(void)
747 {
748 SET_BIT(PWR->CR2, PWR_CR2_USV);
749 }
750
751 /**
752 * @brief Disable VDDUSB supply.
753 * @retval None
754 */
HAL_PWREx_DisableVddUSB(void)755 void HAL_PWREx_DisableVddUSB(void)
756 {
757 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
758 }
759 #endif /* USB_DRD_FS */
760
761 /**
762 * @brief Enable battery charging.
763 * When VDD is present, charge the external battery on VBAT through an internal resistor.
764 * @param ResistorSelection specifies the resistor impedance.
765 * This parameter can be one of the following values:
766 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
767 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
768 * @retval None
769 */
HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)770 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
771 {
772 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
773
774 /* Specify resistor selection */
775 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
776
777 /* Enable battery charging */
778 SET_BIT(PWR->CR4, PWR_CR4_VBE);
779 }
780
781 /**
782 * @brief Disable battery charging.
783 * @retval None
784 */
HAL_PWREx_DisableBatteryCharging(void)785 void HAL_PWREx_DisableBatteryCharging(void)
786 {
787 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
788 }
789 /**
790 * @brief This function handles the PWR PVD/PVMx interrupt request.
791 * @note This API should be called under the PVD_PVM_IRQHandler().
792 * @retval None
793 */
HAL_PWREx_PVD_PVM_IRQHandler(void)794 void HAL_PWREx_PVD_PVM_IRQHandler(void)
795 {
796 /* Check if the Programmable Voltage Detector is enabled (PVD) */
797 if (READ_BIT(PWR->CR2, PWR_CR2_PVDE) != 0U)
798 {
799 /* Check PWR EXTI Rising flag */
800 if (__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0U)
801 {
802 /* PWR PVD interrupt user callback */
803 HAL_PWR_PVDCallback();
804
805 /* Clear PWR EXTI pending bit */
806 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
807 }
808
809 /* Check PWR EXTI Falling flag */
810 if (__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0U)
811 {
812 /* PWR PVD interrupt user callback */
813 HAL_PWR_PVDCallback();
814
815 /* Clear PWR EXTI pending bit */
816 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
817 }
818 }
819
820 /* Next, successively check PVMx exti flags */
821 #if defined(USB_DRD_FS)
822 if (READ_BIT(PWR->CR2, PWR_PVM_1) != 0U)
823 {
824 /* Check PWR EXTI Rising flag */
825 if (__HAL_PWR_PVM1_EXTI_GET_RISING_FLAG() != 0U)
826 {
827 /* PWR PVM interrupt user callback */
828 HAL_PWREx_PVM1_Callback();
829
830 /* Clear PWR EXTI pending bit */
831 __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
832 }
833
834 /* Check PWR EXTI Falling flag */
835 if (__HAL_PWR_PVM1_EXTI_GET_FALLING_FLAG() != 0U)
836 {
837 /* PWR PVM USB interrupt user callback */
838 HAL_PWREx_PVM1_Callback();
839
840 /* Clear PWR EXTI pending bit */
841 __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
842 }
843 }
844 #endif /* USB_DRD_FS */
845 if (READ_BIT(PWR->CR2, PWR_PVM_3) != 0U)
846 {
847 /* Check PWR EXTI Rising flag */
848 if (__HAL_PWR_PVM3_EXTI_GET_RISING_FLAG() != 0U)
849 {
850 /* PWR PVM interrupt user callback */
851 HAL_PWREx_PVM3_Callback();
852
853 /* Clear PWR EXTI pending bit */
854 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
855 }
856
857 /* Check PWR EXTI Falling flag */
858 if (__HAL_PWR_PVM3_EXTI_GET_FALLING_FLAG() != 0U)
859 {
860 /* PWR PVM ADC interrupt user callback */
861 HAL_PWREx_PVM3_Callback();
862
863 /* Clear PWR EXTI pending bit */
864 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
865 }
866 }
867
868 if (READ_BIT(PWR->CR2, PWR_PVM_4) != 0U)
869 {
870 /* Check PWR EXTI Rising flag */
871 if (__HAL_PWR_PVM4_EXTI_GET_RISING_FLAG() != 0U)
872 {
873 /* PWR PVM interrupt user callback */
874 HAL_PWREx_PVM4_Callback();
875
876 /* Clear PWR EXTI pending bit */
877 __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
878 }
879
880 /* Check PWR EXTI Falling flag */
881 if (__HAL_PWR_PVM4_EXTI_GET_FALLING_FLAG() != 0U)
882 {
883 /* PWR PVM4 for DAC interrupt user callback */
884 HAL_PWREx_PVM4_Callback();
885
886 /* Clear PWR EXTI pending bit */
887 __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
888 }
889 }
890 }
891
892 #if defined(USB_DRD_FS)
893 /**
894 * @brief PWR PVM USB interrupt callback
895 * @retval None
896 */
HAL_PWREx_PVM1_Callback(void)897 __weak void HAL_PWREx_PVM1_Callback(void)
898 {
899 /* NOTE : This function should not be modified; when the callback is needed,
900 HAL_PWREx_PVM_USBCallback() API can be implemented in the user file
901 */
902 }
903 #endif /* USB_DRD_FS */
904
905 /**
906 * @brief PWR PVM ADC interrupt callback
907 * @retval None
908 */
HAL_PWREx_PVM3_Callback(void)909 __weak void HAL_PWREx_PVM3_Callback(void)
910 {
911 /* NOTE : This function should not be modified; when the callback is needed,
912 HAL_PWREx_PVM_ADCCallback() API can be implemented in the user file
913 */
914 }
915
916 /**
917 * @brief PWR PVM DAC interrupt callback
918 * @retval None
919 */
HAL_PWREx_PVM4_Callback(void)920 __weak void HAL_PWREx_PVM4_Callback(void)
921 {
922 /* NOTE : This function should not be modified; when the callback is needed,
923 HAL_PWREx_PVM_DACCallback() API can be implemented in the user file
924 */
925 }
926
927 /**
928 * @brief Enable Internal Wake-up Line.
929 * @retval None
930 */
HAL_PWREx_EnableInternalWakeUpLine(void)931 void HAL_PWREx_EnableInternalWakeUpLine(void)
932 {
933 SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
934 }
935
936 /**
937 * @brief Disable Internal Wake-up Line.
938 * @retval None
939 */
HAL_PWREx_DisableInternalWakeUpLine(void)940 void HAL_PWREx_DisableInternalWakeUpLine(void)
941 {
942 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
943 }
944 /**
945 * @}
946 */
947
948 /** @defgroup PWREx_Exported_Functions_Group4 Memories Retention Functions
949 * @brief Memories retention functions
950 *
951 @verbatim
952 ===============================================================================
953 ##### Memories Retention Functions #####
954 ===============================================================================
955 [..]
956 Several STM32U0 devices RAM are configurable to keep / lose RAMs content
957 during Stop mode (Stop 0/1/2).
958 (+) Retained content RAM in Stop modes are :
959 (++) SRAM
960
961 @endverbatim
962 * @{
963 */
964
965 /**
966 * @brief Enable Full SRAM content retention in Standby mode.
967 * @retval None
968 */
HAL_PWREx_EnableSRAMContentRetention(void)969 void HAL_PWREx_EnableSRAMContentRetention(void)
970 {
971 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, PWR_FULL_SRAM_RETENTION);
972 }
973
974 /**
975 * @brief Disable SRAM content retention in Standby mode.
976 * @retval None
977 */
HAL_PWREx_DisableSRAMContentRetention(void)978 void HAL_PWREx_DisableSRAMContentRetention(void)
979 {
980 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
981 }
982
983 /**
984 * @brief Enable Flash Power Down.
985 * @note This API allows to enable flash power down capabilities in low power
986 * run, low power sleep and stop modes.
987 * @param PowerMode this can be a combination of following values:
988 * @arg @ref PWR_FLASHPD_LPRUN
989 * @arg @ref PWR_FLASHPD_LPSLEEP
990 * @arg @ref PWR_FLASHPD_STOP
991 * @retval None
992 */
HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode)993 void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode)
994 {
995 assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode));
996
997 PWR->CR1 |= PowerMode;
998 }
999
1000 /**
1001 * @brief Disable Flash Power Down.
1002 * @note This API allows to disable flash power down capabilities in low power
1003 * run, low power sleep and stop modes.
1004 * @param PowerMode this can be a combination of following values:
1005 * @arg @ref PWR_FLASHPD_LPRUN
1006 * @arg @ref PWR_FLASHPD_LPSLEEP
1007 * @arg @ref PWR_FLASHPD_STOP
1008 * @retval None
1009 */
HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode)1010 void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode)
1011 {
1012 assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode));
1013
1014 PWR->CR1 &= ~PowerMode;
1015 }
1016
1017 /**
1018 * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes.
1019 * @note All the other modes are not affected by this bit.
1020 * @retval None
1021 */
HAL_PWREx_EnableUltraLowPowerMode(void)1022 void HAL_PWREx_EnableUltraLowPowerMode(void)
1023 {
1024 SET_BIT(PWR->CR3, PWR_CR3_ENULP);
1025 }
1026
1027 /**
1028 * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes.
1029 * @note All the other modes are not affected by this bit
1030 * @retval None
1031 */
HAL_PWREx_DisableUltraLowPowerMode(void)1032 void HAL_PWREx_DisableUltraLowPowerMode(void)
1033 {
1034 CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP);
1035 }
1036 /**
1037 * @}
1038 */
1039
1040 /** @defgroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions
1041 * @brief I/O pull-up / pull-down configuration functions
1042 *
1043 @verbatim
1044 ===============================================================================
1045 ##### Pull-Up Pull-Down Configuration Functions #####
1046 ===============================================================================
1047 [..]
1048 In Standby and Shutdown mode, pull up and pull down can be configured to
1049 maintain an I/O in the selected state. If the APC bit in the PWR_APCR
1050 register is set, the I/Os can be configured either with a pull-up through
1051 PWR_PUCRx registers (x=A,B,C,D,E,F), or with a pull-down through
1052 PWR_PDCRx registers (x=A,B,C,D,E,F), or can be kept in analog state
1053 if none of the PWR_PUCRx or PWR_PDCRx register is set.
1054
1055 [..]
1056 The pull-down configuration has highest priority over pull-up
1057 configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same
1058 I/O.
1059 This configuration is lost when exiting the Shutdown but not from Standby
1060 mode.
1061
1062 @endverbatim
1063 * @{
1064 */
1065
1066 /**
1067 * @brief Enable pull-up and pull-down configuration.
1068 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
1069 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
1070 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
1071 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
1072 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
1073 * is no conflict when setting PUy or PDy bit.
1074 * @retval None
1075 */
HAL_PWREx_EnablePullUpPullDownConfig(void)1076 void HAL_PWREx_EnablePullUpPullDownConfig(void)
1077 {
1078 SET_BIT(PWR->CR3, PWR_CR3_APC);
1079 }
1080
1081 /**
1082 * @brief Disable pull-up and pull-down configuration.
1083 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
1084 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
1085 * @retval None
1086 */
HAL_PWREx_DisablePullUpPullDownConfig(void)1087 void HAL_PWREx_DisablePullUpPullDownConfig(void)
1088 {
1089 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
1090 }
1091 /**
1092 * @}
1093 */
1094
1095 /**
1096 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
1097 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
1098 * pull-up state in Standby and Shutdown modes.
1099 * @note This state is effective in Standby and Shutdown modes only if APC bit
1100 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
1101 * @note The configuration is lost when exiting the Shutdown mode due to the
1102 * power-on reset, maintained when exiting the Standby mode.
1103 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
1104 * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
1105 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input
1106 * parameter at the same time are set.
1107 * @param GPIO_Port Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
1108 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
1109 * @param GPIO_Pin Specify the I/O pins numbers.
1110 * This parameter can be one of the following values:
1111 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
1112 * I/O pins are available) or the logical OR of several of them to set
1113 * several bits for a given port in a single API call.
1114 * @retval HAL Status
1115 */
HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port,uint32_t GPIO_Pin)1116 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin)
1117 {
1118 HAL_StatusTypeDef status = HAL_OK;
1119
1120 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
1121 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
1122
1123 switch (GPIO_Port)
1124 {
1125 case PWR_GPIO_A:
1126 SET_BIT(PWR->PUCRA, GPIO_Pin);
1127 CLEAR_BIT(PWR->PDCRA, GPIO_Pin);
1128 break;
1129
1130 case PWR_GPIO_B:
1131 SET_BIT(PWR->PUCRB, GPIO_Pin);
1132 CLEAR_BIT(PWR->PDCRB, GPIO_Pin);
1133 break;
1134
1135 case PWR_GPIO_C:
1136 SET_BIT(PWR->PUCRC, GPIO_Pin);
1137 CLEAR_BIT(PWR->PDCRC, GPIO_Pin);
1138 break;
1139
1140 case PWR_GPIO_D:
1141 SET_BIT(PWR->PUCRD, (GPIO_Pin & PWR_PORTD_AVAILABLE_PINS));
1142 CLEAR_BIT(PWR->PDCRD, (GPIO_Pin & PWR_PORTD_AVAILABLE_PINS));
1143 break;
1144
1145 #if defined (GPIOE)
1146 case PWR_GPIO_E:
1147 SET_BIT(PWR->PUCRE, (GPIO_Pin & PWR_PORTE_AVAILABLE_PINS));
1148 CLEAR_BIT(PWR->PDCRE, (GPIO_Pin & PWR_PORTE_AVAILABLE_PINS));
1149 break;
1150 #endif /* GPIOE */
1151
1152 case PWR_GPIO_F:
1153 SET_BIT(PWR->PUCRF, (GPIO_Pin & PWR_PORTF_AVAILABLE_PINS));
1154 CLEAR_BIT(PWR->PDCRF, (GPIO_Pin & PWR_PORTF_AVAILABLE_PINS));
1155 break;
1156
1157 default:
1158 status = HAL_ERROR;
1159 break;
1160 }
1161
1162 return status;
1163 }
1164
1165 /**
1166 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
1167 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
1168 * in pull-up state in Standby and Shutdown modes.
1169 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input
1170 * parameter at the same time are reset.
1171 * @param GPIO_Port Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
1172 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
1173 * @param GPIO_Pin Specify the I/O pins numbers.
1174 * This parameter can be one of the following values:
1175 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
1176 * I/O pins are available) or the logical OR of several of them to reset
1177 * several bits for a given port in a single API call.
1178 * @retval HAL Status
1179 */
HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port,uint32_t GPIO_Pin)1180 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin)
1181 {
1182 HAL_StatusTypeDef status = HAL_OK;
1183
1184 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
1185 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
1186
1187 switch (GPIO_Port)
1188 {
1189 case PWR_GPIO_A:
1190 CLEAR_BIT(PWR->PUCRA, GPIO_Pin);
1191 break;
1192
1193 case PWR_GPIO_B:
1194 CLEAR_BIT(PWR->PUCRB, GPIO_Pin);
1195 break;
1196
1197 case PWR_GPIO_C:
1198 CLEAR_BIT(PWR->PUCRC, GPIO_Pin);
1199 break;
1200
1201 case PWR_GPIO_D:
1202 CLEAR_BIT(PWR->PUCRD, (GPIO_Pin & PWR_PORTD_AVAILABLE_PINS));
1203 break;
1204
1205 #if defined (GPIOE)
1206 case PWR_GPIO_E:
1207 CLEAR_BIT(PWR->PUCRE, (GPIO_Pin & PWR_PORTE_AVAILABLE_PINS));
1208 break;
1209 #endif /* GPIOE */
1210
1211 case PWR_GPIO_F:
1212 CLEAR_BIT(PWR->PUCRF, (GPIO_Pin & PWR_PORTF_AVAILABLE_PINS));
1213 break;
1214
1215 default:
1216 status = HAL_ERROR;
1217 break;
1218 }
1219
1220 return status;
1221 }
1222
1223 /**
1224 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
1225 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
1226 * pull-down state in Standby and Shutdown modes.
1227 * @note This state is effective in Standby and Shutdown modes only if APC bit
1228 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
1229 * @note The configuration is lost when exiting the Shutdown mode due to the
1230 * power-on reset, maintained when exiting the Standby mode.
1231 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
1232 * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
1233 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input
1234 * parameter at the same time are set.
1235 * @param GPIO_Port Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
1236 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
1237 * @param GPIO_Pin Specify the I/O pins numbers.
1238 * This parameter can be one of the following values:
1239 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
1240 * I/O pins are available) or the logical OR of several of them to set
1241 * several bits for a given port in a single API call.
1242 * @retval HAL Status
1243 */
HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port,uint32_t GPIO_Pin)1244 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin)
1245 {
1246 HAL_StatusTypeDef status = HAL_OK;
1247
1248 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
1249 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
1250
1251 switch (GPIO_Port)
1252 {
1253 case PWR_GPIO_A:
1254 SET_BIT(PWR->PDCRA, GPIO_Pin);
1255 CLEAR_BIT(PWR->PUCRA, GPIO_Pin);
1256 break;
1257
1258 case PWR_GPIO_B:
1259 SET_BIT(PWR->PDCRB, GPIO_Pin);
1260 CLEAR_BIT(PWR->PUCRB, GPIO_Pin);
1261 break;
1262
1263 case PWR_GPIO_C:
1264 SET_BIT(PWR->PDCRC, GPIO_Pin);
1265 CLEAR_BIT(PWR->PUCRC, GPIO_Pin);
1266 break;
1267
1268 case PWR_GPIO_D:
1269 SET_BIT(PWR->PDCRD, (GPIO_Pin & PWR_PORTD_AVAILABLE_PINS));
1270 CLEAR_BIT(PWR->PUCRD, (GPIO_Pin & PWR_PORTD_AVAILABLE_PINS));
1271 break;
1272
1273 #if defined (GPIOE)
1274 case PWR_GPIO_E:
1275 SET_BIT(PWR->PDCRE, (GPIO_Pin & PWR_PORTE_AVAILABLE_PINS));
1276 CLEAR_BIT(PWR->PUCRE, (GPIO_Pin & PWR_PORTE_AVAILABLE_PINS));
1277 break;
1278 #endif /* GPIOE */
1279
1280 case PWR_GPIO_F:
1281 SET_BIT(PWR->PDCRF, (GPIO_Pin & PWR_PORTF_AVAILABLE_PINS));
1282 CLEAR_BIT(PWR->PUCRF, (GPIO_Pin & PWR_PORTF_AVAILABLE_PINS));
1283 break;
1284
1285 default:
1286 status = HAL_ERROR;
1287 break;
1288 }
1289
1290 return status;
1291 }
1292
1293 /**
1294 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
1295 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
1296 * in pull-down state in Standby and Shutdown modes.
1297 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
1298 * parameter at the same time are reset.
1299 * @param GPIO_Port Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
1300 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
1301 * @param GPIO_Pin Specify the I/O pins numbers.
1302 * This parameter can be one of the following values:
1303 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
1304 * I/O pins are available) or the logical OR of several of them to reset
1305 * several bits for a given port in a single API call.
1306 * @retval HAL Status
1307 */
HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port,uint32_t GPIO_Pin)1308 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin)
1309 {
1310 HAL_StatusTypeDef status = HAL_OK;
1311
1312 assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
1313 assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
1314
1315 switch (GPIO_Port)
1316 {
1317 case PWR_GPIO_A:
1318 CLEAR_BIT(PWR->PDCRA, GPIO_Pin);
1319 break;
1320
1321 case PWR_GPIO_B:
1322 CLEAR_BIT(PWR->PDCRB, GPIO_Pin);
1323 break;
1324
1325 case PWR_GPIO_C:
1326 CLEAR_BIT(PWR->PDCRC, GPIO_Pin);
1327 break;
1328
1329 case PWR_GPIO_D:
1330 CLEAR_BIT(PWR->PDCRD, (GPIO_Pin & PWR_PORTD_AVAILABLE_PINS));
1331 break;
1332
1333 #if defined (GPIOE)
1334 case PWR_GPIO_E:
1335 CLEAR_BIT(PWR->PDCRE, (GPIO_Pin & PWR_PORTE_AVAILABLE_PINS));
1336 break;
1337 #endif /* GPIOE */
1338
1339 case PWR_GPIO_F:
1340 CLEAR_BIT(PWR->PDCRF, (GPIO_Pin & PWR_PORTF_AVAILABLE_PINS));
1341 break;
1342
1343 default:
1344 status = HAL_ERROR;
1345 break;
1346 }
1347
1348 return status;
1349 }
1350
1351 #endif /* defined (HAL_PWR_MODULE_ENABLED) */
1352
1353 /**
1354 * @}
1355 */
1356
1357 /**
1358 * @}
1359 */
1360
1361 /**
1362 * @}
1363 */
1364
