1 /**
2 ******************************************************************************
3 * @file stm32u0xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization/de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2023 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 */
23
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32u0xx_hal.h"
26
27 /** @addtogroup STM32U0xx_HAL_Driver
28 * @{
29 */
30
31 /** @defgroup PWR PWR
32 * @brief PWR HAL module driver
33 * @{
34 */
35
36 #ifdef HAL_PWR_MODULE_ENABLED
37
38 /* Private typedef -----------------------------------------------------------*/
39 /* Private define ------------------------------------------------------------*/
40
41 /** @defgroup PWR_Private_Defines PWR Private Defines
42 * @{
43 */
44
45 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
46 * @{
47 */
48 #define PVD_MODE_IT 0x00010000U /*!< Mask for interruption yielded by PVD threshold crossing */
49 #define PVD_MODE_EVT 0x00020000U /*!< Mask for event yielded by PVD threshold crossing */
50 #define PVD_RISING_EDGE 0x00000001U /*!< Mask for rising edge set as PVD trigger */
51 #define PVD_FALLING_EDGE 0x00000002U /*!< Mask for falling edge set as PVD trigger */
52 /**
53 * @}
54 */
55
56 /** @defgroup PWR_Enable_PWR PWR EWUP All Pins
57 * @{
58 */
59 #define PWR_EWUP_Msk 0x0000005FU /*!< Mask for all wake-up pins */
60 /**
61 * @}
62 */
63
64 /**
65 * @}
66 */
67
68 /* Private macro -------------------------------------------------------------*/
69 /* Private variables ---------------------------------------------------------*/
70 /* Private function prototypes -----------------------------------------------*/
71 /* Exported functions --------------------------------------------------------*/
72
73 /** @defgroup PWR_Exported_Functions PWR Exported Functions
74 * @{
75 */
76
77 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
78 * @brief Initialization and de-initialization functions
79 *
80 @verbatim
81 ===============================================================================
82 ##### Initialization and de-initialization functions #####
83 ===============================================================================
84 [..]
85
86 @endverbatim
87 * @{
88 */
89
90 /**
91 * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
92 * @retval None
93 */
HAL_PWR_DeInit(void)94 void HAL_PWR_DeInit(void)
95 {
96 __HAL_RCC_PWR_FORCE_RESET();
97 __HAL_RCC_PWR_RELEASE_RESET();
98 }
99
100 /**
101 * @brief Enable access to the backup domain
102 * (RTC registers, RTC backup data registers).
103 * @note After reset, the backup domain is protected against
104 * possible unwanted write accesses.
105 * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
106 * In order to set or modify the RTC clock, the backup domain access must be
107 * disabled.
108 * @note LSEON bit that switches on and off the LSE crystal belongs as well to the
109 * back-up domain.
110 * @retval None
111 */
HAL_PWR_EnableBkUpAccess(void)112 void HAL_PWR_EnableBkUpAccess(void)
113 {
114 SET_BIT(PWR->CR1, PWR_CR1_DBP);
115 }
116
117 /**
118 * @brief Disable access to the backup domain
119 * (RTC registers, RTC backup data registers).
120 * @retval None
121 */
HAL_PWR_DisableBkUpAccess(void)122 void HAL_PWR_DisableBkUpAccess(void)
123 {
124 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
125 }
126 /**
127 * @}
128 */
129
130
131 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
132 * @brief Low Power modes configuration functions
133 *
134 @verbatim
135
136 ===============================================================================
137 ##### Peripheral Control functions #####
138 ===============================================================================
139
140 [..]
141 *** PVD configuration ***
142 =========================
143 [..]
144 (+) The PVD is used to monitor the VDD power supply by comparing it to a
145 threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
146
147 (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
148 than the PVD threshold. This event is internally connected to the EXTI
149 line16 and can generate an interrupt if enabled. This is done through
150 __HAL_PVD_EXTI_ENABLE_IT() macro.
151 (+) The PVD is stopped in Standby mode.
152
153
154 *** WakeUp pin configuration ***
155 ================================
156 [..]
157 (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
158 The polarity of these pins can be set to configure event detection on high
159 level (rising edge) or low level (falling edge).
160
161
162
163 *** Low Power modes configuration ***
164 =====================================
165 [..]
166 The devices feature 8 low-power modes:
167 (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
168 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
169 (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off,
170 low power regulator on.
171 (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
172 (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
173 (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on,
174 reduced set of waking up IPs compared to Stop 1 mode.
175 (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved,
176 main regulator off, low power regulator on.
177 (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
178 (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
179
180
181 *** Low-power run mode ***
182 ==========================
183 [..]
184 (+) Entry: (from main run mode)
185 (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
186
187 (+) Exit:
188 (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
189 then can the system clock frequency be increased above 2 MHz.
190
191
192 *** Sleep mode / Low-power sleep mode ***
193 =========================================
194 [..]
195 (+) Entry:
196 The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
197 in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt
198 or event-triggered.
199 (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
200 (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
201 In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
202 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
203 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
204
205 (+) WFI Exit:
206 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
207 controller (NVIC) or any wake-up event.
208
209 (+) WFE Exit:
210 (++) Any wake-up event such as an EXTI line configured in event mode.
211
212 [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
213 the MCU is in Low-power Run mode.
214
215 *** Stop 0, Stop 1 and Stop 2 modes ***
216 ===============================
217 [..]
218 (+) Entry:
219 The Stop 0, Stop 1 or Stop 2 modes are entered through the following API's:
220 (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or
221 for porting reasons HAL_PWR_EnterSTOPMode().
222 (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
223 (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
224 (++) PWR_MAINREGULATOR_ON
225 (++) PWR_LOWPOWERREGULATOR_ON
226 (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
227 (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
228 (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
229
230 (+) WFI Exit:
231 (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
232 (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
233 when programmed in wakeup mode.
234 (+) WFE Exit:
235 (++) Any EXTI Line (Internal or External) configured in Event mode.
236
237 [..]
238 When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
239 depending on the LPR bit setting.
240 When exiting Stop 2 mode, the MCU is in Run mode.
241
242 *** Standby mode ***
243 ====================
244 [..]
245 The Standby mode offers two options:
246 (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
247 SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
248 and Standby circuitry.
249 (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
250 SRAM and register contents are lost except for the RTC registers, RTC backup registers
251 and Standby circuitry.
252
253 (++) Entry:
254 (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
255 SRAM1 and register contents are lost except for registers in the Backup domain and
256 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
257 To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
258 to set RRS bit.
259
260 (++) Exit:
261 (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
262 external reset in NRST pin, IWDG reset.
263
264 [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
265
266
267 *** Shutdown mode ***
268 ======================
269 [..]
270 In Shutdown mode,
271 voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
272 SRAM and registers contents are lost except for backup domain registers.
273
274 (+) Entry:
275 The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
276
277 (+) Exit:
278 (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
279 external reset in NRST pin.
280
281 [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
282
283
284 *** Auto-wakeup (AWU) from low-power mode ***
285 =============================================
286 [..]
287 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
288 Wakeup event, a tamper event or a time-stamp event, without depending on
289 an external interrupt (Auto-wakeup mode).
290
291 (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
292
293
294 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
295 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
296
297 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
298 is necessary to configure the RTC to detect the tamper or time stamp event using the
299 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
300
301 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
302 configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
303
304 @endverbatim
305 * @{
306 */
307
308 /**
309 * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
310 * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
311 * configuration information.
312 * @note Refer to the electrical characteristics of your device datasheet for
313 * more details about the voltage thresholds corresponding to each
314 * detection level.
315 * @retval None
316 */
HAL_PWR_ConfigPVD(const PWR_PVDTypeDef * sConfigPVD)317 HAL_StatusTypeDef HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD)
318 {
319 /* Check the parameters */
320 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
321 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
322
323 /* Set PLS bits according to PVDLevel value */
324 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
325
326 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
327 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
328 __HAL_PWR_PVD_EXTI_DISABLE_IT();
329 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
330 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
331
332 /* Configure interrupt mode */
333 if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
334 {
335 __HAL_PWR_PVD_EXTI_ENABLE_IT();
336 }
337
338 /* Configure event mode */
339 if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
340 {
341 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
342 }
343
344 /* Configure the edge */
345 if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
346 {
347 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
348 }
349
350 if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
351 {
352 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
353 }
354
355 return HAL_OK;
356 }
357
358 /**
359 * @brief Enable the Power Voltage Detector (PVD).
360 * @retval None
361 */
HAL_PWR_EnablePVD(void)362 void HAL_PWR_EnablePVD(void)
363 {
364 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
365 }
366
367 /**
368 * @brief Disable the Power Voltage Detector (PVD).
369 * @retval None
370 */
HAL_PWR_DisablePVD(void)371 void HAL_PWR_DisablePVD(void)
372 {
373 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
374 }
375
376 /**
377 * @brief Enable the WakeUp PINx functionality.
378 * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
379 * This parameter can be one of the following legacy values which set the default polarity
380 * i.e. detection on high level (rising edge):
381 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
382 *
383 * or one of the following value where the user can explicitly specify the enabled pin and
384 * the chosen polarity:
385 * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
386 * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
387 * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
388 * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
389 * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
390 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
391 * @retval None
392 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)393 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
394 {
395 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
396
397 /* Specifies the Wake-Up pin polarity for the event detection
398 (rising or falling edge) */
399 MODIFY_REG(PWR->CR4, (PWR_EWUP_Msk & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
400
401 /* Enable wake-up pin */
402 SET_BIT(PWR->CR3, (PWR_EWUP_Msk & WakeUpPinPolarity));
403 }
404
405 /**
406 * @brief Disable the WakeUp PINx functionality.
407 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
408 * This parameter can be one of the following values:
409 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
410 * @retval None
411 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)412 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
413 {
414 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
415
416 CLEAR_BIT(PWR->CR3, (PWR_EWUP_Msk & WakeUpPinx));
417 }
418
419 /**
420 * @brief Enter Sleep or Low-power Sleep mode.
421 * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
422 * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
423 * This parameter can be one of the following values:
424 * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
425 * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
426 * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
427 * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
428 * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
429 * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
430 * Additionally, the clock frequency must be reduced below 2 MHz.
431 * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
432 * be done before calling HAL_PWR_EnterSLEEPMode() API.
433 * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
434 * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
435 * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
436 * This parameter can be one of the following values:
437 * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
438 * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
439 * @note When WFI entry is used, tick interrupt have to be disabled if not desired as
440 * the interrupt wake up source.
441 * @retval None
442 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)443 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
444 {
445 /* Check the parameters */
446 assert_param(IS_PWR_REGULATOR(Regulator));
447 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
448
449 /* Set Regulator parameter */
450 if (Regulator == PWR_MAINREGULATOR_ON)
451 {
452 /* If in low-power run mode at this point, exit it */
453 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
454 {
455 if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
456 {
457 return ;
458 }
459 }
460 /* Regulator now in main mode. */
461 }
462 else
463 {
464 /* If in run mode, first move to low-power run mode.
465 The system clock frequency must be below 2 MHz at this point. */
466 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
467 {
468 HAL_PWREx_EnableLowPowerRunMode();
469 }
470 }
471
472 /* Clear SLEEPDEEP bit of Cortex System Control Register */
473 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
474
475 /* Select SLEEP mode entry -------------------------------------------------*/
476 if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
477 {
478 /* Request Wait For Interrupt */
479 __WFI();
480 }
481 else
482 {
483 /* Request Wait For Event */
484 __SEV();
485 __WFE();
486 __WFE();
487 }
488 }
489
490 /**
491 * @brief Enter Stop 0 mode
492 * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
493 * on devices where only "Stop mode" is mentioned with main or low power regulator ON.
494 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
495 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
496 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
497 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
498 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
499 * only to the peripheral requesting it.
500 * SRAM1, SRAM2 and register contents are preserved.
501 * The BOR is available.
502 * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
503 * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
504 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
505 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
506 * @note When the voltage regulator operates in low power mode (Stop 1), an additional
507 * startup delay is incurred when waking up.
508 * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
509 * is higher although the startup time is reduced.
510 * @param Regulator: Specifies the regulator state in Stop mode.
511 * This parameter can be one of the following values:
512 * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
513 * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
514 * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
515 * This parameter can be one of the following values:
516 * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
517 * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
518 * @retval None
519 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)520 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
521 {
522
523 /* Check the parameters */
524 assert_param(IS_PWR_REGULATOR(Regulator));
525 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
526 /* Select the regulator state in STOP mode */
527 MODIFY_REG(PWR->CR1, PWR_CR1_LPR, Regulator);
528 /* Stop 0 mode with Main Regulator */
529 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, 0U);
530 /* Set SLEEPDEEP bit of Cortex System Control Register */
531 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
532 /* Select Stop mode entry --------------------------------------------------*/
533 if (STOPEntry == PWR_STOPENTRY_WFI)
534 {
535 /* Request Wait For Interrupt */
536 __WFI();
537 }
538 else
539 {
540 /* Request Wait For Event */
541 __SEV();
542 __WFE();
543 __WFE();
544 }
545 /* Reset SLEEPDEEP bit of Cortex System Control Register */
546 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
547 }
548
549 /**
550 * @brief Enter Standby mode.
551 * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
552 * off. The voltage regulator is disabled, except when SRAM2 content is preserved
553 * in which case the regulator is in low-power mode.
554 * SRAM1 and register contents are lost except for registers in the Backup domain and
555 * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
556 * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
557 * to set RRS bit.
558 * The BOR is available.
559 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
560 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
561 * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
562 * same.
563 * These states are effective in Standby mode only if APC bit is set through
564 * HAL_PWREx_EnablePullUpPullDownConfig() API.
565 * @retval None
566 */
HAL_PWR_EnterSTANDBYMode(void)567 void HAL_PWR_EnterSTANDBYMode(void)
568 {
569 /* Set Stand-by mode */
570 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0));
571
572 /* Set SLEEPDEEP bit of Cortex System Control Register */
573 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
574
575 /* Request Wait For Interrupt */
576 __WFI();
577 }
578
579 /**
580 * @brief Enter Shutdown mode.
581 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
582 * off. The voltage regulator is disabled and Vcore domain is powered off.
583 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
584 * The BOR is not available.
585 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
586 * @retval None
587 */
HAL_PWR_EnterSHUTDOWNMode(void)588 void HAL_PWR_EnterSHUTDOWNMode(void)
589 {
590
591 /* Set Shutdown mode */
592 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_2);
593
594
595 /* Set SLEEPDEEP bit of Cortex System Control Register */
596 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
597
598 /* This option is used to ensure that store operations are completed */
599 #if defined ( __CC_ARM)
600 __force_stores();
601 #endif /* __CC_ARM */
602 /* Request Wait For Interrupt */
603 __WFI();
604 }
605
606 /**
607 * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
608 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
609 * re-enters SLEEP mode when an interruption handling is over.
610 * Setting this bit is useful when the processor is expected to run only on
611 * interruptions handling.
612 * @retval None
613 */
HAL_PWR_EnableSleepOnExit(void)614 void HAL_PWR_EnableSleepOnExit(void)
615 {
616 /* Set SLEEPONEXIT bit of Cortex System Control Register */
617 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
618 }
619
620 /**
621 * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
622 * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
623 * re-enters SLEEP mode when an interruption handling is over.
624 * @retval None
625 */
HAL_PWR_DisableSleepOnExit(void)626 void HAL_PWR_DisableSleepOnExit(void)
627 {
628 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
629 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
630 }
631
632 /**
633 * @brief Enable CORTEX M4 SEVONPEND bit.
634 * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
635 * WFE to wake up when an interrupt moves from inactive to pended.
636 * @retval None
637 */
HAL_PWR_EnableSEVOnPend(void)638 void HAL_PWR_EnableSEVOnPend(void)
639 {
640 /* Set SEVONPEND bit of Cortex System Control Register */
641 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
642 }
643
644 /**
645 * @brief Disable CORTEX M4 SEVONPEND bit.
646 * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
647 * WFE to wake up when an interrupt moves from inactive to pended.
648 * @retval None
649 */
HAL_PWR_DisableSEVOnPend(void)650 void HAL_PWR_DisableSEVOnPend(void)
651 {
652 /* Clear SEVONPEND bit of Cortex System Control Register */
653 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
654 }
655
656 /**
657 * @brief PWR PVD interrupt callback
658 * @retval None
659 */
HAL_PWR_PVDCallback(void)660 __weak void HAL_PWR_PVDCallback(void)
661 {
662 /* NOTE : This function should not be modified; when the callback is needed,
663 the HAL_PWR_PVDCallback can be implemented in the user file
664 */
665 }
666 /**
667 * @}
668 */
669
670 /**
671 * @}
672 */
673
674 #endif /* HAL_PWR_MODULE_ENABLED */
675 /**
676 * @}
677 */
678
679 /**
680 * @}
681 */
682
