1 /**
2 ******************************************************************************
3 * @file stm32u0xx_hal_lptim.c
4 * @author MCD Application Team
5 * @brief LPTIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Low Power Timer (LPTIM) peripheral:
8 * + Initialization and de-initialization functions.
9 * + Start/Stop operation functions in polling mode.
10 * + Start/Stop operation functions in interrupt mode.
11 * + Reading operation functions.
12 * + Peripheral State functions.
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2023 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### How to use this driver #####
28 ==============================================================================
29 [..]
30 The LPTIM HAL driver can be used as follows:
31
32 (#)Initialize the LPTIM low level resources by implementing the
33 HAL_LPTIM_MspInit():
34 (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
35 (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
36 (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
37 (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
38 (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
39
40 (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
41 configures mainly:
42 (++) The instance: LPTIM1, LPTIM2, LPTIM3 or LPTIM4.
43 (++) Clock: the counter clock.
44 (+++) Source : it can be either the ULPTIM input (IN1) or one of
45 the internal clock; (APB, LSE, LSI or MSI).
46 (+++) Prescaler: select the clock divider.
47 (++) UltraLowPowerClock : To be used only if the ULPTIM is selected
48 as counter clock source.
49 (+++) Polarity: polarity of the active edge for the counter unit
50 if the ULPTIM input is selected.
51 (+++) SampleTime: clock sampling time to configure the clock glitch
52 filter.
53 (++) Trigger: How the counter start.
54 (+++) Source: trigger can be software or one of the hardware triggers.
55 (+++) ActiveEdge : only for hardware trigger.
56 (+++) SampleTime : trigger sampling time to configure the trigger
57 glitch filter.
58 (++) OutputPolarity : 2 opposite polarities are possible.
59 (++) UpdateMode: specifies whether the update of the autoreload and
60 the compare values is done immediately or after the end of current
61 period.
62 (++) Input1Source: Source selected for input1 (GPIO or comparator output).
63 (++) Input2Source: Source selected for input2 (GPIO or comparator output).
64 Input2 is used only for encoder feature so is used only for LPTIM1 instance.
65
66 (#)Six modes are available:
67
68 (++) PWM Mode: To generate a PWM signal with specified period and pulse,
69 call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
70 mode.
71
72 (++) One Pulse Mode: To generate pulse with specified width in response
73 to a stimulus, call HAL_LPTIM_OnePulse_Start() or
74 HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
75
76 (++) Set once Mode: In this mode, the output changes the level (from
77 low level to high level if the output polarity is configured high, else
78 the opposite) when a compare match occurs. To start this mode, call
79 HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
80 interruption mode.
81
82 (++) Encoder Mode: To use the encoder interface call
83 HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
84 interruption mode. Only available for LPTIM1 instance.
85
86 (++) Time out Mode: an active edge on one selected trigger input rests
87 the counter. The first trigger event will start the timer, any
88 successive trigger event will reset the counter and the timer will
89 restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
90 HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
91
92 (++) Counter Mode: counter can be used to count external events on
93 the LPTIM Input1 or it can be used to count internal clock cycles.
94 To start this mode, call HAL_LPTIM_Counter_Start() or
95 HAL_LPTIM_Counter_Start_IT() for interruption mode.
96
97
98 (#) User can stop any process by calling the corresponding API:
99 HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
100 already started in interruption mode.
101
102 (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
103
104 *** Callback registration ***
105 =============================================
106 [..]
107 The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
108 allows the user to configure dynamically the driver callbacks.
109 [..]
110 Use Function HAL_LPTIM_RegisterCallback() to register a callback.
111 HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
112 the Callback ID and a pointer to the user callback function.
113 [..]
114 Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
115 default weak function.
116 HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
117 and the Callback ID.
118 [..]
119 These functions allow to register/unregister following callbacks:
120
121 (+) MspInitCallback : LPTIM Base Msp Init Callback.
122 (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback.
123 (+) CompareMatchCallback : Compare match Callback.
124 (+) AutoReloadMatchCallback : Auto-reload match Callback.
125 (+) TriggerCallback : External trigger event detection Callback.
126 (+) CompareWriteCallback : Compare register write complete Callback.
127 (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
128 (+) DirectionUpCallback : Up-counting direction change Callback.
129 (+) DirectionDownCallback : Down-counting direction change Callback.
130 (+) UpdateEventCallback : Update event detection Callback.
131 (+) RepCounterWriteCallback : Repetition counter register write complete Callback.
132
133 [..]
134 By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
135 all interrupt callbacks are set to the corresponding weak functions:
136 examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().
137
138 [..]
139 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
140 functionalities in the Init/DeInit only when these callbacks are null
141 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
142 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
143
144 [..]
145 Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
146 Exception done MspInit/MspDeInit that can be registered/unregistered
147 in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
148 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
149 In that case first register the MspInit/MspDeInit user callbacks
150 using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
151
152 [..]
153 When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
154 not defined, the callback registration feature is not available and all callbacks
155 are set to the corresponding weak functions.
156
157 @endverbatim
158 ******************************************************************************
159 */
160
161 /* Includes ------------------------------------------------------------------*/
162 #include "stm32u0xx_hal.h"
163
164 /** @addtogroup STM32U0xx_HAL_Driver
165 * @{
166 */
167
168 /** @defgroup LPTIM LPTIM
169 * @brief LPTIM HAL module driver.
170 * @{
171 */
172
173 #ifdef HAL_LPTIM_MODULE_ENABLED
174
175 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3)
176
177 /* Private typedef -----------------------------------------------------------*/
178 /* Private define ------------------------------------------------------------*/
179 /** @addtogroup LPTIM_Private_Constants
180 * @{
181 */
182 #define TIMEOUT 1000UL /* Timeout is 1s */
183 /**
184 * @}
185 */
186
187 /* Private macro -------------------------------------------------------------*/
188 /* Private variables ---------------------------------------------------------*/
189 /* Private function prototypes -----------------------------------------------*/
190 static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig);
191 static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig);
192 static HAL_StatusTypeDef LPTIM_OC3_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig);
193 static HAL_StatusTypeDef LPTIM_OC4_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig);
194 static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig);
195 static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig);
196 static void LPTIM_IC3_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig);
197 static void LPTIM_IC4_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig);
198 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
199 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
200 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
201 static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag);
202 void LPTIM_DMAError(DMA_HandleTypeDef *hdma);
203 void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
204 void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
205 void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma);
206 void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma);
207
208 /* Exported functions --------------------------------------------------------*/
209
210 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
211 * @{
212 */
213
214 /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
215 * @brief Initialization and Configuration functions.
216 *
217 @verbatim
218 ==============================================================================
219 ##### Initialization and de-initialization functions #####
220 ==============================================================================
221 [..] This section provides functions allowing to:
222 (+) Initialize the LPTIM according to the specified parameters in the
223 LPTIM_InitTypeDef and initialize the associated handle.
224 (+) DeInitialize the LPTIM peripheral.
225 (+) Initialize the LPTIM MSP.
226 (+) DeInitialize the LPTIM MSP.
227
228 @endverbatim
229 * @{
230 */
231
232 /**
233 * @brief Initialize the LPTIM according to the specified parameters in the
234 * LPTIM_InitTypeDef and initialize the associated handle.
235 * @param hlptim LPTIM handle
236 * @retval HAL status
237 */
HAL_LPTIM_Init(LPTIM_HandleTypeDef * hlptim)238 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
239 {
240 uint32_t tmpcfgr;
241
242 /* Check the LPTIM handle allocation */
243 if (hlptim == NULL)
244 {
245 return HAL_ERROR;
246 }
247
248 /* Check the parameters */
249 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
250 assert_param(IS_LPTIM_PERIOD(hlptim->Init.Period));
251
252 assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
253 assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
254 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
255 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
256 {
257 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
258 assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
259 }
260 assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
261 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
262 {
263 assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
264 assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
265 }
266 assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
267 assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
268 assert_param(IS_LPTIM_REPETITION(hlptim->Init.RepetitionCounter));
269
270 if (hlptim->State == HAL_LPTIM_STATE_RESET)
271 {
272 /* Allocate lock resource and initialize it */
273 hlptim->Lock = HAL_UNLOCKED;
274
275 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
276 /* Reset interrupt callbacks to legacy weak callbacks */
277 LPTIM_ResetCallback(hlptim);
278
279 if (hlptim->MspInitCallback == NULL)
280 {
281 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
282 }
283
284 /* Init the low level hardware : GPIO, CLOCK, NVIC */
285 hlptim->MspInitCallback(hlptim);
286 #else
287 /* Init the low level hardware : GPIO, CLOCK, NVIC */
288 HAL_LPTIM_MspInit(hlptim);
289 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
290 }
291
292 /* Change the LPTIM state */
293 hlptim->State = HAL_LPTIM_STATE_BUSY;
294
295 /* Enable the Peripheral */
296 __HAL_LPTIM_ENABLE(hlptim);
297
298 /* Clear flag */
299 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
300
301 /* Set the repetition counter */
302 __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter);
303
304 /* Wait for the completion of the write operation to the LPTIM_RCR register */
305 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_REPOK) == HAL_TIMEOUT)
306 {
307 return HAL_TIMEOUT;
308 }
309
310
311 /* Clear flag */
312 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
313
314 /* Set LPTIM Period */
315 __HAL_LPTIM_AUTORELOAD_SET(hlptim, hlptim->Init.Period);
316
317 /* Wait for the completion of the write operation to the LPTIM_ARR register */
318 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
319 {
320 return HAL_TIMEOUT;
321 }
322
323 /* Disable the Peripheral */
324 __HAL_LPTIM_DISABLE(hlptim);
325
326 /* Get the LPTIMx CFGR value */
327 tmpcfgr = hlptim->Instance->CFGR;
328
329 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
330 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
331 {
332 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
333 }
334 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
335 {
336 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
337 }
338
339 /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
340 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
341 LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
342
343 /* Set initialization parameters */
344 tmpcfgr |= (hlptim->Init.Clock.Source |
345 hlptim->Init.Clock.Prescaler |
346 hlptim->Init.UpdateMode |
347 hlptim->Init.CounterSource);
348
349 /* Glitch filters for internal triggers and external inputs are configured
350 * only if an internal clock source is provided to the LPTIM
351 */
352 if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
353 {
354 tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
355 hlptim->Init.UltraLowPowerClock.SampleTime);
356 }
357
358 /* Configure LPTIM external clock polarity and digital filter */
359 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
360 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
361 {
362 tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
363 hlptim->Init.UltraLowPowerClock.SampleTime);
364 }
365
366 /* Configure LPTIM external trigger */
367 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
368 {
369 /* Enable External trigger and set the trigger source */
370 tmpcfgr |= (hlptim->Init.Trigger.Source |
371 hlptim->Init.Trigger.ActiveEdge |
372 hlptim->Init.Trigger.SampleTime);
373 }
374
375 /* Write to LPTIMx CFGR */
376 hlptim->Instance->CFGR = tmpcfgr;
377
378 /* Configure LPTIM input sources */
379 #if defined(LPTIM3)
380 if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM3))
381 #else
382 if (hlptim->Instance == LPTIM1)
383 #endif /* LPTIM3 */
384 {
385 /* Check LPTIM Input1 and Input2 sources */
386 assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
387 assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source));
388
389 /* Configure LPTIM Input1 and Input2 sources */
390 hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
391 }
392 else
393 {
394 if (hlptim->Instance == LPTIM2)
395 {
396 /* Check LPTIM Input1 source */
397 assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
398
399 /* Configure LPTIM Input1 source */
400 hlptim->Instance->CFGR2 = hlptim->Init.Input1Source;
401 }
402 }
403
404 /* Initialize the LPTIM channels state */
405 LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_READY);
406
407 /* Change the LPTIM state */
408 hlptim->State = HAL_LPTIM_STATE_READY;
409
410 /* Return function status */
411 return HAL_OK;
412 }
413
414 /**
415 * @brief DeInitialize the LPTIM peripheral.
416 * @param hlptim LPTIM handle
417 * @retval HAL status
418 */
HAL_LPTIM_DeInit(LPTIM_HandleTypeDef * hlptim)419 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
420 {
421 /* Check the LPTIM handle allocation */
422 if (hlptim == NULL)
423 {
424 return HAL_ERROR;
425 }
426
427 /* Change the LPTIM state */
428 hlptim->State = HAL_LPTIM_STATE_BUSY;
429
430 __HAL_LPTIM_ENABLE(hlptim);
431 if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
432 {
433 hlptim->Instance->CCMR1 = 0;
434 }
435
436 /* Clear flag */
437 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
438
439 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, 0);
440 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
441 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
442 {
443 return HAL_TIMEOUT;
444 }
445
446 if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
447 {
448 /* Clear flag */
449 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
450
451 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, 0);
452 /* Wait for the completion of the write operation to the LPTIM_CCR2 register */
453 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) == HAL_TIMEOUT)
454 {
455 return HAL_TIMEOUT;
456 }
457 }
458
459 if (IS_LPTIM_CC3_INSTANCE(hlptim->Instance))
460 {
461 hlptim->Instance->CCMR2 = 0;
462
463 /* Clear flag */
464 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP3OK);
465
466 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_3, 0);
467 /* Wait for the completion of the write operation to the LPTIM_CCR3 register */
468 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP3OK) == HAL_TIMEOUT)
469 {
470 return HAL_TIMEOUT;
471 }
472 }
473
474 if (IS_LPTIM_CC4_INSTANCE(hlptim->Instance))
475 {
476 hlptim->Instance->CCMR2 = 0;
477
478 /* Clear flag */
479 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP4OK);
480
481 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_4, 0);
482 /* Wait for the completion of the write operation to the LPTIM_CCR4 register */
483 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP4OK) == HAL_TIMEOUT)
484 {
485 return HAL_TIMEOUT;
486 }
487 }
488
489 /* Clear flag */
490 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
491
492 __HAL_LPTIM_AUTORELOAD_SET(hlptim, 0);
493
494 /* Wait for the completion of the write operation to the LPTIM_ARR register */
495 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
496 {
497 return HAL_TIMEOUT;
498 }
499
500 /* Disable the LPTIM Peripheral Clock */
501 __HAL_LPTIM_DISABLE(hlptim);
502
503 hlptim->Instance->CFGR = 0;
504 hlptim->Instance->CFGR2 = 0;
505
506 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
507 if (hlptim->MspDeInitCallback == NULL)
508 {
509 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
510 }
511
512 /* DeInit the low level hardware: CLOCK, NVIC.*/
513 hlptim->MspDeInitCallback(hlptim);
514 #else
515 /* DeInit the low level hardware: CLOCK, NVIC.*/
516 HAL_LPTIM_MspDeInit(hlptim);
517 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
518
519 /* Change the LPTIM channels state */
520 LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_RESET);
521
522 /* Change the LPTIM state */
523 hlptim->State = HAL_LPTIM_STATE_RESET;
524
525 /* Release Lock */
526 __HAL_UNLOCK(hlptim);
527
528 /* Return function status */
529 return HAL_OK;
530 }
531
532 /**
533 * @brief Initialize the LPTIM MSP.
534 * @param hlptim LPTIM handle
535 * @retval None
536 */
HAL_LPTIM_MspInit(LPTIM_HandleTypeDef * hlptim)537 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
538 {
539 /* Prevent unused argument(s) compilation warning */
540 UNUSED(hlptim);
541
542 /* NOTE : This function should not be modified, when the callback is needed,
543 the HAL_LPTIM_MspInit could be implemented in the user file
544 */
545 }
546
547 /**
548 * @brief DeInitialize LPTIM MSP.
549 * @param hlptim LPTIM handle
550 * @retval None
551 */
HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef * hlptim)552 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
553 {
554 /* Prevent unused argument(s) compilation warning */
555 UNUSED(hlptim);
556
557 /* NOTE : This function should not be modified, when the callback is needed,
558 the HAL_LPTIM_MspDeInit could be implemented in the user file
559 */
560 }
561
562 /**
563 * @}
564 */
565
566 /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
567 * @brief Start-Stop operation functions.
568 *
569 @verbatim
570 ==============================================================================
571 ##### LPTIM Start Stop operation functions #####
572 ==============================================================================
573 [..] This section provides functions allowing to:
574 (+) Start the PWM mode.
575 (+) Stop the PWM mode.
576 (+) Start the One pulse mode.
577 (+) Stop the One pulse mode.
578 (+) Start the Set once mode.
579 (+) Stop the Set once mode.
580 (+) Start the Encoder mode.
581 (+) Stop the Encoder mode.
582 (+) Start the Timeout mode.
583 (+) Stop the Timeout mode.
584 (+) Start the Counter mode.
585 (+) Stop the Counter mode.
586
587
588 @endverbatim
589 * @{
590 */
591
592 /**
593 * @brief Start the LPTIM PWM generation.
594 * @param hlptim LPTIM handle
595 * @param Channel LPTIM Channel to be enabled
596 * This parameter can be one of the following values:
597 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
598 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
599 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
600 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
601 * @retval HAL status
602 */
HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)603 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
604 {
605 /* Check the parameters */
606 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
607
608 /* Check LPTIM channel state */
609 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
610 {
611 return HAL_ERROR;
612 }
613
614 /* Set the LPTIM state */
615 hlptim->State = HAL_LPTIM_STATE_BUSY;
616
617 /* Set the LPTIM channel state */
618 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
619
620 /* Reset WAVE bit to set PWM mode */
621 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
622
623 /* Enable the Peripheral */
624 __HAL_LPTIM_ENABLE(hlptim);
625
626 /* Enable LPTIM signal on the corresponding output pin */
627 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
628
629 /* Start timer in continuous mode */
630 __HAL_LPTIM_START_CONTINUOUS(hlptim);
631
632 /* Change the LPTIM state */
633 hlptim->State = HAL_LPTIM_STATE_READY;
634
635 /* Return function status */
636 return HAL_OK;
637 }
638
639 /**
640 * @brief Stop the LPTIM PWM generation.
641 * @param hlptim LPTIM handle
642 * @param Channel LPTIM Channel to be disabled
643 * This parameter can be one of the following values:
644 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
645 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
646 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
647 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
648 * @retval HAL status
649 */
HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)650 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
651 {
652 /* Check the parameters */
653 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
654
655 /* Change the LPTIM state */
656 hlptim->State = HAL_LPTIM_STATE_BUSY;
657
658 /* Disable LPTIM signal from the corresponding output pin */
659 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
660
661 /* Disable the Peripheral */
662 __HAL_LPTIM_DISABLE(hlptim);
663
664 /* Set the LPTIM channel state */
665 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
666
667 /* Set the LPTIM state */
668 hlptim->State = HAL_LPTIM_STATE_READY;
669
670 /* Return function status */
671 return HAL_OK;
672 }
673
674 /**
675 * @brief Start the LPTIM PWM generation in interrupt mode.
676 * @param hlptim LPTIM handle
677 * @param Channel LPTIM Channel to be enabled
678 * This parameter can be one of the following values:
679 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
680 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
681 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
682 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
683 * @retval HAL status
684 */
HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)685 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
686 {
687 /* Check the parameters */
688 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
689
690 /* Check LPTIM channel state */
691 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
692 {
693 return HAL_ERROR;
694 }
695
696 /* Set the LPTIM state */
697 hlptim->State = HAL_LPTIM_STATE_BUSY;
698
699 /* Set the LPTIM channel state */
700 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
701
702 /* Reset WAVE bit to set PWM mode */
703 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
704
705 /* Enable the Peripheral */
706 __HAL_LPTIM_ENABLE(hlptim);
707 /* Clear flag */
708 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
709
710 switch (Channel)
711 {
712 case LPTIM_CHANNEL_1:
713 /* Enable interrupt */
714 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
715 LPTIM_IT_UPDATE);
716 break;
717 case LPTIM_CHANNEL_2:
718 /* Enable interrupt */
719 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
720 LPTIM_IT_UPDATE);
721 break;
722 case LPTIM_CHANNEL_3:
723 /* Enable interrupt */
724 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP3OK | LPTIM_IT_CC3 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
725 LPTIM_IT_UPDATE);
726 break;
727 case LPTIM_CHANNEL_4:
728 /* Enable interrupt */
729 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP4OK | LPTIM_IT_CC4 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
730 LPTIM_IT_UPDATE);
731 break;
732 default:
733 break;
734 }
735
736 /* Wait for the completion of the write operation to the LPTIM_DIER register */
737 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
738 {
739 return HAL_TIMEOUT;
740 }
741
742 /* If external trigger source is used, then enable external trigger interrupt */
743 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
744 {
745 /* Clear flag */
746 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
747
748 /* Enable external trigger interrupt */
749 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
750
751 /* Wait for the completion of the write operation to the LPTIM_DIER register */
752 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
753 {
754 return HAL_TIMEOUT;
755 }
756 }
757
758 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
759
760 /* Start timer in continuous mode */
761 __HAL_LPTIM_START_CONTINUOUS(hlptim);
762
763 /* Change the LPTIM state */
764 hlptim->State = HAL_LPTIM_STATE_READY;
765
766 /* Return function status */
767 return HAL_OK;
768 }
769
770 /**
771 * @brief Stop the LPTIM PWM generation in interrupt mode.
772 * @param hlptim LPTIM handle
773 * @param Channel LPTIM Channel to be disabled
774 * This parameter can be one of the following values:
775 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
776 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
777 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
778 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
779 * @retval HAL status
780 */
HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)781 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
782 {
783 /* Check the parameters */
784 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
785
786 /* Change the LPTIM state */
787 hlptim->State = HAL_LPTIM_STATE_BUSY;
788
789 /* Disable LPTIM signal from the corresponding output pin */
790 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
791
792 /* Disable the Peripheral */
793 __HAL_LPTIM_DISABLE(hlptim);
794
795 /* Enable the Peripheral */
796 __HAL_LPTIM_ENABLE(hlptim);
797
798 /* Clear flag */
799 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
800
801 switch (Channel)
802 {
803 case LPTIM_CHANNEL_1:
804 /* Disable interrupt */
805 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
806 LPTIM_IT_UPDATE);
807 break;
808 case LPTIM_CHANNEL_2:
809 /* Disable interrupt */
810 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
811 LPTIM_IT_UPDATE);
812 break;
813 case LPTIM_CHANNEL_3:
814 /* Disable interrupt */
815 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP3OK | LPTIM_IT_CC3 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
816 LPTIM_IT_UPDATE);
817 break;
818 case LPTIM_CHANNEL_4:
819 /* Disable interrupt */
820 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP4OK | LPTIM_IT_CC4 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
821 LPTIM_IT_UPDATE);
822 break;
823 default:
824 break;
825 }
826
827 /* Wait for the completion of the write operation to the LPTIM_DIER register */
828 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
829 {
830 return HAL_TIMEOUT;
831 }
832
833 /* If external trigger source is used, then enable external trigger interrupt */
834 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
835 {
836 /* Clear flag */
837 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
838
839 /* Enable external trigger interrupt */
840 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
841
842 /* Wait for the completion of the write operation to the LPTIM_DIER register */
843 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
844 {
845 return HAL_TIMEOUT;
846 }
847 }
848
849 /* Disable the Peripheral */
850 __HAL_LPTIM_DISABLE(hlptim);
851
852 /* Set the LPTIM channel state */
853 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
854
855 /* Set the LPTIM state */
856 hlptim->State = HAL_LPTIM_STATE_READY;
857
858 /* Return function status */
859 return HAL_OK;
860 }
861
862 /**
863 * @brief Start the LPTIM PWM generation in DMA mode.
864 * @param hlptim LPTIM handle
865 * @param Channel LPTIM Channel to be enabled
866 * This parameter can be one of the following values:
867 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
868 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
869 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
870 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
871 * @param pData The destination Buffer address
872 * @param Length The length of data to be transferred from LPTIM peripheral to memory
873 * @retval HAL status
874 */
HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel,const uint32_t * pData,uint32_t Length)875 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, const uint32_t *pData,
876 uint32_t Length)
877 {
878 DMA_HandleTypeDef *hdma;
879
880 /* Check the parameters */
881 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
882 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
883
884 if ((pData == NULL) || (Length == 0U))
885 {
886 return HAL_ERROR;
887 }
888
889 /* Check LPTIM channel state */
890 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
891 {
892 return HAL_ERROR;
893 }
894
895 /* Set the LPTIM state */
896 hlptim->State = HAL_LPTIM_STATE_BUSY;
897
898 /* Set the LPTIM channel state */
899 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
900
901 /* Reset WAVE bit to set PWM mode */
902 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
903
904 /* Enable the Peripheral */
905 __HAL_LPTIM_ENABLE(hlptim);
906
907 /* Enable update event DMA request */
908 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
909
910 /* Wait for the completion of the write operation to the LPTIM_DIER register */
911 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
912 {
913 return HAL_TIMEOUT;
914 }
915
916 switch (Channel)
917 {
918 case LPTIM_CHANNEL_1:
919 /* Set the DMA update event callbacks */
920 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
921 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
922
923 /* Set the DMA error callback */
924 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
925
926 /* Enable the DMA Channel */
927 hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
928 if (HAL_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR1, Length) != HAL_OK)
929 {
930 /* Return error status */
931 return HAL_ERROR;
932 }
933 break;
934 case LPTIM_CHANNEL_2:
935 /* Set the DMA update event callbacks */
936 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
937 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
938
939 /* Set the DMA error callback */
940 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
941
942 /* Enable the DMA Channel */
943 hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
944 if (HAL_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR2, Length) != HAL_OK)
945 {
946 /* Return error status */
947 return HAL_ERROR;
948 }
949 break;
950 case LPTIM_CHANNEL_3:
951 /* Set the DMA update event callbacks */
952 hlptim->hdma[LPTIM_DMA_ID_CC3]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
953 hlptim->hdma[LPTIM_DMA_ID_CC3]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
954
955 /* Set the DMA error callback */
956 hlptim->hdma[LPTIM_DMA_ID_CC3]->XferErrorCallback = LPTIM_DMAError;
957
958 /* Enable the DMA Channel */
959 hdma = hlptim->hdma[LPTIM_DMA_ID_CC3];
960 if (HAL_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR3, Length) != HAL_OK)
961 {
962 /* Return error status */
963 return HAL_ERROR;
964 }
965 break;
966 case LPTIM_CHANNEL_4:
967 /* Set the DMA update event callbacks */
968 hlptim->hdma[LPTIM_DMA_ID_CC4]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
969 hlptim->hdma[LPTIM_DMA_ID_CC4]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
970
971 /* Set the DMA error callback */
972 hlptim->hdma[LPTIM_DMA_ID_CC4]->XferErrorCallback = LPTIM_DMAError;
973
974 /* Enable the DMA Channel */
975 hdma = hlptim->hdma[LPTIM_DMA_ID_CC4];
976 if (HAL_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR4, Length) != HAL_OK)
977 {
978 /* Return error status */
979 return HAL_ERROR;
980 }
981 break;
982 default:
983 break;
984 }
985
986 /* Enable LPTIM signal on the corresponding output pin */
987 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
988
989 /* Start timer in continuous mode */
990 __HAL_LPTIM_START_CONTINUOUS(hlptim);
991
992 /* Change the LPTIM state */
993 hlptim->State = HAL_LPTIM_STATE_READY;
994
995 /* Return function status */
996 return HAL_OK;
997 }
998
999 /**
1000 * @brief Stop the LPTIM PWM generation in DMA mode.
1001 * @param hlptim LPTIM handle
1002 * @param Channel LPTIM Channel to be disabled
1003 * This parameter can be one of the following values:
1004 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1005 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1006 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
1007 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
1008 * @retval HAL status
1009 */
HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1010 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1011 {
1012 /* Check the parameters */
1013 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
1014 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1015
1016 /* Change the LPTIM state */
1017 hlptim->State = HAL_LPTIM_STATE_BUSY;
1018
1019 /* Disable update event DMA request */
1020 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
1021
1022 switch (Channel)
1023 {
1024 case LPTIM_CHANNEL_1:
1025 /* Disable update event DMA request */
1026 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
1027 break;
1028 case LPTIM_CHANNEL_2:
1029 /* Disable update event DMA request */
1030 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
1031 break;
1032 case LPTIM_CHANNEL_3:
1033 /* Disable update event DMA request */
1034 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC3]);
1035 break;
1036 case LPTIM_CHANNEL_4:
1037 /* Disable update event DMA request */
1038 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC4]);
1039 break;
1040 default:
1041 break;
1042 }
1043
1044 /* Disable LPTIM signal from the corresponding output pin */
1045 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1046
1047 /* Disable the Peripheral */
1048 __HAL_LPTIM_DISABLE(hlptim);
1049
1050 /* Set the LPTIM channel state */
1051 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1052
1053 /* Set the LPTIM state */
1054 hlptim->State = HAL_LPTIM_STATE_READY;
1055
1056 /* Return function status */
1057 return HAL_OK;
1058 }
1059
1060 /**
1061 * @brief Start the LPTIM One pulse generation.
1062 * @param hlptim LPTIM handle
1063 * @param Channel LPTIM Channel to be enabled
1064 * This parameter can be one of the following values:
1065 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1066 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1067 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
1068 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
1069 * @retval HAL status
1070 */
HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1071 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1072 {
1073 /* Check the parameters */
1074 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1075
1076 /* Check LPTIM channel state */
1077 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1078 {
1079 return HAL_ERROR;
1080 }
1081
1082 /* Set the LPTIM state */
1083 hlptim->State = HAL_LPTIM_STATE_BUSY;
1084
1085 /* Set the LPTIM channel state */
1086 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1087
1088 /* Reset WAVE bit to set one pulse mode */
1089 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
1090
1091 /* Enable the Peripheral */
1092 __HAL_LPTIM_ENABLE(hlptim);
1093
1094 /* Enable LPTIM signal on the corresponding output pin */
1095 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1096
1097 /* Start timer in single (one shot) mode */
1098 __HAL_LPTIM_START_SINGLE(hlptim);
1099
1100 /* Change the LPTIM state */
1101 hlptim->State = HAL_LPTIM_STATE_READY;
1102
1103 /* Return function status */
1104 return HAL_OK;
1105 }
1106
1107 /**
1108 * @brief Stop the LPTIM One pulse generation.
1109 * @param hlptim LPTIM handle
1110 * @param Channel LPTIM Channel to be disabled
1111 * This parameter can be one of the following values:
1112 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1113 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1114 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
1115 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
1116 * @retval HAL status
1117 */
HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1118 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1119 {
1120 /* Check the parameters */
1121 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1122
1123 /* Set the LPTIM state */
1124 hlptim->State = HAL_LPTIM_STATE_BUSY;
1125
1126 /* Disable LPTIM signal on the corresponding output pin */
1127 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1128
1129 /* Disable the Peripheral */
1130 __HAL_LPTIM_DISABLE(hlptim);
1131
1132 /* Set the LPTIM channel state */
1133 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1134
1135 /* Set the LPTIM state */
1136 hlptim->State = HAL_LPTIM_STATE_READY;
1137
1138 /* Return function status */
1139 return HAL_OK;
1140 }
1141
1142 /**
1143 * @brief Start the LPTIM One pulse generation in interrupt mode.
1144 * @param hlptim LPTIM handle
1145 * @param Channel LPTIM Channel to be enabled
1146 * This parameter can be one of the following values:
1147 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1148 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1149 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
1150 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
1151 * @retval HAL status
1152 */
HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1153 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1154 {
1155 /* Check the parameters */
1156 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1157
1158 /* Check LPTIM channel state */
1159 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1160 {
1161 return HAL_ERROR;
1162 }
1163
1164 /* Set the LPTIM state */
1165 hlptim->State = HAL_LPTIM_STATE_BUSY;
1166
1167 /* Set the LPTIM channel state */
1168 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1169
1170 /* Reset WAVE bit to set one pulse mode */
1171 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
1172
1173 /* Enable the Peripheral */
1174 __HAL_LPTIM_ENABLE(hlptim);
1175
1176 /* Clear flag */
1177 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1178
1179 switch (Channel)
1180 {
1181 case LPTIM_CHANNEL_1:
1182 /* Enable interrupt */
1183 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1184 LPTIM_IT_UPDATE);
1185 break;
1186 case LPTIM_CHANNEL_2:
1187 /* Enable interrupt */
1188 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1189 LPTIM_IT_UPDATE);
1190 break;
1191 case LPTIM_CHANNEL_3:
1192 /* Enable interrupt */
1193 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP3OK | LPTIM_IT_CC3 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1194 LPTIM_IT_UPDATE);
1195 break;
1196 case LPTIM_CHANNEL_4:
1197 /* Enable interrupt */
1198 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP4OK | LPTIM_IT_CC4 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1199 LPTIM_IT_UPDATE);
1200 break;
1201 default:
1202 break;
1203 }
1204
1205 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1206 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1207 {
1208 return HAL_TIMEOUT;
1209 }
1210
1211 /* If external trigger source is used, then enable external trigger interrupt */
1212 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1213 {
1214 /* Clear flag */
1215 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1216 /* Enable external trigger interrupt */
1217 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1218 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1219 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1220 {
1221 return HAL_TIMEOUT;
1222 }
1223 }
1224
1225 /* Enable LPTIM signal on the corresponding output pin */
1226 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1227
1228 /* Start timer in single (one shot) mode */
1229 __HAL_LPTIM_START_SINGLE(hlptim);
1230
1231 /* Change the LPTIM state */
1232 hlptim->State = HAL_LPTIM_STATE_READY;
1233
1234 /* Return function status */
1235 return HAL_OK;
1236 }
1237
1238 /**
1239 * @brief Stop the LPTIM One pulse generation in interrupt mode.
1240 * @param hlptim LPTIM handle
1241 * @param Channel LPTIM Channel to be disabled
1242 * This parameter can be one of the following values:
1243 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1244 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1245 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
1246 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
1247 * @retval HAL status
1248 */
HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1249 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1250 {
1251 /* Check the parameters */
1252 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1253
1254 /* Set the LPTIM state */
1255 hlptim->State = HAL_LPTIM_STATE_BUSY;
1256
1257 /* Disable LPTIM signal on the corresponding output pin */
1258 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1259
1260 /* Disable the Peripheral */
1261 __HAL_LPTIM_DISABLE(hlptim);
1262
1263
1264 /* Enable the Peripheral */
1265 __HAL_LPTIM_ENABLE(hlptim);
1266
1267 /* Clear flag */
1268 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1269
1270 switch (Channel)
1271 {
1272 case LPTIM_CHANNEL_1:
1273 /* Disable interrupt */
1274 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1275 LPTIM_IT_UPDATE);
1276 break;
1277 case LPTIM_CHANNEL_2:
1278 /* Disable interrupt */
1279 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1280 LPTIM_IT_UPDATE);
1281 break;
1282 case LPTIM_CHANNEL_3:
1283 /* Disable interrupt */
1284 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP3OK | LPTIM_IT_CC3 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1285 LPTIM_IT_UPDATE);
1286 break;
1287 case LPTIM_CHANNEL_4:
1288 /* Disable interrupt */
1289 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP4OK | LPTIM_IT_CC4 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1290 LPTIM_IT_UPDATE);
1291 break;
1292 default:
1293 break;
1294 }
1295
1296 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1297 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1298 {
1299 return HAL_TIMEOUT;
1300 }
1301
1302 /* If external trigger source is used, then enable external trigger interrupt */
1303 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1304 {
1305 /* Clear flag */
1306 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1307 /* Enable external trigger interrupt */
1308 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1309 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1310 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1311 {
1312 return HAL_TIMEOUT;
1313 }
1314 }
1315
1316 /* Disable the Peripheral */
1317 __HAL_LPTIM_DISABLE(hlptim);
1318
1319 /* Set the LPTIM channel state */
1320 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1321
1322 /* Set the LPTIM state */
1323 hlptim->State = HAL_LPTIM_STATE_READY;
1324
1325 /* Return function status */
1326 return HAL_OK;
1327 }
1328
1329 /**
1330 * @brief Start the LPTIM in Set once mode.
1331 * @param hlptim LPTIM handle
1332 * @param Channel LPTIM Channel to be enabled
1333 * This parameter can be one of the following values:
1334 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1335 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1336 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
1337 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
1338 * @retval HAL status
1339 */
HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1340 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1341 {
1342 /* Check the parameters */
1343 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1344
1345 /* Check LPTIM channel state */
1346 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1347 {
1348 return HAL_ERROR;
1349 }
1350
1351 /* Set the LPTIM state */
1352 hlptim->State = HAL_LPTIM_STATE_BUSY;
1353
1354 /* Set the LPTIM channel state */
1355 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1356
1357 /* Set WAVE bit to enable the set once mode */
1358 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
1359
1360 /* Enable the Peripheral */
1361 __HAL_LPTIM_ENABLE(hlptim);
1362
1363 /* Enable LPTIM signal on the corresponding output pin */
1364 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1365
1366 /* Start timer in single (one shot) mode */
1367 __HAL_LPTIM_START_SINGLE(hlptim);
1368
1369 /* Change the LPTIM state */
1370 hlptim->State = HAL_LPTIM_STATE_READY;
1371
1372 /* Return function status */
1373 return HAL_OK;
1374 }
1375
1376 /**
1377 * @brief Stop the LPTIM Set once mode.
1378 * @param hlptim LPTIM handle
1379 * @param Channel LPTIM Channel to be disabled
1380 * This parameter can be one of the following values:
1381 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1382 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1383 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
1384 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
1385 * @retval HAL status
1386 */
HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1387 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1388 {
1389 /* Check the parameters */
1390 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1391
1392 /* Set the LPTIM state */
1393 hlptim->State = HAL_LPTIM_STATE_BUSY;
1394
1395 /* Disable LPTIM signal on the corresponding output pin */
1396 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1397
1398 /* Disable the Peripheral */
1399 __HAL_LPTIM_DISABLE(hlptim);
1400
1401 /* Set the LPTIM channel state */
1402 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1403
1404 /* Set the LPTIM state */
1405 hlptim->State = HAL_LPTIM_STATE_READY;
1406
1407 /* Return function status */
1408 return HAL_OK;
1409 }
1410
1411 /**
1412 * @brief Start the LPTIM Set once mode in interrupt mode.
1413 * @param hlptim LPTIM handle
1414 * @param Channel LPTIM Channel to be enabled
1415 * This parameter can be one of the following values:
1416 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1417 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1418 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
1419 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
1420 * @retval HAL status
1421 */
HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1422 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1423 {
1424 /* Check the parameters */
1425 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1426
1427 /* Check LPTIM channel state */
1428 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1429 {
1430 return HAL_ERROR;
1431 }
1432
1433 /* Set the LPTIM state */
1434 hlptim->State = HAL_LPTIM_STATE_BUSY;
1435
1436 /* Set the LPTIM channel state */
1437 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1438
1439 /* Set WAVE bit to enable the set once mode */
1440 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
1441
1442 /* Enable the Peripheral */
1443 __HAL_LPTIM_ENABLE(hlptim);
1444
1445 /* Clear flag */
1446 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1447
1448 switch (Channel)
1449 {
1450 case LPTIM_CHANNEL_1:
1451 /* Enable interrupt */
1452 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
1453 break;
1454 case LPTIM_CHANNEL_2:
1455 /* Enable interrupt */
1456 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
1457 break;
1458 case LPTIM_CHANNEL_3:
1459 /* Enable interrupt */
1460 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP3OK | LPTIM_IT_CC3 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
1461 break;
1462 case LPTIM_CHANNEL_4:
1463 /* Enable interrupt */
1464 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP4OK | LPTIM_IT_CC4 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
1465 break;
1466 default:
1467 break;
1468 }
1469
1470 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1471 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1472 {
1473 return HAL_TIMEOUT;
1474 }
1475
1476 /* If external trigger source is used, then enable external trigger interrupt */
1477 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1478 {
1479 /* Clear flag */
1480 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1481 /* Enable external trigger interrupt */
1482 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1483 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1484 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1485 {
1486 return HAL_TIMEOUT;
1487 }
1488 }
1489
1490 /* Enable LPTIM signal on the corresponding output pin */
1491 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1492
1493 /* Start timer in single (one shot) mode */
1494 __HAL_LPTIM_START_SINGLE(hlptim);
1495
1496 /* Change the LPTIM state */
1497 hlptim->State = HAL_LPTIM_STATE_READY;
1498
1499 /* Return function status */
1500 return HAL_OK;
1501 }
1502
1503 /**
1504 * @brief Stop the LPTIM Set once mode in interrupt mode.
1505 * @param hlptim LPTIM handle
1506 * @param Channel LPTIM Channel to be disabled
1507 * This parameter can be one of the following values:
1508 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1509 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1510 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
1511 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
1512 * @retval HAL status
1513 */
HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1514 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1515 {
1516 /* Check the parameters */
1517 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1518
1519 /* Set the LPTIM state */
1520 hlptim->State = HAL_LPTIM_STATE_BUSY;
1521
1522 /* Disable LPTIM signal on the corresponding output pin */
1523 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1524
1525 /* Disable the Peripheral */
1526 __HAL_LPTIM_DISABLE(hlptim);
1527
1528 /* Enable the Peripheral */
1529 __HAL_LPTIM_ENABLE(hlptim);
1530
1531 /* Clear flag */
1532 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1533
1534 switch (Channel)
1535 {
1536 case LPTIM_CHANNEL_1:
1537 /* Disable interrupt */
1538 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
1539 break;
1540 case LPTIM_CHANNEL_2:
1541 /* Disable interrupt */
1542 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
1543 break;
1544 case LPTIM_CHANNEL_3:
1545 /* Disable interrupt */
1546 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP3OK | LPTIM_IT_CC3 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
1547 break;
1548 case LPTIM_CHANNEL_4:
1549 /* Disable interrupt */
1550 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP4OK | LPTIM_IT_CC4 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
1551 break;
1552 default:
1553 break;
1554 }
1555
1556 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1557 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1558 {
1559 return HAL_TIMEOUT;
1560 }
1561
1562 /* If external trigger source is used, then enable external trigger interrupt */
1563 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1564 {
1565 /* Clear flag */
1566 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1567 /* Enable external trigger interrupt */
1568 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1569
1570 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1571 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1572 {
1573 return HAL_TIMEOUT;
1574 }
1575 }
1576
1577 /* Disable the Peripheral */
1578 __HAL_LPTIM_DISABLE(hlptim);
1579
1580 /* Set the LPTIM channel state */
1581 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1582
1583 /* Set the LPTIM state */
1584 hlptim->State = HAL_LPTIM_STATE_READY;
1585
1586 /* Return function status */
1587 return HAL_OK;
1588 }
1589
1590 /**
1591 * @brief Start the Encoder interface.
1592 * @param hlptim LPTIM handle
1593 * @retval HAL status
1594 */
HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef * hlptim)1595 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim)
1596 {
1597 uint32_t tmpcfgr;
1598
1599 /* Check the parameters */
1600 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1601 assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
1602 assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
1603 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
1604
1605 /* Set the LPTIM state */
1606 hlptim->State = HAL_LPTIM_STATE_BUSY;
1607
1608 /* Get the LPTIMx CFGR value */
1609 tmpcfgr = hlptim->Instance->CFGR;
1610
1611 /* Clear CKPOL bits */
1612 tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
1613
1614 /* Set Input polarity */
1615 tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
1616
1617 /* Write to LPTIMx CFGR */
1618 hlptim->Instance->CFGR = tmpcfgr;
1619
1620 /* Set ENC bit to enable the encoder interface */
1621 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
1622
1623 /* Enable the Peripheral */
1624 __HAL_LPTIM_ENABLE(hlptim);
1625
1626 /* Start timer in continuous mode */
1627 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1628
1629 /* Change the LPTIM state */
1630 hlptim->State = HAL_LPTIM_STATE_READY;
1631
1632 /* Return function status */
1633 return HAL_OK;
1634 }
1635
1636 /**
1637 * @brief Stop the Encoder interface.
1638 * @param hlptim LPTIM handle
1639 * @retval HAL status
1640 */
HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef * hlptim)1641 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
1642 {
1643 /* Check the parameters */
1644 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1645
1646 /* Set the LPTIM state */
1647 hlptim->State = HAL_LPTIM_STATE_BUSY;
1648
1649 /* Disable the Peripheral */
1650 __HAL_LPTIM_DISABLE(hlptim);
1651
1652 /* Reset ENC bit to disable the encoder interface */
1653 hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
1654
1655 /* Change the LPTIM state */
1656 hlptim->State = HAL_LPTIM_STATE_READY;
1657
1658 /* Return function status */
1659 return HAL_OK;
1660 }
1661
1662 /**
1663 * @brief Start the Encoder interface in interrupt mode.
1664 * @param hlptim LPTIM handle
1665 * @retval HAL status
1666 */
HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef * hlptim)1667 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim)
1668 {
1669 uint32_t tmpcfgr;
1670
1671 /* Check the parameters */
1672 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1673 assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
1674 assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
1675 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
1676
1677 /* Set the LPTIM state */
1678 hlptim->State = HAL_LPTIM_STATE_BUSY;
1679
1680 /* Configure edge sensitivity for encoder mode */
1681 /* Get the LPTIMx CFGR value */
1682 tmpcfgr = hlptim->Instance->CFGR;
1683
1684 /* Clear CKPOL bits */
1685 tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
1686
1687 /* Set Input polarity */
1688 tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
1689
1690 /* Write to LPTIMx CFGR */
1691 hlptim->Instance->CFGR = tmpcfgr;
1692
1693 /* Set ENC bit to enable the encoder interface */
1694 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
1695
1696 /* Enable the Peripheral */
1697 __HAL_LPTIM_ENABLE(hlptim);
1698
1699 /* Clear flag */
1700 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1701
1702 /* Enable "switch to up/down direction" interrupt */
1703 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
1704
1705 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1706 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1707 {
1708 return HAL_TIMEOUT;
1709 }
1710
1711
1712 /* Start timer in continuous mode */
1713 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1714
1715 /* Change the LPTIM state */
1716 hlptim->State = HAL_LPTIM_STATE_READY;
1717
1718 /* Return function status */
1719 return HAL_OK;
1720 }
1721
1722 /**
1723 * @brief Stop the Encoder interface in interrupt mode.
1724 * @param hlptim LPTIM handle
1725 * @retval HAL status
1726 */
HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef * hlptim)1727 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1728 {
1729 /* Check the parameters */
1730 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1731
1732 /* Set the LPTIM state */
1733 hlptim->State = HAL_LPTIM_STATE_BUSY;
1734
1735 /* Disable the Peripheral */
1736 __HAL_LPTIM_DISABLE(hlptim);
1737
1738 /* Reset ENC bit to disable the encoder interface */
1739 hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
1740 /* Enable the Peripheral */
1741 __HAL_LPTIM_ENABLE(hlptim);
1742
1743 /* Clear flag */
1744 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1745
1746 /* Disable "switch to down/up direction" interrupt */
1747 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
1748
1749 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1750 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1751 {
1752 return HAL_TIMEOUT;
1753 }
1754
1755 /* Disable the Peripheral */
1756 __HAL_LPTIM_DISABLE(hlptim);
1757
1758 /* Change the LPTIM state */
1759 hlptim->State = HAL_LPTIM_STATE_READY;
1760
1761 /* Return function status */
1762 return HAL_OK;
1763 }
1764
1765 /**
1766 * @brief Start the Timeout function.
1767 * @note The first trigger event will start the timer, any successive
1768 * trigger event will reset the counter and the timer restarts.
1769 * @param hlptim LPTIM handle
1770 * @param Timeout Specifies the TimeOut value to reset the counter.
1771 * This parameter must be a value between 0x0000 and 0xFFFF.
1772 * @retval HAL status
1773 */
HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Timeout)1774 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
1775 {
1776 /* Check the parameters */
1777 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1778 assert_param(IS_LPTIM_PULSE(Timeout));
1779
1780 /* Set the LPTIM state */
1781 hlptim->State = HAL_LPTIM_STATE_BUSY;
1782
1783 /* Set TIMOUT bit to enable the timeout function */
1784 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
1785
1786 /* Enable the Peripheral */
1787 __HAL_LPTIM_ENABLE(hlptim);
1788
1789 /* Clear flag */
1790 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
1791
1792 /* Load the Timeout value in the compare register */
1793 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
1794
1795 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
1796 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
1797 {
1798 return HAL_TIMEOUT;
1799 }
1800
1801 /* Start timer in continuous mode */
1802 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1803
1804 /* Change the LPTIM state */
1805 hlptim->State = HAL_LPTIM_STATE_READY;
1806
1807 /* Return function status */
1808 return HAL_OK;
1809 }
1810
1811 /**
1812 * @brief Stop the Timeout function.
1813 * @param hlptim LPTIM handle
1814 * @retval HAL status
1815 */
HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef * hlptim)1816 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
1817 {
1818 /* Check the parameters */
1819 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1820
1821 /* Set the LPTIM state */
1822 hlptim->State = HAL_LPTIM_STATE_BUSY;
1823
1824 /* Disable the Peripheral */
1825 __HAL_LPTIM_DISABLE(hlptim);
1826
1827 /* Reset TIMOUT bit to enable the timeout function */
1828 hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
1829
1830 /* Change the LPTIM state */
1831 hlptim->State = HAL_LPTIM_STATE_READY;
1832
1833 /* Return function status */
1834 return HAL_OK;
1835 }
1836
1837 /**
1838 * @brief Start the Timeout function in interrupt mode.
1839 * @note The first trigger event will start the timer, any successive
1840 * trigger event will reset the counter and the timer restarts.
1841 * @param hlptim LPTIM handle
1842 * @param Timeout Specifies the TimeOut value to reset the counter.
1843 * This parameter must be a value between 0x0000 and 0xFFFF.
1844 * @retval HAL status
1845 */
HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Timeout)1846 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
1847 {
1848 /* Check the parameters */
1849 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1850 assert_param(IS_LPTIM_PULSE(Timeout));
1851
1852 /* Set the LPTIM state */
1853 hlptim->State = HAL_LPTIM_STATE_BUSY;
1854
1855 /* Set TIMOUT bit to enable the timeout function */
1856 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
1857
1858 /* Enable the Peripheral */
1859 __HAL_LPTIM_ENABLE(hlptim);
1860
1861 /* Clear flag */
1862 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1863
1864 /* Enable Compare match CH1 interrupt */
1865 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
1866
1867 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1868 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1869 {
1870 return HAL_TIMEOUT;
1871 }
1872
1873 /* Clear flag */
1874 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
1875
1876 /* Load the Timeout value in the compare register */
1877 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
1878
1879 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
1880 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
1881 {
1882 return HAL_TIMEOUT;
1883 }
1884
1885 /* Start timer in continuous mode */
1886 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1887
1888 /* Change the LPTIM state */
1889 hlptim->State = HAL_LPTIM_STATE_READY;
1890
1891 /* Return function status */
1892 return HAL_OK;
1893 }
1894
1895 /**
1896 * @brief Stop the Timeout function in interrupt mode.
1897 * @param hlptim LPTIM handle
1898 * @retval HAL status
1899 */
HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef * hlptim)1900 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1901 {
1902 /* Check the parameters */
1903 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1904
1905 /* Set the LPTIM state */
1906 hlptim->State = HAL_LPTIM_STATE_BUSY;
1907
1908 /* Disable the Peripheral */
1909 __HAL_LPTIM_DISABLE(hlptim);
1910
1911 /* Reset TIMOUT bit to enable the timeout function */
1912 hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
1913
1914 /* Enable the Peripheral */
1915 __HAL_LPTIM_ENABLE(hlptim);
1916
1917 /* Clear flag */
1918 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1919
1920 /* Disable Compare match CH1 interrupt */
1921 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
1922
1923 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1924 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1925 {
1926 return HAL_TIMEOUT;
1927 }
1928
1929 /* Disable the Peripheral */
1930 __HAL_LPTIM_DISABLE(hlptim);
1931
1932 /* Change the LPTIM state */
1933 hlptim->State = HAL_LPTIM_STATE_READY;
1934
1935 /* Return function status */
1936 return HAL_OK;
1937 }
1938
1939 /**
1940 * @brief Start the Counter mode.
1941 * @param hlptim LPTIM handle
1942 * @retval HAL status
1943 */
HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef * hlptim)1944 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim)
1945 {
1946 /* Check the parameters */
1947 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1948
1949 /* Set the LPTIM state */
1950 hlptim->State = HAL_LPTIM_STATE_BUSY;
1951
1952 /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
1953 if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
1954 && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
1955 {
1956 /* Check if clock is prescaled */
1957 assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
1958 /* Set clock prescaler to 0 */
1959 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
1960 }
1961
1962 /* Enable the Peripheral */
1963 __HAL_LPTIM_ENABLE(hlptim);
1964
1965 /* Start timer in continuous mode */
1966 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1967
1968 /* Change the LPTIM state */
1969 hlptim->State = HAL_LPTIM_STATE_READY;
1970
1971 /* Return function status */
1972 return HAL_OK;
1973 }
1974
1975 /**
1976 * @brief Stop the Counter mode.
1977 * @param hlptim LPTIM handle
1978 * @retval HAL status
1979 */
HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef * hlptim)1980 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
1981 {
1982 /* Check the parameters */
1983 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1984
1985 /* Set the LPTIM state */
1986 hlptim->State = HAL_LPTIM_STATE_BUSY;
1987
1988 /* Disable the Peripheral */
1989 __HAL_LPTIM_DISABLE(hlptim);
1990
1991 /* Change the LPTIM state */
1992 hlptim->State = HAL_LPTIM_STATE_READY;
1993
1994 /* Return function status */
1995 return HAL_OK;
1996 }
1997
1998 /**
1999 * @brief Start the Counter mode in interrupt mode.
2000 * @param hlptim LPTIM handle
2001 * @retval HAL status
2002 */
HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef * hlptim)2003 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim)
2004 {
2005 /* Check the parameters */
2006 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
2007
2008 /* Set the LPTIM state */
2009 hlptim->State = HAL_LPTIM_STATE_BUSY;
2010
2011 /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
2012 if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
2013 && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
2014 {
2015 /* Check if clock is prescaled */
2016 assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
2017 /* Set clock prescaler to 0 */
2018 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
2019 }
2020
2021 /* Enable the Peripheral */
2022 __HAL_LPTIM_ENABLE(hlptim);
2023
2024 /* Clear flag */
2025 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
2026
2027 /* Enable interrupt */
2028 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
2029
2030 /* Wait for the completion of the write operation to the LPTIM_DIER register */
2031 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
2032 {
2033 return HAL_TIMEOUT;
2034 }
2035
2036 /* Start timer in continuous mode */
2037 __HAL_LPTIM_START_CONTINUOUS(hlptim);
2038
2039 /* Change the LPTIM state */
2040 hlptim->State = HAL_LPTIM_STATE_READY;
2041
2042 /* Return function status */
2043 return HAL_OK;
2044 }
2045
2046 /**
2047 * @brief Stop the Counter mode in interrupt mode.
2048 * @param hlptim LPTIM handle
2049 * @retval HAL status
2050 */
HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef * hlptim)2051 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
2052 {
2053 /* Check the parameters */
2054 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
2055
2056 /* Set the LPTIM state */
2057 hlptim->State = HAL_LPTIM_STATE_BUSY;
2058
2059 /* Disable the Peripheral */
2060 __HAL_LPTIM_DISABLE(hlptim);
2061
2062
2063 /* Enable the Peripheral */
2064 __HAL_LPTIM_ENABLE(hlptim);
2065
2066 /* Clear flag */
2067 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
2068
2069 /* Disable interrupt */
2070 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
2071
2072 /* Wait for the completion of the write operation to the LPTIM_DIER register */
2073 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
2074 {
2075 return HAL_TIMEOUT;
2076 }
2077
2078 /* Disable the Peripheral */
2079 __HAL_LPTIM_DISABLE(hlptim);
2080
2081 /* Change the LPTIM state */
2082 hlptim->State = HAL_LPTIM_STATE_READY;
2083
2084 /* Return function status */
2085 return HAL_OK;
2086 }
2087
2088 /**
2089 * @brief Starts the LPTIM Input Capture measurement.
2090 * @param hlptim LPTIM Input Capture handle
2091 * @param Channel LPTIM Channels to be enabled
2092 * This parameter can be one of the following values:
2093 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2094 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2095 * @arg LPTIM_CHANNEL_3: TIM Channel 3 selected
2096 * @arg LPTIM_CHANNEL_4: TIM Channel 4 selected
2097 * @retval HAL status
2098 */
HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2099 HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2100 {
2101 /* Check the parameters */
2102 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
2103 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2104
2105 /* Check LPTIM channel state */
2106 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
2107 {
2108 return HAL_ERROR;
2109 }
2110
2111 /* Set the LPTIM state */
2112 hlptim->State = HAL_LPTIM_STATE_BUSY;
2113
2114 /* Set the LPTIM channel state */
2115 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
2116
2117 /* Enable the Peripheral */
2118 __HAL_LPTIM_ENABLE(hlptim);
2119
2120 /* Start timer in continuous mode */
2121 __HAL_LPTIM_START_CONTINUOUS(hlptim);
2122
2123 /* Enable capture */
2124 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
2125
2126 /* Change the LPTIM state */
2127 hlptim->State = HAL_LPTIM_STATE_READY;
2128
2129 /* Return function status */
2130 return HAL_OK;
2131 }
2132
2133 /**
2134 * @brief Stops the LPTIM Input Capture measurement.
2135 * @param hlptim LPTIM Input Capture handle
2136 * @param Channel LPTIM Channels to be disabled
2137 * This parameter can be one of the following values:
2138 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2139 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2140 * @arg LPTIM_CHANNEL_3: TIM Channel 3 selected
2141 * @arg LPTIM_CHANNEL_4: TIM Channel 4 selected
2142 * @retval HAL status
2143 */
HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2144 HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2145 {
2146 /* Check the parameters */
2147 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
2148 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2149
2150 /* Set the LPTIM state */
2151 hlptim->State = HAL_LPTIM_STATE_BUSY;
2152
2153 /* Disable capture */
2154 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
2155
2156 /* Disable the Peripheral */
2157 __HAL_LPTIM_DISABLE(hlptim);
2158
2159 /* Set the LPTIM channel state */
2160 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
2161
2162 /* Set the LPTIM state */
2163 hlptim->State = HAL_LPTIM_STATE_READY;
2164
2165 /* Return function status */
2166 return HAL_OK;
2167 }
2168
2169 /**
2170 * @brief Starts the LPTIM Input Capture measurement in interrupt mode.
2171 * @param hlptim LPTIM Input Capture handle
2172 * @param Channel LPTIM Channels to be enabled
2173 * This parameter can be one of the following values:
2174 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2175 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2176 * @arg LPTIM_CHANNEL_3: TIM Channel 3 selected
2177 * @arg LPTIM_CHANNEL_4: TIM Channel 4 selected
2178 * @retval HAL status
2179 */
HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2180 HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2181 {
2182 /* Check the parameters */
2183 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
2184 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2185
2186 /* Check LPTIM channel state */
2187 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
2188 {
2189 return HAL_ERROR;
2190 }
2191
2192 /* Set the LPTIM state */
2193 hlptim->State = HAL_LPTIM_STATE_BUSY;
2194
2195 /* Set the LPTIM channel state */
2196 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
2197
2198 /* Enable the Peripheral */
2199 __HAL_LPTIM_ENABLE(hlptim);
2200
2201 switch (Channel)
2202 {
2203 case LPTIM_CHANNEL_1:
2204 /* Enable Capture/Compare 1 interrupt */
2205 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
2206 break;
2207 case LPTIM_CHANNEL_2:
2208 /* Disable Capture/Compare 2 interrupt */
2209 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC2);
2210 break;
2211 case LPTIM_CHANNEL_3:
2212 /* Enable Capture/Compare 3 interrupt */
2213 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC3);
2214 break;
2215 case LPTIM_CHANNEL_4:
2216 /* Disable Capture/Compare 4 interrupt */
2217 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC4);
2218 break;
2219 default:
2220 break;
2221 }
2222
2223 /* Wait for the completion of the write operation to the LPTIM_DIER register */
2224 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
2225 {
2226 return HAL_TIMEOUT;
2227 }
2228
2229 /* Start timer in continuous mode */
2230 __HAL_LPTIM_START_CONTINUOUS(hlptim);
2231
2232 /* Enable capture */
2233 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
2234
2235 /* Set the LPTIM state */
2236 hlptim->State = HAL_LPTIM_STATE_READY;
2237
2238 /* Return function status */
2239 return HAL_OK;
2240 }
2241
2242 /**
2243 * @brief Stops the LPTIM Input Capture measurement in interrupt mode.
2244 * @param hlptim LPTIM Input Capture handle
2245 * @param Channel LPTIM Channels to be disabled
2246 * This parameter can be one of the following values:
2247 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2248 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2249 * @arg LPTIM_CHANNEL_3: TIM Channel 3 selected
2250 * @arg LPTIM_CHANNEL_4: TIM Channel 4 selected
2251 * @retval HAL status
2252 */
HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2253 HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2254 {
2255 HAL_StatusTypeDef status = HAL_OK;
2256
2257 /* Check the parameters */
2258 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
2259 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2260
2261 /* Set the LPTIM state */
2262 hlptim->State = HAL_LPTIM_STATE_BUSY;
2263
2264 switch (Channel)
2265 {
2266 case LPTIM_CHANNEL_1:
2267 /* Disable Capture/Compare 1 interrupt */
2268 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
2269 break;
2270 case LPTIM_CHANNEL_2:
2271 /* Disable Capture/Compare 2 interrupt */
2272 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC2);
2273 break;
2274 case LPTIM_CHANNEL_3:
2275 /* Disable Capture/Compare 3 interrupt */
2276 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC3);
2277 break;
2278 case LPTIM_CHANNEL_4:
2279 /* Disable Capture/Compare 4 interrupt */
2280 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC4);
2281 break;
2282 default:
2283 status = HAL_ERROR;
2284 break;
2285 }
2286
2287 if (status != HAL_ERROR)
2288 {
2289 /* Disable capture */
2290 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
2291
2292 /* Disable the Peripheral */
2293 __HAL_LPTIM_DISABLE(hlptim);
2294
2295 /* Set the LPTIM channel state */
2296 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
2297
2298 /* Set the LPTIM state */
2299 hlptim->State = HAL_LPTIM_STATE_READY;
2300 }
2301
2302 /* Return function status */
2303 return status;
2304 }
2305
2306 /**
2307 * @brief Starts the LPTIM Input Capture measurement in DMA mode.
2308 * @param hlptim LPTIM Input Capture handle
2309 * @param Channel LPTIM Channels to be enabled
2310 * This parameter can be one of the following values:
2311 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2312 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2313 * @arg LPTIM_CHANNEL_3: TIM Channel 3 selected
2314 * @arg LPTIM_CHANNEL_4: TIM Channel 4 selected
2315 * @param pData The destination Buffer address
2316 * @param Length The length of data to be transferred from LPTIM peripheral to memory
2317 * @retval HAL status
2318 */
HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel,uint32_t * pData,uint32_t Length)2319 HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData,
2320 uint32_t Length)
2321 {
2322 DMA_HandleTypeDef *hdma;
2323
2324 /* Check the parameters */
2325 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
2326 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2327
2328 if ((pData == NULL) || (Length == 0U))
2329 {
2330 return HAL_ERROR;
2331 }
2332
2333 /* Check LPTIM channel state */
2334 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
2335 {
2336 return HAL_ERROR;
2337 }
2338
2339 /* Set the LPTIM state */
2340 hlptim->State = HAL_LPTIM_STATE_BUSY;
2341
2342 /* Set the LPTIM channel state */
2343 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
2344
2345 /* Enable the Peripheral */
2346 __HAL_LPTIM_ENABLE(hlptim);
2347
2348 switch (Channel)
2349 {
2350 case LPTIM_CHANNEL_1:
2351 /* Set the DMA capture callbacks */
2352 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMACaptureCplt;
2353 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
2354
2355 /* Set the DMA error callback */
2356 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
2357
2358 /* Enable the DMA Channel */
2359 hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
2360 if (HAL_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
2361 {
2362 /* Return error status */
2363 return HAL_ERROR;
2364 }
2365
2366 /* Enable Capture/Compare 1 DMA request */
2367 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC1);
2368 break;
2369
2370 case LPTIM_CHANNEL_2:
2371 /* Set the DMA capture callbacks */
2372 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMACaptureCplt;
2373 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
2374
2375 /* Set the DMA error callback */
2376 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
2377
2378 /* Enable the DMA Channel */
2379 hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
2380 if (HAL_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
2381 {
2382 /* Return error status */
2383 return HAL_ERROR;
2384 }
2385
2386 /* Enable Capture/Compare 2 DMA request */
2387 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC2);
2388 break;
2389 case LPTIM_CHANNEL_3:
2390 /* Set the DMA capture callbacks */
2391 hlptim->hdma[LPTIM_DMA_ID_CC3]->XferCpltCallback = LPTIM_DMACaptureCplt;
2392 hlptim->hdma[LPTIM_DMA_ID_CC3]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
2393
2394 /* Set the DMA error callback */
2395 hlptim->hdma[LPTIM_DMA_ID_CC3]->XferErrorCallback = LPTIM_DMAError;
2396
2397 /* Enable the DMA Channel */
2398 hdma = hlptim->hdma[LPTIM_DMA_ID_CC3];
2399 if ((HAL_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR3, (uint32_t)pData, Length)) != HAL_OK)
2400 {
2401 /* Return error status */
2402 return HAL_ERROR;
2403 }
2404
2405 /* Enable Capture/Compare 3 DMA request */
2406 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC3);
2407 break;
2408
2409 case LPTIM_CHANNEL_4:
2410 /* Set the DMA capture callbacks */
2411 hlptim->hdma[LPTIM_DMA_ID_CC4]->XferCpltCallback = LPTIM_DMACaptureCplt;
2412 hlptim->hdma[LPTIM_DMA_ID_CC4]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
2413
2414 /* Set the DMA error callback */
2415 hlptim->hdma[LPTIM_DMA_ID_CC4]->XferErrorCallback = LPTIM_DMAError;
2416
2417 /* Enable the DMA Channel */
2418 hdma = hlptim->hdma[LPTIM_DMA_ID_CC4];
2419 if (HAL_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
2420 {
2421 /* Return error status */
2422 return HAL_ERROR;
2423 }
2424
2425 /* Enable Capture/Compare 4 DMA request */
2426 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC4);
2427 break;
2428
2429 default:
2430 break;
2431 }
2432
2433 /* Wait for the completion of the write operation to the LPTIM_DIER register */
2434 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
2435 {
2436 return HAL_TIMEOUT;
2437 }
2438
2439 /* Start timer in continuous mode */
2440 __HAL_LPTIM_START_CONTINUOUS(hlptim);
2441
2442 /* Enable capture */
2443 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
2444
2445 /* Set the LPTIM state */
2446 hlptim->State = HAL_LPTIM_STATE_READY;
2447
2448 /* Return function status */
2449 return HAL_OK;
2450 }
2451
2452 /**
2453 * @brief Stops the LPTIM Input Capture measurement in DMA mode.
2454 * @param hlptim LPTIM Input Capture handle
2455 * @param Channel LPTIM Channels to be disabled
2456 * This parameter can be one of the following values:
2457 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2458 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2459 * @arg LPTIM_CHANNEL_3: TIM Channel 3 selected
2460 * @arg LPTIM_CHANNEL_4: TIM Channel 4 selected
2461 * @retval HAL status
2462 */
HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2463 HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2464 {
2465 HAL_StatusTypeDef status = HAL_OK;
2466
2467 /* Check the parameters */
2468 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
2469 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2470
2471 /* Set the LPTIM state */
2472 hlptim->State = HAL_LPTIM_STATE_BUSY;
2473
2474 switch (Channel)
2475 {
2476 case LPTIM_CHANNEL_1:
2477 /* Disable Capture/Compare 1 DMA request */
2478 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC1);
2479 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
2480 break;
2481
2482 case LPTIM_CHANNEL_2:
2483 /* Disable Capture/Compare 2 DMA request */
2484 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC2);
2485 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
2486 break;
2487
2488 case LPTIM_CHANNEL_3:
2489 /* Disable Capture/Compare 3 DMA request */
2490 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC3);
2491 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC3]);
2492 break;
2493
2494 case LPTIM_CHANNEL_4:
2495 /* Disable Capture/Compare 4 DMA request */
2496 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC4);
2497 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC4]);
2498 break;
2499 default:
2500 status = HAL_ERROR;
2501 break;
2502 }
2503
2504 if (status != HAL_ERROR)
2505 {
2506 /* Disable capture */
2507 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
2508
2509 /* Disable the Peripheral */
2510 __HAL_LPTIM_DISABLE(hlptim);
2511
2512 /* Set the LPTIM channel state */
2513 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
2514
2515 /* Set the LPTIM state */
2516 hlptim->State = HAL_LPTIM_STATE_READY;
2517 }
2518
2519 /* Return function status */
2520 return status;
2521 }
2522 /**
2523 * @}
2524 */
2525
2526 /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
2527 * @brief Read operation functions.
2528 *
2529 @verbatim
2530 ==============================================================================
2531 ##### LPTIM Read operation functions #####
2532 ==============================================================================
2533 [..] This section provides LPTIM Reading functions.
2534 (+) Read the counter value.
2535 (+) Read the period (Auto-reload) value.
2536 (+) Read the pulse (Compare)value.
2537 @endverbatim
2538 * @{
2539 */
2540
2541 /**
2542 * @brief Return the current counter value.
2543 * @param hlptim LPTIM handle
2544 * @retval Counter value.
2545 */
HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef * hlptim)2546 uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim)
2547 {
2548 /* Check the parameters */
2549 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
2550
2551 return (hlptim->Instance->CNT);
2552 }
2553
2554 /**
2555 * @brief Return the current Autoreload (Period) value.
2556 * @param hlptim LPTIM handle
2557 * @retval Autoreload value.
2558 */
HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef * hlptim)2559 uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim)
2560 {
2561 /* Check the parameters */
2562 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
2563
2564 return (hlptim->Instance->ARR);
2565 }
2566
2567 /**
2568 * @brief Return the current Compare (Pulse) value.
2569 * @param hlptim LPTIM handle
2570 * @param Channel LPTIM Channel to be selected
2571 * This parameter can be one of the following values:
2572 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2573 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2574 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
2575 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
2576 * @retval Compare value.
2577 */
HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2578 uint32_t HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2579 {
2580 uint32_t tmpccr;
2581
2582 /* Check the parameters */
2583 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2584
2585 switch (Channel)
2586 {
2587 case LPTIM_CHANNEL_1:
2588 tmpccr = hlptim->Instance->CCR1;
2589 break;
2590 case LPTIM_CHANNEL_2:
2591 tmpccr = hlptim->Instance->CCR2;
2592 break;
2593 case LPTIM_CHANNEL_3:
2594 tmpccr = hlptim->Instance->CCR3;
2595 break;
2596 case LPTIM_CHANNEL_4:
2597 tmpccr = hlptim->Instance->CCR4;
2598 break;
2599 default:
2600 tmpccr = 0;
2601 break;
2602 }
2603 return tmpccr;
2604 }
2605
2606 /**
2607 * @brief LPTimer Input Capture Get Offset(in counter step unit)
2608 * @note The real capture value corresponding to the input capture trigger can be calculated using
2609 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
2610 * The Offset value is depending on the glitch filter value for the channel
2611 * and the value of the prescaler for the kernel clock.
2612 * Please check Errata Sheet V1_8 for more details under "variable latency
2613 * on input capture channel" section.
2614 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
2615 * the configuration information for LPTIM module.
2616 * @param Channel This parameter can be one of the following values:
2617 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2618 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2619 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
2620 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
2621 * @retval The offset value
2622 */
HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2623 uint8_t HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2624 {
2625
2626 uint8_t offset ;
2627 uint32_t prescaler;
2628 uint32_t filter ;
2629
2630 /* Get prescaler value */
2631 prescaler = LL_LPTIM_GetPrescaler(hlptim->Instance);
2632
2633 /* Get filter value */
2634 filter = LL_LPTIM_IC_GetFilter(hlptim->Instance, Channel);
2635
2636 /* Get offset value */
2637 offset = LL_LPTIM_IC_GET_OFFSET(prescaler, filter);
2638
2639 /* return offset value */
2640 return offset;
2641 }
2642
2643 /**
2644 * @}
2645 */
2646 /** @defgroup LPTIM_Exported_Functions_Group5 LPTIM Config function
2647 * @brief Config channel
2648 *
2649 @verbatim
2650 ==============================================================================
2651 ##### LPTIM Config function #####
2652 ==============================================================================
2653 [..] This section provides LPTIM Config function.
2654 (+) Configure channel: Output Compare mode, Period, Polarity.
2655 @endverbatim
2656 * @{
2657 */
2658
2659 /**
2660 * @brief
2661 * @param hlptim LPTIM handle
2662 * @param sConfig The output configuration structure
2663 * @param Channel LPTIM Channel to be configured
2664 * This parameter can be one of the following values:
2665 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2666 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2667 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
2668 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
2669 * @note Successive calls to HAL_LPTIM_OC_ConfigChannel can only be performed
2670 * after a delay that must be greater or equal than the value of
2671 * (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal
2672 * division factor (1, 2, 4, ..., 128). Any successive call violating
2673 * this delay, leads to unpredictable results.
2674 * @retval HAL status
2675 */
HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig,uint32_t Channel)2676 HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig,
2677 uint32_t Channel)
2678 {
2679 HAL_StatusTypeDef status;
2680 /* Check the parameters */
2681 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2682 assert_param(IS_LPTIM_OC_POLARITY(sConfig->OCPolarity));
2683 assert_param(IS_LPTIM_PULSE(sConfig->Pulse));
2684
2685 hlptim->State = HAL_LPTIM_STATE_BUSY;
2686
2687 switch (Channel)
2688 {
2689 case LPTIM_CHANNEL_1:
2690 {
2691 /* Check the parameters */
2692 assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
2693
2694 /* Configure the LPTIM Channel 1 in Output Compare */
2695 status = LPTIM_OC1_SetConfig(hlptim, sConfig);
2696 if (status != HAL_OK)
2697 {
2698 return status;
2699 }
2700 break;
2701 }
2702 case LPTIM_CHANNEL_2:
2703 {
2704 /* Check the parameters */
2705 assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
2706
2707 /* Configure the LPTIM Channel 2 in Output Compare */
2708 status = LPTIM_OC2_SetConfig(hlptim, sConfig);
2709 if (status != HAL_OK)
2710 {
2711 return status;
2712 }
2713 break;
2714 }
2715
2716 case LPTIM_CHANNEL_3:
2717 {
2718 /* Check the parameters */
2719 assert_param(IS_LPTIM_CC3_INSTANCE(hlptim->Instance));
2720
2721 /* Configure the LPTIM Channel 3 in Output Compare */
2722 status = LPTIM_OC3_SetConfig(hlptim, sConfig);
2723 if (status != HAL_OK)
2724 {
2725 return status;
2726 }
2727 break;
2728 }
2729 case LPTIM_CHANNEL_4:
2730 {
2731 /* Check the parameters */
2732 assert_param(IS_LPTIM_CC4_INSTANCE(hlptim->Instance));
2733
2734 /* Configure the LPTIM Channel 4 in Output Compare */
2735 status = LPTIM_OC4_SetConfig(hlptim, sConfig);
2736 if (status != HAL_OK)
2737 {
2738 return status;
2739 }
2740 break;
2741 }
2742 default:
2743 break;
2744 }
2745
2746 /* Change the LPTIM state */
2747 hlptim->State = HAL_LPTIM_STATE_READY;
2748
2749 /* Return function status */
2750 return HAL_OK;
2751 }
2752
2753 /**
2754 * @brief
2755 * @param hlptim LPTIM handle
2756 * @param sConfig The input configuration structure
2757 * @param Channel LPTIM Channel to be configured
2758 * This parameter can be one of the following values:
2759 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2760 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2761 * @arg LPTIM_CHANNEL_3: LPTIM Channel 3 selected
2762 * @arg LPTIM_CHANNEL_4: LPTIM Channel 4 selected
2763 * @note Successive calls to HAL_LPTIM_IC_ConfigChannel can only be performed
2764 * after a delay that must be greater or equal than the value of
2765 * (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal
2766 * division factor (1, 2, 4, ..., 128). Any successive call violating
2767 * this delay, leads to unpredictable results.
2768 * @retval HAL status
2769 */
HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig,uint32_t Channel)2770 HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig,
2771 uint32_t Channel)
2772 {
2773 /* Check the parameters */
2774 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2775 assert_param(IS_LPTIM_IC_PRESCALER(sConfig->ICPrescaler));
2776 assert_param(IS_LPTIM_IC_POLARITY(sConfig->ICPolarity));
2777 assert_param(IS_LPTIM_IC_FILTER(sConfig->ICFilter));
2778
2779 hlptim->State = HAL_LPTIM_STATE_BUSY;
2780
2781 switch (Channel)
2782 {
2783 case LPTIM_CHANNEL_1:
2784 {
2785 /* Check the parameters */
2786 assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
2787 assert_param(IS_LPTIM_IC1_SOURCE(hlptim->Instance, sConfig->ICInputSource));
2788
2789 /* Configure the LPTIM Channel 1 in Input Capture */
2790 LPTIM_IC1_SetConfig(hlptim, sConfig);
2791 break;
2792 }
2793 case LPTIM_CHANNEL_2:
2794 {
2795 /* Check the parameters */
2796 assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
2797 assert_param(IS_LPTIM_IC2_SOURCE(hlptim->Instance, sConfig->ICInputSource));
2798
2799 /* Configure the LPTIM Channel 2 in Input Capture */
2800 LPTIM_IC2_SetConfig(hlptim, sConfig);
2801 break;
2802 }
2803 case LPTIM_CHANNEL_3:
2804 {
2805 /* Check the parameters */
2806 assert_param(IS_LPTIM_CC3_INSTANCE(hlptim->Instance));
2807 assert_param(IS_LPTIM_IC3_SOURCE(hlptim->Instance, sConfig->ICInputSource));
2808
2809 /* Configure the LPTIM Channel 3 in Input Capture */
2810 LPTIM_IC3_SetConfig(hlptim, sConfig);
2811 break;
2812 }
2813 case LPTIM_CHANNEL_4:
2814 {
2815 /* Check the parameters */
2816 assert_param(IS_LPTIM_CC4_INSTANCE(hlptim->Instance));
2817 assert_param(IS_LPTIM_IC4_SOURCE(hlptim->Instance, sConfig->ICInputSource));
2818
2819 /* Configure the LPTIM Channel 4 in Input Capture */
2820 LPTIM_IC4_SetConfig(hlptim, sConfig);
2821 break;
2822 }
2823 default:
2824 break;
2825 }
2826
2827 /* Change the LPTIM state */
2828 hlptim->State = HAL_LPTIM_STATE_READY;
2829 /* Return function status */
2830 return HAL_OK;
2831 }
2832 /**
2833 * @}
2834 */
2835
2836 /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
2837 * @brief LPTIM IRQ handler.
2838 *
2839 @verbatim
2840 ==============================================================================
2841 ##### LPTIM IRQ handler and callbacks #####
2842 ==============================================================================
2843 [..] This section provides LPTIM IRQ handler and callback functions called within
2844 the IRQ handler:
2845 (+) LPTIM interrupt request handler
2846 (+) Compare match Callback
2847 (+) Auto-reload match Callback
2848 (+) External trigger event detection Callback
2849 (+) Compare register write complete Callback
2850 (+) Auto-reload register write complete Callback
2851 (+) Up-counting direction change Callback
2852 (+) Down-counting direction change Callback
2853
2854 @endverbatim
2855 * @{
2856 */
2857
2858 /**
2859 * @brief Handle LPTIM interrupt request.
2860 * @param hlptim LPTIM handle
2861 * @retval None
2862 */
HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef * hlptim)2863 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
2864 {
2865 /* Capture Compare 1 interrupt */
2866 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1) != RESET)
2867 {
2868 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1) != RESET)
2869 {
2870 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1);
2871 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
2872
2873 /* Input capture event */
2874 if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC1SEL) != 0x00U)
2875 {
2876 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2877 hlptim->IC_CaptureCallback(hlptim);
2878 #else
2879 HAL_LPTIM_IC_CaptureCallback(hlptim);
2880 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2881 }
2882 /* Output compare event */
2883 else
2884 {
2885 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2886 hlptim->CompareMatchCallback(hlptim);
2887 #else
2888 HAL_LPTIM_CompareMatchCallback(hlptim);
2889 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2890 }
2891 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2892 }
2893 }
2894
2895 /* Capture Compare 2 interrupt */
2896 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2) != RESET)
2897 {
2898 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2) != RESET)
2899 {
2900 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2);
2901 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
2902
2903 /* Input capture event */
2904 if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC2SEL) != 0x00U)
2905 {
2906 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2907 hlptim->IC_CaptureCallback(hlptim);
2908 #else
2909 HAL_LPTIM_IC_CaptureCallback(hlptim);
2910 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2911 }
2912 /* Output compare event */
2913 else
2914 {
2915 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2916 hlptim->CompareMatchCallback(hlptim);
2917 #else
2918 HAL_LPTIM_CompareMatchCallback(hlptim);
2919 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2920 }
2921 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2922 }
2923 }
2924
2925 /* Capture Compare 3 interrupt */
2926 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC3) != RESET)
2927 {
2928 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC3) != RESET)
2929 {
2930 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC3);
2931 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_3;
2932
2933 /* Input capture event */
2934 if ((hlptim->Instance->CCMR2 & LPTIM_CCMR2_CC3SEL) != 0x00U)
2935 {
2936 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2937 hlptim->IC_CaptureCallback(hlptim);
2938 #else
2939 HAL_LPTIM_IC_CaptureCallback(hlptim);
2940 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2941 }
2942 /* Output compare event */
2943 else
2944 {
2945 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2946 hlptim->CompareMatchCallback(hlptim);
2947 #else
2948 HAL_LPTIM_CompareMatchCallback(hlptim);
2949 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2950 }
2951 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2952 }
2953 }
2954
2955 /* Capture Compare 4 interrupt */
2956 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC4) != RESET)
2957 {
2958 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC4) != RESET)
2959 {
2960 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC4);
2961 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_4;
2962
2963 /* Input capture event */
2964 if ((hlptim->Instance->CCMR2 & LPTIM_CCMR2_CC4SEL) != 0x00U)
2965 {
2966 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2967 hlptim->IC_CaptureCallback(hlptim);
2968 #else
2969 HAL_LPTIM_IC_CaptureCallback(hlptim);
2970 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2971 }
2972 /* Output compare event */
2973 else
2974 {
2975 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2976 hlptim->CompareMatchCallback(hlptim);
2977 #else
2978 HAL_LPTIM_CompareMatchCallback(hlptim);
2979 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2980 }
2981 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2982 }
2983 }
2984
2985 /* Over Capture 1 interrupt */
2986 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1O) != RESET)
2987 {
2988 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1O) != RESET)
2989 {
2990 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1O);
2991 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
2992
2993 /* Over capture event */
2994 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2995 hlptim->IC_OverCaptureCallback(hlptim);
2996 #else
2997 HAL_LPTIM_IC_OverCaptureCallback(hlptim);
2998 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2999 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3000 }
3001 }
3002
3003 /* Over Capture 2 interrupt */
3004 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2O) != RESET)
3005 {
3006 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2O) != RESET)
3007 {
3008 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2O);
3009 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3010
3011 /* Over capture event */
3012 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3013 hlptim->IC_OverCaptureCallback(hlptim);
3014 #else
3015 HAL_LPTIM_IC_OverCaptureCallback(hlptim);
3016 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3017 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3018 }
3019 }
3020
3021 /* Over Capture 3 interrupt */
3022 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC3O) != RESET)
3023 {
3024 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC3O) != RESET)
3025 {
3026 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC3O);
3027 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_3;
3028
3029 /* Over capture event */
3030 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3031 hlptim->IC_OverCaptureCallback(hlptim);
3032 #else
3033 HAL_LPTIM_IC_OverCaptureCallback(hlptim);
3034 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3035 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3036 }
3037 }
3038
3039 /* Over Capture 4 interrupt */
3040 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC4O) != RESET)
3041 {
3042 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC4O) != RESET)
3043 {
3044 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC4O);
3045 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_4;
3046
3047 /* Over capture event */
3048 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3049 hlptim->IC_OverCaptureCallback(hlptim);
3050 #else
3051 HAL_LPTIM_IC_OverCaptureCallback(hlptim);
3052 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3053 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3054 }
3055 }
3056
3057 /* Autoreload match interrupt */
3058 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
3059 {
3060 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
3061 {
3062 /* Clear Autoreload match flag */
3063 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
3064
3065 /* Autoreload match Callback */
3066 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3067 hlptim->AutoReloadMatchCallback(hlptim);
3068 #else
3069 HAL_LPTIM_AutoReloadMatchCallback(hlptim);
3070 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3071 }
3072 }
3073
3074 /* Trigger detected interrupt */
3075 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
3076 {
3077 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
3078 {
3079 /* Clear Trigger detected flag */
3080 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
3081
3082 /* Trigger detected callback */
3083 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3084 hlptim->TriggerCallback(hlptim);
3085 #else
3086 HAL_LPTIM_TriggerCallback(hlptim);
3087 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3088 }
3089 }
3090
3091 /* Compare write interrupt */
3092 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP1OK) != RESET)
3093 {
3094 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP1OK) != RESET)
3095 {
3096 /* Clear Compare write flag */
3097 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
3098 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3099 /* Compare write Callback */
3100 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3101 hlptim->CompareWriteCallback(hlptim);
3102 #else
3103 HAL_LPTIM_CompareWriteCallback(hlptim);
3104 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3105 }
3106 }
3107
3108 /* Compare write interrupt */
3109 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP2OK) != RESET)
3110 {
3111 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP2OK) != RESET)
3112 {
3113 /* Clear Compare write flag */
3114 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
3115 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3116 /* Compare write Callback */
3117 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3118 hlptim->CompareWriteCallback(hlptim);
3119 #else
3120 HAL_LPTIM_CompareWriteCallback(hlptim);
3121 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3122 }
3123 }
3124
3125 /* Autoreload write interrupt */
3126 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
3127 {
3128 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
3129 {
3130 /* Clear Autoreload write flag */
3131 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
3132
3133 /* Autoreload write Callback */
3134 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3135 hlptim->AutoReloadWriteCallback(hlptim);
3136 #else
3137 HAL_LPTIM_AutoReloadWriteCallback(hlptim);
3138 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3139 }
3140 }
3141
3142 /* Direction counter changed from Down to Up interrupt */
3143 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
3144 {
3145 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
3146 {
3147 /* Clear Direction counter changed from Down to Up flag */
3148 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
3149
3150 /* Direction counter changed from Down to Up Callback */
3151 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3152 hlptim->DirectionUpCallback(hlptim);
3153 #else
3154 HAL_LPTIM_DirectionUpCallback(hlptim);
3155 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3156 }
3157 }
3158
3159 /* Direction counter changed from Up to Down interrupt */
3160 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
3161 {
3162 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
3163 {
3164 /* Clear Direction counter changed from Up to Down flag */
3165 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
3166
3167 /* Direction counter changed from Up to Down Callback */
3168 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3169 hlptim->DirectionDownCallback(hlptim);
3170 #else
3171 HAL_LPTIM_DirectionDownCallback(hlptim);
3172 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3173 }
3174 }
3175
3176 /* Repetition counter underflowed (or contains zero) and the LPTIM counter
3177 overflowed */
3178 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UPDATE) != RESET)
3179 {
3180 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UPDATE) != RESET)
3181 {
3182 /* Clear update event flag */
3183 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UPDATE);
3184
3185 /* Update event Callback */
3186 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3187 hlptim->UpdateEventCallback(hlptim);
3188 #else
3189 HAL_LPTIM_UpdateEventCallback(hlptim);
3190 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3191 }
3192 }
3193
3194 /* Successful APB bus write to repetition counter register */
3195 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK) != RESET)
3196 {
3197 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK) != RESET)
3198 {
3199 /* Clear successful APB bus write to repetition counter flag */
3200 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
3201
3202 /* Successful APB bus write to repetition counter Callback */
3203 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3204 hlptim->RepCounterWriteCallback(hlptim);
3205 #else
3206 HAL_LPTIM_RepCounterWriteCallback(hlptim);
3207 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3208 }
3209 }
3210 }
3211
3212 /**
3213 * @brief Compare match callback in non-blocking mode.
3214 * @param hlptim LPTIM handle
3215 * @retval None
3216 */
HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef * hlptim)3217 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
3218 {
3219 /* Prevent unused argument(s) compilation warning */
3220 UNUSED(hlptim);
3221
3222 /* NOTE : This function should not be modified, when the callback is needed,
3223 the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
3224 */
3225 }
3226
3227 /**
3228 * @brief Autoreload match callback in non-blocking mode.
3229 * @param hlptim LPTIM handle
3230 * @retval None
3231 */
HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef * hlptim)3232 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
3233 {
3234 /* Prevent unused argument(s) compilation warning */
3235 UNUSED(hlptim);
3236
3237 /* NOTE : This function should not be modified, when the callback is needed,
3238 the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
3239 */
3240 }
3241
3242 /**
3243 * @brief Trigger detected callback in non-blocking mode.
3244 * @param hlptim LPTIM handle
3245 * @retval None
3246 */
HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef * hlptim)3247 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
3248 {
3249 /* Prevent unused argument(s) compilation warning */
3250 UNUSED(hlptim);
3251
3252 /* NOTE : This function should not be modified, when the callback is needed,
3253 the HAL_LPTIM_TriggerCallback could be implemented in the user file
3254 */
3255 }
3256
3257 /**
3258 * @brief Compare write callback in non-blocking mode.
3259 * @param hlptim LPTIM handle
3260 * @retval None
3261 */
HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef * hlptim)3262 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
3263 {
3264 /* Prevent unused argument(s) compilation warning */
3265 UNUSED(hlptim);
3266
3267 /* NOTE : This function should not be modified, when the callback is needed,
3268 the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
3269 */
3270 }
3271
3272 /**
3273 * @brief Autoreload write callback in non-blocking mode.
3274 * @param hlptim LPTIM handle
3275 * @retval None
3276 */
HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef * hlptim)3277 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
3278 {
3279 /* Prevent unused argument(s) compilation warning */
3280 UNUSED(hlptim);
3281
3282 /* NOTE : This function should not be modified, when the callback is needed,
3283 the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
3284 */
3285 }
3286
3287 /**
3288 * @brief Direction counter changed from Down to Up callback in non-blocking mode.
3289 * @param hlptim LPTIM handle
3290 * @retval None
3291 */
HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef * hlptim)3292 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
3293 {
3294 /* Prevent unused argument(s) compilation warning */
3295 UNUSED(hlptim);
3296
3297 /* NOTE : This function should not be modified, when the callback is needed,
3298 the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
3299 */
3300 }
3301
3302 /**
3303 * @brief Direction counter changed from Up to Down callback in non-blocking mode.
3304 * @param hlptim LPTIM handle
3305 * @retval None
3306 */
HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef * hlptim)3307 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
3308 {
3309 /* Prevent unused argument(s) compilation warning */
3310 UNUSED(hlptim);
3311
3312 /* NOTE : This function should not be modified, when the callback is needed,
3313 the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
3314 */
3315 }
3316
3317 /**
3318 * @brief Repetition counter underflowed (or contains zero) and LPTIM counter overflowed callback in non-blocking mode.
3319 * @param hlptim LPTIM handle
3320 * @retval None
3321 */
HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef * hlptim)3322 __weak void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim)
3323 {
3324 /* Prevent unused argument(s) compilation warning */
3325 UNUSED(hlptim);
3326
3327 /* NOTE : This function should not be modified, when the callback is needed,
3328 the HAL_LPTIM_UpdateEventCallback could be implemented in the user file
3329 */
3330 }
3331
3332 /**
3333 * @brief Successful APB bus write to repetition counter register callback in non-blocking mode.
3334 * @param hlptim LPTIM handle
3335 * @retval None
3336 */
HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef * hlptim)3337 __weak void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim)
3338 {
3339 /* Prevent unused argument(s) compilation warning */
3340 UNUSED(hlptim);
3341
3342 /* NOTE : This function should not be modified, when the callback is needed,
3343 the HAL_LPTIM_RepCounterWriteCallback could be implemented in the user file
3344 */
3345 }
3346
3347 /**
3348 * @brief Input Capture callback in non-blocking mode
3349 * @param hlptim LPTIM handle
3350 * @retval None
3351 */
HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef * hlptim)3352 __weak void HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef *hlptim)
3353 {
3354 /* Prevent unused argument(s) compilation warning */
3355 UNUSED(hlptim);
3356
3357 /* NOTE : This function should not be modified, when the callback is needed,
3358 the HAL_LPTIM_IC_CaptureCallback could be implemented in the user file
3359 */
3360 }
3361
3362 /**
3363 * @brief Over Capture callback in non-blocking mode
3364 * @param hlptim LPTIM handle
3365 * @retval None
3366 */
HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef * hlptim)3367 __weak void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim)
3368 {
3369 /* Prevent unused argument(s) compilation warning */
3370 UNUSED(hlptim);
3371
3372 /* NOTE : This function should not be modified, when the callback is needed,
3373 the HAL_LPTIM_IC_OverCaptureCallback could be implemented in the user file
3374 */
3375 }
3376
3377 /**
3378 * @brief Input Capture half complete callback in non-blocking mode
3379 * @param hlptim LPTIM IC handle
3380 * @retval None
3381 */
HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef * hlptim)3382 __weak void HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
3383 {
3384 /* Prevent unused argument(s) compilation warning */
3385 UNUSED(hlptim);
3386
3387 /* NOTE : This function should not be modified, when the callback is needed,
3388 the HAL_LPTIM_IC_CaptureHalfCpltCallback could be implemented in the user file
3389 */
3390 }
3391
3392 /**
3393 * @brief Update event half complete callback in non-blocking mode
3394 * @param hlptim LPTIM handle
3395 * @retval None
3396 */
HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef * hlptim)3397 __weak void HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
3398 {
3399 /* Prevent unused argument(s) compilation warning */
3400 UNUSED(hlptim);
3401
3402 /* NOTE : This function should not be modified, when the callback is needed,
3403 the HAL_LPTIM_UpdateEventHalfCpltCallback could be implemented in the user file
3404 */
3405 }
3406
3407 /**
3408 * @brief Error callback in non-blocking mode
3409 * @param hlptim LPTIM handle
3410 * @retval None
3411 */
HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef * hlptim)3412 __weak void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim)
3413 {
3414 /* Prevent unused argument(s) compilation warning */
3415 UNUSED(hlptim);
3416
3417 /* NOTE : This function should not be modified, when the callback is needed,
3418 the HAL_LPTIM_ErrorCallback could be implemented in the user file
3419 */
3420 }
3421
3422
3423 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3424 /**
3425 * @brief Register a User LPTIM callback to be used instead of the weak predefined callback
3426 * @param hlptim LPTIM handle
3427 * @param CallbackID ID of the callback to be registered
3428 * This parameter can be one of the following values:
3429 * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
3430 * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
3431 * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
3432 * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
3433 * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
3434 * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
3435 * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
3436 * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
3437 * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
3438 * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID
3439 * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
3440 * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID
3441 * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID
3442 * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID
3443 * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
3444 * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID
3445 * @param pCallback pointer to the callback function
3446 * @retval status
3447 */
HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef * hlptim,HAL_LPTIM_CallbackIDTypeDef CallbackID,pLPTIM_CallbackTypeDef pCallback)3448 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim,
3449 HAL_LPTIM_CallbackIDTypeDef CallbackID,
3450 pLPTIM_CallbackTypeDef pCallback)
3451 {
3452 HAL_StatusTypeDef status = HAL_OK;
3453
3454 if (pCallback == NULL)
3455 {
3456 return HAL_ERROR;
3457 }
3458
3459 if (hlptim->State == HAL_LPTIM_STATE_READY)
3460 {
3461 switch (CallbackID)
3462 {
3463 case HAL_LPTIM_MSPINIT_CB_ID :
3464 hlptim->MspInitCallback = pCallback;
3465 break;
3466
3467 case HAL_LPTIM_MSPDEINIT_CB_ID :
3468 hlptim->MspDeInitCallback = pCallback;
3469 break;
3470
3471 case HAL_LPTIM_COMPARE_MATCH_CB_ID :
3472 hlptim->CompareMatchCallback = pCallback;
3473 break;
3474
3475 case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
3476 hlptim->AutoReloadMatchCallback = pCallback;
3477 break;
3478
3479 case HAL_LPTIM_TRIGGER_CB_ID :
3480 hlptim->TriggerCallback = pCallback;
3481 break;
3482
3483 case HAL_LPTIM_COMPARE_WRITE_CB_ID :
3484 hlptim->CompareWriteCallback = pCallback;
3485 break;
3486
3487 case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
3488 hlptim->AutoReloadWriteCallback = pCallback;
3489 break;
3490
3491 case HAL_LPTIM_DIRECTION_UP_CB_ID :
3492 hlptim->DirectionUpCallback = pCallback;
3493 break;
3494
3495 case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
3496 hlptim->DirectionDownCallback = pCallback;
3497 break;
3498
3499 case HAL_LPTIM_UPDATE_EVENT_CB_ID :
3500 hlptim->UpdateEventCallback = pCallback;
3501 break;
3502
3503 case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
3504 hlptim->RepCounterWriteCallback = pCallback;
3505 break;
3506
3507 case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
3508 hlptim->UpdateEventHalfCpltCallback = pCallback;
3509 break;
3510
3511 case HAL_LPTIM_ERROR_CB_ID :
3512 hlptim->ErrorCallback = pCallback;
3513 break;
3514
3515 case HAL_LPTIM_IC_CAPTURE_CB_ID :
3516 hlptim->IC_CaptureCallback = pCallback;
3517 break;
3518
3519 case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
3520 hlptim->IC_CaptureHalfCpltCallback = pCallback;
3521 break;
3522
3523 case HAL_LPTIM_OVER_CAPTURE_CB_ID :
3524 hlptim->IC_OverCaptureCallback = pCallback;
3525 break;
3526
3527 default :
3528 /* Return error status */
3529 status = HAL_ERROR;
3530 break;
3531 }
3532 }
3533 else if (hlptim->State == HAL_LPTIM_STATE_RESET)
3534 {
3535 switch (CallbackID)
3536 {
3537 case HAL_LPTIM_MSPINIT_CB_ID :
3538 hlptim->MspInitCallback = pCallback;
3539 break;
3540
3541 case HAL_LPTIM_MSPDEINIT_CB_ID :
3542 hlptim->MspDeInitCallback = pCallback;
3543 break;
3544
3545 default :
3546 /* Return error status */
3547 status = HAL_ERROR;
3548 break;
3549 }
3550 }
3551 else
3552 {
3553 /* Return error status */
3554 status = HAL_ERROR;
3555 }
3556
3557 return status;
3558 }
3559
3560 /**
3561 * @brief Unregister a LPTIM callback
3562 * LLPTIM callback is redirected to the weak predefined callback
3563 * @param hlptim LPTIM handle
3564 * @param CallbackID ID of the callback to be unregistered
3565 * This parameter can be one of the following values:
3566 * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
3567 * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
3568 * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
3569 * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
3570 * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
3571 * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
3572 * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
3573 * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
3574 * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
3575 * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID
3576 * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
3577 * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID
3578 * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID
3579 * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID
3580 * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
3581 * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID
3582 * @retval status
3583 */
HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef * hlptim,HAL_LPTIM_CallbackIDTypeDef CallbackID)3584 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim,
3585 HAL_LPTIM_CallbackIDTypeDef CallbackID)
3586 {
3587 HAL_StatusTypeDef status = HAL_OK;
3588
3589 if (hlptim->State == HAL_LPTIM_STATE_READY)
3590 {
3591 switch (CallbackID)
3592 {
3593 case HAL_LPTIM_MSPINIT_CB_ID :
3594 /* Legacy weak MspInit Callback */
3595 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
3596 break;
3597
3598 case HAL_LPTIM_MSPDEINIT_CB_ID :
3599 /* Legacy weak Msp DeInit Callback */
3600 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
3601 break;
3602
3603 case HAL_LPTIM_COMPARE_MATCH_CB_ID :
3604 /* Legacy weak Compare match Callback */
3605 hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
3606 break;
3607
3608 case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
3609 /* Legacy weak Auto-reload match Callback */
3610 hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
3611 break;
3612
3613 case HAL_LPTIM_TRIGGER_CB_ID :
3614 /* Legacy weak External trigger event detection Callback */
3615 hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
3616 break;
3617
3618 case HAL_LPTIM_COMPARE_WRITE_CB_ID :
3619 /* Legacy weak Compare register write complete Callback */
3620 hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
3621 break;
3622
3623 case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
3624 /* Legacy weak Auto-reload register write complete Callback */
3625 hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
3626 break;
3627
3628 case HAL_LPTIM_DIRECTION_UP_CB_ID :
3629 /* Legacy weak Up-counting direction change Callback */
3630 hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
3631 break;
3632
3633 case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
3634 /* Legacy weak Down-counting direction change Callback */
3635 hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
3636 break;
3637
3638 case HAL_LPTIM_UPDATE_EVENT_CB_ID :
3639 /* Legacy weak Update event detection Callback */
3640 hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
3641 break;
3642
3643 case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
3644 /* Legacy weak Repetition counter register write complete Callback */
3645 hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
3646 break;
3647
3648 case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
3649 /* Legacy weak Update event half complete detection Callback */
3650 hlptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
3651 break;
3652
3653 case HAL_LPTIM_ERROR_CB_ID :
3654 /* Legacy weak error Callback */
3655 hlptim->ErrorCallback = HAL_LPTIM_ErrorCallback;
3656 break;
3657
3658 case HAL_LPTIM_IC_CAPTURE_CB_ID :
3659 /* Legacy weak IC Capture Callback */
3660 hlptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
3661 break;
3662
3663 case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
3664 /* Legacy weak IC Capture half complete Callback */
3665 hlptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
3666 break;
3667
3668 case HAL_LPTIM_OVER_CAPTURE_CB_ID :
3669 /* Legacy weak IC over capture Callback */
3670 hlptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
3671 break;
3672
3673 default :
3674 /* Return error status */
3675 status = HAL_ERROR;
3676 break;
3677 }
3678 }
3679 else if (hlptim->State == HAL_LPTIM_STATE_RESET)
3680 {
3681 switch (CallbackID)
3682 {
3683 case HAL_LPTIM_MSPINIT_CB_ID :
3684 /* Legacy weak MspInit Callback */
3685 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
3686 break;
3687
3688 case HAL_LPTIM_MSPDEINIT_CB_ID :
3689 /* Legacy weak Msp DeInit Callback */
3690 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
3691 break;
3692
3693 default :
3694 /* Return error status */
3695 status = HAL_ERROR;
3696 break;
3697 }
3698 }
3699 else
3700 {
3701 /* Return error status */
3702 status = HAL_ERROR;
3703 }
3704
3705 return status;
3706 }
3707 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3708
3709 /**
3710 * @}
3711 */
3712
3713 /** @defgroup LPTIM_Group5 Peripheral State functions
3714 * @brief Peripheral State functions.
3715 *
3716 @verbatim
3717 ==============================================================================
3718 ##### Peripheral State functions #####
3719 ==============================================================================
3720 [..]
3721 This subsection permits to get in run-time the status of the peripheral.
3722
3723 @endverbatim
3724 * @{
3725 */
3726
3727 /**
3728 * @brief Return the LPTIM handle state.
3729 * @param hlptim LPTIM handle
3730 * @retval HAL state
3731 */
HAL_LPTIM_GetState(const LPTIM_HandleTypeDef * hlptim)3732 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim)
3733 {
3734 /* Return LPTIM handle state */
3735 return hlptim->State;
3736 }
3737
3738 /**
3739 * @}
3740 */
3741
3742
3743 /**
3744 * @}
3745 */
3746
3747 /* Private functions ---------------------------------------------------------*/
3748
3749 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
3750 * @{
3751 */
3752 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3753 /**
3754 * @brief Reset interrupt callbacks to the legacy weak callbacks.
3755 * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains
3756 * the configuration information for LPTIM module.
3757 * @retval None
3758 */
LPTIM_ResetCallback(LPTIM_HandleTypeDef * lptim)3759 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
3760 {
3761 /* Reset the LPTIM callback to the legacy weak callbacks */
3762 lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
3763 lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
3764 lptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
3765 lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
3766 lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
3767 lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
3768 lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
3769 lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
3770 lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
3771 lptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
3772 lptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
3773 lptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
3774 lptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
3775 lptim->ErrorCallback = HAL_LPTIM_ErrorCallback;
3776 }
3777 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3778
3779 /**
3780 * @brief LPTimer Wait for flag set
3781 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3782 * the configuration information for LPTIM module.
3783 * @param flag The lptim flag
3784 * @retval HAL status
3785 */
LPTIM_WaitForFlag(const LPTIM_HandleTypeDef * hlptim,uint32_t flag)3786 static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag)
3787 {
3788 HAL_StatusTypeDef result = HAL_OK;
3789 uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
3790 do
3791 {
3792 count--;
3793 if (count == 0UL)
3794 {
3795 result = HAL_TIMEOUT;
3796 }
3797 } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
3798
3799 return result;
3800 }
3801
3802 /**
3803 * @brief LPTIM DMA error callback
3804 * @param hdma pointer to DMA handle.
3805 * @retval None
3806 */
LPTIM_DMAError(DMA_HandleTypeDef * hdma)3807 void LPTIM_DMAError(DMA_HandleTypeDef *hdma)
3808 {
3809 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3810
3811 hlptim->State = HAL_LPTIM_STATE_READY;
3812
3813 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3814 hlptim->ErrorCallback(hlptim);
3815 #else
3816 HAL_LPTIM_ErrorCallback(hlptim);
3817 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3818 }
3819
3820 /**
3821 * @brief LPTIM DMA Capture complete callback.
3822 * @param hdma pointer to DMA handle.
3823 * @retval None
3824 */
LPTIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)3825 void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
3826 {
3827 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3828
3829 hlptim->State = HAL_LPTIM_STATE_READY;
3830
3831 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3832 {
3833 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3834 }
3835 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3836 {
3837 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3838 }
3839 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC3])
3840 {
3841 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_3;
3842 }
3843 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC4])
3844 {
3845 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_4;
3846 }
3847 else
3848 {
3849 /* nothing to do */
3850 }
3851
3852 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3853 hlptim->IC_CaptureCallback(hlptim);
3854 #else
3855 HAL_LPTIM_IC_CaptureCallback(hlptim);
3856 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3857
3858 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3859 }
3860
3861 /**
3862 * @brief LPTIM DMA Capture half complete callback.
3863 * @param hdma pointer to DMA handle.
3864 * @retval None
3865 */
LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)3866 void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
3867 {
3868 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3869
3870 hlptim->State = HAL_LPTIM_STATE_READY;
3871
3872 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3873 {
3874 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3875 }
3876 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3877 {
3878 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3879 }
3880 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC3])
3881 {
3882 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_3;
3883 }
3884 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC4])
3885 {
3886 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_4;
3887 }
3888 else
3889 {
3890 /* nothing to do */
3891 }
3892
3893 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3894 hlptim->IC_CaptureHalfCpltCallback(hlptim);
3895 #else
3896 HAL_LPTIM_IC_CaptureHalfCpltCallback(hlptim);
3897 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3898
3899 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3900 }
3901
3902 /**
3903 * @brief LPTIM DMA Update event complete callback.
3904 * @param hdma pointer to DMA handle.
3905 * @retval None
3906 */
LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef * hdma)3907 void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma)
3908 {
3909 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3910
3911 hlptim->State = HAL_LPTIM_STATE_READY;
3912
3913 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3914 {
3915 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3916 }
3917 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3918 {
3919 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3920 }
3921 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC3])
3922 {
3923 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_3;
3924 }
3925 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC4])
3926 {
3927 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_4;
3928 }
3929 else
3930 {
3931 /* nothing to do */
3932 }
3933
3934 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3935 hlptim->UpdateEventCallback(hlptim);
3936 #else
3937 HAL_LPTIM_UpdateEventCallback(hlptim);
3938 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3939
3940 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3941 }
3942
3943 /**
3944 * @brief LPTIM DMA Capture half complete callback.
3945 * @param hdma pointer to DMA handle.
3946 * @retval None
3947 */
LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef * hdma)3948 void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma)
3949 {
3950 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3951
3952 hlptim->State = HAL_LPTIM_STATE_READY;
3953
3954 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3955 {
3956 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3957 }
3958 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3959 {
3960 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3961 }
3962 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC3])
3963 {
3964 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_3;
3965 }
3966 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC4])
3967 {
3968 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_4;
3969 }
3970 else
3971 {
3972 /* nothing to do */
3973 }
3974
3975 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3976 hlptim->UpdateEventHalfCpltCallback(hlptim);
3977 #else
3978 HAL_LPTIM_UpdateEventHalfCpltCallback(hlptim);
3979 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3980
3981 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3982 }
3983 /**
3984 * @brief LPTimer Output Compare 1 configuration
3985 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3986 * the configuration information for LPTIM module.
3987 * @param sConfig The output configuration structure
3988 * @retval None
3989 */
LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig)3990 static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig)
3991 {
3992 uint32_t tmpccmr1;
3993
3994 tmpccmr1 = hlptim->Instance->CCMR1;
3995 tmpccmr1 &= ~(LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_CC1SEL_Msk);
3996
3997 tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC1P_Pos;
3998
3999 /* Enable the Peripheral */
4000 __HAL_LPTIM_ENABLE(hlptim);
4001
4002 /* Clear flag */
4003 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
4004
4005 /* Write to CCR1 register */
4006 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, sConfig->Pulse);
4007
4008 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
4009 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
4010 {
4011 return HAL_TIMEOUT;
4012 }
4013
4014 /* Disable the Peripheral */
4015 __HAL_LPTIM_DISABLE(hlptim);
4016
4017 /* Write to CCMR1 register */
4018 hlptim->Instance->CCMR1 = tmpccmr1;
4019
4020 return HAL_OK;
4021 }
4022
4023 /**
4024 * @brief LPTimer Output Compare 2 configuration
4025 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
4026 * the configuration information for LPTIM module.
4027 * @param sConfig The output configuration structure
4028 * @retval None
4029 */
LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig)4030 static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig)
4031 {
4032 uint32_t tmpccmr1;
4033
4034 tmpccmr1 = hlptim->Instance->CCMR1;
4035 tmpccmr1 &= ~(LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_CC2SEL_Msk);
4036 tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC2P_Pos;
4037
4038 /* Enable the Peripheral */
4039 __HAL_LPTIM_ENABLE(hlptim);
4040
4041 /* Clear flag */
4042 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
4043
4044 /* Write to CCR2 register */
4045 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, sConfig->Pulse);
4046
4047 /* Wait for the completion of the write operation to the LPTIM_CCR2 register */
4048 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) != HAL_OK)
4049 {
4050 return HAL_TIMEOUT;
4051 }
4052
4053 /* Disable the Peripheral */
4054 __HAL_LPTIM_DISABLE(hlptim);
4055
4056 /* Write to CCMR1 register */
4057 hlptim->Instance->CCMR1 = tmpccmr1;
4058
4059 return HAL_OK;
4060 }
4061
4062 /**
4063 * @brief LPTimer Output Compare 3 configuration
4064 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
4065 * the configuration information for LPTIM module.
4066 * @param sConfig The output configuration structure
4067 * @retval None
4068 */
LPTIM_OC3_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig)4069 static HAL_StatusTypeDef LPTIM_OC3_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig)
4070 {
4071 uint32_t tmpccmr2;
4072
4073 tmpccmr2 = hlptim->Instance->CCMR2;
4074 tmpccmr2 &= ~(LPTIM_CCMR2_CC3P_Msk | LPTIM_CCMR2_CC3SEL_Msk);
4075
4076 tmpccmr2 |= sConfig->OCPolarity << LPTIM_CCMR2_CC3P_Pos;
4077
4078 /* Enable the Peripheral */
4079 __HAL_LPTIM_ENABLE(hlptim);
4080
4081 /* Clear flag */
4082 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP3OK);
4083
4084 /* Write to CCR3 register */
4085 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_3, sConfig->Pulse);
4086
4087 /* Wait for the completion of the write operation to the LPTIM_CCR3 register */
4088 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP3OK) == HAL_TIMEOUT)
4089 {
4090 return HAL_TIMEOUT;
4091 }
4092
4093 /* Disable the Peripheral */
4094 __HAL_LPTIM_DISABLE(hlptim);
4095
4096 /* Write to CCMR1 register */
4097 hlptim->Instance->CCMR2 = tmpccmr2;
4098
4099 return HAL_OK;
4100 }
4101
4102 /**
4103 * @brief LPTimer Output Compare 4 configuration
4104 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
4105 * the configuration information for LPTIM module.
4106 * @param sConfig The output configuration structure
4107 * @retval None
4108 */
LPTIM_OC4_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig)4109 static HAL_StatusTypeDef LPTIM_OC4_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig)
4110 {
4111 uint32_t tmpccmr2;
4112
4113 tmpccmr2 = hlptim->Instance->CCMR2;
4114 tmpccmr2 &= ~(LPTIM_CCMR2_CC4P_Msk | LPTIM_CCMR2_CC4SEL_Msk);
4115
4116 tmpccmr2 |= sConfig->OCPolarity << LPTIM_CCMR2_CC4P_Pos;
4117
4118 /* Enable the Peripheral */
4119 __HAL_LPTIM_ENABLE(hlptim);
4120
4121 /* Clear flag */
4122 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP4OK);
4123
4124 /* Write to CCR4 register */
4125 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_4, sConfig->Pulse);
4126
4127 /* Wait for the completion of the write operation to the LPTIM_CCR4 register */
4128 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP4OK) == HAL_TIMEOUT)
4129 {
4130 return HAL_TIMEOUT;
4131 }
4132
4133 /* Disable the Peripheral */
4134 __HAL_LPTIM_DISABLE(hlptim);
4135
4136 /* Write to CCMR1 register */
4137 hlptim->Instance->CCMR2 = tmpccmr2;
4138
4139 return HAL_OK;
4140 }
4141
4142 /**
4143 * @brief LPTimer Input Capture 1 configuration
4144 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
4145 * the configuration information for LPTIM module.
4146 * @param sConfig The input configuration structure
4147 * @retval None
4148 */
LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig)4149 static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig)
4150 {
4151 uint32_t tmpccmr1;
4152 uint32_t tmpcfgr2;
4153
4154 tmpccmr1 = hlptim->Instance->CCMR1;
4155 tmpccmr1 &= ~(LPTIM_CCMR1_IC1PSC_Msk | LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_IC1F_Msk);
4156 tmpccmr1 |= sConfig->ICPrescaler |
4157 sConfig->ICPolarity |
4158 sConfig->ICFilter |
4159 LPTIM_CCMR1_CC1SEL;
4160
4161 tmpcfgr2 = hlptim->Instance->CFGR2;
4162 tmpcfgr2 &= ~(LPTIM_CFGR2_IC1SEL_Msk);
4163 tmpcfgr2 |= sConfig->ICInputSource;
4164
4165 /* Write to CCMR1 register */
4166 hlptim->Instance->CCMR1 = tmpccmr1;
4167
4168 /* Write to CFGR2 register */
4169 hlptim->Instance->CFGR2 = tmpcfgr2;
4170 }
4171
4172 /**
4173 * @brief LPTimer Input Capture 2 configuration
4174 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
4175 * the configuration information for LPTIM module.
4176 * @param sConfig The input configuration structure
4177 * @retval None
4178 */
LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig)4179 static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig)
4180 {
4181 uint32_t tmpccmr1;
4182 uint32_t tmpcfgr2;
4183
4184 tmpccmr1 = hlptim->Instance->CCMR1;
4185 tmpccmr1 &= ~(LPTIM_CCMR1_IC2PSC_Msk | LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_IC2F_Msk);
4186 tmpccmr1 |= (sConfig->ICPrescaler << (LPTIM_CCMR1_IC2PSC_Pos - LPTIM_CCMR1_IC1PSC_Pos)) |
4187 (sConfig->ICPolarity << (LPTIM_CCMR1_CC2P_Pos - LPTIM_CCMR1_CC1P_Pos)) |
4188 (sConfig->ICFilter << (LPTIM_CCMR1_IC2F_Pos - LPTIM_CCMR1_IC1F_Pos)) |
4189 LPTIM_CCMR1_CC2SEL;
4190
4191 tmpcfgr2 = hlptim->Instance->CFGR2;
4192 tmpcfgr2 &= ~(LPTIM_CFGR2_IC2SEL_Msk);
4193 tmpcfgr2 |= sConfig->ICInputSource;
4194
4195 /* Write to CCMR1 register */
4196 hlptim->Instance->CCMR1 = tmpccmr1;
4197
4198 /* Write to CFGR2 register */
4199 hlptim->Instance->CFGR2 = tmpcfgr2;
4200 }
4201
4202 /**
4203 * @brief LPTimer Input Capture 3 configuration
4204 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
4205 * the configuration information for LPTIM module.
4206 * @param sConfig The input configuration structure
4207 * @retval None
4208 */
LPTIM_IC3_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig)4209 static void LPTIM_IC3_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig)
4210 {
4211 uint32_t tmpccmr2;
4212 uint32_t tmpcfgr2;
4213
4214 tmpccmr2 = hlptim->Instance->CCMR1;
4215 tmpccmr2 &= ~(LPTIM_CCMR2_IC3PSC_Msk | LPTIM_CCMR2_CC3P_Msk | LPTIM_CCMR2_IC3F_Msk);
4216 tmpccmr2 |= sConfig->ICPrescaler |
4217 sConfig->ICPolarity |
4218 sConfig->ICFilter |
4219 LPTIM_CCMR1_CC1SEL;
4220
4221 tmpcfgr2 = hlptim->Instance->CFGR2;
4222 tmpcfgr2 &= ~(LPTIM_CFGR2_IC3SEL_Msk);
4223 tmpcfgr2 |= sConfig->ICInputSource;
4224
4225 /* Write to CCMR2 register */
4226 hlptim->Instance->CCMR2 = tmpccmr2;
4227
4228 /* Write to CFGR2 register */
4229 hlptim->Instance->CFGR2 = tmpcfgr2;
4230 }
4231
4232 /**
4233 * @brief LPTimer Input Capture 4 configuration
4234 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
4235 * the configuration information for LPTIM module.
4236 * @param sConfig The input configuration structure
4237 * @retval None
4238 */
LPTIM_IC4_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig)4239 static void LPTIM_IC4_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig)
4240 {
4241 uint32_t tmpccmr2;
4242 uint32_t tmpcfgr2;
4243
4244 tmpccmr2 = hlptim->Instance->CCMR2;
4245 tmpccmr2 &= ~(LPTIM_CCMR2_IC4PSC_Msk | LPTIM_CCMR2_CC4P_Msk | LPTIM_CCMR2_IC4F_Msk);
4246 tmpccmr2 |= (sConfig->ICPrescaler << (LPTIM_CCMR2_IC4PSC_Pos - LPTIM_CCMR2_IC3PSC_Pos)) |
4247 (sConfig->ICPolarity << (LPTIM_CCMR2_CC4P_Pos - LPTIM_CCMR2_CC3P_Pos)) |
4248 (sConfig->ICFilter << (LPTIM_CCMR2_IC4F_Pos - LPTIM_CCMR2_IC3F_Pos)) |
4249 LPTIM_CCMR2_CC3SEL;
4250
4251 tmpcfgr2 = hlptim->Instance->CFGR2;
4252 tmpcfgr2 &= ~(LPTIM_CFGR2_IC4SEL_Msk);
4253 tmpcfgr2 |= sConfig->ICInputSource;
4254
4255 /* Write to CCMR2 register */
4256 hlptim->Instance->CCMR2 = tmpccmr2;
4257
4258 /* Write to CFGR2 register */
4259 hlptim->Instance->CFGR2 = tmpcfgr2;
4260 }
4261
4262 /**
4263 * @}
4264 */
4265 #endif /* LPTIM1 || LPTIM2 || LPTIM3 */
4266
4267 #endif /* HAL_LPTIM_MODULE_ENABLED */
4268 /**
4269 * @}
4270 */
4271
4272 /**
4273 * @}
4274 */
4275
