1 /**
2 ******************************************************************************
3 * @file stm32u0xx_hal_adc.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Converter (ADC)
7 * peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 * + Peripheral State functions
11 * Other functions (extended functions) are available in file
12 * "stm32u0xx_hal_adc_ex.c".
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2023 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### ADC peripheral features #####
28 ==============================================================================
29 [..]
30 (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
31
32 (+) Interrupt generation at the end of regular conversion and in case of
33 analog watchdog or overrun events.
34
35 (+) Single and continuous conversion modes.
36
37 (+) Scan mode for conversion of several channels sequentially.
38
39 (+) Data alignment with in-built data coherency.
40
41 (+) Programmable sampling time (common to group of channels)
42
43 (+) External trigger (timer or EXTI) with configurable polarity
44
45 (+) DMA request generation for transfer of conversions data of regular group.
46
47 (+) ADC calibration
48
49 (+) ADC conversion of regular group.
50
51 (+) ADC supply requirements: 1.62 V to 3.6 V.
52
53 (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
54 Vdda or to an external voltage reference).
55
56
57 ##### How to use this driver #####
58 ==============================================================================
59 [..]
60
61 *** Configuration of top level parameters related to ADC ***
62 ============================================================
63 [..]
64
65 (#) Enable the ADC interface
66 (++) As prerequisite, ADC clock must be configured at RCC top level.
67 Caution: On this series, ADC clock frequency max is 35MHz (refer
68 to device datasheet).
69 Therefore, ADC clock source from RCC and ADC clock
70 prescaler must be configured to remain below
71 this maximum frequency.
72
73 (++) Two clock settings are mandatory:
74 (+++) ADC clock (core clock, also possibly conversion clock).
75
76 (+++) ADC clock (conversions clock).
77 Four possible clock sources: synchronous clock from APB clock (same as ADC core clock)
78 or asynchronous clock from RCC level: SYSCLK, HSI16, PLLPCLK.
79
80 (+++) Example:
81 Into HAL_ADC_MspInit() (recommended code location) or with
82 other device clock parameters configuration:
83 (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory: core clock)
84 (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
85
86 (++) ADC clock source and clock prescaler are configured at ADC level with
87 parameter "ClockPrescaler" using function HAL_ADC_Init().
88
89 (#) ADC pins configuration
90 (++) Enable the clock for the ADC GPIOs
91 using macro __HAL_RCC_GPIOx_CLK_ENABLE()
92 (++) Configure these ADC pins in analog mode
93 using function HAL_GPIO_Init()
94
95 (#) Optionally, in case of usage of ADC with interruptions:
96 (++) Configure the NVIC for ADC
97 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
98 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
99 into the function of corresponding ADC interruption vector
100 ADCx_IRQHandler().
101
102 (#) Optionally, in case of usage of DMA:
103 (++) Configure the DMA (DMA channel, mode normal or circular, ...)
104 using function HAL_DMA_Init().
105 (++) Configure the NVIC for DMA
106 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
107 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
108 into the function of corresponding DMA interruption vector
109 DMAx_Channelx_IRQHandler().
110
111 *** Configuration of ADC, group regular, channels parameters ***
112 ================================================================
113 [..]
114
115 (#) Configure the ADC parameters (resolution, data alignment, ...)
116 and regular group parameters (conversion trigger, sequencer, ...)
117 using function HAL_ADC_Init().
118
119 (#) Configure the channels for regular group parameters (channel number,
120 channel rank into sequencer, ..., into regular group)
121 using function HAL_ADC_ConfigChannel().
122
123 (#) Optionally, configure the analog watchdog parameters (channels
124 monitored, thresholds, ...)
125 using function HAL_ADC_AnalogWDGConfig().
126
127 *** Execution of ADC conversions ***
128 ====================================
129 [..]
130
131 (#) Optionally, perform an automatic ADC calibration to improve the
132 conversion accuracy
133 using function HAL_ADCEx_Calibration_Start().
134
135 (#) ADC driver can be used among three modes: polling, interruption,
136 transfer by DMA.
137
138 (++) ADC conversion by polling:
139 (+++) Activate the ADC peripheral and start conversions
140 using function HAL_ADC_Start()
141 (+++) Wait for ADC conversion completion
142 using function HAL_ADC_PollForConversion()
143 (+++) Retrieve conversion results
144 using function HAL_ADC_GetValue()
145 (+++) Stop conversion and disable the ADC peripheral
146 using function HAL_ADC_Stop()
147
148 (++) ADC conversion by interruption:
149 (+++) Activate the ADC peripheral and start conversions
150 using function HAL_ADC_Start_IT()
151 (+++) Wait for ADC conversion completion by call of function
152 HAL_ADC_ConvCpltCallback()
153 (this function must be implemented in user program)
154 (+++) Retrieve conversion results
155 using function HAL_ADC_GetValue()
156 (+++) Stop conversion and disable the ADC peripheral
157 using function HAL_ADC_Stop_IT()
158
159 (++) ADC conversion with transfer by DMA:
160 (+++) Activate the ADC peripheral and start conversions
161 using function HAL_ADC_Start_DMA()
162 (+++) Wait for ADC conversion completion by call of function
163 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
164 (these functions must be implemented in user program)
165 (+++) Conversion results are automatically transferred by DMA into
166 destination variable address.
167 (+++) Stop conversion and disable the ADC peripheral
168 using function HAL_ADC_Stop_DMA()
169
170 [..]
171
172 (@) Callback functions must be implemented in user program:
173 (+@) HAL_ADC_ErrorCallback()
174 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
175 (+@) HAL_ADC_ConvCpltCallback()
176 (+@) HAL_ADC_ConvHalfCpltCallback
177
178 *** Deinitialization of ADC ***
179 ============================================================
180 [..]
181
182 (#) Disable the ADC interface
183 (++) ADC clock can be hard reset and disabled at RCC top level.
184 (++) Hard reset of ADC peripherals
185 using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
186 (++) ADC clock disable
187 using the equivalent macro/functions as configuration step.
188 (+++) Example:
189 Into HAL_ADC_MspDeInit() (recommended code location) or with
190 other device clock parameters configuration:
191 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
192 (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
193 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
194
195 (#) ADC pins configuration
196 (++) Disable the clock for the ADC GPIOs
197 using macro __HAL_RCC_GPIOx_CLK_DISABLE()
198
199 (#) Optionally, in case of usage of ADC with interruptions:
200 (++) Disable the NVIC for ADC
201 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
202
203 (#) Optionally, in case of usage of DMA:
204 (++) Deinitialize the DMA
205 using function HAL_DMA_Init().
206 (++) Disable the NVIC for DMA
207 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
208
209 [..]
210
211 *** Callback registration ***
212 =============================================
213 [..]
214
215 The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
216 allows the user to configure dynamically the driver callbacks.
217 Use Functions HAL_ADC_RegisterCallback()
218 to register an interrupt callback.
219 [..]
220
221 Function HAL_ADC_RegisterCallback() allows to register following callbacks:
222 (+) ConvCpltCallback : ADC conversion complete callback
223 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
224 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
225 (+) ErrorCallback : ADC error callback
226 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
227 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
228 (+) EndOfSamplingCallback : ADC end of sampling callback
229 (+) MspInitCallback : ADC Msp Init callback
230 (+) MspDeInitCallback : ADC Msp DeInit callback
231 This function takes as parameters the HAL peripheral handle, the Callback ID
232 and a pointer to the user callback function.
233 [..]
234
235 Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
236 weak function.
237 [..]
238
239 HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
240 and the Callback ID.
241 This function allows to reset following callbacks:
242 (+) ConvCpltCallback : ADC conversion complete callback
243 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
244 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
245 (+) ErrorCallback : ADC error callback
246 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
247 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
248 (+) EndOfSamplingCallback : ADC end of sampling callback
249 (+) MspInitCallback : ADC Msp Init callback
250 (+) MspDeInitCallback : ADC Msp DeInit callback
251 [..]
252
253 By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
254 all callbacks are set to the corresponding weak functions:
255 examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
256 Exception done for MspInit and MspDeInit functions that are
257 reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
258 these callbacks are null (not registered beforehand).
259 [..]
260
261 If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
262 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
263 [..]
264
265 Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
266 Exception done MspInit/MspDeInit functions that can be registered/unregistered
267 in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
268 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
269 [..]
270
271 Then, the user first registers the MspInit/MspDeInit user callbacks
272 using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
273 or HAL_ADC_Init() function.
274 [..]
275
276 When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
277 not defined, the callback registration feature is not available and all callbacks
278 are set to the corresponding weak functions.
279
280 @endverbatim
281 ******************************************************************************
282 */
283
284 /* Includes ------------------------------------------------------------------*/
285 #include "stm32u0xx_hal.h"
286
287 /** @addtogroup STM32U0xx_HAL_Driver
288 * @{
289 */
290
291 /** @defgroup ADC ADC
292 * @brief ADC HAL module driver
293 * @{
294 */
295
296 #ifdef HAL_ADC_MODULE_ENABLED
297
298 /* Private typedef -----------------------------------------------------------*/
299 /* Private define ------------------------------------------------------------*/
300
301 /** @defgroup ADC_Private_Constants ADC Private Constants
302 * @{
303 */
304
305 /* Fixed timeout values for ADC calibration, enable settling time, disable */
306 /* settling time. */
307 /* Values defined to be higher than worst cases: low clock frequency, */
308 /* maximum prescaler. */
309 /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
310 /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */
311 /* Unit: ms */
312 #define ADC_ENABLE_TIMEOUT (2UL)
313 #define ADC_DISABLE_TIMEOUT (2UL)
314 #define ADC_STOP_CONVERSION_TIMEOUT (2UL)
315 #define ADC_CHANNEL_CONF_RDY_TIMEOUT (1UL)
316
317 /* Register CHSELR bits corresponding to ranks 2 to 8 . */
318 #define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | \
319 ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)
320
321 /**
322 * @}
323 */
324
325 /* Private macro -------------------------------------------------------------*/
326 /* Private variables ---------------------------------------------------------*/
327 /* Private function prototypes -----------------------------------------------*/
328 /** @defgroup ADC_Private_Functions ADC Private Functions
329 * @{
330 */
331 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
332 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
333 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
334 /**
335 * @}
336 */
337
338 /* Exported functions ---------------------------------------------------------*/
339
340 /** @defgroup ADC_Exported_Functions ADC Exported Functions
341 * @{
342 */
343
344 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
345 * @brief ADC Initialization and Configuration functions
346 *
347 @verbatim
348 ===============================================================================
349 ##### Initialization and de-initialization functions #####
350 ===============================================================================
351 [..] This section provides functions allowing to:
352 (+) Initialize and configure the ADC.
353 (+) De-initialize the ADC.
354 @endverbatim
355 * @{
356 */
357
358 /**
359 * @brief Initialize the ADC peripheral and regular group according to
360 * parameters specified in structure "ADC_InitTypeDef".
361 * @note As prerequisite, ADC clock must be configured at RCC top level
362 * (refer to description of RCC configuration for ADC
363 * in header of this file).
364 * @note Possibility to update parameters on the fly:
365 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
366 * coming from ADC state reset. Following calls to this function can
367 * be used to reconfigure some parameters of ADC_InitTypeDef
368 * structure on the fly, without modifying MSP configuration. If ADC
369 * MSP has to be modified again, HAL_ADC_DeInit() must be called
370 * before HAL_ADC_Init().
371 * The setting of these parameters is conditioned to ADC state.
372 * For parameters constraints, see comments of structure
373 * "ADC_InitTypeDef".
374 * @note This function configures the ADC within 2 scopes: scope of entire
375 * ADC and scope of regular group. For parameters details, see comments
376 * of structure "ADC_InitTypeDef".
377 * @param hadc ADC handle
378 * @retval HAL status
379 */
HAL_ADC_Init(ADC_HandleTypeDef * hadc)380 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
381 {
382 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
383 uint32_t tmp_cfgr1 = 0UL;
384 uint32_t tmp_cfgr2 = 0UL;
385 uint32_t tmp_adc_reg_is_conversion_on_going;
386 __IO uint32_t wait_loop_index = 0UL;
387
388 /* Check ADC handle */
389 if (hadc == NULL)
390 {
391 return HAL_ERROR;
392 }
393
394 /* Check the parameters */
395 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
396 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
397 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
398 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
399 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
400 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
401 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
402 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
403 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
404 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
405 assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
406 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
407 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
408 assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1));
409 assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2));
410 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
411 if (hadc->Init.OversamplingMode == ENABLE)
412 {
413 assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
414 assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
415 assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
416 }
417 assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode));
418
419 if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
420 {
421 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
422
423 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
424 {
425 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
426 }
427 }
428
429 /* ADC group regular discontinuous mode can be enabled only if */
430 /* continuous mode is disabled. */
431 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
432
433 /* Actions performed only if ADC is coming from state reset: */
434 /* - Initialization of ADC MSP */
435 if (hadc->State == HAL_ADC_STATE_RESET)
436 {
437 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
438 /* Init the ADC Callback settings */
439 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
440 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
441 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
442 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
443 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
444 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
445 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
446 hadc->CalibrationCpltCallback = HAL_ADC_CalibrationCpltCallback; /* Legacy weak callback */
447 hadc->ADCReadyCallback = HAL_ADC_ADCReadyCallback; /* Legacy weak callback */
448 hadc->ChannelConfigReadyCallback = HAL_ADCEx_ChannelConfigReadyCallback; /* Legacy weak callback */
449
450 if (hadc->MspInitCallback == NULL)
451 {
452 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
453 }
454
455 /* Init the low level hardware */
456 hadc->MspInitCallback(hadc);
457 #else
458 /* Init the low level hardware */
459 HAL_ADC_MspInit(hadc);
460 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
461
462 /* Set ADC error code to none */
463 ADC_CLEAR_ERRORCODE(hadc);
464
465 /* Initialize Lock */
466 hadc->Lock = HAL_UNLOCKED;
467 }
468
469 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
470 {
471 /* Enable ADC internal voltage regulator */
472 LL_ADC_EnableInternalRegulator(hadc->Instance);
473
474 /* Delay for ADC stabilization time */
475 /* Wait loop initialization and execution */
476 /* Note: Variable divided by 2 to compensate partially */
477 /* CPU processing cycles, scaling in us split to not */
478 /* exceed 32 bits register capacity and handle low frequency. */
479 wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
480 while (wait_loop_index != 0UL)
481 {
482 wait_loop_index--;
483 }
484 }
485
486 /* Verification that ADC voltage regulator is correctly enabled, whether */
487 /* or not ADC is coming from state reset (if any potential problem of */
488 /* clocking, voltage regulator would not be enabled). */
489 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
490 {
491 /* Update ADC state machine to error */
492 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
493
494 /* Set ADC error code to ADC peripheral internal error */
495 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
496
497 tmp_hal_status = HAL_ERROR;
498 }
499
500 /* Configuration of ADC parameters if previous preliminary actions are */
501 /* correctly completed and if there is no conversion on going on regular */
502 /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
503 /* called to update a parameter on the fly). */
504 tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
505
506 if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
507 && (tmp_adc_reg_is_conversion_on_going == 0UL)
508 )
509 {
510 /* Set ADC state */
511 ADC_STATE_CLR_SET(hadc->State,
512 HAL_ADC_STATE_REG_BUSY,
513 HAL_ADC_STATE_BUSY_INTERNAL);
514
515 /* Configuration of common ADC parameters */
516
517 /* Parameters update conditioned to ADC state: */
518 /* Parameters that can be updated only when ADC is disabled: */
519 /* - Internal voltage regulator (no parameter in HAL ADC init structure) */
520 /* - Clock configuration */
521 /* - ADC resolution */
522 /* - Oversampling */
523 /* - discontinuous mode */
524 /* - LowPowerAutoWait mode */
525 /* - LowPowerAutoPowerOff mode */
526 /* - continuous conversion mode */
527 /* - overrun */
528 /* - external trigger to start conversion */
529 /* - external trigger polarity */
530 /* - data alignment */
531 /* - resolution */
532 /* - scan direction */
533 /* - DMA continuous request */
534 /* - Trigger frequency mode */
535 /* Note: If low power mode AutoPowerOff is enabled, ADC enable */
536 /* and disable phases are performed automatically by hardware */
537 /* (in this case, flag ADC_FLAG_RDY is not set). */
538 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
539 {
540 /* Some parameters of this register are not reset, since they are set */
541 /* by other functions and must be kept in case of usage of this */
542 /* function on the fly (update of a parameter of ADC_InitTypeDef */
543 /* without needing to reconfigure all other ADC groups/channels */
544 /* parameters): */
545 /* - internal measurement paths (VrefInt, ...) */
546 /* (set into HAL_ADC_ConfigChannel() ) */
547
548 tmp_cfgr1 |= (hadc->Init.Resolution |
549 ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
550 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
551 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
552 ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
553 hadc->Init.DataAlign |
554 ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
555 ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
556
557 /* Update setting of discontinuous mode only if continuous mode is disabled */
558 if (hadc->Init.DiscontinuousConvMode == ENABLE)
559 {
560 if (hadc->Init.ContinuousConvMode == DISABLE)
561 {
562 /* Enable the selected ADC group regular discontinuous mode */
563 tmp_cfgr1 |= ADC_CFGR1_DISCEN;
564 }
565 else
566 {
567 /* ADC regular group discontinuous was intended to be enabled, */
568 /* but ADC regular group modes continuous and sequencer discontinuous */
569 /* cannot be enabled simultaneously. */
570
571 /* Update ADC state machine to error */
572 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
573
574 /* Set ADC error code to ADC peripheral internal error */
575 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
576 }
577 }
578
579 /* Enable external trigger if trigger selection is different of software */
580 /* start. */
581 /* Note: This configuration keeps the hardware feature of parameter */
582 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
583 /* software start. */
584 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
585 {
586 tmp_cfgr1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) |
587 hadc->Init.ExternalTrigConvEdge);
588 }
589
590 /* Update ADC configuration register with previous settings */
591 MODIFY_REG(hadc->Instance->CFGR1,
592 ADC_CFGR1_RES |
593 ADC_CFGR1_DISCEN |
594 ADC_CFGR1_CHSELRMOD |
595 ADC_CFGR1_AUTOFF |
596 ADC_CFGR1_WAIT |
597 ADC_CFGR1_CONT |
598 ADC_CFGR1_OVRMOD |
599 ADC_CFGR1_EXTSEL |
600 ADC_CFGR1_EXTEN |
601 ADC_CFGR1_ALIGN |
602 ADC_CFGR1_SCANDIR |
603 ADC_CFGR1_DMACFG,
604 tmp_cfgr1);
605
606 tmp_cfgr2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
607 hadc->Init.TriggerFrequencyMode
608 );
609
610 if (hadc->Init.OversamplingMode == ENABLE)
611 {
612 tmp_cfgr2 |= (ADC_CFGR2_OVSE |
613 (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
614 hadc->Init.Oversampling.Ratio |
615 hadc->Init.Oversampling.RightBitShift |
616 hadc->Init.Oversampling.TriggeredMode
617 );
618 }
619
620 MODIFY_REG(hadc->Instance->CFGR2,
621 ADC_CFGR2_CKMODE |
622 ADC_CFGR2_LFTRIG |
623 ADC_CFGR2_OVSE |
624 ADC_CFGR2_OVSR |
625 ADC_CFGR2_OVSS |
626 ADC_CFGR2_TOVS,
627 tmp_cfgr2);
628
629 /* Configuration of ADC clock mode: asynchronous clock source */
630 /* with selectable prescaler. */
631 if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
632 ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) &&
633 ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4))
634 {
635 MODIFY_REG(ADC1_COMMON->CCR,
636 ADC_CCR_PRESC,
637 hadc->Init.ClockPrescaler & ADC_CCR_PRESC);
638 }
639 }
640
641 /* Channel sampling time configuration */
642 LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1);
643 LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2);
644
645 /* Configuration of regular group sequencer: */
646 /* - if scan mode is disabled, regular channels sequence length is set to */
647 /* 0x00: 1 channel converted (channel on regular rank 1) */
648 /* Parameter "NbrOfConversion" is discarded. */
649 /* Note: Scan mode is not present by hardware on this device, but */
650 /* emulated by software for alignment over all STM32 devices. */
651 /* - if scan mode is enabled, regular channels sequence length is set to */
652 /* parameter "NbrOfConversion". */
653 /* Channels must be configured into each rank using function */
654 /* "HAL_ADC_ConfigChannel()". */
655 if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
656 {
657 /* Set sequencer scan length by clearing ranks above rank 1 */
658 /* and do not modify rank 1 value. */
659 SET_BIT(hadc->Instance->CHSELR,
660 ADC_CHSELR_SQ2_TO_SQ8);
661 }
662 else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
663 {
664 /* Set ADC group regular sequencer: */
665 /* - Set ADC group regular sequencer to value memorized */
666 /* in HAL ADC handle */
667 /* Note: This value maybe be initialized at a unknown value, */
668 /* therefore after the first call of "HAL_ADC_Init()", */
669 /* each rank corresponding to parameter "NbrOfConversion" */
670 /* must be set using "HAL_ADC_ConfigChannel()". */
671 /* - Set sequencer scan length by clearing ranks above maximum rank */
672 /* and do not modify other ranks value. */
673 MODIFY_REG(hadc->Instance->CHSELR,
674 ADC_CHSELR_SQ_ALL,
675 (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL))
676 | (hadc->ADCGroupRegularSequencerRanks)
677 );
678 }
679 else
680 {
681 /* Nothing to do */
682 }
683
684 /* Check back that ADC registers have effectively been configured to */
685 /* ensure of no potential problem of ADC core peripheral clocking. */
686 if (LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
687 == hadc->Init.SamplingTimeCommon1)
688 {
689 /* Set ADC error code to none */
690 ADC_CLEAR_ERRORCODE(hadc);
691
692 /* Set the ADC state */
693 ADC_STATE_CLR_SET(hadc->State,
694 HAL_ADC_STATE_BUSY_INTERNAL,
695 HAL_ADC_STATE_READY);
696 }
697 else
698 {
699 /* Update ADC state machine to error */
700 ADC_STATE_CLR_SET(hadc->State,
701 HAL_ADC_STATE_BUSY_INTERNAL,
702 HAL_ADC_STATE_ERROR_INTERNAL);
703
704 /* Set ADC error code to ADC peripheral internal error */
705 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
706
707 tmp_hal_status = HAL_ERROR;
708 }
709
710 }
711 else
712 {
713 /* Update ADC state machine to error */
714 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
715
716 tmp_hal_status = HAL_ERROR;
717 }
718
719 return tmp_hal_status;
720 }
721
722 /**
723 * @brief Deinitialize the ADC peripheral registers to their default reset
724 * values, with deinitialization of the ADC MSP.
725 * @note For devices with several ADCs: reset of ADC common registers is done
726 * only if all ADCs sharing the same common group are disabled.
727 * (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
728 * all ADC instances use the same core clock at RCC level, disabling
729 * the core clock reset all ADC instances).
730 * If this is not the case, reset of these common parameters reset is
731 * bypassed without error reporting: it can be the intended behavior in
732 * case of reset of a single ADC while the other ADCs sharing the same
733 * common group is still running.
734 * @param hadc ADC handle
735 * @retval HAL status
736 */
HAL_ADC_DeInit(ADC_HandleTypeDef * hadc)737 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
738 {
739 HAL_StatusTypeDef tmp_hal_status;
740
741 /* Check ADC handle */
742 if (hadc == NULL)
743 {
744 return HAL_ERROR;
745 }
746
747 /* Check the parameters */
748 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
749
750 /* Set ADC state */
751 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
752
753 /* Stop potential conversion on going, on regular group */
754 tmp_hal_status = ADC_ConversionStop(hadc);
755
756 /* Disable ADC peripheral if conversions are effectively stopped */
757 if (tmp_hal_status == HAL_OK)
758 {
759 /* Disable the ADC peripheral */
760 tmp_hal_status = ADC_Disable(hadc);
761
762 /* Check if ADC is effectively disabled */
763 if (tmp_hal_status == HAL_OK)
764 {
765 /* Change ADC state */
766 hadc->State = HAL_ADC_STATE_READY;
767 }
768
769 /* Disable ADC internal voltage regulator */
770 LL_ADC_DisableInternalRegulator(hadc->Instance);
771 }
772
773 /* Note: HAL ADC deInit is done independently of ADC conversion stop */
774 /* and disable return status. In case of status fail, attempt to */
775 /* perform deinitialization anyway and it is up user code in */
776 /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
777 /* system RCC hard reset. */
778
779 /* ========== Reset ADC registers ========== */
780 /* Reset register IER */
781 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 |
782 ADC_IT_AWD1 | ADC_IT_OVR |
783 ADC_IT_EOS | ADC_IT_EOC |
784 ADC_IT_EOCAL | ADC_IT_EOSMP | ADC_IT_RDY));
785
786 /* Reset register ISR */
787 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 |
788 ADC_FLAG_AWD1 | ADC_FLAG_OVR |
789 ADC_FLAG_EOS | ADC_FLAG_EOC |
790 ADC_FLAG_EOCAL | ADC_FLAG_EOSMP | ADC_FLAG_RDY));
791
792 /* Reset register CR */
793 /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
794 /* "read-set": no direct reset applicable. */
795
796 /* Reset register CFGR1 */
797 hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN |
798 ADC_CFGR1_CHSELRMOD | ADC_CFGR1_AUTOFF |
799 ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
800 ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES |
801 ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN);
802
803 /* Reset register SMPR */
804 hadc->Instance->SMPR &= ~ADC_SMPR_SMP1;
805
806 /* Reset register CHSELR */
807 hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL);
808
809 /* Reset register DR */
810 /* bits in access mode read only, no direct reset applicable */
811
812 /* Reset registers AWDxTR */
813 hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1);
814 hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2);
815 hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3);
816
817 /* Reset register CFGR2 */
818 /* Note: CFGR2 reset done at the end of de-initialization due to */
819 /* clock source reset */
820 /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
821 /* already done above. */
822 hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
823
824 /* Reset register CCR */
825 ADC1_COMMON->CCR &= ~(ADC_CCR_VBATEN | ADC_CCR_TSEN | ADC_CCR_VREFEN | ADC_CCR_PRESC);
826
827 /* ========== Hard reset ADC peripheral ========== */
828 /* Performs a global reset of the entire ADC peripheral: ADC state is */
829 /* forced to a similar state after device power-on. */
830 /* Note: A possible implementation is to add RCC bus reset of ADC */
831 /* (for example, using macro */
832 /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
833 /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */
834 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
835 if (hadc->MspDeInitCallback == NULL)
836 {
837 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
838 }
839
840 /* DeInit the low level hardware */
841 hadc->MspDeInitCallback(hadc);
842 #else
843 /* DeInit the low level hardware */
844 HAL_ADC_MspDeInit(hadc);
845 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
846
847 /* Reset HAL ADC handle variable */
848 hadc->ADCGroupRegularSequencerRanks = 0x00000000UL;
849
850 /* Set ADC error code to none */
851 ADC_CLEAR_ERRORCODE(hadc);
852
853 /* Set ADC state */
854 hadc->State = HAL_ADC_STATE_RESET;
855
856 __HAL_UNLOCK(hadc);
857
858 return tmp_hal_status;
859 }
860
861 /**
862 * @brief Initialize the ADC MSP.
863 * @param hadc ADC handle
864 * @retval None
865 */
HAL_ADC_MspInit(ADC_HandleTypeDef * hadc)866 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
867 {
868 /* Prevent unused argument(s) compilation warning */
869 UNUSED(hadc);
870
871 /* NOTE : This function should not be modified. When the callback is needed,
872 function HAL_ADC_MspInit must be implemented in the user file.
873 */
874 }
875
876 /**
877 * @brief DeInitialize the ADC MSP.
878 * @param hadc ADC handle
879 * @note All ADC instances use the same core clock at RCC level, disabling
880 * the core clock reset all ADC instances).
881 * @retval None
882 */
HAL_ADC_MspDeInit(ADC_HandleTypeDef * hadc)883 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
884 {
885 /* Prevent unused argument(s) compilation warning */
886 UNUSED(hadc);
887
888 /* NOTE : This function should not be modified. When the callback is needed,
889 function HAL_ADC_MspDeInit must be implemented in the user file.
890 */
891 }
892
893 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
894 /**
895 * @brief Register a User ADC Callback
896 * To be used instead of the weak predefined callback
897 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
898 * the configuration information for the specified ADC.
899 * @param CallbackID ID of the callback to be registered
900 * This parameter can be one of the following values:
901 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
902 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
903 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
904 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
905 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
906 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
907 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
908 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
909 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
910 * @arg @ref HAL_ADC_END_OF_CALIBRATION_CB_ID ADC end of calibration callback ID
911 * @arg @ref HAL_ADC_ADC_READY_CB_ID ADC Ready callback ID
912 * @arg @ref HAL_ADC_CONFIG_CHANNEL_ID ADC config channel callback ID
913 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
914 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
915 * @param pCallback pointer to the Callback function
916 * @retval HAL status
917 */
HAL_ADC_RegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID,pADC_CallbackTypeDef pCallback)918 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
919 pADC_CallbackTypeDef pCallback)
920 {
921 HAL_StatusTypeDef status = HAL_OK;
922
923 if (pCallback == NULL)
924 {
925 /* Update the error code */
926 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
927
928 return HAL_ERROR;
929 }
930
931 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
932 {
933 switch (CallbackID)
934 {
935 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
936 hadc->ConvCpltCallback = pCallback;
937 break;
938
939 case HAL_ADC_CONVERSION_HALF_CB_ID :
940 hadc->ConvHalfCpltCallback = pCallback;
941 break;
942
943 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
944 hadc->LevelOutOfWindowCallback = pCallback;
945 break;
946
947 case HAL_ADC_ERROR_CB_ID :
948 hadc->ErrorCallback = pCallback;
949 break;
950
951 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
952 hadc->LevelOutOfWindow2Callback = pCallback;
953 break;
954
955 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
956 hadc->LevelOutOfWindow3Callback = pCallback;
957 break;
958
959 case HAL_ADC_END_OF_SAMPLING_CB_ID :
960 hadc->EndOfSamplingCallback = pCallback;
961 break;
962
963 case HAL_ADC_END_OF_CALIBRATION_CB_ID :
964 hadc->CalibrationCpltCallback = pCallback;
965 break;
966
967 case HAL_ADC_ADC_READY_CB_ID :
968 hadc->ADCReadyCallback = pCallback;
969 break;
970
971 case HAL_ADC_CONFIG_CHANNEL_ID :
972 hadc->ChannelConfigReadyCallback = pCallback;
973 break;
974 case HAL_ADC_MSPINIT_CB_ID :
975 hadc->MspInitCallback = pCallback;
976 break;
977
978 case HAL_ADC_MSPDEINIT_CB_ID :
979 hadc->MspDeInitCallback = pCallback;
980 break;
981
982 default :
983 /* Update the error code */
984 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
985
986 /* Return error status */
987 status = HAL_ERROR;
988 break;
989 }
990 }
991 else if (HAL_ADC_STATE_RESET == hadc->State)
992 {
993 switch (CallbackID)
994 {
995 case HAL_ADC_MSPINIT_CB_ID :
996 hadc->MspInitCallback = pCallback;
997 break;
998
999 case HAL_ADC_MSPDEINIT_CB_ID :
1000 hadc->MspDeInitCallback = pCallback;
1001 break;
1002
1003 default :
1004 /* Update the error code */
1005 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1006
1007 /* Return error status */
1008 status = HAL_ERROR;
1009 break;
1010 }
1011 }
1012 else
1013 {
1014 /* Update the error code */
1015 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1016
1017 /* Return error status */
1018 status = HAL_ERROR;
1019 }
1020
1021 return status;
1022 }
1023
1024 /**
1025 * @brief Unregister a ADC Callback
1026 * ADC callback is redirected to the weak predefined callback
1027 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
1028 * the configuration information for the specified ADC.
1029 * @param CallbackID ID of the callback to be unregistered
1030 * This parameter can be one of the following values:
1031 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
1032 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
1033 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
1034 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
1035 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
1036 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
1037 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
1038 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
1039 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
1040 * @arg @ref HAL_ADC_END_OF_CALIBRATION_CB_ID ADC end of calibration callback ID
1041 * @arg @ref HAL_ADC_ADC_READY_CB_ID ADC Ready callback ID
1042 * @arg @ref HAL_ADC_CONFIG_CHANNEL_ID ADC config channel callback ID
1043 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
1044 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
1045 * @retval HAL status
1046 */
HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID)1047 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
1048 {
1049 HAL_StatusTypeDef status = HAL_OK;
1050
1051 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
1052 {
1053 switch (CallbackID)
1054 {
1055 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
1056 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
1057 break;
1058
1059 case HAL_ADC_CONVERSION_HALF_CB_ID :
1060 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
1061 break;
1062
1063 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
1064 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
1065 break;
1066
1067 case HAL_ADC_ERROR_CB_ID :
1068 hadc->ErrorCallback = HAL_ADC_ErrorCallback;
1069 break;
1070
1071 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
1072 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
1073 break;
1074
1075 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
1076 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
1077 break;
1078
1079 case HAL_ADC_END_OF_SAMPLING_CB_ID :
1080 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
1081 break;
1082 case HAL_ADC_END_OF_CALIBRATION_CB_ID :
1083 hadc->CalibrationCpltCallback = HAL_ADC_CalibrationCpltCallback;
1084 break;
1085
1086 case HAL_ADC_ADC_READY_CB_ID :
1087 hadc->ADCReadyCallback = HAL_ADC_ADCReadyCallback;
1088 break;
1089
1090 case HAL_ADC_CONFIG_CHANNEL_ID :
1091 hadc->ChannelConfigReadyCallback = HAL_ADCEx_ChannelConfigReadyCallback;
1092 break;
1093
1094 case HAL_ADC_MSPINIT_CB_ID :
1095 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
1096 break;
1097
1098 case HAL_ADC_MSPDEINIT_CB_ID :
1099 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1100 break;
1101
1102 default :
1103 /* Update the error code */
1104 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1105
1106 /* Return error status */
1107 status = HAL_ERROR;
1108 break;
1109 }
1110 }
1111 else if (HAL_ADC_STATE_RESET == hadc->State)
1112 {
1113 switch (CallbackID)
1114 {
1115 case HAL_ADC_MSPINIT_CB_ID :
1116 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
1117 break;
1118
1119 case HAL_ADC_MSPDEINIT_CB_ID :
1120 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1121 break;
1122
1123 default :
1124 /* Update the error code */
1125 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1126
1127 /* Return error status */
1128 status = HAL_ERROR;
1129 break;
1130 }
1131 }
1132 else
1133 {
1134 /* Update the error code */
1135 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1136
1137 /* Return error status */
1138 status = HAL_ERROR;
1139 }
1140
1141 return status;
1142 }
1143
1144 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1145
1146 /**
1147 * @}
1148 */
1149
1150 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
1151 * @brief ADC IO operation functions
1152 *
1153 @verbatim
1154 ===============================================================================
1155 ##### IO operation functions #####
1156 ===============================================================================
1157 [..] This section provides functions allowing to:
1158 (+) Start conversion of regular group.
1159 (+) Stop conversion of regular group.
1160 (+) Poll for conversion complete on regular group.
1161 (+) Poll for conversion event.
1162 (+) Get result of regular channel conversion.
1163 (+) Start conversion of regular group and enable interruptions.
1164 (+) Stop conversion of regular group and disable interruptions.
1165 (+) Handle ADC interrupt request
1166 (+) Start conversion of regular group and enable DMA transfer.
1167 (+) Stop conversion of regular group and disable ADC DMA transfer.
1168 @endverbatim
1169 * @{
1170 */
1171
1172 /**
1173 * @brief Enable ADC, start conversion of regular group.
1174 * @note Interruptions enabled in this function: None.
1175 * @param hadc ADC handle
1176 * @retval HAL status
1177 */
HAL_ADC_Start(ADC_HandleTypeDef * hadc)1178 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
1179 {
1180 HAL_StatusTypeDef tmp_hal_status;
1181
1182 /* Check the parameters */
1183 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1184
1185 /* Perform ADC enable and conversion start if no conversion is on going */
1186 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1187 {
1188 __HAL_LOCK(hadc);
1189
1190 /* Enable the ADC peripheral */
1191 tmp_hal_status = ADC_Enable(hadc);
1192
1193 /* Start conversion if ADC is effectively enabled */
1194 if (tmp_hal_status == HAL_OK)
1195 {
1196 /* Set ADC state */
1197 /* - Clear state bitfield related to regular group conversion results */
1198 /* - Set state bitfield related to regular operation */
1199 ADC_STATE_CLR_SET(hadc->State,
1200 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1201 HAL_ADC_STATE_REG_BUSY);
1202
1203 /* Set ADC error code */
1204 /* Reset all ADC error code fields */
1205 ADC_CLEAR_ERRORCODE(hadc);
1206
1207 /* Clear ADC group regular conversion flag and overrun flag */
1208 /* (To ensure of no unknown state from potential previous ADC operations) */
1209 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1210
1211 /* Process unlocked */
1212 /* Unlock before starting ADC conversions: in case of potential */
1213 /* interruption, to let the process to ADC IRQ Handler. */
1214 __HAL_UNLOCK(hadc);
1215
1216 /* Enable conversion of regular group. */
1217 /* If software start has been selected, conversion starts immediately. */
1218 /* If external trigger has been selected, conversion will start at next */
1219 /* trigger event. */
1220 /* Start ADC group regular conversion */
1221 LL_ADC_REG_StartConversion(hadc->Instance);
1222 }
1223 else
1224 {
1225 __HAL_UNLOCK(hadc);
1226 }
1227 }
1228 else
1229 {
1230 tmp_hal_status = HAL_BUSY;
1231 }
1232
1233 return tmp_hal_status;
1234 }
1235
1236 /**
1237 * @brief Stop ADC conversion of regular group (and injected channels in
1238 * case of auto_injection mode), disable ADC peripheral.
1239 * @note: ADC peripheral disable is forcing stop of potential
1240 * conversion on injected group. If injected group is under use, it
1241 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1242 * @param hadc ADC handle
1243 * @retval HAL status.
1244 */
HAL_ADC_Stop(ADC_HandleTypeDef * hadc)1245 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
1246 {
1247 HAL_StatusTypeDef tmp_hal_status;
1248
1249 /* Check the parameters */
1250 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1251
1252 __HAL_LOCK(hadc);
1253
1254 /* 1. Stop potential conversion on going, on ADC group regular */
1255 tmp_hal_status = ADC_ConversionStop(hadc);
1256
1257 /* Disable ADC peripheral if conversions are effectively stopped */
1258 if (tmp_hal_status == HAL_OK)
1259 {
1260 /* 2. Disable the ADC peripheral */
1261 tmp_hal_status = ADC_Disable(hadc);
1262
1263 /* Check if ADC is effectively disabled */
1264 if (tmp_hal_status == HAL_OK)
1265 {
1266 /* Set ADC state */
1267 ADC_STATE_CLR_SET(hadc->State,
1268 HAL_ADC_STATE_REG_BUSY,
1269 HAL_ADC_STATE_READY);
1270 }
1271 }
1272
1273 __HAL_UNLOCK(hadc);
1274
1275 return tmp_hal_status;
1276 }
1277
1278 /**
1279 * @brief Wait for regular group conversion to be completed.
1280 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
1281 * conversion) are cleared by this function, with an exception:
1282 * if low power feature "LowPowerAutoWait" is enabled, flags are
1283 * not cleared to not interfere with this feature until data register
1284 * is read using function HAL_ADC_GetValue().
1285 * @note This function cannot be used in a particular setup: ADC configured
1286 * in DMA mode and polling for end of each conversion (ADC init
1287 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
1288 * In this case, DMA resets the flag EOC and polling cannot be
1289 * performed on each conversion. Nevertheless, polling can still
1290 * be performed on the complete sequence (ADC init
1291 * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
1292 * @param hadc ADC handle
1293 * @param Timeout Timeout value in millisecond.
1294 * @retval HAL status
1295 */
HAL_ADC_PollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)1296 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
1297 {
1298 uint32_t tickstart;
1299 uint32_t tmp_flag_end;
1300
1301 /* Check the parameters */
1302 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1303
1304 /* If end of conversion selected to end of sequence conversions */
1305 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
1306 {
1307 tmp_flag_end = ADC_FLAG_EOS;
1308 }
1309 /* If end of conversion selected to end of unitary conversion */
1310 else /* ADC_EOC_SINGLE_CONV */
1311 {
1312 /* Verification that ADC configuration is compliant with polling for */
1313 /* each conversion: */
1314 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
1315 /* several ranks and polling for end of each conversion. */
1316 /* For code simplicity sake, this particular case is generalized to */
1317 /* ADC configured in DMA mode and and polling for end of each conversion. */
1318 if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) != 0UL)
1319 {
1320 /* Update ADC state machine to error */
1321 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1322
1323 return HAL_ERROR;
1324 }
1325 else
1326 {
1327 tmp_flag_end = (ADC_FLAG_EOC);
1328 }
1329 }
1330
1331 /* Get tick count */
1332 tickstart = HAL_GetTick();
1333
1334 /* Wait until End of unitary conversion or sequence conversions flag is raised */
1335 while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
1336 {
1337 /* Check if timeout is disabled (set to infinite wait) */
1338 if (Timeout != HAL_MAX_DELAY)
1339 {
1340 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
1341 {
1342 /* New check to avoid false timeout detection in case of preemption */
1343 if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
1344 {
1345 /* Update ADC state machine to timeout */
1346 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1347
1348 __HAL_UNLOCK(hadc);
1349
1350 return HAL_TIMEOUT;
1351 }
1352 }
1353 }
1354 }
1355
1356 /* Update ADC state machine */
1357 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1358
1359 /* Determine whether any further conversion upcoming on group regular */
1360 /* by external trigger, continuous mode or scan sequence on going. */
1361 if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
1362 && (hadc->Init.ContinuousConvMode == DISABLE)
1363 )
1364 {
1365 /* Check whether end of sequence is reached */
1366 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
1367 {
1368 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
1369 /* ADSTART==0 (no conversion on going) */
1370 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1371 {
1372 /* Disable ADC end of single conversion interrupt on group regular */
1373 /* Note: Overrun interrupt was enabled with EOC interrupt in */
1374 /* HAL_Start_IT(), but is not disabled here because can be used */
1375 /* by overrun IRQ process below. */
1376 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
1377
1378 /* Set ADC state */
1379 ADC_STATE_CLR_SET(hadc->State,
1380 HAL_ADC_STATE_REG_BUSY,
1381 HAL_ADC_STATE_READY);
1382 }
1383 else
1384 {
1385 /* Change ADC state to error state */
1386 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1387
1388 /* Set ADC error code to ADC peripheral internal error */
1389 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
1390 }
1391 }
1392 }
1393
1394 /* Clear end of conversion flag of regular group if low power feature */
1395 /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
1396 /* until data register is read using function HAL_ADC_GetValue(). */
1397 if (hadc->Init.LowPowerAutoWait == DISABLE)
1398 {
1399 /* Clear regular group conversion flag */
1400 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
1401 }
1402
1403 /* Return function status */
1404 return HAL_OK;
1405 }
1406
1407 /**
1408 * @brief Poll for ADC event.
1409 * @param hadc ADC handle
1410 * @param EventType the ADC event type.
1411 * This parameter can be one of the following values:
1412 * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
1413 * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on
1414 * all STM32 series)
1415 * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on
1416 * all STM32 series)
1417 * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on
1418 * all STM32 series)
1419 * @arg @ref ADC_OVR_EVENT ADC Overrun event
1420 * @param Timeout Timeout value in millisecond.
1421 * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
1422 * Indeed, the latter is reset only if hadc->Init.Overrun field is set
1423 * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
1424 * by a new converted data as soon as OVR is cleared.
1425 * To reset OVR flag once the preserved data is retrieved, the user can resort
1426 * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1427 * @retval HAL status
1428 */
HAL_ADC_PollForEvent(ADC_HandleTypeDef * hadc,uint32_t EventType,uint32_t Timeout)1429 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
1430 {
1431 uint32_t tickstart;
1432
1433 /* Check the parameters */
1434 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1435 assert_param(IS_ADC_EVENT_TYPE(EventType));
1436
1437 /* Get tick count */
1438 tickstart = HAL_GetTick();
1439
1440 /* Check selected event flag */
1441 while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
1442 {
1443 /* Check if timeout is disabled (set to infinite wait) */
1444 if (Timeout != HAL_MAX_DELAY)
1445 {
1446 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
1447 {
1448 /* New check to avoid false timeout detection in case of preemption */
1449 if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
1450 {
1451 /* Update ADC state machine to timeout */
1452 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1453
1454 __HAL_UNLOCK(hadc);
1455
1456 return HAL_TIMEOUT;
1457 }
1458 }
1459 }
1460 }
1461
1462 switch (EventType)
1463 {
1464 /* End Of Sampling event */
1465 case ADC_EOSMP_EVENT:
1466 /* Set ADC state */
1467 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
1468
1469 /* Clear the End Of Sampling flag */
1470 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
1471
1472 break;
1473
1474 /* Analog watchdog (level out of window) event */
1475 /* Note: In case of several analog watchdog enabled, if needed to know */
1476 /* which one triggered and on which ADCx, test ADC state of analog watchdog */
1477 /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
1478 /* For example: */
1479 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
1480 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
1481 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
1482
1483 /* Check analog watchdog 1 flag */
1484 case ADC_AWD_EVENT:
1485 /* Set ADC state */
1486 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1487
1488 /* Clear ADC analog watchdog flag */
1489 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
1490
1491 break;
1492
1493 /* Check analog watchdog 2 flag */
1494 case ADC_AWD2_EVENT:
1495 /* Set ADC state */
1496 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
1497
1498 /* Clear ADC analog watchdog flag */
1499 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
1500
1501 break;
1502
1503 /* Check analog watchdog 3 flag */
1504 case ADC_AWD3_EVENT:
1505 /* Set ADC state */
1506 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
1507
1508 /* Clear ADC analog watchdog flag */
1509 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
1510
1511 break;
1512
1513 /* Overrun event */
1514 default: /* Case ADC_OVR_EVENT */
1515 /* If overrun is set to overwrite previous data, overrun event is not */
1516 /* considered as an error. */
1517 /* (cf ref manual "Managing conversions without using the DMA and without */
1518 /* overrun ") */
1519 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1520 {
1521 /* Set ADC state */
1522 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
1523
1524 /* Set ADC error code to overrun */
1525 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1526 }
1527 else
1528 {
1529 /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
1530 otherwise, data register is potentially overwritten by new converted data as soon
1531 as OVR is cleared. */
1532 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1533 }
1534 break;
1535 }
1536
1537 /* Return function status */
1538 return HAL_OK;
1539 }
1540
1541 /**
1542 * @brief Enable ADC, start conversion of regular group with interruption.
1543 * @note Interruptions enabled in this function according to initialization
1544 * setting : EOC (end of conversion), EOS (end of sequence),
1545 * OVR overrun.
1546 * Each of these interruptions has its dedicated callback function.
1547 * @note To guarantee a proper reset of all interruptions once all the needed
1548 * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
1549 * a correct stop of the IT-based conversions.
1550 * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
1551 * interruption. If required (e.g. in case of oversampling with trigger
1552 * mode), the user must:
1553 * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
1554 * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
1555 * before calling HAL_ADC_Start_IT().
1556 * @param hadc ADC handle
1557 * @retval HAL status
1558 */
HAL_ADC_Start_IT(ADC_HandleTypeDef * hadc)1559 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
1560 {
1561 HAL_StatusTypeDef tmp_hal_status;
1562
1563 /* Check the parameters */
1564 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1565
1566 /* Perform ADC enable and conversion start if no conversion is on going */
1567 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1568 {
1569 __HAL_LOCK(hadc);
1570
1571 /* Enable the ADC peripheral */
1572 tmp_hal_status = ADC_Enable(hadc);
1573
1574 /* Start conversion if ADC is effectively enabled */
1575 if (tmp_hal_status == HAL_OK)
1576 {
1577 /* Set ADC state */
1578 /* - Clear state bitfield related to regular group conversion results */
1579 /* - Set state bitfield related to regular operation */
1580 ADC_STATE_CLR_SET(hadc->State,
1581 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1582 HAL_ADC_STATE_REG_BUSY);
1583
1584
1585 /* Set ADC error code */
1586 /* Reset all ADC error code fields */
1587 ADC_CLEAR_ERRORCODE(hadc);
1588
1589 /* Clear ADC group regular conversion flag and overrun flag */
1590 /* (To ensure of no unknown state from potential previous ADC operations) */
1591 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1592
1593 /* Process unlocked */
1594 /* Unlock before starting ADC conversions: in case of potential */
1595 /* interruption, to let the process to ADC IRQ Handler. */
1596 __HAL_UNLOCK(hadc);
1597
1598 /* Disable all interruptions before enabling the desired ones */
1599 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1600
1601 /* Enable ADC end of conversion interrupt */
1602 switch (hadc->Init.EOCSelection)
1603 {
1604 case ADC_EOC_SEQ_CONV:
1605 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
1606 break;
1607 /* case ADC_EOC_SINGLE_CONV */
1608 default:
1609 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
1610 break;
1611 }
1612
1613 /* Enable ADC overrun interrupt */
1614 /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
1615 ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
1616 behavior and no CPU time is lost for a non-processed interruption */
1617 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1618 {
1619 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1620 }
1621
1622 /* Enable conversion of regular group. */
1623 /* If software start has been selected, conversion starts immediately. */
1624 /* If external trigger has been selected, conversion will start at next */
1625 /* trigger event. */
1626 /* Start ADC group regular conversion */
1627 LL_ADC_REG_StartConversion(hadc->Instance);
1628 }
1629 else
1630 {
1631 __HAL_UNLOCK(hadc);
1632 }
1633
1634 }
1635 else
1636 {
1637 tmp_hal_status = HAL_BUSY;
1638 }
1639
1640 return tmp_hal_status;
1641 }
1642
1643 /**
1644 * @brief Stop ADC conversion of regular group (and injected group in
1645 * case of auto_injection mode), disable interrution of
1646 * end-of-conversion, disable ADC peripheral.
1647 * @param hadc ADC handle
1648 * @retval HAL status.
1649 */
HAL_ADC_Stop_IT(ADC_HandleTypeDef * hadc)1650 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
1651 {
1652 HAL_StatusTypeDef tmp_hal_status;
1653
1654 /* Check the parameters */
1655 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1656
1657 __HAL_LOCK(hadc);
1658
1659 /* 1. Stop potential conversion on going, on ADC group regular */
1660 tmp_hal_status = ADC_ConversionStop(hadc);
1661
1662 /* Disable ADC peripheral if conversions are effectively stopped */
1663 if (tmp_hal_status == HAL_OK)
1664 {
1665 /* Disable ADC end of conversion interrupt for regular group */
1666 /* Disable ADC overrun interrupt */
1667 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1668
1669 /* 2. Disable the ADC peripheral */
1670 tmp_hal_status = ADC_Disable(hadc);
1671
1672 /* Check if ADC is effectively disabled */
1673 if (tmp_hal_status == HAL_OK)
1674 {
1675 /* Set ADC state */
1676 ADC_STATE_CLR_SET(hadc->State,
1677 HAL_ADC_STATE_REG_BUSY,
1678 HAL_ADC_STATE_READY);
1679 }
1680 }
1681
1682 __HAL_UNLOCK(hadc);
1683
1684 return tmp_hal_status;
1685 }
1686
1687 /**
1688 * @brief Enable ADC, start conversion of regular group and transfer result through DMA.
1689 * @note Interruptions enabled in this function:
1690 * overrun (if applicable), DMA half transfer, DMA transfer complete.
1691 * Each of these interruptions has its dedicated callback function.
1692 * @param hadc ADC handle
1693 * @param pData Destination Buffer address.
1694 * @param Length Number of data to be transferred from ADC peripheral to memory
1695 * @retval HAL status.
1696 */
HAL_ADC_Start_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)1697 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
1698 {
1699 HAL_StatusTypeDef tmp_hal_status;
1700
1701 /* Check the parameters */
1702 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1703
1704 /* Perform ADC enable and conversion start if no conversion is on going */
1705 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1706 {
1707 __HAL_LOCK(hadc);
1708
1709 /* Specific case for first call occurrence of this function (DMA transfer */
1710 /* not activated and ADC disabled), DMA transfer must be activated */
1711 /* with ADC disabled. */
1712 if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) == 0UL)
1713 {
1714 if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
1715 {
1716 /* Disable ADC */
1717 LL_ADC_Disable(hadc->Instance);
1718 }
1719
1720 /* Enable ADC DMA mode */
1721 hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN;
1722 }
1723
1724 /* Enable the ADC peripheral */
1725 tmp_hal_status = ADC_Enable(hadc);
1726
1727 /* Start conversion if ADC is effectively enabled */
1728 if (tmp_hal_status == HAL_OK)
1729 {
1730 /* Set ADC state */
1731 /* - Clear state bitfield related to regular group conversion results */
1732 /* - Set state bitfield related to regular operation */
1733 ADC_STATE_CLR_SET(hadc->State,
1734 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1735 HAL_ADC_STATE_REG_BUSY);
1736
1737 /* Set ADC error code */
1738 /* Reset all ADC error code fields */
1739 ADC_CLEAR_ERRORCODE(hadc);
1740
1741 /* Set the DMA transfer complete callback */
1742 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
1743
1744 /* Set the DMA half transfer complete callback */
1745 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
1746
1747 /* Set the DMA error callback */
1748 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
1749
1750
1751 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
1752 /* start (in case of SW start): */
1753
1754 /* Clear regular group conversion flag and overrun flag */
1755 /* (To ensure of no unknown state from potential previous ADC */
1756 /* operations) */
1757 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1758
1759 /* Process unlocked */
1760 /* Unlock before starting ADC conversions: in case of potential */
1761 /* interruption, to let the process to ADC IRQ Handler. */
1762 __HAL_UNLOCK(hadc);
1763
1764 /* Enable ADC overrun interrupt */
1765 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1766
1767 /* Start the DMA channel */
1768 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
1769
1770 /* Enable conversion of regular group. */
1771 /* If software start has been selected, conversion starts immediately. */
1772 /* If external trigger has been selected, conversion will start at next */
1773 /* trigger event. */
1774 /* Start ADC group regular conversion */
1775 LL_ADC_REG_StartConversion(hadc->Instance);
1776 }
1777 }
1778 else
1779 {
1780 tmp_hal_status = HAL_BUSY;
1781 }
1782
1783 return tmp_hal_status;
1784 }
1785
1786 /**
1787 * @brief Stop ADC conversion of regular group (and injected group in
1788 * case of auto_injection mode), disable ADC DMA transfer, disable
1789 * ADC peripheral.
1790 * @param hadc ADC handle
1791 * @retval HAL status.
1792 */
HAL_ADC_Stop_DMA(ADC_HandleTypeDef * hadc)1793 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
1794 {
1795 HAL_StatusTypeDef tmp_hal_status;
1796
1797 /* Check the parameters */
1798 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1799
1800 __HAL_LOCK(hadc);
1801
1802 /* 1. Stop potential ADC group regular conversion on going */
1803 tmp_hal_status = ADC_ConversionStop(hadc);
1804
1805 /* Disable ADC peripheral if conversions are effectively stopped */
1806 if (tmp_hal_status == HAL_OK)
1807 {
1808 /* Disable the DMA channel (in case of DMA in circular mode or stop */
1809 /* while DMA transfer is on going) */
1810 if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
1811 {
1812 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1813
1814 /* Check if DMA channel effectively disabled */
1815 if (tmp_hal_status != HAL_OK)
1816 {
1817 /* Update ADC state machine to error */
1818 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1819 }
1820 }
1821
1822 /* Disable ADC overrun interrupt */
1823 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1824
1825 /* 2. Disable the ADC peripheral */
1826 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
1827 /* to keep in memory a potential failing status. */
1828 if (tmp_hal_status == HAL_OK)
1829 {
1830 tmp_hal_status = ADC_Disable(hadc);
1831 }
1832 else
1833 {
1834 (void)ADC_Disable(hadc);
1835 }
1836
1837 /* Check if ADC is effectively disabled */
1838 if (tmp_hal_status == HAL_OK)
1839 {
1840 /* Set ADC state */
1841 ADC_STATE_CLR_SET(hadc->State,
1842 HAL_ADC_STATE_REG_BUSY,
1843 HAL_ADC_STATE_READY);
1844 }
1845
1846 /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
1847 CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
1848 }
1849
1850 __HAL_UNLOCK(hadc);
1851
1852 return tmp_hal_status;
1853 }
1854
1855 /**
1856 * @brief Get ADC regular group conversion result.
1857 * @note Reading register DR automatically clears ADC flag EOC
1858 * (ADC group regular end of unitary conversion).
1859 * @note This function does not clear ADC flag EOS
1860 * (ADC group regular end of sequence conversion).
1861 * Occurrence of flag EOS rising:
1862 * - If sequencer is composed of 1 rank, flag EOS is equivalent
1863 * to flag EOC.
1864 * - If sequencer is composed of several ranks, during the scan
1865 * sequence flag EOC only is raised, at the end of the scan sequence
1866 * both flags EOC and EOS are raised.
1867 * To clear this flag, either use function:
1868 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
1869 * model polling: @ref HAL_ADC_PollForConversion()
1870 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
1871 * @param hadc ADC handle
1872 * @retval ADC group regular conversion data
1873 */
HAL_ADC_GetValue(const ADC_HandleTypeDef * hadc)1874 uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
1875 {
1876 /* Check the parameters */
1877 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1878
1879 /* Note: EOC flag is not cleared here by software because automatically */
1880 /* cleared by hardware when reading register DR. */
1881
1882 /* Return ADC converted value */
1883 return hadc->Instance->DR;
1884 }
1885
1886 /**
1887 * @brief Handle ADC interrupt request.
1888 * @param hadc ADC handle
1889 * @retval None
1890 */
HAL_ADC_IRQHandler(ADC_HandleTypeDef * hadc)1891 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
1892 {
1893 uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
1894 uint32_t tmp_isr = hadc->Instance->ISR;
1895 uint32_t tmp_ier = hadc->Instance->IER;
1896
1897 /* Check the parameters */
1898 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1899 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
1900
1901 /* ========== Check End of Sampling flag for ADC group regular ========== */
1902 if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
1903 {
1904 /* Update state machine on end of sampling status if not in error state */
1905 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
1906 {
1907 /* Set ADC state */
1908 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
1909 }
1910
1911 /* End Of Sampling callback */
1912 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1913 hadc->EndOfSamplingCallback(hadc);
1914 #else
1915 HAL_ADCEx_EndOfSamplingCallback(hadc);
1916 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1917
1918 /* Clear regular group conversion flag */
1919 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
1920 }
1921
1922 /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
1923 if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
1924 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
1925 {
1926 /* Update state machine on conversion status if not in error state */
1927 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
1928 {
1929 /* Set ADC state */
1930 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1931 }
1932
1933 /* Determine whether any further conversion upcoming on group regular */
1934 /* by external trigger, continuous mode or scan sequence on going */
1935 /* to disable interruption. */
1936 if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
1937 && (hadc->Init.ContinuousConvMode == DISABLE)
1938 )
1939 {
1940 /* If End of Sequence is reached, disable interrupts */
1941 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
1942 {
1943 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
1944 /* ADSTART==0 (no conversion on going) */
1945 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1946 {
1947 /* Disable ADC end of single conversion interrupt on group regular */
1948 /* Note: Overrun interrupt was enabled with EOC interrupt in */
1949 /* HAL_Start_IT(), but is not disabled here because can be used */
1950 /* by overrun IRQ process below. */
1951 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
1952
1953 /* Set ADC state */
1954 ADC_STATE_CLR_SET(hadc->State,
1955 HAL_ADC_STATE_REG_BUSY,
1956 HAL_ADC_STATE_READY);
1957 }
1958 else
1959 {
1960 /* Change ADC state to error state */
1961 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1962
1963 /* Set ADC error code to ADC peripheral internal error */
1964 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
1965 }
1966 }
1967 }
1968
1969 /* Conversion complete callback */
1970 /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
1971 /* to determine if conversion has been triggered from EOC or EOS, */
1972 /* possibility to use: */
1973 /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
1974 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1975 hadc->ConvCpltCallback(hadc);
1976 #else
1977 HAL_ADC_ConvCpltCallback(hadc);
1978 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1979
1980 /* Clear regular group conversion flag */
1981 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
1982 /* conversion flags clear induces the release of the preserved data.*/
1983 /* Therefore, if the preserved data value is needed, it must be */
1984 /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
1985 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
1986 }
1987
1988 /* ========== Check Analog watchdog 1 flag ========== */
1989 if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
1990 {
1991 /* Set ADC state */
1992 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1993
1994 /* Level out of window 1 callback */
1995 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1996 hadc->LevelOutOfWindowCallback(hadc);
1997 #else
1998 HAL_ADC_LevelOutOfWindowCallback(hadc);
1999 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2000
2001 /* Clear ADC analog watchdog flag */
2002 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
2003 }
2004
2005 /* ========== Check analog watchdog 2 flag ========== */
2006 if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
2007 {
2008 /* Set ADC state */
2009 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
2010
2011 /* Level out of window 2 callback */
2012 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2013 hadc->LevelOutOfWindow2Callback(hadc);
2014 #else
2015 HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
2016 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2017
2018 /* Clear ADC analog watchdog flag */
2019 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
2020 }
2021
2022 /* ========== Check analog watchdog 3 flag ========== */
2023 if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
2024 {
2025 /* Set ADC state */
2026 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
2027
2028 /* Level out of window 3 callback */
2029 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2030 hadc->LevelOutOfWindow3Callback(hadc);
2031 #else
2032 HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
2033 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2034
2035 /* Clear ADC analog watchdog flag */
2036 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
2037 }
2038
2039 /* ========== Check Overrun flag ========== */
2040 if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
2041 {
2042 /* If overrun is set to overwrite previous data (default setting), */
2043 /* overrun event is not considered as an error. */
2044 /* (cf ref manual "Managing conversions without using the DMA and without */
2045 /* overrun ") */
2046 /* Exception for usage with DMA overrun event always considered as an */
2047 /* error. */
2048 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
2049 {
2050 overrun_error = 1UL;
2051 }
2052 else
2053 {
2054 /* Check DMA configuration */
2055 if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE)
2056 {
2057 overrun_error = 1UL;
2058 }
2059 }
2060
2061 if (overrun_error == 1UL)
2062 {
2063 /* Change ADC state to error state */
2064 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
2065
2066 /* Set ADC error code to overrun */
2067 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
2068
2069 /* Error callback */
2070 /* Note: In case of overrun, ADC conversion data is preserved until */
2071 /* flag OVR is reset. */
2072 /* Therefore, old ADC conversion data can be retrieved in */
2073 /* function "HAL_ADC_ErrorCallback()". */
2074 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2075 hadc->ErrorCallback(hadc);
2076 #else
2077 HAL_ADC_ErrorCallback(hadc);
2078 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2079 }
2080
2081 /* Clear ADC overrun flag */
2082 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
2083 }
2084
2085 /* ========== Check ADC Ready flag ========== */
2086 if (((tmp_isr & ADC_FLAG_RDY) == ADC_FLAG_RDY) && ((tmp_ier & ADC_IT_RDY) == ADC_IT_RDY))
2087 {
2088 /* Update state machine on end of sampling status if not in error state */
2089 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2090 {
2091 /* Set ADC state */
2092 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2093 }
2094
2095 /* ADC Ready callback */
2096 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2097 hadc->ADCReadyCallback(hadc);
2098 #else
2099 HAL_ADC_ADCReadyCallback(hadc);
2100 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2101
2102 /* Leave ADRDY flag up (used by HAL), disable interrupt source instead */
2103 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_RDY);
2104 }
2105
2106 /* ========== Check End of Calibration flag ========== */
2107 if (((tmp_isr & ADC_FLAG_EOCAL) == ADC_FLAG_EOCAL) && ((tmp_ier & ADC_IT_EOCAL) == ADC_IT_EOCAL))
2108 {
2109 /* End Of Calibration callback */
2110 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2111 hadc->CalibrationCpltCallback(hadc);
2112 #else
2113 HAL_ADC_CalibrationCpltCallback(hadc);
2114 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2115
2116 /* Clear end of calibration flag */
2117 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOCAL);
2118 }
2119
2120 /* ========== Check channel configuration ready flag ========== */
2121 if (((tmp_isr & ADC_FLAG_CCRDY) == ADC_FLAG_CCRDY) && ((tmp_ier & ADC_IT_CCRDY) == ADC_IT_CCRDY))
2122 {
2123 /* Channel configuration ready callback */
2124 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2125 hadc->ChannelConfigReadyCallback(hadc);
2126 #else
2127 HAL_ADCEx_ChannelConfigReadyCallback(hadc);
2128 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2129
2130 /* Clear ADC analog watchdog flag */
2131 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_CCRDY);
2132 }
2133 }
2134
2135 /**
2136 * @brief Conversion complete callback in non-blocking mode.
2137 * @param hadc ADC handle
2138 * @retval None
2139 */
HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef * hadc)2140 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
2141 {
2142 /* Prevent unused argument(s) compilation warning */
2143 UNUSED(hadc);
2144
2145 /* NOTE : This function should not be modified. When the callback is needed,
2146 function HAL_ADC_ConvCpltCallback must be implemented in the user file.
2147 */
2148 }
2149
2150 /**
2151 * @brief Conversion DMA half-transfer callback in non-blocking mode.
2152 * @param hadc ADC handle
2153 * @retval None
2154 */
HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef * hadc)2155 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
2156 {
2157 /* Prevent unused argument(s) compilation warning */
2158 UNUSED(hadc);
2159
2160 /* NOTE : This function should not be modified. When the callback is needed,
2161 function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
2162 */
2163 }
2164
2165 /**
2166 * @brief Analog watchdog 1 callback in non-blocking mode.
2167 * @param hadc ADC handle
2168 * @retval None
2169 */
HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef * hadc)2170 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
2171 {
2172 /* Prevent unused argument(s) compilation warning */
2173 UNUSED(hadc);
2174
2175 /* NOTE : This function should not be modified. When the callback is needed,
2176 function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
2177 */
2178 }
2179
2180 /**
2181 * @brief ADC error callback in non-blocking mode
2182 * (ADC conversion with interruption or transfer by DMA).
2183 * @note In case of error due to overrun when using ADC with DMA transfer
2184 * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
2185 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
2186 * - If needed, restart a new ADC conversion using function
2187 * "HAL_ADC_Start_DMA()"
2188 * (this function is also clearing overrun flag)
2189 * @param hadc ADC handle
2190 * @retval None
2191 */
HAL_ADC_ErrorCallback(ADC_HandleTypeDef * hadc)2192 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
2193 {
2194 /* Prevent unused argument(s) compilation warning */
2195 UNUSED(hadc);
2196
2197 /* NOTE : This function should not be modified. When the callback is needed,
2198 function HAL_ADC_ErrorCallback must be implemented in the user file.
2199 */
2200 }
2201
2202 /**
2203 * @brief Calibration complete callback in non-blocking mode.
2204 * @param hadc ADC handle
2205 * @retval None
2206 */
HAL_ADC_CalibrationCpltCallback(ADC_HandleTypeDef * hadc)2207 __weak void HAL_ADC_CalibrationCpltCallback(ADC_HandleTypeDef *hadc)
2208 {
2209 /* Prevent unused argument(s) compilation warning */
2210 UNUSED(hadc);
2211
2212 /* NOTE : This function should not be modified. When the callback is needed,
2213 function HAL_ADC_CalibrationCpltCallback must be implemented in the user file.
2214 */
2215 }
2216
2217
2218 /**
2219 * @brief ADC Ready callback in non-blocking mode.
2220 * @param hadc ADC handle
2221 * @retval None
2222 */
HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef * hadc)2223 __weak void HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef *hadc)
2224 {
2225 /* Prevent unused argument(s) compilation warning */
2226 UNUSED(hadc);
2227
2228 /* NOTE : This function should not be modified. When the callback is needed,
2229 function HAL_ADC_ADCReadyCallback must be implemented in the user file.
2230 */
2231 }
2232
2233 /**
2234 * @}
2235 */
2236
2237 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
2238 * @brief Peripheral Control functions
2239 *
2240 @verbatim
2241 ===============================================================================
2242 ##### Peripheral Control functions #####
2243 ===============================================================================
2244 [..] This section provides functions allowing to:
2245 (+) Configure channels on regular group
2246 (+) Configure the analog watchdog
2247
2248 @endverbatim
2249 * @{
2250 */
2251
2252 /**
2253 * @brief Configure a channel to be assigned to ADC group regular.
2254 * @note In case of usage of internal measurement channels:
2255 * Vbat/VrefInt/TempSensor.
2256 * These internal paths can be disabled using function
2257 * HAL_ADC_DeInit().
2258 * @note Possibility to update parameters on the fly:
2259 * This function initializes channel into ADC group regular,
2260 * following calls to this function can be used to reconfigure
2261 * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
2262 * without resetting the ADC.
2263 * The setting of these parameters is conditioned to ADC state:
2264 * Refer to comments of structure "ADC_ChannelConfTypeDef".
2265 * @param hadc ADC handle
2266 * @param pConfig Structure of ADC channel assigned to ADC group regular.
2267 * @retval HAL status
2268 */
HAL_ADC_ConfigChannel(ADC_HandleTypeDef * hadc,const ADC_ChannelConfTypeDef * pConfig)2269 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
2270 {
2271 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2272 uint32_t tmp_config_internal_channel;
2273 __IO uint32_t wait_loop_index = 0UL;
2274
2275 /* Check the parameters */
2276 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2277 assert_param(IS_ADC_CHANNEL(pConfig->Channel));
2278 assert_param(IS_ADC_SAMPLING_TIME_COMMON(pConfig->SamplingTime));
2279
2280 if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
2281 (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
2282 {
2283 assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(pConfig->Rank));
2284 }
2285 else
2286 {
2287 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
2288
2289 assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
2290 }
2291
2292 __HAL_LOCK(hadc);
2293
2294 /* Parameters update conditioned to ADC state: */
2295 /* Parameters that can be updated when ADC is disabled or enabled without */
2296 /* conversion on going on regular group: */
2297 /* - Channel number */
2298 /* - Channel sampling time */
2299 /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */
2300 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2301 {
2302 /* Configure channel: depending on rank setting, add it or remove it from */
2303 /* ADC sequencer. */
2304 /* If sequencer set to not fully configurable with channel rank set to */
2305 /* none, remove the channel from the sequencer. */
2306 /* Otherwise (sequencer set to fully configurable or to to not fully */
2307 /* configurable with channel rank to be set), configure the selected */
2308 /* channel. */
2309 if (pConfig->Rank != ADC_RANK_NONE)
2310 {
2311 /* Regular sequence configuration */
2312 /* Note: ADC channel configuration requires few ADC clock cycles */
2313 /* to be ready. Processing of ADC settings in this function */
2314 /* induce that a specific wait time is not necessary. */
2315 /* For more details on ADC channel configuration ready, */
2316 /* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */
2317 if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
2318 (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
2319 {
2320 /* Sequencer set to not fully configurable: */
2321 /* Set the channel by enabling the corresponding bitfield. */
2322 LL_ADC_REG_SetSequencerChAdd(hadc->Instance, pConfig->Channel);
2323 }
2324 else
2325 {
2326 /* Sequencer set to fully configurable: */
2327 /* Set the channel by entering it into the selected rank. */
2328
2329 /* Memorize the channel set into variable in HAL ADC handle */
2330 MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
2331 ADC_CHSELR_SQ1 << (pConfig->Rank & 0x1FUL),
2332 __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel) << (pConfig->Rank & 0x1FUL));
2333
2334 /* If the selected rank is below ADC group regular sequencer length, */
2335 /* apply the configuration in ADC register. */
2336 /* Note: Otherwise, configuration is not applied. */
2337 /* To apply it, parameter'NbrOfConversion' must be increased. */
2338 if (((pConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
2339 {
2340 LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
2341 }
2342 }
2343
2344 /* Set sampling time of the selected ADC channel */
2345 LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
2346
2347 /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
2348 /* internal measurement paths enable: If internal channel selected, */
2349 /* enable dedicated internal buffers and path. */
2350 /* Note: these internal measurement paths can be disabled using */
2351 /* HAL_ADC_DeInit() or removing the channel from sequencer with */
2352 /* channel configuration parameter "Rank". */
2353 if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
2354 {
2355 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2356
2357 /* If the requested internal measurement path has already been enabled, */
2358 /* bypass the configuration processing. */
2359 if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
2360 ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
2361 {
2362 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2363 LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
2364
2365 /* Delay for temperature sensor stabilization time */
2366 /* Wait loop initialization and execution */
2367 /* Note: Variable divided by 2 to compensate partially */
2368 /* CPU processing cycles, scaling in us split to not */
2369 /* exceed 32 bits register capacity and handle low frequency. */
2370 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
2371 while (wait_loop_index != 0UL)
2372 {
2373 wait_loop_index--;
2374 }
2375 }
2376 else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
2377 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
2378 {
2379 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2380 LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
2381 }
2382 else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) &&
2383 ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
2384 {
2385 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2386 LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
2387 }
2388 else
2389 {
2390 /* nothing to do */
2391 }
2392 }
2393 }
2394 else
2395 {
2396 /* Regular sequencer configuration */
2397 /* Note: Case of sequencer set to fully configurable: */
2398 /* Sequencer rank cannot be disabled, only affected to */
2399 /* another channel. */
2400 /* To remove a rank, use parameter 'NbrOfConversion". */
2401 if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
2402 (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
2403 {
2404 /* Sequencer set to not fully configurable: */
2405 /* Reset the channel by disabling the corresponding bitfield. */
2406 LL_ADC_REG_SetSequencerChRem(hadc->Instance, pConfig->Channel);
2407 }
2408
2409 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
2410 /* If internal channel selected, enable dedicated internal buffers and */
2411 /* paths. */
2412 if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
2413 {
2414 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2415
2416 if (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
2417 {
2418 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2419 ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel);
2420 }
2421 else if (pConfig->Channel == ADC_CHANNEL_VBAT)
2422 {
2423 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2424 ~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel);
2425 }
2426 else if (pConfig->Channel == ADC_CHANNEL_VREFINT)
2427 {
2428 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2429 ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel);
2430 }
2431 else
2432 {
2433 /* nothing to do */
2434 }
2435 }
2436 }
2437 }
2438
2439 /* If a conversion is on going on regular group, no update on regular */
2440 /* channel could be done on neither of the channel configuration structure */
2441 /* parameters. */
2442 else
2443 {
2444 /* Update ADC state machine to error */
2445 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2446
2447 tmp_hal_status = HAL_ERROR;
2448 }
2449
2450 __HAL_UNLOCK(hadc);
2451
2452 return tmp_hal_status;
2453 }
2454
2455 /**
2456 * @brief Configure the analog watchdog.
2457 * @note Possibility to update parameters on the fly:
2458 * This function initializes the selected analog watchdog, successive
2459 * calls to this function can be used to reconfigure some parameters
2460 * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
2461 * the ADC.
2462 * The setting of these parameters is conditioned to ADC state.
2463 * For parameters constraints, see comments of structure
2464 * "ADC_AnalogWDGConfTypeDef".
2465 * @note On this STM32 series, analog watchdog thresholds can be modified
2466 * while ADC conversion is on going.
2467 * In this case, some constraints must be taken into account:
2468 * the programmed threshold values are effective from the next
2469 * ADC EOC (end of unitary conversion).
2470 * Considering that registers write delay may happen due to
2471 * bus activity, this might cause an uncertainty on the
2472 * effective timing of the new programmed threshold values.
2473 * @param hadc ADC handle
2474 * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
2475 * @retval HAL status
2476 */
HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef * hadc,const ADC_AnalogWDGConfTypeDef * pAnalogWDGConfig)2477 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
2478 {
2479 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2480 uint32_t tmp_awd_high_threshold_shifted;
2481 uint32_t tmp_awd_low_threshold_shifted;
2482 uint32_t backup_setting_adc_enable_state = 0UL;
2483
2484 /* Check the parameters */
2485 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2486 assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
2487 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
2488 assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
2489
2490 if (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
2491 {
2492 assert_param(IS_ADC_CHANNEL(pAnalogWDGConfig->Channel));
2493 }
2494
2495 /* Verify thresholds range */
2496 if (hadc->Init.OversamplingMode == ENABLE)
2497 {
2498 /* Case of oversampling enabled: depending on ratio and shift configuration,
2499 analog watchdog thresholds can be higher than ADC resolution.
2500 Verify if thresholds are within maximum thresholds range. */
2501 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold));
2502 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold));
2503 }
2504 else
2505 {
2506 /* Verify if thresholds are within the selected ADC resolution */
2507 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold));
2508 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
2509 }
2510
2511 __HAL_LOCK(hadc);
2512
2513 /* Parameters update conditioned to ADC state: */
2514 /* Parameters that can be updated when ADC is disabled or enabled without */
2515 /* conversion on going on ADC group regular: */
2516 /* - Analog watchdog channels */
2517 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2518 {
2519 /* Analog watchdog configuration */
2520 if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
2521 {
2522 /* Constraint of ADC on this STM32 series: ADC must be disable
2523 to modify bitfields of register ADC_CFGR1 */
2524 if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
2525 {
2526 backup_setting_adc_enable_state = 1UL;
2527 tmp_hal_status = ADC_Disable(hadc);
2528 }
2529
2530 /* Configuration of analog watchdog: */
2531 /* - Set the analog watchdog enable mode: one or overall group of */
2532 /* channels. */
2533 switch (pAnalogWDGConfig->WatchdogMode)
2534 {
2535 case ADC_ANALOGWATCHDOG_SINGLE_REG:
2536 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
2537 __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
2538 LL_ADC_GROUP_REGULAR));
2539 break;
2540
2541 case ADC_ANALOGWATCHDOG_ALL_REG:
2542 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
2543 break;
2544
2545 default: /* ADC_ANALOGWATCHDOG_NONE */
2546 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
2547 break;
2548 }
2549
2550 if (backup_setting_adc_enable_state == 1UL)
2551 {
2552 if (tmp_hal_status == HAL_OK)
2553 {
2554 tmp_hal_status = ADC_Enable(hadc);
2555 }
2556 }
2557
2558 /* Update state, clear previous result related to AWD1 */
2559 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
2560
2561 /* Clear flag ADC analog watchdog */
2562 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
2563 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
2564 /* (in case left enabled by previous ADC operations). */
2565 LL_ADC_ClearFlag_AWD1(hadc->Instance);
2566
2567 /* Configure ADC analog watchdog interrupt */
2568 if (pAnalogWDGConfig->ITMode == ENABLE)
2569 {
2570 LL_ADC_EnableIT_AWD1(hadc->Instance);
2571 }
2572 else
2573 {
2574 LL_ADC_DisableIT_AWD1(hadc->Instance);
2575 }
2576 }
2577 /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
2578 else
2579 {
2580 switch (pAnalogWDGConfig->WatchdogMode)
2581 {
2582 case ADC_ANALOGWATCHDOG_SINGLE_REG:
2583 /* Update AWD by bitfield to keep the possibility to monitor */
2584 /* several channels by successive calls of this function. */
2585 if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
2586 {
2587 SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel)));
2588 }
2589 else
2590 {
2591 SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel)));
2592 }
2593 break;
2594
2595 case ADC_ANALOGWATCHDOG_ALL_REG:
2596 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance,
2597 pAnalogWDGConfig->WatchdogNumber,
2598 LL_ADC_AWD_ALL_CHANNELS_REG);
2599 break;
2600
2601 default: /* ADC_ANALOGWATCHDOG_NONE */
2602 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
2603 break;
2604 }
2605
2606 if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
2607 {
2608 /* Update state, clear previous result related to AWD2 */
2609 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
2610
2611 /* Clear flag ADC analog watchdog */
2612 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
2613 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
2614 /* (in case left enabled by previous ADC operations). */
2615 LL_ADC_ClearFlag_AWD2(hadc->Instance);
2616
2617 /* Configure ADC analog watchdog interrupt */
2618 if (pAnalogWDGConfig->ITMode == ENABLE)
2619 {
2620 LL_ADC_EnableIT_AWD2(hadc->Instance);
2621 }
2622 else
2623 {
2624 LL_ADC_DisableIT_AWD2(hadc->Instance);
2625 }
2626 }
2627 /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
2628 else
2629 {
2630 /* Update state, clear previous result related to AWD3 */
2631 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
2632
2633 /* Clear flag ADC analog watchdog */
2634 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
2635 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
2636 /* (in case left enabled by previous ADC operations). */
2637 LL_ADC_ClearFlag_AWD3(hadc->Instance);
2638
2639 /* Configure ADC analog watchdog interrupt */
2640 if (pAnalogWDGConfig->ITMode == ENABLE)
2641 {
2642 LL_ADC_EnableIT_AWD3(hadc->Instance);
2643 }
2644 else
2645 {
2646 LL_ADC_DisableIT_AWD3(hadc->Instance);
2647 }
2648 }
2649 }
2650
2651 }
2652
2653 /* Analog watchdog thresholds configuration */
2654 if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
2655 {
2656 /* Shift the offset with respect to the selected ADC resolution: */
2657 /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
2658 /* are set to 0. */
2659 tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
2660 tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
2661 }
2662 /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
2663 else
2664 {
2665 /* No need to shift the offset with respect to the selected ADC resolution: */
2666 /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
2667 /* are set to 0. */
2668 tmp_awd_high_threshold_shifted = pAnalogWDGConfig->HighThreshold;
2669 tmp_awd_low_threshold_shifted = pAnalogWDGConfig->LowThreshold;
2670 }
2671
2672 /* Set ADC analog watchdog thresholds value of both thresholds high and low */
2673 LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted,
2674 tmp_awd_low_threshold_shifted);
2675
2676 __HAL_UNLOCK(hadc);
2677
2678 return tmp_hal_status;
2679 }
2680
2681
2682 /**
2683 * @}
2684 */
2685
2686 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
2687 * @brief ADC Peripheral State functions
2688 *
2689 @verbatim
2690 ===============================================================================
2691 ##### Peripheral state and errors functions #####
2692 ===============================================================================
2693 [..]
2694 This subsection provides functions to get in run-time the status of the
2695 peripheral.
2696 (+) Check the ADC state
2697 (+) Check the ADC error code
2698
2699 @endverbatim
2700 * @{
2701 */
2702
2703 /**
2704 * @brief Return the ADC handle state.
2705 * @note ADC state machine is managed by bitfields, ADC status must be
2706 * compared with states bits.
2707 * For example:
2708 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
2709 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
2710 * @param hadc ADC handle
2711 * @retval ADC handle state (bitfield on 32 bits)
2712 */
HAL_ADC_GetState(const ADC_HandleTypeDef * hadc)2713 uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc)
2714 {
2715 /* Check the parameters */
2716 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2717
2718 /* Return ADC handle state */
2719 return hadc->State;
2720 }
2721
2722 /**
2723 * @brief Return the ADC error code.
2724 * @param hadc ADC handle
2725 * @retval ADC error code (bitfield on 32 bits)
2726 */
HAL_ADC_GetError(const ADC_HandleTypeDef * hadc)2727 uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc)
2728 {
2729 /* Check the parameters */
2730 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2731
2732 return hadc->ErrorCode;
2733 }
2734
2735 /**
2736 * @}
2737 */
2738
2739 /**
2740 * @}
2741 */
2742
2743 /** @defgroup ADC_Private_Functions ADC Private Functions
2744 * @{
2745 */
2746
2747 /**
2748 * @brief Stop ADC conversion.
2749 * @note Prerequisite condition to use this function: ADC conversions must be
2750 * stopped to disable the ADC.
2751 * @param hadc ADC handle
2752 * @retval HAL status.
2753 */
ADC_ConversionStop(ADC_HandleTypeDef * hadc)2754 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc)
2755 {
2756 uint32_t tickstart;
2757
2758 /* Check the parameters */
2759 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2760
2761 /* Verification if ADC is not already stopped on regular group to bypass */
2762 /* this function if not needed. */
2763 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
2764 {
2765 /* Stop potential conversion on going on regular group */
2766 /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
2767 if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
2768 {
2769 /* Stop ADC group regular conversion */
2770 LL_ADC_REG_StopConversion(hadc->Instance);
2771 }
2772
2773 /* Wait for conversion effectively stopped */
2774 /* Get tick count */
2775 tickstart = HAL_GetTick();
2776
2777 while ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL)
2778 {
2779 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
2780 {
2781 /* New check to avoid false timeout detection in case of preemption */
2782 if ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL)
2783 {
2784 /* Update ADC state machine to error */
2785 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2786
2787 /* Set ADC error code to ADC peripheral internal error */
2788 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2789
2790 return HAL_ERROR;
2791 }
2792 }
2793 }
2794
2795 }
2796
2797 /* Return HAL status */
2798 return HAL_OK;
2799 }
2800
2801 /**
2802 * @brief Enable the selected ADC.
2803 * @note Prerequisite condition to use this function: ADC must be disabled
2804 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
2805 * @param hadc ADC handle
2806 * @retval HAL status.
2807 */
ADC_Enable(ADC_HandleTypeDef * hadc)2808 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
2809 {
2810 uint32_t tickstart;
2811 __IO uint32_t wait_loop_index = 0UL;
2812
2813 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
2814 /* enabling phase not yet completed: flag ADC ready not yet set). */
2815 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
2816 /* causes: ADC clock not running, ...). */
2817 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2818 {
2819 /* Check if conditions to enable the ADC are fulfilled */
2820 if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
2821 {
2822 /* Update ADC state machine to error */
2823 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2824
2825 /* Set ADC error code to ADC peripheral internal error */
2826 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2827
2828 return HAL_ERROR;
2829 }
2830
2831 /* Enable the ADC peripheral */
2832 LL_ADC_Enable(hadc->Instance);
2833
2834 if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2835 != 0UL)
2836 {
2837 /* Delay for temperature sensor buffer stabilization time */
2838 /* Wait loop initialization and execution */
2839 /* Note: Variable divided by 2 to compensate partially */
2840 /* CPU processing cycles, scaling in us split to not */
2841 /* exceed 32 bits register capacity and handle low frequency. */
2842 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL)
2843 * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
2844 while (wait_loop_index != 0UL)
2845 {
2846 wait_loop_index--;
2847 }
2848 }
2849
2850 /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
2851 /* performed automatically by hardware and flag ADC ready is not set. */
2852 if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
2853 {
2854 /* Wait for ADC effectively enabled */
2855 tickstart = HAL_GetTick();
2856
2857 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
2858 {
2859 /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
2860 has been cleared (after a calibration), ADEN bit is reset by the
2861 calibration logic.
2862 The workaround is to continue setting ADEN until ADRDY is becomes 1.
2863 Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
2864 4 ADC clock cycle duration */
2865 /* Note: Test of ADC enabled required due to hardware constraint to */
2866 /* not enable ADC if already enabled. */
2867 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2868 {
2869 LL_ADC_Enable(hadc->Instance);
2870 }
2871
2872 if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
2873 {
2874 /* New check to avoid false timeout detection in case of preemption */
2875 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
2876 {
2877 /* Update ADC state machine to error */
2878 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2879
2880 /* Set ADC error code to ADC peripheral internal error */
2881 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2882
2883 return HAL_ERROR;
2884 }
2885 }
2886 }
2887 }
2888 }
2889
2890 /* Return HAL status */
2891 return HAL_OK;
2892 }
2893
2894 /**
2895 * @brief Disable the selected ADC.
2896 * @note Prerequisite condition to use this function: ADC conversions must be
2897 * stopped.
2898 * @param hadc ADC handle
2899 * @retval HAL status.
2900 */
ADC_Disable(ADC_HandleTypeDef * hadc)2901 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
2902 {
2903 uint32_t tickstart;
2904 const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
2905
2906 /* Verification if ADC is not already disabled: */
2907 /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
2908 /* disabled. */
2909 if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
2910 && (tmp_adc_is_disable_on_going == 0UL)
2911 )
2912 {
2913 /* Check if conditions to disable the ADC are fulfilled */
2914 if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
2915 {
2916 /* Disable the ADC peripheral */
2917 LL_ADC_Disable(hadc->Instance);
2918 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
2919 }
2920 else
2921 {
2922 /* Update ADC state machine to error */
2923 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2924
2925 /* Set ADC error code to ADC peripheral internal error */
2926 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2927
2928 return HAL_ERROR;
2929 }
2930
2931 /* Wait for ADC effectively disabled */
2932 /* Get tick count */
2933 tickstart = HAL_GetTick();
2934
2935 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
2936 {
2937 if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
2938 {
2939 /* New check to avoid false timeout detection in case of preemption */
2940 if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
2941 {
2942 /* Update ADC state machine to error */
2943 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2944
2945 /* Set ADC error code to ADC peripheral internal error */
2946 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2947
2948 return HAL_ERROR;
2949 }
2950 }
2951 }
2952 }
2953
2954 /* Return HAL status */
2955 return HAL_OK;
2956 }
2957
2958 /**
2959 * @brief DMA transfer complete callback.
2960 * @param hdma pointer to DMA handle.
2961 * @retval None
2962 */
ADC_DMAConvCplt(DMA_HandleTypeDef * hdma)2963 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
2964 {
2965 /* Retrieve ADC handle corresponding to current DMA handle */
2966 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2967
2968 /* Update state machine on conversion status if not in error state */
2969 if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
2970 {
2971 /* Set ADC state */
2972 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
2973
2974 /* Determine whether any further conversion upcoming on group regular */
2975 /* by external trigger, continuous mode or scan sequence on going */
2976 /* to disable interruption. */
2977 if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
2978 && (hadc->Init.ContinuousConvMode == DISABLE)
2979 )
2980 {
2981 /* If End of Sequence is reached, disable interrupts */
2982 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
2983 {
2984 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
2985 /* ADSTART==0 (no conversion on going) */
2986 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2987 {
2988 /* Disable ADC end of single conversion interrupt on group regular */
2989 /* Note: Overrun interrupt was enabled with EOC interrupt in */
2990 /* HAL_Start_IT(), but is not disabled here because can be used */
2991 /* by overrun IRQ process below. */
2992 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
2993
2994 /* Set ADC state */
2995 ADC_STATE_CLR_SET(hadc->State,
2996 HAL_ADC_STATE_REG_BUSY,
2997 HAL_ADC_STATE_READY);
2998 }
2999 else
3000 {
3001 /* Change ADC state to error state */
3002 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
3003
3004 /* Set ADC error code to ADC peripheral internal error */
3005 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3006 }
3007 }
3008 }
3009
3010 /* Conversion complete callback */
3011 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3012 hadc->ConvCpltCallback(hadc);
3013 #else
3014 HAL_ADC_ConvCpltCallback(hadc);
3015 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3016 }
3017 else /* DMA and-or internal error occurred */
3018 {
3019 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
3020 {
3021 /* Call HAL ADC Error Callback function */
3022 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3023 hadc->ErrorCallback(hadc);
3024 #else
3025 HAL_ADC_ErrorCallback(hadc);
3026 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3027 }
3028 else
3029 {
3030 /* Call ADC DMA error callback */
3031 hadc->DMA_Handle->XferErrorCallback(hdma);
3032 }
3033 }
3034 }
3035
3036 /**
3037 * @brief DMA half transfer complete callback.
3038 * @param hdma pointer to DMA handle.
3039 * @retval None
3040 */
ADC_DMAHalfConvCplt(DMA_HandleTypeDef * hdma)3041 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
3042 {
3043 /* Retrieve ADC handle corresponding to current DMA handle */
3044 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3045
3046 /* Half conversion callback */
3047 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3048 hadc->ConvHalfCpltCallback(hadc);
3049 #else
3050 HAL_ADC_ConvHalfCpltCallback(hadc);
3051 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3052 }
3053
3054 /**
3055 * @brief DMA error callback.
3056 * @param hdma pointer to DMA handle.
3057 * @retval None
3058 */
ADC_DMAError(DMA_HandleTypeDef * hdma)3059 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
3060 {
3061 /* Retrieve ADC handle corresponding to current DMA handle */
3062 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3063
3064 /* Set ADC state */
3065 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
3066
3067 /* Set ADC error code to DMA error */
3068 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
3069
3070 /* Error callback */
3071 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3072 hadc->ErrorCallback(hadc);
3073 #else
3074 HAL_ADC_ErrorCallback(hadc);
3075 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3076 }
3077
3078 /**
3079 * @}
3080 */
3081
3082 #endif /* HAL_ADC_MODULE_ENABLED */
3083 /**
3084 * @}
3085 */
3086
3087 /**
3088 * @}
3089 */
3090
