1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_pwr.c
4 * @author MCD Application Team
5 * @brief PWR LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 #if defined (USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32n6xx_ll_pwr.h"
23
24 /** @addtogroup STM32N6xx_LL_Driver
25 * @{
26 */
27
28 #if defined (PWR)
29
30 /** @defgroup PWR_LL PWR
31 * @{
32 */
33
34 /* Private types -------------------------------------------------------------*/
35 /* Private variables ---------------------------------------------------------*/
36 /* Private constants ---------------------------------------------------------*/
37 /* Private macros ------------------------------------------------------------*/
38 /* Private function prototypes -----------------------------------------------*/
39 /* Exported functions --------------------------------------------------------*/
40
41 /** @addtogroup PWR_LL_Exported_Functions
42 * @{
43 */
44
45 /** @addtogroup PWR_LL_EF_Init
46 * @{
47 */
48
49 /**
50 * @brief De-initialize the PWR registers to their default reset values.
51 * @retval An ErrorStatus enumeration value:
52 * - SUCCESS : PWR registers are de-initialized.
53 * - ERROR : not applicable.
54 */
LL_PWR_DeInit(void)55 ErrorStatus LL_PWR_DeInit(void)
56 {
57 WRITE_REG(PWR->CR1, 0x00000024U);
58 WRITE_REG(PWR->CR2, 0x00000000U);
59 WRITE_REG(PWR->CR3, 0x00000000U);
60 WRITE_REG(PWR->CR4, 0x00000000U);
61 WRITE_REG(PWR->VOSCR, 0x00020002U);
62 WRITE_REG(PWR->BDCR1, 0x00000000U);
63 WRITE_REG(PWR->BDCR2, 0x00000000U);
64 WRITE_REG(PWR->DBPCR, 0x00000000U);
65 WRITE_REG(PWR->CPUCR, 0x00010000U);
66 WRITE_REG(PWR->SVMCR1, 0x00000000U);
67 WRITE_REG(PWR->SVMCR2, 0x00000000U);
68 WRITE_REG(PWR->SVMCR3, 0x00000000U);
69 WRITE_REG(PWR->WKUPCR, 0x00000000U);
70 WRITE_REG(PWR->WKUPSR, 0x00000000U);
71 WRITE_REG(PWR->WKUPEPR, 0x00000000U);
72
73 /* Clear PWR low power flags */
74 LL_PWR_ClearFlag_STOP_SB();
75
76 /* Clear PWR wake up flags */
77 LL_PWR_ClearFlag_WU();
78
79 /* Reset privilege attribute */
80 LL_PWR_ConfigPrivilege(0);
81
82 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
83 /* Reset secure attribute */
84 LL_PWR_ConfigSecure(0);
85 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
86
87 return SUCCESS;
88 }
89
90 /**
91 * @}
92 */
93
94 /**
95 * @}
96 */
97
98 /**
99 * @}
100 */
101
102 #endif /* defined(PWR) */
103 /**
104 * @}
105 */
106
107 #endif /* defined (USE_FULL_LL_DRIVER) */
108
109
