1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### LL DMA driver acronyms #####
20 ==============================================================================
21 [..] Acronyms table :
22 =========================================
23 || Acronym || ||
24 =========================================
25 || SRC || Source ||
26 || DEST || Destination ||
27 || ADDR || Address ||
28 || ADDRS || Addresses ||
29 || INC || Increment / Incremented ||
30 || DEC || Decrement / Decremented ||
31 || BLK || Block ||
32 || RPT || Repeat / Repeated ||
33 || TRIG || Trigger ||
34 =========================================
35 @endverbatim
36 ******************************************************************************
37 */
38
39 #if defined (USE_FULL_LL_DRIVER)
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32n6xx_ll_dma.h"
43 #include "stm32n6xx_ll_bus.h"
44 #ifdef USE_FULL_ASSERT
45 #include "stm32_assert.h"
46 #else
47 #define assert_param(expr) ((void)0U)
48 #endif /* USE_FULL_ASSERT */
49
50 /** @addtogroup STM32N6xx_LL_Driver
51 * @{
52 */
53
54 #if (defined (GPDMA1) || defined (HPDMA1))
55
56 /** @addtogroup DMA_LL
57 * @{
58 */
59
60 /* Private types -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62 /* Private constants ---------------------------------------------------------*/
63 /* Private macros ------------------------------------------------------------*/
64
65 /** @addtogroup DMA_LL_Private_Macros
66 * @{
67 */
68 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == HPDMA1) && \
69 (((Channel) == LL_DMA_CHANNEL_0) || \
70 ((Channel) == LL_DMA_CHANNEL_1) || \
71 ((Channel) == LL_DMA_CHANNEL_2) || \
72 ((Channel) == LL_DMA_CHANNEL_3) || \
73 ((Channel) == LL_DMA_CHANNEL_4) || \
74 ((Channel) == LL_DMA_CHANNEL_5) || \
75 ((Channel) == LL_DMA_CHANNEL_6) || \
76 ((Channel) == LL_DMA_CHANNEL_7) || \
77 ((Channel) == LL_DMA_CHANNEL_8) || \
78 ((Channel) == LL_DMA_CHANNEL_9) || \
79 ((Channel) == LL_DMA_CHANNEL_10) || \
80 ((Channel) == LL_DMA_CHANNEL_11) || \
81 ((Channel) == LL_DMA_CHANNEL_12) || \
82 ((Channel) == LL_DMA_CHANNEL_13) || \
83 ((Channel) == LL_DMA_CHANNEL_14) || \
84 ((Channel) == LL_DMA_CHANNEL_15) || \
85 ((Channel) == LL_DMA_CHANNEL_ALL))) || \
86 (((INSTANCE) == GPDMA1) && \
87 (((Channel) == LL_DMA_CHANNEL_0) || \
88 ((Channel) == LL_DMA_CHANNEL_1) || \
89 ((Channel) == LL_DMA_CHANNEL_2) || \
90 ((Channel) == LL_DMA_CHANNEL_3) || \
91 ((Channel) == LL_DMA_CHANNEL_4) || \
92 ((Channel) == LL_DMA_CHANNEL_5) || \
93 ((Channel) == LL_DMA_CHANNEL_6) || \
94 ((Channel) == LL_DMA_CHANNEL_7) || \
95 ((Channel) == LL_DMA_CHANNEL_8) || \
96 ((Channel) == LL_DMA_CHANNEL_9) || \
97 ((Channel) == LL_DMA_CHANNEL_10) || \
98 ((Channel) == LL_DMA_CHANNEL_11) || \
99 ((Channel) == LL_DMA_CHANNEL_12) || \
100 ((Channel) == LL_DMA_CHANNEL_13) || \
101 ((Channel) == LL_DMA_CHANNEL_14) || \
102 ((Channel) == LL_DMA_CHANNEL_15) || \
103 ((Channel) == LL_DMA_CHANNEL_ALL))))
104
105 #define IS_LL_HPDMA_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == HPDMA1) && \
106 (((Channel) == LL_DMA_CHANNEL_0) || \
107 ((Channel) == LL_DMA_CHANNEL_1) || \
108 ((Channel) == LL_DMA_CHANNEL_2) || \
109 ((Channel) == LL_DMA_CHANNEL_3) || \
110 ((Channel) == LL_DMA_CHANNEL_4) || \
111 ((Channel) == LL_DMA_CHANNEL_5) || \
112 ((Channel) == LL_DMA_CHANNEL_6) || \
113 ((Channel) == LL_DMA_CHANNEL_7) || \
114 ((Channel) == LL_DMA_CHANNEL_8) || \
115 ((Channel) == LL_DMA_CHANNEL_9) || \
116 ((Channel) == LL_DMA_CHANNEL_10) || \
117 ((Channel) == LL_DMA_CHANNEL_11) || \
118 ((Channel) == LL_DMA_CHANNEL_12) || \
119 ((Channel) == LL_DMA_CHANNEL_13) || \
120 ((Channel) == LL_DMA_CHANNEL_14) || \
121 ((Channel) == LL_DMA_CHANNEL_15)))
122
123 #define IS_LL_GPDMA_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \
124 (((Channel) == LL_DMA_CHANNEL_0) || \
125 ((Channel) == LL_DMA_CHANNEL_1) || \
126 ((Channel) == LL_DMA_CHANNEL_2) || \
127 ((Channel) == LL_DMA_CHANNEL_3) || \
128 ((Channel) == LL_DMA_CHANNEL_4) || \
129 ((Channel) == LL_DMA_CHANNEL_5) || \
130 ((Channel) == LL_DMA_CHANNEL_6) || \
131 ((Channel) == LL_DMA_CHANNEL_7) || \
132 ((Channel) == LL_DMA_CHANNEL_8) || \
133 ((Channel) == LL_DMA_CHANNEL_9) || \
134 ((Channel) == LL_DMA_CHANNEL_10) || \
135 ((Channel) == LL_DMA_CHANNEL_11) || \
136 ((Channel) == LL_DMA_CHANNEL_12) || \
137 ((Channel) == LL_DMA_CHANNEL_13) || \
138 ((Channel) == LL_DMA_CHANNEL_14) || \
139 ((Channel) == LL_DMA_CHANNEL_15)))
140
141 #define IS_LL_DMA_2D_CHANNEL_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == HPDMA1) && \
142 (((Channel) == LL_DMA_CHANNEL_12) || \
143 ((Channel) == LL_DMA_CHANNEL_13) || \
144 ((Channel) == LL_DMA_CHANNEL_14) || \
145 ((Channel) == LL_DMA_CHANNEL_15))) || \
146 (((INSTANCE) == GPDMA1) && \
147 (((Channel) == LL_DMA_CHANNEL_12) || \
148 ((Channel) == LL_DMA_CHANNEL_13) || \
149 ((Channel) == LL_DMA_CHANNEL_14) || \
150 ((Channel) == LL_DMA_CHANNEL_15))))
151
152 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_NORMAL) || \
153 ((__VALUE__) == LL_DMA_PFCTRL))
154
155 #define IS_LL_DMA_PFREQ_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == HPDMA1) && \
156 (((Channel) == LL_DMA_CHANNEL_0) || \
157 ((Channel) == LL_DMA_CHANNEL_1) || \
158 ((Channel) == LL_DMA_CHANNEL_15))) || \
159 (((INSTANCE) == GPDMA1) && \
160 (((Channel) == LL_DMA_CHANNEL_0) || \
161 ((Channel) == LL_DMA_CHANNEL_1) || \
162 ((Channel) == LL_DMA_CHANNEL_15))))
163
164 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) || \
165 ((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
166 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH))
167
168 #define IS_LL_DMA_DATA_ALIGNMENT(__VALUE__) (((__VALUE__) == LL_DMA_DATA_ALIGN_ZEROPADD) || \
169 ((__VALUE__) == LL_DMA_DATA_ALIGN_SIGNEXTPADD) || \
170 ((__VALUE__) == LL_DMA_DATA_PACK_UNPACK))
171
172 #define IS_LL_DMA_BURST_LENGTH(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= 64U))
173
174 #define IS_LL_DMA_SRC_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_SRC_DATAWIDTH_BYTE) || \
175 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_HALFWORD) || \
176 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_WORD) || \
177 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_DOUBLEWORD))
178
179 #define IS_LL_DMA_DEST_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_DEST_DATAWIDTH_BYTE) || \
180 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_HALFWORD) || \
181 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_WORD) || \
182 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_DOUBLEWORD))
183
184 #define IS_LL_DMA_SRC_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_FIXED) || \
185 ((__VALUE__) == LL_DMA_SRC_INCREMENT))
186
187 #define IS_LL_DMA_DEST_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_FIXED) || \
188 ((__VALUE__) == LL_DMA_DEST_INCREMENT))
189
190 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_LOW_PRIORITY_LOW_WEIGHT) || \
191 ((__VALUE__) == LL_DMA_LOW_PRIORITY_MID_WEIGHT) || \
192 ((__VALUE__) == LL_DMA_LOW_PRIORITY_HIGH_WEIGHT) || \
193 ((__VALUE__) == LL_DMA_HIGH_PRIORITY))
194
195 #define IS_LL_DMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0xFFFFU)
196
197 #define IS_LL_DMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x0EFFU)
198
199 #define IS_LL_DMA_TRIGGER_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TRIGM_BLK_TRANSFER) || \
200 ((__VALUE__) == LL_DMA_TRIGM_RPT_BLK_TRANSFER) || \
201 ((__VALUE__) == LL_DMA_TRIGM_LLI_LINK_TRANSFER) || \
202 ((__VALUE__) == LL_DMA_TRIGM_SINGLBURST_TRANSFER ))
203
204 #define IS_LL_DMA_TRIGGER_POLARITY(__VALUE__) (((__VALUE__) == LL_DMA_TRIG_POLARITY_MASKED) || \
205 ((__VALUE__) == LL_DMA_TRIG_POLARITY_RISING) || \
206 ((__VALUE__) == LL_DMA_TRIG_POLARITY_FALLING))
207
208 #define IS_LL_DMA_BLKHW_REQUEST(__VALUE__) (((__VALUE__) == LL_DMA_HWREQUEST_SINGLEBURST) || \
209 ((__VALUE__) == LL_DMA_HWREQUEST_BLK))
210
211 #define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_HPDMA1_TRIGGER_EXTIT15_SYNC)
212
213 #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_HPDMA1_REQUEST_I3C2_RS)
214
215 #define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER) || \
216 ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER) || \
217 ((__VALUE__) == LL_DMA_TCEM_EACH_LLITEM_TRANSFER) || \
218 ((__VALUE__) == LL_DMA_TCEM_LAST_LLITEM_TRANSFER))
219
220 #define IS_LL_DMA_DEST_WORD_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_WORD_PRESERVE) || \
221 ((__VALUE__) == LL_DMA_DEST_WORD_EXCHANGE))
222
223 #define IS_LL_DMA_DEST_HALFWORD_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_HALFWORD_PRESERVE) || \
224 ((__VALUE__) == LL_DMA_DEST_HALFWORD_EXCHANGE))
225
226 #define IS_LL_DMA_DEST_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_BYTE_PRESERVE) || \
227 ((__VALUE__) == LL_DMA_DEST_BYTE_EXCHANGE))
228
229 #define IS_LL_DMA_SRC_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_BYTE_PRESERVE) || \
230 ((__VALUE__) == LL_DMA_SRC_BYTE_EXCHANGE))
231
232 #define IS_LL_DMA_LINK_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT0) || \
233 ((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT1))
234
235 #define IS_LL_DMA_SRC_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT0) || \
236 ((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT1))
237
238 #define IS_LL_DMA_DEST_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT0) || \
239 ((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT1))
240
241 #define IS_LL_DMA_LINK_STEP_MODE(__VALUE__) (((__VALUE__) == LL_DMA_LSM_FULL_EXECUTION) || \
242 ((__VALUE__) == LL_DMA_LSM_1LINK_EXECUTION))
243
244 #define IS_LL_DMA_BURST_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_SRC_ADDR_INCREMENT) || \
245 ((__VALUE__) == LL_DMA_BURST_SRC_ADDR_DECREMENT))
246
247 #define IS_LL_DMA_BURST_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_DEST_ADDR_INCREMENT) || \
248 ((__VALUE__) == LL_DMA_BURST_DEST_ADDR_DECREMENT))
249
250 #define IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
251
252 #define IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_INCREMENT) || \
253 ((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_DECREMENT))
254
255 #define IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_INCREMENT) || \
256 ((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_DECREMENT))
257
258 #define IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0xFFFFU)
259
260 #define IS_LL_DMA_LINK_BASEADDR(__VALUE__) (((__VALUE__) & 0xFFFFU) == 0U)
261
262 #define IS_LL_DMA_LINK_ADDR_OFFSET(__VALUE__) (((__VALUE__) & 0x03U) == 0U)
263
264 #define IS_LL_DMA_LINK_UPDATE_REGISTERS(__VALUE__) ((((__VALUE__) & 0x01FE0000U) == 0U) && ((__VALUE__) != 0U))
265
266 #define IS_LL_DMA_LINK_NODETYPE(__VALUE__) (((__VALUE__) == LL_DMA_HPDMA_2D_NODE) || \
267 ((__VALUE__) == LL_DMA_HPDMA_LINEAR_NODE) || \
268 ((__VALUE__) == LL_DMA_GPDMA_2D_NODE) || \
269 ((__VALUE__) == LL_DMA_GPDMA_LINEAR_NODE))
270
271 #if defined (CPU_IN_SECURE_STATE)
272 #define IS_LL_DMA_CHANNEL_SRC_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_SRC_NSEC) || \
273 ((__VALUE__) == LL_DMA_CHANNEL_SRC_SEC))
274
275 #define IS_LL_DMA_CHANNEL_DEST_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_DEST_NSEC) || \
276 ((__VALUE__) == LL_DMA_CHANNEL_DEST_SEC))
277
278 #endif /* CPU_IN_SECURE_STATE */
279 #define IS_LL_DMA_LIMIT_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == HPDMA1) && \
280 (((Channel) == LL_DMA_CHANNEL_12) || \
281 ((Channel) == LL_DMA_CHANNEL_13) || \
282 ((Channel) == LL_DMA_CHANNEL_14) || \
283 ((Channel) == LL_DMA_CHANNEL_15)))
284
285 /**
286 * @}
287 */
288
289 /* Private function prototypes -----------------------------------------------*/
290 /* Exported functions --------------------------------------------------------*/
291
292 /** @addtogroup DMA_LL_Exported_Functions
293 * @{
294 */
295
296 /** @addtogroup DMA_LL_EF_Init
297 * @{
298 */
299
300 /**
301 * @brief De-initialize the DMA registers to their default reset values.
302 * @note This API is used for all available DMA channels.
303 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
304 * helper macros :
305 * @arg @ref LL_DMA_GET_INSTANCE
306 * @arg @ref LL_DMA_GET_CHANNEL
307 * @param DMAx DMAx Instance
308 * @param Channel This parameter can be one of the following values:
309 * @arg @ref LL_DMA_CHANNEL_0
310 * @arg @ref LL_DMA_CHANNEL_1
311 * @arg @ref LL_DMA_CHANNEL_2
312 * @arg @ref LL_DMA_CHANNEL_3
313 * @arg @ref LL_DMA_CHANNEL_4
314 * @arg @ref LL_DMA_CHANNEL_5
315 * @arg @ref LL_DMA_CHANNEL_6
316 * @arg @ref LL_DMA_CHANNEL_7
317 * @arg @ref LL_DMA_CHANNEL_8
318 * @arg @ref LL_DMA_CHANNEL_9
319 * @arg @ref LL_DMA_CHANNEL_10
320 * @arg @ref LL_DMA_CHANNEL_11
321 * @arg @ref LL_DMA_CHANNEL_12
322 * @arg @ref LL_DMA_CHANNEL_13
323 * @arg @ref LL_DMA_CHANNEL_14
324 * @arg @ref LL_DMA_CHANNEL_15
325 * @retval An ErrorStatus enumeration value:
326 * - SUCCESS : DMA registers are de-initialized.
327 * - ERROR : DMA registers are not de-initialized.
328 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)329 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
330 {
331 DMA_Channel_TypeDef *tmp;
332 ErrorStatus status = SUCCESS;
333
334 /* Check the DMA Instance DMAx and Channel parameters */
335 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
336
337 if (Channel == LL_DMA_CHANNEL_ALL)
338 {
339 if (DMAx == GPDMA1)
340 {
341 /* Force reset of DMA clock */
342 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
343
344 /* Release reset of DMA clock */
345 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
346 }
347 else
348 {
349 /* Force reset of DMA clock */
350 LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_HPDMA1);
351
352 /* Release reset of DMA clock */
353 LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_HPDMA1);
354 }
355 }
356 else
357 {
358 /* Get the DMA Channel Instance */
359 tmp = (DMA_Channel_TypeDef *)(LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
360
361 /* Suspend DMA channel */
362 LL_DMA_SuspendChannel(DMAx, Channel);
363
364 /* Disable the selected Channel */
365 LL_DMA_ResetChannel(DMAx, Channel);
366
367 /* Reset DMAx_Channely control register */
368 LL_DMA_WriteReg(tmp, CLBAR, 0U);
369
370 /* Reset DMAx_Channely control register */
371 LL_DMA_WriteReg(tmp, CCR, 0U);
372
373 /* Reset DMAx_Channely Configuration register */
374 LL_DMA_WriteReg(tmp, CTR1, 0U);
375
376 /* Reset DMAx_Channely transfer register 2 */
377 LL_DMA_WriteReg(tmp, CTR2, 0U);
378
379 /* Reset DMAx_Channely block number of data register */
380 LL_DMA_WriteReg(tmp, CBR1, 0U);
381
382 /* Reset DMAx_Channely source address register */
383 LL_DMA_WriteReg(tmp, CSAR, 0U);
384
385 /* Reset DMAx_Channely destination address register */
386 LL_DMA_WriteReg(tmp, CDAR, 0U);
387
388 /* Check DMA channel */
389 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
390 {
391 /* Reset DMAx_Channely transfer register 3 */
392 LL_DMA_WriteReg(tmp, CTR3, 0U);
393
394 /* Reset DMAx_Channely Block register 2 */
395 LL_DMA_WriteReg(tmp, CBR2, 0U);
396 }
397
398 /* Reset DMAx_Channely Linked list address register */
399 LL_DMA_WriteReg(tmp, CLLR, 0U);
400
401 /* Reset DMAx_Channely pending flags */
402 LL_DMA_WriteReg(tmp, CFCR, 0x00003F00U);
403
404 /* Reset DMAx_Channely attribute */
405 LL_DMA_DisableChannelPrivilege(DMAx, Channel);
406
407 #if defined (CPU_IN_SECURE_STATE)
408 LL_DMA_DisableChannelSecure(DMAx, Channel);
409 #endif /* CPU_IN_SECURE_STATE */
410 }
411
412 return (uint32_t)status;
413 }
414
415 /**
416 * @brief Initialize the DMA registers according to the specified parameters
417 * in DMA_InitStruct.
418 * @note This API is used for all available DMA channels.
419 * @note A software request transfer can be done once programming the direction
420 * field in memory to memory value.
421 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
422 * helper macros :
423 * @arg @ref LL_DMA_GET_INSTANCE
424 * @arg @ref LL_DMA_GET_CHANNEL
425 * @note Warning if AXI port is selected with HPDMA, the maximum source (and destination) length should be less
426 * than 17. Otherwise, an error will be returned and no initialization performed.
427 * @param DMAx DMAx Instance
428 * @param Channel This parameter can be one of the following values:
429 * @arg @ref LL_DMA_CHANNEL_0
430 * @arg @ref LL_DMA_CHANNEL_1
431 * @arg @ref LL_DMA_CHANNEL_2
432 * @arg @ref LL_DMA_CHANNEL_3
433 * @arg @ref LL_DMA_CHANNEL_4
434 * @arg @ref LL_DMA_CHANNEL_5
435 * @arg @ref LL_DMA_CHANNEL_6
436 * @arg @ref LL_DMA_CHANNEL_7
437 * @arg @ref LL_DMA_CHANNEL_8
438 * @arg @ref LL_DMA_CHANNEL_9
439 * @arg @ref LL_DMA_CHANNEL_10
440 * @arg @ref LL_DMA_CHANNEL_11
441 * @arg @ref LL_DMA_CHANNEL_12
442 * @arg @ref LL_DMA_CHANNEL_13
443 * @arg @ref LL_DMA_CHANNEL_14
444 * @arg @ref LL_DMA_CHANNEL_15
445 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
446 * @retval An ErrorStatus enumeration value:
447 * - SUCCESS : DMA registers are initialized.
448 * - ERROR : Not applicable.
449 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitTypeDef * DMA_InitStruct)450 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
451 {
452 /* Check the DMA Instance DMAx and Channel parameters*/
453 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
454
455 /* Check the DMA parameters from DMA_InitStruct */
456 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
457
458 /* Check direction */
459 if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
460 {
461 assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitStruct->Request));
462 }
463
464 assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitStruct->DataAlignment));
465 assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitStruct->SrcDataWidth));
466 assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitStruct->DestDataWidth));
467 assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitStruct->SrcIncMode));
468 assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitStruct->DestIncMode));
469 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
470 assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitStruct->BlkDataLength));
471 assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitStruct->TriggerPolarity));
472 assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitStruct->BlkHWRequest));
473 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitStruct->TransferEventMode));
474 assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitStruct->LinkStepMode));
475 assert_param(IS_LL_DMA_LINK_BASEADDR(DMA_InitStruct->LinkedListBaseAddr));
476 assert_param(IS_LL_DMA_LINK_ADDR_OFFSET(DMA_InitStruct->LinkedListAddrOffset));
477 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
478 if (DMA_InitStruct->Mode == LL_DMA_PFCTRL)
479 {
480 assert_param(IS_LL_DMA_PFREQ_INSTANCE(DMAx, Channel));
481 }
482
483 /* Check DMA instance */
484 if ((IS_LL_HPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) || (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U))
485 {
486 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->SrcBurstLength));
487 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->DestBurstLength));
488 assert_param(IS_LL_DMA_DEST_WORD_EXCHANGE(DMA_InitStruct->DestWordExchange));
489 assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitStruct->DestHWordExchange));
490 assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitStruct->DestByteExchange));
491 assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitStruct->SrcByteExchange));
492 assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitStruct->LinkAllocatedPort));
493 assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitStruct->SrcAllocatedPort));
494 assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitStruct->DestAllocatedPort));
495 }
496
497 /* Check trigger polarity */
498 if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
499 {
500 assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitStruct->TriggerMode));
501 assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitStruct->TriggerSelection));
502 }
503
504 /* Check DMA channel */
505 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
506 {
507 assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitStruct->BlkRptCount));
508 assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitStruct->SrcAddrUpdateMode));
509 assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitStruct->DestAddrUpdateMode));
510 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->SrcAddrOffset));
511 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->DestAddrOffset));
512 assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitStruct->BlkRptSrcAddrUpdateMode));
513 assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitStruct->BlkRptDestAddrUpdateMode));
514 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptSrcAddrOffset));
515 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptDestAddrOffset));
516 }
517
518 if (DMAx == HPDMA1)
519 {
520 if ((DMA_InitStruct->SrcAllocatedPort == LL_DMA_SRC_ALLOCATED_PORT0) &&
521 (DMA_InitStruct->SrcBurstLength > 16U))
522 {
523 return (uint32_t)ERROR;
524 }
525 if ((DMA_InitStruct->DestAllocatedPort == LL_DMA_DEST_ALLOCATED_PORT0) &&
526 (DMA_InitStruct->DestBurstLength > 16U))
527 {
528 return (uint32_t)ERROR;
529 }
530 }
531
532 /*-------------------------- DMAx CLBAR Configuration ------------------------
533 * Configure the Transfer linked list address with parameter :
534 * - LinkedListBaseAdd: DMA_CLBAR_LBA[31:16] bits
535 */
536 LL_DMA_SetLinkedListBaseAddr(DMAx, Channel, DMA_InitStruct->LinkedListBaseAddr);
537
538 /*-------------------------- DMAx CCR Configuration --------------------------
539 * Configure the control parameter :
540 * - LinkAllocatedPort: DMA_CCR_LAP bit
541 * - LinkStepMode: DMA_CCR_LSM bit
542 * - Priority: DMA_CCR_PRIO [23:22] bits
543 */
544 LL_DMA_ConfigControl(DMAx, Channel, DMA_InitStruct->Priority | \
545 DMA_InitStruct->LinkAllocatedPort | \
546 DMA_InitStruct->LinkStepMode);
547
548 /*-------------------------- DMAx CTR1 Configuration -------------------------
549 * Configure the Data transfer parameter :
550 * - DestAllocatedPort: DMA_CTR1_DAP bit
551 * - DestWordExchange: DMA_CTR1_DWX bit
552 * - DestHWordExchange: DMA_CTR1_DHX bit
553 * - DestByteExchange: DMA_CTR1_DBX bit
554 * - DestIncMode: DMA_CTR1_DINC bit
555 * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
556 * - SrcAllocatedPort: DMA_CTR1_SAP bit
557 * - SrcByteExchange: DMA_CTR1_SBX bit
558 * - DataAlignment: DMA_CTR1_PAM [12:11] bits
559 * - SrcIncMode: DMA_CTR1_SINC bit
560 * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
561 * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
562 * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
563 */
564 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->DestAllocatedPort | \
565 DMA_InitStruct->DestWordExchange | \
566 DMA_InitStruct->DestHWordExchange | \
567 DMA_InitStruct->DestByteExchange | \
568 DMA_InitStruct->DestIncMode | \
569 DMA_InitStruct->DestDataWidth | \
570 DMA_InitStruct->SrcAllocatedPort | \
571 DMA_InitStruct->SrcByteExchange | \
572 DMA_InitStruct->DataAlignment | \
573 DMA_InitStruct->SrcIncMode | \
574 DMA_InitStruct->SrcDataWidth);
575 /* Check DMA instance */
576 if ((IS_LL_HPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) || (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U))
577 {
578 LL_DMA_ConfigBurstLength(DMAx, Channel, DMA_InitStruct->SrcBurstLength,
579 DMA_InitStruct->DestBurstLength);
580 }
581
582 /*-------------------------- DMAx CTR2 Configuration -------------------------
583 * Configure the channel transfer parameter :
584 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
585 * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
586 * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
587 * - BlkHWRequest: DMA_CTR2_BREQ bit
588 * - Mode: DMA_CTR2_PFREQ bit
589 * - Direction: DMA_CTR2_DREQ bit
590 * - Direction: DMA_CTR2_SWREQ bit
591 * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
592 * - Request: DMA_CTR2_REQSEL [6:0] bits
593 */
594 LL_DMA_ConfigChannelTransfer(DMAx, Channel, DMA_InitStruct->TransferEventMode | \
595 DMA_InitStruct->TriggerPolarity | \
596 DMA_InitStruct->BlkHWRequest | \
597 DMA_InitStruct->Mode | \
598 DMA_InitStruct->Direction);
599
600 /* Check direction */
601 if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
602 {
603 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->Request);
604 }
605
606 /* Check trigger polarity */
607 if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
608 {
609 LL_DMA_SetHWTrigger(DMAx, Channel, DMA_InitStruct->TriggerSelection);
610 LL_DMA_SetTriggerMode(DMAx, Channel, DMA_InitStruct->TriggerMode);
611 }
612
613 /*-------------------------- DMAx CBR1 Configuration -------------------------
614 * Configure the Transfer Block counters and update mode with parameter :
615 * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
616 * - BlkRptCount: DMA_CBR1_BRC[26:16] bits
617 * BlkRptCount field is supported only by 2D addressing channels.
618 * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit
619 * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels.
620 * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit
621 * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels.
622 * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit
623 * SrcAddrUpdateMode field is supported only by 2D addressing channels.
624 * - DestAddrUpdateMode: DMA_CBR1_DDEC bit
625 * DestAddrUpdateMode field is supported only by 2D addressing channels.
626 */
627 LL_DMA_SetBlkDataLength(DMAx, Channel, DMA_InitStruct->BlkDataLength);
628
629 /* Check DMA channel */
630 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
631 {
632 LL_DMA_SetBlkRptCount(DMAx, Channel, DMA_InitStruct->BlkRptCount);
633 LL_DMA_ConfigBlkRptAddrUpdate(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrUpdateMode | \
634 DMA_InitStruct->BlkRptDestAddrUpdateMode | \
635 DMA_InitStruct->SrcAddrUpdateMode | \
636 DMA_InitStruct->DestAddrUpdateMode);
637 }
638
639 /*-------------------------- DMAx CSAR and CDAR Configuration ----------------
640 * Configure the Transfer source address with parameter :
641 * - SrcAddress: DMA_CSAR_SA[31:0] bits
642 * - DestAddress: DMA_CDAR_DA[31:0] bits
643 */
644 LL_DMA_ConfigAddresses(DMAx, Channel, DMA_InitStruct->SrcAddress, DMA_InitStruct->DestAddress);
645
646 /* Check DMA channel */
647 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
648 {
649 /*------------------------ DMAx CTR3 Configuration -------------------------
650 * Configure the Transfer Block counters and update mode with parameter :
651 * - SrcAddrOffset: DMA_CTR3_SAO[28:16] bits
652 * SrcAddrOffset field is supported only by 2D addressing channels.
653 * - DestAddrOffset: DMA_CTR3_DAO[12:0] bits
654 * DestAddrOffset field is supported only by 2D addressing channels.
655 */
656 LL_DMA_ConfigAddrUpdateValue(DMAx, Channel, DMA_InitStruct->SrcAddrOffset, DMA_InitStruct->DestAddrOffset);
657
658 /*------------------------ DMAx CBR2 Configuration -----------------------
659 * Configure the Transfer Block counters and update mode with parameter :
660 * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits
661 * BlkRptSrcAddrOffset field is supported only by 2D addressing channels.
662 * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits
663 * BlkRptDestAddrOffset field is supported only by 2D addressing channels.
664 */
665 LL_DMA_ConfigBlkRptAddrUpdateValue(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrOffset,
666 DMA_InitStruct->BlkRptDestAddrOffset);
667 }
668
669 /*-------------------------- DMAx CLLR Configuration -------------------------
670 * Configure the Transfer linked list address with parameter :
671 * - DestAddrOffset: DMA_CLLR_LA[15:2] bits
672 */
673 LL_DMA_SetLinkedListAddrOffset(DMAx, Channel, DMA_InitStruct->LinkedListAddrOffset);
674
675 return (uint32_t)SUCCESS;
676 }
677
678 /**
679 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
680 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
681 * @retval None.
682 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)683 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
684 {
685 /* Set DMA_InitStruct fields to default values */
686 DMA_InitStruct->SrcAddress = 0x00000000U;
687 DMA_InitStruct->DestAddress = 0x00000000U;
688 DMA_InitStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
689 DMA_InitStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
690 DMA_InitStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
691 DMA_InitStruct->SrcBurstLength = 1U;
692 DMA_InitStruct->DestBurstLength = 1U;
693 DMA_InitStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
694 DMA_InitStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
695 DMA_InitStruct->SrcIncMode = LL_DMA_SRC_FIXED;
696 DMA_InitStruct->DestIncMode = LL_DMA_DEST_FIXED;
697 DMA_InitStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
698 DMA_InitStruct->BlkDataLength = 0x00000000U;
699 DMA_InitStruct->Mode = LL_DMA_NORMAL;
700 DMA_InitStruct->BlkRptCount = 0x00000000U;
701 DMA_InitStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
702 DMA_InitStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
703 DMA_InitStruct->TriggerSelection = 0x00000000U;
704 DMA_InitStruct->Request = 0x00000000U;
705 DMA_InitStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
706 DMA_InitStruct->DestWordExchange = LL_DMA_DEST_WORD_PRESERVE;
707 DMA_InitStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
708 DMA_InitStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
709 DMA_InitStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
710 DMA_InitStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
711 DMA_InitStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
712 DMA_InitStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
713 DMA_InitStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
714 DMA_InitStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT;
715 DMA_InitStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT;
716 DMA_InitStruct->SrcAddrOffset = 0x00000000U;
717 DMA_InitStruct->DestAddrOffset = 0x00000000U;
718 DMA_InitStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
719 DMA_InitStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
720 DMA_InitStruct->BlkRptSrcAddrOffset = 0x00000000U;
721 DMA_InitStruct->BlkRptDestAddrOffset = 0x00000000U;
722 DMA_InitStruct->LinkedListBaseAddr = 0x00000000U;
723 DMA_InitStruct->LinkedListAddrOffset = 0x00000000U;
724 }
725
726 /**
727 * @brief Set each @ref LL_DMA_InitLinkedListTypeDef field to default value.
728 * @param DMA_InitLinkedListStruct Pointer to
729 * a @ref LL_DMA_InitLinkedListTypeDef structure.
730 * @retval None.
731 */
LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef * DMA_InitLinkedListStruct)732 void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
733 {
734 /* Set LL_DMA_InitLinkedListTypeDef fields to default values */
735 DMA_InitLinkedListStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
736 DMA_InitLinkedListStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
737 DMA_InitLinkedListStruct->TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER;
738 DMA_InitLinkedListStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
739 }
740
741 /**
742 * @brief De-initialize the DMA linked list.
743 * @note This API is used for all available DMA channels.
744 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
745 * helper macros :
746 * @arg @ref LL_DMA_GET_INSTANCE
747 * @arg @ref LL_DMA_GET_CHANNEL
748 * @param DMAx DMAx Instance
749 * @param Channel This parameter can be one of the following values:
750 * @arg @ref LL_DMA_CHANNEL_0
751 * @arg @ref LL_DMA_CHANNEL_1
752 * @arg @ref LL_DMA_CHANNEL_2
753 * @arg @ref LL_DMA_CHANNEL_3
754 * @arg @ref LL_DMA_CHANNEL_4
755 * @arg @ref LL_DMA_CHANNEL_5
756 * @arg @ref LL_DMA_CHANNEL_6
757 * @arg @ref LL_DMA_CHANNEL_7
758 * @arg @ref LL_DMA_CHANNEL_8
759 * @arg @ref LL_DMA_CHANNEL_9
760 * @arg @ref LL_DMA_CHANNEL_10
761 * @arg @ref LL_DMA_CHANNEL_11
762 * @arg @ref LL_DMA_CHANNEL_12
763 * @arg @ref LL_DMA_CHANNEL_13
764 * @arg @ref LL_DMA_CHANNEL_14
765 * @arg @ref LL_DMA_CHANNEL_15
766 * @retval An ErrorStatus enumeration value:
767 * - SUCCESS : DMA registers are de-initialized.
768 * - ERROR : DMA registers are not de-initialized.
769 */
LL_DMA_List_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)770 uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
771 {
772 return LL_DMA_DeInit(DMAx, Channel);
773 }
774
775 /**
776 * @brief Initialize the DMA linked list according to the specified parameters
777 * in LL_DMA_InitLinkedListTypeDef.
778 * @note This API is used for all available DMA channels.
779 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
780 * helper macros :
781 * @arg @ref LL_DMA_GET_INSTANCE
782 * @arg @ref LL_DMA_GET_CHANNEL
783 * @param DMAx DMAx Instance
784 * @param Channel This parameter can be one of the following values:
785 * @arg @ref LL_DMA_CHANNEL_0
786 * @arg @ref LL_DMA_CHANNEL_1
787 * @arg @ref LL_DMA_CHANNEL_2
788 * @arg @ref LL_DMA_CHANNEL_3
789 * @arg @ref LL_DMA_CHANNEL_4
790 * @arg @ref LL_DMA_CHANNEL_5
791 * @arg @ref LL_DMA_CHANNEL_6
792 * @arg @ref LL_DMA_CHANNEL_7
793 * @arg @ref LL_DMA_CHANNEL_8
794 * @arg @ref LL_DMA_CHANNEL_9
795 * @arg @ref LL_DMA_CHANNEL_10
796 * @arg @ref LL_DMA_CHANNEL_11
797 * @arg @ref LL_DMA_CHANNEL_12
798 * @arg @ref LL_DMA_CHANNEL_13
799 * @arg @ref LL_DMA_CHANNEL_14
800 * @arg @ref LL_DMA_CHANNEL_15
801 * @param DMA_InitLinkedListStruct pointer to
802 * a @ref LL_DMA_InitLinkedListTypeDef structure.
803 * @retval An ErrorStatus enumeration value:
804 * - SUCCESS : DMA registers are initialized.
805 * - ERROR : Not applicable.
806 */
LL_DMA_List_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitLinkedListTypeDef * DMA_InitLinkedListStruct)807 uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
808 {
809 /* Check the DMA Instance DMAx and Channel parameters*/
810 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
811
812 /* Check the DMA parameters from DMA_InitLinkedListStruct */
813 assert_param(IS_LL_DMA_PRIORITY(DMA_InitLinkedListStruct->Priority));
814 assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitLinkedListStruct->LinkStepMode));
815 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitLinkedListStruct->TransferEventMode));
816 /* Check DMA instance */
817 if ((IS_LL_HPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) || (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U))
818 {
819 assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitLinkedListStruct->LinkAllocatedPort));
820 }
821
822 /*-------------------------- DMAx CCR Configuration --------------------------
823 * Configure the control parameter :
824 * - LinkAllocatedPort: DMA_CCR_LAP bit
825 * LinkAllocatedPort field is supported only by GPDMA channels.
826 * - LinkStepMode: DMA_CCR_LSM bit
827 * - Priority: DMA_CCR_PRIO [23:22] bits
828 */
829 LL_DMA_ConfigControl(DMAx, Channel, DMA_InitLinkedListStruct->Priority | \
830 DMA_InitLinkedListStruct->LinkAllocatedPort | \
831 DMA_InitLinkedListStruct->LinkStepMode);
832
833 /*-------------------------- DMAx CTR2 Configuration -------------------------
834 * Configure the channel transfer parameter :
835 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
836 */
837 LL_DMA_SetTransferEventMode(DMAx, Channel, DMA_InitLinkedListStruct->TransferEventMode);
838
839 return (uint32_t)SUCCESS;
840 }
841
842 /**
843 * @brief Set each @ref LL_DMA_InitNodeTypeDef field to default value.
844 * @param DMA_InitNodeStruct Pointer to a @ref LL_DMA_InitNodeTypeDef
845 * structure.
846 * @retval None.
847 */
LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef * DMA_InitNodeStruct)848 void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct)
849 {
850 /* Set DMA_InitNodeStruct fields to default values */
851 #if defined (CPU_IN_SECURE_STATE)
852 DMA_InitNodeStruct->DestSecure = LL_DMA_CHANNEL_DEST_NSEC;
853 #endif /* CPU_IN_SECURE_STATE */
854 DMA_InitNodeStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
855 DMA_InitNodeStruct->DestWordExchange = LL_DMA_DEST_WORD_PRESERVE;
856 DMA_InitNodeStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
857 DMA_InitNodeStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
858 DMA_InitNodeStruct->DestBurstLength = 1U;
859 DMA_InitNodeStruct->DestIncMode = LL_DMA_DEST_FIXED;
860 DMA_InitNodeStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
861 #if defined (CPU_IN_SECURE_STATE)
862 DMA_InitNodeStruct->SrcSecure = LL_DMA_CHANNEL_SRC_NSEC;
863 #endif /* CPU_IN_SECURE_STATE */
864 DMA_InitNodeStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
865 DMA_InitNodeStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
866 DMA_InitNodeStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
867 DMA_InitNodeStruct->SrcBurstLength = 1U;
868 DMA_InitNodeStruct->SrcIncMode = LL_DMA_SRC_FIXED;
869 DMA_InitNodeStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
870 DMA_InitNodeStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
871 DMA_InitNodeStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
872 DMA_InitNodeStruct->TriggerSelection = 0x00000000U;
873 DMA_InitNodeStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
874 DMA_InitNodeStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
875 DMA_InitNodeStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
876 DMA_InitNodeStruct->Request = 0x00000000U;
877 DMA_InitNodeStruct->Mode = LL_DMA_NORMAL;
878 DMA_InitNodeStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
879 DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
880 DMA_InitNodeStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT;
881 DMA_InitNodeStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT;
882 DMA_InitNodeStruct->BlkRptCount = 0x00000000U;
883 DMA_InitNodeStruct->BlkDataLength = 0x00000000U;
884 DMA_InitNodeStruct->SrcAddress = 0x00000000U;
885 DMA_InitNodeStruct->DestAddress = 0x00000000U;
886 DMA_InitNodeStruct->DestAddrOffset = 0x00000000U;
887 DMA_InitNodeStruct->SrcAddrOffset = 0x00000000U;
888 DMA_InitNodeStruct->BlkRptDestAddrOffset = 0x00000000U;
889 DMA_InitNodeStruct->BlkRptSrcAddrOffset = 0x00000000U;
890 DMA_InitNodeStruct->UpdateRegisters = (LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 | \
891 LL_DMA_UPDATE_CBR1 | LL_DMA_UPDATE_CSAR | \
892 LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CTR3 | \
893 LL_DMA_UPDATE_CBR2 | LL_DMA_UPDATE_CLLR);
894 DMA_InitNodeStruct->NodeType = LL_DMA_GPDMA_LINEAR_NODE;
895 }
896
897 /**
898 * @brief Initializes DMA linked list node according to the specified
899 * parameters in the DMA_InitNodeStruct.
900 * @note Warning: the maximum allowed AXI burst length shall not exceed 16.
901 * Otherwise, an error will be returned and no initialization performed.
902 * @param DMA_InitNodeStruct Pointer to a LL_DMA_InitNodeTypeDef structure
903 * that contains linked list node
904 * registers configurations.
905 * @param pNode Pointer to linked list node to fill according to
906 * LL_DMA_LinkNodeTypeDef parameters.
907 * @retval None
908 */
LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef * DMA_InitNodeStruct,LL_DMA_LinkNodeTypeDef * pNode)909 uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode)
910 {
911 uint32_t reg_counter = 0U;
912
913 /* Check the DMA Node type */
914 assert_param(IS_LL_DMA_LINK_NODETYPE(DMA_InitNodeStruct->NodeType));
915
916 /* Check the DMA parameters from DMA_InitNodeStruct */
917 assert_param(IS_LL_DMA_DIRECTION(DMA_InitNodeStruct->Direction));
918
919 /* Check direction */
920 if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
921 {
922 assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitNodeStruct->Request));
923 }
924
925 assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitNodeStruct->DataAlignment));
926 assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitNodeStruct->SrcDataWidth));
927 assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitNodeStruct->DestDataWidth));
928 assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitNodeStruct->SrcIncMode));
929 assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitNodeStruct->DestIncMode));
930 assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitNodeStruct->BlkDataLength));
931 assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitNodeStruct->TriggerPolarity));
932 assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitNodeStruct->BlkHWRequest));
933 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitNodeStruct->TransferEventMode));
934 assert_param(IS_LL_DMA_LINK_UPDATE_REGISTERS(DMA_InitNodeStruct->UpdateRegisters));
935 assert_param(IS_LL_DMA_MODE(DMA_InitNodeStruct->Mode));
936
937 #if defined (CPU_IN_SECURE_STATE)
938 assert_param(IS_LL_DMA_CHANNEL_SRC_SEC(DMA_InitNodeStruct->SrcSecure));
939 assert_param(IS_LL_DMA_CHANNEL_DEST_SEC(DMA_InitNodeStruct->DestSecure));
940 #endif /* CPU_IN_SECURE_STATE */
941
942 /* Check trigger polarity */
943 if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
944 {
945 assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode));
946 assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection));
947 }
948
949 {
950 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength));
951 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength));
952 assert_param(IS_LL_DMA_DEST_WORD_EXCHANGE(DMA_InitNodeStruct->DestWordExchange));
953 assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitNodeStruct->DestHWordExchange));
954 assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitNodeStruct->DestByteExchange));
955 assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitNodeStruct->SrcByteExchange));
956 assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitNodeStruct->SrcAllocatedPort));
957 assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitNodeStruct->DestAllocatedPort));
958 }
959
960 /* Check DMA channel */
961 if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || \
962 (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
963 {
964 assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitNodeStruct->BlkRptCount));
965 assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitNodeStruct->SrcAddrUpdateMode));
966 assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitNodeStruct->DestAddrUpdateMode));
967 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->SrcAddrOffset));
968 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->DestAddrOffset));
969 assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode));
970 assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptDestAddrUpdateMode));
971 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptSrcAddrOffset));
972 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptDestAddrOffset));
973 }
974
975 if ((DMA_InitNodeStruct->NodeType & (LL_DMA_HPDMA_2D_NODE | LL_DMA_HPDMA_LINEAR_NODE)) != 0U)
976 {
977 if (((DMA_InitNodeStruct->SrcAllocatedPort & DMA_CTR1_SAP) == LL_DMA_SRC_ALLOCATED_PORT0) &&
978 (DMA_InitNodeStruct->SrcBurstLength > 16U))
979 {
980 return (uint32_t)ERROR;
981 }
982 if (((DMA_InitNodeStruct->DestAllocatedPort & DMA_CTR1_DAP) == LL_DMA_DEST_ALLOCATED_PORT0) &&
983 (DMA_InitNodeStruct->DestBurstLength > 16U))
984 {
985 return (uint32_t)ERROR;
986 }
987 }
988
989 /* Check if CTR1 register update is enabled */
990 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR1) == LL_DMA_UPDATE_CTR1)
991 {
992 /*-------------------------- DMAx CTR1 Configuration -----------------------
993 * Configure the Data transfer parameter :
994 * - DestAllocatedPort: DMA_CTR1_DAP bit
995 * - DestWordExchange: DMA_CTR1_DWX bit
996 * - DestHWordExchange: DMA_CTR1_DHX bit
997 * - DestByteExchange: DMA_CTR1_DBX bit
998 * - DestIncMode: DMA_CTR1_DINC bit
999 * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
1000 * - SrcAllocatedPort: DMA_CTR1_SAP bit
1001 * - SrcByteExchange: DMA_CTR1_SBX bit
1002 * - DataAlignment: DMA_CTR1_PAM [12:11] bits
1003 * - SrcIncMode: DMA_CTR1_SINC bit
1004 * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
1005 * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
1006 * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
1007 */
1008
1009 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->DestIncMode | \
1010 DMA_InitNodeStruct->DestDataWidth | \
1011 DMA_InitNodeStruct->DataAlignment | \
1012 DMA_InitNodeStruct->SrcIncMode | \
1013 DMA_InitNodeStruct->SrcDataWidth);
1014
1015 #if defined (CPU_IN_SECURE_STATE)
1016 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestSecure | \
1017 DMA_InitNodeStruct->SrcSecure);
1018 #endif /* CPU_IN_SECURE_STATE */
1019
1020 /* Update CTR1 register fields */
1021 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort | \
1022 DMA_InitNodeStruct->DestWordExchange | \
1023 DMA_InitNodeStruct->DestHWordExchange | \
1024 DMA_InitNodeStruct->DestByteExchange | \
1025 ((DMA_InitNodeStruct->DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) | \
1026 DMA_InitNodeStruct->SrcAllocatedPort | \
1027 DMA_InitNodeStruct->SrcByteExchange | \
1028 ((DMA_InitNodeStruct->SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos));
1029
1030 /* Increment counter for the next register */
1031 reg_counter++;
1032 }
1033
1034
1035 /* Check if CTR2 register update is enabled */
1036 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR2) == LL_DMA_UPDATE_CTR2)
1037 {
1038 /*-------------------------- DMAx CTR2 Configuration -----------------------
1039 * Configure the channel transfer parameter :
1040 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
1041 * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
1042 * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
1043 * - Mode: DMA_CTR2_PFREQ bit
1044 * - BlkHWRequest: DMA_CTR2_BREQ bit
1045 * - Direction: DMA_CTR2_DREQ bit
1046 * - Direction: DMA_CTR2_SWREQ bit
1047 * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
1048 * - Request: DMA_CTR2_REQSEL [6:0] bits
1049 */
1050 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->TransferEventMode | \
1051 DMA_InitNodeStruct->TriggerPolarity | \
1052 DMA_InitNodeStruct->BlkHWRequest | \
1053 DMA_InitNodeStruct->Mode | \
1054 DMA_InitNodeStruct->Direction);
1055
1056 /* Check direction */
1057 if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
1058 {
1059 pNode->LinkRegisters[reg_counter] |= DMA_InitNodeStruct->Request & DMA_CTR2_REQSEL;
1060 }
1061
1062 /* Check trigger polarity */
1063 if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
1064 {
1065 pNode->LinkRegisters[reg_counter] |= (((DMA_InitNodeStruct->TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & \
1066 DMA_CTR2_TRIGSEL) | DMA_InitNodeStruct->TriggerMode);
1067 }
1068
1069
1070 /* Increment counter for the next register */
1071 reg_counter++;
1072 }
1073
1074 /* Check if CBR1 register update is enabled */
1075 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR1) == LL_DMA_UPDATE_CBR1)
1076 {
1077 /*-------------------------- DMAx CBR1 Configuration -----------------------
1078 * Configure the Transfer Block counters and update mode with parameter :
1079 * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
1080 * - BlkRptCount: DMA_CBR1_BRC[26:16] bits
1081 * BlkRptCount field is supported only by 2D addressing channels.
1082 * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit
1083 * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels.
1084 * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit
1085 * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels.
1086 * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit
1087 * SrcAddrUpdateMode field is supported only by 2D addressing channels.
1088 * - DestAddrUpdateMode: DMA_CBR1_DDEC bit
1089 * DestAddrUpdateMode field is supported only by 2D addressing channels.
1090 */
1091 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->BlkDataLength;
1092
1093 /* Update CBR1 register fields for 2D addressing channels */
1094 if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || \
1095 (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
1096 {
1097 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->BlkRptDestAddrUpdateMode | \
1098 DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode | \
1099 DMA_InitNodeStruct->DestAddrUpdateMode | \
1100 DMA_InitNodeStruct->SrcAddrUpdateMode | \
1101 ((DMA_InitNodeStruct->BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC));
1102 }
1103
1104 /* Increment counter for the next register */
1105 reg_counter++;
1106 }
1107
1108 /* Check if CSAR register update is enabled */
1109 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CSAR) == LL_DMA_UPDATE_CSAR)
1110 {
1111 /*-------------------------- DMAx CSAR Configuration -----------------------
1112 * Configure the Transfer Block counters and update mode with parameter :
1113 * - SrcAddress: DMA_CSAR_SA[31:0] bits
1114 */
1115 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->SrcAddress;
1116
1117 /* Increment counter for the next register */
1118 reg_counter++;
1119 }
1120
1121
1122 /* Check if CDAR register update is enabled */
1123 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CDAR) == LL_DMA_UPDATE_CDAR)
1124 {
1125 /*-------------------------- DMAx CDAR Configuration -----------------------
1126 * Configure the Transfer Block counters and update mode with parameter :
1127 * - DestAddress: DMA_CDAR_DA[31:0] bits
1128 */
1129 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->DestAddress;
1130
1131 /* Increment counter for the next register */
1132 reg_counter++;
1133 }
1134
1135 /* Update CTR3 register fields for 2D addressing channels */
1136 if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
1137 {
1138 /* Check if CTR3 register update is enabled */
1139 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR3) == LL_DMA_UPDATE_CTR3)
1140 {
1141 /*-------------------------- DMAx CTR3 Configuration ---------------------
1142 * Configure the Block counters and update mode with parameter :
1143 * - DestAddressOffset: DMA_CTR3_DAO[12:0] bits
1144 * DestAddressOffset field is supported only by 2D addressing channels.
1145 * - SrcAddressOffset: DMA_CTR3_SAO[12:0] bits
1146 * SrcAddressOffset field is supported only by 2D addressing channels.
1147 */
1148 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->SrcAddrOffset | \
1149 ((DMA_InitNodeStruct->DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
1150
1151 /* Increment counter for the next register */
1152 reg_counter++;
1153 }
1154 }
1155
1156
1157 /* Update CBR2 register fields for 2D addressing channels */
1158 if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
1159 {
1160 /* Check if CBR2 register update is enabled */
1161 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR2) == LL_DMA_UPDATE_CBR2)
1162 {
1163 /*-------------------------- DMAx CBR2 Configuration ---------------------
1164 * Configure the Block counters and update mode with parameter :
1165 * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits
1166 * BlkRptDestAddrOffset field is supported only by 2D addressing channels.
1167 * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits
1168 * BlkRptSrcAddrOffset field is supported only by 2D addressing channels.
1169 */
1170 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->BlkRptSrcAddrOffset | \
1171 ((DMA_InitNodeStruct->BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & \
1172 DMA_CBR2_BRDAO));
1173
1174 /* Increment counter for the next register */
1175 reg_counter++;
1176 }
1177 }
1178
1179 /* Check if CLLR register update is enabled */
1180 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CLLR) == LL_DMA_UPDATE_CLLR)
1181 {
1182 /*-------------------------- DMAx CLLR Configuration -----------------------
1183 * Configure the Transfer Block counters and update mode with parameter :
1184 * - UpdateRegisters DMA_CLLR_UT1 bit
1185 * - UpdateRegisters DMA_CLLR_UT2 bit
1186 * - UpdateRegisters DMA_CLLR_UB1 bit
1187 * - UpdateRegisters DMA_CLLR_USA bit
1188 * - UpdateRegisters DMA_CLLR_UDA bit
1189 * - UpdateRegisters DMA_CLLR_UT3 bit
1190 * DMA_CLLR_UT3 bit is discarded for linear addressing channels.
1191 * - UpdateRegisters DMA_CLLR_UB2 bit
1192 * DMA_CLLR_UB2 bit is discarded for linear addressing channels.
1193 * - UpdateRegisters DMA_CLLR_ULL bit
1194 */
1195 pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CLLR_UT2 | \
1196 DMA_CLLR_UB1 | DMA_CLLR_USA | \
1197 DMA_CLLR_UDA | DMA_CLLR_ULL)));
1198
1199 /* Update CLLR register fields for 2D addressing channels */
1200 if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || \
1201 (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
1202 {
1203 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CLLR_UB2));
1204 }
1205 }
1206 else
1207 {
1208 /* Reset of the CLLR of the node being created */
1209 pNode->LinkRegisters[reg_counter] = 0U;
1210 }
1211
1212 return (uint32_t)SUCCESS;
1213 }
1214
1215 /**
1216 * @brief Connect Linked list Nodes.
1217 * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Linked list node.
1218 * @param PrevNodeCLLRIdx Offset of Previous Node CLLR register.
1219 * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
1220 * @param pNewLinkNode Pointer to new Linked list.
1221 * @param NewNodeCLLRIdx Offset of New Node CLLR register.
1222 * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
1223 * @retval None
1224 */
LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef * pPrevLinkNode,uint32_t PrevNodeCLLRIdx,LL_DMA_LinkNodeTypeDef * pNewLinkNode,uint32_t NewNodeCLLRIdx)1225 void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
1226 LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx)
1227 {
1228 pPrevLinkNode->LinkRegisters[PrevNodeCLLRIdx] = (((uint32_t)pNewLinkNode & DMA_CLLR_LA) | \
1229 (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \
1230 DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \
1231 DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL)));
1232 }
1233
1234 /**
1235 * @brief Disconnect the next linked list node.
1236 * @param pLinkNode Pointer to linked list node to be disconnected from the next one.
1237 * @param LinkNodeCLLRIdx Offset of Link Node CLLR register.
1238 * @retval None.
1239 */
LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef * pLinkNode,uint32_t LinkNodeCLLRIdx)1240 void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx)
1241 {
1242 pLinkNode->LinkRegisters[LinkNodeCLLRIdx] = 0;
1243 }
1244
1245 /**
1246 * @}
1247 */
1248
1249 /**
1250 * @}
1251 */
1252
1253 /**
1254 * @}
1255 */
1256
1257 #endif /* GPDMA1 || HPDMA1 */
1258
1259 /**
1260 * @}
1261 */
1262
1263 #endif /* USE_FULL_LL_DRIVER */
1264
1265
