1 /**
2 ******************************************************************************
3 * @file stm32n6xx_hal_rif.c
4 * @author MCD Application Team
5 * @brief RIF HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Resource Isolation Framework (RIF) peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2023 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ==============================================================================
24 ##### RIF main features #####
25 ==============================================================================
26 [..]
27 (+) Resource Isolation framework (RIF) is a comprehensive set of hardware
28 blocks designed to enforce and manage isolation of STM32 hardware resources
29 like memory and peripherals.
30
31 (+) Resource Isolation Framework (RIF) composed of the following sub-blocks:
32 (++) RIMC: Resource Isolation Master Controller
33 This sub-block assigns all non RIF-aware bus master to one
34 security domain by setting secure, privileged and compartment
35 information on the system bus.
36 Note that if non-secure software is permitted to configure one of
37 these peripherals, then this setting is ignored and all accesses
38 initiated by the peripheral are forced to be non-secure.
39 (++) RISC: Resource Isolation Slave Controller
40 This sub-block assigns all non-RIF aware peripherals to zero,
41 one or any security domains (secure, privilege, compartment).
42 (++) RISAF: Resource Isolation Slave unit for Address space (Full version)
43 This sub-block assigns memory regions and subregions to one or
44 more security domains (secure, privilege, compartment).
45 (++) IAC: Illegal Access Controller
46 This sub-block centralizes detection of RIF-related accesses,
47 managed by a secure application. Supported illegal accesses are:
48 secure, privileged.
49
50 [..]
51 (+) All the setter functions are protected under the CPU_AS_TRUSTED_DOMAIN
52 directive.
53 It ensures that only the trusted domain can manage the critical
54 configurations of the RIF.
55 This directive is defined in the CMSIS file.
56
57 ===============================================================================
58 ##### How to use this driver #####
59 ===============================================================================
60 [..]
61 *** Locking RIF components configuration ***
62 ============================================================
63 [..]
64 (#) Lock and get the lock configuration of RIMC registers until next reset
65 with HAL_RIF_RIMC_Lock / HAL_RIF_RIMC_GetLock.
66 (#) Lock and get the lock configuration of RISC registers until next reset
67 with HAL_RIF_RISC_Lock / HAL_RIF_RISC_GetLock.
68 (#) Lock and get the lock configuration of slave resources registers until
69 next reset with HAL_RIF_RISC_SlaveConfigLock / HAL_RIF_RISC_GetSlaveConfigLock.
70 (#) Lock and get the lock configuration of RISAF registers until next reset
71 with HAL_RIF_RISAF_Lock / HAL_RIF_RISAF_GetLock.
72
73 *** Context-related functions ***
74 ============================================================
75 [..]
76 (#) Set or get Debugger Access Port Compartment ID with HAL_RIF_RIMC_SetDebugAccessPortCID /
77 HAL_RIF_RIMC_GetDebugAccessPortCID functions.
78 (#) Check the Debug Domain and Global Debug Domain status with
79 HAL_RIF_RIMC_GetDebugStatus.
80
81 #if defined(GENERATOR_RIF_FEATURE_ENCRYPTION_IMPLEMENTED)
82 *** Encryption-related functions ***
83 ============================================================
84 [..]
85 (#) Read of write RISAF encryption keys and related flags.
86
87 #endif
88 *** Configuration of master-related attributes ***
89 ============================================================
90 [..]
91 (#) Set or get the secure, privilege and compartment configuration of a
92 bus master thanks to the HAL_RIF_RIMC_ConfigMasterAttributes /
93 HAL_RIF_RIMC_GetConfigMasterAttributes functions.
94 (#) Lock and get lock status the bus master attributes configuration until
95 next system reset using HAL_RIF_RIMC_Lock.
96
97 *** Configuration of slave-related attributes ***
98 ============================================================
99 [..]
100 (#) Set or get the secure and privilege configuration of a bus slave
101 thanks to the HAL_RIF_RISC_SetSlaveSecureAttributes /
102 HAL_RIF_RISC_GetSlaveSecureAttributes functions.
103 (#) Lock and get lock status each bus slave attributes configuration using
104 HAL_RIF_RISC_SlaveConfigLock or lock the whole RISC configuration with
105 HAL_RIF_RISC_Lock until next system reset.
106
107 *** Configuration of RISAF attributes ***
108 ============================================================
109 [..]
110 (#) Set or get a base region configuration with HAL_RIF_RISAF_ConfigBaseRegion /
111 HAL_RIF_RISAF_GetConfigBaseRegion.
112 (#) Set or get a subregion configuration with HAL_RIF_RISAF_ConfigSubRegion /
113 HAL_RIF_RISAF_GetConfigSubRegion.
114 (#) Delegate a subregion configuration to another CID with HAL_RIF_RISAF_ConfigSubRegionDelegation.
115 (#) Get the data from an illegal access to a protected memory region with
116 HAL_RIF_RISAF_GetIllegalAccess.
117
118 *** IAC related functions ***
119 ============================================================
120 [..]
121 (#) Enable or disable peripheral illegal access detection with HAL_RIF_IAC_EnableIT /
122 HAL_RIF_IAC_DisableIT.
123 (#) Retrieve an illegal access flag from a designated peripheral with HAL_RIF_IAC_GetFlag
124 or clear it with HAL_RIF_IAC_ClearFlag.
125 (#) Illegal access interrupt service routines are served by HAL_RIF_IRQHandler()
126 and user can add his own code using HAL_RIF_ILA_Callback().
127
128 @endverbatim
129 ******************************************************************************
130 */
131
132 /* Includes ------------------------------------------------------------------*/
133 #include "stm32n6xx_hal.h"
134
135 /** @addtogroup STM32N6xx_HAL_Driver
136 * @{
137 */
138
139 /** @defgroup RIF RIF
140 * @brief RIF HAL module driver.
141 * @{
142 */
143
144 #ifdef HAL_RIF_MODULE_ENABLED
145
146 /* Private typedef -----------------------------------------------------------*/
147 /* Private defines ------------------------------------------------------------*/
148 /** @addtogroup RIF_Private_Defines RIF Private Defines
149 * @{
150 */
151 #define RIF_PERIPH_IAC_REG_MAX 4U
152 /**
153 * @}
154 */
155
156 /* Private macro -------------------------------------------------------------*/
157 /* Private variables ---------------------------------------------------------*/
158 /* Private function prototypes -----------------------------------------------*/
159 /* Exported functions --------------------------------------------------------*/
160
161 /** @defgroup RIF_Exported_Functions RIF Exported Functions
162 * @{
163 */
164
165 /** @defgroup RIF_Exported_Functions_Group1 RIMC Configuration functions
166 * @brief RIMC Configuration functions
167 *
168 @verbatim
169 ==============================================================================
170 ##### RIMC Configuration functions #####
171 ==============================================================================
172 [..]
173 This section provides functions allowing to configure RIMC
174 RIMC is Resource Isolation Master Controller
175 @endverbatim
176 * @{
177 */
178 #if defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE)
179 /**
180 * @brief Lock overall configuration of RIMC.
181 * @note Once set, the overall configuration of RIMC cannot be modified
182 * upon next system reset.
183 * @note This API is protected by the Trusted Domain compilation directive.
184 * @note This API is protected by the TrustZone Enabled compilation directive.
185 * @retval None
186 */
HAL_RIF_RIMC_Lock(void)187 void HAL_RIF_RIMC_Lock(void)
188 {
189 /* Set RIMC Lock bit */
190 RIFSC->RIMC_CR |= RIFSC_RIMC_CR_GLOCK;
191 }
192 #endif /* defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE) */
193
194 /**
195 * @brief Get RIMC global lock status.
196 * @retval RIF_LOCK_ENABLE if RIMC configuration is locked, else RIF_LOCK_DISABLE
197 */
HAL_RIF_RIMC_GetLock(void)198 uint32_t HAL_RIF_RIMC_GetLock(void)
199 {
200 uint32_t lock_status;
201
202 /* Read RIMC lock bit */
203 lock_status = (RIFSC->RIMC_CR & RIF_LOCK_ENABLE);
204
205 return lock_status;
206 }
207
208 #if defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE)
209 /**
210 * @brief Change the Debugger Access Port ID
211 * @note This API is protected by the Trusted Domain compilation directive.
212 * @note This API is protected by the TrustZone Enabled compilation directive.
213 * @param CID specifies the Debugger Access Port CID
214 * This parameter can be a combination of following values:
215 * @arg @ref RIF_CID_0 Compartment 0 ID selected as Debug access port ID
216 * @arg @ref RIF_CID_1 Compartment 1 ID selected as Debug access port ID
217 * @arg @ref RIF_CID_2 Compartment 2 ID selected as Debug access port ID
218 * @arg @ref RIF_CID_3 Compartment 3 ID selected as Debug access port ID
219 * @arg @ref RIF_CID_4 Compartment 4 ID selected as Debug access port ID
220 * @arg @ref RIF_CID_5 Compartment 5 ID selected as Debug access port ID
221 * @arg @ref RIF_CID_6 Compartment 6 ID selected as Debug access port ID
222 * @arg @ref RIF_CID_7 Compartment 7 ID selected as Debug access port ID
223 * @retval None
224 */
HAL_RIF_RIMC_SetDebugAccessPortCID(uint32_t CID)225 void HAL_RIF_RIMC_SetDebugAccessPortCID(uint32_t CID)
226 {
227 uint32_t dap_cid;
228 uint32_t rimc_cr_reg;
229
230 /* Check the parameter */
231 assert_param(IS_RIF_SINGLE_CID(CID));
232
233 /* Set Debug Access Port CID bits */
234 dap_cid = POSITION_VAL(CID);
235 rimc_cr_reg = RIFSC->RIMC_CR;
236 rimc_cr_reg &= (~RIFSC_RIMC_CR_DAPCID);
237 rimc_cr_reg |= (dap_cid << RIFSC_RIMC_CR_DAPCID_Pos);
238 RIFSC->RIMC_CR = rimc_cr_reg;
239 }
240 #endif /* defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE) */
241
242 /**
243 * @brief Get the Debugger Access Port ID
244 * @retval Debugger Access Port ID
245 */
HAL_RIF_RIMC_GetDebugAccessPortCID(void)246 uint32_t HAL_RIF_RIMC_GetDebugAccessPortCID(void)
247 {
248 uint32_t dap_cid;
249
250 /* Read Debug Access Port CID bits */
251 dap_cid = (RIFSC->RIMC_CR & RIFSC_RIMC_CR_DAPCID) >> RIFSC_RIMC_CR_DAPCID_Pos;
252 dap_cid = (1UL << dap_cid);
253 return dap_cid;
254 }
255
256 #if defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE)
257 /**
258 * @brief Configure CID, Secure and Privilege attributes for the designated master.
259 * @note RIF_CID_7 is not an authorized value for the MasterCID field.
260 * @note This API is protected by the Trusted Domain compilation directive.
261 * @note This API is protected by the TrustZone Enabled compilation directive.
262 * @param MasterId specifies the index of the bus master.
263 * This parameter can be one of @ref RIF_MASTER_INDEX
264 * @param pConfig Pointer on Master Isolation configuration structure
265 * @retval None
266 */
HAL_RIF_RIMC_ConfigMasterAttributes(uint32_t MasterId,const RIMC_MasterConfig_t * pConfig)267 void HAL_RIF_RIMC_ConfigMasterAttributes(uint32_t MasterId, const RIMC_MasterConfig_t *pConfig)
268 {
269 uint32_t master_cid;
270 uint32_t rimc_attr_val;
271
272 /* Check the parameter */
273 assert_param(pConfig != (void *)NULL);
274 assert_param(IS_RIF_MASTER_INDEX(MasterId));
275 assert_param(IS_RIF_SINGLE_CID(pConfig->MasterCID));
276 assert_param(IS_RIF_MASTER_CID(pConfig->MasterCID));
277 assert_param(IS_RIF_SEC_PRIV_ATTRIBUTE(pConfig->SecPriv));
278
279 master_cid = POSITION_VAL(pConfig->MasterCID);
280 rimc_attr_val = RIFSC->RIMC_ATTRx[MasterId];
281 rimc_attr_val &= (~(RIFSC_RIMC_ATTRx_MCID | RIFSC_RIMC_ATTRx_MPRIV | RIFSC_RIMC_ATTRx_MSEC));
282 rimc_attr_val |= ((master_cid << RIFSC_RIMC_ATTRx_MCID_Pos) | (pConfig->SecPriv << RIFSC_RIMC_ATTRx_MSEC_Pos));
283 RIFSC->RIMC_ATTRx[MasterId] = rimc_attr_val;
284 }
285 #endif /* defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE) */
286
287 /**
288 * @brief Get the CID, Secure and Privilege attributes for the designated master.
289 * @note This API is protected by the Trusted Domain compilation directive.
290 * @param MasterId specifies the index of the bus master.
291 * This parameter can be one of @ref RIF_MASTER_INDEX
292 * @param pConfig Pointer on Master Isolation configuration structure
293 * @retval None
294 */
HAL_RIF_RIMC_GetConfigMasterAttributes(uint32_t MasterId,RIMC_MasterConfig_t * pConfig)295 void HAL_RIF_RIMC_GetConfigMasterAttributes(uint32_t MasterId, RIMC_MasterConfig_t *pConfig)
296 {
297 uint32_t master_cid;
298 uint32_t rimc_attr_val;
299
300 /* Check the parameter */
301 assert_param(pConfig != (void *)NULL);
302 assert_param(IS_RIF_MASTER_INDEX(MasterId));
303
304 rimc_attr_val = RIFSC->RIMC_ATTRx[MasterId];
305 pConfig->SecPriv = ((rimc_attr_val & (RIFSC_RIMC_ATTRx_MPRIV | RIFSC_RIMC_ATTRx_MSEC))
306 >> RIFSC_RIMC_ATTRx_MSEC_Pos);
307 master_cid = ((rimc_attr_val & RIFSC_RIMC_ATTRx_MCID) >> RIFSC_RIMC_ATTRx_MCID_Pos);
308 pConfig->MasterCID = (1UL << master_cid);
309 }
310 /**
311 * @}
312 */
313
314 /** @defgroup RIF_Exported_Functions_Group2 RIFSC Configuration functions
315 * @brief RIFSC Configuration functions
316 *
317 @verbatim
318 ==============================================================================
319 ##### RIFSC Configuration functions #####
320 ==============================================================================
321 [..]
322 This section provides functions allowing to configure RIFSC
323 RIFSC is Resource Isolation Framework Secure Controller
324 @endverbatim
325 * @{
326 */
327 #if defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE)
328 /**
329 * @brief Lock overall configuration of RISC.
330 * @note Once set, the overall configuration of RIFSC cannot be modified
331 * upon next system reset.
332 * @note This API is protected by the Trusted Domain compilation directive.
333 * @note This API is protected by the TrustZone Enabled compilation directive.
334 * @retval None
335 */
HAL_RIF_RISC_Lock(void)336 void HAL_RIF_RISC_Lock(void)
337 {
338 /* Set RISC Lock bit */
339 RIFSC->RISC_CR |= RIFSC_RISC_CR_GLOCK;
340 }
341 #endif /* defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE) */
342
343 /**
344 * @brief Get the RIFSC global lock status.
345 * @retval 1 if RISC configuration is locked, else 0
346 */
HAL_RIF_RISC_GetLock(void)347 uint32_t HAL_RIF_RISC_GetLock(void)
348 {
349 uint32_t lock_status;
350
351 /* Read RISC lock bit */
352 lock_status = (RIFSC->RISC_CR & RIF_LOCK_ENABLE);
353
354 return lock_status;
355 }
356
357 /**
358 * @brief Configure the Security and Privilege of a designated slave peripheral.
359 * @param PeriphId specifies the index of the bus slave.
360 * This parameter can be one of @ref RIF_PERIPHERAL_INDEX
361 * @param SecPriv specifies the security and privilege attributes of the peripheral.
362 * This parameter can be one or a combination of @ref RIF_SEC_PRIV
363 * @retval None
364 */
HAL_RIF_RISC_SetSlaveSecureAttributes(uint32_t PeriphId,uint32_t SecPriv)365 void HAL_RIF_RISC_SetSlaveSecureAttributes(uint32_t PeriphId, uint32_t SecPriv)
366 {
367 __IO uint32_t sec_reg_val;
368
369 assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_RCC_PERIPH_INDEX(PeriphId));
370 assert_param(IS_RIF_SEC_PRIV_ATTRIBUTE(SecPriv));
371
372 sec_reg_val = RIFSC->RISC_SECCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT];
373 sec_reg_val &= (~(1U << (PeriphId & RIF_PERIPH_BIT_POSITION)));
374 sec_reg_val |= ((SecPriv & RIF_ATTRIBUTE_SEC) << (PeriphId & RIF_PERIPH_BIT_POSITION));
375 RIFSC->RISC_SECCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT] = sec_reg_val;
376
377 sec_reg_val = RIFSC->RISC_PRIVCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT];
378 sec_reg_val &= (~(1U << (PeriphId & RIF_PERIPH_BIT_POSITION)));
379 sec_reg_val |= (((SecPriv & RIF_ATTRIBUTE_PRIV) >> 1U) << (PeriphId & RIF_PERIPH_BIT_POSITION));
380 RIFSC->RISC_PRIVCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT] = sec_reg_val;
381 }
382
383 /**
384 * @brief Get the Security and Privilege configuration of a designated slave peripheral.
385 * @param PeriphId specifies the index of the bus slave.
386 * This parameter can be one of @ref RIF_PERIPHERAL_INDEX
387 * @retval can be a combination of @ref RIF_SEC_PRIV
388 */
HAL_RIF_RISC_GetSlaveSecureAttributes(uint32_t PeriphId)389 uint32_t HAL_RIF_RISC_GetSlaveSecureAttributes(uint32_t PeriphId)
390 {
391 uint32_t sec_attr;
392 const __IO uint32_t *p_sec_reg;
393
394 assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_RCC_PERIPH_INDEX(PeriphId));
395
396 p_sec_reg = &(RIFSC->RISC_SECCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT]);
397 sec_attr = ((*p_sec_reg & ((uint32_t)RIF_ATTRIBUTE_SEC << (PeriphId & RIF_PERIPH_BIT_POSITION))) >> (PeriphId & RIF_PERIPH_BIT_POSITION));
398
399 p_sec_reg = &(RIFSC->RISC_PRIVCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT]);
400 sec_attr |= (((*p_sec_reg & ((uint32_t)RIF_ATTRIBUTE_SEC << (PeriphId & RIF_PERIPH_BIT_POSITION))) >> (PeriphId & RIF_PERIPH_BIT_POSITION)) << 1U);
401
402 return sec_attr;
403 }
404
405 #if defined(CPU_AS_TRUSTED_DOMAIN)
406 /**
407 * @brief Lock the Isolation and Security configuration of the designated slave peripheral.
408 * @note This API is protected by the Trusted Domain compilation directive.
409 * @param PeriphId specifies the index of the bus slave.
410 * This parameter can be one of @ref RIF_PERIPHERAL_INDEX
411 * @retval None
412 */
HAL_RIF_RISC_SlaveConfigLock(uint32_t PeriphId)413 void HAL_RIF_RISC_SlaveConfigLock(uint32_t PeriphId)
414 {
415 __IO uint32_t *p_lock_reg;
416
417 assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_RCC_PERIPH_INDEX(PeriphId));
418
419 /* Set RISC Peripheral Lock bit */
420 p_lock_reg = &(RIFSC->RISC_RCFGLOCKRx[PeriphId >> RIF_PERIPH_REG_SHIFT]);
421 *p_lock_reg |= (RIF_LOCK_ENABLE << (PeriphId & RIF_PERIPH_BIT_POSITION));
422 }
423 #endif /* defined(CPU_AS_TRUSTED_DOMAIN) */
424
425 /**
426 * @brief Get the Isolation and Security configuration lock status.
427 * @param PeriphId specifies the index of the bus slave.
428 * This parameter can be one of @ref RIF_PERIPHERAL_INDEX
429 * @retval 1 if the Isolation and Security configuration is locked, else 0
430 */
HAL_RIF_RISC_GetSlaveConfigLock(uint32_t PeriphId)431 uint32_t HAL_RIF_RISC_GetSlaveConfigLock(uint32_t PeriphId)
432 {
433 uint32_t lock_status;
434 const __IO uint32_t *p_lock_reg;
435
436 assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_RCC_PERIPH_INDEX(PeriphId));
437
438 p_lock_reg = &(RIFSC->RISC_RCFGLOCKRx[PeriphId >> RIF_PERIPH_REG_SHIFT]);
439 lock_status = ((*p_lock_reg & (RIF_LOCK_ENABLE << (PeriphId & RIF_PERIPH_BIT_POSITION))) >> (PeriphId & RIF_PERIPH_BIT_POSITION));
440
441 return lock_status;
442 }
443
444 /**
445 * @}
446 */
447
448 /** @defgroup RIF_Exported_Functions_Group4 RISAF Configuration functions
449 * @brief RISAF Configuration functions
450 *
451 @verbatim
452 ==============================================================================
453 ##### RISAF Configuration functions #####
454 ==============================================================================
455 [..]
456 This section provides functions allowing to configure RISAF
457 RISAL is Resource Isolation Slave unit for Address space protection (Full version)
458 @endverbatim
459 * @{
460 */
461 #if defined(CPU_AS_TRUSTED_DOMAIN)
462 /**
463 * @brief Lock overall configuration of RISAF.
464 * @note Once set, the overall configuration of RISAF cannot be modified
465 * upon next system reset.
466 * @note This API is protected by the Trusted Domain compilation directive.
467 * @param RISAFx specifies the RISAF instance.
468 * This parameter is one of the RISAF instances defined in the CMSIS.
469 * @retval None
470 */
HAL_RIF_RISAF_Lock(RISAF_TypeDef * RISAFx)471 void HAL_RIF_RISAF_Lock(RISAF_TypeDef *RISAFx)
472 {
473 /* Check the parameters */
474 assert_param(IS_RISAF_INSTANCE(RISAFx));
475
476 /* Set RISAF Lock bit */
477 RISAFx->CR |= RISAF_CR_GLOCK;
478 }
479 #endif /* defined(CPU_AS_TRUSTED_DOMAIN) */
480
481 /**
482 * @brief Get RISAF global lock status.
483 * @param RISAFx specifies the RISAF instance.
484 * This parameter is one of the RISAF instances defined in the CMSIS.
485 * @retval 1 if RISAF configuration is locked, else 0
486 */
HAL_RIF_RISAF_GetLock(const RISAF_TypeDef * RISAFx)487 uint32_t HAL_RIF_RISAF_GetLock(const RISAF_TypeDef *RISAFx)
488 {
489 uint32_t lock_status;
490
491 /* Read RIMC lock bit */
492 lock_status = (RISAFx->CR & RIF_LOCK_ENABLE);
493
494 return lock_status;
495 }
496
497 #if defined(GENERATOR_RIF_FEATURE_ENCRYPTION_IMPLEMENTED)
498 /**
499 * @brief Get encryption and key related flags.
500 * @param RISAFx specifies the RISAF instance.
501 * This parameter is one of the RISAF instances defined in the CMSIS.
502 * @retval A combination of the three encryption related flags
503 */
HAL_RIF_RISAF_GetEncryptionStatus(RISAF_TypeDef * RISAFx)504 uint32_t HAL_RIF_RISAF_GetEncryptionStatus(RISAF_TypeDef *RISAFx)
505 {
506 uint32_t tmp = 0;
507
508 return tmp;
509 }
510
511 #if defined(CPU_AS_TRUSTED_DOMAIN)
512 /**
513 * @brief Write the encryption keys used by the DDRMCE.
514 * @note This API is protected by the Trusted Domain compilation directive.
515 * @param RISAFx specifies the RISAF instance.
516 * This parameter is one of the RISAF instances defined in the CMSIS.
517 * @param Keys Pointer on the Encryption keys structure
518 * @retval None
519 */
HAL_RIF_RISAF_WriteEncryptionKeys(RISAF_TypeDef * RISAFx,RISAF_EncryptionKeys_t * Keys)520 void HAL_RIF_RISAF_WriteEncryptionKeys(RISAF_TypeDef *RISAFx, RISAF_EncryptionKeys_t *Keys)
521 {
522 }
523 #endif /* defined(CPU_AS_TRUSTED_DOMAIN) */
524
525 #endif /* defined(GENERATOR_RIF_FEATURE_ENCRYPTION_IMPLEMENTED) */
526 #if defined(CPU_AS_TRUSTED_DOMAIN)
527 /**
528 * @brief Configure a RISAF Base region.
529 * @note If pConfig->Filtering is equal to RISAF_FILTER_DISABLE, this API only disable the filtering without modifying
530 * its configuration.
531 * @note It is not possible to modify the start and end address of the region if the filtering is already enabled.
532 * @note This API is protected by the Trusted Domain compilation directive.
533 * @param RISAFx specifies the RISAF instance.
534 * This parameter is one of the RISAF instances defined in the CMSIS.
535 * @param Region specifies the RISAF region index
536 * This parameter can be one one of the following values:
537 * @arg @ref RISAF_REGION_1
538 * @arg @ref RISAF_REGION_2
539 * @arg @ref RISAF_REGION_3
540 * @arg @ref RISAF_REGION_4
541 * @arg @ref RISAF_REGION_5
542 * @arg @ref RISAF_REGION_6
543 * @arg @ref RISAF_REGION_7
544 * @arg @ref RISAF_REGION_8
545 * @arg @ref RISAF_REGION_9
546 * @arg @ref RISAF_REGION_10
547 * @arg @ref RISAF_REGION_11
548 * @arg @ref RISAF_REGION_12
549 * @arg @ref RISAF_REGION_13
550 * @arg @ref RISAF_REGION_14
551 * @arg @ref RISAF_REGION_15
552 * @param pConfig Pointer on RISAF Base Region configuration structure
553 * @retval None
554 */
HAL_RIF_RISAF_ConfigBaseRegion(RISAF_TypeDef * RISAFx,uint32_t Region,const RISAF_BaseRegionConfig_t * pConfig)555 void HAL_RIF_RISAF_ConfigBaseRegion(RISAF_TypeDef *RISAFx, uint32_t Region, const RISAF_BaseRegionConfig_t *pConfig)
556 {
557 /* Check the parameters */
558 assert_param(pConfig != (void *)NULL);
559 assert_param(IS_RISAF_INSTANCE(RISAFx));
560 assert_param(IS_RISAF_REGION(Region));
561 assert_param(IS_RISAF_MAX_REGION(RISAFx, Region));
562
563 /* Only disable the section */
564 if (pConfig->Filtering == RISAF_FILTER_DISABLE)
565 {
566 RISAFx->REG[Region].CFGR &= (~(RISAF_FILTER_ENABLE));
567 }
568 else
569 {
570 /* Check the parameters */
571 assert_param(IS_RISAF_FILTERING(pConfig->Filtering));
572 assert_param(IS_RIF_CID(pConfig->PrivWhitelist));
573 assert_param(IS_RIF_CID(pConfig->ReadWhitelist));
574 assert_param(IS_RIF_CID(pConfig->WriteWhitelist));
575 assert_param(IS_RIF_SEC_PRIV_ATTRIBUTE(pConfig->Secure));
576 assert_param(IS_RISAF_GRANULARITY(RISAFx, pConfig->StartAddress));
577 assert_param(IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(RISAFx, pConfig->StartAddress));
578 assert_param(IS_RISAF_GRANULARITY(RISAFx, (pConfig->EndAddress + 1U)));
579 assert_param(IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(RISAFx, pConfig->EndAddress));
580 assert_param(pConfig->StartAddress < pConfig->EndAddress);
581
582 /* Update region start and end addresses */
583 RISAFx->REG[Region].STARTR = pConfig->StartAddress;
584 RISAFx->REG[Region].ENDR = pConfig->EndAddress;
585
586 /* Update filtering mode, security and privilege attributes and whitelists */
587 RISAFx->REG[Region].CIDCFGR = (pConfig->ReadWhitelist | (pConfig->WriteWhitelist << RISAF_REGx_CIDCFGR_WRENC0_Pos));
588 RISAFx->REG[Region].CFGR = (pConfig->Filtering | (pConfig->Secure << RISAF_REGx_CFGR_SEC_Pos)
589 | (pConfig->PrivWhitelist << RISAF_REGx_CFGR_PRIVC0_Pos));
590 }
591 }
592 #endif /* defined(CPU_AS_TRUSTED_DOMAIN) */
593
594 /**
595 * @brief Get the configuration of a RISAF Base region.
596 * @param RISAFx specifies the RISAF instance.
597 * This parameter is one of the RISAF instances defined in the CMSIS.
598 * @param Region specifies the RISAF region index
599 * This parameter can be one one of the following values:
600 * @arg @ref RISAF_REGION_1
601 * @arg @ref RISAF_REGION_2
602 * @arg @ref RISAF_REGION_3
603 * @arg @ref RISAF_REGION_4
604 * @arg @ref RISAF_REGION_5
605 * @arg @ref RISAF_REGION_6
606 * @arg @ref RISAF_REGION_7
607 * @arg @ref RISAF_REGION_8
608 * @arg @ref RISAF_REGION_9
609 * @arg @ref RISAF_REGION_10
610 * @arg @ref RISAF_REGION_11
611 * @arg @ref RISAF_REGION_12
612 * @arg @ref RISAF_REGION_13
613 * @arg @ref RISAF_REGION_14
614 * @arg @ref RISAF_REGION_15
615 * @param pConfig Pointer on RISAF Base Region configuration structure
616 * @retval None
617 */
HAL_RIF_RISAF_GetConfigBaseRegion(const RISAF_TypeDef * RISAFx,uint32_t Region,RISAF_BaseRegionConfig_t * pConfig)618 void HAL_RIF_RISAF_GetConfigBaseRegion(const RISAF_TypeDef *RISAFx, uint32_t Region, RISAF_BaseRegionConfig_t *pConfig)
619 {
620 uint32_t cfgr_reg;
621 uint32_t cidcfgr_reg;
622
623 /* Check the parameters */
624 assert_param(IS_RISAF_INSTANCE(RISAFx));
625 assert_param(IS_RISAF_REGION(Region));
626 assert_param(IS_RISAF_MAX_REGION(RISAFx, Region));
627 assert_param(pConfig != (void *)NULL);
628
629 cfgr_reg = RISAFx->REG[Region].CFGR;
630 cidcfgr_reg = RISAFx->REG[Region].CIDCFGR;
631
632 pConfig->Filtering = (cfgr_reg & RISAF_REGx_CFGR_BREN);
633 pConfig->Secure = ((cfgr_reg & RISAF_REGx_CFGR_SEC) >> RISAF_REGx_CFGR_SEC_Pos);
634 pConfig->PrivWhitelist = ((cfgr_reg & (RIF_CID_MASK << RISAF_REGx_CFGR_PRIVC0_Pos)) >> RISAF_REGx_CFGR_PRIVC0_Pos);
635 pConfig->ReadWhitelist = (cidcfgr_reg & RIF_CID_MASK);
636 pConfig->WriteWhitelist = ((cidcfgr_reg & (RIF_CID_MASK << RISAF_REGx_CIDCFGR_WRENC0_Pos)) >> RISAF_REGx_CIDCFGR_WRENC0_Pos);
637 pConfig->StartAddress = RISAFx->REG[Region].STARTR;
638 pConfig->EndAddress = RISAFx->REG[Region].ENDR;
639 }
640
641 #if defined(CPU_AS_TRUSTED_DOMAIN)
642 /**
643 * @brief Delegate a Subregion configuration to another CID.
644 * @note This API is protected by the Trusted Domain compilation directive.
645 * @param RISAFx specifies the RISAF instance.
646 * This parameter is one of the RISAF instances defined in the CMSIS.
647 * @param Region specifies the RISAF region index
648 * This parameter can be one one of the following values:
649 * @arg @ref RISAF_REGION_1
650 * @arg @ref RISAF_REGION_2
651 * @arg @ref RISAF_REGION_3
652 * @arg @ref RISAF_REGION_4
653 * @arg @ref RISAF_REGION_5
654 * @arg @ref RISAF_REGION_6
655 * @arg @ref RISAF_REGION_7
656 * @arg @ref RISAF_REGION_8
657 * @arg @ref RISAF_REGION_9
658 * @arg @ref RISAF_REGION_10
659 * @arg @ref RISAF_REGION_11
660 * @arg @ref RISAF_REGION_12
661 * @arg @ref RISAF_REGION_13
662 * @arg @ref RISAF_REGION_14
663 * @arg @ref RISAF_REGION_15
664 * @param SubRegion specifies the RISAB Subregion index
665 * This parameter can be one of the following values:
666 * @arg @ref RISAF_SUBREGION_A
667 * @arg @ref RISAF_SUBREGION_B
668 * @param pConfig Pointer on RISAF Subregion configuration structure
669 * @retval None
670 */
HAL_RIF_RISAF_ConfigSubRegionDelegation(RISAF_TypeDef * RISAFx,uint32_t Region,uint32_t SubRegion,const RISAF_DelegationConfig_t * pConfig)671 void HAL_RIF_RISAF_ConfigSubRegionDelegation(RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion,
672 const RISAF_DelegationConfig_t *pConfig)
673 {
674 uint32_t cid;
675 uint32_t nestr_reg;
676
677 /* Check the parameters */
678 assert_param(pConfig != (void *)NULL);
679 assert_param(IS_RISAF_INSTANCE(RISAFx));
680 assert_param(IS_RISAF_REGION(Region));
681 assert_param(IS_RISAF_MAX_REGION(RISAFx, Region));
682 assert_param(IS_RISAF_SUBREGION(SubRegion));
683 assert_param(IS_RISAF_DELEGATION(pConfig->Delegation));
684 assert_param(IS_RIF_SINGLE_CID(pConfig->DelegatedCID));
685
686 /* Convert mask into bit position */
687 cid = POSITION_VAL(pConfig->DelegatedCID);
688
689 if (SubRegion == RISAF_SUBREGION_A)
690 {
691 nestr_reg = RISAFx->REG[Region].ANESTR;
692 nestr_reg &= (~(RISAF_REGx_zNESTR_DCCID | RISAF_REGx_zNESTR_DCEN));
693 nestr_reg |= ((cid << RISAF_REGx_zNESTR_DCCID_Pos) | pConfig->Delegation);
694 RISAFx->REG[Region].ANESTR = nestr_reg;
695 }
696 else
697 {
698 nestr_reg = RISAFx->REG[Region].BNESTR;
699 nestr_reg &= (~(RISAF_REGx_zNESTR_DCCID | RISAF_REGx_zNESTR_DCEN));
700 nestr_reg |= ((cid << RISAF_REGx_zNESTR_DCCID_Pos) | pConfig->Delegation);
701 RISAFx->REG[Region].BNESTR = nestr_reg;
702 }
703 }
704 #endif /* defined(CPU_AS_TRUSTED_DOMAIN) */
705
706 /**
707 * @brief Get the delegation configuration of a RISAF Subregion.
708 * @param RISAFx specifies the RISAF instance.
709 * This parameter is one of the RISAF instances defined in the CMSIS.
710 * @param Region specifies the RISAF region index
711 * This parameter can be one one of the following values:
712 * @arg @ref RISAF_REGION_1
713 * @arg @ref RISAF_REGION_2
714 * @arg @ref RISAF_REGION_3
715 * @arg @ref RISAF_REGION_4
716 * @arg @ref RISAF_REGION_5
717 * @arg @ref RISAF_REGION_6
718 * @arg @ref RISAF_REGION_7
719 * @arg @ref RISAF_REGION_8
720 * @arg @ref RISAF_REGION_9
721 * @arg @ref RISAF_REGION_10
722 * @arg @ref RISAF_REGION_11
723 * @arg @ref RISAF_REGION_12
724 * @arg @ref RISAF_REGION_13
725 * @arg @ref RISAF_REGION_14
726 * @arg @ref RISAF_REGION_15
727 * @param SubRegion specifies the RISAB Subregion index
728 * This parameter can be one of the following values:
729 * @arg @ref RISAF_SUBREGION_A
730 * @arg @ref RISAF_SUBREGION_B
731 * @param pConfig Pointer on RISAF Subregion configuration structure
732 * @retval None
733 */
HAL_RIF_RISAF_GetConfigSubRegionDelegation(const RISAF_TypeDef * RISAFx,uint32_t Region,uint32_t SubRegion,RISAF_DelegationConfig_t * pConfig)734 void HAL_RIF_RISAF_GetConfigSubRegionDelegation(const RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion,
735 RISAF_DelegationConfig_t *pConfig)
736 {
737 uint32_t cid;
738
739 /* Check the parameters */
740 assert_param(pConfig != (void *)NULL);
741 assert_param(IS_RISAF_INSTANCE(RISAFx));
742 assert_param(IS_RISAF_REGION(Region));
743 assert_param(IS_RISAF_MAX_REGION(RISAFx, Region));
744 assert_param(IS_RISAF_SUBREGION(SubRegion));
745
746 if (SubRegion == RISAF_SUBREGION_A)
747 {
748 pConfig->Delegation = (RISAFx->REG[Region].ANESTR & RISAF_REGx_zNESTR_DCEN);
749 cid = ((RISAFx->REG[Region].ANESTR & RISAF_REGx_zNESTR_DCCID) >> RISAF_REGx_zNESTR_DCCID_Pos);
750 }
751 else
752 {
753 pConfig->Delegation = (RISAFx->REG[Region].BNESTR & RISAF_REGx_zNESTR_DCEN);
754 cid = ((RISAFx->REG[Region].BNESTR & RISAF_REGx_zNESTR_DCCID) >> RISAF_REGx_zNESTR_DCCID_Pos);
755 }
756
757 pConfig->DelegatedCID = (1UL << cid);
758 }
759
760 /**
761 * @brief Configure a RISAF subregion.
762 * @note If pConfig->Filtering is equal to RISAF_FILTER_DISABLE, this API only disable the filtering without modifying
763 * its configuration. It also can lock the current subregion configuration.
764 * @note It is not possible to modify the start and end address of a subregion if the filtering is already enabled.
765 * @param RISAFx specifies the RISAF instance.
766 * This parameter is one of the RISAF instances defined in the CMSIS.
767 * @param Region specifies the RISAF region index
768 * This parameter can be one one of the following values:
769 * @arg @ref RISAF_REGION_1
770 * @arg @ref RISAF_REGION_2
771 * @arg @ref RISAF_REGION_3
772 * @arg @ref RISAF_REGION_4
773 * @arg @ref RISAF_REGION_5
774 * @arg @ref RISAF_REGION_6
775 * @arg @ref RISAF_REGION_7
776 * @arg @ref RISAF_REGION_8
777 * @arg @ref RISAF_REGION_9
778 * @arg @ref RISAF_REGION_10
779 * @arg @ref RISAF_REGION_11
780 * @arg @ref RISAF_REGION_12
781 * @arg @ref RISAF_REGION_13
782 * @arg @ref RISAF_REGION_14
783 * @arg @ref RISAF_REGION_15
784 * @param SubRegion specifies the RISAB Subregion index
785 * This parameter can be one of the following values:
786 * @arg @ref RISAF_SUBREGION_A
787 * @arg @ref RISAF_SUBREGION_B
788 * @param pConfig Pointer on RISAF Base Region configuration structure
789 * @retval None
790 */
HAL_RIF_RISAF_ConfigSubRegion(RISAF_TypeDef * RISAFx,uint32_t Region,uint32_t SubRegion,const RISAF_SubRegionConfig_t * pConfig)791 void HAL_RIF_RISAF_ConfigSubRegion(RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion,
792 const RISAF_SubRegionConfig_t *pConfig)
793 {
794 uint32_t cid;
795
796 /* Check the parameters */
797 assert_param(pConfig != (void *)NULL);
798 assert_param(IS_RISAF_INSTANCE(RISAFx));
799 assert_param(IS_RISAF_REGION(Region));
800 assert_param(IS_RISAF_MAX_REGION(RISAFx, Region));
801 assert_param(IS_RISAF_SUBREGION(SubRegion));
802 assert_param(IS_RISAF_FILTERING(pConfig->Filtering));
803 assert_param(IS_RIF_LOCK_STATE(pConfig->Lock));
804
805 /* Convert mask into bit position */
806 cid = POSITION_VAL(pConfig->CID);
807
808 if (SubRegion == RISAF_SUBREGION_A)
809 {
810 if (pConfig->Filtering == RISAF_FILTER_DISABLE)
811 {
812 RISAFx->REG[Region].ACFGR &= (~(RISAF_FILTER_ENABLE | RISAF_REGx_zCFGR_RLOCK));
813 RISAFx->REG[Region].ACFGR |= (pConfig->Lock << RISAF_REGx_zCFGR_RLOCK_Pos);
814 }
815 else
816 {
817 /* Check the parameters */
818 assert_param(IS_RISAF_READ_WRITE(pConfig->ReadWrite));
819 assert_param(IS_RIF_SEC_PRIV_ATTRIBUTE(pConfig->SecPriv));
820 assert_param(IS_RISAF_GRANULARITY(RISAFx, pConfig->StartAddress));
821 assert_param(IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(RISAFx, pConfig->StartAddress));
822 assert_param(IS_RISAF_GRANULARITY(RISAFx, (pConfig->EndAddress + 1U)));
823 assert_param(IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(RISAFx, pConfig->EndAddress));
824 assert_param(pConfig->StartAddress < pConfig->EndAddress);
825
826 RISAFx->REG[Region].ASTARTR = pConfig->StartAddress;
827 RISAFx->REG[Region].AENDR = pConfig->EndAddress;
828 RISAFx->REG[Region].ACFGR = (pConfig->Filtering | (pConfig->Lock << RISAF_REGx_zCFGR_RLOCK_Pos)
829 | (cid << RISAF_REGx_zCFGR_SRCID_Pos) | (pConfig->SecPriv << RISAF_REGx_zCFGR_SEC_Pos)
830 | (pConfig->ReadWrite));
831 }
832 }
833 else
834 {
835 if (pConfig->Filtering == RISAF_FILTER_DISABLE)
836 {
837 RISAFx->REG[Region].BCFGR &= (~(RISAF_FILTER_ENABLE | RISAF_REGx_zCFGR_RLOCK));
838 RISAFx->REG[Region].BCFGR |= (pConfig->Lock << RISAF_REGx_zCFGR_RLOCK_Pos);
839 }
840 else
841 {
842 /* Check the parameters */
843 assert_param(IS_RISAF_READ_WRITE(pConfig->ReadWrite));
844 assert_param(IS_RIF_SEC_PRIV_ATTRIBUTE(pConfig->SecPriv));
845 assert_param(IS_RISAF_GRANULARITY(RISAFx, pConfig->StartAddress));
846 assert_param(IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(RISAFx, pConfig->StartAddress));
847 assert_param(IS_RISAF_GRANULARITY(RISAFx, (pConfig->EndAddress + 1U)));
848 assert_param(IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(RISAFx, pConfig->EndAddress));
849 assert_param(pConfig->StartAddress < pConfig->EndAddress);
850
851 RISAFx->REG[Region].BSTARTR = pConfig->StartAddress;
852 RISAFx->REG[Region].BENDR = pConfig->EndAddress;
853 RISAFx->REG[Region].BCFGR = (pConfig->Filtering | (pConfig->Lock << RISAF_REGx_zCFGR_RLOCK_Pos)
854 | (cid << RISAF_REGx_zCFGR_SRCID_Pos) | (pConfig->SecPriv << RISAF_REGx_zCFGR_SEC_Pos)
855 | (pConfig->ReadWrite));
856 }
857 }
858 }
859
860 /**
861 * @brief Get the configuration of a RISAF Subregion.
862 * @param RISAFx specifies the RISAF instance.
863 * This parameter is one of the RISAF instances defined in the CMSIS.
864 * @param Region specifies the RISAF region index
865 * This parameter can be one one of the following values:
866 * @arg @ref RISAF_REGION_1
867 * @arg @ref RISAF_REGION_2
868 * @arg @ref RISAF_REGION_3
869 * @arg @ref RISAF_REGION_4
870 * @arg @ref RISAF_REGION_5
871 * @arg @ref RISAF_REGION_6
872 * @arg @ref RISAF_REGION_7
873 * @arg @ref RISAF_REGION_8
874 * @arg @ref RISAF_REGION_9
875 * @arg @ref RISAF_REGION_10
876 * @arg @ref RISAF_REGION_11
877 * @arg @ref RISAF_REGION_12
878 * @arg @ref RISAF_REGION_13
879 * @arg @ref RISAF_REGION_14
880 * @arg @ref RISAF_REGION_15
881 * @param SubRegion specifies the RISAB Subregion index
882 * This parameter can be one of the following values:
883 * @arg @ref RISAF_SUBREGION_A
884 * @arg @ref RISAF_SUBREGION_B
885 * @param pConfig Pointer on RISAF Base Region configuration structure
886 * @retval None
887 */
HAL_RIF_RISAF_GetConfigSubRegion(const RISAF_TypeDef * RISAFx,uint32_t Region,uint32_t SubRegion,RISAF_SubRegionConfig_t * pConfig)888 void HAL_RIF_RISAF_GetConfigSubRegion(const RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion,
889 RISAF_SubRegionConfig_t *pConfig)
890 {
891 uint32_t cid;
892 uint32_t cfgr_reg;
893
894 /* Check the parameters */
895 assert_param(pConfig != (void *)NULL);
896 assert_param(IS_RISAF_INSTANCE(RISAFx));
897 assert_param(IS_RISAF_REGION(Region));
898 assert_param(IS_RISAF_MAX_REGION(RISAFx, Region));
899 assert_param(IS_RISAF_SUBREGION(SubRegion));
900
901 if (SubRegion == RISAF_SUBREGION_A)
902 {
903 cfgr_reg = RISAFx->REG[Region].ACFGR;
904 pConfig->StartAddress = RISAFx->REG[Region].ASTARTR;
905 pConfig->EndAddress = RISAFx->REG[Region].AENDR;
906 }
907 else
908 {
909 cfgr_reg = RISAFx->REG[Region].BCFGR;
910 pConfig->StartAddress = RISAFx->REG[Region].BSTARTR;
911 pConfig->EndAddress = RISAFx->REG[Region].BENDR;
912 }
913
914 pConfig->Filtering = (cfgr_reg & RISAF_REGx_zCFGR_SREN);
915 cid = ((cfgr_reg & RISAF_REGx_zCFGR_SRCID) >> RISAF_REGx_zCFGR_SRCID_Pos);
916 pConfig->CID = (1UL << cid);
917 pConfig->SecPriv = ((cfgr_reg & (RISAF_REGx_zCFGR_PRIV | RISAF_REGx_zCFGR_SEC)) >> RISAF_REGx_zCFGR_SEC_Pos);
918 pConfig->ReadWrite = (cfgr_reg & (RISAF_REGx_zCFGR_WREN | RISAF_REGx_zCFGR_RDEN));
919 pConfig->Lock = ((cfgr_reg & RISAF_REGx_zCFGR_RLOCK) >> RISAF_REGx_zCFGR_RLOCK_Pos);
920 }
921
922 #if defined(CPU_AS_TRUSTED_DOMAIN)
923 /**
924 * @brief Get the error detected by the RISAF control block,
925 * the illegal access data and clear related flags.
926 * Error information can be illegal access or control access type. In case of an illegal access detection, the
927 * error information is:
928 * - responsible CID;
929 * - security access type;
930 * - privilege access type;
931 * - read (fetch) or write access type;
932 * - targeted address.
933 * @note This API is protected by the Trusted Domain compilation directive.
934 * @param RISAFx specifies the RISAF instance.
935 * This parameter is one of the RISAF instances defined in the CMSIS.
936 * @param IllegalAccess Pointer on illegal access structure
937 * @retval None
938 */
HAL_RIF_RISAF_GetIllegalAccess(RISAF_TypeDef * RISAFx,RISAF_IllegalAccess_t * IllegalAccess)939 void HAL_RIF_RISAF_GetIllegalAccess(RISAF_TypeDef *RISAFx, RISAF_IllegalAccess_t *IllegalAccess)
940 {
941 uint32_t cid;
942 uint32_t secpriv;
943
944 /* Check the parameters */
945 assert_param(IllegalAccess != (void *)NULL);
946 assert_param(IS_RISAF_INSTANCE(RISAFx));
947
948 /* Get illegal access type */
949 IllegalAccess->ErrorType = (RISAFx->IASR & (RISAF_IASR_IAEF | RISAF_IASR_CAEF));
950
951 if (IllegalAccess->ErrorType != RISAF_ILLEGAL_ACCESS_NONE)
952 {
953 /* Get illegal access data */
954 cid = (RISAFx->IAR->IAESR & RISAF_IAESR_IACID);
955 IllegalAccess->Data.CID = (1UL << cid);
956 secpriv = ((RISAFx->IAR->IAESR & (RISAF_IAESR_IASEC | RISAF_IAESR_IAPRIV)) >> RISAF_IAESR_IAPRIV_Pos);
957 IllegalAccess->Data.SecPriv = ((secpriv >> 1UL) | (secpriv << 1UL)) & 3UL;
958 IllegalAccess->Data.AccessType = ((RISAFx->IAR->IAESR & RISAF_IAESR_IANRW) >> RISAF_IAESR_IANRW_Pos);
959
960 if ((IllegalAccess->ErrorType & RISAF_ILLEGAL_ACCESS) != 0U)
961 {
962 IllegalAccess->Data.Address = RISAFx->IAR->IADDR;
963 }
964 else
965 {
966 IllegalAccess->Data.Address = 0U;
967 }
968
969 /* Clear flags */
970 RISAFx->IACR = (RISAF_IACR_IAEF | RISAF_IACR_CAEF);
971 }
972 }
973 #endif /* defined(CPU_AS_TRUSTED_DOMAIN) */
974 /**
975 * @}
976 */
977
978 /** @defgroup RIF_Exported_Functions_Group6 IAC Configuration functions
979 * @brief IAC Configuration functions
980 *
981 @verbatim
982 ==============================================================================
983 ##### IAC Configuration functions #####
984 ==============================================================================
985 [..]
986 This section provides functions allowing to configure IAC
987 IAC is Illegal Access Controller
988 @endverbatim
989 * @{
990 */
991 #if defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE)
992 /**
993 * @brief Enable interrupt generation on illegal access detection on peripheral or memory access.
994 * @note This API is protected by the Trusted Domain compilation directive.
995 * @note This API is protected by the TrustZone Enabled compilation directive.
996 * @param PeriphId specifies the index of the bus slave.
997 * This parameter can be one of @ref RIF_PERIPHERAL_INDEX
998 * @retval None
999 */
HAL_RIF_IAC_EnableIT(uint32_t PeriphId)1000 void HAL_RIF_IAC_EnableIT(uint32_t PeriphId)
1001 {
1002 __IO uint32_t *p_interrupt_reg;
1003
1004 /* Check parameters */
1005 assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_AWARE_PERIPH_INDEX(PeriphId));
1006
1007 p_interrupt_reg = &(IAC->IER[PeriphId >> RIF_PERIPH_REG_SHIFT]);
1008 *p_interrupt_reg |= (1UL << (PeriphId & RIF_PERIPH_BIT_POSITION));
1009
1010 }
1011
1012 /**
1013 * @brief Disable interrupt generation on illegal access detection on peripheral or memory access.
1014 * @note This API is protected by the Trusted Domain compilation directive.
1015 * @param PeriphId specifies the index of the bus slave.
1016 * This parameter can be one of @ref RIF_PERIPHERAL_INDEX
1017 * @retval None
1018 */
HAL_RIF_IAC_DisableIT(uint32_t PeriphId)1019 void HAL_RIF_IAC_DisableIT(uint32_t PeriphId)
1020 {
1021 __IO uint32_t *p_interrupt_reg;
1022
1023 /* Check parameters */
1024 assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_AWARE_PERIPH_INDEX(PeriphId));
1025
1026 p_interrupt_reg = &(IAC->IER[PeriphId >> RIF_PERIPH_REG_SHIFT]);
1027 *p_interrupt_reg &= (~(1UL << (PeriphId & RIF_PERIPH_BIT_POSITION)));
1028 }
1029
1030 /**
1031 * @brief Get illegal access detection flag.
1032 * @note This API is protected by the Trusted Domain compilation directive.
1033 * @param PeriphId specifies the index of the bus slave.
1034 * This parameter can be one of @ref RIF_PERIPHERAL_INDEX
1035 * @retval Detection flag value
1036 */
HAL_RIF_IAC_GetFlag(uint32_t PeriphId)1037 uint32_t HAL_RIF_IAC_GetFlag(uint32_t PeriphId)
1038 {
1039 uint32_t interrupt_flag;
1040 const __IO uint32_t *p_interrupt_reg;
1041 uint32_t shift_var;
1042
1043 /* Check parameters */
1044 assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_AWARE_PERIPH_INDEX(PeriphId));
1045
1046 shift_var = (PeriphId & RIF_PERIPH_BIT_POSITION);
1047 p_interrupt_reg = &(IAC->ISR[PeriphId >> RIF_PERIPH_REG_SHIFT]);
1048 interrupt_flag = ((*p_interrupt_reg & (1UL << shift_var)) >> shift_var);
1049
1050 return interrupt_flag;
1051 }
1052
1053 /**
1054 * @brief Clear illegal access detection flag.
1055 * @note This API is protected by the Trusted Domain compilation directive.
1056 * @param PeriphId specifies the index of the bus slave.
1057 * This parameter can be one of @ref RIF_PERIPHERAL_INDEX
1058 * @retval None
1059 */
HAL_RIF_IAC_ClearFlag(uint32_t PeriphId)1060 void HAL_RIF_IAC_ClearFlag(uint32_t PeriphId)
1061 {
1062 __IO uint32_t *p_interrupt_reg;
1063
1064 /* Check parameters */
1065 assert_param(IS_RIF_RISC_PERIPH_INDEX(PeriphId) || IS_RIF_AWARE_PERIPH_INDEX(PeriphId));
1066
1067 p_interrupt_reg = &(IAC->ICR[PeriphId >> RIF_PERIPH_REG_SHIFT]);
1068 *p_interrupt_reg = (1UL << (PeriphId & RIF_PERIPH_BIT_POSITION));
1069 }
1070
1071 /**
1072 * @brief Parse all pending flags and call callback when necessary.
1073 * @note This API is protected by the Trusted Domain compilation directive.
1074 * @retval None
1075 */
HAL_RIF_IRQHandler(void)1076 void HAL_RIF_IRQHandler(void)
1077 {
1078 uint32_t reg_index;
1079 uint32_t flag_mask;
1080 uint32_t position;
1081 uint32_t periph_id;
1082
1083 for (reg_index = 0 ; reg_index < (RIF_PERIPH_IAC_REG_MAX + 1U) ; reg_index++)
1084 {
1085 flag_mask = IAC->ISR[reg_index];
1086
1087 position = 0U;
1088 while ((flag_mask >> position) != 0U)
1089 {
1090 if ((flag_mask & (1UL << position)) != 0U)
1091 {
1092 periph_id = ((reg_index << RIF_PERIPH_REG_SHIFT) | position);
1093 HAL_RIF_IAC_ClearFlag(periph_id);
1094 HAL_RIF_ILA_Callback(periph_id);
1095 }
1096 position++;
1097 }
1098 }
1099 }
1100
1101 /**
1102 * @brief RIF illegal access callback.
1103 * @note This API is protected by the Trusted Domain compilation directive.
1104 * @note This API is protected by the TrustZone Enabled compilation directive.
1105 * @param PeriphId specifies the index of the bus slave.
1106 * This parameter can be one of @ref RIF_PERIPHERAL_INDEX
1107 * @retval None
1108 */
HAL_RIF_ILA_Callback(uint32_t PeriphId)1109 __weak void HAL_RIF_ILA_Callback(uint32_t PeriphId)
1110 {
1111 /* Prevent unused argument(s) compilation warning */
1112 UNUSED(PeriphId);
1113
1114 /* NOTE: This function should not be modified, when the callback is needed,
1115 the HAL_RIF_ILA_Callback could be implemented in the user file
1116 */
1117 }
1118 #endif /* CPU_AS_TRUSTED_DOMAIN && CPU_IN_SECURE_STATE */
1119 /**
1120 * @}
1121 */
1122
1123 /**
1124 * @}
1125 */
1126
1127 #endif /* HAL_RIF_MODULE_ENABLED */
1128
1129 /**
1130 * @}
1131 */
1132
1133 /**
1134 * @}
1135 */
1136
