1 /**
2 ******************************************************************************
3 * @file stm32n6xx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extension peripheral:
8 * + Extended Peripheral Control functions
9 *
10 ******************************************************************************
11 * @attention
12 *
13 * Copyright (c) 2023 STMicroelectronics.
14 * All rights reserved.
15 *
16 * This software is licensed under terms that can be found in the LICENSE file in
17 * the root directory of this software component.
18 * If no LICENSE file comes with this software, it is provided AS-IS.
19 *
20 ******************************************************************************
21 */
22
23 /* Includes ------------------------------------------------------------------*/
24 #include "stm32n6xx_hal.h"
25
26 /** @addtogroup STM32N6xx_HAL_Driver
27 * @{
28 */
29
30 /** @defgroup RCCEx RCCEx
31 * @brief RCC HAL module driver
32 * @{
33 */
34
35 #ifdef HAL_RCC_MODULE_ENABLED
36
37 /* Private typedef -----------------------------------------------------------*/
38 /* Private defines -----------------------------------------------------------*/
39 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
40 * @{
41 */
42 #if defined(USE_FPGA)
43 /* ***** FPGA values ******/
44 #define RCC_PLL_SOURCE_FREQ 32000000UL /* PLL source forced to 32MHz */
45 #endif /* USE_FPGA */
46 /**
47 * @}
48 */
49
50 /* Private macros ------------------------------------------------------------*/
51 /* Private variables ---------------------------------------------------------*/
52 /* Private function prototypes -----------------------------------------------*/
53 /** @defgroup RCCEx_Private_Functions_Prototypes RCCEx Private Functions Prototypes
54 * @{
55 */
56 static uint32_t RCCEx_GetHCLKFreq(uint32_t SYSCLK_Frequency);
57 static uint32_t RCCEx_GetPCLK1Freq(uint32_t HCLK_Frequency);
58 static uint32_t RCCEx_GetPCLK2Freq(uint32_t PCLK_Frequency);
59 static uint32_t RCCEx_GetPCLK4Freq(uint32_t PCLK_Frequency);
60 static uint32_t RCCEx_GetPCLK5Freq(uint32_t PCLK_Frequency);
61 static uint32_t RCCEx_GetPLLSourceFreq(uint32_t PLLsource);
62 static uint32_t RCCEx_CalcPLLFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N,
63 uint32_t FRACN, uint32_t P1, uint32_t P2);
64 static uint32_t RCCEx_GetADCCLKFreq(uint32_t ADCxSource);
65 static uint32_t RCCEx_GetADFCLKFreq(uint32_t ADFxSource);
66 static uint32_t RCCEx_GetCLKPCLKFreq(uint32_t CLKPxSource);
67 static uint32_t RCCEx_GetCSICLKFreq(void);
68 static uint32_t RCCEx_GetDCMIPPCLKFreq(uint32_t DCMIPPxSource);
69 static uint32_t RCCEx_GetETH1CLKFreq(uint32_t ETH1xSource);
70 static uint32_t RCCEx_GetETH1PTPCLKFreq(uint32_t ETH1PTPxSource);
71 static uint32_t RCCEx_GetFDCANCLKFreq(uint32_t FDCANxSource);
72 static uint32_t RCCEx_GetFMCCLKFreq(uint32_t FMCxSource);
73 static uint32_t RCCEx_GetI2CCLKFreq(uint32_t I2CxSource);
74 static uint32_t RCCEx_GetI3CCLKFreq(uint32_t I3CxSource);
75 static uint32_t RCCEx_GetLPTIMCLKFreq(uint32_t LPTIMxSource);
76 static uint32_t RCCEx_GetLPUARTCLKFreq(uint32_t LPUARTxSource);
77 static uint32_t RCCEx_GetLTDCCLKFreq(uint32_t LPTIMxSource);
78 static uint32_t RCCEx_GetMDFCLKFreq(uint32_t MDFxSource);
79 static uint32_t RCCEx_GetPSSICLKFreq(uint32_t PSSIxSource);
80 static uint32_t RCCEx_GetRTCCLKFreq(void);
81 static uint32_t RCCEx_GetSAICLKFreq(uint32_t SAIxSource);
82 static uint32_t RCCEx_GetSDMMCCLKFreq(uint32_t SDMMCxSource);
83 static uint32_t RCCEx_GetSPDIFRXCLKFreq(uint32_t SPDIFRXxSource);
84 static uint32_t RCCEx_GetSPICLKFreq(uint32_t SPIxSource);
85 static uint32_t RCCEx_GetUARTCLKFreq(uint32_t UARTxSource);
86 static uint32_t RCCEx_GetUSARTCLKFreq(uint32_t USARTxSource);
87 static uint32_t RCCEx_GetOTGPHYCLKFreq(uint32_t OTGPHYxSource);
88 static uint32_t RCCEx_GetOTGPHYCKREFCLKFreq(uint32_t OTGPHYxCKREFSource);
89 static uint32_t RCCEx_GetXSPICLKFreq(uint32_t XSPIxSource);
90 /**
91 * @}
92 */
93
94 /* Exported functions --------------------------------------------------------*/
95 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
96 * @{
97 */
98
99 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
100 * @brief Extended Peripheral Control functions
101 *
102 @verbatim
103 ===============================================================================
104 ##### Extended Peripheral Control functions #####
105 ===============================================================================
106 [..]
107 This subsection provides a set of functions allowing to control the RCC Clocks
108 frequencies.
109 [..]
110 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
111 select the RTC clock source; in this case the Backup domain will be reset in
112 order to modify the RTC Clock source, as consequence RTC registers (including
113 the backup registers) and RCC_BDCR register are set to their reset values.
114
115 @endverbatim
116 * @{
117 */
118 /**
119 * @brief Initializes the RCC extended peripherals clocks according to the specified
120 * parameters in the RCC_PeriphCLKInitTypeDef.
121 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
122 * contains the configuration information for the Extended Peripherals clocks
123 * (ADC, ADF1, CKPER, DCMI, DCMIPP, FDCAN, FMC, I2C1, I2C2, I2C3, I2C4, I3C1, I3C2,
124 * LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LTDC, LPUART1, MDF1, PSSI, RTC, SAI1, SAI2,
125 * SDMMC1, SDMMC2, SPDIFRX1, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, TIM,
126 * USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8, UART9, USART10,
127 * USBPHY1, USBPHY2, USB OTGHS1, USB OTGHS2, XSPI1, XSPI2, XSPI3).
128 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
129 * the RTC clock source; in this case the Backup domain will be reset in
130 * order to modify the RTC Clock source, as consequence RTC registers (including
131 * the backup registers) are set to their reset values.
132 * @note Dynamic switches are used for peripheral input clock selection meaning the switch setting
133 * can only be changed if both input clocks are present during transition time.
134 * @note Care must be taken when RCC_PPPCLKSOURCE_ICx is selected. The ICx ClockSelection and ClockDivider fields
135 * modification indeed impacts all peripherals using this ICx as clock source.
136 *
137 * @retval HAL status
138 */
HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef * PeriphClkInit)139 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit)
140 {
141 uint32_t tmpreg;
142 uint32_t tickstart;
143 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
144 HAL_StatusTypeDef status = HAL_OK; /* Final status */
145
146 /* Check the parameters */
147 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
148
149 /*---------------------------- RTC configuration -------------------------------*/
150 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
151 {
152 /* check for RTC Parameters used to output RTCCLK */
153 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
154
155 /* As the RTC clock source selection can be changed only if the Backup Domain is reset */
156 /* reset the Backup domain only if the RTC Clock source selection is modified from default reset value */
157 tmpreg = LL_RCC_GetRTCClockSource();
158
159 if ((tmpreg != RCC_RTCCLKSOURCE_DISABLE) && (tmpreg != (PeriphClkInit->RTCClockSelection & RCC_CCIPR7_RTCSEL)))
160 {
161 /* Enable write access to Backup domain */
162 SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
163
164 /* Read back to check Backup domain enabled */
165 if (READ_BIT(PWR->DBPCR, PWR_DBPCR_DBP) == 0U)
166 {
167 ret = HAL_ERROR;
168 }
169 else
170 {
171 #if 0 /* TO DO */
172 /* Store the content of BDCR register before the reset of Backup Domain */
173 /* excepted the RTC clock source selection that will be changed */
174 tmpreg = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
175 __HAL_RCC_BACKUPRESET_FORCE();
176 __HAL_RCC_BACKUPRESET_RELEASE();
177 /* Restore the content of BDCR register */
178 WRITE_REG(RCC->BDCR, tmpreg);
179 #endif /* #if 0 TO DO */
180 }
181 }
182
183 if (ret == HAL_OK)
184 {
185 /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
186 if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
187 {
188 /* Get Start Tick*/
189 tickstart = HAL_GetTick();
190
191 /* Wait till LSE is ready */
192 while (LL_RCC_LSE_IsReady() == 0U)
193 {
194 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
195 {
196 ret = HAL_TIMEOUT;
197 break;
198 }
199 }
200 }
201
202 if (ret == HAL_OK)
203 {
204 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
205 }
206 else
207 {
208 /* set overall return value */
209 status = ret;
210 }
211 }
212 else
213 {
214 /* set overall return value */
215 status = ret;
216 }
217 }
218
219 /*------------------------------------ CKPER configuration --------------------------------------*/
220 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
221 {
222 /* Check the parameters */
223 assert_param(IS_RCC_CKPERCLKSOURCE(PeriphClkInit->CkperClockSelection));
224
225 if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC5)
226 {
227 /* Check the parameters */
228 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC5].ClockSelection));
229 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC5].ClockDivider));
230
231 /* Set IC5 configuration */
232 MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL | RCC_IC5CFGR_IC5INT,
233 PeriphClkInit->ICSelection[RCC_IC5].ClockSelection | \
234 ((PeriphClkInit->ICSelection[RCC_IC5].ClockDivider - 1U) << RCC_IC5CFGR_IC5INT_Pos));
235
236 LL_RCC_IC5_Enable();
237 }
238 else if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC10)
239 {
240 /* Check the parameters */
241 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection));
242 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider));
243
244 /* Set IC10 configuration */
245 MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT,
246 PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \
247 ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos));
248
249 LL_RCC_IC10_Enable();
250 }
251 else if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC15)
252 {
253 /* Check the parameters */
254 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
255 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
256
257 /* Set IC15 configuration */
258 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
259 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
260 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
261
262 LL_RCC_IC15_Enable();
263 }
264 else if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC19)
265 {
266 /* Check the parameters */
267 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC19].ClockSelection));
268 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC19].ClockDivider));
269
270 /* Set IC19 configuration */
271 MODIFY_REG(RCC->IC19CFGR, RCC_IC19CFGR_IC19SEL | RCC_IC19CFGR_IC19INT,
272 PeriphClkInit->ICSelection[RCC_IC19].ClockSelection | \
273 ((PeriphClkInit->ICSelection[RCC_IC19].ClockDivider - 1U) << RCC_IC19CFGR_IC19INT_Pos));
274
275 LL_RCC_IC19_Enable();
276 }
277 else if (PeriphClkInit->CkperClockSelection == RCC_CLKPCLKSOURCE_IC20)
278 {
279 /* Check the parameters */
280 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC20].ClockSelection));
281 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC20].ClockDivider));
282
283 /* Set IC20 configuration */
284 MODIFY_REG(RCC->IC20CFGR, RCC_IC20CFGR_IC20SEL | RCC_IC20CFGR_IC20INT,
285 PeriphClkInit->ICSelection[RCC_IC20].ClockSelection | \
286 ((PeriphClkInit->ICSelection[RCC_IC20].ClockDivider - 1U) << RCC_IC20CFGR_IC20INT_Pos));
287
288 LL_RCC_IC20_Enable();
289 }
290 else
291 {
292 /* No ICx selected as source */
293 }
294
295 /* Configure the CKPER clock source */
296 __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
297 }
298
299 /*-------------------------- XSPI1 clock source configuration ----------------*/
300 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI1) == RCC_PERIPHCLK_XSPI1)
301 {
302 /* Check the parameters */
303 assert_param(IS_RCC_XSPI1CLKSOURCE(PeriphClkInit->Xspi1ClockSelection));
304
305 if (PeriphClkInit->Xspi1ClockSelection == RCC_XSPI1CLKSOURCE_IC3)
306 {
307 /* Check the parameters */
308 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC3].ClockSelection));
309 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC3].ClockDivider));
310
311 /* Set IC3 configuration */
312 MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL | RCC_IC3CFGR_IC3INT,
313 PeriphClkInit->ICSelection[RCC_IC3].ClockSelection | \
314 ((PeriphClkInit->ICSelection[RCC_IC3].ClockDivider - 1U) << RCC_IC3CFGR_IC3INT_Pos));
315
316 LL_RCC_IC3_Enable();
317 }
318 else if (PeriphClkInit->Xspi1ClockSelection == RCC_XSPI1CLKSOURCE_IC4)
319 {
320 /* Check the parameters */
321 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection));
322 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider));
323
324 /* Set IC4 configuration */
325 MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT,
326 PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \
327 ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos));
328
329 LL_RCC_IC4_Enable();
330 }
331 else if (PeriphClkInit->Xspi1ClockSelection == RCC_XSPI1CLKSOURCE_CLKP)
332 {
333 LL_RCC_CLKP_Enable();
334 }
335 else
336 {
337 /* No specific enable to do on other sources */
338 }
339
340 /* Configure the XSPI1 clock source */
341 __HAL_RCC_XSPI1_CONFIG(PeriphClkInit->Xspi1ClockSelection);
342 }
343
344 /*-------------------------- XSPI2 clock source configuration ----------------*/
345 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI2) == RCC_PERIPHCLK_XSPI2)
346 {
347 /* Check the parameters */
348 assert_param(IS_RCC_XSPI2CLKSOURCE(PeriphClkInit->Xspi2ClockSelection));
349
350 if (PeriphClkInit->Xspi2ClockSelection == RCC_XSPI2CLKSOURCE_IC3)
351 {
352 /* Check the parameters */
353 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC3].ClockSelection));
354 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC3].ClockDivider));
355
356 /* Set IC3 configuration */
357 MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL | RCC_IC3CFGR_IC3INT,
358 PeriphClkInit->ICSelection[RCC_IC3].ClockSelection | \
359 ((PeriphClkInit->ICSelection[RCC_IC3].ClockDivider - 1U) << RCC_IC3CFGR_IC3INT_Pos));
360
361 LL_RCC_IC3_Enable();
362 }
363 else if (PeriphClkInit->Xspi2ClockSelection == RCC_XSPI2CLKSOURCE_IC4)
364 {
365 /* Check the parameters */
366 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection));
367 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider));
368
369 /* Set IC4 configuration */
370 MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT,
371 PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \
372 ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos));
373
374 LL_RCC_IC4_Enable();
375 }
376 else if (PeriphClkInit->Xspi2ClockSelection == RCC_XSPI2CLKSOURCE_CLKP)
377 {
378 LL_RCC_CLKP_Enable();
379 }
380 else
381 {
382 /* No specific enable to do on other sources */
383 }
384
385 /* Configure the XSPI2 clock source */
386 __HAL_RCC_XSPI2_CONFIG(PeriphClkInit->Xspi2ClockSelection);
387 }
388
389 /*-------------------------- XSPI3 clock source configuration ----------------*/
390 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_XSPI3) == RCC_PERIPHCLK_XSPI3)
391 {
392 /* Check the parameters */
393 assert_param(IS_RCC_XSPI3CLKSOURCE(PeriphClkInit->Xspi3ClockSelection));
394
395 if (PeriphClkInit->Xspi3ClockSelection == RCC_XSPI3CLKSOURCE_IC3)
396 {
397 /* Check the parameters */
398 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC3].ClockSelection));
399 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC3].ClockDivider));
400
401 /* Set IC3 configuration */
402 MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL | RCC_IC3CFGR_IC3INT,
403 PeriphClkInit->ICSelection[RCC_IC3].ClockSelection | \
404 ((PeriphClkInit->ICSelection[RCC_IC3].ClockDivider - 1U) << RCC_IC3CFGR_IC3INT_Pos));
405
406 LL_RCC_IC3_Enable();
407 }
408 else if (PeriphClkInit->Xspi3ClockSelection == RCC_XSPI3CLKSOURCE_IC4)
409 {
410 /* Check the parameters */
411 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection));
412 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider));
413
414 /* Set IC4 configuration */
415 MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT,
416 PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \
417 ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos));
418
419 LL_RCC_IC4_Enable();
420 }
421 else if (PeriphClkInit->Xspi3ClockSelection == RCC_XSPI3CLKSOURCE_CLKP)
422 {
423 LL_RCC_CLKP_Enable();
424 }
425 else
426 {
427 /* No specific enable to do on other sources */
428 }
429
430 /* Configure the XSPI3 clock source */
431 __HAL_RCC_XSPI3_CONFIG(PeriphClkInit->Xspi3ClockSelection);
432 }
433
434 /*---------------------------- FMC configuration -------------------------------*/
435 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
436 {
437 /* Check the parameters */
438 assert_param(IS_RCC_FMCCLKSOURCE(PeriphClkInit->FmcClockSelection));
439
440 if (PeriphClkInit->FmcClockSelection == RCC_FMCCLKSOURCE_IC3)
441 {
442 /* Check the parameters */
443 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC3].ClockSelection));
444 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC3].ClockDivider));
445
446 /* Set IC3 configuration */
447 MODIFY_REG(RCC->IC3CFGR, RCC_IC3CFGR_IC3SEL | RCC_IC3CFGR_IC3INT,
448 PeriphClkInit->ICSelection[RCC_IC3].ClockSelection | \
449 ((PeriphClkInit->ICSelection[RCC_IC3].ClockDivider - 1U) << RCC_IC3CFGR_IC3INT_Pos));
450
451 LL_RCC_IC3_Enable();
452 }
453 else if (PeriphClkInit->FmcClockSelection == RCC_FMCCLKSOURCE_IC4)
454 {
455 /* Check the parameters */
456 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection));
457 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider));
458
459 /* Set IC4 configuration */
460 MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT,
461 PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \
462 ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos));
463
464 LL_RCC_IC4_Enable();
465 }
466 else if (PeriphClkInit->FmcClockSelection == RCC_FMCCLKSOURCE_CLKP)
467 {
468 LL_RCC_CLKP_Enable();
469 }
470 else
471 {
472 /* No specific enable to do on other sources */
473 }
474
475 /* Set the source of FMC kernel clock*/
476 __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
477 }
478
479 /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
480 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
481 {
482 /* Check the parameters */
483 assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
484
485 if (PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_IC4)
486 {
487 /* Check the parameters */
488 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection));
489 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider));
490
491 /* Set IC4 configuration */
492 MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT,
493 PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \
494 ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos));
495
496 LL_RCC_IC4_Enable();
497 }
498 else if (PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_IC5)
499 {
500 /* Check the parameters */
501 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC5].ClockSelection));
502 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC5].ClockDivider));
503
504 /* Set IC5 configuration */
505 MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL | RCC_IC5CFGR_IC5INT,
506 PeriphClkInit->ICSelection[RCC_IC5].ClockSelection | \
507 ((PeriphClkInit->ICSelection[RCC_IC5].ClockDivider - 1U) << RCC_IC5CFGR_IC5INT_Pos));
508
509 LL_RCC_IC5_Enable();
510 }
511 else if (PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_CLKP)
512 {
513 LL_RCC_CLKP_Enable();
514 }
515 else
516 {
517 /* No specific enable to do on other sources */
518 }
519
520 /* Set the source of SDMMC1 clock*/
521 __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
522 }
523
524 /*------------------------------------- SDMMC2 Configuration ------------------------------------*/
525 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
526 {
527 /* Check the parameters */
528 assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
529
530 if (PeriphClkInit->Sdmmc2ClockSelection == RCC_SDMMC2CLKSOURCE_IC4)
531 {
532 /* Check the parameters */
533 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC4].ClockSelection));
534 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC4].ClockDivider));
535
536 /* Set IC4 configuration */
537 MODIFY_REG(RCC->IC4CFGR, RCC_IC4CFGR_IC4SEL | RCC_IC4CFGR_IC4INT,
538 PeriphClkInit->ICSelection[RCC_IC4].ClockSelection | \
539 ((PeriphClkInit->ICSelection[RCC_IC4].ClockDivider - 1U) << RCC_IC4CFGR_IC4INT_Pos));
540
541 LL_RCC_IC4_Enable();
542 }
543 else if (PeriphClkInit->Sdmmc2ClockSelection == RCC_SDMMC2CLKSOURCE_IC5)
544 {
545 /* Check the parameters */
546 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC5].ClockSelection));
547 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC5].ClockDivider));
548
549 /* Set IC5 configuration */
550 MODIFY_REG(RCC->IC5CFGR, RCC_IC5CFGR_IC5SEL | RCC_IC5CFGR_IC5INT,
551 PeriphClkInit->ICSelection[RCC_IC5].ClockSelection | \
552 ((PeriphClkInit->ICSelection[RCC_IC5].ClockDivider - 1U) << RCC_IC5CFGR_IC5INT_Pos));
553
554 LL_RCC_IC5_Enable();
555 }
556 else if (PeriphClkInit->Sdmmc2ClockSelection == RCC_SDMMC2CLKSOURCE_CLKP)
557 {
558 LL_RCC_CLKP_Enable();
559 }
560 else
561 {
562 /* No specific enable to do on other sources */
563 }
564
565 /* Set the source of SDMMC2 clock*/
566 __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
567 }
568
569 /*---------------------------- ADC configuration -------------------------------*/
570 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
571 {
572 /* Check the parameters */
573 assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
574 assert_param(IS_RCC_ADCDIVIDER(PeriphClkInit->AdcDivider));
575
576 if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_IC7)
577 {
578 /* Check the parameters */
579 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection));
580 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider));
581
582 /* Set IC7 configuration */
583 MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT,
584 PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \
585 ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos));
586
587 LL_RCC_IC7_Enable();
588 }
589 else if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_IC8)
590 {
591 /* Check the parameters */
592 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
593 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
594
595 /* Set IC8 configuration */
596 MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
597 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
598 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
599
600 LL_RCC_IC8_Enable();
601 }
602 else if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_CLKP)
603 {
604 LL_RCC_CLKP_Enable();
605 }
606 else
607 {
608 /* No specific enable to do on other sources */
609 }
610
611 /* Configure the ADC clock source and divider */
612 MODIFY_REG(RCC->CCIPR1, (RCC_CCIPR1_ADCPRE | RCC_CCIPR1_ADC12SEL), \
613 (((PeriphClkInit->AdcDivider - 1U) << RCC_CCIPR1_ADCPRE_Pos) | (PeriphClkInit->AdcClockSelection)));
614 }
615
616 /*---------------------------- ADF1 configuration --------------------------*/
617 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1)
618 {
619 /* Check the parameters */
620 assert_param(IS_RCC_ADF1CLKSOURCE(PeriphClkInit->Adf1ClockSelection));
621
622 if (PeriphClkInit->Adf1ClockSelection == RCC_ADF1CLKSOURCE_IC7)
623 {
624 /* Check the parameters */
625 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection));
626 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider));
627
628 /* Set IC7 configuration */
629 MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT,
630 PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \
631 ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos));
632
633 LL_RCC_IC7_Enable();
634 }
635 else if (PeriphClkInit->Adf1ClockSelection == RCC_ADF1CLKSOURCE_IC8)
636 {
637 /* Check the parameters */
638 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
639 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
640
641 /* Set IC8 configuration */
642 MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
643 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
644 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
645
646 LL_RCC_IC8_Enable();
647 }
648 else if (PeriphClkInit->Adf1ClockSelection == RCC_ADF1CLKSOURCE_CLKP)
649 {
650 LL_RCC_CLKP_Enable();
651 }
652 else
653 {
654 /* No specific enable to do on other sources */
655 }
656
657 /* Set the source of ADF1 clock*/
658 __HAL_RCC_ADF1_CONFIG(PeriphClkInit->Adf1ClockSelection);
659 }
660
661 /*------------------------------------ CSI configuration --------------------------------------*/
662 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_CSI) == RCC_PERIPHCLK_CSI)
663 {
664 /* Check the parameters */
665 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC18].ClockSelection));
666 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC18].ClockDivider));
667
668 /* Set IC18 configuration */
669 MODIFY_REG(RCC->IC18CFGR, RCC_IC18CFGR_IC18SEL | RCC_IC18CFGR_IC18INT,
670 PeriphClkInit->ICSelection[RCC_IC18].ClockSelection | \
671 ((PeriphClkInit->ICSelection[RCC_IC18].ClockDivider - 1U) << RCC_IC18CFGR_IC18INT_Pos));
672
673 LL_RCC_IC18_Enable();
674 }
675
676 /*---------------------- DCMIPP configuration ------------------------------*/
677 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_DCMIPP) == RCC_PERIPHCLK_DCMIPP)
678 {
679 /* Check the parameters */
680 assert_param(IS_RCC_DCMIPPCLKSOURCE(PeriphClkInit->DcmippClockSelection));
681
682 if (PeriphClkInit->DcmippClockSelection == RCC_DCMIPPCLKSOURCE_IC17)
683 {
684 /* Check the parameters */
685 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC17].ClockSelection));
686 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC17].ClockDivider));
687
688 /* Set IC17 configuration */
689 MODIFY_REG(RCC->IC17CFGR, RCC_IC17CFGR_IC17SEL | RCC_IC17CFGR_IC17INT,
690 PeriphClkInit->ICSelection[RCC_IC17].ClockSelection | \
691 ((PeriphClkInit->ICSelection[RCC_IC17].ClockDivider - 1U) << RCC_IC17CFGR_IC17INT_Pos));
692
693 LL_RCC_IC17_Enable();
694 }
695 else if (PeriphClkInit->DcmippClockSelection == RCC_DCMIPPCLKSOURCE_CLKP)
696 {
697 LL_RCC_CLKP_Enable();
698 }
699 else
700 {
701 /* No specific enable to do on other sources */
702 }
703
704 /* Configure the CEC clock source */
705 __HAL_RCC_DCMIPP_CONFIG(PeriphClkInit->DcmippClockSelection);
706 }
707
708 /*---------------------- ETH1 configuration --------------------------------*/
709 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1) == RCC_PERIPHCLK_ETH1)
710 {
711 /* Check the parameters */
712 assert_param(IS_RCC_ETH1CLKSOURCE(PeriphClkInit->Eth1ClockSelection));
713
714 if (PeriphClkInit->Eth1ClockSelection == RCC_ETH1CLKSOURCE_IC12)
715 {
716 /* Check the parameters */
717 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC12].ClockSelection));
718 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC12].ClockDivider));
719
720 /* Set IC12 configuration */
721 MODIFY_REG(RCC->IC12CFGR, RCC_IC12CFGR_IC12SEL | RCC_IC12CFGR_IC12INT,
722 PeriphClkInit->ICSelection[RCC_IC12].ClockSelection | \
723 ((PeriphClkInit->ICSelection[RCC_IC12].ClockDivider - 1U) << RCC_IC12CFGR_IC12INT_Pos));
724
725 LL_RCC_IC12_Enable();
726 }
727 else if (PeriphClkInit->Eth1ClockSelection == RCC_ETH1CLKSOURCE_CLKP)
728 {
729 LL_RCC_CLKP_Enable();
730 }
731 else
732 {
733 /* No specific enable to do on other sources */
734 }
735
736 /* Configure the ETH1 clock source */
737 __HAL_RCC_ETH1_CONFIG(PeriphClkInit->Eth1ClockSelection);
738 }
739
740 /*---------------------- ETH1PHY configuration -----------------------------*/
741 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1PHY) == RCC_PERIPHCLK_ETH1PHY)
742 {
743 /* Check the parameters */
744 assert_param(IS_RCC_ETH1PHYIF(PeriphClkInit->Eth1PhyInterfaceSelection));
745
746 /* Configure the source of ETH1 PHY interface */
747 __HAL_RCC_ETH1PHY_CONFIG(PeriphClkInit->Eth1PhyInterfaceSelection);
748 }
749
750 /*---------------------- ETH1 RX configuration -----------------------------*/
751 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1RX) == RCC_PERIPHCLK_ETH1RX)
752 {
753 /* Check the parameters */
754 assert_param(IS_RCC_ETH1RXCLKSOURCE(PeriphClkInit->Eth1RxClockSelection));
755
756 /* Configure the ETH1 RX clock source */
757 __HAL_RCC_ETH1RX_CONFIG(PeriphClkInit->Eth1RxClockSelection);
758 }
759
760 /*---------------------- ETH1 TX configuration -----------------------------*/
761 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1TX) == RCC_PERIPHCLK_ETH1TX)
762 {
763 /* Check the parameters */
764 assert_param(IS_RCC_ETH1TXCLKSOURCE(PeriphClkInit->Eth1TxClockSelection));
765
766 /* Configure the ETH1 TX clock source */
767 __HAL_RCC_ETH1TX_CONFIG(PeriphClkInit->Eth1TxClockSelection);
768 }
769
770 /*---------------------- ETH1 PTP configuration ----------------------------*/
771 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_ETH1PTP) == RCC_PERIPHCLK_ETH1PTP)
772 {
773 /* Check the parameters */
774 assert_param(IS_RCC_ETH1PTPCLKSOURCE(PeriphClkInit->Eth1PtpClockSelection));
775 assert_param(IS_RCC_ETH1PTPDIVIDER(PeriphClkInit->Eth1PtpDivider));
776
777 if (PeriphClkInit->Eth1PtpClockSelection == RCC_ETH1PTPCLKSOURCE_IC13)
778 {
779 /* Check the parameters */
780 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC13].ClockSelection));
781 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC13].ClockDivider));
782
783 /* Set IC13 configuration */
784 MODIFY_REG(RCC->IC13CFGR, RCC_IC13CFGR_IC13SEL | RCC_IC13CFGR_IC13INT,
785 PeriphClkInit->ICSelection[RCC_IC13].ClockSelection | \
786 ((PeriphClkInit->ICSelection[RCC_IC13].ClockDivider - 1U) << RCC_IC13CFGR_IC13INT_Pos));
787
788 LL_RCC_IC13_Enable();
789 }
790 else if (PeriphClkInit->Eth1PtpClockSelection == RCC_ETH1PTPCLKSOURCE_CLKP)
791 {
792 LL_RCC_CLKP_Enable();
793 }
794 else
795 {
796 /* No specific enable to do on other sources */
797 }
798
799 /* Configure the ETH1 PTP clock source and divider */
800 MODIFY_REG(RCC->CCIPR2, (RCC_CCIPR2_ETH1PTPDIV | RCC_CCIPR2_ETH1PTPSEL), \
801 (((PeriphClkInit->Eth1PtpDivider - 1U) << RCC_CCIPR2_ETH1PTPDIV_Pos) | PeriphClkInit->Eth1PtpClockSelection));
802 }
803
804 /*---------------------- FDCAN configuration -------------------------------*/
805 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
806 {
807 /* Check the parameters */
808 assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
809
810 if (PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_IC19)
811 {
812 /* Check the parameters */
813 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC19].ClockSelection));
814 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC19].ClockDivider));
815
816 /* Set IC19 configuration */
817 MODIFY_REG(RCC->IC19CFGR, RCC_IC19CFGR_IC19SEL | RCC_IC19CFGR_IC19INT,
818 PeriphClkInit->ICSelection[RCC_IC19].ClockSelection | \
819 ((PeriphClkInit->ICSelection[RCC_IC19].ClockDivider - 1U) << RCC_IC19CFGR_IC19INT_Pos));
820
821 LL_RCC_IC19_Enable();
822 }
823 else if (PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_CLKP)
824 {
825 LL_RCC_CLKP_Enable();
826 }
827 else
828 {
829 /* No specific enable to do on other sources */
830 }
831
832 /* Set the source of FDCAN clock*/
833 __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
834 }
835
836 /*------------------------------ I2C1 Configuration ------------------------*/
837 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
838 {
839 /* Check the parameters */
840 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
841
842 if (PeriphClkInit->I2c1ClockSelection == RCC_I2C1CLKSOURCE_IC10)
843 {
844 /* Check the parameters */
845 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection));
846 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider));
847
848 /* Set IC10 configuration */
849 MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT,
850 PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \
851 ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos));
852
853 LL_RCC_IC10_Enable();
854 }
855 else if (PeriphClkInit->I2c1ClockSelection == RCC_I2C1CLKSOURCE_IC15)
856 {
857 /* Check the parameters */
858 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
859 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
860
861 /* Set IC15 configuration */
862 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
863 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
864 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
865
866 LL_RCC_IC15_Enable();
867 }
868 else if (PeriphClkInit->I2c1ClockSelection == RCC_I2C1CLKSOURCE_CLKP)
869 {
870 LL_RCC_CLKP_Enable();
871 }
872 else
873 {
874 /* No specific enable to do on other sources */
875 }
876
877 /* Set the source of I2C1 clock*/
878 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
879 }
880
881 /*------------------------------ I2C2 Configuration ------------------------*/
882 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
883 {
884 /* Check the parameters */
885 assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
886
887 if (PeriphClkInit->I2c2ClockSelection == RCC_I2C2CLKSOURCE_IC10)
888 {
889 /* Check the parameters */
890 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection));
891 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider));
892
893 /* Set IC10 configuration */
894 MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT,
895 PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \
896 ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos));
897
898 LL_RCC_IC10_Enable();
899 }
900 else if (PeriphClkInit->I2c2ClockSelection == RCC_I2C2CLKSOURCE_IC15)
901 {
902 /* Check the parameters */
903 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
904 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
905
906 /* Set IC15 configuration */
907 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
908 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
909 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
910
911 LL_RCC_IC15_Enable();
912 }
913 else if (PeriphClkInit->I2c2ClockSelection == RCC_I2C2CLKSOURCE_CLKP)
914 {
915 LL_RCC_CLKP_Enable();
916 }
917 else
918 {
919 /* No specific enable to do on other sources */
920 }
921
922 /* Set the source of I2C2 clock*/
923 __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
924 }
925
926 /*------------------------------ I2C3 Configuration ------------------------*/
927 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
928 {
929 /* Check the parameters */
930 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
931
932 if (PeriphClkInit->I2c3ClockSelection == RCC_I2C3CLKSOURCE_IC10)
933 {
934 /* Check the parameters */
935 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection));
936 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider));
937
938 /* Set IC10 configuration */
939 MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT,
940 PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \
941 ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos));
942
943 LL_RCC_IC10_Enable();
944 }
945 else if (PeriphClkInit->I2c3ClockSelection == RCC_I2C3CLKSOURCE_IC15)
946 {
947 /* Check the parameters */
948 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
949 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
950
951 /* Set IC15 configuration */
952 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
953 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
954 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
955
956 LL_RCC_IC15_Enable();
957 }
958 else if (PeriphClkInit->I2c3ClockSelection == RCC_I2C3CLKSOURCE_CLKP)
959 {
960 LL_RCC_CLKP_Enable();
961 }
962 else
963 {
964 /* No specific enable to do on other sources */
965 }
966
967 /* Set the source of I2C3 clock*/
968 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
969 }
970
971 /*------------------------------ I2C4 Configuration ------------------------*/
972 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
973 {
974 /* Check the parameters */
975 assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
976
977 if (PeriphClkInit->I2c4ClockSelection == RCC_I2C4CLKSOURCE_IC10)
978 {
979 /* Check the parameters */
980 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection));
981 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider));
982
983 /* Set IC10 configuration */
984 MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT,
985 PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \
986 ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos));
987
988 LL_RCC_IC10_Enable();
989 }
990 else if (PeriphClkInit->I2c4ClockSelection == RCC_I2C4CLKSOURCE_IC15)
991 {
992 /* Check the parameters */
993 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
994 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
995
996 /* Set IC15 configuration */
997 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
998 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
999 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
1000
1001 LL_RCC_IC15_Enable();
1002 }
1003 else if (PeriphClkInit->I2c4ClockSelection == RCC_I2C4CLKSOURCE_CLKP)
1004 {
1005 LL_RCC_CLKP_Enable();
1006 }
1007 else
1008 {
1009 /* No specific enable to do on other sources */
1010 }
1011
1012 /* Set the source of I2C4 clock*/
1013 __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
1014 }
1015
1016 /*------------------------------ I3C1 Configuration ------------------------*/
1017 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I3C1) == RCC_PERIPHCLK_I3C1)
1018 {
1019 /* Check the parameters */
1020 assert_param(IS_RCC_I3C1CLKSOURCE(PeriphClkInit->I3c1ClockSelection));
1021
1022 if (PeriphClkInit->I3c1ClockSelection == RCC_I3C1CLKSOURCE_IC10)
1023 {
1024 /* Check the parameters */
1025 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection));
1026 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider));
1027
1028 /* Set IC10 configuration */
1029 MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT,
1030 PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \
1031 ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos));
1032
1033 LL_RCC_IC10_Enable();
1034 }
1035 else if (PeriphClkInit->I3c1ClockSelection == RCC_I3C1CLKSOURCE_IC15)
1036 {
1037 /* Check the parameters */
1038 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
1039 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
1040
1041 /* Set IC15 configuration */
1042 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
1043 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
1044 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
1045
1046 LL_RCC_IC15_Enable();
1047 }
1048 else if (PeriphClkInit->I3c1ClockSelection == RCC_I3C1CLKSOURCE_CLKP)
1049 {
1050 LL_RCC_CLKP_Enable();
1051 }
1052 else
1053 {
1054 /* No specific enable to do on other sources */
1055 }
1056
1057 /* Set the source of I3C1 clock*/
1058 __HAL_RCC_I3C1_CONFIG(PeriphClkInit->I3c1ClockSelection);
1059 }
1060
1061 /*------------------------------ I3C2 Configuration ------------------------*/
1062 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_I3C2) == RCC_PERIPHCLK_I3C2)
1063 {
1064 /* Check the parameters */
1065 assert_param(IS_RCC_I3C2CLKSOURCE(PeriphClkInit->I3c2ClockSelection));
1066
1067 if (PeriphClkInit->I3c2ClockSelection == RCC_I3C2CLKSOURCE_IC10)
1068 {
1069 /* Check the parameters */
1070 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC10].ClockSelection));
1071 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC10].ClockDivider));
1072
1073 /* Set IC10 configuration */
1074 MODIFY_REG(RCC->IC10CFGR, RCC_IC10CFGR_IC10SEL | RCC_IC10CFGR_IC10INT,
1075 PeriphClkInit->ICSelection[RCC_IC10].ClockSelection | \
1076 ((PeriphClkInit->ICSelection[RCC_IC10].ClockDivider - 1U) << RCC_IC10CFGR_IC10INT_Pos));
1077
1078 LL_RCC_IC10_Enable();
1079 }
1080 else if (PeriphClkInit->I3c2ClockSelection == RCC_I3C2CLKSOURCE_IC15)
1081 {
1082 /* Check the parameters */
1083 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
1084 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
1085
1086 /* Set IC15 configuration */
1087 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
1088 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
1089 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
1090
1091 LL_RCC_IC15_Enable();
1092 }
1093 else if (PeriphClkInit->I3c2ClockSelection == RCC_I3C2CLKSOURCE_CLKP)
1094 {
1095 LL_RCC_CLKP_Enable();
1096 }
1097 else
1098 {
1099 /* No specific enable to do on other sources */
1100 }
1101
1102 /* Set the source of I3C2 clock*/
1103 __HAL_RCC_I3C2_CONFIG(PeriphClkInit->I3c2ClockSelection);
1104 }
1105
1106 /*---------------------------- LPTIM1 configuration ------------------------*/
1107 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
1108 {
1109 /* Check the parameters */
1110 assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
1111
1112 if (PeriphClkInit->Lptim1ClockSelection == RCC_LPTIM1CLKSOURCE_IC15)
1113 {
1114 /* Check the parameters */
1115 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
1116 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
1117
1118 /* Set IC15 configuration */
1119 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
1120 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
1121 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
1122
1123 LL_RCC_IC15_Enable();
1124 }
1125 else if (PeriphClkInit->Lptim1ClockSelection == RCC_LPTIM1CLKSOURCE_CLKP)
1126 {
1127 LL_RCC_CLKP_Enable();
1128 }
1129 else
1130 {
1131 /* No specific enable to do on other sources */
1132 }
1133
1134 /* Set the source of LPTIM1 clock*/
1135 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
1136 }
1137
1138 /*---------------------------- LPTIM2 configuration ------------------------*/
1139 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
1140 {
1141 /* Check the parameters */
1142 assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection));
1143
1144 if (PeriphClkInit->Lptim2ClockSelection == RCC_LPTIM2CLKSOURCE_IC15)
1145 {
1146 /* Check the parameters */
1147 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
1148 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
1149
1150 /* Set IC15 configuration */
1151 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
1152 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
1153 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
1154
1155 LL_RCC_IC15_Enable();
1156 }
1157 else if (PeriphClkInit->Lptim2ClockSelection == RCC_LPTIM2CLKSOURCE_CLKP)
1158 {
1159 LL_RCC_CLKP_Enable();
1160 }
1161 else
1162 {
1163 /* No specific enable to do on other sources */
1164 }
1165
1166 /* Set the source of LPTIM2 clock*/
1167 __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
1168 }
1169
1170 /*---------------------------- LPTIM3 configuration -----------------*/
1171 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3)
1172 {
1173 /* Check the parameters */
1174 assert_param(IS_RCC_LPTIM3CLKSOURCE(PeriphClkInit->Lptim3ClockSelection));
1175
1176 if (PeriphClkInit->Lptim3ClockSelection == RCC_LPTIM3CLKSOURCE_IC15)
1177 {
1178 /* Check the parameters */
1179 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
1180 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
1181
1182 /* Set IC15 configuration */
1183 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
1184 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
1185 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
1186
1187 LL_RCC_IC15_Enable();
1188 }
1189 else if (PeriphClkInit->Lptim3ClockSelection == RCC_LPTIM3CLKSOURCE_CLKP)
1190 {
1191 LL_RCC_CLKP_Enable();
1192 }
1193 else
1194 {
1195 /* No specific enable to do on other sources */
1196 }
1197
1198 /* Set the source of LPTIM3 clock */
1199 __HAL_RCC_LPTIM3_CONFIG(PeriphClkInit->Lptim3ClockSelection);
1200 }
1201
1202 /*---------------------------- LPTIM4 configuration -----------------*/
1203 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM4) == RCC_PERIPHCLK_LPTIM4)
1204 {
1205 /* Check the parameters */
1206 assert_param(IS_RCC_LPTIM4CLKSOURCE(PeriphClkInit->Lptim4ClockSelection));
1207
1208 if (PeriphClkInit->Lptim4ClockSelection == RCC_LPTIM4CLKSOURCE_IC15)
1209 {
1210 /* Check the parameters */
1211 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
1212 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
1213
1214 /* Set IC15 configuration */
1215 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
1216 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
1217 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
1218
1219 LL_RCC_IC15_Enable();
1220 }
1221 else if (PeriphClkInit->Lptim4ClockSelection == RCC_LPTIM4CLKSOURCE_CLKP)
1222 {
1223 LL_RCC_CLKP_Enable();
1224 }
1225 else
1226 {
1227 /* No specific enable to do on other sources */
1228 }
1229
1230 /* Set the source of LPTIM4 clock */
1231 __HAL_RCC_LPTIM4_CONFIG(PeriphClkInit->Lptim4ClockSelection);
1232 }
1233
1234 /*---------------------------- LPTIM5 configuration -----------------*/
1235 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPTIM5) == RCC_PERIPHCLK_LPTIM5)
1236 {
1237 /* Check the parameters */
1238 assert_param(IS_RCC_LPTIM5CLKSOURCE(PeriphClkInit->Lptim5ClockSelection));
1239
1240 if (PeriphClkInit->Lptim5ClockSelection == RCC_LPTIM5CLKSOURCE_IC15)
1241 {
1242 /* Check the parameters */
1243 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
1244 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
1245
1246 /* Set IC15 configuration */
1247 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
1248 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
1249 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
1250
1251 LL_RCC_IC15_Enable();
1252 }
1253 else if (PeriphClkInit->Lptim5ClockSelection == RCC_LPTIM5CLKSOURCE_CLKP)
1254 {
1255 LL_RCC_CLKP_Enable();
1256 }
1257 else
1258 {
1259 /* No specific enable to do on other sources */
1260 }
1261
1262 /* Set the source of LPTIM5 clock */
1263 __HAL_RCC_LPTIM5_CONFIG(PeriphClkInit->Lptim5ClockSelection);
1264 }
1265
1266 /*-------------------------- LPUART1 Configuration -------------------------*/
1267 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
1268 {
1269 /* Check the parameters */
1270 assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
1271
1272 if (PeriphClkInit->Lpuart1ClockSelection == RCC_LPUART1CLKSOURCE_IC9)
1273 {
1274 /* Check the parameters */
1275 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
1276 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
1277
1278 /* Set IC9 configuration */
1279 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
1280 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
1281 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
1282
1283 LL_RCC_IC9_Enable();
1284 }
1285 else if (PeriphClkInit->Lpuart1ClockSelection == RCC_LPUART1CLKSOURCE_IC14)
1286 {
1287 /* Check the parameters */
1288 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
1289 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
1290
1291 /* Set IC14 configuration */
1292 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
1293 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
1294 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
1295
1296 LL_RCC_IC14_Enable();
1297 }
1298 else if (PeriphClkInit->Lpuart1ClockSelection == RCC_LPUART1CLKSOURCE_CLKP)
1299 {
1300 LL_RCC_CLKP_Enable();
1301 }
1302 else
1303 {
1304 /* No specific enable to do on other sources */
1305 }
1306
1307 /* Set the source of LPUART1 clock */
1308 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
1309 }
1310
1311 /*-------------------------- LTDC Configuration ----------------------------*/
1312 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
1313 {
1314 /* Check the parameters */
1315 assert_param(IS_RCC_LTDCCLKSOURCE(PeriphClkInit->LtdcClockSelection));
1316
1317 if (PeriphClkInit->LtdcClockSelection == RCC_LTDCCLKSOURCE_IC16)
1318 {
1319 /* Check the parameters */
1320 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC16].ClockSelection));
1321 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC16].ClockDivider));
1322
1323 /* Set IC16 configuration */
1324 MODIFY_REG(RCC->IC16CFGR, RCC_IC16CFGR_IC16SEL | RCC_IC16CFGR_IC16INT,
1325 PeriphClkInit->ICSelection[RCC_IC16].ClockSelection | \
1326 ((PeriphClkInit->ICSelection[RCC_IC16].ClockDivider - 1U) << RCC_IC16CFGR_IC16INT_Pos));
1327
1328 LL_RCC_IC16_Enable();
1329 }
1330 else if (PeriphClkInit->LtdcClockSelection == RCC_LTDCCLKSOURCE_CLKP)
1331 {
1332 LL_RCC_CLKP_Enable();
1333 }
1334 else
1335 {
1336 /* No specific enable to do on other sources */
1337 }
1338
1339 /* Set the source of LTDC clock */
1340 __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection);
1341 }
1342
1343 /*---------------------------- MDF1 configuration --------------------------*/
1344 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_MDF1) == RCC_PERIPHCLK_MDF1)
1345 {
1346 /* Check the parameters */
1347 assert_param(IS_RCC_MDF1CLKSOURCE(PeriphClkInit->Mdf1ClockSelection));
1348
1349 if (PeriphClkInit->Mdf1ClockSelection == RCC_MDF1CLKSOURCE_IC7)
1350 {
1351 /* Check the parameters */
1352 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection));
1353 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider));
1354
1355 /* Set IC7 configuration */
1356 MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT,
1357 PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \
1358 ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos));
1359
1360 LL_RCC_IC7_Enable();
1361 }
1362 else if (PeriphClkInit->Mdf1ClockSelection == RCC_MDF1CLKSOURCE_IC8)
1363 {
1364 /* Check the parameters */
1365 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
1366 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
1367
1368 /* Set IC8 configuration */
1369 MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
1370 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
1371 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
1372
1373 LL_RCC_IC8_Enable();
1374 }
1375 else if (PeriphClkInit->Mdf1ClockSelection == RCC_MDF1CLKSOURCE_CLKP)
1376 {
1377 LL_RCC_CLKP_Enable();
1378 }
1379 else
1380 {
1381 /* No specific enable to do on other sources */
1382 }
1383
1384 /* Set the source of MDF1 clock*/
1385 __HAL_RCC_MDF1_CONFIG(PeriphClkInit->Mdf1ClockSelection);
1386 }
1387
1388 /*---------------------------- PSSI configuration --------------------------*/
1389 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PSSI) == RCC_PERIPHCLK_PSSI)
1390 {
1391 /* Check the parameters */
1392 assert_param(IS_RCC_PSSICLKSOURCE(PeriphClkInit->PssiClockSelection));
1393
1394 if (PeriphClkInit->PssiClockSelection == RCC_PSSICLKSOURCE_IC20)
1395 {
1396 /* Check the parameters */
1397 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC20].ClockSelection));
1398 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC20].ClockDivider));
1399
1400 /* Set IC20 configuration */
1401 MODIFY_REG(RCC->IC20CFGR, RCC_IC20CFGR_IC20SEL | RCC_IC20CFGR_IC20INT,
1402 PeriphClkInit->ICSelection[RCC_IC20].ClockSelection | \
1403 ((PeriphClkInit->ICSelection[RCC_IC20].ClockDivider - 1U) << RCC_IC20CFGR_IC20INT_Pos));
1404
1405 LL_RCC_IC20_Enable();
1406 }
1407 else if (PeriphClkInit->PssiClockSelection == RCC_PSSICLKSOURCE_CLKP)
1408 {
1409 LL_RCC_CLKP_Enable();
1410 }
1411 else
1412 {
1413 /* No specific enable to do on other sources */
1414 }
1415
1416 /* Set the source of PSSI clock*/
1417 __HAL_RCC_PSSI_CONFIG(PeriphClkInit->PssiClockSelection);
1418 }
1419
1420 /*---------------------------- SAI1 configuration --------------------------*/
1421 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
1422 {
1423 /* Check the parameters */
1424 assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
1425
1426 if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_IC7)
1427 {
1428 /* Check the parameters */
1429 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection));
1430 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider));
1431
1432 /* Set IC7 configuration */
1433 MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT,
1434 PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \
1435 ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos));
1436
1437 LL_RCC_IC7_Enable();
1438 }
1439 else if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_IC8)
1440 {
1441 /* Check the parameters */
1442 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
1443 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
1444
1445 /* Set IC8 configuration */
1446 MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
1447 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
1448 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
1449
1450 LL_RCC_IC8_Enable();
1451 }
1452 else if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_CLKP)
1453 {
1454 LL_RCC_CLKP_Enable();
1455 }
1456 else
1457 {
1458 /* No specific enable to do on other sources */
1459 }
1460
1461 /* Set the source of SAI1 clock*/
1462 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
1463 }
1464
1465 /*---------------------------- SAI2 configuration --------------------------*/
1466 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)
1467 {
1468 /* Check the parameters */
1469 assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
1470
1471 if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_IC7)
1472 {
1473 /* Check the parameters */
1474 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection));
1475 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider));
1476
1477 /* Set IC7 configuration */
1478 MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT,
1479 PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \
1480 ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos));
1481
1482 LL_RCC_IC7_Enable();
1483 }
1484 else if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_IC8)
1485 {
1486 /* Check the parameters */
1487 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
1488 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
1489
1490 /* Set IC8 configuration */
1491 MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
1492 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
1493 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
1494
1495 LL_RCC_IC8_Enable();
1496 }
1497 else if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_CLKP)
1498 {
1499 LL_RCC_CLKP_Enable();
1500 }
1501 else
1502 {
1503 /* No specific enable to do on other sources */
1504 }
1505
1506 /* Set the source of SAI2 clock*/
1507 __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
1508 }
1509
1510 /*---------------------------- SPDIFRX1 configuration -------------------------------*/
1511 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPDIFRX1) == RCC_PERIPHCLK_SPDIFRX1)
1512 {
1513 /* Check the parameters */
1514 assert_param(IS_RCC_SPDIFRX1CLKSOURCE(PeriphClkInit->Spdifrx1ClockSelection));
1515
1516 if (PeriphClkInit->Spdifrx1ClockSelection == RCC_SPDIFRX1CLKSOURCE_IC7)
1517 {
1518 /* Check the parameters */
1519 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC7].ClockSelection));
1520 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC7].ClockDivider));
1521
1522 /* Set IC7 configuration */
1523 MODIFY_REG(RCC->IC7CFGR, RCC_IC7CFGR_IC7SEL | RCC_IC7CFGR_IC7INT,
1524 PeriphClkInit->ICSelection[RCC_IC7].ClockSelection | \
1525 ((PeriphClkInit->ICSelection[RCC_IC7].ClockDivider - 1U) << RCC_IC7CFGR_IC7INT_Pos));
1526
1527 LL_RCC_IC7_Enable();
1528 }
1529 else if (PeriphClkInit->Spdifrx1ClockSelection == RCC_SPDIFRX1CLKSOURCE_IC8)
1530 {
1531 /* Check the parameters */
1532 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
1533 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
1534
1535 /* Set IC8 configuration */
1536 MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
1537 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
1538 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
1539
1540 LL_RCC_IC8_Enable();
1541 }
1542 else if (PeriphClkInit->Spdifrx1ClockSelection == RCC_SPDIFRX1CLKSOURCE_CLKP)
1543 {
1544 LL_RCC_CLKP_Enable();
1545 }
1546 else
1547 {
1548 /* No specific enable to do on other sources */
1549 }
1550
1551 /* Set the source of SPDIFRX1 clock */
1552 __HAL_RCC_SPDIFRX1_CONFIG(PeriphClkInit->Spdifrx1ClockSelection);
1553 }
1554
1555 /*---------------------------- SPI1 configuration --------------------------*/
1556 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1)
1557 {
1558 /* Check the parameters */
1559 assert_param(IS_RCC_SPI1CLKSOURCE(PeriphClkInit->Spi1ClockSelection));
1560
1561 if (PeriphClkInit->Spi1ClockSelection == RCC_SPI1CLKSOURCE_IC8)
1562 {
1563 /* Check the parameters */
1564 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
1565 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
1566
1567 /* Set IC8 configuration */
1568 MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
1569 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
1570 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
1571
1572 LL_RCC_IC8_Enable();
1573 }
1574 else if (PeriphClkInit->Spi1ClockSelection == RCC_SPI1CLKSOURCE_IC9)
1575 {
1576 /* Check the parameters */
1577 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
1578 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
1579
1580 /* Set IC9 configuration */
1581 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
1582 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
1583 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
1584
1585 LL_RCC_IC9_Enable();
1586 }
1587 else if (PeriphClkInit->Spi1ClockSelection == RCC_SPI1CLKSOURCE_CLKP)
1588 {
1589 LL_RCC_CLKP_Enable();
1590 }
1591 else
1592 {
1593 /* No specific enable to do on other sources */
1594 }
1595
1596 /* Set the source of SPI1 clock*/
1597 __HAL_RCC_SPI1_CONFIG(PeriphClkInit->Spi1ClockSelection);
1598 }
1599
1600 /*---------------------------- SPI2 configuration ---------------------*/
1601 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2)
1602 {
1603 /* Check the parameters */
1604 assert_param(IS_RCC_SPI2CLKSOURCE(PeriphClkInit->Spi2ClockSelection));
1605
1606 if (PeriphClkInit->Spi2ClockSelection == RCC_SPI2CLKSOURCE_IC8)
1607 {
1608 /* Check the parameters */
1609 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
1610 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
1611
1612 /* Set IC8 configuration */
1613 MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
1614 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
1615 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
1616
1617 LL_RCC_IC8_Enable();
1618 }
1619 else if (PeriphClkInit->Spi2ClockSelection == RCC_SPI2CLKSOURCE_IC9)
1620 {
1621 /* Check the parameters */
1622 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
1623 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
1624
1625 /* Set IC9 configuration */
1626 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
1627 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
1628 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
1629
1630 LL_RCC_IC9_Enable();
1631 }
1632 else if (PeriphClkInit->Spi2ClockSelection == RCC_SPI2CLKSOURCE_CLKP)
1633 {
1634 LL_RCC_CLKP_Enable();
1635 }
1636 else
1637 {
1638 /* No specific enable to do on other sources */
1639 }
1640
1641 /* Set the source of SPI2 clock*/
1642 __HAL_RCC_SPI2_CONFIG(PeriphClkInit->Spi2ClockSelection);
1643 }
1644
1645 /*---------------------------- SPI3 configuration ---------------------*/
1646 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3)
1647 {
1648 /* Check the parameters */
1649 assert_param(IS_RCC_SPI3CLKSOURCE(PeriphClkInit->Spi3ClockSelection));
1650
1651 if (PeriphClkInit->Spi3ClockSelection == RCC_SPI3CLKSOURCE_IC8)
1652 {
1653 /* Check the parameters */
1654 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
1655 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
1656
1657 /* Set IC8 configuration */
1658 MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
1659 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
1660 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
1661
1662 LL_RCC_IC8_Enable();
1663 }
1664 else if (PeriphClkInit->Spi3ClockSelection == RCC_SPI3CLKSOURCE_IC9)
1665 {
1666 /* Check the parameters */
1667 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
1668 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
1669
1670 /* Set IC9 configuration */
1671 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
1672 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
1673 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
1674
1675 LL_RCC_IC9_Enable();
1676 }
1677 else if (PeriphClkInit->Spi3ClockSelection == RCC_SPI3CLKSOURCE_CLKP)
1678 {
1679 LL_RCC_CLKP_Enable();
1680 }
1681 else
1682 {
1683 /* No specific enable to do on other sources */
1684 }
1685
1686 /* Set the source of SPI3 clock*/
1687 __HAL_RCC_SPI3_CONFIG(PeriphClkInit->Spi3ClockSelection);
1688 }
1689
1690 /*---------------------------- SPI4 configuration -------------------------------*/
1691 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI4) == RCC_PERIPHCLK_SPI4)
1692 {
1693 /* Check the parameters */
1694 assert_param(IS_RCC_SPI4CLKSOURCE(PeriphClkInit->Spi4ClockSelection));
1695
1696 if (PeriphClkInit->Spi4ClockSelection == RCC_SPI4CLKSOURCE_IC9)
1697 {
1698 /* Check the parameters */
1699 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
1700 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
1701
1702 /* Set IC9 configuration */
1703 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
1704 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
1705 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
1706
1707 LL_RCC_IC9_Enable();
1708 }
1709 else if (PeriphClkInit->Spi4ClockSelection == RCC_SPI4CLKSOURCE_IC14)
1710 {
1711 /* Check the parameters */
1712 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
1713 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
1714
1715 /* Set IC14 configuration */
1716 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
1717 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
1718 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
1719
1720 LL_RCC_IC14_Enable();
1721 }
1722 else if (PeriphClkInit->Spi4ClockSelection == RCC_SPI4CLKSOURCE_CLKP)
1723 {
1724 LL_RCC_CLKP_Enable();
1725 }
1726 else
1727 {
1728 /* No specific enable to do on other sources */
1729 }
1730
1731 /* Set the source of SPI4 clock */
1732 __HAL_RCC_SPI4_CONFIG(PeriphClkInit->Spi4ClockSelection);
1733 }
1734
1735 /*---------------------------- SPI5 configuration -------------------------------*/
1736 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI5) == RCC_PERIPHCLK_SPI5)
1737 {
1738 /* Check the parameters */
1739 assert_param(IS_RCC_SPI5CLKSOURCE(PeriphClkInit->Spi5ClockSelection));
1740
1741 if (PeriphClkInit->Spi5ClockSelection == RCC_SPI5CLKSOURCE_IC9)
1742 {
1743 /* Check the parameters */
1744 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
1745 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
1746
1747 /* Set IC9 configuration */
1748 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
1749 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
1750 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
1751
1752 LL_RCC_IC9_Enable();
1753 }
1754 else if (PeriphClkInit->Spi5ClockSelection == RCC_SPI5CLKSOURCE_IC14)
1755 {
1756 /* Check the parameters */
1757 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
1758 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
1759
1760 /* Set IC14 configuration */
1761 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
1762 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
1763 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
1764
1765 LL_RCC_IC14_Enable();
1766 }
1767 else if (PeriphClkInit->Spi5ClockSelection == RCC_SPI5CLKSOURCE_CLKP)
1768 {
1769 LL_RCC_CLKP_Enable();
1770 }
1771 else
1772 {
1773 /* No specific enable to do on other sources */
1774 }
1775
1776 /* Set the source of SPI5 clock */
1777 __HAL_RCC_SPI5_CONFIG(PeriphClkInit->Spi5ClockSelection);
1778 }
1779
1780 /*---------------------------- SPI6 configuration --------------------------*/
1781 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
1782 {
1783 /* Check the parameters */
1784 assert_param(IS_RCC_SPI6CLKSOURCE(PeriphClkInit->Spi6ClockSelection));
1785
1786 if (PeriphClkInit->Spi6ClockSelection == RCC_SPI6CLKSOURCE_IC8)
1787 {
1788 /* Check the parameters */
1789 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC8].ClockSelection));
1790 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC8].ClockDivider));
1791
1792 /* Set IC8 configuration */
1793 MODIFY_REG(RCC->IC8CFGR, RCC_IC8CFGR_IC8SEL | RCC_IC8CFGR_IC8INT,
1794 PeriphClkInit->ICSelection[RCC_IC8].ClockSelection | \
1795 ((PeriphClkInit->ICSelection[RCC_IC8].ClockDivider - 1U) << RCC_IC8CFGR_IC8INT_Pos));
1796
1797 LL_RCC_IC8_Enable();
1798 }
1799 else if (PeriphClkInit->Spi6ClockSelection == RCC_SPI6CLKSOURCE_IC9)
1800 {
1801 /* Check the parameters */
1802 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
1803 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
1804
1805 /* Set IC9 configuration */
1806 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
1807 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
1808 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
1809
1810 LL_RCC_IC9_Enable();
1811 }
1812 else if (PeriphClkInit->Spi6ClockSelection == RCC_SPI6CLKSOURCE_CLKP)
1813 {
1814 LL_RCC_CLKP_Enable();
1815 }
1816 else
1817 {
1818 /* No specific enable to do on other sources */
1819 }
1820
1821 /* Set the source of SPI6 clock*/
1822 __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
1823 }
1824
1825 /*-------------------------- USART1 configuration --------------------------*/
1826 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
1827 {
1828 /* Check the parameters */
1829 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
1830
1831 if (PeriphClkInit->Usart1ClockSelection == RCC_USART1CLKSOURCE_IC9)
1832 {
1833 /* Check the parameters */
1834 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
1835 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
1836
1837 /* Set IC9 configuration */
1838 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
1839 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
1840 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
1841
1842 LL_RCC_IC9_Enable();
1843 }
1844 else if (PeriphClkInit->Usart1ClockSelection == RCC_USART1CLKSOURCE_IC14)
1845 {
1846 /* Check the parameters */
1847 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
1848 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
1849
1850 /* Set IC14 configuration */
1851 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
1852 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
1853 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
1854
1855 LL_RCC_IC14_Enable();
1856 }
1857 else if (PeriphClkInit->Usart1ClockSelection == RCC_USART1CLKSOURCE_CLKP)
1858 {
1859 LL_RCC_CLKP_Enable();
1860 }
1861 else
1862 {
1863 /* No specific enable to do on other sources */
1864 }
1865
1866 /* Set the source of USART1 clock */
1867 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
1868 }
1869
1870 /*-------------------------- USART2 configuration --------------------------*/
1871 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
1872 {
1873 /* Check the parameters */
1874 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
1875
1876 if (PeriphClkInit->Usart2ClockSelection == RCC_USART2CLKSOURCE_IC9)
1877 {
1878 /* Check the parameters */
1879 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
1880 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
1881
1882 /* Set IC9 configuration */
1883 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
1884 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
1885 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
1886
1887 LL_RCC_IC9_Enable();
1888 }
1889 else if (PeriphClkInit->Usart2ClockSelection == RCC_USART2CLKSOURCE_IC14)
1890 {
1891 /* Check the parameters */
1892 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
1893 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
1894
1895 /* Set IC14 configuration */
1896 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
1897 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
1898 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
1899
1900 LL_RCC_IC14_Enable();
1901 }
1902 else if (PeriphClkInit->Usart2ClockSelection == RCC_USART2CLKSOURCE_CLKP)
1903 {
1904 LL_RCC_CLKP_Enable();
1905 }
1906 else
1907 {
1908 /* No specific enable to do on other sources */
1909 }
1910
1911 /* Set the source of USART2 clock */
1912 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
1913 }
1914
1915 /*-------------------------- USART3 configuration --------------------------*/
1916 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
1917 {
1918 /* Check the parameters */
1919 assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
1920
1921 if (PeriphClkInit->Usart3ClockSelection == RCC_USART3CLKSOURCE_IC9)
1922 {
1923 /* Check the parameters */
1924 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
1925 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
1926
1927 /* Set IC9 configuration */
1928 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
1929 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
1930 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
1931
1932 LL_RCC_IC9_Enable();
1933 }
1934 else if (PeriphClkInit->Usart3ClockSelection == RCC_USART3CLKSOURCE_IC14)
1935 {
1936 /* Check the parameters */
1937 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
1938 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
1939
1940 /* Set IC14 configuration */
1941 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
1942 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
1943 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
1944
1945 LL_RCC_IC14_Enable();
1946 }
1947 else if (PeriphClkInit->Usart3ClockSelection == RCC_USART3CLKSOURCE_CLKP)
1948 {
1949 LL_RCC_CLKP_Enable();
1950 }
1951 else
1952 {
1953 /* No specific enable to do on other sources */
1954 }
1955
1956 /* Set the source of USART3 clock */
1957 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
1958 }
1959
1960 /*-------------------------- UART4 configuration --------------------------*/
1961 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
1962 {
1963 /* Check the parameters */
1964 assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
1965
1966 if (PeriphClkInit->Uart4ClockSelection == RCC_UART4CLKSOURCE_IC9)
1967 {
1968 /* Check the parameters */
1969 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
1970 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
1971
1972 /* Set IC9 configuration */
1973 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
1974 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
1975 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
1976
1977 LL_RCC_IC9_Enable();
1978 }
1979 else if (PeriphClkInit->Uart4ClockSelection == RCC_UART4CLKSOURCE_IC14)
1980 {
1981 /* Check the parameters */
1982 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
1983 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
1984
1985 /* Set IC14 configuration */
1986 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
1987 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
1988 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
1989
1990 LL_RCC_IC14_Enable();
1991 }
1992 else if (PeriphClkInit->Uart4ClockSelection == RCC_UART4CLKSOURCE_CLKP)
1993 {
1994 LL_RCC_CLKP_Enable();
1995 }
1996 else
1997 {
1998 /* No specific enable to do on other sources */
1999 }
2000
2001 /* Set the source of UART4 clock */
2002 __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
2003 }
2004
2005 /*-------------------------- UART5 configuration --------------------------*/
2006 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
2007 {
2008 /* Check the parameters */
2009 assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
2010
2011 if (PeriphClkInit->Uart5ClockSelection == RCC_UART5CLKSOURCE_IC9)
2012 {
2013 /* Check the parameters */
2014 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
2015 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
2016
2017 /* Set IC9 configuration */
2018 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
2019 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
2020 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
2021
2022 LL_RCC_IC9_Enable();
2023 }
2024 else if (PeriphClkInit->Uart5ClockSelection == RCC_UART5CLKSOURCE_IC14)
2025 {
2026 /* Check the parameters */
2027 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
2028 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
2029
2030 /* Set IC14 configuration */
2031 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
2032 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
2033 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
2034
2035 LL_RCC_IC14_Enable();
2036 }
2037 else if (PeriphClkInit->Uart5ClockSelection == RCC_UART5CLKSOURCE_CLKP)
2038 {
2039 LL_RCC_CLKP_Enable();
2040 }
2041 else
2042 {
2043 /* No specific enable to do on other sources */
2044 }
2045
2046 /* Set the source of UART5 clock */
2047 __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
2048 }
2049
2050 /*-------------------------- USART6 configuration --------------------------*/
2051 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
2052 {
2053 /* Check the parameters */
2054 assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
2055
2056 if (PeriphClkInit->Usart6ClockSelection == RCC_USART6CLKSOURCE_IC9)
2057 {
2058 /* Check the parameters */
2059 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
2060 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
2061
2062 /* Set IC9 configuration */
2063 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
2064 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
2065 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
2066
2067 LL_RCC_IC9_Enable();
2068 }
2069 else if (PeriphClkInit->Usart6ClockSelection == RCC_USART6CLKSOURCE_IC14)
2070 {
2071 /* Check the parameters */
2072 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
2073 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
2074
2075 /* Set IC14 configuration */
2076 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
2077 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
2078 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
2079
2080 LL_RCC_IC14_Enable();
2081 }
2082 else if (PeriphClkInit->Usart6ClockSelection == RCC_USART6CLKSOURCE_CLKP)
2083 {
2084 LL_RCC_CLKP_Enable();
2085 }
2086 else
2087 {
2088 /* No specific enable to do on other sources */
2089 }
2090
2091 /* Set the source of USART6 clock */
2092 __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
2093 }
2094
2095 /*-------------------------- UART7 configuration --------------------------*/
2096 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
2097 {
2098 /* Check the parameters */
2099 assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
2100
2101 if (PeriphClkInit->Uart7ClockSelection == RCC_UART7CLKSOURCE_IC9)
2102 {
2103 /* Check the parameters */
2104 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
2105 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
2106
2107 /* Set IC9 configuration */
2108 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
2109 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
2110 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
2111
2112 LL_RCC_IC9_Enable();
2113 }
2114 else if (PeriphClkInit->Uart7ClockSelection == RCC_UART7CLKSOURCE_IC14)
2115 {
2116 /* Check the parameters */
2117 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
2118 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
2119
2120 /* Set IC14 configuration */
2121 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
2122 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
2123 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
2124
2125 LL_RCC_IC14_Enable();
2126 }
2127 else if (PeriphClkInit->Uart7ClockSelection == RCC_UART7CLKSOURCE_CLKP)
2128 {
2129 LL_RCC_CLKP_Enable();
2130 }
2131 else
2132 {
2133 /* No specific enable to do on other sources */
2134 }
2135
2136 /* Set the source of UART7 clock */
2137 __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
2138 }
2139
2140 /*-------------------------- UART8 configuration --------------------------*/
2141 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
2142 {
2143 /* Check the parameters */
2144 assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
2145
2146 if (PeriphClkInit->Uart8ClockSelection == RCC_UART8CLKSOURCE_IC9)
2147 {
2148 /* Check the parameters */
2149 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
2150 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
2151
2152 /* Set IC9 configuration */
2153 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
2154 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
2155 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
2156
2157 LL_RCC_IC9_Enable();
2158 }
2159 else if (PeriphClkInit->Uart8ClockSelection == RCC_UART8CLKSOURCE_IC14)
2160 {
2161 /* Check the parameters */
2162 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
2163 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
2164
2165 /* Set IC14 configuration */
2166 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
2167 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
2168 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
2169
2170 LL_RCC_IC14_Enable();
2171 }
2172 else if (PeriphClkInit->Uart8ClockSelection == RCC_UART8CLKSOURCE_CLKP)
2173 {
2174 LL_RCC_CLKP_Enable();
2175 }
2176 else
2177 {
2178 /* No specific enable to do on other sources */
2179 }
2180
2181 /* Set the source of UART8 clock */
2182 __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
2183 }
2184
2185 /*-------------------------- UART9 configuration --------------------------*/
2186 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_UART9) == RCC_PERIPHCLK_UART9)
2187 {
2188 /* Check the parameters */
2189 assert_param(IS_RCC_UART9CLKSOURCE(PeriphClkInit->Uart9ClockSelection));
2190
2191 if (PeriphClkInit->Uart9ClockSelection == RCC_UART9CLKSOURCE_IC9)
2192 {
2193 /* Check the parameters */
2194 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
2195 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
2196
2197 /* Set IC9 configuration */
2198 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
2199 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
2200 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
2201
2202 LL_RCC_IC9_Enable();
2203 }
2204 else if (PeriphClkInit->Uart9ClockSelection == RCC_UART9CLKSOURCE_IC14)
2205 {
2206 /* Check the parameters */
2207 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
2208 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
2209
2210 /* Set IC14 configuration */
2211 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
2212 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
2213 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
2214
2215 LL_RCC_IC14_Enable();
2216 }
2217 else if (PeriphClkInit->Uart9ClockSelection == RCC_UART9CLKSOURCE_CLKP)
2218 {
2219 LL_RCC_CLKP_Enable();
2220 }
2221 else
2222 {
2223 /* No specific enable to do on other sources */
2224 }
2225
2226 /* Set the source of UART9 clock */
2227 __HAL_RCC_UART9_CONFIG(PeriphClkInit->Uart9ClockSelection);
2228 }
2229
2230 /*-------------------------- USART10 configuration --------------------------*/
2231 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USART10) == RCC_PERIPHCLK_USART10)
2232 {
2233 /* Check the parameters */
2234 assert_param(IS_RCC_USART10CLKSOURCE(PeriphClkInit->Usart10ClockSelection));
2235
2236 if (PeriphClkInit->Usart10ClockSelection == RCC_USART10CLKSOURCE_IC9)
2237 {
2238 /* Check the parameters */
2239 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC9].ClockSelection));
2240 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC9].ClockDivider));
2241
2242 /* Set IC9 configuration */
2243 MODIFY_REG(RCC->IC9CFGR, RCC_IC9CFGR_IC9SEL | RCC_IC9CFGR_IC9INT,
2244 PeriphClkInit->ICSelection[RCC_IC9].ClockSelection | \
2245 ((PeriphClkInit->ICSelection[RCC_IC9].ClockDivider - 1U) << RCC_IC9CFGR_IC9INT_Pos));
2246
2247 LL_RCC_IC9_Enable();
2248 }
2249 else if (PeriphClkInit->Usart10ClockSelection == RCC_USART10CLKSOURCE_IC14)
2250 {
2251 /* Check the parameters */
2252 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC14].ClockSelection));
2253 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC14].ClockDivider));
2254
2255 /* Set IC14 configuration */
2256 MODIFY_REG(RCC->IC14CFGR, RCC_IC14CFGR_IC14SEL | RCC_IC14CFGR_IC14INT,
2257 PeriphClkInit->ICSelection[RCC_IC14].ClockSelection | \
2258 ((PeriphClkInit->ICSelection[RCC_IC14].ClockDivider - 1U) << RCC_IC14CFGR_IC14INT_Pos));
2259
2260 LL_RCC_IC14_Enable();
2261 }
2262 else if (PeriphClkInit->Usart10ClockSelection == RCC_USART10CLKSOURCE_CLKP)
2263 {
2264 LL_RCC_CLKP_Enable();
2265 }
2266 else
2267 {
2268 /* No specific enable to do on other sources */
2269 }
2270
2271 /* Set the source of USART10 clock */
2272 __HAL_RCC_USART10_CONFIG(PeriphClkInit->Usart10ClockSelection);
2273 }
2274
2275 /*------------------------------ USBPHY1 Configuration ---------------------*/
2276 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBPHY1) == RCC_PERIPHCLK_USBPHY1)
2277 {
2278 /* Check the parameters */
2279 assert_param(IS_RCC_USBPHY1CLKSOURCE(PeriphClkInit->UsbPhy1ClockSelection));
2280
2281 /* Set the source of USBPHY1 clock*/
2282 __HAL_RCC_USBPHY1_CONFIG(PeriphClkInit->UsbPhy1ClockSelection);
2283 }
2284
2285 /*------------------------------ USBPHY2 Configuration ---------------------*/
2286 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBPHY2) == RCC_PERIPHCLK_USBPHY2)
2287 {
2288 /* Check the parameters */
2289 assert_param(IS_RCC_USBPHY2CLKSOURCE(PeriphClkInit->UsbPhy2ClockSelection));
2290
2291 /* Set the source of USBPHY2 clock*/
2292 __HAL_RCC_USBPHY2_CONFIG(PeriphClkInit->UsbPhy2ClockSelection);
2293 }
2294
2295 /*------------------------------ USBOTGHS1 Configuration -------------------*/
2296 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBOTGHS1) == RCC_PERIPHCLK_USBOTGHS1)
2297 {
2298 /* Check the parameters */
2299 assert_param(IS_RCC_USBOTGHS1CLKSOURCE(PeriphClkInit->UsbOtgHs1ClockSelection));
2300
2301 if (PeriphClkInit->UsbOtgHs1ClockSelection == RCC_USBOTGHS1CLKSOURCE_IC15)
2302 {
2303 /* Check the parameters */
2304 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
2305 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
2306
2307 /* Set IC15 configuration */
2308 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
2309 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
2310 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
2311
2312 LL_RCC_IC15_Enable();
2313 }
2314 else if (PeriphClkInit->UsbOtgHs1ClockSelection == RCC_USBOTGHS1CLKSOURCE_CLKP)
2315 {
2316 LL_RCC_CLKP_Enable();
2317 }
2318 else
2319 {
2320 /* No specific enable to do on other sources */
2321 }
2322
2323 /* Set the source of USBOTGHS1 clock */
2324 __HAL_RCC_USBOTGHS1_CONFIG(PeriphClkInit->UsbOtgHs1ClockSelection);
2325 }
2326
2327 /*------------------------------ USBOTGHS2 Configuration -------------------*/
2328 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_USBOTGHS2) == RCC_PERIPHCLK_USBOTGHS2)
2329 {
2330 /* Check the parameters */
2331 assert_param(IS_RCC_USBOTGHS2CLKSOURCE(PeriphClkInit->UsbOtgHs2ClockSelection));
2332
2333 if (PeriphClkInit->UsbOtgHs2ClockSelection == RCC_USBOTGHS2CLKSOURCE_IC15)
2334 {
2335 /* Check the parameters */
2336 assert_param(IS_RCC_ICCLKSOURCE(PeriphClkInit->ICSelection[RCC_IC15].ClockSelection));
2337 assert_param(IS_RCC_ICCLKDIVIDER(PeriphClkInit->ICSelection[RCC_IC15].ClockDivider));
2338
2339 /* Set IC15 configuration */
2340 MODIFY_REG(RCC->IC15CFGR, RCC_IC15CFGR_IC15SEL | RCC_IC15CFGR_IC15INT,
2341 PeriphClkInit->ICSelection[RCC_IC15].ClockSelection | \
2342 ((PeriphClkInit->ICSelection[RCC_IC15].ClockDivider - 1U) << RCC_IC15CFGR_IC15INT_Pos));
2343
2344 LL_RCC_IC15_Enable();
2345 }
2346 else if (PeriphClkInit->UsbOtgHs2ClockSelection == RCC_USBOTGHS2CLKSOURCE_CLKP)
2347 {
2348 LL_RCC_CLKP_Enable();
2349 }
2350 else
2351 {
2352 /* No specific enable to do on other sources */
2353 }
2354
2355 /* Set the source of USBOTGHS2 clock */
2356 __HAL_RCC_USBOTGHS2_CONFIG(PeriphClkInit->UsbOtgHs2ClockSelection);
2357 }
2358
2359 /*------------------------------------ TIM configuration --------------------------------------*/
2360 if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
2361 {
2362 /* Check the parameters */
2363 assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
2364
2365 /* Configure Timer Prescaler */
2366 __HAL_RCC_TIMCLKPRESCALER_CONFIG(PeriphClkInit->TIMPresSelection);
2367 }
2368
2369 if (status == HAL_OK)
2370 {
2371 return HAL_OK;
2372 }
2373 return HAL_ERROR;
2374 }
2375
2376 /**
2377 * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
2378 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
2379 * returns the configuration information for the Extended Peripherals clocks :
2380 * (ADC, ADF1, CKPER, DCMI, DCMIPP, FDCAN, FMC, I2C1, I2C2, I2C3, I2C4, I3C1, I3C2,
2381 * LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LTDC, LPUART1, MDF1, PSSI, RTC, SAI1, SAI2,
2382 * SDMMC1, SDMMC2, SPDIFRX1, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, TIM,
2383 * USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8, UART9, USART10,
2384 * USBPHYC, USB OTGFS, XSPI1, XSPI2, XSPI3).
2385 * @retval None
2386 */
HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef * PeriphClkInit)2387 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
2388 {
2389 const __IO uint32_t *p_icxcfgr;
2390 uint32_t icx_val;
2391 /* Set all possible values for the extended clock type parameter------------*/
2392 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_CKPER | \
2393 RCC_PERIPHCLK_CSI | RCC_PERIPHCLK_DCMIPP | RCC_PERIPHCLK_ETH1 | \
2394 RCC_PERIPHCLK_ETH1PHY | RCC_PERIPHCLK_ETH1RX | RCC_PERIPHCLK_ETH1TX | \
2395 RCC_PERIPHCLK_ETH1PTP | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_FMC | \
2396 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
2397 RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_I3C2 | \
2398 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM3 | \
2399 RCC_PERIPHCLK_LPTIM4 | RCC_PERIPHCLK_LPTIM5 | RCC_PERIPHCLK_LTDC | \
2400 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_PSSI | \
2401 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
2402 RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SDMMC2 | RCC_PERIPHCLK_SPDIFRX1 | \
2403 RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \
2404 RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 | \
2405 RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
2406 RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
2407 RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 | RCC_PERIPHCLK_UART8 | \
2408 RCC_PERIPHCLK_UART9 | RCC_PERIPHCLK_USART10 | \
2409 RCC_PERIPHCLK_XSPI1 | RCC_PERIPHCLK_XSPI2 | RCC_PERIPHCLK_XSPI3 | \
2410 RCC_PERIPHCLK_USBPHY1 | RCC_PERIPHCLK_USBOTGHS1 | \
2411 RCC_PERIPHCLK_USBPHY2 | RCC_PERIPHCLK_USBOTGHS2;
2412
2413 /* Get IC x dividers */
2414 p_icxcfgr = &(RCC->IC1CFGR);
2415 for (uint32_t i = 0; i < 20U; i++)
2416 {
2417 icx_val = *p_icxcfgr;
2418 PeriphClkInit->ICSelection[i].ClockSelection = (icx_val & RCC_IC1CFGR_IC1SEL) >> RCC_IC1CFGR_IC1SEL_Pos;
2419 PeriphClkInit->ICSelection[i].ClockDivider = ((icx_val & RCC_IC1CFGR_IC1INT) >> RCC_IC1CFGR_IC1INT_Pos) + 1U;
2420 p_icxcfgr++;
2421 }
2422
2423 /* Get the ADC clock source ------------------------------------------------*/
2424 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
2425 /* Get the ADC divider ------------------------------------------------*/
2426 PeriphClkInit->AdcDivider = __HAL_RCC_GET_ADC_DIVIDER();
2427 /* Get the ADF1 clock source -----------------------------------------------*/
2428 PeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE();
2429 /* Get the CKPER clock source ----------------------------------------------*/
2430 PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE();
2431 /* Get the DCMIPP clock source ---------------------------------------------*/
2432 PeriphClkInit->DcmippClockSelection = __HAL_RCC_GET_DCMIPP_SOURCE();
2433 /* Get the ETH1 clock source -----------------------------------------------*/
2434 PeriphClkInit->Eth1ClockSelection = __HAL_RCC_GET_ETH1_SOURCE();
2435 /* Get the ETH1 PHY interface ----------------------------------------------*/
2436 PeriphClkInit->Eth1PhyInterfaceSelection = __HAL_RCC_GET_ETH1PHY_INTERFACE();
2437 /* Get the ETH1 RX clock source --------------------------------------------*/
2438 PeriphClkInit->Eth1RxClockSelection = __HAL_RCC_GET_ETH1RX_SOURCE();
2439 /* Get the ETH1 TX clock source --------------------------------------------*/
2440 PeriphClkInit->Eth1TxClockSelection = __HAL_RCC_GET_ETH1TX_SOURCE();
2441 /* Get the ETH1 PTP clock source -------------------------------------------*/
2442 PeriphClkInit->Eth1PtpClockSelection = __HAL_RCC_GET_ETH1PTP_SOURCE();
2443 /* Get the ETH1 PTP divider ------------------------------------------------*/
2444 PeriphClkInit->Eth1PtpDivider = __HAL_RCC_GET_ETH1PTP_DIVIDER();
2445 /* Get the FDCAN kernel clock source ---------------------------------------*/
2446 PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
2447 /* Get the FMC kernel clock source -----------------------------------------*/
2448 PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE();
2449 /* Get the I2C1 clock source -----------------------------------------------*/
2450 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
2451 /* Get the I2C2 clock source -----------------------------------------------*/
2452 PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
2453 /* Get the I2C3 clock source -----------------------------------------------*/
2454 PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
2455 /* Get the I2C4 clock source -----------------------------------------------*/
2456 PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
2457 /* Get the I3C1 clock source -----------------------------------------------*/
2458 PeriphClkInit->I3c1ClockSelection = __HAL_RCC_GET_I3C1_SOURCE();
2459 /* Get the I3C2 clock source -----------------------------------------------*/
2460 PeriphClkInit->I3c2ClockSelection = __HAL_RCC_GET_I3C2_SOURCE();
2461 /* Get the LPTIM1 clock source ---------------------------------------------*/
2462 PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
2463 /* Get the LPTIM2 clock source ---------------------------------------------*/
2464 PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
2465 /* Get the LPTIM3 clock source ---------------------------------------------*/
2466 PeriphClkInit->Lptim3ClockSelection = __HAL_RCC_GET_LPTIM3_SOURCE();
2467 /* Get the LPTIM4 clock source ---------------------------------------------*/
2468 PeriphClkInit->Lptim4ClockSelection = __HAL_RCC_GET_LPTIM4_SOURCE();
2469 /* Get the LPTIM5 clock source ---------------------------------------------*/
2470 PeriphClkInit->Lptim5ClockSelection = __HAL_RCC_GET_LPTIM5_SOURCE();
2471 /* Get the LPUART1 clock source --------------------------------------------*/
2472 PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
2473 /* Get the LTDC clock source -----------------------------------------------*/
2474 PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE();
2475 /* Get the MDF1 clock source -----------------------------------------------*/
2476 PeriphClkInit->Mdf1ClockSelection = __HAL_RCC_GET_MDF1_SOURCE();
2477 /* Get the PSSI clock source -----------------------------------------------*/
2478 PeriphClkInit->PssiClockSelection = __HAL_RCC_GET_PSSI_SOURCE();
2479 /* Get the RTC clock source ------------------------------------------------*/
2480 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
2481 /* Get the SAI1 clock source -----------------------------------------------*/
2482 PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
2483 /* Get the SAI2 clock source -----------------------------------------------*/
2484 PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
2485 /* Get the SDMMC1 clock source ---------------------------------------------*/
2486 PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
2487 /* Get the SDMMC2 clock source ---------------------------------------------*/
2488 PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
2489 /* Get the SPDIFRX1 clock source -------------------------------------------*/
2490 PeriphClkInit->Spdifrx1ClockSelection = __HAL_RCC_GET_SPDIFRX1_SOURCE();
2491 /* Get the SPI1 clock source -----------------------------------------------*/
2492 PeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE();
2493 /* Get the SPI2 clock source -----------------------------------------------*/
2494 PeriphClkInit->Spi2ClockSelection = __HAL_RCC_GET_SPI2_SOURCE();
2495 /* Get the SPI3 clock source -----------------------------------------------*/
2496 PeriphClkInit->Spi3ClockSelection = __HAL_RCC_GET_SPI3_SOURCE();
2497 /* Get the SPI4 clock source -----------------------------------------------*/
2498 PeriphClkInit->Spi4ClockSelection = __HAL_RCC_GET_SPI4_SOURCE();
2499 /* Get the SPI5 clock source -----------------------------------------------*/
2500 PeriphClkInit->Spi5ClockSelection = __HAL_RCC_GET_SPI5_SOURCE();
2501 /* Get the SPI6 clock source -----------------------------------------------*/
2502 PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE();
2503 /* Get the TIM Prescaler configuration -------------------------------------*/
2504 PeriphClkInit->TIMPresSelection = __HAL_RCC_GET_TIMCLKPRESCALER();
2505 /* Get the USART1 clock source ---------------------------------------------*/
2506 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
2507 /* Get the USART2 clock source ---------------------------------------------*/
2508 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
2509 /* Get the USART3 clock source ---------------------------------------------*/
2510 PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
2511 /* Get the UART4 clock source ----------------------------------------------*/
2512 PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
2513 /* Get the UART5 clock source ----------------------------------------------*/
2514 PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
2515 /* Get the USART6 clock source ---------------------------------------------*/
2516 PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
2517 /* Get the UART7 clock source ----------------------------------------------*/
2518 PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
2519 /* Get the UART8 clock source ----------------------------------------------*/
2520 PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
2521 /* Get the UART9 clock source ----------------------------------------------*/
2522 PeriphClkInit->Uart9ClockSelection = __HAL_RCC_GET_UART9_SOURCE();
2523 /* Get the USART10 clock source --------------------------------------------*/
2524 PeriphClkInit->Usart10ClockSelection = __HAL_RCC_GET_USART10_SOURCE();
2525 /* Get the USBPHY1 clock source --------------------------------------------*/
2526 PeriphClkInit->UsbPhy1ClockSelection = __HAL_RCC_GET_USBPHY1_SOURCE();
2527 /* Get the USB OTGHS1 clock source -----------------------------------------*/
2528 PeriphClkInit->UsbOtgHs1ClockSelection = __HAL_RCC_GET_USBOTGHS1_SOURCE();
2529 /* Get the USBPHY2 clock source --------------------------------------------*/
2530 PeriphClkInit->UsbPhy2ClockSelection = __HAL_RCC_GET_USBPHY2_SOURCE();
2531 /* Get the USB OTGHS2 clock source -----------------------------------------*/
2532 PeriphClkInit->UsbOtgHs2ClockSelection = __HAL_RCC_GET_USBOTGHS2_SOURCE();
2533 /* Get the XSPI1 clock source ----------------------------------------------*/
2534 PeriphClkInit->Xspi1ClockSelection = __HAL_RCC_GET_XSPI1_SOURCE();
2535 /* Get the XSPI2 clock source ----------------------------------------------*/
2536 PeriphClkInit->Xspi2ClockSelection = __HAL_RCC_GET_XSPI2_SOURCE();
2537 /* Get the XSPI3 clock source ----------------------------------------------*/
2538 PeriphClkInit->Xspi3ClockSelection = __HAL_RCC_GET_XSPI3_SOURCE();
2539 }
2540
2541 /**
2542 * @brief Return the peripheral clock frequency for a given peripheral (SAI..)
2543 * @note Return 0 if peripheral clock identifier not managed by this API or
2544 * if the selected clock source is not enabled (HSI, PLLs clock output..)
2545 * @param PeriphClk: Peripheral clock identifier
2546 * This parameter can be one of the following values:
2547 * @arg RCC_PERIPHCLK_ADC : ADC peripheral clock
2548 * @arg RCC_PERIPHCLK_ADF1 : ADF1 peripheral clock
2549 * @arg RCC_PERIPHCLK_CSI : CSI peripheral clock
2550 * @arg RCC_PERIPHCLK_DCMIPP : DCMIPP peripheral clock
2551 * @arg RCC_PERIPHCLK_I2C1 : I2C1 peripheral clock
2552 * @arg RCC_PERIPHCLK_I2C2 : I2C2 peripheral clock
2553 * @arg RCC_PERIPHCLK_I2C3 : I2C3 peripheral clock
2554 * @arg RCC_PERIPHCLK_I2C4 : I2C4 peripheral clock
2555 * @arg RCC_PERIPHCLK_I3C1 : I3C1 peripheral clock
2556 * @arg RCC_PERIPHCLK_I3C2 : I3C2 peripheral clock
2557 * @arg RCC_PERIPHCLK_FDCAN : FDCAN peripheral clock
2558 * @arg RCC_PERIPHCLK_FMC : FMC peripheral clock
2559 * @arg RCC_PERIPHCLK_LPTIM1 : LPTIM1 peripheral clock
2560 * @arg RCC_PERIPHCLK_LPTIM2 : LPTIM2 peripheral clock
2561 * @arg RCC_PERIPHCLK_LPTIM3 : LPTIM3 peripheral clock
2562 * @arg RCC_PERIPHCLK_LPTIM4 : LPTIM4 peripheral clock
2563 * @arg RCC_PERIPHCLK_LPTIM5 : LPTIM5 peripheral clock
2564 * @arg RCC_PERIPHCLK_LPUART1 : LPUART1 peripheral clock
2565 * @arg RCC_PERIPHCLK_LTDC : LTDC peripheral clock
2566 * @arg RCC_PERIPHCLK_MDF1 : MDF1 peripheral clock
2567 * @arg RCC_PERIPHCLK_PSSI : PSSI peripheral clock
2568 * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock
2569 * @arg RCC_PERIPHCLK_SAI2 : SAI2 peripheral clock
2570 * @arg RCC_PERIPHCLK_SDMMC1 : SDMMC1 peripheral clock
2571 * @arg RCC_PERIPHCLK_SDMMC2 : SDMMC2 peripheral clock
2572 * @arg RCC_PERIPHCLK_SPDIFRX1 : SPDIFRX1 peripheral clock
2573 * @arg RCC_PERIPHCLK_SPI1 : SPI1 peripheral clock
2574 * @arg RCC_PERIPHCLK_SPI2 : SPI2 peripheral clock
2575 * @arg RCC_PERIPHCLK_SPI3 : SPI3 peripheral clock
2576 * @arg RCC_PERIPHCLK_SPI4 : SPI4 peripheral clock
2577 * @arg RCC_PERIPHCLK_SPI5 : SPI5 peripheral clock
2578 * @arg RCC_PERIPHCLK_SPI6 : SPI6 peripheral clock
2579 * @arg RCC_PERIPHCLK_USART1 : USART1 peripheral clock
2580 * @arg RCC_PERIPHCLK_USART2 : USART2 peripheral clock
2581 * @arg RCC_PERIPHCLK_USART3 : USART3 peripheral clock
2582 * @arg RCC_PERIPHCLK_UART4 : UART4 peripheral clock
2583 * @arg RCC_PERIPHCLK_UART5 : UART5 peripheral clock
2584 * @arg RCC_PERIPHCLK_USART6 : USART6 peripheral clock
2585 * @arg RCC_PERIPHCLK_UART7 : UART7 peripheral clock
2586 * @arg RCC_PERIPHCLK_UART8 : UART8 peripheral clock
2587 * @arg RCC_PERIPHCLK_UART9 : UART9 peripheral clock
2588 * @arg RCC_PERIPHCLK_USART10 : USART10 peripheral clock
2589 * @arg RCC_PERIPHCLK_XSPI1 : XSPI1 peripheral clock
2590 * @arg RCC_PERIPHCLK_XSPI2 : XSPI2 peripheral clock
2591 * @arg RCC_PERIPHCLK_XSPI3 : XSPI3 peripheral clock
2592 * @retval Frequency in KHz
2593 */
HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)2594 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
2595 {
2596 uint32_t frequency = 0; /* Set to 0 for returned value if no source clock */
2597
2598 switch (PeriphClk)
2599 {
2600 case RCC_PERIPHCLK_ADC:
2601 frequency = RCCEx_GetADCCLKFreq(LL_RCC_ADC_CLKSOURCE);
2602 break;
2603
2604 case RCC_PERIPHCLK_ADF1:
2605 frequency = RCCEx_GetADFCLKFreq(LL_RCC_ADF1_CLKSOURCE);
2606 break;
2607
2608 case RCC_PERIPHCLK_CSI:
2609 frequency = RCCEx_GetCSICLKFreq();
2610 break;
2611
2612 case RCC_PERIPHCLK_CKPER:
2613 frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
2614 break;
2615
2616 case RCC_PERIPHCLK_DCMIPP:
2617 frequency = RCCEx_GetDCMIPPCLKFreq(LL_RCC_DCMIPP_CLKSOURCE);
2618 break;
2619
2620 case RCC_PERIPHCLK_ETH1:
2621 frequency = RCCEx_GetETH1CLKFreq(LL_RCC_ETH1_CLKSOURCE);
2622 break;
2623
2624 case RCC_PERIPHCLK_ETH1PTP:
2625 frequency = RCCEx_GetETH1PTPCLKFreq(LL_RCC_ETH1PTP_CLKSOURCE);
2626 break;
2627
2628 case RCC_PERIPHCLK_FDCAN:
2629 frequency = RCCEx_GetFDCANCLKFreq(LL_RCC_FDCAN_CLKSOURCE);
2630 break;
2631
2632 case RCC_PERIPHCLK_FMC:
2633 frequency = RCCEx_GetFMCCLKFreq(LL_RCC_FMC_CLKSOURCE);
2634 break;
2635
2636 case RCC_PERIPHCLK_I2C1:
2637 frequency = RCCEx_GetI2CCLKFreq(LL_RCC_I2C1_CLKSOURCE);
2638 break;
2639
2640 case RCC_PERIPHCLK_I2C2:
2641 frequency = RCCEx_GetI2CCLKFreq(LL_RCC_I2C2_CLKSOURCE);
2642 break;
2643
2644 case RCC_PERIPHCLK_I2C3:
2645 frequency = RCCEx_GetI2CCLKFreq(LL_RCC_I2C3_CLKSOURCE);
2646 break;
2647
2648 case RCC_PERIPHCLK_I2C4:
2649 frequency = RCCEx_GetI2CCLKFreq(LL_RCC_I2C4_CLKSOURCE);
2650 break;
2651
2652 case RCC_PERIPHCLK_I3C1:
2653 frequency = RCCEx_GetI3CCLKFreq(LL_RCC_I3C1_CLKSOURCE);
2654 break;
2655
2656 case RCC_PERIPHCLK_I3C2:
2657 frequency = RCCEx_GetI3CCLKFreq(LL_RCC_I3C2_CLKSOURCE);
2658 break;
2659
2660 case RCC_PERIPHCLK_LPTIM1:
2661 frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM1_CLKSOURCE);
2662 break;
2663
2664 case RCC_PERIPHCLK_LPTIM2:
2665 frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM2_CLKSOURCE);
2666 break;
2667
2668 case RCC_PERIPHCLK_LPTIM3:
2669 frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM3_CLKSOURCE);
2670 break;
2671
2672 case RCC_PERIPHCLK_LPTIM4:
2673 frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM4_CLKSOURCE);
2674 break;
2675
2676 case RCC_PERIPHCLK_LPTIM5:
2677 frequency = RCCEx_GetLPTIMCLKFreq(LL_RCC_LPTIM5_CLKSOURCE);
2678 break;
2679
2680 case RCC_PERIPHCLK_LPUART1:
2681 frequency = RCCEx_GetLPUARTCLKFreq(LL_RCC_LPUART1_CLKSOURCE);
2682 break;
2683
2684 case RCC_PERIPHCLK_LTDC:
2685 frequency = RCCEx_GetLTDCCLKFreq(LL_RCC_LTDC_CLKSOURCE);
2686 break;
2687
2688 case RCC_PERIPHCLK_MDF1:
2689 frequency = RCCEx_GetMDFCLKFreq(LL_RCC_MDF1_CLKSOURCE);
2690 break;
2691
2692 case RCC_PERIPHCLK_PSSI:
2693 frequency = RCCEx_GetPSSICLKFreq(LL_RCC_PSSI_CLKSOURCE);
2694 break;
2695
2696 case RCC_PERIPHCLK_RTC:
2697 frequency = RCCEx_GetRTCCLKFreq();
2698 break;
2699
2700 case RCC_PERIPHCLK_SAI1:
2701 frequency = RCCEx_GetSAICLKFreq(LL_RCC_SAI1_CLKSOURCE);
2702 break;
2703
2704 case RCC_PERIPHCLK_SAI2:
2705 frequency = RCCEx_GetSAICLKFreq(LL_RCC_SAI2_CLKSOURCE);
2706 break;
2707
2708 case RCC_PERIPHCLK_SDMMC1:
2709 frequency = RCCEx_GetSDMMCCLKFreq(LL_RCC_SDMMC1_CLKSOURCE);
2710 break;
2711
2712 case RCC_PERIPHCLK_SDMMC2:
2713 frequency = RCCEx_GetSDMMCCLKFreq(LL_RCC_SDMMC2_CLKSOURCE);
2714 break;
2715
2716 case RCC_PERIPHCLK_SPDIFRX1:
2717 frequency = RCCEx_GetSPDIFRXCLKFreq(LL_RCC_SPDIFRX1_CLKSOURCE);
2718 break;
2719
2720 case RCC_PERIPHCLK_SPI1:
2721 frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI1_CLKSOURCE);
2722 break;
2723
2724 case RCC_PERIPHCLK_SPI2:
2725 frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI2_CLKSOURCE);
2726 break;
2727
2728 case RCC_PERIPHCLK_SPI3:
2729 frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI3_CLKSOURCE);
2730 break;
2731
2732 case RCC_PERIPHCLK_SPI4:
2733 frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI4_CLKSOURCE);
2734 break;
2735
2736 case RCC_PERIPHCLK_SPI5:
2737 frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI5_CLKSOURCE);
2738 break;
2739
2740 case RCC_PERIPHCLK_SPI6:
2741 frequency = RCCEx_GetSPICLKFreq(LL_RCC_SPI6_CLKSOURCE);
2742 break;
2743
2744 case RCC_PERIPHCLK_USART1:
2745 frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART1_CLKSOURCE);
2746 break;
2747
2748 case RCC_PERIPHCLK_USART2:
2749 frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART2_CLKSOURCE);
2750 break;
2751
2752 case RCC_PERIPHCLK_USART3:
2753 frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART3_CLKSOURCE);
2754 break;
2755
2756 case RCC_PERIPHCLK_UART4:
2757 frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART4_CLKSOURCE);
2758 break;
2759
2760 case RCC_PERIPHCLK_UART5:
2761 frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART5_CLKSOURCE);
2762 break;
2763
2764 case RCC_PERIPHCLK_USART6:
2765 frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART6_CLKSOURCE);
2766 break;
2767
2768 case RCC_PERIPHCLK_UART7:
2769 frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART7_CLKSOURCE);
2770 break;
2771
2772 case RCC_PERIPHCLK_UART8:
2773 frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART8_CLKSOURCE);
2774 break;
2775
2776 case RCC_PERIPHCLK_UART9:
2777 frequency = RCCEx_GetUARTCLKFreq(LL_RCC_UART9_CLKSOURCE);
2778 break;
2779
2780 case RCC_PERIPHCLK_USART10:
2781 frequency = RCCEx_GetUSARTCLKFreq(LL_RCC_USART10_CLKSOURCE);
2782 break;
2783
2784 case RCC_PERIPHCLK_USBPHY1:
2785 frequency = RCCEx_GetOTGPHYCKREFCLKFreq(LL_RCC_OTGPHY1CKREF_CLKSOURCE);
2786 break;
2787
2788 case RCC_PERIPHCLK_USBOTGHS1:
2789 frequency = RCCEx_GetOTGPHYCLKFreq(LL_RCC_OTGPHY1_CLKSOURCE);
2790 break;
2791
2792 case RCC_PERIPHCLK_USBPHY2:
2793 frequency = RCCEx_GetOTGPHYCKREFCLKFreq(LL_RCC_OTGPHY2CKREF_CLKSOURCE);
2794 break;
2795
2796 case RCC_PERIPHCLK_USBOTGHS2:
2797 frequency = RCCEx_GetOTGPHYCLKFreq(LL_RCC_OTGPHY2_CLKSOURCE);
2798 break;
2799
2800 case RCC_PERIPHCLK_XSPI1:
2801 frequency = RCCEx_GetXSPICLKFreq(LL_RCC_XSPI1_CLKSOURCE);
2802 break;
2803
2804 case RCC_PERIPHCLK_XSPI2:
2805 frequency = RCCEx_GetXSPICLKFreq(LL_RCC_XSPI2_CLKSOURCE);
2806 break;
2807
2808 case RCC_PERIPHCLK_XSPI3:
2809 frequency = RCCEx_GetXSPICLKFreq(LL_RCC_XSPI3_CLKSOURCE);
2810 break;
2811
2812 default:
2813 /* Unexpected case, frequency is by default set to 0 */
2814 break;
2815 }
2816
2817 return frequency;
2818 }
2819
2820 /**
2821 * @brief Return PLL1 clock frequency
2822 * @note RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
2823 * @retval PLL1 output clock frequency
2824 */
HAL_RCCEx_GetPLL1CLKFreq(void)2825 uint32_t HAL_RCCEx_GetPLL1CLKFreq(void)
2826 {
2827 uint32_t plloutputfreq = RCC_PERIPH_FREQUENCY_NO;
2828 uint32_t divm;
2829
2830 /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
2831 SYSCLK = PLL_VCO / PLLP1 / PLLP2
2832 */
2833 if (LL_RCC_PLL1_IsReady() != 0U)
2834 {
2835 if (LL_RCC_PLL1P_IsEnabled() != 0U)
2836 {
2837 uint32_t pllinputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL1_GetSource());
2838
2839 if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO)
2840 {
2841 #if defined(USE_FPGA)
2842 /**** FPGA PLL input forced to 32MHz *****/
2843 pllinputfreq = RCC_PLL_SOURCE_FREQ;
2844 /*****************************************/
2845 #endif /* USE_FPGA */
2846 divm = LL_RCC_PLL1_GetM();
2847
2848 if (divm != 0U)
2849 {
2850 plloutputfreq = RCCEx_CalcPLLFreq(pllinputfreq, divm, LL_RCC_PLL1_GetN(), LL_RCC_PLL1_GetFRACN(), \
2851 LL_RCC_PLL1_GetP1(), LL_RCC_PLL1_GetP2());
2852 }
2853 }
2854 }
2855 }
2856 else if (LL_RCC_PLL1_IsEnabledBypass() != 0U)
2857 {
2858 plloutputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL1_GetSource());
2859 }
2860 else
2861 {
2862 /* Nothing to do */
2863 }
2864
2865 return plloutputfreq;
2866 }
2867
2868 /**
2869 * @brief Return PLL2 clock frequency
2870 * @note RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
2871 * @retval PLL2 output clock frequency
2872 */
HAL_RCCEx_GetPLL2CLKFreq(void)2873 uint32_t HAL_RCCEx_GetPLL2CLKFreq(void)
2874 {
2875 uint32_t plloutputfreq = RCC_PERIPH_FREQUENCY_NO;
2876 uint32_t divm;
2877
2878 /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
2879 SYSCLK = PLL_VCO / PLLP1 / PLLP2
2880 */
2881 if (LL_RCC_PLL2_IsReady() != 0U)
2882 {
2883 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2884 {
2885 uint32_t pllinputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL2_GetSource());
2886
2887 if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO)
2888 {
2889 #if defined(USE_FPGA)
2890 /**** FPGA PLL input forced to 32MHz *****/
2891 pllinputfreq = RCC_PLL_SOURCE_FREQ;
2892 /*****************************************/
2893 #endif /* USE_FPGA */
2894 divm = LL_RCC_PLL2_GetM();
2895
2896 if (divm != 0U)
2897 {
2898 plloutputfreq = RCCEx_CalcPLLFreq(pllinputfreq, divm, LL_RCC_PLL2_GetN(), LL_RCC_PLL2_GetFRACN(), \
2899 LL_RCC_PLL2_GetP1(), LL_RCC_PLL2_GetP2());
2900 }
2901 }
2902 }
2903 }
2904 else if (LL_RCC_PLL2_IsEnabledBypass() != 0U)
2905 {
2906 plloutputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL2_GetSource());
2907 }
2908 else
2909 {
2910 /* Nothing to do */
2911 }
2912
2913 return plloutputfreq;
2914 }
2915
2916 /**
2917 * @brief Return PLL3 clock frequency
2918 * @note RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
2919 * @retval PLL3 output clock frequency
2920 */
HAL_RCCEx_GetPLL3CLKFreq(void)2921 uint32_t HAL_RCCEx_GetPLL3CLKFreq(void)
2922 {
2923 uint32_t plloutputfreq = RCC_PERIPH_FREQUENCY_NO;
2924 uint32_t divm;
2925
2926 /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
2927 SYSCLK = PLL_VCO / PLLP1 / PLLP2
2928 */
2929 if (LL_RCC_PLL3_IsReady() != 0U)
2930 {
2931 if (LL_RCC_PLL3P_IsEnabled() != 0U)
2932 {
2933 uint32_t pllinputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL3_GetSource());
2934
2935 if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO)
2936 {
2937 #if defined(USE_FPGA)
2938 /**** FPGA PLL input forced to 32MHz *****/
2939 pllinputfreq = RCC_PLL_SOURCE_FREQ;
2940 /*****************************************/
2941 #endif /* USE_FPGA */
2942 divm = LL_RCC_PLL3_GetM();
2943
2944 if (divm != 0U)
2945 {
2946 plloutputfreq = RCCEx_CalcPLLFreq(pllinputfreq, divm, LL_RCC_PLL3_GetN(), LL_RCC_PLL3_GetFRACN(), \
2947 LL_RCC_PLL3_GetP1(), LL_RCC_PLL3_GetP2());
2948 }
2949 }
2950 }
2951 }
2952 else if (LL_RCC_PLL3_IsEnabledBypass() != 0U)
2953 {
2954 plloutputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL3_GetSource());
2955 }
2956 else
2957 {
2958 /* Nothing to do */
2959 }
2960
2961 return plloutputfreq;
2962 }
2963
2964 /**
2965 * @brief Return PLL4 clock frequency
2966 * @note RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
2967 * @retval PLL4 output clock frequency
2968 */
HAL_RCCEx_GetPLL4CLKFreq(void)2969 uint32_t HAL_RCCEx_GetPLL4CLKFreq(void)
2970 {
2971 uint32_t plloutputfreq = RCC_PERIPH_FREQUENCY_NO;
2972 uint32_t divm;
2973
2974 /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
2975 SYSCLK = PLL_VCO / PLLP1 / PLLP2
2976 */
2977 if (LL_RCC_PLL4_IsReady() != 0U)
2978 {
2979 if (LL_RCC_PLL4P_IsEnabled() != 0U)
2980 {
2981 uint32_t pllinputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL4_GetSource());
2982
2983 if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO)
2984 {
2985 #if defined(USE_FPGA)
2986 /**** FPGA PLL input forced to 32MHz *****/
2987 pllinputfreq = RCC_PLL_SOURCE_FREQ;
2988 /*****************************************/
2989 #endif /* USE_FPGA */
2990 divm = LL_RCC_PLL4_GetM();
2991
2992 if (divm != 0U)
2993 {
2994 plloutputfreq = RCCEx_CalcPLLFreq(pllinputfreq, divm, LL_RCC_PLL4_GetN(), LL_RCC_PLL4_GetFRACN(), \
2995 LL_RCC_PLL4_GetP1(), LL_RCC_PLL4_GetP2());
2996 }
2997 }
2998 }
2999 }
3000 else if (LL_RCC_PLL4_IsEnabledBypass() != 0U)
3001 {
3002 plloutputfreq = RCCEx_GetPLLSourceFreq(LL_RCC_PLL4_GetSource());
3003 }
3004 else
3005 {
3006 /* Nothing to do */
3007 }
3008
3009 return plloutputfreq;
3010 }
3011
3012 /**
3013 * @}
3014 */
3015
3016 /** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions
3017 * @brief Extended Peripheral Control functions
3018 * @{
3019 */
3020 /**
3021 * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock
3022 * @param WakeUpClk Wakeup clock
3023 * This parameter can be one of the following values:
3024 * @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI oscillator selection
3025 * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
3026 * @note This function shall not be called after the Clock Security System on HSE has been
3027 * enabled and the system clock is HSE or a switch on HSE is requested.
3028 * @retval None
3029 */
HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)3030 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
3031 {
3032 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
3033
3034 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
3035 }
3036
3037 /**
3038 * @brief Enable the LSE Clock Security System.
3039 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
3040 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
3041 * clock with HAL_RCCEx_PeriphCLKConfig().
3042 * @note Backup domain access should be enabled
3043 * @retval None
3044 */
HAL_RCCEx_EnableLSECSS(void)3045 void HAL_RCCEx_EnableLSECSS(void)
3046 {
3047 LL_RCC_LSE_EnableCSS();
3048 }
3049
3050 /**
3051 * @brief Disable the LSE Clock Security System.
3052 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
3053 * @note Backup domain access should be enabled
3054 * @retval None
3055 */
HAL_RCCEx_DisableLSECSS(void)3056 void HAL_RCCEx_DisableLSECSS(void)
3057 {
3058 /* Disable LSE CSS IT if any */
3059 __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
3060
3061 LL_RCC_LSE_DisableCSS();
3062 }
3063
3064 /**
3065 * @brief Enable the LSE Clock Security System Interrupt.
3066 * @note LSE Clock Security System Interrupt is mapped on EXTI line 65 which must be
3067 * enabled at application level to wake up from low power modes
3068 * @retval None
3069 */
HAL_RCCEx_EnableLSECSS_IT(void)3070 void HAL_RCCEx_EnableLSECSS_IT(void)
3071 {
3072 /* Enable LSE CSS IT */
3073 __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
3074
3075 LL_RCC_LSE_EnableCSS();
3076 }
3077
3078 /**
3079 * @brief Disable the LSE Clock Security System Interrupt.
3080 * @retval None
3081 */
HAL_RCCEx_DisableLSECSS_IT(void)3082 void HAL_RCCEx_DisableLSECSS_IT(void)
3083 {
3084 /* Disable LSE CSS IT */
3085 __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
3086
3087 LL_RCC_LSE_DisableCSS();
3088 }
3089
3090 /**
3091 * @brief Rearm the LSE Clock Security System
3092 * @note Allow to re-arm the LSE Clock Security System after a LSE failure detection
3093 * @retval None
3094 */
HAL_RCCEx_ReArmLSECSS(void)3095 void HAL_RCCEx_ReArmLSECSS(void)
3096 {
3097 LL_RCC_LSE_ReArmCSS();
3098 }
3099
3100 /**
3101 * @brief Handle the RCC LSE Clock Security System interrupt request.
3102 * @retval None
3103 */
HAL_RCCEx_LSECSS_IRQHandler(void)3104 void HAL_RCCEx_LSECSS_IRQHandler(void)
3105 {
3106 /* Check RCC LSE CSSF flag */
3107 if (__HAL_RCC_GET_IT(RCC_IT_LSECSS))
3108 {
3109 /* Clear RCC LSE CSS pending bit */
3110 __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
3111
3112 /* RCC LSE Clock Security System interrupt user callback */
3113 HAL_RCCEx_LSECSS_Callback();
3114 }
3115 }
3116
3117 /**
3118 * @brief RCCEx LSE Clock Security System interrupt callback.
3119 * @retval none
3120 */
HAL_RCCEx_LSECSS_Callback(void)3121 __weak void HAL_RCCEx_LSECSS_Callback(void)
3122 {
3123 /* NOTE : This function should not be modified, when the callback is needed,
3124 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
3125 */
3126 }
3127
3128 /**
3129 * @brief Configure the requested PLL to SSCG Mode
3130 * @param PLLnumber PLL number to configure.
3131 * This parameter can be one of the following values:
3132 * @ref RCC_PLL_Selection
3133 * @param pPLLInit Pointer to an RCC_PLLInitTypeDef structure that
3134 * contains the configuration parameters.
3135 * @param pPLLSSCGInit Pointer to an RCC_PLLSSCGInitTypeDef structure that
3136 * contains the configuration parameters specific to SSCG.
3137 * @note PLL is temporary disabled to apply new parameters
3138 *
3139 * @retval HAL status
3140 */
HAL_RCCEx_PLLSSCGConfig(uint32_t PLLnumber,const RCC_PLLInitTypeDef * pPLLInit,const RCC_PLLSSCGInitTypeDef * pPLLSSCGInit)3141 HAL_StatusTypeDef HAL_RCCEx_PLLSSCGConfig(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit,
3142 const RCC_PLLSSCGInitTypeDef *pPLLSSCGInit)
3143 {
3144 __IO uint32_t *p_rcc_pll_cfgr1_reg;
3145 __IO uint32_t *p_rcc_pll_cfgr2_reg;
3146 __IO uint32_t *p_rcc_pll_cfgr3_reg;
3147 HAL_StatusTypeDef ret = HAL_OK;
3148 uint32_t tickstart;
3149
3150 p_rcc_pll_cfgr1_reg = &(RCC->PLL1CFGR1) + (((uint32_t)0x4) * PLLnumber);
3151 p_rcc_pll_cfgr2_reg = &(RCC->PLL1CFGR2) + (((uint32_t)0x4) * PLLnumber);
3152 p_rcc_pll_cfgr3_reg = &(RCC->PLL1CFGR3) + (((uint32_t)0x4) * PLLnumber);
3153
3154 if (pPLLInit->PLLState == RCC_PLL_ON)
3155 {
3156 /* Check the parameters */
3157 assert_param(IS_RCC_PLLSOURCE(pPLLInit->PLLSource));
3158 assert_param(IS_RCC_PLLFRACN_VALUE(pPLLInit->PLLFractional));
3159 assert_param(IS_RCC_PLLM_VALUE(pPLLInit->PLLM));
3160 assert_param(IS_RCC_PLLN_VALUE(pPLLInit->PLLN));
3161 assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP1));
3162 assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP2));
3163 assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP2));
3164
3165 /* Ensure PLLx is disabled */
3166 WRITE_REG(RCC->CCR, RCC_CCR_PLL1ONC << PLLnumber);
3167
3168 /* Get Start Tick*/
3169 tickstart = HAL_GetTick();
3170
3171 /* Wait till PLLx is disabled */
3172 while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == (RCC_SR_PLL1RDY << PLLnumber))
3173 {
3174 if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE)
3175 {
3176 return HAL_TIMEOUT;
3177 }
3178 }
3179
3180 /* Ensure PLLxMODSSDIS='1' */
3181 SET_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1MODSSDIS);
3182
3183 /* Clear bypass mode */
3184 CLEAR_BIT(*p_rcc_pll_cfgr1_reg, RCC_PLL1CFGR1_PLL1BYP);
3185
3186 /* Configure the PLLx clock source, multiplication and division factors. */
3187 MODIFY_REG(*p_rcc_pll_cfgr1_reg, (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DIVN), \
3188 (pPLLInit->PLLSource | (pPLLInit->PLLM << RCC_PLL1CFGR1_PLL1DIVM_Pos) \
3189 | (pPLLInit->PLLN << RCC_PLL1CFGR1_PLL1DIVN_Pos)));
3190 MODIFY_REG(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2), \
3191 ((pPLLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos)));
3192
3193 /* Configure PLLx DIVNFRAC */
3194 MODIFY_REG(*p_rcc_pll_cfgr2_reg, RCC_PLL1CFGR2_PLL1DIVNFRAC, \
3195 pPLLInit->PLLFractional << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos);
3196
3197 /* Configure PLLx SSCG Parameters */
3198 MODIFY_REG(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODDIV | RCC_PLL1CFGR3_PLL1MODSPR | RCC_PLL1CFGR3_PLL1MODSPR), \
3199 ((pPLLSSCGInit->PLLModDiv << RCC_PLL1CFGR3_PLL1MODDIV_Pos) \
3200 | (pPLLSSCGInit->PLLModSpreadDepth << RCC_PLL1CFGR3_PLL1MODSPR_Pos)
3201 | (pPLLSSCGInit->PLLModSpreadMode << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos)));
3202
3203 /* Clear PLLxMODSSDIS, PLLxMODDSEN and DACEN to 0 */
3204 CLEAR_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1MODSSDIS | RCC_PLL1CFGR3_PLL1MODDSEN | RCC_PLL1CFGR3_PLL1DACEN);
3205
3206 /* Ensure PLLxMODSSRST='1' and Enable PLLx post divider output */
3207 SET_BIT(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODSSRST | RCC_PLL1CFGR3_PLL1PDIVEN));
3208
3209 /* Set PLLxMODDSEN and DACEN */
3210 SET_BIT(*p_rcc_pll_cfgr3_reg, (RCC_PLL1CFGR3_PLL1MODDSEN | RCC_PLL1CFGR3_PLL1DACEN));
3211
3212 /* Enable the PLLx */
3213 WRITE_REG(RCC->CSR, RCC_CSR_PLL1ONS << PLLnumber);
3214
3215 /* Get Start Tick*/
3216 tickstart = HAL_GetTick();
3217
3218 /* Wait till PLLx is ready */
3219 while (READ_BIT(RCC->SR, (RCC_SR_PLL1RDY << PLLnumber)) == 0U)
3220 {
3221 if ((HAL_GetTick() - tickstart) > RCC_PLL_TIMEOUT_VALUE)
3222 {
3223 return HAL_TIMEOUT;
3224 }
3225 }
3226
3227 /* When PLL is Ready, deassert the PLLxMODSSRST */
3228 CLEAR_BIT(*p_rcc_pll_cfgr3_reg, RCC_PLL1CFGR3_PLL1MODSSRST);
3229 }
3230 else if (pPLLInit->PLLState == RCC_PLL_BYPASS)
3231 {
3232 ret = HAL_ERROR;
3233 }
3234 else
3235 {
3236 /* other states are not managed this function */
3237 }
3238
3239 return ret;
3240 }
3241 /**
3242 * @}
3243 */
3244
3245 /**
3246 * @}
3247 */
3248
3249 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
3250 * @{
3251 */
3252
3253 /**
3254 * @brief Return HCLK clock frequency
3255 * @param SYSCLK_Frequency SYSCLK clock frequency
3256 * @retval HCLK clock frequency (in Hz)
3257 */
RCCEx_GetHCLKFreq(uint32_t SYSCLK_Frequency)3258 static uint32_t RCCEx_GetHCLKFreq(uint32_t SYSCLK_Frequency)
3259 {
3260 /* HCLK clock frequency */
3261 return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
3262 }
3263
3264 /**
3265 * @brief Return PCLK1 clock frequency
3266 * @param HCLK_Frequency HCLK clock frequency
3267 * @retval PCLK1 clock frequency (in Hz)
3268 */
RCCEx_GetPCLK1Freq(uint32_t HCLK_Frequency)3269 static uint32_t RCCEx_GetPCLK1Freq(uint32_t HCLK_Frequency)
3270 {
3271 /* PCLK1 clock frequency */
3272 return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
3273 }
3274
3275 /**
3276 * @brief Return PCLK2 clock frequency
3277 * @param HCLK_Frequency HCLK clock frequency
3278 * @retval PCLK2 clock frequency (in Hz)
3279 */
RCCEx_GetPCLK2Freq(uint32_t HCLK_Frequency)3280 static uint32_t RCCEx_GetPCLK2Freq(uint32_t HCLK_Frequency)
3281 {
3282 /* PCLK2 clock frequency */
3283 return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
3284 }
3285
3286 /**
3287 * @brief Return PCLK4 clock frequency
3288 * @param HCLK_Frequency HCLK clock frequency
3289 * @retval PCLK4 clock frequency (in Hz)
3290 */
RCCEx_GetPCLK4Freq(uint32_t HCLK_Frequency)3291 static uint32_t RCCEx_GetPCLK4Freq(uint32_t HCLK_Frequency)
3292 {
3293 /* PCLK4 clock frequency */
3294 return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
3295 }
3296
3297 /**
3298 * @brief Return PCLK5 clock frequency
3299 * @param HCLK_Frequency HCLK clock frequency
3300 * @retval PCLK5 clock frequency (in Hz)
3301 */
RCCEx_GetPCLK5Freq(uint32_t HCLK_Frequency)3302 static uint32_t RCCEx_GetPCLK5Freq(uint32_t HCLK_Frequency)
3303 {
3304 /* PCLK5 clock frequency */
3305 return LL_RCC_CALC_PCLK5_FREQ(HCLK_Frequency, LL_RCC_GetAPB5Prescaler());
3306 }
3307
3308 /**
3309 * @brief Return PLL source clock frequency
3310 * @param PLLsource PLL source clock
3311 * @retval PLL source clock frequency (in Hz)
3312 */
RCCEx_GetPLLSourceFreq(uint32_t PLLsource)3313 static uint32_t RCCEx_GetPLLSourceFreq(uint32_t PLLsource)
3314 {
3315 uint32_t pllinputfreq = RCC_PERIPH_FREQUENCY_NO;
3316
3317 switch (PLLsource)
3318 {
3319 case LL_RCC_PLLSOURCE_HSI:
3320 if (LL_RCC_HSI_IsReady() != 0U)
3321 {
3322 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
3323 }
3324 break;
3325
3326 case LL_RCC_PLLSOURCE_MSI:
3327 if (LL_RCC_MSI_IsReady() != 0U)
3328 {
3329 if (LL_RCC_MSI_GetFrequency() == LL_RCC_MSI_FREQ_4MHZ)
3330 {
3331 pllinputfreq = MSI_VALUE;
3332 }
3333 else
3334 {
3335 pllinputfreq = 16000000UL;
3336 }
3337 }
3338 break;
3339
3340 case LL_RCC_PLLSOURCE_HSE:
3341 if (LL_RCC_HSE_IsReady() != 0U)
3342 {
3343 pllinputfreq = HSE_VALUE;
3344 }
3345 break;
3346
3347 case LL_RCC_PLLSOURCE_I2S_CKIN:
3348 pllinputfreq = EXTERNAL_CLOCK_VALUE;
3349 break;
3350
3351 default:
3352 /* unexpected case */
3353 break;
3354 }
3355
3356 return pllinputfreq;
3357 }
3358
3359 /**
3360 * @brief Calculate the PLL frequency output when used in integer or fractional mode
3361 * @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/MSI)
3362 * @param M Between 1 and 63
3363 * @param N Between 16 and 640 in integer mode, 20 to 320 in fractional mode
3364 * @param FRACN 0 in integer mode, between 0 and 0xFFFFFF in fractional mode
3365 * @param P1 VCO output divider P1 between 1 and 7
3366 * @param P2 VCO output divider P2 between 1 and 7
3367 * @retval PLL clock frequency (in Hz)
3368 */
RCCEx_CalcPLLFreq(uint32_t PLLInputFreq,uint32_t M,uint32_t N,uint32_t FRACN,uint32_t P1,uint32_t P2)3369 static uint32_t RCCEx_CalcPLLFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t P1,
3370 uint32_t P2)
3371 {
3372 float_t freq;
3373
3374 freq = ((float_t)PLLInputFreq * ((float_t)N + ((float_t)FRACN / (float_t)0x1000000))) / (float_t)M;
3375
3376 freq = freq / (float_t)P1;
3377 freq = freq / (float_t)P2;
3378
3379 return (uint32_t)freq;
3380 }
3381
3382 /**
3383 * @brief Return ADC clock frequency
3384 * @param ADCxSource This parameter can be one of the following values:
3385 * @arg @ref RCCEx_ADC_Clock_Source
3386 * @retval ADC clock frequency (in Hz)
3387 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
3388 */
RCCEx_GetADCCLKFreq(uint32_t ADCxSource)3389 static uint32_t RCCEx_GetADCCLKFreq(uint32_t ADCxSource)
3390 {
3391 uint32_t adc_frequency = RCC_PERIPH_FREQUENCY_NO;
3392 uint32_t ic_divider;
3393
3394 switch (LL_RCC_GetADCClockSource(ADCxSource))
3395 {
3396 case LL_RCC_ADC_CLKSOURCE_HCLK:
3397 adc_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
3398 break;
3399
3400 case LL_RCC_ADC_CLKSOURCE_CLKP:
3401 adc_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
3402 break;
3403
3404 case LL_RCC_ADC_CLKSOURCE_IC7:
3405 if (LL_RCC_IC7_IsEnabled() != 0U)
3406 {
3407 ic_divider = LL_RCC_IC7_GetDivider();
3408 switch (LL_RCC_IC7_GetSource())
3409 {
3410 case LL_RCC_ICCLKSOURCE_PLL1:
3411 adc_frequency = HAL_RCCEx_GetPLL1CLKFreq();
3412 adc_frequency = adc_frequency / ic_divider;
3413 break;
3414 case LL_RCC_ICCLKSOURCE_PLL2:
3415 adc_frequency = HAL_RCCEx_GetPLL2CLKFreq();
3416 adc_frequency = adc_frequency / ic_divider;
3417 break;
3418 case LL_RCC_ICCLKSOURCE_PLL3:
3419 adc_frequency = HAL_RCCEx_GetPLL3CLKFreq();
3420 adc_frequency = adc_frequency / ic_divider;
3421 break;
3422 case LL_RCC_ICCLKSOURCE_PLL4:
3423 adc_frequency = HAL_RCCEx_GetPLL4CLKFreq();
3424 adc_frequency = adc_frequency / ic_divider;
3425 break;
3426 default:
3427 /* Unexpected case */
3428 break;
3429 }
3430 }
3431 break;
3432
3433 case LL_RCC_ADC_CLKSOURCE_IC8:
3434 if (LL_RCC_IC8_IsEnabled() != 0U)
3435 {
3436 ic_divider = LL_RCC_IC8_GetDivider();
3437 switch (LL_RCC_IC8_GetSource())
3438 {
3439 case LL_RCC_ICCLKSOURCE_PLL1:
3440 adc_frequency = HAL_RCCEx_GetPLL1CLKFreq();
3441 adc_frequency = adc_frequency / ic_divider;
3442 break;
3443 case LL_RCC_ICCLKSOURCE_PLL2:
3444 adc_frequency = HAL_RCCEx_GetPLL2CLKFreq();
3445 adc_frequency = adc_frequency / ic_divider;
3446 break;
3447 case LL_RCC_ICCLKSOURCE_PLL3:
3448 adc_frequency = HAL_RCCEx_GetPLL3CLKFreq();
3449 adc_frequency = adc_frequency / ic_divider;
3450 break;
3451 case LL_RCC_ICCLKSOURCE_PLL4:
3452 adc_frequency = HAL_RCCEx_GetPLL4CLKFreq();
3453 adc_frequency = adc_frequency / ic_divider;
3454 break;
3455 default:
3456 /* Unexpected case */
3457 break;
3458 }
3459 }
3460 break;
3461
3462 case LL_RCC_ADC_CLKSOURCE_HSI:
3463 if (LL_RCC_HSI_IsReady() != 0U)
3464 {
3465 adc_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
3466 }
3467 break;
3468
3469 case LL_RCC_ADC_CLKSOURCE_MSI:
3470 if (LL_RCC_MSI_IsReady() != 0U)
3471 {
3472 adc_frequency = MSI_VALUE;
3473 }
3474 break;
3475
3476 case LL_RCC_ADC_CLKSOURCE_I2S_CKIN:
3477 adc_frequency = EXTERNAL_CLOCK_VALUE;
3478 break;
3479
3480 case LL_RCC_ADC_CLKSOURCE_TIMG:
3481 adc_frequency = HAL_RCC_GetSysClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
3482 break;
3483
3484 default:
3485 /* Unexpected case */
3486 break;
3487 }
3488
3489 return (adc_frequency / __HAL_RCC_GET_ADC_DIVIDER());
3490 }
3491
3492 /**
3493 * @brief Return ADFx clock frequency
3494 * @param ADFxSource This parameter can be one of the following values:
3495 * @arg @ref RCCEx_ADF1_Clock_Source
3496 * @retval ADF clock frequency (in Hz)
3497 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
3498 */
RCCEx_GetADFCLKFreq(uint32_t ADFxSource)3499 static uint32_t RCCEx_GetADFCLKFreq(uint32_t ADFxSource)
3500 {
3501 uint32_t adf_frequency = RCC_PERIPH_FREQUENCY_NO;
3502 uint32_t ic_divider;
3503
3504 switch (LL_RCC_GetADFClockSource(ADFxSource))
3505 {
3506 case LL_RCC_ADF1_CLKSOURCE_HCLK:
3507 adf_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
3508 break;
3509
3510 case LL_RCC_ADF1_CLKSOURCE_CLKP:
3511 adf_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
3512 break;
3513
3514 case LL_RCC_ADF1_CLKSOURCE_IC7:
3515 if (LL_RCC_IC7_IsEnabled() != 0U)
3516 {
3517 ic_divider = LL_RCC_IC7_GetDivider();
3518 switch (LL_RCC_IC7_GetSource())
3519 {
3520 case LL_RCC_ICCLKSOURCE_PLL1:
3521 adf_frequency = HAL_RCCEx_GetPLL1CLKFreq();
3522 adf_frequency = adf_frequency / ic_divider;
3523 break;
3524 case LL_RCC_ICCLKSOURCE_PLL2:
3525 adf_frequency = HAL_RCCEx_GetPLL2CLKFreq();
3526 adf_frequency = adf_frequency / ic_divider;
3527 break;
3528 case LL_RCC_ICCLKSOURCE_PLL3:
3529 adf_frequency = HAL_RCCEx_GetPLL3CLKFreq();
3530 adf_frequency = adf_frequency / ic_divider;
3531 break;
3532 case LL_RCC_ICCLKSOURCE_PLL4:
3533 adf_frequency = HAL_RCCEx_GetPLL4CLKFreq();
3534 adf_frequency = adf_frequency / ic_divider;
3535 break;
3536 default:
3537 /* Unexpected case */
3538 break;
3539 }
3540 }
3541 break;
3542
3543 case LL_RCC_ADF1_CLKSOURCE_IC8:
3544 if (LL_RCC_IC8_IsEnabled() != 0U)
3545 {
3546 ic_divider = LL_RCC_IC8_GetDivider();
3547 switch (LL_RCC_IC8_GetSource())
3548 {
3549 case LL_RCC_ICCLKSOURCE_PLL1:
3550 adf_frequency = HAL_RCCEx_GetPLL1CLKFreq();
3551 adf_frequency = adf_frequency / ic_divider;
3552 break;
3553 case LL_RCC_ICCLKSOURCE_PLL2:
3554 adf_frequency = HAL_RCCEx_GetPLL2CLKFreq();
3555 adf_frequency = adf_frequency / ic_divider;
3556 break;
3557 case LL_RCC_ICCLKSOURCE_PLL3:
3558 adf_frequency = HAL_RCCEx_GetPLL3CLKFreq();
3559 adf_frequency = adf_frequency / ic_divider;
3560 break;
3561 case LL_RCC_ICCLKSOURCE_PLL4:
3562 adf_frequency = HAL_RCCEx_GetPLL4CLKFreq();
3563 adf_frequency = adf_frequency / ic_divider;
3564 break;
3565 default:
3566 /* Unexpected case */
3567 break;
3568 }
3569 }
3570 break;
3571
3572 case LL_RCC_ADF1_CLKSOURCE_HSI:
3573 if (LL_RCC_HSI_IsReady() != 0U)
3574 {
3575 adf_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
3576 }
3577 break;
3578
3579 case LL_RCC_ADF1_CLKSOURCE_MSI:
3580 if (LL_RCC_MSI_IsReady() != 0U)
3581 {
3582 adf_frequency = MSI_VALUE;
3583 }
3584 break;
3585
3586 case LL_RCC_ADF1_CLKSOURCE_I2S_CKIN:
3587 adf_frequency = EXTERNAL_CLOCK_VALUE;
3588 break;
3589
3590 case LL_RCC_ADF1_CLKSOURCE_TIMG:
3591 adf_frequency = HAL_RCC_GetSysClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
3592 break;
3593
3594 default:
3595 /* Unexpected case */
3596 break;
3597 }
3598
3599 return adf_frequency;
3600 }
3601
3602 /**
3603 * @brief Return CLKP clock frequency
3604 * @param CLKPxSource This parameter can be one of the following values:
3605 * @arg @ref RCCEx_CLKP_Clock_Source
3606 * @retval CLKP clock frequency (in Hz)
3607 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
3608 */
RCCEx_GetCLKPCLKFreq(uint32_t CLKPxSource)3609 static uint32_t RCCEx_GetCLKPCLKFreq(uint32_t CLKPxSource)
3610 {
3611 uint32_t clkp_frequency = RCC_PERIPH_FREQUENCY_NO;
3612 uint32_t ic_divider;
3613
3614 if (LL_RCC_CLKP_IsEnabled() == 1U)
3615 {
3616 switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
3617 {
3618 case LL_RCC_CLKP_CLKSOURCE_HSI:
3619 if (LL_RCC_HSI_IsReady() != 0U)
3620 {
3621 clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
3622 }
3623 break;
3624
3625 case LL_RCC_CLKP_CLKSOURCE_MSI:
3626 if (LL_RCC_MSI_IsReady() != 0U)
3627 {
3628 clkp_frequency = MSI_VALUE;
3629 }
3630 break;
3631
3632 case LL_RCC_CLKP_CLKSOURCE_HSE:
3633 if (LL_RCC_HSE_IsReady() != 0U)
3634 {
3635 clkp_frequency = HSE_VALUE;
3636 }
3637 break;
3638
3639 case LL_RCC_CLKP_CLKSOURCE_IC5:
3640 if (LL_RCC_IC5_IsEnabled() != 0U)
3641 {
3642 ic_divider = LL_RCC_IC5_GetDivider();
3643 switch (LL_RCC_IC5_GetSource())
3644 {
3645 case LL_RCC_ICCLKSOURCE_PLL1:
3646 clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
3647 clkp_frequency = clkp_frequency / ic_divider;
3648 break;
3649 case LL_RCC_ICCLKSOURCE_PLL2:
3650 clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
3651 clkp_frequency = clkp_frequency / ic_divider;
3652 break;
3653 case LL_RCC_ICCLKSOURCE_PLL3:
3654 clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
3655 clkp_frequency = clkp_frequency / ic_divider;
3656 break;
3657 case LL_RCC_ICCLKSOURCE_PLL4:
3658 clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
3659 clkp_frequency = clkp_frequency / ic_divider;
3660 break;
3661 default:
3662 /* Unexpected case */
3663 break;
3664 }
3665 }
3666 break;
3667
3668 case LL_RCC_CLKP_CLKSOURCE_IC10:
3669 if (LL_RCC_IC10_IsEnabled() != 0U)
3670 {
3671 ic_divider = LL_RCC_IC10_GetDivider();
3672 switch (LL_RCC_IC10_GetSource())
3673 {
3674 case LL_RCC_ICCLKSOURCE_PLL1:
3675 clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
3676 clkp_frequency = clkp_frequency / ic_divider;
3677 break;
3678 case LL_RCC_ICCLKSOURCE_PLL2:
3679 clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
3680 clkp_frequency = clkp_frequency / ic_divider;
3681 break;
3682 case LL_RCC_ICCLKSOURCE_PLL3:
3683 clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
3684 clkp_frequency = clkp_frequency / ic_divider;
3685 break;
3686 case LL_RCC_ICCLKSOURCE_PLL4:
3687 clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
3688 clkp_frequency = clkp_frequency / ic_divider;
3689 break;
3690 default:
3691 /* Unexpected case */
3692 break;
3693 }
3694 }
3695 break;
3696
3697 case LL_RCC_CLKP_CLKSOURCE_IC15:
3698 if (LL_RCC_IC15_IsEnabled() != 0U)
3699 {
3700 ic_divider = LL_RCC_IC15_GetDivider();
3701 switch (LL_RCC_IC15_GetSource())
3702 {
3703 case LL_RCC_ICCLKSOURCE_PLL1:
3704 clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
3705 clkp_frequency = clkp_frequency / ic_divider;
3706 break;
3707 case LL_RCC_ICCLKSOURCE_PLL2:
3708 clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
3709 clkp_frequency = clkp_frequency / ic_divider;
3710 break;
3711 case LL_RCC_ICCLKSOURCE_PLL3:
3712 clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
3713 clkp_frequency = clkp_frequency / ic_divider;
3714 break;
3715 case LL_RCC_ICCLKSOURCE_PLL4:
3716 clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
3717 clkp_frequency = clkp_frequency / ic_divider;
3718 break;
3719 default:
3720 /* Unexpected case */
3721 break;
3722 }
3723 }
3724 break;
3725
3726 case LL_RCC_CLKP_CLKSOURCE_IC19:
3727 if (LL_RCC_IC19_IsEnabled() != 0U)
3728 {
3729 ic_divider = LL_RCC_IC19_GetDivider();
3730 switch (LL_RCC_IC19_GetSource())
3731 {
3732 case LL_RCC_ICCLKSOURCE_PLL1:
3733 clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
3734 clkp_frequency = clkp_frequency / ic_divider;
3735 break;
3736 case LL_RCC_ICCLKSOURCE_PLL2:
3737 clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
3738 clkp_frequency = clkp_frequency / ic_divider;
3739 break;
3740 case LL_RCC_ICCLKSOURCE_PLL3:
3741 clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
3742 clkp_frequency = clkp_frequency / ic_divider;
3743 break;
3744 case LL_RCC_ICCLKSOURCE_PLL4:
3745 clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
3746 clkp_frequency = clkp_frequency / ic_divider;
3747 break;
3748 default:
3749 /* Unexpected case */
3750 break;
3751 }
3752 }
3753 break;
3754
3755 case LL_RCC_CLKP_CLKSOURCE_IC20:
3756 if (LL_RCC_IC20_IsEnabled() != 0U)
3757 {
3758 ic_divider = LL_RCC_IC20_GetDivider();
3759 switch (LL_RCC_IC20_GetSource())
3760 {
3761 case LL_RCC_ICCLKSOURCE_PLL1:
3762 clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
3763 clkp_frequency = clkp_frequency / ic_divider;
3764 break;
3765 case LL_RCC_ICCLKSOURCE_PLL2:
3766 clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
3767 clkp_frequency = clkp_frequency / ic_divider;
3768 break;
3769 case LL_RCC_ICCLKSOURCE_PLL3:
3770 clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
3771 clkp_frequency = clkp_frequency / ic_divider;
3772 break;
3773 case LL_RCC_ICCLKSOURCE_PLL4:
3774 clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
3775 clkp_frequency = clkp_frequency / ic_divider;
3776 break;
3777 default:
3778 /* Unexpected case */
3779 break;
3780 }
3781 }
3782 break;
3783
3784 default:
3785 /* Unexpected case */
3786 break;
3787 }
3788 }
3789
3790 return clkp_frequency;
3791 }
3792
3793 /**
3794 * @brief Return CSI clock frequency
3795 * @retval CLKP clock frequency (in Hz)
3796 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
3797 */
RCCEx_GetCSICLKFreq(void)3798 static uint32_t RCCEx_GetCSICLKFreq(void)
3799 {
3800 uint32_t clkp_frequency = RCC_PERIPH_FREQUENCY_NO;
3801
3802 if (LL_RCC_IC18_IsEnabled() != 0U)
3803 {
3804 uint32_t ic_divider = LL_RCC_IC18_GetDivider();
3805 switch (LL_RCC_IC18_GetSource())
3806 {
3807 case LL_RCC_ICCLKSOURCE_PLL1:
3808 clkp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
3809 clkp_frequency = clkp_frequency / ic_divider;
3810 break;
3811 case LL_RCC_ICCLKSOURCE_PLL2:
3812 clkp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
3813 clkp_frequency = clkp_frequency / ic_divider;
3814 break;
3815 case LL_RCC_ICCLKSOURCE_PLL3:
3816 clkp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
3817 clkp_frequency = clkp_frequency / ic_divider;
3818 break;
3819 case LL_RCC_ICCLKSOURCE_PLL4:
3820 clkp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
3821 clkp_frequency = clkp_frequency / ic_divider;
3822 break;
3823 default:
3824 /* Unexpected case */
3825 break;
3826 }
3827 }
3828
3829 return clkp_frequency;
3830 }
3831
3832 /**
3833 * @brief Return DCMIPP clock frequency
3834 * @param DCMIPPxSource This parameter can be one of the following values:
3835 * @arg @ref RCCEx_DCMIPP_Clock_Source
3836 * @retval DCMIPP clock frequency (in Hz)
3837 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
3838 */
RCCEx_GetDCMIPPCLKFreq(uint32_t DCMIPPxSource)3839 static uint32_t RCCEx_GetDCMIPPCLKFreq(uint32_t DCMIPPxSource)
3840 {
3841 uint32_t dcmipp_frequency = RCC_PERIPH_FREQUENCY_NO;
3842 uint32_t ic_divider;
3843
3844 switch (LL_RCC_GetDCMIPPClockSource(DCMIPPxSource))
3845 {
3846 case LL_RCC_DCMIPP_CLKSOURCE_PCLK5:
3847 dcmipp_frequency = RCCEx_GetPCLK5Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
3848 break;
3849
3850 case LL_RCC_DCMIPP_CLKSOURCE_CLKP:
3851 dcmipp_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
3852 break;
3853
3854 case LL_RCC_DCMIPP_CLKSOURCE_IC17:
3855 if (LL_RCC_IC17_IsEnabled() != 0U)
3856 {
3857 ic_divider = LL_RCC_IC17_GetDivider();
3858 switch (LL_RCC_IC17_GetSource())
3859 {
3860 case LL_RCC_ICCLKSOURCE_PLL1:
3861 dcmipp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
3862 dcmipp_frequency = dcmipp_frequency / ic_divider;
3863 break;
3864 case LL_RCC_ICCLKSOURCE_PLL2:
3865 dcmipp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
3866 dcmipp_frequency = dcmipp_frequency / ic_divider;
3867 break;
3868 case LL_RCC_ICCLKSOURCE_PLL3:
3869 dcmipp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
3870 dcmipp_frequency = dcmipp_frequency / ic_divider;
3871 break;
3872 case LL_RCC_ICCLKSOURCE_PLL4:
3873 dcmipp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
3874 dcmipp_frequency = dcmipp_frequency / ic_divider;
3875 break;
3876 default:
3877 /* Unexpected case */
3878 break;
3879 }
3880 }
3881 break;
3882
3883 case LL_RCC_DCMIPP_CLKSOURCE_HSI:
3884 if (LL_RCC_HSI_IsReady() != 0U)
3885 {
3886 dcmipp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
3887 }
3888 break;
3889
3890 default:
3891 /* Unexpected case */
3892 break;
3893 }
3894
3895 return dcmipp_frequency;
3896 }
3897
3898 /**
3899 * @brief Return ETH1 clock frequency
3900 * @param ETH1xSource This parameter can be one of the following values:
3901 * @arg @ref RCCEx_ETH1_Clock_Source
3902 * @retval ETH1 clock frequency (in Hz)
3903 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
3904 */
RCCEx_GetETH1CLKFreq(uint32_t ETH1xSource)3905 static uint32_t RCCEx_GetETH1CLKFreq(uint32_t ETH1xSource)
3906 {
3907 uint32_t eth1_frequency = RCC_PERIPH_FREQUENCY_NO;
3908 uint32_t ic_divider;
3909
3910 switch (LL_RCC_GetETHClockSource(ETH1xSource))
3911 {
3912 case LL_RCC_ETH1_CLKSOURCE_HCLK:
3913 eth1_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
3914 break;
3915
3916 case LL_RCC_ETH1_CLKSOURCE_CLKP:
3917 eth1_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
3918 break;
3919
3920 case LL_RCC_ETH1_CLKSOURCE_IC12:
3921 if (LL_RCC_IC12_IsEnabled() != 0U)
3922 {
3923 ic_divider = LL_RCC_IC12_GetDivider();
3924 switch (LL_RCC_IC12_GetSource())
3925 {
3926 case LL_RCC_ICCLKSOURCE_PLL1:
3927 eth1_frequency = HAL_RCCEx_GetPLL1CLKFreq();
3928 eth1_frequency = eth1_frequency / ic_divider;
3929 break;
3930 case LL_RCC_ICCLKSOURCE_PLL2:
3931 eth1_frequency = HAL_RCCEx_GetPLL2CLKFreq();
3932 eth1_frequency = eth1_frequency / ic_divider;
3933 break;
3934 case LL_RCC_ICCLKSOURCE_PLL3:
3935 eth1_frequency = HAL_RCCEx_GetPLL3CLKFreq();
3936 eth1_frequency = eth1_frequency / ic_divider;
3937 break;
3938 case LL_RCC_ICCLKSOURCE_PLL4:
3939 eth1_frequency = HAL_RCCEx_GetPLL4CLKFreq();
3940 eth1_frequency = eth1_frequency / ic_divider;
3941 break;
3942 default:
3943 /* Unexpected case */
3944 break;
3945 }
3946 }
3947 break;
3948
3949 case LL_RCC_ETH1_CLKSOURCE_HSE:
3950 if (LL_RCC_HSE_IsReady() != 0U)
3951 {
3952 eth1_frequency = HSE_VALUE;
3953 }
3954 break;
3955
3956 default:
3957 /* Unexpected case */
3958 break;
3959 }
3960
3961 return eth1_frequency;
3962 }
3963
3964 /**
3965 * @brief Return ETH1PTP clock frequency
3966 * @param ETH1PTPxSource This parameter can be one of the following values:
3967 * @arg @ref RCCEx_ETH1_PTP_Clock_Source
3968 * @retval ETH1PTP clock frequency (in Hz)
3969 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
3970 */
RCCEx_GetETH1PTPCLKFreq(uint32_t ETH1PTPxSource)3971 static uint32_t RCCEx_GetETH1PTPCLKFreq(uint32_t ETH1PTPxSource)
3972 {
3973 uint32_t eth1ptp_frequency = RCC_PERIPH_FREQUENCY_NO;
3974 uint32_t ic_divider;
3975
3976 switch (LL_RCC_GetETHPTPClockSource(ETH1PTPxSource))
3977 {
3978 case LL_RCC_ETH1PTP_CLKSOURCE_HCLK:
3979 eth1ptp_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
3980 break;
3981
3982 case LL_RCC_ETH1PTP_CLKSOURCE_CLKP:
3983 eth1ptp_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
3984 break;
3985
3986 case LL_RCC_ETH1PTP_CLKSOURCE_IC13:
3987 if (LL_RCC_IC13_IsEnabled() != 0U)
3988 {
3989 ic_divider = LL_RCC_IC13_GetDivider();
3990 switch (LL_RCC_IC13_GetSource())
3991 {
3992 case LL_RCC_ICCLKSOURCE_PLL1:
3993 eth1ptp_frequency = HAL_RCCEx_GetPLL1CLKFreq();
3994 eth1ptp_frequency = eth1ptp_frequency / ic_divider;
3995 break;
3996 case LL_RCC_ICCLKSOURCE_PLL2:
3997 eth1ptp_frequency = HAL_RCCEx_GetPLL2CLKFreq();
3998 eth1ptp_frequency = eth1ptp_frequency / ic_divider;
3999 break;
4000 case LL_RCC_ICCLKSOURCE_PLL3:
4001 eth1ptp_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4002 eth1ptp_frequency = eth1ptp_frequency / ic_divider;
4003 break;
4004 case LL_RCC_ICCLKSOURCE_PLL4:
4005 eth1ptp_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4006 eth1ptp_frequency = eth1ptp_frequency / ic_divider;
4007 break;
4008 default:
4009 /* Unexpected case */
4010 break;
4011 }
4012 }
4013 break;
4014
4015 case LL_RCC_ETH1PTP_CLKSOURCE_HSE:
4016 if (LL_RCC_HSE_IsReady() != 0U)
4017 {
4018 eth1ptp_frequency = HSE_VALUE;
4019 }
4020 break;
4021
4022 default:
4023 /* Unexpected case */
4024 break;
4025 }
4026
4027 return (eth1ptp_frequency / __HAL_RCC_GET_ETH1PTP_DIVIDER());
4028 }
4029
4030 /**
4031 * @brief Return FDCAN clock frequency
4032 * @param FDCANxSource This parameter can be one of the following values:
4033 * @arg @ref RCCEx_FDCAN_Clock_Source
4034 * @retval FDCAN clock frequency (in Hz)
4035 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
4036 */
RCCEx_GetFDCANCLKFreq(uint32_t FDCANxSource)4037 static uint32_t RCCEx_GetFDCANCLKFreq(uint32_t FDCANxSource)
4038 {
4039 uint32_t fdcan_frequency = RCC_PERIPH_FREQUENCY_NO;
4040 uint32_t ic_divider;
4041
4042 switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
4043 {
4044 case LL_RCC_FDCAN_CLKSOURCE_PCLK1:
4045 fdcan_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
4046 break;
4047
4048 case LL_RCC_FDCAN_CLKSOURCE_CLKP:
4049 fdcan_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
4050 break;
4051
4052 case LL_RCC_FDCAN_CLKSOURCE_IC19:
4053 if (LL_RCC_IC19_IsEnabled() != 0U)
4054 {
4055 ic_divider = LL_RCC_IC19_GetDivider();
4056 switch (LL_RCC_IC19_GetSource())
4057 {
4058 case LL_RCC_ICCLKSOURCE_PLL1:
4059 fdcan_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4060 fdcan_frequency = fdcan_frequency / ic_divider;
4061 break;
4062 case LL_RCC_ICCLKSOURCE_PLL2:
4063 fdcan_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4064 fdcan_frequency = fdcan_frequency / ic_divider;
4065 break;
4066 case LL_RCC_ICCLKSOURCE_PLL3:
4067 fdcan_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4068 fdcan_frequency = fdcan_frequency / ic_divider;
4069 break;
4070 case LL_RCC_ICCLKSOURCE_PLL4:
4071 fdcan_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4072 fdcan_frequency = fdcan_frequency / ic_divider;
4073 break;
4074 default:
4075 /* Unexpected case */
4076 break;
4077 }
4078 }
4079 break;
4080
4081 case LL_RCC_FDCAN_CLKSOURCE_HSE:
4082 if (LL_RCC_HSE_IsReady() != 0U)
4083 {
4084 fdcan_frequency = HSE_VALUE;
4085 }
4086 break;
4087
4088 default:
4089 /* Unexpected case */
4090 break;
4091 }
4092
4093 return fdcan_frequency;
4094 }
4095
4096 /**
4097 * @brief Return FMC clock frequency
4098 * @param FMCxSource This parameter can be one of the following values:
4099 * @arg @ref RCCEx_FMC_Clock_Source
4100 * @retval FMC clock frequency (in Hz)
4101 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
4102 */
RCCEx_GetFMCCLKFreq(uint32_t FMCxSource)4103 static uint32_t RCCEx_GetFMCCLKFreq(uint32_t FMCxSource)
4104 {
4105 uint32_t fmc_frequency = RCC_PERIPH_FREQUENCY_NO;
4106 uint32_t ic_divider;
4107
4108 switch (LL_RCC_GetFMCClockSource(FMCxSource))
4109 {
4110 case LL_RCC_FMC_CLKSOURCE_HCLK:
4111 fmc_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
4112 break;
4113
4114 case LL_RCC_FMC_CLKSOURCE_CLKP:
4115 fmc_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
4116 break;
4117
4118 case LL_RCC_FMC_CLKSOURCE_IC3:
4119 if (LL_RCC_IC3_IsEnabled() != 0U)
4120 {
4121 ic_divider = LL_RCC_IC3_GetDivider();
4122 switch (LL_RCC_IC3_GetSource())
4123 {
4124 case LL_RCC_ICCLKSOURCE_PLL1:
4125 fmc_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4126 fmc_frequency = fmc_frequency / ic_divider;
4127 break;
4128 case LL_RCC_ICCLKSOURCE_PLL2:
4129 fmc_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4130 fmc_frequency = fmc_frequency / ic_divider;
4131 break;
4132 case LL_RCC_ICCLKSOURCE_PLL3:
4133 fmc_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4134 fmc_frequency = fmc_frequency / ic_divider;
4135 break;
4136 case LL_RCC_ICCLKSOURCE_PLL4:
4137 fmc_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4138 fmc_frequency = fmc_frequency / ic_divider;
4139 break;
4140 default:
4141 /* Unexpected case */
4142 break;
4143 }
4144 }
4145 break;
4146
4147 case LL_RCC_FMC_CLKSOURCE_IC4:
4148 if (LL_RCC_IC4_IsEnabled() != 0U)
4149 {
4150 ic_divider = LL_RCC_IC4_GetDivider();
4151 switch (LL_RCC_IC4_GetSource())
4152 {
4153 case LL_RCC_ICCLKSOURCE_PLL1:
4154 fmc_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4155 fmc_frequency = fmc_frequency / ic_divider;
4156 break;
4157 case LL_RCC_ICCLKSOURCE_PLL2:
4158 fmc_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4159 fmc_frequency = fmc_frequency / ic_divider;
4160 break;
4161 case LL_RCC_ICCLKSOURCE_PLL3:
4162 fmc_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4163 fmc_frequency = fmc_frequency / ic_divider;
4164 break;
4165 case LL_RCC_ICCLKSOURCE_PLL4:
4166 fmc_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4167 fmc_frequency = fmc_frequency / ic_divider;
4168 break;
4169 default:
4170 /* Unexpected case */
4171 break;
4172 }
4173 }
4174 break;
4175
4176 default:
4177 /* Unexpected case */
4178 break;
4179 }
4180
4181 return fmc_frequency;
4182 }
4183
4184 /**
4185 * @brief Return I2Cx clock frequency
4186 * @param I2CxSource This parameter can be one of the following values:
4187 * @arg @ref RCCEx_I2C1_Clock_Source
4188 * @arg @ref RCCEx_I2C2_Clock_Source
4189 * @arg @ref RCCEx_I2C3_Clock_Source
4190 * @arg @ref RCCEx_I2C4_Clock_Source
4191 * @retval I2C clock frequency (in Hz)
4192 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
4193 */
RCCEx_GetI2CCLKFreq(uint32_t I2CxSource)4194 static uint32_t RCCEx_GetI2CCLKFreq(uint32_t I2CxSource)
4195 {
4196 uint32_t i2c_frequency = RCC_PERIPH_FREQUENCY_NO;
4197 uint32_t ic_divider;
4198
4199 switch (LL_RCC_GetI2CClockSource(I2CxSource))
4200 {
4201 case LL_RCC_I2C1_CLKSOURCE_PCLK1:
4202 case LL_RCC_I2C2_CLKSOURCE_PCLK1:
4203 case LL_RCC_I2C3_CLKSOURCE_PCLK1:
4204 case LL_RCC_I2C4_CLKSOURCE_PCLK1:
4205 i2c_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
4206 break;
4207
4208 case LL_RCC_I2C1_CLKSOURCE_CLKP:
4209 case LL_RCC_I2C2_CLKSOURCE_CLKP:
4210 case LL_RCC_I2C3_CLKSOURCE_CLKP:
4211 case LL_RCC_I2C4_CLKSOURCE_CLKP:
4212 i2c_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
4213 break;
4214
4215 case LL_RCC_I2C1_CLKSOURCE_IC10:
4216 case LL_RCC_I2C2_CLKSOURCE_IC10:
4217 case LL_RCC_I2C3_CLKSOURCE_IC10:
4218 case LL_RCC_I2C4_CLKSOURCE_IC10:
4219 if (LL_RCC_IC10_IsEnabled() != 0U)
4220 {
4221 ic_divider = LL_RCC_IC10_GetDivider();
4222 switch (LL_RCC_IC10_GetSource())
4223 {
4224 case LL_RCC_ICCLKSOURCE_PLL1:
4225 i2c_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4226 i2c_frequency = i2c_frequency / ic_divider;
4227 break;
4228 case LL_RCC_ICCLKSOURCE_PLL2:
4229 i2c_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4230 i2c_frequency = i2c_frequency / ic_divider;
4231 break;
4232 case LL_RCC_ICCLKSOURCE_PLL3:
4233 i2c_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4234 i2c_frequency = i2c_frequency / ic_divider;
4235 break;
4236 case LL_RCC_ICCLKSOURCE_PLL4:
4237 i2c_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4238 i2c_frequency = i2c_frequency / ic_divider;
4239 break;
4240 default:
4241 /* Unexpected case */
4242 break;
4243 }
4244 }
4245 break;
4246
4247 case LL_RCC_I2C1_CLKSOURCE_IC15:
4248 case LL_RCC_I2C2_CLKSOURCE_IC15:
4249 case LL_RCC_I2C3_CLKSOURCE_IC15:
4250 case LL_RCC_I2C4_CLKSOURCE_IC15:
4251 if (LL_RCC_IC15_IsEnabled() != 0U)
4252 {
4253 ic_divider = LL_RCC_IC15_GetDivider();
4254 switch (LL_RCC_IC15_GetSource())
4255 {
4256 case LL_RCC_ICCLKSOURCE_PLL1:
4257 i2c_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4258 i2c_frequency = i2c_frequency / ic_divider;
4259 break;
4260 case LL_RCC_ICCLKSOURCE_PLL2:
4261 i2c_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4262 i2c_frequency = i2c_frequency / ic_divider;
4263 break;
4264 case LL_RCC_ICCLKSOURCE_PLL3:
4265 i2c_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4266 i2c_frequency = i2c_frequency / ic_divider;
4267 break;
4268 case LL_RCC_ICCLKSOURCE_PLL4:
4269 i2c_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4270 i2c_frequency = i2c_frequency / ic_divider;
4271 break;
4272 default:
4273 /* Unexpected case */
4274 break;
4275 }
4276 }
4277 break;
4278
4279 case LL_RCC_I2C1_CLKSOURCE_HSI:
4280 case LL_RCC_I2C2_CLKSOURCE_HSI:
4281 case LL_RCC_I2C3_CLKSOURCE_HSI:
4282 case LL_RCC_I2C4_CLKSOURCE_HSI:
4283 if (LL_RCC_HSI_IsReady() != 0U)
4284 {
4285 i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
4286 }
4287 break;
4288
4289 case LL_RCC_I2C1_CLKSOURCE_MSI:
4290 case LL_RCC_I2C2_CLKSOURCE_MSI:
4291 case LL_RCC_I2C3_CLKSOURCE_MSI:
4292 case LL_RCC_I2C4_CLKSOURCE_MSI:
4293 if (LL_RCC_MSI_IsReady() != 0U)
4294 {
4295 i2c_frequency = MSI_VALUE;
4296 }
4297 break;
4298
4299 default:
4300 /* Unexpected case */
4301 break;
4302 }
4303
4304 return i2c_frequency;
4305 }
4306
4307 /**
4308 * @brief Return I3Cx clock frequency
4309 * @param I3CxSource This parameter can be one of the following values:
4310 * @arg @ref RCCEx_I3C1_Clock_Source
4311 * @arg @ref RCCEx_I3C2_Clock_Source
4312 * @retval I3C clock frequency (in Hz)
4313 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
4314 */
RCCEx_GetI3CCLKFreq(uint32_t I3CxSource)4315 static uint32_t RCCEx_GetI3CCLKFreq(uint32_t I3CxSource)
4316 {
4317 uint32_t i3c_frequency = RCC_PERIPH_FREQUENCY_NO;
4318 uint32_t ic_divider;
4319
4320 switch (LL_RCC_GetI3CClockSource(I3CxSource))
4321 {
4322 case LL_RCC_I3C1_CLKSOURCE_PCLK1:
4323 case LL_RCC_I3C2_CLKSOURCE_PCLK1:
4324 i3c_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
4325 break;
4326
4327 case LL_RCC_I3C1_CLKSOURCE_CLKP:
4328 case LL_RCC_I3C2_CLKSOURCE_CLKP:
4329 i3c_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
4330 break;
4331
4332 case LL_RCC_I3C1_CLKSOURCE_IC10:
4333 case LL_RCC_I3C2_CLKSOURCE_IC10:
4334 if (LL_RCC_IC10_IsEnabled() != 0U)
4335 {
4336 ic_divider = LL_RCC_IC10_GetDivider();
4337 switch (LL_RCC_IC10_GetSource())
4338 {
4339 case LL_RCC_ICCLKSOURCE_PLL1:
4340 i3c_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4341 i3c_frequency = i3c_frequency / ic_divider;
4342 break;
4343 case LL_RCC_ICCLKSOURCE_PLL2:
4344 i3c_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4345 i3c_frequency = i3c_frequency / ic_divider;
4346 break;
4347 case LL_RCC_ICCLKSOURCE_PLL3:
4348 i3c_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4349 i3c_frequency = i3c_frequency / ic_divider;
4350 break;
4351 case LL_RCC_ICCLKSOURCE_PLL4:
4352 i3c_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4353 i3c_frequency = i3c_frequency / ic_divider;
4354 break;
4355 default:
4356 /* Unexpected case */
4357 break;
4358 }
4359 }
4360 break;
4361
4362 case LL_RCC_I3C1_CLKSOURCE_IC15:
4363 case LL_RCC_I3C2_CLKSOURCE_IC15:
4364 if (LL_RCC_IC15_IsEnabled() != 0U)
4365 {
4366 ic_divider = LL_RCC_IC15_GetDivider();
4367 switch (LL_RCC_IC15_GetSource())
4368 {
4369 case LL_RCC_ICCLKSOURCE_PLL1:
4370 i3c_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4371 i3c_frequency = i3c_frequency / ic_divider;
4372 break;
4373 case LL_RCC_ICCLKSOURCE_PLL2:
4374 i3c_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4375 i3c_frequency = i3c_frequency / ic_divider;
4376 break;
4377 case LL_RCC_ICCLKSOURCE_PLL3:
4378 i3c_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4379 i3c_frequency = i3c_frequency / ic_divider;
4380 break;
4381 case LL_RCC_ICCLKSOURCE_PLL4:
4382 i3c_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4383 i3c_frequency = i3c_frequency / ic_divider;
4384 break;
4385 default:
4386 /* Unexpected case */
4387 break;
4388 }
4389 }
4390 break;
4391
4392 case LL_RCC_I3C1_CLKSOURCE_HSI:
4393 case LL_RCC_I3C2_CLKSOURCE_HSI:
4394 if (LL_RCC_HSI_IsReady() != 0U)
4395 {
4396 i3c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
4397 }
4398 break;
4399
4400 case LL_RCC_I3C1_CLKSOURCE_MSI:
4401 case LL_RCC_I3C2_CLKSOURCE_MSI:
4402 if (LL_RCC_MSI_IsReady() != 0U)
4403 {
4404 i3c_frequency = MSI_VALUE;
4405 }
4406 break;
4407
4408 default:
4409 /* Unexpected case */
4410 break;
4411 }
4412
4413 return i3c_frequency;
4414 }
4415
4416 /**
4417 * @brief Return LPTIMx clock frequency
4418 * @param LPTIMxSource This parameter can be one of the following values:
4419 * @arg @ref RCCEx_LPTIM1_Clock_Source
4420 * @arg @ref RCCEx_LPTIM2_Clock_Source
4421 * @arg @ref RCCEx_LPTIM3_Clock_Source
4422 * @arg @ref RCCEx_LPTIM4_Clock_Source
4423 * @arg @ref RCCEx_LPTIM5_Clock_Source
4424 * @retval LPTIM clock frequency (in Hz)
4425 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
4426 */
RCCEx_GetLPTIMCLKFreq(uint32_t LPTIMxSource)4427 static uint32_t RCCEx_GetLPTIMCLKFreq(uint32_t LPTIMxSource)
4428 {
4429 uint32_t lptim_frequency = RCC_PERIPH_FREQUENCY_NO;
4430 uint32_t ic_divider;
4431
4432 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
4433 {
4434 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
4435 lptim_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
4436 break;
4437
4438 case LL_RCC_LPTIM2_CLKSOURCE_PCLK4:
4439 case LL_RCC_LPTIM3_CLKSOURCE_PCLK4:
4440 case LL_RCC_LPTIM4_CLKSOURCE_PCLK4:
4441 case LL_RCC_LPTIM5_CLKSOURCE_PCLK4:
4442 lptim_frequency = RCCEx_GetPCLK4Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
4443 break;
4444
4445 case LL_RCC_LPTIM1_CLKSOURCE_CLKP:
4446 case LL_RCC_LPTIM2_CLKSOURCE_CLKP:
4447 case LL_RCC_LPTIM3_CLKSOURCE_CLKP:
4448 case LL_RCC_LPTIM4_CLKSOURCE_CLKP:
4449 case LL_RCC_LPTIM5_CLKSOURCE_CLKP:
4450 lptim_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
4451 break;
4452
4453 case LL_RCC_LPTIM1_CLKSOURCE_IC15:
4454 case LL_RCC_LPTIM2_CLKSOURCE_IC15:
4455 case LL_RCC_LPTIM3_CLKSOURCE_IC15:
4456 case LL_RCC_LPTIM4_CLKSOURCE_IC15:
4457 case LL_RCC_LPTIM5_CLKSOURCE_IC15:
4458 if (LL_RCC_IC15_IsEnabled() != 0U)
4459 {
4460 ic_divider = LL_RCC_IC15_GetDivider();
4461 switch (LL_RCC_IC15_GetSource())
4462 {
4463 case LL_RCC_ICCLKSOURCE_PLL1:
4464 lptim_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4465 lptim_frequency = lptim_frequency / ic_divider;
4466 break;
4467 case LL_RCC_ICCLKSOURCE_PLL2:
4468 lptim_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4469 lptim_frequency = lptim_frequency / ic_divider;
4470 break;
4471 case LL_RCC_ICCLKSOURCE_PLL3:
4472 lptim_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4473 lptim_frequency = lptim_frequency / ic_divider;
4474 break;
4475 case LL_RCC_ICCLKSOURCE_PLL4:
4476 lptim_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4477 lptim_frequency = lptim_frequency / ic_divider;
4478 break;
4479 default:
4480 /* Unexpected case */
4481 break;
4482 }
4483 }
4484 break;
4485
4486 case LL_RCC_LPTIM1_CLKSOURCE_LSE:
4487 case LL_RCC_LPTIM2_CLKSOURCE_LSE:
4488 case LL_RCC_LPTIM3_CLKSOURCE_LSE:
4489 case LL_RCC_LPTIM4_CLKSOURCE_LSE:
4490 case LL_RCC_LPTIM5_CLKSOURCE_LSE:
4491 if (LL_RCC_LSE_IsReady() != 0U)
4492 {
4493 lptim_frequency = LSE_VALUE;
4494 }
4495 break;
4496
4497 case LL_RCC_LPTIM1_CLKSOURCE_LSI:
4498 case LL_RCC_LPTIM2_CLKSOURCE_LSI:
4499 case LL_RCC_LPTIM3_CLKSOURCE_LSI:
4500 case LL_RCC_LPTIM4_CLKSOURCE_LSI:
4501 case LL_RCC_LPTIM5_CLKSOURCE_LSI:
4502 if (LL_RCC_LSI_IsReady() != 0U)
4503 {
4504 lptim_frequency = LSI_VALUE;
4505 }
4506 break;
4507
4508 case LL_RCC_LPTIM1_CLKSOURCE_TIMG:
4509 case LL_RCC_LPTIM2_CLKSOURCE_TIMG:
4510 case LL_RCC_LPTIM3_CLKSOURCE_TIMG:
4511 case LL_RCC_LPTIM4_CLKSOURCE_TIMG:
4512 case LL_RCC_LPTIM5_CLKSOURCE_TIMG:
4513 lptim_frequency = HAL_RCC_GetSysClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
4514 break;
4515
4516 default:
4517 /* Unexpected case */
4518 break;
4519 }
4520
4521 return lptim_frequency;
4522 }
4523
4524 /**
4525 * @brief Return LPUART clock frequency
4526 * @param LPUARTxSource This parameter can be one of the following values:
4527 * @arg @ref RCCEx_LPUART1_Clock_Source
4528 * @retval LPUART clock frequency (in Hz)
4529 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
4530 */
RCCEx_GetLPUARTCLKFreq(uint32_t LPUARTxSource)4531 static uint32_t RCCEx_GetLPUARTCLKFreq(uint32_t LPUARTxSource)
4532 {
4533 uint32_t lpuart_frequency = RCC_PERIPH_FREQUENCY_NO;
4534 uint32_t ic_divider;
4535
4536 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
4537 {
4538 case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
4539 lpuart_frequency = RCCEx_GetPCLK4Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
4540 break;
4541
4542 case LL_RCC_LPUART1_CLKSOURCE_CLKP:
4543 lpuart_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
4544 break;
4545
4546 case LL_RCC_LPUART1_CLKSOURCE_IC9:
4547 if (LL_RCC_IC9_IsEnabled() != 0U)
4548 {
4549 ic_divider = LL_RCC_IC9_GetDivider();
4550 switch (LL_RCC_IC9_GetSource())
4551 {
4552 case LL_RCC_ICCLKSOURCE_PLL1:
4553 lpuart_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4554 lpuart_frequency = lpuart_frequency / ic_divider;
4555 break;
4556 case LL_RCC_ICCLKSOURCE_PLL2:
4557 lpuart_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4558 lpuart_frequency = lpuart_frequency / ic_divider;
4559 break;
4560 case LL_RCC_ICCLKSOURCE_PLL3:
4561 lpuart_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4562 lpuart_frequency = lpuart_frequency / ic_divider;
4563 break;
4564 case LL_RCC_ICCLKSOURCE_PLL4:
4565 lpuart_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4566 lpuart_frequency = lpuart_frequency / ic_divider;
4567 break;
4568 default:
4569 /* Unexpected case */
4570 break;
4571 }
4572 }
4573 break;
4574
4575 case LL_RCC_LPUART1_CLKSOURCE_IC14:
4576 if (LL_RCC_IC14_IsEnabled() != 0U)
4577 {
4578 ic_divider = LL_RCC_IC14_GetDivider();
4579 switch (LL_RCC_IC14_GetSource())
4580 {
4581 case LL_RCC_ICCLKSOURCE_PLL1:
4582 lpuart_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4583 lpuart_frequency = lpuart_frequency / ic_divider;
4584 break;
4585 case LL_RCC_ICCLKSOURCE_PLL2:
4586 lpuart_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4587 lpuart_frequency = lpuart_frequency / ic_divider;
4588 break;
4589 case LL_RCC_ICCLKSOURCE_PLL3:
4590 lpuart_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4591 lpuart_frequency = lpuart_frequency / ic_divider;
4592 break;
4593 case LL_RCC_ICCLKSOURCE_PLL4:
4594 lpuart_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4595 lpuart_frequency = lpuart_frequency / ic_divider;
4596 break;
4597 default:
4598 /* Unexpected case */
4599 break;
4600 }
4601 }
4602 break;
4603
4604 case LL_RCC_LPUART1_CLKSOURCE_HSI:
4605 if (LL_RCC_HSI_IsReady() != 0U)
4606 {
4607 lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
4608 }
4609 break;
4610
4611 case LL_RCC_LPUART1_CLKSOURCE_MSI:
4612 if (LL_RCC_MSI_IsReady() != 0U)
4613 {
4614 lpuart_frequency = MSI_VALUE;
4615 }
4616 break;
4617
4618 case LL_RCC_LPUART1_CLKSOURCE_LSE:
4619 if (LL_RCC_LSE_IsReady() != 0U)
4620 {
4621 lpuart_frequency = LSE_VALUE;
4622 }
4623 break;
4624
4625 default:
4626 /* Unexpected case */
4627 break;
4628 }
4629
4630 return lpuart_frequency;
4631 }
4632
4633 /**
4634 * @brief Return LTDC clock frequency
4635 * @param LTDCxSource This parameter can be one of the following values:
4636 * @arg @ref RCCEx_LTDC_Clock_Source
4637 * @retval LTDC clock frequency (in Hz)
4638 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
4639 */
RCCEx_GetLTDCCLKFreq(uint32_t LTDCxSource)4640 static uint32_t RCCEx_GetLTDCCLKFreq(uint32_t LTDCxSource)
4641 {
4642 uint32_t ltdc_frequency = RCC_PERIPH_FREQUENCY_NO;
4643 uint32_t ic_divider;
4644
4645 switch (LL_RCC_GetLTDCClockSource(LTDCxSource))
4646 {
4647 case LL_RCC_LTDC_CLKSOURCE_PCLK5:
4648 ltdc_frequency = RCCEx_GetPCLK5Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
4649 break;
4650
4651 case LL_RCC_LTDC_CLKSOURCE_CLKP:
4652 ltdc_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
4653 break;
4654
4655 case LL_RCC_LTDC_CLKSOURCE_IC16:
4656 if (LL_RCC_IC16_IsEnabled() != 0U)
4657 {
4658 ic_divider = LL_RCC_IC16_GetDivider();
4659 switch (LL_RCC_IC16_GetSource())
4660 {
4661 case LL_RCC_ICCLKSOURCE_PLL1:
4662 ltdc_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4663 ltdc_frequency = ltdc_frequency / ic_divider;
4664 break;
4665 case LL_RCC_ICCLKSOURCE_PLL2:
4666 ltdc_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4667 ltdc_frequency = ltdc_frequency / ic_divider;
4668 break;
4669 case LL_RCC_ICCLKSOURCE_PLL3:
4670 ltdc_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4671 ltdc_frequency = ltdc_frequency / ic_divider;
4672 break;
4673 case LL_RCC_ICCLKSOURCE_PLL4:
4674 ltdc_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4675 ltdc_frequency = ltdc_frequency / ic_divider;
4676 break;
4677 default:
4678 /* Unexpected case */
4679 break;
4680 }
4681 }
4682 break;
4683
4684 case LL_RCC_LTDC_CLKSOURCE_HSI:
4685 if (LL_RCC_HSI_IsReady() != 0U)
4686 {
4687 ltdc_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
4688 }
4689 break;
4690
4691 default:
4692 /* Unexpected case */
4693 break;
4694 }
4695
4696 return ltdc_frequency;
4697 }
4698
4699 /**
4700 * @brief Return MDFx clock frequency
4701 * @param MDFxSource This parameter can be one of the following values:
4702 * @arg @ref RCCEx_MDF1_Clock_Source
4703 * @retval MDF clock frequency (in Hz)
4704 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
4705 */
RCCEx_GetMDFCLKFreq(uint32_t MDFxSource)4706 static uint32_t RCCEx_GetMDFCLKFreq(uint32_t MDFxSource)
4707 {
4708 uint32_t adf_frequency = RCC_PERIPH_FREQUENCY_NO;
4709 uint32_t ic_divider;
4710
4711 switch (LL_RCC_GetMDFClockSource(MDFxSource))
4712 {
4713 case LL_RCC_MDF1_CLKSOURCE_HCLK:
4714 adf_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
4715 break;
4716
4717 case LL_RCC_MDF1_CLKSOURCE_CLKP:
4718 adf_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
4719 break;
4720
4721 case LL_RCC_MDF1_CLKSOURCE_IC7:
4722 if (LL_RCC_IC7_IsEnabled() != 0U)
4723 {
4724 ic_divider = LL_RCC_IC7_GetDivider();
4725 switch (LL_RCC_IC7_GetSource())
4726 {
4727 case LL_RCC_ICCLKSOURCE_PLL1:
4728 adf_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4729 adf_frequency = adf_frequency / ic_divider;
4730 break;
4731 case LL_RCC_ICCLKSOURCE_PLL2:
4732 adf_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4733 adf_frequency = adf_frequency / ic_divider;
4734 break;
4735 case LL_RCC_ICCLKSOURCE_PLL3:
4736 adf_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4737 adf_frequency = adf_frequency / ic_divider;
4738 break;
4739 case LL_RCC_ICCLKSOURCE_PLL4:
4740 adf_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4741 adf_frequency = adf_frequency / ic_divider;
4742 break;
4743 default:
4744 /* Unexpected case */
4745 break;
4746 }
4747 }
4748 break;
4749
4750 case LL_RCC_MDF1_CLKSOURCE_IC8:
4751 if (LL_RCC_IC8_IsEnabled() != 0U)
4752 {
4753 ic_divider = LL_RCC_IC8_GetDivider();
4754 switch (LL_RCC_IC8_GetSource())
4755 {
4756 case LL_RCC_ICCLKSOURCE_PLL1:
4757 adf_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4758 adf_frequency = adf_frequency / ic_divider;
4759 break;
4760 case LL_RCC_ICCLKSOURCE_PLL2:
4761 adf_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4762 adf_frequency = adf_frequency / ic_divider;
4763 break;
4764 case LL_RCC_ICCLKSOURCE_PLL3:
4765 adf_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4766 adf_frequency = adf_frequency / ic_divider;
4767 break;
4768 case LL_RCC_ICCLKSOURCE_PLL4:
4769 adf_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4770 adf_frequency = adf_frequency / ic_divider;
4771 break;
4772 default:
4773 /* Unexpected case */
4774 break;
4775 }
4776 }
4777 break;
4778
4779 case LL_RCC_MDF1_CLKSOURCE_HSI:
4780 if (LL_RCC_HSI_IsReady() != 0U)
4781 {
4782 adf_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
4783 }
4784 break;
4785
4786 case LL_RCC_MDF1_CLKSOURCE_MSI:
4787 if (LL_RCC_MSI_IsReady() != 0U)
4788 {
4789 adf_frequency = MSI_VALUE;
4790 }
4791 break;
4792
4793 case LL_RCC_MDF1_CLKSOURCE_I2S_CKIN:
4794 adf_frequency = EXTERNAL_CLOCK_VALUE;
4795 break;
4796
4797 case LL_RCC_MDF1_CLKSOURCE_TIMG:
4798 adf_frequency = HAL_RCC_GetSysClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
4799 break;
4800
4801 default:
4802 /* Unexpected case */
4803 break;
4804 }
4805
4806 return adf_frequency;
4807 }
4808
4809 /**
4810 * @brief Return PSSI clock frequency
4811 * @param PSSIxSource This parameter can be one of the following values:
4812 * @arg @ref RCCEx_PSSI_Clock_Source
4813 * @retval PSSI clock frequency (in Hz)
4814 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
4815 */
RCCEx_GetPSSICLKFreq(uint32_t PSSIxSource)4816 static uint32_t RCCEx_GetPSSICLKFreq(uint32_t PSSIxSource)
4817 {
4818 uint32_t pssi_frequency = RCC_PERIPH_FREQUENCY_NO;
4819 uint32_t ic_divider;
4820
4821 switch (LL_RCC_GetPSSIClockSource(PSSIxSource))
4822 {
4823 case LL_RCC_PSSI_CLKSOURCE_HCLK:
4824 pssi_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
4825 break;
4826
4827 case LL_RCC_PSSI_CLKSOURCE_CLKP:
4828 pssi_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
4829 break;
4830
4831 case LL_RCC_PSSI_CLKSOURCE_IC20:
4832 if (LL_RCC_IC20_IsEnabled() != 0U)
4833 {
4834 ic_divider = LL_RCC_IC20_GetDivider();
4835 switch (LL_RCC_IC20_GetSource())
4836 {
4837 case LL_RCC_ICCLKSOURCE_PLL1:
4838 pssi_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4839 pssi_frequency = pssi_frequency / ic_divider;
4840 break;
4841 case LL_RCC_ICCLKSOURCE_PLL2:
4842 pssi_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4843 pssi_frequency = pssi_frequency / ic_divider;
4844 break;
4845 case LL_RCC_ICCLKSOURCE_PLL3:
4846 pssi_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4847 pssi_frequency = pssi_frequency / ic_divider;
4848 break;
4849 case LL_RCC_ICCLKSOURCE_PLL4:
4850 pssi_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4851 pssi_frequency = pssi_frequency / ic_divider;
4852 break;
4853 default:
4854 /* Unexpected case */
4855 break;
4856 }
4857 }
4858 break;
4859
4860 case LL_RCC_PSSI_CLKSOURCE_HSI:
4861 if (LL_RCC_HSI_IsReady() != 0U)
4862 {
4863 pssi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
4864 }
4865 break;
4866
4867 default:
4868 /* Unexpected case */
4869 break;
4870 }
4871
4872 return pssi_frequency;
4873 }
4874
4875 /**
4876 * @brief Return RTC clock frequency
4877 * @retval RTC clock frequency (in Hz)
4878 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
4879 */
RCCEx_GetRTCCLKFreq()4880 static uint32_t RCCEx_GetRTCCLKFreq()
4881 {
4882 uint32_t rtc_frequency = RCC_PERIPH_FREQUENCY_NO;
4883
4884 switch (LL_RCC_GetRTCClockSource())
4885 {
4886 case LL_RCC_RTC_CLKSOURCE_NONE:
4887 /* Nothing to do */
4888 break;
4889
4890 case LL_RCC_RTC_CLKSOURCE_LSE:
4891 if (LL_RCC_LSE_IsReady() != 0U)
4892 {
4893 rtc_frequency = LSE_VALUE;
4894 }
4895 break;
4896
4897 case LL_RCC_RTC_CLKSOURCE_LSI:
4898 if (LL_RCC_LSI_IsReady() != 0U)
4899 {
4900 rtc_frequency = LSI_VALUE;
4901 }
4902 break;
4903
4904 case LL_RCC_RTC_CLKSOURCE_HSE:
4905 if (LL_RCC_HSE_IsReady() != 0U)
4906 {
4907 uint32_t prescaler = (READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCPRE) >> RCC_CCIPR7_RTCPRE_Pos) + 1U;
4908 rtc_frequency = HSE_VALUE / prescaler;
4909 }
4910 break;
4911
4912 default:
4913 /* Unexpected case */
4914 break;
4915 }
4916
4917 return rtc_frequency;
4918 }
4919
4920 /**
4921 * @brief Return SAIx clock frequency
4922 * @param SAIxSource This parameter can be one of the following values:
4923 * @arg @ref RCCEx_SAI1_Clock_Source
4924 * @arg @ref RCCEx_SAI2_Clock_Source
4925 * @retval SAI clock frequency (in Hz)
4926 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
4927 */
RCCEx_GetSAICLKFreq(uint32_t SAIxSource)4928 static uint32_t RCCEx_GetSAICLKFreq(uint32_t SAIxSource)
4929 {
4930 uint32_t sai_frequency = RCC_PERIPH_FREQUENCY_NO;
4931 uint32_t ic_divider;
4932
4933 switch (LL_RCC_GetSAIClockSource(SAIxSource))
4934 {
4935 case LL_RCC_SAI1_CLKSOURCE_PCLK2:
4936 case LL_RCC_SAI2_CLKSOURCE_PCLK2:
4937 sai_frequency = RCCEx_GetPCLK2Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
4938 break;
4939
4940 case LL_RCC_SAI1_CLKSOURCE_CLKP:
4941 case LL_RCC_SAI2_CLKSOURCE_CLKP:
4942 sai_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
4943 break;
4944
4945 case LL_RCC_SAI1_CLKSOURCE_IC7:
4946 case LL_RCC_SAI2_CLKSOURCE_IC7:
4947 if (LL_RCC_IC7_IsEnabled() != 0U)
4948 {
4949 ic_divider = LL_RCC_IC7_GetDivider();
4950 switch (LL_RCC_IC7_GetSource())
4951 {
4952 case LL_RCC_ICCLKSOURCE_PLL1:
4953 sai_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4954 sai_frequency = sai_frequency / ic_divider;
4955 break;
4956 case LL_RCC_ICCLKSOURCE_PLL2:
4957 sai_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4958 sai_frequency = sai_frequency / ic_divider;
4959 break;
4960 case LL_RCC_ICCLKSOURCE_PLL3:
4961 sai_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4962 sai_frequency = sai_frequency / ic_divider;
4963 break;
4964 case LL_RCC_ICCLKSOURCE_PLL4:
4965 sai_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4966 sai_frequency = sai_frequency / ic_divider;
4967 break;
4968 default:
4969 /* Unexpected case */
4970 break;
4971 }
4972 }
4973 break;
4974
4975 case LL_RCC_SAI1_CLKSOURCE_IC8:
4976 case LL_RCC_SAI2_CLKSOURCE_IC8:
4977 if (LL_RCC_IC8_IsEnabled() != 0U)
4978 {
4979 ic_divider = LL_RCC_IC8_GetDivider();
4980 switch (LL_RCC_IC8_GetSource())
4981 {
4982 case LL_RCC_ICCLKSOURCE_PLL1:
4983 sai_frequency = HAL_RCCEx_GetPLL1CLKFreq();
4984 sai_frequency = sai_frequency / ic_divider;
4985 break;
4986 case LL_RCC_ICCLKSOURCE_PLL2:
4987 sai_frequency = HAL_RCCEx_GetPLL2CLKFreq();
4988 sai_frequency = sai_frequency / ic_divider;
4989 break;
4990 case LL_RCC_ICCLKSOURCE_PLL3:
4991 sai_frequency = HAL_RCCEx_GetPLL3CLKFreq();
4992 sai_frequency = sai_frequency / ic_divider;
4993 break;
4994 case LL_RCC_ICCLKSOURCE_PLL4:
4995 sai_frequency = HAL_RCCEx_GetPLL4CLKFreq();
4996 sai_frequency = sai_frequency / ic_divider;
4997 break;
4998 default:
4999 /* Unexpected case */
5000 break;
5001 }
5002 }
5003 break;
5004
5005 case LL_RCC_SAI1_CLKSOURCE_HSI:
5006 case LL_RCC_SAI2_CLKSOURCE_HSI:
5007 if (LL_RCC_HSI_IsReady() != 0U)
5008 {
5009 sai_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
5010 }
5011 break;
5012
5013 case LL_RCC_SAI1_CLKSOURCE_MSI:
5014 case LL_RCC_SAI2_CLKSOURCE_MSI:
5015 if (LL_RCC_MSI_IsReady() != 0U)
5016 {
5017 sai_frequency = MSI_VALUE;
5018 }
5019 break;
5020
5021 case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN:
5022 case LL_RCC_SAI2_CLKSOURCE_I2S_CKIN:
5023 sai_frequency = EXTERNAL_CLOCK_VALUE;
5024 break;
5025
5026 case LL_RCC_SAI1_CLKSOURCE_SPDIFRX1:
5027 case LL_RCC_SAI2_CLKSOURCE_SPDIFRX1:
5028 sai_frequency = RCCEx_GetSPDIFRXCLKFreq(LL_RCC_SPDIFRX1_CLKSOURCE);
5029 break;
5030
5031 default:
5032 /* Unexpected case */
5033 break;
5034 }
5035
5036 return sai_frequency;
5037 }
5038
5039 /**
5040 * @brief Return SDMMC clock frequency
5041 * @param SDMMCxSource This parameter can be one of the following values:
5042 * @arg @ref RCCEx_SDMMC1_Clock_Source
5043 * @arg @ref RCCEx_SDMMC2_Clock_Source
5044 * @retval SDMMC clock frequency (in Hz)
5045 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
5046 */
RCCEx_GetSDMMCCLKFreq(uint32_t SDMMCxSource)5047 static uint32_t RCCEx_GetSDMMCCLKFreq(uint32_t SDMMCxSource)
5048 {
5049 uint32_t sdmmc_frequency = RCC_PERIPH_FREQUENCY_NO;
5050 uint32_t ic_divider;
5051
5052 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
5053 {
5054 case LL_RCC_SDMMC1_CLKSOURCE_HCLK:
5055 case LL_RCC_SDMMC2_CLKSOURCE_HCLK:
5056 sdmmc_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
5057 break;
5058
5059 case LL_RCC_SDMMC1_CLKSOURCE_CLKP:
5060 case LL_RCC_SDMMC2_CLKSOURCE_CLKP:
5061 sdmmc_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
5062 break;
5063
5064 case LL_RCC_SDMMC1_CLKSOURCE_IC4:
5065 case LL_RCC_SDMMC2_CLKSOURCE_IC4:
5066 if (LL_RCC_IC4_IsEnabled() != 0U)
5067 {
5068 ic_divider = LL_RCC_IC4_GetDivider();
5069 switch (LL_RCC_IC4_GetSource())
5070 {
5071 case LL_RCC_ICCLKSOURCE_PLL1:
5072 sdmmc_frequency = HAL_RCCEx_GetPLL1CLKFreq();
5073 sdmmc_frequency = sdmmc_frequency / ic_divider;
5074 break;
5075 case LL_RCC_ICCLKSOURCE_PLL2:
5076 sdmmc_frequency = HAL_RCCEx_GetPLL2CLKFreq();
5077 sdmmc_frequency = sdmmc_frequency / ic_divider;
5078 break;
5079 case LL_RCC_ICCLKSOURCE_PLL3:
5080 sdmmc_frequency = HAL_RCCEx_GetPLL3CLKFreq();
5081 sdmmc_frequency = sdmmc_frequency / ic_divider;
5082 break;
5083 case LL_RCC_ICCLKSOURCE_PLL4:
5084 sdmmc_frequency = HAL_RCCEx_GetPLL4CLKFreq();
5085 sdmmc_frequency = sdmmc_frequency / ic_divider;
5086 break;
5087 default:
5088 /* Unexpected case */
5089 break;
5090 }
5091 }
5092 break;
5093
5094 case LL_RCC_SDMMC1_CLKSOURCE_IC5:
5095 case LL_RCC_SDMMC2_CLKSOURCE_IC5:
5096 if (LL_RCC_IC5_IsEnabled() != 0U)
5097 {
5098 ic_divider = LL_RCC_IC5_GetDivider();
5099 switch (LL_RCC_IC5_GetSource())
5100 {
5101 case LL_RCC_ICCLKSOURCE_PLL1:
5102 sdmmc_frequency = HAL_RCCEx_GetPLL1CLKFreq();
5103 sdmmc_frequency = sdmmc_frequency / ic_divider;
5104 break;
5105 case LL_RCC_ICCLKSOURCE_PLL2:
5106 sdmmc_frequency = HAL_RCCEx_GetPLL2CLKFreq();
5107 sdmmc_frequency = sdmmc_frequency / ic_divider;
5108 break;
5109 case LL_RCC_ICCLKSOURCE_PLL3:
5110 sdmmc_frequency = HAL_RCCEx_GetPLL3CLKFreq();
5111 sdmmc_frequency = sdmmc_frequency / ic_divider;
5112 break;
5113 case LL_RCC_ICCLKSOURCE_PLL4:
5114 sdmmc_frequency = HAL_RCCEx_GetPLL4CLKFreq();
5115 sdmmc_frequency = sdmmc_frequency / ic_divider;
5116 break;
5117 default:
5118 /* Unexpected case */
5119 break;
5120 }
5121 }
5122 break;
5123
5124 default:
5125 /* Unexpected case */
5126 break;
5127 }
5128
5129 return sdmmc_frequency;
5130 }
5131
5132 /**
5133 * @brief Return SPDIFRX clock frequency
5134 * @param SPDIFRXxSource This parameter can be one of the following values:
5135 * @arg @ref RCCEx_SPDIFRX1_Clock_Source
5136 * @retval SPDIF clock frequency (in Hz)
5137 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
5138 */
RCCEx_GetSPDIFRXCLKFreq(uint32_t SPDIFRXxSource)5139 static uint32_t RCCEx_GetSPDIFRXCLKFreq(uint32_t SPDIFRXxSource)
5140 {
5141 uint32_t spdifrx_frequency = RCC_PERIPH_FREQUENCY_NO;
5142 uint32_t ic_divider;
5143
5144 switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
5145 {
5146 case LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1:
5147 spdifrx_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
5148 break;
5149
5150 case LL_RCC_SPDIFRX1_CLKSOURCE_CLKP:
5151 spdifrx_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
5152 break;
5153
5154 case LL_RCC_SPDIFRX1_CLKSOURCE_IC7:
5155 if (LL_RCC_IC7_IsEnabled() != 0U)
5156 {
5157 ic_divider = LL_RCC_IC7_GetDivider();
5158 switch (LL_RCC_IC7_GetSource())
5159 {
5160 case LL_RCC_ICCLKSOURCE_PLL1:
5161 spdifrx_frequency = HAL_RCCEx_GetPLL1CLKFreq();
5162 spdifrx_frequency = spdifrx_frequency / ic_divider;
5163 break;
5164 case LL_RCC_ICCLKSOURCE_PLL2:
5165 spdifrx_frequency = HAL_RCCEx_GetPLL2CLKFreq();
5166 spdifrx_frequency = spdifrx_frequency / ic_divider;
5167 break;
5168 case LL_RCC_ICCLKSOURCE_PLL3:
5169 spdifrx_frequency = HAL_RCCEx_GetPLL3CLKFreq();
5170 spdifrx_frequency = spdifrx_frequency / ic_divider;
5171 break;
5172 case LL_RCC_ICCLKSOURCE_PLL4:
5173 spdifrx_frequency = HAL_RCCEx_GetPLL4CLKFreq();
5174 spdifrx_frequency = spdifrx_frequency / ic_divider;
5175 break;
5176 default:
5177 /* Unexpected case */
5178 break;
5179 }
5180 }
5181 break;
5182
5183 case LL_RCC_SPDIFRX1_CLKSOURCE_IC8:
5184 if (LL_RCC_IC8_IsEnabled() != 0U)
5185 {
5186 ic_divider = LL_RCC_IC8_GetDivider();
5187 switch (LL_RCC_IC8_GetSource())
5188 {
5189 case LL_RCC_ICCLKSOURCE_PLL1:
5190 spdifrx_frequency = HAL_RCCEx_GetPLL1CLKFreq();
5191 spdifrx_frequency = spdifrx_frequency / ic_divider;
5192 break;
5193 case LL_RCC_ICCLKSOURCE_PLL2:
5194 spdifrx_frequency = HAL_RCCEx_GetPLL2CLKFreq();
5195 spdifrx_frequency = spdifrx_frequency / ic_divider;
5196 break;
5197 case LL_RCC_ICCLKSOURCE_PLL3:
5198 spdifrx_frequency = HAL_RCCEx_GetPLL3CLKFreq();
5199 spdifrx_frequency = spdifrx_frequency / ic_divider;
5200 break;
5201 case LL_RCC_ICCLKSOURCE_PLL4:
5202 spdifrx_frequency = HAL_RCCEx_GetPLL4CLKFreq();
5203 spdifrx_frequency = spdifrx_frequency / ic_divider;
5204 break;
5205 default:
5206 /* Unexpected case */
5207 break;
5208 }
5209 }
5210 break;
5211
5212 case LL_RCC_SPDIFRX1_CLKSOURCE_HSI:
5213 if (LL_RCC_HSI_IsReady() != 0U)
5214 {
5215 spdifrx_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
5216 }
5217 break;
5218
5219 case LL_RCC_SPDIFRX1_CLKSOURCE_MSI:
5220 if (LL_RCC_MSI_IsReady() != 0U)
5221 {
5222 spdifrx_frequency = MSI_VALUE;
5223 }
5224 break;
5225
5226 case LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN:
5227 spdifrx_frequency = EXTERNAL_CLOCK_VALUE;
5228 break;
5229
5230 default:
5231 /* Unexpected case */
5232 break;
5233 }
5234
5235 return spdifrx_frequency;
5236 }
5237
5238 /**
5239 * @brief Return SPIx clock frequency
5240 * @param SPIxSource This parameter can be one of the following values:
5241 * @arg @ref RCCEx_SPI1_Clock_Source
5242 * @arg @ref RCCEx_SPI2_Clock_Source
5243 * @arg @ref RCCEx_SPI3_Clock_Source
5244 * @arg @ref RCCEx_SPI4_Clock_Source
5245 * @arg @ref RCCEx_SPI5_Clock_Source
5246 * @arg @ref RCCEx_SPI6_Clock_Source
5247 * @retval SPI clock frequency (in Hz)
5248 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
5249 */
RCCEx_GetSPICLKFreq(uint32_t SPIxSource)5250 static uint32_t RCCEx_GetSPICLKFreq(uint32_t SPIxSource)
5251 {
5252 uint32_t spi_frequency = RCC_PERIPH_FREQUENCY_NO;
5253 uint32_t ic_divider;
5254
5255 switch (LL_RCC_GetSPIClockSource(SPIxSource))
5256 {
5257 case LL_RCC_SPI2_CLKSOURCE_PCLK1:
5258 case LL_RCC_SPI3_CLKSOURCE_PCLK1:
5259 spi_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
5260 break;
5261
5262 case LL_RCC_SPI1_CLKSOURCE_PCLK2:
5263 case LL_RCC_SPI4_CLKSOURCE_PCLK2:
5264 case LL_RCC_SPI5_CLKSOURCE_PCLK2:
5265 spi_frequency = RCCEx_GetPCLK2Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
5266 break;
5267
5268 case LL_RCC_SPI6_CLKSOURCE_PCLK4:
5269 spi_frequency = RCCEx_GetPCLK4Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
5270 break;
5271
5272 case LL_RCC_SPI1_CLKSOURCE_CLKP:
5273 case LL_RCC_SPI2_CLKSOURCE_CLKP:
5274 case LL_RCC_SPI3_CLKSOURCE_CLKP:
5275 case LL_RCC_SPI4_CLKSOURCE_CLKP:
5276 case LL_RCC_SPI5_CLKSOURCE_CLKP:
5277 case LL_RCC_SPI6_CLKSOURCE_CLKP:
5278 spi_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
5279 break;
5280
5281 case LL_RCC_SPI1_CLKSOURCE_IC8:
5282 case LL_RCC_SPI2_CLKSOURCE_IC8:
5283 case LL_RCC_SPI3_CLKSOURCE_IC8:
5284 case LL_RCC_SPI6_CLKSOURCE_IC8:
5285 if (LL_RCC_IC8_IsEnabled() != 0U)
5286 {
5287 ic_divider = LL_RCC_IC8_GetDivider();
5288 switch (LL_RCC_IC8_GetSource())
5289 {
5290 case LL_RCC_ICCLKSOURCE_PLL1:
5291 spi_frequency = HAL_RCCEx_GetPLL1CLKFreq();
5292 spi_frequency = spi_frequency / ic_divider;
5293 break;
5294 case LL_RCC_ICCLKSOURCE_PLL2:
5295 spi_frequency = HAL_RCCEx_GetPLL2CLKFreq();
5296 spi_frequency = spi_frequency / ic_divider;
5297 break;
5298 case LL_RCC_ICCLKSOURCE_PLL3:
5299 spi_frequency = HAL_RCCEx_GetPLL3CLKFreq();
5300 spi_frequency = spi_frequency / ic_divider;
5301 break;
5302 case LL_RCC_ICCLKSOURCE_PLL4:
5303 spi_frequency = HAL_RCCEx_GetPLL4CLKFreq();
5304 spi_frequency = spi_frequency / ic_divider;
5305 break;
5306 default:
5307 /* Unexpected case */
5308 break;
5309 }
5310 }
5311 break;
5312
5313 case LL_RCC_SPI1_CLKSOURCE_IC9:
5314 case LL_RCC_SPI2_CLKSOURCE_IC9:
5315 case LL_RCC_SPI3_CLKSOURCE_IC9:
5316 case LL_RCC_SPI4_CLKSOURCE_IC9:
5317 case LL_RCC_SPI5_CLKSOURCE_IC9:
5318 case LL_RCC_SPI6_CLKSOURCE_IC9:
5319 if (LL_RCC_IC9_IsEnabled() != 0U)
5320 {
5321 ic_divider = LL_RCC_IC9_GetDivider();
5322 switch (LL_RCC_IC9_GetSource())
5323 {
5324 case LL_RCC_ICCLKSOURCE_PLL1:
5325 spi_frequency = HAL_RCCEx_GetPLL1CLKFreq();
5326 spi_frequency = spi_frequency / ic_divider;
5327 break;
5328 case LL_RCC_ICCLKSOURCE_PLL2:
5329 spi_frequency = HAL_RCCEx_GetPLL2CLKFreq();
5330 spi_frequency = spi_frequency / ic_divider;
5331 break;
5332 case LL_RCC_ICCLKSOURCE_PLL3:
5333 spi_frequency = HAL_RCCEx_GetPLL3CLKFreq();
5334 spi_frequency = spi_frequency / ic_divider;
5335 break;
5336 case LL_RCC_ICCLKSOURCE_PLL4:
5337 spi_frequency = HAL_RCCEx_GetPLL4CLKFreq();
5338 spi_frequency = spi_frequency / ic_divider;
5339 break;
5340 default:
5341 /* Unexpected case */
5342 break;
5343 }
5344 }
5345 break;
5346
5347 case LL_RCC_SPI4_CLKSOURCE_IC14:
5348 case LL_RCC_SPI5_CLKSOURCE_IC14:
5349 if (LL_RCC_IC14_IsEnabled() != 0U)
5350 {
5351 ic_divider = LL_RCC_IC14_GetDivider();
5352 switch (LL_RCC_IC14_GetSource())
5353 {
5354 case LL_RCC_ICCLKSOURCE_PLL1:
5355 spi_frequency = HAL_RCCEx_GetPLL1CLKFreq();
5356 spi_frequency = spi_frequency / ic_divider;
5357 break;
5358 case LL_RCC_ICCLKSOURCE_PLL2:
5359 spi_frequency = HAL_RCCEx_GetPLL2CLKFreq();
5360 spi_frequency = spi_frequency / ic_divider;
5361 break;
5362 case LL_RCC_ICCLKSOURCE_PLL3:
5363 spi_frequency = HAL_RCCEx_GetPLL3CLKFreq();
5364 spi_frequency = spi_frequency / ic_divider;
5365 break;
5366 case LL_RCC_ICCLKSOURCE_PLL4:
5367 spi_frequency = HAL_RCCEx_GetPLL4CLKFreq();
5368 spi_frequency = spi_frequency / ic_divider;
5369 break;
5370 default:
5371 /* Unexpected case */
5372 break;
5373 }
5374 }
5375 break;
5376
5377 case LL_RCC_SPI1_CLKSOURCE_HSI:
5378 case LL_RCC_SPI2_CLKSOURCE_HSI:
5379 case LL_RCC_SPI3_CLKSOURCE_HSI:
5380 case LL_RCC_SPI4_CLKSOURCE_HSI:
5381 case LL_RCC_SPI5_CLKSOURCE_HSI:
5382 case LL_RCC_SPI6_CLKSOURCE_HSI:
5383 if (LL_RCC_HSI_IsReady() != 0U)
5384 {
5385 spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
5386 }
5387 break;
5388
5389 case LL_RCC_SPI1_CLKSOURCE_MSI:
5390 case LL_RCC_SPI2_CLKSOURCE_MSI:
5391 case LL_RCC_SPI3_CLKSOURCE_MSI:
5392 case LL_RCC_SPI4_CLKSOURCE_MSI:
5393 case LL_RCC_SPI5_CLKSOURCE_MSI:
5394 case LL_RCC_SPI6_CLKSOURCE_MSI:
5395 if (LL_RCC_MSI_IsReady() != 0U)
5396 {
5397 spi_frequency = MSI_VALUE;
5398 }
5399 break;
5400
5401 case LL_RCC_SPI1_CLKSOURCE_I2S_CKIN:
5402 case LL_RCC_SPI2_CLKSOURCE_I2S_CKIN:
5403 case LL_RCC_SPI3_CLKSOURCE_I2S_CKIN:
5404 case LL_RCC_SPI6_CLKSOURCE_I2S_CKIN:
5405 spi_frequency = EXTERNAL_CLOCK_VALUE;
5406 break;
5407
5408 case LL_RCC_SPI4_CLKSOURCE_HSE:
5409 case LL_RCC_SPI5_CLKSOURCE_HSE:
5410 if (LL_RCC_HSE_IsReady() != 0U)
5411 {
5412 spi_frequency = HSE_VALUE;
5413 }
5414 break;
5415
5416 default:
5417 /* Unexpected case */
5418 break;
5419 }
5420
5421 return spi_frequency;
5422 }
5423
5424 /**
5425 * @brief Return UARTx clock frequency
5426 * @param UARTxSource This parameter can be one of the following values:
5427 * @arg @ref RCCEx_UART4_Clock_Source
5428 * @arg @ref RCCEx_UART5_Clock_Source
5429 * @arg @ref RCCEx_UART7_Clock_Source
5430 * @arg @ref RCCEx_UART8_Clock_Source
5431 * @arg @ref RCCEx_UART9_Clock_Source
5432 * @retval USART clock frequency (in Hz)
5433 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
5434 */
RCCEx_GetUARTCLKFreq(uint32_t UARTxSource)5435 static uint32_t RCCEx_GetUARTCLKFreq(uint32_t UARTxSource)
5436 {
5437 uint32_t uart_frequency = RCC_PERIPH_FREQUENCY_NO;
5438 uint32_t ic_divider;
5439
5440 switch (LL_RCC_GetUARTClockSource(UARTxSource))
5441 {
5442 case LL_RCC_UART4_CLKSOURCE_PCLK1:
5443 case LL_RCC_UART5_CLKSOURCE_PCLK1:
5444 case LL_RCC_UART7_CLKSOURCE_PCLK1:
5445 case LL_RCC_UART8_CLKSOURCE_PCLK1:
5446 uart_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
5447 break;
5448
5449 case LL_RCC_UART9_CLKSOURCE_PCLK2:
5450 uart_frequency = RCCEx_GetPCLK2Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
5451 break;
5452
5453 case LL_RCC_UART4_CLKSOURCE_CLKP:
5454 case LL_RCC_UART5_CLKSOURCE_CLKP:
5455 case LL_RCC_UART7_CLKSOURCE_CLKP:
5456 case LL_RCC_UART8_CLKSOURCE_CLKP:
5457 case LL_RCC_UART9_CLKSOURCE_CLKP:
5458 uart_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
5459 break;
5460
5461 case LL_RCC_UART4_CLKSOURCE_IC9:
5462 case LL_RCC_UART5_CLKSOURCE_IC9:
5463 case LL_RCC_UART7_CLKSOURCE_IC9:
5464 case LL_RCC_UART8_CLKSOURCE_IC9:
5465 case LL_RCC_UART9_CLKSOURCE_IC9:
5466 if (LL_RCC_IC9_IsEnabled() != 0U)
5467 {
5468 ic_divider = LL_RCC_IC9_GetDivider();
5469 switch (LL_RCC_IC9_GetSource())
5470 {
5471 case LL_RCC_ICCLKSOURCE_PLL1:
5472 uart_frequency = HAL_RCCEx_GetPLL1CLKFreq();
5473 uart_frequency = uart_frequency / ic_divider;
5474 break;
5475 case LL_RCC_ICCLKSOURCE_PLL2:
5476 uart_frequency = HAL_RCCEx_GetPLL2CLKFreq();
5477 uart_frequency = uart_frequency / ic_divider;
5478 break;
5479 case LL_RCC_ICCLKSOURCE_PLL3:
5480 uart_frequency = HAL_RCCEx_GetPLL3CLKFreq();
5481 uart_frequency = uart_frequency / ic_divider;
5482 break;
5483 case LL_RCC_ICCLKSOURCE_PLL4:
5484 uart_frequency = HAL_RCCEx_GetPLL4CLKFreq();
5485 uart_frequency = uart_frequency / ic_divider;
5486 break;
5487 default:
5488 /* Unexpected case */
5489 break;
5490 }
5491 }
5492 break;
5493
5494 case LL_RCC_UART4_CLKSOURCE_IC14:
5495 case LL_RCC_UART5_CLKSOURCE_IC14:
5496 case LL_RCC_UART7_CLKSOURCE_IC14:
5497 case LL_RCC_UART8_CLKSOURCE_IC14:
5498 case LL_RCC_UART9_CLKSOURCE_IC14:
5499 if (LL_RCC_IC14_IsEnabled() != 0U)
5500 {
5501 ic_divider = LL_RCC_IC14_GetDivider();
5502 switch (LL_RCC_IC14_GetSource())
5503 {
5504 case LL_RCC_ICCLKSOURCE_PLL1:
5505 uart_frequency = HAL_RCCEx_GetPLL1CLKFreq();
5506 uart_frequency = uart_frequency / ic_divider;
5507 break;
5508 case LL_RCC_ICCLKSOURCE_PLL2:
5509 uart_frequency = HAL_RCCEx_GetPLL2CLKFreq();
5510 uart_frequency = uart_frequency / ic_divider;
5511 break;
5512 case LL_RCC_ICCLKSOURCE_PLL3:
5513 uart_frequency = HAL_RCCEx_GetPLL3CLKFreq();
5514 uart_frequency = uart_frequency / ic_divider;
5515 break;
5516 case LL_RCC_ICCLKSOURCE_PLL4:
5517 uart_frequency = HAL_RCCEx_GetPLL4CLKFreq();
5518 uart_frequency = uart_frequency / ic_divider;
5519 break;
5520 default:
5521 /* Unexpected case */
5522 break;
5523 }
5524 }
5525 break;
5526
5527 case LL_RCC_UART4_CLKSOURCE_HSI:
5528 case LL_RCC_UART5_CLKSOURCE_HSI:
5529 case LL_RCC_UART7_CLKSOURCE_HSI:
5530 case LL_RCC_UART8_CLKSOURCE_HSI:
5531 case LL_RCC_UART9_CLKSOURCE_HSI:
5532 if (LL_RCC_HSI_IsReady() != 0U)
5533 {
5534 uart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
5535 }
5536 break;
5537
5538 case LL_RCC_UART4_CLKSOURCE_MSI:
5539 case LL_RCC_UART5_CLKSOURCE_MSI:
5540 case LL_RCC_UART7_CLKSOURCE_MSI:
5541 case LL_RCC_UART8_CLKSOURCE_MSI:
5542 case LL_RCC_UART9_CLKSOURCE_MSI:
5543 if (LL_RCC_MSI_IsReady() != 0U)
5544 {
5545 uart_frequency = MSI_VALUE;
5546 }
5547 break;
5548
5549 case LL_RCC_UART4_CLKSOURCE_LSE:
5550 case LL_RCC_UART5_CLKSOURCE_LSE:
5551 case LL_RCC_UART7_CLKSOURCE_LSE:
5552 case LL_RCC_UART8_CLKSOURCE_LSE:
5553 case LL_RCC_UART9_CLKSOURCE_LSE:
5554 if (LL_RCC_LSE_IsReady() != 0U)
5555 {
5556 uart_frequency = LSE_VALUE;
5557 }
5558 break;
5559
5560 default:
5561 /* Unexpected case */
5562 break;
5563 }
5564
5565 return uart_frequency;
5566 }
5567
5568 /**
5569 * @brief Return USARTx clock frequency
5570 * @param USARTxSource This parameter can be one of the following values:
5571 * @arg @ref RCCEx_USART1_Clock_Source
5572 * @arg @ref RCCEx_USART2_Clock_Source
5573 * @arg @ref RCCEx_USART3_Clock_Source
5574 * @arg @ref RCCEx_USART6_Clock_Source
5575 * @arg @ref RCCEx_USART10_Clock_Source
5576 * @retval USART clock frequency (in Hz)
5577 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
5578 */
RCCEx_GetUSARTCLKFreq(uint32_t USARTxSource)5579 static uint32_t RCCEx_GetUSARTCLKFreq(uint32_t USARTxSource)
5580 {
5581 uint32_t usart_frequency = RCC_PERIPH_FREQUENCY_NO;
5582 uint32_t ic_divider;
5583
5584 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
5585 {
5586 case LL_RCC_USART1_CLKSOURCE_PCLK2:
5587 case LL_RCC_USART6_CLKSOURCE_PCLK2:
5588 case LL_RCC_USART10_CLKSOURCE_PCLK2:
5589 usart_frequency = RCCEx_GetPCLK2Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
5590 break;
5591
5592 case LL_RCC_USART2_CLKSOURCE_PCLK1:
5593 case LL_RCC_USART3_CLKSOURCE_PCLK1:
5594 usart_frequency = RCCEx_GetPCLK1Freq(RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq()));
5595 break;
5596
5597 case LL_RCC_USART1_CLKSOURCE_CLKP:
5598 case LL_RCC_USART2_CLKSOURCE_CLKP:
5599 case LL_RCC_USART3_CLKSOURCE_CLKP:
5600 case LL_RCC_USART6_CLKSOURCE_CLKP:
5601 case LL_RCC_USART10_CLKSOURCE_CLKP:
5602 usart_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
5603 break;
5604
5605 case LL_RCC_USART1_CLKSOURCE_IC9:
5606 case LL_RCC_USART2_CLKSOURCE_IC9:
5607 case LL_RCC_USART3_CLKSOURCE_IC9:
5608 case LL_RCC_USART6_CLKSOURCE_IC9:
5609 case LL_RCC_USART10_CLKSOURCE_IC9:
5610 if (LL_RCC_IC9_IsEnabled() != 0U)
5611 {
5612 ic_divider = LL_RCC_IC9_GetDivider();
5613 switch (LL_RCC_IC9_GetSource())
5614 {
5615 case LL_RCC_ICCLKSOURCE_PLL1:
5616 usart_frequency = HAL_RCCEx_GetPLL1CLKFreq();
5617 usart_frequency = usart_frequency / ic_divider;
5618 break;
5619 case LL_RCC_ICCLKSOURCE_PLL2:
5620 usart_frequency = HAL_RCCEx_GetPLL2CLKFreq();
5621 usart_frequency = usart_frequency / ic_divider;
5622 break;
5623 case LL_RCC_ICCLKSOURCE_PLL3:
5624 usart_frequency = HAL_RCCEx_GetPLL3CLKFreq();
5625 usart_frequency = usart_frequency / ic_divider;
5626 break;
5627 case LL_RCC_ICCLKSOURCE_PLL4:
5628 usart_frequency = HAL_RCCEx_GetPLL4CLKFreq();
5629 usart_frequency = usart_frequency / ic_divider;
5630 break;
5631 default:
5632 /* Unexpected case */
5633 break;
5634 }
5635 }
5636 break;
5637
5638 case LL_RCC_USART1_CLKSOURCE_IC14:
5639 case LL_RCC_USART2_CLKSOURCE_IC14:
5640 case LL_RCC_USART3_CLKSOURCE_IC14:
5641 case LL_RCC_USART6_CLKSOURCE_IC14:
5642 case LL_RCC_USART10_CLKSOURCE_IC14:
5643 if (LL_RCC_IC14_IsEnabled() != 0U)
5644 {
5645 ic_divider = LL_RCC_IC14_GetDivider();
5646 switch (LL_RCC_IC14_GetSource())
5647 {
5648 case LL_RCC_ICCLKSOURCE_PLL1:
5649 usart_frequency = HAL_RCCEx_GetPLL1CLKFreq();
5650 usart_frequency = usart_frequency / ic_divider;
5651 break;
5652 case LL_RCC_ICCLKSOURCE_PLL2:
5653 usart_frequency = HAL_RCCEx_GetPLL2CLKFreq();
5654 usart_frequency = usart_frequency / ic_divider;
5655 break;
5656 case LL_RCC_ICCLKSOURCE_PLL3:
5657 usart_frequency = HAL_RCCEx_GetPLL3CLKFreq();
5658 usart_frequency = usart_frequency / ic_divider;
5659 break;
5660 case LL_RCC_ICCLKSOURCE_PLL4:
5661 usart_frequency = HAL_RCCEx_GetPLL4CLKFreq();
5662 usart_frequency = usart_frequency / ic_divider;
5663 break;
5664 default:
5665 /* Unexpected case */
5666 break;
5667 }
5668 }
5669 break;
5670
5671 case LL_RCC_USART1_CLKSOURCE_HSI:
5672 case LL_RCC_USART2_CLKSOURCE_HSI:
5673 case LL_RCC_USART3_CLKSOURCE_HSI:
5674 case LL_RCC_USART6_CLKSOURCE_HSI:
5675 case LL_RCC_USART10_CLKSOURCE_HSI:
5676 if (LL_RCC_HSI_IsReady() != 0U)
5677 {
5678 usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
5679 }
5680 break;
5681
5682 case LL_RCC_USART1_CLKSOURCE_MSI:
5683 case LL_RCC_USART2_CLKSOURCE_MSI:
5684 case LL_RCC_USART3_CLKSOURCE_MSI:
5685 case LL_RCC_USART6_CLKSOURCE_MSI:
5686 case LL_RCC_USART10_CLKSOURCE_MSI:
5687 if (LL_RCC_MSI_IsReady() != 0U)
5688 {
5689 usart_frequency = MSI_VALUE;
5690 }
5691 break;
5692
5693 case LL_RCC_USART1_CLKSOURCE_LSE:
5694 case LL_RCC_USART2_CLKSOURCE_LSE:
5695 case LL_RCC_USART3_CLKSOURCE_LSE:
5696 case LL_RCC_USART6_CLKSOURCE_LSE:
5697 case LL_RCC_USART10_CLKSOURCE_LSE:
5698 if (LL_RCC_LSE_IsReady() != 0U)
5699 {
5700 usart_frequency = LSE_VALUE;
5701 }
5702 break;
5703
5704 default:
5705 /* Unexpected case */
5706 break;
5707 }
5708
5709 return usart_frequency;
5710 }
5711
5712 /**
5713 * @brief Return OTGPHYx clock frequency
5714 * @param OTGPHYxSource This parameter can be one of the following values:
5715 * @arg @ref RCCEx_USB_OTGHS1_Clock_Source
5716 * @arg @ref RCCEx_USB_OTGHS2_Clock_Source
5717 * @retval OTGPHY clock frequency (in Hz)
5718 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled
5719 */
RCCEx_GetOTGPHYCLKFreq(uint32_t OTGPHYxSource)5720 static uint32_t RCCEx_GetOTGPHYCLKFreq(uint32_t OTGPHYxSource)
5721 {
5722 uint32_t usb_frequency = RCC_PERIPH_FREQUENCY_NO;
5723
5724 switch (LL_RCC_GetUSBClockSource(OTGPHYxSource))
5725 {
5726 case LL_RCC_OTGPHY1_CLKSOURCE_CLKP:
5727 case LL_RCC_OTGPHY2_CLKSOURCE_CLKP:
5728 usb_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
5729 break;
5730 case LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2:
5731 case LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2:
5732 if (LL_RCC_HSE_IsReady() != 0U)
5733 {
5734 usb_frequency = HSE_VALUE / 2U;
5735 }
5736 break;
5737 case LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC:
5738 case LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC:
5739 if (LL_RCC_HSE_IsReady() != 0U)
5740 {
5741 if (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock() == 0UL)
5742 {
5743 usb_frequency = HSE_VALUE;
5744 }
5745 else
5746 {
5747 usb_frequency = HSE_VALUE / 2U;
5748 }
5749 }
5750 break;
5751 case LL_RCC_OTGPHY1_CLKSOURCE_IC15:
5752 case LL_RCC_OTGPHY2_CLKSOURCE_IC15:
5753 if (LL_RCC_IC15_IsEnabled() != 0U)
5754 {
5755 uint32_t ic_divider = LL_RCC_IC15_GetDivider();
5756 switch (LL_RCC_IC15_GetSource())
5757 {
5758 case LL_RCC_ICCLKSOURCE_PLL1:
5759 usb_frequency = HAL_RCCEx_GetPLL1CLKFreq();
5760 usb_frequency = usb_frequency / ic_divider;
5761 break;
5762 case LL_RCC_ICCLKSOURCE_PLL2:
5763 usb_frequency = HAL_RCCEx_GetPLL2CLKFreq();
5764 usb_frequency = usb_frequency / ic_divider;
5765 break;
5766 case LL_RCC_ICCLKSOURCE_PLL3:
5767 usb_frequency = HAL_RCCEx_GetPLL3CLKFreq();
5768 usb_frequency = usb_frequency / ic_divider;
5769 break;
5770 case LL_RCC_ICCLKSOURCE_PLL4:
5771 usb_frequency = HAL_RCCEx_GetPLL4CLKFreq();
5772 usb_frequency = usb_frequency / ic_divider;
5773 break;
5774 default:
5775 /* Unexpected case */
5776 break;
5777 }
5778 }
5779 break;
5780
5781 default:
5782 /* Unexpected case */
5783 break;
5784 }
5785
5786 return usb_frequency;
5787 }
5788
5789 /**
5790 * @brief Return OTGPHYxCKREF clock frequency
5791 * @param OTGPHYxCKREFSource This parameter can be one of the following values:
5792 * @arg @ref RCCEx_USBPHY1_Clock_Source
5793 * @arg @ref RCCEx_USBPHY2_Clock_Source
5794 * @retval OTGPHYCKREF clock frequency (in Hz)
5795 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled
5796 */
RCCEx_GetOTGPHYCKREFCLKFreq(uint32_t OTGPHYxCKREFSource)5797 static uint32_t RCCEx_GetOTGPHYCKREFCLKFreq(uint32_t OTGPHYxCKREFSource)
5798 {
5799 uint32_t usb_frequency = RCC_PERIPH_FREQUENCY_NO;
5800
5801 switch (LL_RCC_GetUSBClockSource(OTGPHYxCKREFSource))
5802 {
5803 case LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC:
5804 case LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC:
5805 if (LL_RCC_HSE_IsReady() != 0U)
5806 {
5807 if (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock() == 0UL)
5808 {
5809 usb_frequency = HSE_VALUE;
5810 }
5811 else
5812 {
5813 usb_frequency = HSE_VALUE / 2U;
5814 }
5815 }
5816 break;
5817
5818 case LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1:
5819 usb_frequency = RCCEx_GetOTGPHYCLKFreq(LL_RCC_OTGPHY1_CLKSOURCE);
5820 break;
5821
5822 case LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2:
5823 usb_frequency = RCCEx_GetOTGPHYCLKFreq(LL_RCC_OTGPHY2_CLKSOURCE);
5824 break;
5825
5826 default:
5827 /* Unexpected case */
5828 break;
5829 }
5830
5831 return usb_frequency;
5832 }
5833
5834 /**
5835 * @brief Return XSPI clock frequency
5836 * @param XSPIxSource This parameter can be one of the following values:
5837 * @arg @ref RCCEx_XSPI1_Clock_Source
5838 * @arg @ref RCCEx_XSPI2_Clock_Source
5839 * @arg @ref RCCEx_XSPI3_Clock_Source
5840 * @retval XSPI clock frequency (in Hz)
5841 * - @ref RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
5842 */
5843
RCCEx_GetXSPICLKFreq(uint32_t XSPIxSource)5844 static uint32_t RCCEx_GetXSPICLKFreq(uint32_t XSPIxSource)
5845 {
5846 uint32_t xspi_frequency = RCC_PERIPH_FREQUENCY_NO;
5847 uint32_t ic_divider;
5848
5849 switch (LL_RCC_GetXSPIClockSource(XSPIxSource))
5850 {
5851 case LL_RCC_XSPI1_CLKSOURCE_HCLK:
5852 case LL_RCC_XSPI2_CLKSOURCE_HCLK:
5853 case LL_RCC_XSPI3_CLKSOURCE_HCLK:
5854 xspi_frequency = RCCEx_GetHCLKFreq(HAL_RCC_GetSysClockFreq());
5855 break;
5856
5857 case LL_RCC_XSPI1_CLKSOURCE_CLKP:
5858 case LL_RCC_XSPI2_CLKSOURCE_CLKP:
5859 case LL_RCC_XSPI3_CLKSOURCE_CLKP:
5860 xspi_frequency = RCCEx_GetCLKPCLKFreq(LL_RCC_CLKP_CLKSOURCE);
5861 break;
5862
5863 case LL_RCC_XSPI1_CLKSOURCE_IC3:
5864 case LL_RCC_XSPI2_CLKSOURCE_IC3:
5865 case LL_RCC_XSPI3_CLKSOURCE_IC3:
5866 if (LL_RCC_IC3_IsEnabled() != 0U)
5867 {
5868 ic_divider = LL_RCC_IC3_GetDivider();
5869 switch (LL_RCC_IC3_GetSource())
5870 {
5871 case LL_RCC_ICCLKSOURCE_PLL1:
5872 xspi_frequency = HAL_RCCEx_GetPLL1CLKFreq();
5873 xspi_frequency = xspi_frequency / ic_divider;
5874 break;
5875 case LL_RCC_ICCLKSOURCE_PLL2:
5876 xspi_frequency = HAL_RCCEx_GetPLL2CLKFreq();
5877 xspi_frequency = xspi_frequency / ic_divider;
5878 break;
5879 case LL_RCC_ICCLKSOURCE_PLL3:
5880 xspi_frequency = HAL_RCCEx_GetPLL3CLKFreq();
5881 xspi_frequency = xspi_frequency / ic_divider;
5882 break;
5883 case LL_RCC_ICCLKSOURCE_PLL4:
5884 xspi_frequency = HAL_RCCEx_GetPLL4CLKFreq();
5885 xspi_frequency = xspi_frequency / ic_divider;
5886 break;
5887 default:
5888 /* Unexpected case */
5889 break;
5890 }
5891 }
5892 break;
5893
5894 case LL_RCC_XSPI1_CLKSOURCE_IC4:
5895 case LL_RCC_XSPI2_CLKSOURCE_IC4:
5896 case LL_RCC_XSPI3_CLKSOURCE_IC4:
5897 if (LL_RCC_IC4_IsEnabled() != 0U)
5898 {
5899 ic_divider = LL_RCC_IC4_GetDivider();
5900 switch (LL_RCC_IC4_GetSource())
5901 {
5902 case LL_RCC_ICCLKSOURCE_PLL1:
5903 xspi_frequency = HAL_RCCEx_GetPLL1CLKFreq();
5904 xspi_frequency = xspi_frequency / ic_divider;
5905 break;
5906 case LL_RCC_ICCLKSOURCE_PLL2:
5907 xspi_frequency = HAL_RCCEx_GetPLL2CLKFreq();
5908 xspi_frequency = xspi_frequency / ic_divider;
5909 break;
5910 case LL_RCC_ICCLKSOURCE_PLL3:
5911 xspi_frequency = HAL_RCCEx_GetPLL3CLKFreq();
5912 xspi_frequency = xspi_frequency / ic_divider;
5913 break;
5914 case LL_RCC_ICCLKSOURCE_PLL4:
5915 xspi_frequency = HAL_RCCEx_GetPLL4CLKFreq();
5916 xspi_frequency = xspi_frequency / ic_divider;
5917 break;
5918 default:
5919 /* Unexpected case */
5920 break;
5921 }
5922 }
5923 break;
5924
5925 default:
5926 /* Nothing to do */
5927 break;
5928 }
5929
5930 return xspi_frequency;
5931 }
5932
5933 /**
5934 * @}
5935 */
5936
5937 #endif /* HAL_RCC_MODULE_ENABLED */
5938
5939 /**
5940 * @}
5941 */
5942
5943 /**
5944 * @}
5945 */
5946
