1 /**
2 ******************************************************************************
3 * @file stm32n6xx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @brief Extended PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller extension peripheral :
8 * + Power Supply Control Functions
9 * + Low Power Control Functions
10 * + Voltage Monitoring Functions
11 * + Memories Retention Functions
12 * + I/O Pull-Up Pull-Down Configuration Functions
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2023 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### How to use this driver #####
27 ==============================================================================
28 [..]
29 (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply
30 with the following different setups according to hardware:
31 (+) PWR_SMPS_SUPPLY
32 (+) PWR_EXTERNAL_SOURCE_SUPPLY
33
34 (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup.
35
36 (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main
37 internal regulator output voltage. The voltage scaling could be one of
38 the following scales :
39 (+) PWR_REGULATOR_VOLTAGE_SCALE0
40 (+) PWR_REGULATOR_VOLTAGE_SCALE1
41
42 (#) Call HAL_PWREx_GetVoltageRange() function to get the current output
43 voltage applied to the main regulator.
44
45 (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the main
46 internal regulator output voltage in STOP mode. The voltage scaling could be one of
47 the following scales :
48 (+) PWR_REGULATOR_STOP_VOLTAGE_SCALE3
49 (+) PWR_REGULATOR_STOP_VOLTAGE_SCALE5
50
51 (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current output
52 voltage applied to the main regulator in STOP mode.
53
54 (#) Call HAL_PWREx_EnableWakeUpPin() functions to enable the Wake-up pin
55 functionality for the selected pin.
56
57 (#) Call HAL_PWREx_EnableBkupRAMRetention() and HAL_PWREx_DisableBkupRAMRetention()
58 functions to enable and disable BKPSRAM retention in Standby mode.
59
60 (#) Call HAL_PWREx_EnableTCMRetention() and HAL_PWREx_DisableTCMRetention() functions
61 to enable and disable the I-TCM and D-TCM RAMs retention in Standby mode.
62
63 (#) Call HAL_PWREx_EnableTCMFLXRetention() and HAL_PWREx_DisableTCMFLXRetention()
64 functions to enable and disable the I-TCM FLEXMEM retention in Standby mode.
65
66 (#) Call HAL_PWREx_SetPulseLow() function to configure the minimum guaranteed
67 duration of the pwr_on low pulse in Standby mode ( between ~ 0 -> 31 ms).
68
69 (#) Call HAL_PWREx_GetPulseLow() function to get the minimum guaranteed
70 duration of the pwr_on low pulse in Standby mode.
71
72 (#) Call HAL_PWREx_EnableTCMFLXRetention() and HAL_PWREx_DisableTCMFLXRetention()
73 functions to enable and disable the I-TCM FLEXMEM retention in Standby mode.
74
75 (#) Call HAL_PWREx_EnableSMPSPWM() and HAL_PWREx_DisableSMPSPWM() functions to
76 enable and disable the SMPS low-power mode in Stop SVOS range 3.
77
78 (#) Call HAL_PWREx_EnablePullDownOutput() and HAL_PWREx_DisablePullDownOutput()
79 functions to enable and disable the pull down on output voltage during
80 power-down mode.
81
82 (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring()
83 functions to enable and disable the VBAT and Temperature monitoring.
84 When VBAT and Temperature monitoring feature is enables, use
85 HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get
86 respectively the Temperature level and VBAT level.
87
88 (#) Call HAL_PWREx_EnableVDDCOREMonitoring() and HAL_PWREx_EnableVDDCOREMonitoring()
89 functions to enable and disable the VCORE monitoring.
90 When VDDCORE monitoring feature is enables, use HAL_PWREx_GetVDDCORELevel()
91 function to get the current VDDCORE level.
92
93 (#) Call HAL_PWREx_ConfigVDDCORELevel() function to configure the VDDCORE
94 voltage detector low-level selection.
95
96 (#) Call HAL_PWREx_ConfigVddIORange() functions to configure the Vdd IO range:
97 (+) PWR_VDDIO
98 (+) PWR_VDDIO2
99 (+) PWR_VDDIO3
100 (+) PWR_VDDIO4
101 (+) PWR_VDDIO5
102 The voltage range setting could be one of the following values:
103 (+) PWR_VDDIO_RANGE_3V3
104 (+) PWR_VDDIO_RANGE_1V8
105
106 (#) Call HAL_PWREx_GetVddIORange() function to get the current
107 voltage range setting on the selected Vdd IO.
108
109 (#) Call HAL_PWREx_EnableVddIO4RangeSTBY() and HAL_PWREx_DisableVddIO4RangeSTBY()
110 functions to enable and disable the VDD IO4 voltage range Standby mode.
111
112 (#) Call HAL_PWREx_EnableVddIO5RangeSTBY() and HAL_PWREx_DisableVddIO5RangeSTBY()
113 functions to enable and disable the VDD IO5 voltage range Standby mode.
114
115 (#) Call HAL_PWREx_EnableVddUSB() and HAL_PWREx_DisableVddUSB()
116 functions to enable and disable the VDD33USB supply valid.
117
118 (#) Call HAL_PWREx_EnableVddIO2() and HAL_PWREx_DisableVddIO2()
119 functions to enable and disable the VDDIO2 supply valid.
120
121 (#) Call HAL_PWREx_EnableVddIO3() and HAL_PWREx_DisableVddIO3()
122 functions to enable and disable the VDDIO3 supply valid.
123
124 (#) Call HAL_PWREx_EnableVddIO4() and HAL_PWREx_DisableVddIO4()
125 functions to enable and disable the VDDIO4 supply valid.
126
127 (#) Call HAL_PWREx_EnableVddIO5() and HAL_PWREx_DisableVddIO5()
128 functions to enable and disable the VDDIO5 supply valid.
129
130 (#) Call HAL_PWREx_EnableVddA() and HAL_PWREx_DisableVddA()
131 functions to enable and disable the VDDA18ADC supply valid.
132
133 (#) Call HAL_PWREx_ConfigPVM() after setting parameters to be configured
134 (event mode and PVD type) in order to set up the Peripheral Voltage
135 Monitor, then use HAL_PWREx_EnableVddUSBVMEN(), HAL_PWREx_EnableVddIO2VMEN(),
136 HAL_PWREx_EnableVddIO3VMEN(), HAL_PWREx_EnableVddIO4VMEN(),
137 HAL_PWREx_EnableVddIO5VMEN() and HAL_PWREx_EnableVddAVMEN() functions to
138 start the PVM VDDx monitoring.
139 Use HAL_PWREx_DisableVddUSBVMEN(), HAL_PWREx_DisableVddIO2VMEN(),
140 HAL_PWREx_DisableVddIO3VMEN(), HAL_PWREx_DisableVddIO4VMEN(),
141 HAL_PWREx_DisableVddIO5VMEN() and HAL_PWREx_DisableVddAVMEN() to stop
142 the PVM VDDx monitoring.
143 (+) PVM monitored voltages are :
144 (++) VDDUSB
145 (++) VDDIO2
146 (++) VDDIO3
147 (++) VDDIO4
148 (++) VDDIO5
149 (++) VDDA
150
151 (#) Call HAL_PWREx_PVD_PVM_IRQHandler() function to handle the PWR PVD and
152 PVM interrupt request.
153
154 @endverbatim
155 ******************************************************************************
156 */
157
158 /* Includes ------------------------------------------------------------------*/
159 #include "stm32n6xx_hal.h"
160
161 /** @addtogroup STM32N6xx_HAL_Driver
162 * @{
163 */
164
165 /** @defgroup PWREx PWREx
166 * @brief PWR Extended HAL module driver
167 * @{
168 */
169
170 #if defined (HAL_PWR_MODULE_ENABLED)
171
172 /* Private typedef -----------------------------------------------------------*/
173 /* Private define ------------------------------------------------------------*/
174
175 /** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value
176 * @{
177 */
178 #define PWR_FLAG_SETTING_DELAY (1000U)
179 /**
180 * @}
181 */
182
183 /** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets
184 * @{
185 */
186 /* Wake-Up Pins EXTI register mask */
187 #define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM60 | EXTI_IMR2_IM61 |\
188 EXTI_IMR2_IM62 | EXTI_IMR2_IM63 )
189
190 /* Wake-Up Pins PWR Pin Pull shift offsets */
191 #define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)
192 /**
193 * @}
194 */
195
196 /** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask
197 * @{
198 */
199 #define PVM_RISING_EDGE (1U) /*!< Mask for rising edge set as PVM trigger */
200 #define PVM_FALLING_EDGE (2U) /*!< Mask for falling edge set as PVM trigger */
201 #define PVM_MODE_IT (4U) /*!< Mask for interruption yielded by PVM threshold crossing */
202 #define PVM_MODE_EVT (8U) /*!< Mask for event yielded by PVM threshold crossing */
203 /**
204 * @}
205 */
206
207 /** @defgroup PWR_VDDCOREVM_Mode_Mask PWR VddCORE VM Mode Mask
208 * @{
209 */
210 #define VDDCOREVM_RISING_EDGE (1U) /*!< Mask for rising edge set as PVM trigger */
211 #define VDDCOREVM_FALLING_EDGE (2U) /*!< Mask for falling edge set as PVM trigger */
212 #define VDDCOREVM_MODE_IT (4U) /*!< Mask for interruption yielded by PVM threshold crossing */
213 #define VDDCOREVM_MODE_EVT (8U) /*!< Mask for event yielded by PVM threshold crossing */
214 /**
215 * @}
216 */
217
218
219
220 /* Private macro -------------------------------------------------------------*/
221 /* Private variables ---------------------------------------------------------*/
222 /* Private function prototypes -----------------------------------------------*/
223 /* Exported functions --------------------------------------------------------*/
224
225 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
226 * @{
227 */
228
229 /** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
230 * @brief Power supply control functions
231 *
232 @verbatim
233 ===============================================================================
234 ##### Power supply control functions #####
235 ===============================================================================
236 [..]
237 This section provides functions allowing to control power supply.
238
239 (+) The STM32N6 series devices allows two different supply configurations:
240 Direct SMPS supply and external supply.
241
242 (#) After a system reset, the software must configure the used supply configuration
243 in PWR_CR1 using HAL_PWREx_ConfigSupply() function before changing VOS in PWR_VOSCR,
244 or the RCC sys_ck frequency.
245
246 @endverbatim
247 * @{
248 */
249
250 /**
251 * @brief Configure the system Power Supply.
252 * @param SupplySource : Specifies the Power Supply source to set after a
253 * system startup.
254 * This parameter can be one of the following values :
255 * @arg @ref PWR_SMPS_SUPPLY : VCORE power domains are supplied
256 * from SMPS step-down converter
257 * according to VOS.
258 * @arg @ref PWR_EXTERNAL_SOURCE_SUPPLY : VCORE supplied from external source.
259 * SMPS step-down converter disabled.
260 * @note: The power supply configuration can be written only one time after POR.
261 * @note: The power supply configuration is not reset by wakeup from Standby mode and
262 * application reset, but only reset by VDD POR.
263 * @retval HAL status.
264 */
HAL_PWREx_ConfigSupply(uint32_t SupplySource)265 HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)
266 {
267 uint32_t tickstart;
268
269 /* Check the parameters */
270 assert_param(IS_PWR_SUPPLY(SupplySource));
271
272 /* Set the power supply configuration */
273 MODIFY_REG(PWR->CR1, PWR_SUPPLY_CONFIG_MASK, SupplySource);
274
275 /* Get tick */
276 tickstart = HAL_GetTick();
277
278 /* Wait till voltage level flag is set */
279 while ((PWR->VOSCR & PWR_VOSCR_ACTVOSRDY) == 0U)
280 {
281 if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY)
282 {
283 return HAL_ERROR;
284 }
285 }
286
287 return HAL_OK;
288 }
289
290 /**
291 * @brief Get the power supply configuration.
292 * @retval The supply configuration.
293 */
HAL_PWREx_GetSupplyConfig(void)294 uint32_t HAL_PWREx_GetSupplyConfig(void)
295 {
296 return (PWR->CR1 & PWR_SUPPLY_CONFIG_MASK);
297 }
298
299 /**
300 * @brief Configure the main internal regulator output voltage.
301 * @param VoltageScaling : Specifies the regulator output voltage to achieve
302 * a tradeoff between performance and power
303 * consumption.
304 * This parameter can be one of the following values :
305 * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage scaling range 0 (highest frequency).
306 * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage scaling range 1 (lowest power).
307 * @note After reset, the system starts from HSI with VOS low.
308 * @note When increasing the performance, the voltage scaling must be changed
309 * before increasing the system frequency.
310 * When decreasing performance, the system frequency must first be decreased
311 * before changing the voltage scaling.
312 * @note When exiting from Stop mode or Standby mode, the Run mode voltage
313 * scaling is reset to the default VOS low value.
314 * @retval HAL Status
315 */
HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)316 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
317 {
318 uint32_t tickstart;
319
320 /* Check the parameters */
321 assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
322
323 /* Set the voltage range */
324 MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, VoltageScaling);
325
326 /* Get tick */
327 tickstart = HAL_GetTick();
328
329 /* Wait till voltage level flag is set */
330 while ((PWR->VOSCR & PWR_VOSCR_VOSRDY) == 0U)
331 {
332 if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY)
333 {
334 return HAL_ERROR;
335 }
336 }
337
338 return HAL_OK;
339 }
340
341 /**
342 * @brief Get the main internal regulator output voltage. Reflecting the last
343 * VOS value applied to the PMU.
344 * @retval The current applied VOS selection.
345 */
HAL_PWREx_GetVoltageRange(void)346 uint32_t HAL_PWREx_GetVoltageRange(void)
347 {
348 /* Get the active voltage scaling */
349 return ((PWR->VOSCR & PWR_VOSCR_ACTVOS) >> PWR_VOSCR_ACTVOS_Pos);
350 }
351
352 /**
353 * @brief Configure the main internal regulator output voltage in STOP mode.
354 * @param VoltageScaling : Specifies the regulator output voltage when the
355 * system enters Stop mode to achieve a tradeoff between performance
356 * and power consumption.
357 * This parameter can be one of the following values:
358 * @arg PWR_REGULATOR_STOP_VOLTAGE_SCALE3 : System Stop mode voltage scaling range 3 (highest frequency).
359 * @arg PWR_REGULATOR_STOP_VOLTAGE_SCALE5 : System Stop mode voltage scaling range 5 (lowest power).
360 * @retval None.
361 */
HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling)362 void HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling)
363 {
364 /* Check the parameters */
365 assert_param(IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VoltageScaling));
366
367 /* Return the stop mode voltage range */
368 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_SVOS, VoltageScaling);
369 }
370
371 /**
372 * @brief Get the main internal regulator output voltage in STOP mode.
373 * @retval The actual applied SVOS selection.
374 */
HAL_PWREx_GetStopModeVoltageRange(void)375 uint32_t HAL_PWREx_GetStopModeVoltageRange(void)
376 {
377 /* Return the stop voltage scaling */
378 return (PWR->CPUCR & PWR_CPUCR_SVOS);
379 }
380 /**
381 * @}
382 */
383
384 /** @defgroup PWREx_Exported_Functions_Group2 Wakeup Pins configuration functions
385 * @brief Wakeup Pins configuration functions
386 *
387 @verbatim
388 ===============================================================================
389 ##### Wakeup Pins configuration functions #####
390 ===============================================================================
391 [..]
392
393 *** Wakeup Pins configuration ****
394 ===================================
395 [..]
396 Wakeup pins allow the system to exit from Standby mode. The configuration
397 of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams)
398 function with:
399 (+) sPinParams: structure to enable and configure a wakeup pin:
400 (++) WakeUpPin: Wakeup pin to be enabled.
401 (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
402 (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
403 [..]
404 The wakeup pins are internally connected to the EXTI lines [60-63] to
405 generate an interrupt if enabled.
406 [..]
407 When a wakeup pin event is received the HAL_PWR_WAKEUP_PIN_IRQHandler is
408 called and the appropriate flag is set in the PWR_WKUPSR register. Then in
409 the HAL_PWR_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be
410 cleared and the appropriate user callback will be called. The user can add
411 his own code by customization of function pointer HAL_PWR_WKUPx_Callback.
412
413 @endverbatim
414 * @{
415 */
416 /**
417 * @brief Enable the Wake-up PINx functionality.
418 * @param sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that
419 * contains the configuration information for the wake-up
420 * Pin.
421 * @retval None.
422 */
HAL_PWREx_EnableWakeUpPin(const PWREx_WakeupPinTypeDef * sPinParams)423 void HAL_PWREx_EnableWakeUpPin(const PWREx_WakeupPinTypeDef *sPinParams)
424 {
425 uint32_t pinConfig;
426 uint32_t regMask;
427 const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1;
428
429 /* Check the parameters */
430 assert_param(IS_PWR_WAKEUP_PIN(sPinParams->WakeUpPin));
431 assert_param(IS_PWR_WAKEUP_PIN_POLARITY(sPinParams->PinPolarity));
432 assert_param(IS_PWR_WAKEUP_PIN_PULL(sPinParams->PinPull));
433
434 pinConfig = sPinParams->WakeUpPin | \
435 (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \
436 (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) + \
437 PWR_WKUPEPR_WKUPPUPD1_Pos) & 0x1FU));
438
439 regMask = sPinParams->WakeUpPin | \
440 (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
441 (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU));
442
443 /* Enable and Specify the Wake-Up pin polarity and the pull configuration
444 for the event detection (rising or falling edge) */
445 MODIFY_REG(PWR->WKUPEPR, regMask, pinConfig);
446
447 /* Configure the Wakeup Pin EXTI Line */
448 MODIFY_REG(EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM60_Pos));
449 }
450 /**
451 * @}
452 */
453
454
455 /** @defgroup PWREx_Exported_Functions_Group3 Memories Retention Functions
456 * @brief Memories Retention Functions
457 *
458 @verbatim
459 ===============================================================================
460 ##### Memories Retention Functions #####
461 ===============================================================================
462 [..]
463
464 *** Backup RAM (BKPSRAM) retention ****
465 =======================================
466 [..]
467 By default the content of BKPSRAM memories aren't retained in Standby mode.
468 By setting the BKPRBSEN bit in the PWR_BDCR2 register using the
469 HAL_PWREx_EnableBkupRAMRetention() function, the content of these memories
470 are retained even in Standby mode.
471
472 *** TCM RAMs and I-TCM FLEXMEM retention ****
473 =======================================
474 [..]
475 By default the content of TCM RAMs and I-TCM FLEXMEM aren't retained in
476 Standby mode.
477
478 By setting the TCMRBSEN bit in the PWR_CR4 register using the
479 HAL_PWREx_EnableTCMRetention() function, the content of these memories
480 are retained even in Standby mode.
481
482 By setting the TCMFLXRBSEN bit in the PWR_CR4 register using the
483 HAL_PWREx_EnableTCMFLXRetention () function, the content of these memories
484 are retained even in Standby mode.
485
486 @endverbatim
487 * @{
488 */
489
490 /**
491 * @brief Enable the Backup RAM retention in Standby and VBAT modes.
492 * @note After reset, PWR_BDCR2 is write-protected.
493 * DBP must be set in PWR_DBPCR to disable the write protection.
494 * @retval None.
495 */
HAL_PWREx_EnableBkupRAMRetention(void)496 void HAL_PWREx_EnableBkupRAMRetention(void)
497 {
498 SET_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN);
499 }
500
501 /**
502 * @brief Disable the Backup RAM retention in Standby and VBAT modes.
503 * @note After reset, PWR_BDCR2 is write-protected.
504 * DBP must be set in PWR_DBPCR to disable the write protection.
505 * @retval None.
506 */
HAL_PWREx_DisableBkupRAMRetention(void)507 void HAL_PWREx_DisableBkupRAMRetention(void)
508 {
509 CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN);
510 }
511
512 /**
513 * @brief Enable the TCM RAMs retention in Standby mode.
514 * @retval None.
515 */
HAL_PWREx_EnableTCMRetention(void)516 void HAL_PWREx_EnableTCMRetention(void)
517 {
518 SET_BIT(PWR->CR4, PWR_CR4_TCMRBSEN);
519 }
520
521 /**
522 * @brief Disable the TCM RAMs retention in Standby mode.
523 * @retval None.
524 */
HAL_PWREx_DisableTCMRetention(void)525 void HAL_PWREx_DisableTCMRetention(void)
526 {
527 CLEAR_BIT(PWR->CR4, PWR_CR4_TCMRBSEN);
528 }
529
530 /**
531 * @brief Enable the I-TCM FLEXMEM retention in Standby mode.
532 * @retval None.
533 */
HAL_PWREx_EnableTCMFLXRetention(void)534 void HAL_PWREx_EnableTCMFLXRetention(void)
535 {
536 SET_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN);
537 }
538
539 /**
540 * @brief Disable the I-TCM FLEXMEM retention in Standby mode.
541 * @retval None.
542 */
HAL_PWREx_DisableTCMFLXRetention(void)543 void HAL_PWREx_DisableTCMFLXRetention(void)
544 {
545 CLEAR_BIT(PWR->CR4, PWR_CR4_TCMFLXRBSEN);
546 }
547 /**
548 * @}
549 */
550
551
552 /** @defgroup PWREx_Exported_Functions_Group4 Low Power Control Functions
553 * @brief Low Power Control Functions
554 *
555 @verbatim
556 ===============================================================================
557 ##### Low Power Control Functions #####
558 ===============================================================================
559 [..]
560 @endverbatim
561 * @{
562 */
563
564 /**
565 * @brief Configure the pwr_on pulse low configuration.
566 * @param Pulselowtime : Specifies minimum guaranteed duration of
567 the pwr_on low pulse in Standby mode.
568 * This parameter can be a value between 0 and 31:
569 * 0: No guaranteed minimum low time.
570 * 1: 1* 32 LSI cycles= ~ 1 ms guaranteed minimum low time.
571 * X: X* 32 LSI cycles= ~ X ms guaranteed minimum low time.
572 * @retval None.
573 */
HAL_PWREx_SetPulseLow(uint32_t Pulselowtime)574 void HAL_PWREx_SetPulseLow(uint32_t Pulselowtime)
575 {
576 assert_param(IS_PWR_PULSE_LOW_TIME(Pulselowtime));
577
578 /* Set the pwr_on pulse low configuration */
579 MODIFY_REG(PWR->CR1, PWR_CR1_POPL_Msk, (Pulselowtime << PWR_CR1_POPL_Pos));
580 }
581
582 /**
583 * @brief Get the pwr_on pulse low configuration.
584 * @retval The actual applied minimum guaranteed duration of the
585 * pwr_on low pulse in Standby mode.
586 */
HAL_PWREx_GetPulseLow(void)587 uint32_t HAL_PWREx_GetPulseLow(void)
588 {
589 /* Return the stop voltage scaling */
590 return ((PWR->CR1 & PWR_CR1_POPL_Msk) >> PWR_CR1_POPL_Pos);
591 }
592
593 /**
594 * @brief Enable SMPS low-power mode (SVOS range 3 only).
595 * @note LPDS08V bit is used to keep the SMPS in PWM mode (MR) in Stop SVOS range 3.
596 * @retval None.
597 */
HAL_PWREx_EnableSMPSPWM(void)598 void HAL_PWREx_EnableSMPSPWM(void)
599 {
600 SET_BIT(PWR->CR1, PWR_CR1_LPDS08V);
601 }
602
603 /**
604 * @brief Disable SMPS low-power mode (SVOS range 3 only).
605 * @retval None.
606 */
HAL_PWREx_DisableSMPSPWM(void)607 void HAL_PWREx_DisableSMPSPWM(void)
608 {
609 CLEAR_BIT(PWR->CR1, PWR_CR1_LPDS08V);
610 }
611
612 /**
613 * @brief Enable the pull down on output voltage during power-down mode.
614 * @retval None.
615 */
HAL_PWREx_EnablePullDownOutput(void)616 void HAL_PWREx_EnablePullDownOutput(void)
617 {
618 SET_BIT(PWR->CR1, PWR_CR1_MODE_PDN);
619 }
620
621 /**
622 * @brief Disable the pull down on output voltage during power-down mode.
623 * @retval None.
624 */
HAL_PWREx_DisablePullDownOutput(void)625 void HAL_PWREx_DisablePullDownOutput(void)
626 {
627 CLEAR_BIT(PWR->CR1, PWR_CR1_MODE_PDN);
628 }
629 /**
630 * @}
631 */
632
633 /** @defgroup PWREx_Exported_Functions_Group5 Power Monitoring functions
634 * @brief Power Monitoring functions
635 *
636 @verbatim
637 ===============================================================================
638 ##### Power Monitoring functions #####
639 ===============================================================================
640
641 *** VBAT and Temperature supervision ***
642 ========================================
643 [..]
644 (+) The VBAT battery voltage supply can be monitored by comparing it with
645 two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags
646 in the PWR control register 2 (PWR_BDCR1), indicate if VBAT is higher or
647 lower than the threshold.
648 (+) The temperature can be monitored by comparing it with two threshold
649 levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR
650 control register 2 (PWR_BDCR1), indicate whether the device temperature
651 is higher or lower than the threshold.
652 (+) The VBAT and the temperature monitoring is enabled by
653 HAL_PWREx_EnableMonitoring() function and disabled by
654 HAL_PWREx_DisableMonitoring() function.
655 (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can
656 be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
657 PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
658 (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature
659 level which can be :
660 PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
661 PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.
662
663 @endverbatim
664 * @{
665 */
666
667 /**
668 * @brief Enable the VBAT and temperature monitoring.
669 * @note After reset, PWR_BDCR1 is write-protected.
670 * DBP must be set in PWR_DBPCR to disable the write protection.
671 * @retval HAL status.
672 */
HAL_PWREx_EnableMonitoring(void)673 void HAL_PWREx_EnableMonitoring(void)
674 {
675 /* Enable the VBAT and Temperature monitoring */
676 SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
677 }
678
679 /**
680 * @brief Disable the VBAT and temperature monitoring.
681 * @note After reset, PWR_BDCR1 is write-protected.
682 * DBP must be set in PWR_DBPCR to disable the write protection.
683 * @retval HAL status.
684 */
HAL_PWREx_DisableMonitoring(void)685 void HAL_PWREx_DisableMonitoring(void)
686 {
687 /* Disable the VBAT and Temperature monitoring */
688 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
689 }
690
691 /**
692 * @brief Indicate whether the junction temperature is between, above or below
693 * the thresholds.
694 * @retval Temperature level.
695 */
HAL_PWREx_GetTemperatureLevel(void)696 uint32_t HAL_PWREx_GetTemperatureLevel(void)
697 {
698 uint32_t tempLevel;
699 uint32_t regValue;
700
701 /* Read the temperature flags */
702 regValue = READ_BIT(PWR->BDCR1, (PWR_BDCR1_TEMPH | PWR_BDCR1_TEMPL));
703
704 /* Check if the temperature is below the threshold */
705 if (regValue == PWR_BDCR1_TEMPL)
706 {
707 tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD;
708 }
709 /* Check if the temperature is above the threshold */
710 else if (regValue == PWR_BDCR1_TEMPH)
711 {
712 tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD;
713 }
714 /* The temperature is between the thresholds */
715 else
716 {
717 tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD;
718 }
719
720 return tempLevel;
721 }
722
723 /**
724 * @brief Indicate whether the Battery voltage level is between, above or below
725 * the thresholds.
726 * @retval VBAT level.
727 */
HAL_PWREx_GetVBATLevel(void)728 uint32_t HAL_PWREx_GetVBATLevel(void)
729 {
730 uint32_t vbatLevel;
731 uint32_t regValue;
732
733 /* Read the VBAT flags */
734 regValue = READ_BIT(PWR->BDCR1, (PWR_BDCR1_VBATH | PWR_BDCR1_VBATL));
735
736 /* Check if the VBAT is below the threshold */
737 if (regValue == PWR_BDCR1_VBATL)
738 {
739 vbatLevel = PWR_VBAT_BELOW_LOW_THRESHOLD;
740 }
741 /* Check if the VBAT is above the threshold */
742 else if (regValue == PWR_BDCR1_VBATH)
743 {
744 vbatLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD;
745 }
746 /* The VBAT is between the thresholds */
747 else
748 {
749 vbatLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD;
750 }
751
752 return vbatLevel;
753 }
754
755 /**
756 * @brief Enable the VDDCORE monitoring.
757 * @retval HAL status.
758 */
HAL_PWREx_EnableVDDCOREMonitoring(void)759 void HAL_PWREx_EnableVDDCOREMonitoring(void)
760 {
761 /* Enable the VDDCORE monitoring */
762 SET_BIT(PWR->CR3, PWR_CR3_VCOREMONEN);
763 }
764
765 /**
766 * @brief Disable the VDDCORE monitoring.
767 * @retval HAL status.
768 */
HAL_PWREx_DisableVDDCOREMonitoring(void)769 void HAL_PWREx_DisableVDDCOREMonitoring(void)
770 {
771 /* Disable the VDDCORE monitoring */
772 CLEAR_BIT(PWR->CR3, PWR_CR3_VCOREMONEN);
773 }
774
775 /**
776 * @brief Configure the VDDCORE voltage detector low-level selection.
777 * @param pConfigVddCOREVM : Pointer to a PWR_VddCOREVMTypeDef structure that contains the
778 * PVM configuration information (LowVoltageThreshold and Mode).
779 * @retval None.
780 */
HAL_PWREx_ConfigVDDCOREVM(const PWR_VddCOREVMTypeDef * pConfigVddCOREVM)781 void HAL_PWREx_ConfigVDDCOREVM(const PWR_VddCOREVMTypeDef *pConfigVddCOREVM)
782 {
783 assert_param(IS_PWR_VDDCOREVM_LEVEL(pConfigVddCOREVM->LowVoltageThreshold));
784 assert_param(IS_PWR_VDDCOREVM_MODE(pConfigVddCOREVM->Mode));
785
786 /* Disable VDDCORE monitoring Event/Interrupt */
787 __HAL_PWR_VCOREVM_EXTI_DISABLE_EVENT();
788 __HAL_PWR_VCOREVM_EXTI_DISABLE_IT();
789 __HAL_PWR_VCOREVM_EXTI_DISABLE_RISING_EDGE();
790 __HAL_PWR_VCOREVM_EXTI_DISABLE_FALLING_EDGE();
791
792 /* Set the VDDCORE voltage detector low-level selection */
793 MODIFY_REG(PWR->CR3, PWR_CR3_VCORELLS_Msk, pConfigVddCOREVM->LowVoltageThreshold);
794
795 /* Configure the VDDCORE monitoring in interrupt mode */
796 if ((pConfigVddCOREVM->Mode & VDDCOREVM_MODE_IT) == VDDCOREVM_MODE_IT)
797 {
798 __HAL_PWR_VCOREVM_EXTI_ENABLE_IT();
799 }
800
801 /* Configure the VDDCORE monitoring in event mode */
802 if ((pConfigVddCOREVM->Mode & VDDCOREVM_MODE_EVT) == VDDCOREVM_MODE_EVT)
803 {
804 __HAL_PWR_VCOREVM_EXTI_ENABLE_EVENT();
805 }
806
807 /* Rising edge configuration */
808 if ((pConfigVddCOREVM->Mode & VDDCOREVM_RISING_EDGE) == VDDCOREVM_RISING_EDGE)
809 {
810 __HAL_PWR_VCOREVM_EXTI_ENABLE_RISING_EDGE();
811 }
812
813 /* Falling edge configuration */
814 if ((pConfigVddCOREVM->Mode & VDDCOREVM_FALLING_EDGE) == VDDCOREVM_FALLING_EDGE)
815 {
816 __HAL_PWR_VCOREVM_EXTI_ENABLE_FALLING_EDGE();
817 }
818 }
819
820 /**
821 * @brief Indicate whether the VDDCORE level is between, above or below
822 * the thresholds.
823 * @retval VDDCORE level.
824 */
HAL_PWREx_GetVDDCORELevel(void)825 uint32_t HAL_PWREx_GetVDDCORELevel(void)
826 {
827 uint32_t vcoreLevel;
828 uint32_t regValue;
829
830 /* Read the VCORE flags */
831 regValue = READ_BIT(PWR->CR3, (PWR_CR3_VCOREH | PWR_CR3_VCOREL));
832
833 /* Check if the VCORE is below the threshold */
834 if (regValue == PWR_CR3_VCOREL)
835 {
836 vcoreLevel = PWR_VDDCORE_BELOW_LOW_THRESHOLD;
837 }
838 /* Check if the VCORE is above the threshold */
839 else if (regValue == PWR_CR3_VCOREH)
840 {
841 vcoreLevel = PWR_VDDCORE_ABOVE_HIGH_THRESHOLD;
842 }
843 /* The VCORE is between the thresholds */
844 else
845 {
846 vcoreLevel = PWR_VDDCORE_BETWEEN_HIGH_LOW_THRESHOLD;
847 }
848
849 return vcoreLevel;
850 }
851
852 /**
853 * @brief Configure the VDD I/O voltage range.
854 * @param VddIOPort VDD I/O
855 * This parameter can be one of the following values:
856 * @arg @ref PWR_VDDIO Vdd IO
857 * @arg @ref PWR_VDDIO2 Vdd IO2
858 * @arg @ref PWR_VDDIO3 Vdd IO3
859 * @arg @ref PWR_VDDIO4 Vdd IO4
860 * @arg @ref PWR_VDDIO5 Vdd IO5
861 * @param VoltageRange Voltage range
862 * This parameter can be one of the following values:
863 * @arg @ref PWR_VDDIO_RANGE_3V3 3v3 voltage range
864 * @arg @ref PWR_VDDIO_RANGE_1V8 1v8 voltage range
865 * @note HSLV_VDDIOx option bit must be set to allow 1v8 voltage
866 * range operation.
867 * @note Setting this configuration while VDDIOx is in 3v3 range
868 * damages the device.
869 * @retval None.
870 */
HAL_PWREx_ConfigVddIORange(uint32_t VddIOPort,uint32_t VoltageRange)871 void HAL_PWREx_ConfigVddIORange(uint32_t VddIOPort, uint32_t VoltageRange)
872 {
873 /* Check the parameters */
874 assert_param(IS_PWR_VDDIO(VddIOPort));
875 assert_param(IS_PWR_VDDIO_RANGE(VoltageRange));
876
877 switch (VddIOPort)
878 {
879 case PWR_VDDIO:
880 MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIOVRSEL, VoltageRange << PWR_SVMCR3_VDDIOVRSEL_Pos);
881 break;
882
883 case PWR_VDDIO2:
884 MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VRSEL, VoltageRange << PWR_SVMCR3_VDDIO2VRSEL_Pos);
885 break;
886
887 case PWR_VDDIO3:
888 MODIFY_REG(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VRSEL, VoltageRange << PWR_SVMCR3_VDDIO3VRSEL_Pos);
889 break;
890
891 case PWR_VDDIO4:
892 MODIFY_REG(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSEL, VoltageRange << PWR_SVMCR1_VDDIO4VRSEL_Pos);
893 break;
894
895 case PWR_VDDIO5:
896 MODIFY_REG(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL, VoltageRange << PWR_SVMCR2_VDDIO5VRSEL_Pos);
897 break;
898
899 default:
900 break;
901 }
902 }
903
904 /**
905 * @brief Configure the VDD I/O voltage range.
906 * @param VddIOPort VDD I/O
907 * This parameter can be one of the following values:
908 * @arg @ref PWR_VDDIO Vdd IO
909 * @arg @ref PWR_VDDIO2 Vdd IO2
910 * @arg @ref PWR_VDDIO3 Vdd IO3
911 * @arg @ref PWR_VDDIO4 Vdd IO4
912 * @arg @ref PWR_VDDIO5 Vdd IO5
913 * @retval The voltage range:
914 * @arg @ref PWR_VDDIO_RANGE_3V3 3v3 voltage range
915 * @arg @ref PWR_VDDIO_RANGE_1V8 1v8 voltage range
916 */
HAL_PWREx_GetVddIORange(uint32_t VddIOPort)917 uint32_t HAL_PWREx_GetVddIORange(uint32_t VddIOPort)
918 {
919 uint32_t voltage_range = 0U;
920
921 /* Check the parameters */
922 assert_param(IS_PWR_VDDIO(VddIOPort));
923
924 switch (VddIOPort)
925 {
926 case PWR_VDDIO:
927 voltage_range = (READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIOVRSEL) >> PWR_SVMCR3_VDDIOVRSEL_Pos);
928 break;
929
930 case PWR_VDDIO2:
931 voltage_range = (READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VRSEL) >> PWR_SVMCR3_VDDIO2VRSEL_Pos);
932 break;
933
934 case PWR_VDDIO3:
935 voltage_range = (READ_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VRSEL) >> PWR_SVMCR3_VDDIO3VRSEL_Pos);
936 break;
937
938 case PWR_VDDIO4:
939 voltage_range = (READ_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSEL) >> PWR_SVMCR1_VDDIO4VRSEL_Pos);
940 break;
941
942 case PWR_VDDIO5:
943 voltage_range = (READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL) >> PWR_SVMCR2_VDDIO5VRSEL_Pos);
944 break;
945
946 default:
947 break;
948 }
949 return voltage_range;
950 }
951
952 /**
953 * @brief Enable VDD IO4 voltage range Standby mode.
954 * @note When this bit is set, the VDDIO4VRSEL configuration
955 * is retained in Standby mode.
956 * @note This bit must be set if the VDDIO4 is in 1v8 range
957 * in Standby mode, and when exiting Standby mode.
958 * @note It must not be set when VDDIO4 is in 3v3 range in
959 * Standby mode, or when exiting Standby mode.
960 * @retval None.
961 */
HAL_PWREx_EnableVddIO4RangeSTBY(void)962 void HAL_PWREx_EnableVddIO4RangeSTBY(void)
963 {
964 SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY);
965 }
966
967 /**
968 * @brief Disable VDD IO4 voltage range Standby mode.
969 * @retval None.
970 */
HAL_PWREx_DisableVddIO4RangeSTBY(void)971 void HAL_PWREx_DisableVddIO4RangeSTBY(void)
972 {
973 CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VRSTBY);
974 }
975
976 /**
977 * @brief Enable VDD IO5 voltage range Standby mode.
978 * @note When this bit is set, the VDDIO5VRSEL configuration
979 * is retained in Standby mode.
980 * @note This bit must be set if the VDDIO5 is in 1v8 range
981 * in Standby mode, and when exiting Standby mode.
982 * @note It must not be set when VDDIO5 is in 3v3 range in
983 * Standby mode, or when exiting Standby mode.
984 * @retval None.
985 */
HAL_PWREx_EnableVddIO5RangeSTBY(void)986 void HAL_PWREx_EnableVddIO5RangeSTBY(void)
987 {
988 SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY);
989 }
990
991 /**
992 * @brief Disable VDD IO5 voltage range Standby mode.
993 * @retval None.
994 */
HAL_PWREx_DisableVddIO5RangeSTBY(void)995 void HAL_PWREx_DisableVddIO5RangeSTBY(void)
996 {
997 CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY);
998 }
999
1000 /**
1001 * @brief Enable VDDUSB supply valid.
1002 * @note Setting this bit is mandatory to use the USB2 HS PHYs.
1003 * is present for consumption saving.
1004 * @retval None.
1005 */
HAL_PWREx_EnableVddUSB(void)1006 void HAL_PWREx_EnableVddUSB(void)
1007 {
1008 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV);
1009 }
1010
1011 /**
1012 * @brief Disable VDDUSB supply valid.
1013 * @retval None.
1014 */
HAL_PWREx_DisableVddUSB(void)1015 void HAL_PWREx_DisableVddUSB(void)
1016 {
1017 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33SV);
1018 }
1019
1020 /**
1021 * @brief Enable VDDIO2 supply valid.
1022 * @note Setting this bit is mandatory to use PO[5:0] and PP[15:0] I/Os.
1023 * @retval None.
1024 */
HAL_PWREx_EnableVddIO2(void)1025 void HAL_PWREx_EnableVddIO2(void)
1026 {
1027 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV);
1028 }
1029
1030 /**
1031 * @brief Disable VDDIO2 supply valid.
1032 * @retval None.
1033 */
HAL_PWREx_DisableVddIO2(void)1034 void HAL_PWREx_DisableVddIO2(void)
1035 {
1036 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2SV);
1037 }
1038
1039 /**
1040 * @brief Enable VDDIO3 supply valid.
1041 * @note Setting this bit is mandatory to use PN[12:0] I/Os.
1042 * @retval None.
1043 */
HAL_PWREx_EnableVddIO3(void)1044 void HAL_PWREx_EnableVddIO3(void)
1045 {
1046 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV);
1047 }
1048
1049 /**
1050 * @brief Disable VDDIO3 supply valid.
1051 * @retval None.
1052 */
HAL_PWREx_DisableVddIO3(void)1053 void HAL_PWREx_DisableVddIO3(void)
1054 {
1055 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3SV);
1056 }
1057
1058 /**
1059 * @brief Enable VDDIO4 supply valid.
1060 * @note Setting this bit is mandatory to use PB[9,8], PC[12:6], and PD[2] I/Os.
1061 * @retval None.
1062 */
HAL_PWREx_EnableVddIO4(void)1063 void HAL_PWREx_EnableVddIO4(void)
1064 {
1065 SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV);
1066 }
1067
1068 /**
1069 * @brief Disable VDDIO4 supply valid.
1070 * @retval None.
1071 */
HAL_PWREx_DisableVddIO4(void)1072 void HAL_PWREx_DisableVddIO4(void)
1073 {
1074 CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4SV);
1075 }
1076
1077 /**
1078 * @brief Enable VDDIO5 supply valid.
1079 * @note Setting this bit is mandatory to use PN[12:0] I/Os.
1080 * @retval None.
1081 */
HAL_PWREx_EnableVddIO5(void)1082 void HAL_PWREx_EnableVddIO5(void)
1083 {
1084 SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV);
1085 }
1086
1087 /**
1088 * @brief Disable VDDIO5 supply valid.
1089 * @retval None.
1090 */
HAL_PWREx_DisableVddIO5(void)1091 void HAL_PWREx_DisableVddIO5(void)
1092 {
1093 CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV);
1094 }
1095
1096 /**
1097 * @brief Enable VDDA supply valid.
1098 * @note Setting this bit is mandatory to use the analog to digital converters.
1099 * @retval None.
1100 */
HAL_PWREx_EnableVddA(void)1101 void HAL_PWREx_EnableVddA(void)
1102 {
1103 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV);
1104 }
1105
1106 /**
1107 * @brief Disable VDDA supply valid.
1108 * @retval None.
1109 */
HAL_PWREx_DisableVddA(void)1110 void HAL_PWREx_DisableVddA(void)
1111 {
1112 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_ASV);
1113 }
1114
1115 /**
1116 * @brief Enable the VDD33USB independent USB 33 voltage monitor.
1117 * @retval None.
1118 */
HAL_PWREx_EnableVddUSBVMEN(void)1119 void HAL_PWREx_EnableVddUSBVMEN(void)
1120 {
1121 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN);
1122 }
1123
1124 /**
1125 * @brief Disable the VDD33USB independent USB 33 voltage monitor.
1126 * @retval None.
1127 */
HAL_PWREx_DisableVddUSBVMEN(void)1128 void HAL_PWREx_DisableVddUSBVMEN(void)
1129 {
1130 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_USB33VMEN);
1131 }
1132
1133 /**
1134 * @brief Enable the VDDIO2 independent voltage monitor.
1135 * @retval None.
1136 */
HAL_PWREx_EnableVddIO2VMEN(void)1137 void HAL_PWREx_EnableVddIO2VMEN(void)
1138 {
1139 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN);
1140 }
1141
1142 /**
1143 * @brief Disable the VDDIO2 independent voltage monitor.
1144 * @retval None.
1145 */
HAL_PWREx_DisableVddIO2VMEN(void)1146 void HAL_PWREx_DisableVddIO2VMEN(void)
1147 {
1148 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO2VMEN);
1149 }
1150
1151 /**
1152 * @brief Enable the VDDIO3 independent voltage monitor.
1153 * @retval None.
1154 */
HAL_PWREx_EnableVddIO3VMEN(void)1155 void HAL_PWREx_EnableVddIO3VMEN(void)
1156 {
1157 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN);
1158 }
1159
1160 /**
1161 * @brief Disable the VDDIO3 independent voltage monitor.
1162 * @retval None.
1163 */
HAL_PWREx_DisableVddIO3VMEN(void)1164 void HAL_PWREx_DisableVddIO3VMEN(void)
1165 {
1166 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_VDDIO3VMEN);
1167 }
1168
1169 /**
1170 * @brief Enable the VDDIO4 independent voltage monitor.
1171 * @retval None.
1172 */
HAL_PWREx_EnableVddIO4VMEN(void)1173 void HAL_PWREx_EnableVddIO4VMEN(void)
1174 {
1175 SET_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN);
1176 }
1177
1178 /**
1179 * @brief Disable the VDDIO4 independent voltage monitor.
1180 * @retval None.
1181 */
HAL_PWREx_DisableVddIO4VMEN(void)1182 void HAL_PWREx_DisableVddIO4VMEN(void)
1183 {
1184 CLEAR_BIT(PWR->SVMCR1, PWR_SVMCR1_VDDIO4VMEN);
1185 }
1186
1187 /**
1188 * @brief Enable the VDDIO5 independent voltage monitor.
1189 * @retval None.
1190 */
HAL_PWREx_EnableVddIO5VMEN(void)1191 void HAL_PWREx_EnableVddIO5VMEN(void)
1192 {
1193 SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN);
1194 }
1195
1196 /**
1197 * @brief Disable the VDDIO5 independent voltage monitor.
1198 * @retval None.
1199 */
HAL_PWREx_DisableVddIO5VMEN(void)1200 void HAL_PWREx_DisableVddIO5VMEN(void)
1201 {
1202 CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN);
1203 }
1204
1205 /**
1206 * @brief Enable the VDDA18ADC independent ADC voltage monitor.
1207 * @retval None.
1208 */
HAL_PWREx_EnableVddAVMEN(void)1209 void HAL_PWREx_EnableVddAVMEN(void)
1210 {
1211 SET_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN);
1212 }
1213
1214 /**
1215 * @brief Disable the VDDA18ADC independent ADC voltage monitor.
1216 * @retval None.
1217 */
HAL_PWREx_DisableVddAVMEN(void)1218 void HAL_PWREx_DisableVddAVMEN(void)
1219 {
1220 CLEAR_BIT(PWR->SVMCR3, PWR_SVMCR3_AVMEN);
1221 }
1222
1223 /**
1224 * @brief Configure the voltage monitor threshold detected by the Peripheral
1225 * voltage monitoring (PVM).
1226 * @param pConfigPVM : Pointer to a PWR_PVMTypeDef structure that contains the
1227 * PVM configuration information (PVMType and EventMode).
1228 * @retval HAL Status.
1229 */
HAL_PWREx_ConfigPVM(const PWR_PVMTypeDef * pConfigPVM)1230 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(const PWR_PVMTypeDef *pConfigPVM)
1231 {
1232
1233 /* Check the parameters */
1234 assert_param(IS_PWR_PVM_TYPE(pConfigPVM->PVMType));
1235 assert_param(IS_PWR_PVM_MODE(pConfigPVM->Mode));
1236
1237 /* Check the peripheral voltage monitor type */
1238 switch (pConfigPVM->PVMType)
1239 {
1240 case PWR_VDDUSB_VM: /* Independent USB voltage monitor */
1241
1242 /* Disable EXTI USBVM event and interrupt */
1243 __HAL_PWR_USBVM_EXTI_DISABLE_EVENT();
1244 __HAL_PWR_USBVM_EXTI_DISABLE_IT();
1245 __HAL_PWR_USBVM_EXTI_DISABLE_RISING_EDGE();
1246 __HAL_PWR_USBVM_EXTI_DISABLE_FALLING_EDGE();
1247
1248 /* Configure the USBVM in interrupt mode */
1249 if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1250 {
1251 __HAL_PWR_USBVM_EXTI_ENABLE_IT();
1252 }
1253
1254 /* Configure the USBVM in event mode */
1255 if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1256 {
1257 __HAL_PWR_USBVM_EXTI_ENABLE_EVENT();
1258 }
1259
1260 /* Configure the USBVM in rising edge */
1261 if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1262 {
1263 __HAL_PWR_USBVM_EXTI_ENABLE_RISING_EDGE();
1264 }
1265
1266 /* Configure the USBVM in falling edge */
1267 if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1268 {
1269 __HAL_PWR_USBVM_EXTI_ENABLE_FALLING_EDGE();
1270 }
1271 break;
1272
1273 case PWR_VDDIO2_VM: /* Independent I/Os voltage monitor */
1274
1275 /* Disable EXTI IO2VM event and interrupt */
1276 __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT();
1277 __HAL_PWR_IO2VM_EXTI_DISABLE_IT();
1278 __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE();
1279 __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE();
1280
1281 /* Configure the IO2VM in interrupt mode */
1282 if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1283 {
1284 __HAL_PWR_IO2VM_EXTI_ENABLE_IT();
1285 }
1286
1287 /* Configure the IO2VM in event mode */
1288 if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1289 {
1290 __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT();
1291 }
1292
1293 /* Configure the IO2VM in rising edge */
1294 if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1295 {
1296 __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE();
1297 }
1298
1299 /* Configure the IO2VM in falling edge */
1300 if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1301 {
1302 __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE();
1303 }
1304 break;
1305
1306 case PWR_VDDIO3_VM: /* Independent I/Os voltage monitor */
1307
1308 /* Disable EXTI IO3VM event and interrupt */
1309 __HAL_PWR_IO3VM_EXTI_DISABLE_EVENT();
1310 __HAL_PWR_IO3VM_EXTI_DISABLE_IT();
1311 __HAL_PWR_IO3VM_EXTI_DISABLE_RISING_EDGE();
1312 __HAL_PWR_IO3VM_EXTI_DISABLE_FALLING_EDGE();
1313
1314 /* Configure the IO3VM in interrupt mode */
1315 if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1316 {
1317 __HAL_PWR_IO3VM_EXTI_ENABLE_IT();
1318 }
1319
1320 /* Configure the IO3VM in event mode */
1321 if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1322 {
1323 __HAL_PWR_IO3VM_EXTI_ENABLE_EVENT();
1324 }
1325
1326 /* Configure the IO3VM in rising edge */
1327 if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1328 {
1329 __HAL_PWR_IO3VM_EXTI_ENABLE_RISING_EDGE();
1330 }
1331
1332 /* Configure the IO3VM in falling edge */
1333 if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1334 {
1335 __HAL_PWR_IO3VM_EXTI_ENABLE_FALLING_EDGE();
1336 }
1337 break;
1338
1339 case PWR_VDDIO4_VM: /* Independent I/Os voltage monitor */
1340
1341 /* Disable EXTI IO4VM event and interrupt */
1342 __HAL_PWR_IO4VM_EXTI_DISABLE_EVENT();
1343 __HAL_PWR_IO4VM_EXTI_DISABLE_IT();
1344 __HAL_PWR_IO4VM_EXTI_DISABLE_RISING_EDGE();
1345 __HAL_PWR_IO4VM_EXTI_DISABLE_FALLING_EDGE();
1346
1347 /* Configure the IO4VM in interrupt mode */
1348 if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1349 {
1350 __HAL_PWR_IO4VM_EXTI_ENABLE_IT();
1351 }
1352
1353 /* Configure the IO4VM in event mode */
1354 if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1355 {
1356 __HAL_PWR_IO4VM_EXTI_ENABLE_EVENT();
1357 }
1358
1359 /* Configure the IO4VM in rising edge */
1360 if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1361 {
1362 __HAL_PWR_IO4VM_EXTI_ENABLE_RISING_EDGE();
1363 }
1364
1365 /* Configure the IO4VM in falling edge */
1366 if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1367 {
1368 __HAL_PWR_IO4VM_EXTI_ENABLE_FALLING_EDGE();
1369 }
1370 break;
1371
1372 case PWR_VDDIO5_VM: /* Independent I/Os voltage monitor */
1373
1374 /* Disable EXTI IO5VM event and interrupt */
1375 __HAL_PWR_IO5VM_EXTI_DISABLE_EVENT();
1376 __HAL_PWR_IO5VM_EXTI_DISABLE_IT();
1377 __HAL_PWR_IO5VM_EXTI_DISABLE_RISING_EDGE();
1378 __HAL_PWR_IO5VM_EXTI_DISABLE_FALLING_EDGE();
1379
1380 /* Configure the IO5VM in interrupt mode */
1381 if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1382 {
1383 __HAL_PWR_IO5VM_EXTI_ENABLE_IT();
1384 }
1385
1386 /* Configure the IO5VM in event mode */
1387 if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1388 {
1389 __HAL_PWR_IO5VM_EXTI_ENABLE_EVENT();
1390 }
1391
1392 /* Configure the IO5VM in rising edge */
1393 if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1394 {
1395 __HAL_PWR_IO5VM_EXTI_ENABLE_RISING_EDGE();
1396 }
1397
1398 /* Configure the IO5VM in falling edge */
1399 if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1400 {
1401 __HAL_PWR_IO5VM_EXTI_ENABLE_FALLING_EDGE();
1402 }
1403 break;
1404
1405 case PWR_VDDA_VM: /* Independent ADC voltage monitor */
1406
1407 /* Disable EXTI ADCVM event and interrupt */
1408 __HAL_PWR_ADCVM_EXTI_DISABLE_EVENT();
1409 __HAL_PWR_ADCVM_EXTI_DISABLE_IT();
1410 __HAL_PWR_ADCVM_EXTI_DISABLE_RISING_EDGE();
1411 __HAL_PWR_ADCVM_EXTI_DISABLE_FALLING_EDGE();
1412
1413 /* Configure the ADCVM in interrupt mode */
1414 if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1415 {
1416 __HAL_PWR_ADCVM_EXTI_ENABLE_IT();
1417 }
1418
1419 /* Configure the ADCVM in event mode */
1420 if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1421 {
1422 __HAL_PWR_ADCVM_EXTI_ENABLE_EVENT();
1423 }
1424
1425 /* Configure the ADCVM in rising edge */
1426 if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1427 {
1428 __HAL_PWR_ADCVM_EXTI_ENABLE_RISING_EDGE();
1429 }
1430
1431 /* Configure the ADCVM in falling edge */
1432 if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1433 {
1434 __HAL_PWR_ADCVM_EXTI_ENABLE_FALLING_EDGE();
1435 }
1436 break;
1437
1438 default: /* No valid voltage monitor selected */
1439 return HAL_ERROR;
1440 break;
1441 }
1442
1443 return HAL_OK;
1444 }
1445
1446 /**
1447 * @brief This function handles the PWR PVD/PVM interrupt request.
1448 * @retval None.
1449 */
HAL_PWREx_PVD_PVM_IRQHandler(void)1450 void HAL_PWREx_PVD_PVM_IRQHandler(void)
1451 {
1452 uint32_t rising_flag;
1453 uint32_t falling_flag;
1454
1455 rising_flag = READ_REG(EXTI->RPR3);
1456 falling_flag = READ_REG(EXTI->FPR3);
1457
1458 /* Check PWR VDDCORE monitoring exti rising flag */
1459 if ((rising_flag & PWR_EXTI_LINE_VCOREVM) != 0U)
1460 {
1461 /* Clear VDDCORE monitoring exti pending bit */
1462 __HAL_PWR_VCOREVM_EXTI_CLEAR_RISING_FLAG();
1463
1464 /* PWR VDDCORE monitoring interrupt rising user callback */
1465 HAL_PWREx_VDDCORE_Rising_Callback();
1466 }
1467
1468 /* Check PWR VDDCORE monitoring exti falling flag */
1469 if ((falling_flag & PWR_EXTI_LINE_VCOREVM) != 0U)
1470 {
1471 /* Clear VDDCORE monitoring exti pending bit */
1472 __HAL_PWR_VCOREVM_EXTI_CLEAR_FALLING_FLAG();
1473
1474 /* PWR VDDCORE monitoring interrupt falling user callback */
1475 HAL_PWREx_VDDCORE_Falling_Callback();
1476 }
1477
1478 /* Check PWR PVD exti rising flag */
1479 if ((rising_flag & PWR_EXTI_LINE_PVD) != 0U)
1480 {
1481 /* Clear PVD exti pending bit */
1482 __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG();
1483
1484 /* PWR PVD interrupt rising user callback */
1485 HAL_PWR_PVD_Rising_Callback();
1486 }
1487
1488 /* Check PWR PVD exti falling flag */
1489 if ((falling_flag & PWR_EXTI_LINE_PVD) != 0U)
1490 {
1491 /* Clear PVD exti pending bit */
1492 __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG();
1493
1494 /* PWR PVD interrupt falling user callback */
1495 HAL_PWR_PVD_Falling_Callback();
1496 }
1497
1498 /* Check PWR PVM USB exti rising flag */
1499 if ((rising_flag & PWR_EXTI_LINE_PVM_VDDUSB) != 0U)
1500 {
1501 /* Clear PVM USB exti pending bit */
1502 __HAL_PWR_USBVM_EXTI_CLEAR_RISING_FLAG();
1503
1504 /* PWR PVM USB interrupt rising user callback */
1505 HAL_PWREx_USBVM_Rising_Callback();
1506 }
1507
1508 /* Check PWR PVM USB exti falling flag */
1509 if ((falling_flag & PWR_EXTI_LINE_PVM_VDDUSB) != 0U)
1510 {
1511 /* Clear PVM USB exti pending bit */
1512 __HAL_PWR_USBVM_EXTI_CLEAR_FALLING_FLAG();
1513
1514 /* PWR PVM USB interrupt falling user callback */
1515 HAL_PWREx_USBVM_Falling_Callback();
1516 }
1517
1518 /* Check PWR PVM IO2 exti rising flag */
1519 if ((rising_flag & PWR_EXTI_LINE_PVM_VDDIO2) != 0U)
1520 {
1521 /* Clear PVM IO2 exti pending bit */
1522 __HAL_PWR_IO2VM_EXTI_CLEAR_RISING_FLAG();
1523
1524 /* PWR PVM IO2 interrupt rising user callback */
1525 HAL_PWREx_IO2VM_Rising_Callback();
1526 }
1527
1528 /* Check PWR PVM IO2 exti falling flag */
1529 if ((falling_flag & PWR_EXTI_LINE_PVM_VDDIO2) != 0U)
1530 {
1531 /* Clear PVM IO2 exti pending bit */
1532 __HAL_PWR_IO2VM_EXTI_CLEAR_FALLING_FLAG();
1533
1534 /* PWR PVM IO2 interrupt falling user callback */
1535 HAL_PWREx_IO2VM_Falling_Callback();
1536 }
1537
1538 /* Check PWR PVM IO3 exti rising flag */
1539 if ((rising_flag & PWR_EXTI_LINE_PVM_VDDIO3) != 0U)
1540 {
1541 /* Clear PVM IO3 exti pending bit */
1542 __HAL_PWR_IO3VM_EXTI_CLEAR_RISING_FLAG();
1543
1544 /* PWR PVM IO3 interrupt rising user callback */
1545 HAL_PWREx_IO3VM_Rising_Callback();
1546 }
1547
1548 /* Check PWR PVM IO3 exti falling flag */
1549 if ((falling_flag & PWR_EXTI_LINE_PVM_VDDIO3) != 0U)
1550 {
1551 /* Clear PVM IO3 exti pending bit */
1552 __HAL_PWR_IO3VM_EXTI_CLEAR_FALLING_FLAG();
1553
1554 /* PWR PVM IO3 interrupt falling user callback */
1555 HAL_PWREx_IO3VM_Falling_Callback();
1556 }
1557
1558 /* Check PWR PVM IO4 exti rising flag */
1559 if ((rising_flag & PWR_EXTI_LINE_PVM_VDDIO4) != 0U)
1560 {
1561 /* Clear PVM IO4 exti pending bit */
1562 __HAL_PWR_IO4VM_EXTI_CLEAR_RISING_FLAG();
1563
1564 /* PWR PVM IO4 interrupt rising user callback */
1565 HAL_PWREx_IO4VM_Rising_Callback();
1566 }
1567
1568 /* Check PWR PVM IO4 exti falling flag */
1569 if ((falling_flag & PWR_EXTI_LINE_PVM_VDDIO4) != 0U)
1570 {
1571 /* Clear PVM IO4 exti pending bit */
1572 __HAL_PWR_IO4VM_EXTI_CLEAR_FALLING_FLAG();
1573
1574 /* PWR PVM IO4 interrupt falling user callback */
1575 HAL_PWREx_IO4VM_Falling_Callback();
1576 }
1577
1578 /* Check PWR PVM IO5 exti rising flag */
1579 if ((rising_flag & PWR_EXTI_LINE_PVM_VDDIO5) != 0U)
1580 {
1581 /* Clear PVM IO5 exti pending bit */
1582 __HAL_PWR_IO5VM_EXTI_CLEAR_RISING_FLAG();
1583
1584 /* PWR PVM IO5 interrupt rising user callback */
1585 HAL_PWREx_IO5VM_Rising_Callback();
1586 }
1587
1588 /* Check PWR PVM IO5 exti falling flag */
1589 if ((falling_flag & PWR_EXTI_LINE_PVM_VDDIO5) != 0U)
1590 {
1591 /* Clear PVM IO5 exti pending bit */
1592 __HAL_PWR_IO5VM_EXTI_CLEAR_FALLING_FLAG();
1593
1594 /* PWR PVM IO5 interrupt falling user callback */
1595 HAL_PWREx_IO5VM_Falling_Callback();
1596
1597 }
1598
1599 /* Check PWR PVM ADC VM exti rising flag */
1600 if ((rising_flag & PWR_EXTI_LINE_PVM_VDDA) != 0U)
1601 {
1602 /* Clear PVM ADC VM exti pending bit */
1603 __HAL_PWR_ADCVM_EXTI_CLEAR_RISING_FLAG();
1604
1605 /* PWR PVM ADC VM interrupt rising user callback */
1606 HAL_PWREx_ADCVM_Rising_Callback();
1607 }
1608
1609 /* Check PWR PVM ADC VM exti falling flag */
1610 if ((falling_flag & PWR_EXTI_LINE_PVM_VDDA) != 0U)
1611 {
1612 /* Clear PVM ADC VM exti pending bit */
1613 __HAL_PWR_ADCVM_EXTI_CLEAR_FALLING_FLAG();
1614
1615 /* PWR PVM ADC VM interrupt falling user callback */
1616 HAL_PWREx_ADCVM_Falling_Callback();
1617 }
1618 }
1619
1620 /**
1621 * @brief PWR VDDCORE interrupt Rising callback.
1622 * @retval None.
1623 */
HAL_PWREx_VDDCORE_Rising_Callback(void)1624 __weak void HAL_PWREx_VDDCORE_Rising_Callback(void)
1625 {
1626 /* NOTE : This function should not be modified; when the callback is needed,
1627 HAL_PWREx_VDDCORE_Rising_Callback() API can be implemented in the user file
1628 */
1629 }
1630
1631 /**
1632 * @brief PWR VDDCORE interrupt Falling callback.
1633 * @retval None.
1634 */
HAL_PWREx_VDDCORE_Falling_Callback(void)1635 __weak void HAL_PWREx_VDDCORE_Falling_Callback(void)
1636 {
1637 /* NOTE : This function should not be modified; when the callback is needed,
1638 HAL_PWREx_VDDCORE_Falling_Callback() API can be implemented in the user file
1639 */
1640 }
1641
1642 /**
1643 * @brief PWR USBVM interrupt Rising callback.
1644 * @retval None.
1645 */
HAL_PWREx_USBVM_Rising_Callback(void)1646 __weak void HAL_PWREx_USBVM_Rising_Callback(void)
1647 {
1648 /* NOTE : This function should not be modified; when the callback is needed,
1649 HAL_PWREx_USBVM_Rising_Callback() API can be implemented in the user file
1650 */
1651 }
1652
1653 /**
1654 * @brief PWR USBVM interrupt Falling callback.
1655 * @retval None.
1656 */
HAL_PWREx_USBVM_Falling_Callback(void)1657 __weak void HAL_PWREx_USBVM_Falling_Callback(void)
1658 {
1659 /* NOTE : This function should not be modified; when the callback is needed,
1660 HAL_PWREx_USBVM_Falling_Callback() API can be implemented in the user file
1661 */
1662 }
1663
1664 /**
1665 * @brief PWR IO2VM interrupt Rising callback.
1666 * @retval None.
1667 */
HAL_PWREx_IO2VM_Rising_Callback(void)1668 __weak void HAL_PWREx_IO2VM_Rising_Callback(void)
1669 {
1670 /* NOTE : This function should not be modified; when the callback is needed,
1671 HAL_PWREx_IO2VM_Rising_Callback() API can be implemented in the user file
1672 */
1673 }
1674
1675 /**
1676 * @brief PWR IO2VM interrupt Falling callback.
1677 * @retval None.
1678 */
HAL_PWREx_IO2VM_Falling_Callback(void)1679 __weak void HAL_PWREx_IO2VM_Falling_Callback(void)
1680 {
1681 /* NOTE : This function should not be modified; when the callback is needed,
1682 HAL_PWREx_IO2VM_Falling_Callback() API can be implemented in the user file
1683 */
1684 }
1685
1686 /**
1687 * @brief PWR IO3VM interrupt Rising callback.
1688 * @retval None.
1689 */
HAL_PWREx_IO3VM_Rising_Callback(void)1690 __weak void HAL_PWREx_IO3VM_Rising_Callback(void)
1691 {
1692 /* NOTE : This function should not be modified; when the callback is needed,
1693 HAL_PWREx_IO3VM_Rising_Callback() API can be implemented in the user file
1694 */
1695 }
1696
1697 /**
1698 * @brief PWR IO3VM interrupt Falling callback.
1699 * @retval None.
1700 */
HAL_PWREx_IO3VM_Falling_Callback(void)1701 __weak void HAL_PWREx_IO3VM_Falling_Callback(void)
1702 {
1703 /* NOTE : This function should not be modified; when the callback is needed,
1704 HAL_PWREx_IO3VM_Falling_Callback() API can be implemented in the user file
1705 */
1706 }
1707
1708 /**
1709 * @brief PWR IO4VM interrupt Rising callback.
1710 * @retval None.
1711 */
HAL_PWREx_IO4VM_Rising_Callback(void)1712 __weak void HAL_PWREx_IO4VM_Rising_Callback(void)
1713 {
1714 /* NOTE : This function should not be modified; when the callback is needed,
1715 HAL_PWREx_IO4VM_Rising_Callback() API can be implemented in the user file
1716 */
1717 }
1718
1719 /**
1720 * @brief PWR IO4VM interrupt Falling callback.
1721 * @retval None.
1722 */
HAL_PWREx_IO4VM_Falling_Callback(void)1723 __weak void HAL_PWREx_IO4VM_Falling_Callback(void)
1724 {
1725 /* NOTE : This function should not be modified; when the callback is needed,
1726 HAL_PWREx_IO4VM_Falling_Callback() API can be implemented in the user file
1727 */
1728 }
1729
1730 /**
1731 * @brief PWR IO5VM interrupt Rising callback.
1732 * @retval None.
1733 */
HAL_PWREx_IO5VM_Rising_Callback(void)1734 __weak void HAL_PWREx_IO5VM_Rising_Callback(void)
1735 {
1736 /* NOTE : This function should not be modified; when the callback is needed,
1737 HAL_PWREx_IO5VM_Rising_Callback() API can be implemented in the user file
1738 */
1739 }
1740
1741 /**
1742 * @brief PWR IO5VM interrupt Falling callback.
1743 * @retval None.
1744 */
HAL_PWREx_IO5VM_Falling_Callback(void)1745 __weak void HAL_PWREx_IO5VM_Falling_Callback(void)
1746 {
1747 /* NOTE : This function should not be modified; when the callback is needed,
1748 HAL_PWREx_IO5VM_Falling_Callback() API can be implemented in the user file
1749 */
1750 }
1751
1752 /**
1753 * @brief PWR ADCVM interrupt Rising callback.
1754 * @retval None.
1755 */
HAL_PWREx_ADCVM_Rising_Callback(void)1756 __weak void HAL_PWREx_ADCVM_Rising_Callback(void)
1757 {
1758 /* NOTE : This function should not be modified; when the callback is needed,
1759 HAL_PWREx_ADCVM_Rising_Callback() API can be implemented in the user file
1760 */
1761 }
1762
1763 /**
1764 * @brief PWR ADCVM interrupt Falling callback.
1765 * @retval None.
1766 */
HAL_PWREx_ADCVM_Falling_Callback(void)1767 __weak void HAL_PWREx_ADCVM_Falling_Callback(void)
1768 {
1769 /* NOTE : This function should not be modified; when the callback is needed,
1770 HAL_PWREx_ADCVM_Falling_Callback() API can be implemented in the user file
1771 */
1772 }
1773 /**
1774 * @}
1775 */
1776
1777 /**
1778 * @}
1779 */
1780
1781 /**
1782 * @}
1783 */
1784
1785
1786 #endif /* defined (HAL_PWR_MODULE_ENABLED) */
1787
1788 /**
1789 * @}
1790 */
1791
1792 /**
1793 * @}
1794 */
1795
1796 /**
1797 * @}
1798 */
1799
