1 /**
2 **********************************************************************************************************************
3 * @file stm32n6xx_hal_dma.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following functionalities of the Direct Memory Access
6 * (DMA) peripheral:
7 * + Initialization/De-Initialization Functions
8 * + I/O Operation Functions
9 * + State and Errors Functions
10 * + DMA Attributes Functions
11 *
12 **********************************************************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2023 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 **********************************************************************************************************************
23 @verbatim
24 ======================================================================================================================
25 ##### How to use this driver #####
26 ======================================================================================================================
27 [..]
28 (#) GPDMA and HPDMA are made available on this series.
29 Transfer could be done thanks to AXI or AHB ports.
30
31 HPDMA support transmission through:
32 AXI port 0.
33 AHB port 1.
34 GPDMA allows transmission through:
35 GPDMA_P = port-0.
36 GPDMA_M = port-1
37
38 The supported configurations for GPDMA and HPDMA can be found
39 in the Connectivity matrix table of the reference manual.
40 Mind that DTCM and ITCM can be only be accessed thanks to HPDMA
41 AXI port 0.
42 [..]
43 DMA transfer modes are divided to 2 major categories :
44 (+) Normal transfers (legacy)
45 (+) Linked-list transfers
46
47 [..]
48 Normal transfers mode is initialized via the standard module and linked-list mode is configured via the extended
49 module.
50
51 [..]
52 Additionally to linked-list capability, all advanced DMA features are managed and configured via the extended
53 module as extensions to normal mode.
54 Advanced features are :
55 (+) Repeated block feature.
56 (+) Trigger feature.
57 (+) Data handling feature.
58
59 [..]
60 DMA Legacy circular transfer, is replaced by circular linked-list configuration.
61
62
63 *** Initialization and De-Initialization ***
64 ============================================
65 [..]
66 For a given channel, enable and configure the peripheral to be connected to the DMA Channel (except for internal
67 SRAM/FLASH memories: no initialization is necessary) please refer to Reference manual for connection between
68 peripherals and DMA requests.
69
70 [..]
71 For a given channel, use HAL_DMA_Init function to program the required configuration for normal transfer through
72 the following parameters:
73
74 (+) Request : Specifies the DMA channel request
75 Request parameters :
76 (++) can be a value of DMA_Request_Selection
77
78 (+) BlkHWRequest : Specifies the Block hardware request mode for DMA channel
79 (++) can be a value of DMA_Block_Request
80
81 (+) Direction : Specifies the transfer direction for DMA channel
82 (++) can be a value of DMA_Transfer_Direction
83
84 (+) SrcInc : Specifies the source increment mode for the DMA channel
85 (++) can be a value of DMA_Source_Increment_Mode
86
87 (+) DestInc : Specifies the destination increment mode for the DMA channel
88 (++) can be a value of DMA_Destination_Increment_Mode
89
90 (+) SrcDataWidth : Specifies the source data width for the DMA channel
91 (++) can be a value of DMA_Source_Data_Width
92
93 (+) DestDataWidth : Specifies the destination data width for the DMA channel
94 (++) can be a value of DMA_Destination_Data_Width
95
96 (+) Priority : Specifies the priority for the DMA channel
97 (++) can be a value of DMA_Priority_Level
98
99 (+) SrcBurstLength : Specifies the source burst length (number of beats) for the DMA channel
100 (++) can be a value of between 1 and 64
101
102 (+) DestBurstLength : Specifies the destination burst length (number of beats) for the DMA channel
103 (++) can be a value of between 1 and 64
104
105 (+) TransferAllocatedPort : Specifies the source and destination allocated ports
106 (++) can be a value of DMA_Transfer_Allocated_Port
107
108 (+) TransferEventMode : Specifies the transfer event mode for the DMA channel
109 (++) can be a value of DMA_Transfer_Event_Mode
110
111 (+) Mode : Specifies the transfer mode for the DMA channel
112 (++) can be one of the following modes :
113 (+++) DMA_NORMAL : Normal Mode
114 (+++) DMA_PFCTRL : Peripheral Flow Control (peripheral early termination) Mode
115
116 *** Polling mode IO operation ***
117 =================================
118 [..]
119 (+) Use HAL_DMA_Start() to start a DMA normal transfer after the configuration of source address, destination
120 address and the size of data to be transferred.
121
122 (+) Use HAL_DMA_PollForTransfer() to poll for selected transfer level. In this case a fixed Timeout can be
123 configured by User depending on his application.
124 Transfer level can be :
125 (++) HAL_DMA_HALF_TRANSFER
126 (++) HAL_DMA_FULL_TRANSFER
127 For circular transfer, this API returns an HAL_ERROR with HAL_DMA_ERROR_NOT_SUPPORTED error code.
128
129 (+) Use HAL_DMA_Abort() function to abort any ongoing DMA transfer in blocking mode.
130 This API returns HAL_ERROR when there is no ongoing transfer or timeout is reached when disabling the DMA
131 channel. (This API should not be called from an interrupt service routine)
132
133
134 *** Interrupt mode IO operation ***
135 ===================================
136 [..]
137 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
138
139 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
140
141 (+) Use HAL_DMA_RegisterCallback() function to register user callbacks from the following list :
142 (++) XferCpltCallback : transfer complete callback.
143 (++) XferHalfCpltCallback : half transfer complete callback.
144 (++) XferErrorCallback : transfer error callback.
145 (++) XferAbortCallback : transfer abort complete callback.
146 (++) XferSuspendCallback : transfer suspend complete callback.
147
148 (+) Use HAL_DMA_Start_IT() to start the DMA transfer after the enable of DMA interrupts and the configuration
149 of source address,destination address and the size of data to be transferred.
150
151 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() interrupt subroutine to handle any DMA interrupt.
152
153 (+) Use HAL_DMA_Abort_IT() function to abort any on-going DMA transfer in non-blocking mode.
154 This API will suspend immediately the DMA channel execution. When the transfer is effectively suspended,
155 an interrupt is generated and HAL_DMA_IRQHandler() will reset the channel and execute the callback
156 XferAbortCallback. (This API could be called from an interrupt service routine)
157
158
159 *** State and errors ***
160 ========================
161 [..]
162 (+) Use HAL_DMA_GetState() function to get the DMA state.
163 (+) Use HAL_DMA_GetError() function to get the DMA error code.
164
165
166 *** Security and privilege attributes ***
167 =========================================
168 [..]
169 (+) Use HAL_DMA_ConfigChannelAttributes() function to configure DMA channel security and privilege attributes.
170 (++) Security : at channel level, at source level and at destination level.
171 (++) Privilege : at channel level.
172 (+) Use HAL_DMA_GetConfigChannelAttributes() function to get the DMA channel attributes.
173 (+) Use HAL_DMA_LockChannelAttributes() function to lock the DMA channel security and privilege attributes
174 configuration. This API can be called once after each system boot.
175 If called again, HAL_DMA_ConfigChannelAttributes() API has no effect.
176 Unlock is done either by a system boot or a by an RCC reset.
177 (+) Use HAL_DMA_GetLockChannelAttributes() function to get the attributes lock status.
178 (+) Use HAL_DMA_SetIsolationAttributes() function to configure the HPDMA channel isolation attribute.
179 (+) Use HAL_DMA_GetIsolationAttributes() function to get the HPDMA channel isolation attribute.
180
181 *** Isolation attributes ***
182 ==================================
183 It is recommended to always enable the isolation feature of the DMA (CFEN = 1) of the HPDMA channel.
184 The default isolation shall be 1. i.e. the Cortex CID.
185 Indeed, should the isolation bit CFEN be equal to 0, a default isolation CID is still carried out and is 0 (zero).
186 the CID generated by a channel access is zero-ed when CFEN=0, even if SCID is different from 000.
187
188 Similarly, it is recommended that all RIMU related IP (SDMMC, OTG, ETH, GPU, DMA2D, ...) to always enable and
189 generate (CID = 1).
190
191 *** DMA HAL driver macros list ***
192 ==================================
193 [..]
194 Below the list of most used macros in DMA HAL driver.
195
196 (+) __HAL_DMA_ENABLE : Enable the specified DMA Channel.
197 (+) __HAL_DMA_DISABLE : Disable the specified DMA Channel.
198 (+) __HAL_DMA_GET_FLAG : Get the DMA Channel pending flags.
199 (+) __HAL_DMA_CLEAR_FLAG : Clear the DMA Channel pending flags.
200 (+) __HAL_DMA_ENABLE_IT : Enable the specified DMA Channel interrupts.
201 (+) __HAL_DMA_DISABLE_IT : Disable the specified DMA Channel interrupts.
202 (+) __HAL_DMA_GET_IT_SOURCE : Check whether the specified DMA Channel interrupt has occurred or not.
203
204 *** Valid burst length ***
205 ==================================
206 [..]
207 HPDMA allowed AXI maximum burst length
208 (+) The maximum allowed AXI burst length shall not exceed 16.
209 (++) If either selected source or destination length is above 16, HAL_DMA_Init will return HAL_ERROR.
210
211 [..]
212 (@) You can refer to the header file of the DMA HAL driver for more useful macros.
213
214 @endverbatim
215 **********************************************************************************************************************
216 */
217
218 /* Includes ----------------------------------------------------------------------------------------------------------*/
219 #include "stm32n6xx_hal.h"
220
221 /** @addtogroup STM32N6xx_HAL_Driver
222 * @{
223 */
224
225 /** @defgroup DMA DMA
226 * @brief DMA HAL module driver
227 * @{
228 */
229
230 #ifdef HAL_DMA_MODULE_ENABLED
231
232 /* Private typedef ---------------------------------------------------------------------------------------------------*/
233 /* Private constants -------------------------------------------------------------------------------------------------*/
234 /* Private macro -----------------------------------------------------------------------------------------------------*/
235 /* Private variables -------------------------------------------------------------------------------------------------*/
236 /* Private function prototypes ---------------------------------------------------------------------------------------*/
237 static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma,
238 uint32_t SrcAddress,
239 uint32_t DstAddress,
240 uint32_t SrcDataSize);
241 static void DMA_Init(DMA_HandleTypeDef const *const hdma);
242
243 /* Exported functions ------------------------------------------------------------------------------------------------*/
244
245 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
246 * @{
247 */
248
249 /** @addtogroup DMA_Exported_Functions_Group1
250 *
251 @verbatim
252 ======================================================================================================================
253 ##### Initialization and de-initialization functions #####
254 ======================================================================================================================
255 [..]
256 This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode.
257
258 [..]
259 (+) The HAL_DMA_Init() function follows the DMA channel configuration procedures as described in reference manual.
260 (+) The HAL_DMA_DeInit() function allows to de-initialize the DMA channel.
261
262 @endverbatim
263 * @{
264 */
265
266 /**
267 * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef and
268 * create the associated handle.
269 * @note Warning: the maximum allowed AXI burst length shall not exceed 16.
270 * Otherwise, an error will be returned and no initialization performed.
271 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
272 * specified DMA Channel.
273 * @retval HAL status.
274 */
HAL_DMA_Init(DMA_HandleTypeDef * const hdma)275 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma)
276 {
277 /* Get tick number */
278 uint32_t tickstart = HAL_GetTick();
279
280 /* Check the DMA peripheral handle parameter */
281 if (hdma == NULL)
282 {
283 return HAL_ERROR;
284 }
285
286 /* Check the parameters */
287 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
288 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
289 if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
290 {
291 assert_param(IS_DMA_REQUEST(hdma->Init.Request));
292 }
293 assert_param(IS_DMA_BLOCK_HW_REQUEST(hdma->Init.BlkHWRequest));
294 assert_param(IS_DMA_SOURCE_INC(hdma->Init.SrcInc));
295 assert_param(IS_DMA_DESTINATION_INC(hdma->Init.DestInc));
296 assert_param(IS_DMA_SOURCE_DATA_WIDTH(hdma->Init.SrcDataWidth));
297 assert_param(IS_DMA_DESTINATION_DATA_WIDTH(hdma->Init.DestDataWidth));
298 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
299 assert_param(IS_DMA_TCEM_EVENT_MODE(hdma->Init.TransferEventMode));
300 assert_param(IS_DMA_MODE(hdma->Init.Mode));
301 if (hdma->Init.Mode == DMA_PFCTRL)
302 {
303 assert_param(IS_DMA_PFREQ_INSTANCE(hdma->Instance));
304 }
305 /* Check DMA channel instance */
306 if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U))
307 {
308 assert_param(IS_DMA_BURST_LENGTH(hdma->Init.SrcBurstLength));
309 assert_param(IS_DMA_BURST_LENGTH(hdma->Init.DestBurstLength));
310 assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(hdma->Init.TransferAllocatedPort));
311 }
312
313 /* Check if the burst length may face DMA AXI limitation */
314 if (IS_HPDMA_INSTANCE(hdma->Instance) != 0U)
315 {
316 if (((hdma->Init.TransferAllocatedPort & DMA_CTR1_SAP) == DMA_SRC_ALLOCATED_PORT0) &&
317 (hdma->Init.SrcBurstLength > 16U))
318 {
319 return HAL_ERROR;
320 }
321 if (((hdma->Init.TransferAllocatedPort & DMA_CTR1_DAP) == DMA_DEST_ALLOCATED_PORT0) &&
322 (hdma->Init.DestBurstLength > 16U))
323 {
324 return HAL_ERROR;
325 }
326 }
327
328 /* Allocate lock resource */
329 __HAL_UNLOCK(hdma);
330
331 /* Update the DMA channel state */
332 hdma->State = HAL_DMA_STATE_BUSY;
333
334 /* Disable the DMA channel */
335 __HAL_DMA_DISABLE(hdma);
336
337 /* Check if the DMA channel is effectively disabled */
338 while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
339 {
340 /* Check for the Timeout */
341 if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
342 {
343 /* Update the DMA channel error code */
344 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
345
346 /* Update the DMA channel state */
347 hdma->State = HAL_DMA_STATE_ERROR;
348
349 return HAL_ERROR;
350 }
351 }
352
353 /* Initialize the DMA channel registers */
354 DMA_Init(hdma);
355
356 /* Update DMA channel operation mode */
357 hdma->Mode = hdma->Init.Mode;
358
359 /* Update the DMA channel error code */
360 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
361
362 /* Update the DMA channel state */
363 hdma->State = HAL_DMA_STATE_READY;
364
365 return HAL_OK;
366 }
367
368 /**
369 * @brief DeInitialize the DMA channel when it is configured in normal mode.
370 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
371 * specified DMA Channel.
372 * @retval HAL status.
373 */
HAL_DMA_DeInit(DMA_HandleTypeDef * const hdma)374 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma)
375 {
376 uint32_t tickstart = HAL_GetTick();
377
378 /* Check the DMA peripheral handle parameter */
379 if (hdma == NULL)
380 {
381 return HAL_ERROR;
382 }
383
384 /* Check the parameters */
385 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
386 /* Disable the selected DMA Channel */
387 __HAL_DMA_DISABLE(hdma);
388
389 /* Check if the DMA channel is effectively disabled */
390 while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
391 {
392 /* Check for the Timeout */
393 if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
394 {
395 /* Update the DMA channel error code */
396 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
397
398 /* Update the DMA channel state */
399 hdma->State = HAL_DMA_STATE_ERROR;
400
401 return HAL_ERROR;
402 }
403 }
404
405 /* Reset DMA Channel registers */
406 hdma->Instance->CLBAR = 0U;
407 hdma->Instance->CCR = 0U;
408 /* As secure, privilege and CID configuration, bit field DSEC and SSEC are managed in */
409 /* HAL_DMA_ConfigChannelAttributes function, so it mustn't be cleaned in HAL_DMA_DeInit */
410 hdma->Instance->CTR1 = hdma->Instance->CTR1 & (0U | DMA_CTR1_DSEC | DMA_CTR1_SSEC);
411 hdma->Instance->CTR2 = 0U;
412 hdma->Instance->CBR1 = 0U;
413 hdma->Instance->CSAR = 0U;
414 hdma->Instance->CDAR = 0U;
415 hdma->Instance->CLLR = 0U;
416
417 /* Reset 2D Addressing registers */
418 if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
419 {
420 hdma->Instance->CTR3 = 0U;
421 hdma->Instance->CBR2 = 0U;
422 }
423
424 /* Clear all flags */
425 __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
426 DMA_FLAG_TO));
427
428 /* Clean all callbacks */
429 hdma->XferCpltCallback = NULL;
430 hdma->XferHalfCpltCallback = NULL;
431 hdma->XferErrorCallback = NULL;
432 hdma->XferAbortCallback = NULL;
433 hdma->XferSuspendCallback = NULL;
434
435 /* Clean DMA queue */
436 hdma->LinkedListQueue = NULL;
437
438 /* Clean DMA parent */
439 if (hdma->Parent != NULL)
440 {
441 hdma->Parent = NULL;
442 }
443
444 /* Update DMA channel operation mode */
445 hdma->Mode = DMA_NORMAL;
446
447 /* Update the DMA channel error code */
448 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
449
450 /* Update the DMA channel state */
451 hdma->State = HAL_DMA_STATE_RESET;
452
453 /* Release Lock */
454 __HAL_UNLOCK(hdma);
455
456 return HAL_OK;
457 }
458 /**
459 * @}
460 */
461
462 /** @addtogroup DMA_Exported_Functions_Group2
463 *
464 @verbatim
465 ======================================================================================================================
466 ##### IO operation functions #####
467 ======================================================================================================================
468 [..]
469 This section provides functions allowing to :
470 (+) Configure the source, destination address and data size and Start DMA transfer in normal mode
471 (+) Abort DMA transfer
472 (+) Poll for transfer complete
473 (+) Handle DMA interrupt request
474 (+) Register and Unregister DMA callbacks
475
476 [..]
477 (+) The HAL_DMA_Start() function allows to start the DMA channel transfer in normal mode (Blocking mode).
478 (+) The HAL_DMA_Start_IT() function allows to start the DMA channel transfer in normal mode (Non-blocking mode).
479 (+) The HAL_DMA_Abort() function allows to abort any on-going transfer (Blocking mode).
480 (+) The HAL_DMA_Abort_IT() function allows to abort any on-going transfer (Non-blocking mode).
481 (+) The HAL_DMA_PollForTransfer() function allows to poll on half transfer and transfer complete (Blocking mode).
482 This API cannot be used for circular transfers.
483 (+) The HAL_DMA_IRQHandler() function allows to handle any DMA channel interrupt (Non-blocking mode).
484 (+) The HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() functions allow respectively to register and
485 unregister user customized callbacks.
486 User callbacks are called under HAL_DMA_IRQHandler().
487
488 @endverbatim
489 * @{
490 */
491
492 /**
493 * @brief Start the DMA channel transfer in normal mode (Blocking mode).
494 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for
495 * the specified DMA Channel.
496 * @param SrcAddress : The source data address.
497 * @param DstAddress : The destination data address.
498 * @param SrcDataSize : The length of data to be transferred from source to destination in bytes.
499 * @retval HAL status.
500 */
HAL_DMA_Start(DMA_HandleTypeDef * const hdma,uint32_t SrcAddress,uint32_t DstAddress,uint32_t SrcDataSize)501 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma,
502 uint32_t SrcAddress,
503 uint32_t DstAddress,
504 uint32_t SrcDataSize)
505 {
506 /* Check the DMA peripheral handle parameter */
507 if (hdma == NULL)
508 {
509 return HAL_ERROR;
510 }
511
512 /* Check the parameters */
513 assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize));
514
515 /* Process locked */
516 __HAL_LOCK(hdma);
517
518 /* Check DMA channel state */
519 if (hdma->State == HAL_DMA_STATE_READY)
520 {
521 /* Update the DMA channel state */
522 hdma->State = HAL_DMA_STATE_BUSY;
523
524 /* Update the DMA channel error code */
525 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
526
527 /* Configure the source address, destination address, the data size and clear flags */
528 DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize);
529
530 /* Enable DMA channel */
531 __HAL_DMA_ENABLE(hdma);
532 }
533 else
534 {
535 /* Update the DMA channel error code */
536 hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
537
538 /* Process unlocked */
539 __HAL_UNLOCK(hdma);
540
541 return HAL_ERROR;
542 }
543
544 return HAL_OK;
545 }
546
547 /**
548 * @brief Starts the DMA channel transfer in normal mode with interrupts enabled (Non-blocking mode).
549 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
550 * specified DMA Channel.
551 * @param SrcAddress : The source data address.
552 * @param DstAddress : The destination data address.
553 * @param SrcDataSize : The length of data to be transferred from source to destination in bytes.
554 * @retval HAL status.
555 */
HAL_DMA_Start_IT(DMA_HandleTypeDef * const hdma,uint32_t SrcAddress,uint32_t DstAddress,uint32_t SrcDataSize)556 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma,
557 uint32_t SrcAddress,
558 uint32_t DstAddress,
559 uint32_t SrcDataSize)
560 {
561 /* Check the DMA peripheral handle parameter */
562 if (hdma == NULL)
563 {
564 return HAL_ERROR;
565 }
566
567 /* Check the parameters */
568 assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize));
569
570 /* Process locked */
571 __HAL_LOCK(hdma);
572
573 /* Check DMA channel state */
574 if (hdma->State == HAL_DMA_STATE_READY)
575 {
576 /* Update the DMA channel state */
577 hdma->State = HAL_DMA_STATE_BUSY;
578
579 /* Update the DMA channel error code */
580 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
581
582 /* Configure the source address, destination address, the data size and clear flags */
583 DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize);
584
585 /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */
586 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO));
587
588 /* Check half transfer complete callback */
589 if (hdma->XferHalfCpltCallback != NULL)
590 {
591 /* If Half Transfer complete callback is set, enable the corresponding IT */
592 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
593 }
594
595 /* Check Half suspend callback */
596 if (hdma->XferSuspendCallback != NULL)
597 {
598 /* If Transfer suspend callback is set, enable the corresponding IT */
599 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP);
600 }
601
602 /* Enable DMA channel */
603 __HAL_DMA_ENABLE(hdma);
604 }
605 else
606 {
607 /* Update the DMA channel error code */
608 hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
609
610 /* Process unlocked */
611 __HAL_UNLOCK(hdma);
612
613 return HAL_ERROR;
614 }
615
616 return HAL_OK;
617 }
618
619 /**
620 * @brief Abort any on-going DMA channel transfer (Blocking mode).
621 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
622 * specified DMA Channel.
623 * @note After suspending a DMA channel, a wait until the DMA channel is effectively stopped is added. If a channel
624 * is suspended while a data transfer is on-going, the current data will be transferred and the channel will be
625 * effectively suspended only after the transfer of any on-going data is finished.
626 * @retval HAL status.
627 */
HAL_DMA_Abort(DMA_HandleTypeDef * const hdma)628 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma)
629 {
630 /* Get tick number */
631 uint32_t tickstart = HAL_GetTick();
632
633 /* Check the DMA peripheral handle parameter */
634 if (hdma == NULL)
635 {
636 return HAL_ERROR;
637 }
638
639 /* Check DMA channel state */
640 if (hdma->State != HAL_DMA_STATE_BUSY)
641 {
642 /* Update the DMA channel error code */
643 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
644
645 /* Process Unlocked */
646 __HAL_UNLOCK(hdma);
647
648 return HAL_ERROR;
649 }
650 else
651 {
652 /* Suspend the channel */
653 hdma->Instance->CCR |= DMA_CCR_SUSP;
654
655 /* Update the DMA channel state */
656 hdma->State = HAL_DMA_STATE_SUSPEND;
657
658 /* Check if the DMA Channel is suspended */
659 while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U)
660 {
661 /* Check for the Timeout */
662 if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
663 {
664 /* Update the DMA channel error code */
665 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
666
667 /* Update the DMA channel state */
668 hdma->State = HAL_DMA_STATE_ERROR;
669
670 /* Check DMA channel transfer mode */
671 if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
672 {
673 /* Update the linked-list queue state */
674 hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
675 }
676
677 /* Process Unlocked */
678 __HAL_UNLOCK(hdma);
679
680 return HAL_ERROR;
681 }
682 }
683
684 /* Reset the channel */
685 hdma->Instance->CCR |= DMA_CCR_RESET;
686
687 /* Update the DMA channel state */
688 hdma->State = HAL_DMA_STATE_ABORT;
689
690 /* Clear all status flags */
691 __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
692 DMA_FLAG_TO));
693
694 /* Update the DMA channel state */
695 hdma->State = HAL_DMA_STATE_READY;
696
697 /* Check DMA channel transfer mode */
698 if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
699 {
700 /* Update the linked-list queue state */
701 hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
702
703 /* Clear remaining data size to ensure loading linked-list from memory next start */
704 hdma->Instance->CBR1 = 0U;
705 }
706
707 /* Process Unlocked */
708 __HAL_UNLOCK(hdma);
709 }
710
711 return HAL_OK;
712 }
713
714 /**
715 * @brief Abort any on-going DMA channel transfer in interrupt mode (Non-blocking mode).
716 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
717 * specified DMA Channel.
718 * @retval HAL status.
719 */
HAL_DMA_Abort_IT(DMA_HandleTypeDef * const hdma)720 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma)
721 {
722 /* Check the DMA peripheral handle parameter */
723 if (hdma == NULL)
724 {
725 return HAL_ERROR;
726 }
727
728 /* Check DMA channel state */
729 if (hdma->State != HAL_DMA_STATE_BUSY)
730 {
731 /* Update the DMA channel error code */
732 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
733
734 return HAL_ERROR;
735 }
736 else
737 {
738 /* Update the DMA channel state */
739 hdma->State = HAL_DMA_STATE_ABORT;
740
741 /* Suspend the channel and activate suspend interrupt */
742 hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE);
743 }
744
745 return HAL_OK;
746 }
747
748 /**
749 * @brief Polling for transfer status (Blocking mode).
750 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
751 * specified DMA Channel.
752 * @param CompleteLevel : Specifies the DMA level complete.
753 * @param Timeout : Timeout duration.
754 * @retval HAL status
755 */
HAL_DMA_PollForTransfer(DMA_HandleTypeDef * const hdma,HAL_DMA_LevelCompleteTypeDef CompleteLevel,uint32_t Timeout)756 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma,
757 HAL_DMA_LevelCompleteTypeDef CompleteLevel,
758 uint32_t Timeout)
759 {
760 /* Get tick number */
761 uint32_t tickstart = HAL_GetTick();
762 uint32_t level_flag;
763 uint32_t tmp_csr;
764
765 /* Check the DMA peripheral handle parameter */
766 if (hdma == NULL)
767 {
768 return HAL_ERROR;
769 }
770
771 /* Check the parameters */
772 assert_param(IS_DMA_LEVEL_COMPLETE(CompleteLevel));
773
774 /* Check DMA channel state */
775 if (hdma->State != HAL_DMA_STATE_BUSY)
776 {
777 /* Update the DMA channel error code */
778 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
779
780 /* Process Unlocked */
781 __HAL_UNLOCK(hdma);
782
783 return HAL_ERROR;
784 }
785
786 /* Polling mode is not supported in circular mode */
787 if ((hdma->Mode & DMA_LINKEDLIST_CIRCULAR) == DMA_LINKEDLIST_CIRCULAR)
788 {
789 /* Update the DMA channel error code */
790 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
791
792 return HAL_ERROR;
793 }
794
795 /* Get the level transfer complete flag */
796 level_flag = ((CompleteLevel == HAL_DMA_FULL_TRANSFER) ? DMA_FLAG_IDLE : DMA_FLAG_HT);
797
798 /* Get DMA channel status */
799 tmp_csr = hdma->Instance->CSR;
800
801 while ((tmp_csr & level_flag) == 0U)
802 {
803 /* Check for the timeout */
804 if (Timeout != HAL_MAX_DELAY)
805 {
806 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
807 {
808 /* Update the DMA channel error code */
809 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
810
811 /*
812 If timeout, abort the current transfer.
813 Note that the Abort function will
814 - Clear all transfer flags.
815 - Unlock.
816 - Set the State.
817 */
818 (void)HAL_DMA_Abort(hdma);
819
820 return HAL_ERROR;
821 }
822 }
823
824 /* Get a newer CSR register value */
825 tmp_csr = hdma->Instance->CSR;
826 }
827
828 /* Check trigger overrun flag */
829 if ((tmp_csr & DMA_FLAG_TO) != 0U)
830 {
831 /* Update the DMA channel error code */
832 hdma->ErrorCode |= HAL_DMA_ERROR_TO;
833
834 /* Clear the error flag */
835 __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO);
836 }
837
838 /* Check error flags */
839 if ((tmp_csr & (DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE)) != 0U)
840 {
841 /* Check the data transfer error flag */
842 if ((tmp_csr & DMA_FLAG_DTE) != 0U)
843 {
844 /* Update the DMA channel error code */
845 hdma->ErrorCode |= HAL_DMA_ERROR_DTE;
846
847 /* Clear the error flag */
848 __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE);
849 }
850
851 /* Check the update link error flag */
852 if ((tmp_csr & DMA_FLAG_ULE) != 0U)
853 {
854 /* Update the DMA channel error code */
855 hdma->ErrorCode |= HAL_DMA_ERROR_ULE;
856
857 /* Clear the error flag */
858 __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE);
859 }
860
861 /* Check the user setting error flag */
862 if ((tmp_csr & DMA_FLAG_USE) != 0U)
863 {
864 /* Update the DMA channel error code */
865 hdma->ErrorCode |= HAL_DMA_ERROR_USE;
866
867 /* Clear the error flag */
868 __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE);
869 }
870
871 /* Reset the channel */
872 hdma->Instance->CCR |= DMA_CCR_RESET;
873
874 /* Update the DMA channel state */
875 hdma->State = HAL_DMA_STATE_READY;
876
877 /* Check DMA channel transfer mode */
878 if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
879 {
880 /* Update the linked-list queue state */
881 hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
882 }
883
884 /* Process Unlocked */
885 __HAL_UNLOCK(hdma);
886
887 return HAL_ERROR;
888 }
889
890 /* Clear the transfer level flag */
891 if (CompleteLevel == HAL_DMA_HALF_TRANSFER)
892 {
893 /* Clear the Half Transfer flag */
894 __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT);
895 }
896 else if (CompleteLevel == HAL_DMA_FULL_TRANSFER)
897 {
898 /* Clear the transfer flags */
899 __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT));
900
901 /* Update the DMA channel state */
902 hdma->State = HAL_DMA_STATE_READY;
903
904 /* Check DMA channel transfer mode */
905 if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
906 {
907 /* Update the linked-list queue state */
908 hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
909 }
910
911 /* Process unlocked */
912 __HAL_UNLOCK(hdma);
913 }
914 else
915 {
916 return HAL_ERROR;
917 }
918
919 return HAL_OK;
920 }
921
922 /**
923 * @brief Handle DMA interrupt request (Non-blocking mode).
924 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
925 * specified DMA Channel.
926 * @retval None.
927 */
HAL_DMA_IRQHandler(DMA_HandleTypeDef * const hdma)928 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
929 {
930 const DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma);
931 uint32_t global_it_flag = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
932 uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag);
933 #if defined (CPU_IN_SECURE_STATE)
934 uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag);
935 #endif /* CPU_IN_SECURE_STATE */
936
937 /* Global Interrupt Flag management *********************************************************************************/
938 #if defined (CPU_IN_SECURE_STATE)
939 if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U))
940 #else
941 if (global_active_flag_ns == 0U)
942 #endif /* CPU_IN_SECURE_STATE */
943 {
944 return; /* the global interrupt flag for the current channel is down , nothing to do */
945 }
946
947 /* Data Transfer Error Interrupt management *************************************************************************/
948 if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U)
949 {
950 /* Check if interrupt source is enabled */
951 if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U)
952 {
953 /* Clear the transfer error flag */
954 __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE);
955
956 /* Update the DMA channel error code */
957 hdma->ErrorCode |= HAL_DMA_ERROR_DTE;
958 }
959 }
960
961 /* Update Linked-list Error Interrupt management ********************************************************************/
962 if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U)
963 {
964 /* Check if interrupt source is enabled */
965 if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U)
966 {
967 /* Clear the update linked-list error flag */
968 __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE);
969
970 /* Update the DMA channel error code */
971 hdma->ErrorCode |= HAL_DMA_ERROR_ULE;
972 }
973 }
974
975 /* User Setting Error Interrupt management **************************************************************************/
976 if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U)
977 {
978 /* Check if interrupt source is enabled */
979 if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U)
980 {
981 /* Clear the user setting error flag */
982 __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE);
983
984 /* Update the DMA channel error code */
985 hdma->ErrorCode |= HAL_DMA_ERROR_USE;
986 }
987 }
988
989 /* Trigger Overrun Interrupt management *****************************************************************************/
990 if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U)
991 {
992 /* Check if interrupt source is enabled */
993 if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U)
994 {
995 /* Clear the trigger overrun flag */
996 __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO);
997
998 /* Update the DMA channel error code */
999 hdma->ErrorCode |= HAL_DMA_ERROR_TO;
1000 }
1001 }
1002
1003 /* Half Transfer Complete Interrupt management **********************************************************************/
1004 if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U)
1005 {
1006 /* Check if interrupt source is enabled */
1007 if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
1008 {
1009 /* Clear the half transfer flag */
1010 __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT);
1011
1012 /* Check half transfer complete callback */
1013 if (hdma->XferHalfCpltCallback != NULL)
1014 {
1015 /* Half transfer callback */
1016 hdma->XferHalfCpltCallback(hdma);
1017 }
1018 }
1019 }
1020
1021 /* Suspend Transfer Interrupt management ****************************************************************************/
1022 if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U)
1023 {
1024 /* Check if interrupt source is enabled */
1025 if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U)
1026 {
1027 /* Clear the block transfer complete flag */
1028 __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_SUSP);
1029
1030 /* Check DMA channel state */
1031 if (hdma->State == HAL_DMA_STATE_ABORT)
1032 {
1033 /* Disable the suspend transfer interrupt */
1034 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_SUSP);
1035
1036 /* Reset the channel internal state and reset the FIFO */
1037 hdma->Instance->CCR |= DMA_CCR_RESET;
1038
1039 /* Update the DMA channel state */
1040 hdma->State = HAL_DMA_STATE_READY;
1041
1042 /* Check DMA channel transfer mode */
1043 if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1044 {
1045 /* Update the linked-list queue state */
1046 hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
1047
1048 /* Clear remaining data size to ensure loading linked-list from memory next start */
1049 hdma->Instance->CBR1 = 0U;
1050 }
1051
1052 /* Process Unlocked */
1053 __HAL_UNLOCK(hdma);
1054
1055 /* Check transfer abort callback */
1056 if (hdma->XferAbortCallback != NULL)
1057 {
1058 /* Transfer abort callback */
1059 hdma->XferAbortCallback(hdma);
1060 }
1061
1062 return;
1063 }
1064 else
1065 {
1066 /* Update the DMA channel state */
1067 hdma->State = HAL_DMA_STATE_SUSPEND;
1068
1069 /* Check transfer suspend callback */
1070 if (hdma->XferSuspendCallback != NULL)
1071 {
1072 /* Transfer suspend callback */
1073 hdma->XferSuspendCallback(hdma);
1074 }
1075 }
1076 }
1077 }
1078
1079 /* Transfer Complete Interrupt management ***************************************************************************/
1080 if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U)
1081 {
1082 /* Check if interrupt source is enabled */
1083 if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
1084 {
1085 /* Check DMA channel transfer mode */
1086 if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1087 {
1088 /* If linked-list transfer */
1089 if (hdma->Instance->CLLR == 0U)
1090 {
1091 if (hdma->Instance->CBR1 == 0U)
1092 {
1093 /* Update the DMA channel state */
1094 hdma->State = HAL_DMA_STATE_READY;
1095
1096 /* Update the linked-list queue state */
1097 hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
1098 }
1099 }
1100 }
1101 else
1102 {
1103 /* If normal transfer */
1104 if (hdma->Instance->CBR1 == 0U)
1105 {
1106 /* Update the DMA channel state */
1107 hdma->State = HAL_DMA_STATE_READY;
1108 }
1109 }
1110
1111 /* Clear TC and HT transfer flags */
1112 __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT));
1113
1114 /* Process Unlocked */
1115 __HAL_UNLOCK(hdma);
1116
1117 /* Check transfer complete callback */
1118 if (hdma->XferCpltCallback != NULL)
1119 {
1120 /* Channel Transfer Complete callback */
1121 hdma->XferCpltCallback(hdma);
1122 }
1123 }
1124 }
1125
1126 /* Manage error case ************************************************************************************************/
1127 if (hdma->ErrorCode != HAL_DMA_ERROR_NONE)
1128 {
1129 /* Reset the channel internal state and reset the FIFO */
1130 hdma->Instance->CCR |= DMA_CCR_RESET;
1131
1132 /* Update the DMA channel state */
1133 hdma->State = HAL_DMA_STATE_READY;
1134
1135 /* Check DMA channel transfer mode */
1136 if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1137 {
1138 /* Update the linked-list queue state */
1139 hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
1140 }
1141
1142 /* Process Unlocked */
1143 __HAL_UNLOCK(hdma);
1144
1145 /* Check transfer error callback */
1146 if (hdma->XferErrorCallback != NULL)
1147 {
1148 /* Transfer error callback */
1149 hdma->XferErrorCallback(hdma);
1150 }
1151 }
1152 }
1153
1154 /**
1155 * @brief Register callback according to specified ID.
1156 * @note The HAL_DMA_RegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET
1157 * to register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID.
1158 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
1159 * specified DMA Channel.
1160 * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration.
1161 * @param pCallback : Pointer to private callback function.
1162 * @retval HAL status.
1163 */
HAL_DMA_RegisterCallback(DMA_HandleTypeDef * const hdma,HAL_DMA_CallbackIDTypeDef CallbackID,void (* const pCallback)(DMA_HandleTypeDef * const _hdma))1164 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma,
1165 HAL_DMA_CallbackIDTypeDef CallbackID,
1166 void (*const pCallback)(DMA_HandleTypeDef *const _hdma))
1167 {
1168 HAL_StatusTypeDef status = HAL_OK;
1169
1170 /* Check the DMA peripheral handle parameter */
1171 if (hdma == NULL)
1172 {
1173 return HAL_ERROR;
1174 }
1175
1176 /* Check DMA channel state */
1177 if (hdma->State == HAL_DMA_STATE_READY)
1178 {
1179 /* Check callback ID */
1180 switch (CallbackID)
1181 {
1182 case HAL_DMA_XFER_CPLT_CB_ID:
1183 {
1184 /* Register transfer complete callback */
1185 hdma->XferCpltCallback = pCallback;
1186 break;
1187 }
1188
1189 case HAL_DMA_XFER_HALFCPLT_CB_ID:
1190 {
1191 /* Register half transfer callback */
1192 hdma->XferHalfCpltCallback = pCallback;
1193 break;
1194 }
1195
1196 case HAL_DMA_XFER_ERROR_CB_ID:
1197 {
1198 /* Register transfer error callback */
1199 hdma->XferErrorCallback = pCallback;
1200 break;
1201 }
1202
1203 case HAL_DMA_XFER_ABORT_CB_ID:
1204 {
1205 /* Register abort callback */
1206 hdma->XferAbortCallback = pCallback;
1207 break;
1208 }
1209
1210 case HAL_DMA_XFER_SUSPEND_CB_ID:
1211 {
1212 /* Register suspend callback */
1213 hdma->XferSuspendCallback = pCallback;
1214 break;
1215 }
1216
1217 default:
1218 {
1219 /* Update error status */
1220 status = HAL_ERROR;
1221 break;
1222 }
1223 }
1224 }
1225 else
1226 {
1227 /* Update error status */
1228 status = HAL_ERROR;
1229 }
1230
1231 return status;
1232 }
1233
1234 /**
1235 * @brief Unregister callback according to specified ID.
1236 * @note The HAL_DMA_UnRegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET
1237 * to un-register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID.
1238 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
1239 * specified DMA Channel.
1240 * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum.
1241 * @retval HAL status.
1242 */
HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef * const hdma,HAL_DMA_CallbackIDTypeDef CallbackID)1243 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma,
1244 HAL_DMA_CallbackIDTypeDef CallbackID)
1245 {
1246 HAL_StatusTypeDef status = HAL_OK;
1247
1248 /* Check the DMA peripheral handle parameter */
1249 if (hdma == NULL)
1250 {
1251 return HAL_ERROR;
1252 }
1253
1254 /* Check DMA channel state */
1255 if (hdma->State == HAL_DMA_STATE_READY)
1256 {
1257 /* Check callback ID */
1258 switch (CallbackID)
1259 {
1260 case HAL_DMA_XFER_CPLT_CB_ID:
1261 {
1262 /* UnRegister transfer complete callback */
1263 hdma->XferCpltCallback = NULL;
1264 break;
1265 }
1266
1267 case HAL_DMA_XFER_HALFCPLT_CB_ID:
1268 {
1269 /* UnRegister half transfer callback */
1270 hdma->XferHalfCpltCallback = NULL;
1271 break;
1272 }
1273
1274 case HAL_DMA_XFER_ERROR_CB_ID:
1275 {
1276 /* UnRegister transfer error callback */
1277 hdma->XferErrorCallback = NULL;
1278 break;
1279 }
1280
1281 case HAL_DMA_XFER_ABORT_CB_ID:
1282 {
1283 /* UnRegister abort callback */
1284 hdma->XferAbortCallback = NULL;
1285 break;
1286 }
1287
1288 case HAL_DMA_XFER_SUSPEND_CB_ID:
1289 {
1290 /* UnRegister suspend callback */
1291 hdma->XferSuspendCallback = NULL;
1292 break;
1293 }
1294
1295 case HAL_DMA_XFER_ALL_CB_ID:
1296 {
1297 /* UnRegister all available callbacks */
1298 hdma->XferCpltCallback = NULL;
1299 hdma->XferHalfCpltCallback = NULL;
1300 hdma->XferErrorCallback = NULL;
1301 hdma->XferAbortCallback = NULL;
1302 hdma->XferSuspendCallback = NULL;
1303 break;
1304 }
1305
1306 default:
1307 {
1308 /* Update error status */
1309 status = HAL_ERROR;
1310 break;
1311 }
1312 }
1313 }
1314 else
1315 {
1316 /* Update error status */
1317 status = HAL_ERROR;
1318 }
1319
1320 return status;
1321 }
1322 /**
1323 * @}
1324 */
1325
1326 /** @addtogroup DMA_Exported_Functions_Group3
1327 *
1328 @verbatim
1329 ======================================================================================================================
1330 ##### State and Errors functions #####
1331 ======================================================================================================================
1332 [..]
1333 This section provides functions allowing to :
1334 (+) Check the DMA state
1335 (+) Get error code
1336
1337 [..]
1338 (+) The HAL_DMA_GetState() function allows to get the DMA channel state.
1339 (+) The HAL_DMA_DeInit() function allows to get the DMA channel error code.
1340
1341 @endverbatim
1342 * @{
1343 */
1344
1345 /**
1346 * @brief Returns the DMA channel state.
1347 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
1348 * specified DMA Channel.
1349 * @retval DMA state.
1350 */
HAL_DMA_GetState(DMA_HandleTypeDef const * const hdma)1351 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma)
1352 {
1353 /* Return the DMA channel state */
1354 return hdma->State;
1355 }
1356
1357 /**
1358 * @brief Return the DMA channel error code.
1359 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
1360 * specified DMA Channel.
1361 * @retval DMA Error Code.
1362 */
HAL_DMA_GetError(DMA_HandleTypeDef const * const hdma)1363 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma)
1364 {
1365 /* Return the DMA channel error code */
1366 return hdma->ErrorCode;
1367 }
1368 /**
1369 * @}
1370 */
1371
1372 /** @addtogroup DMA_Exported_Functions_Group4
1373 *
1374 @verbatim
1375 ======================================================================================================================
1376 ##### DMA Attributes functions #####
1377 ======================================================================================================================
1378 [..]
1379 This section provides functions allowing to :
1380 (+) Configure DMA channel secure and privilege attributes.
1381 (+) Get DMA channel secure and privilege attributes.
1382 (+) Lock DMA channel secure and privilege attributes configuration.
1383 (+) Check whether DMA channel secure and privilege attributes configuration is locked or not.
1384
1385 [..]
1386 (+) The HAL_DMA_ConfigChannelAttributes() function allows to configure DMA channel security and privilege
1387 attributes.
1388 (+) The HAL_DMA_GetConfigChannelAttributes() function allows to get DMA channel security and privilege attributes
1389 configuration.
1390 (+) The HAL_DMA_LockChannelAttributes() function allows to lock the DMA channel security and privilege attributes.
1391 (+) The HAL_DMA_GetLockChannelAttributes() function allows to get the DMA channel security and privilege
1392 attributes lock status.
1393
1394 @endverbatim
1395 * @{
1396 */
1397
1398 /**
1399 * @brief Configure the DMA channel security and privilege attribute(s).
1400 * @note These attributes cannot be modified when the corresponding lock state is enabled.
1401 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for
1402 * the specified DMA Channel.
1403 * @param ChannelAttributes : Specifies the DMA channel secure/privilege attributes.
1404 * This parameter can be a one or a combination of @ref DMA_Channel_Attributes.
1405 * @retval HAL Status.
1406 */
HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef * const hdma,uint32_t ChannelAttributes)1407 HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, uint32_t ChannelAttributes)
1408 {
1409 DMA_TypeDef *p_dma_instance;
1410 uint32_t channel_idx;
1411
1412 /* Check the DMA peripheral handle parameter */
1413 if (hdma == NULL)
1414 {
1415 return HAL_ERROR;
1416 }
1417
1418 /* Check the parameters */
1419 assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes));
1420
1421 /* Get DMA instance */
1422 p_dma_instance = GET_DMA_INSTANCE(hdma);
1423
1424 /* Get channel index */
1425 channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
1426
1427 /* Check DMA channel privilege attribute management */
1428 if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) == DMA_CHANNEL_ATTR_PRIV_MASK)
1429 {
1430 /* Configure DMA channel privilege attribute */
1431 if ((ChannelAttributes & DMA_CHANNEL_PRIV) == DMA_CHANNEL_PRIV)
1432 {
1433 p_dma_instance->PRIVCFGR |= channel_idx;
1434 }
1435 else
1436 {
1437 p_dma_instance->PRIVCFGR &= (~channel_idx);
1438 }
1439 }
1440
1441 #if defined (CPU_IN_SECURE_STATE)
1442 /* Check DMA channel security attribute management */
1443 if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_MASK) == DMA_CHANNEL_ATTR_SEC_MASK)
1444 {
1445 /* Configure DMA channel security attribute */
1446 if ((ChannelAttributes & DMA_CHANNEL_SEC) == DMA_CHANNEL_SEC)
1447 {
1448 p_dma_instance->SECCFGR |= channel_idx;
1449 }
1450 else
1451 {
1452 p_dma_instance->SECCFGR &= (~channel_idx);
1453 }
1454 }
1455
1456 /* Channel source security attribute management */
1457 if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_SRC_MASK) == DMA_CHANNEL_ATTR_SEC_SRC_MASK)
1458 {
1459 /* Configure DMA channel source security attribute */
1460 if ((ChannelAttributes & DMA_CHANNEL_SRC_SEC) == DMA_CHANNEL_SRC_SEC)
1461 {
1462 hdma->Instance->CTR1 |= DMA_CTR1_SSEC;
1463 }
1464 else
1465 {
1466 hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC);
1467 }
1468 }
1469
1470 /* Channel destination security attribute management */
1471 if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_DEST_MASK) == DMA_CHANNEL_ATTR_SEC_DEST_MASK)
1472 {
1473 /* Configure DMA channel destination security attribute */
1474 if ((ChannelAttributes & DMA_CHANNEL_DEST_SEC) == DMA_CHANNEL_DEST_SEC)
1475 {
1476 hdma->Instance->CTR1 |= DMA_CTR1_DSEC;
1477 }
1478 else
1479 {
1480 hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC);
1481 }
1482 }
1483 #endif /* CPU_IN_SECURE_STATE */
1484
1485 return HAL_OK;
1486 }
1487
1488 /**
1489 * @brief Get the DMA channel security and privilege attributes.
1490 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
1491 * for the specified DMA Channel.
1492 * @param pChannelAttributes : Pointer to the returned attributes.
1493 * @retval HAL Status.
1494 */
HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const * const hdma,uint32_t * const pChannelAttributes)1495 HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma,
1496 uint32_t *const pChannelAttributes)
1497 {
1498 const DMA_TypeDef *p_dma_instance;
1499 uint32_t attributes;
1500 uint32_t channel_idx;
1501
1502 /* Check the DMA peripheral handle and channel attributes parameters */
1503 if ((hdma == NULL) || (pChannelAttributes == NULL))
1504 {
1505 return HAL_ERROR;
1506 }
1507
1508 /* Get DMA instance */
1509 p_dma_instance = GET_DMA_INSTANCE(hdma);
1510
1511 /* Get channel index */
1512 channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
1513
1514 /* Get DMA channel privilege attribute */
1515 attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV;
1516
1517 /* Get DMA channel security attribute */
1518 attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC;
1519
1520 /* Get DMA channel source security attribute */
1521 attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_SRC_SEC;
1522
1523 /* Get DMA channel destination security attribute */
1524 attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC;
1525
1526 /* return value */
1527 *pChannelAttributes = attributes;
1528
1529 return HAL_OK;
1530 }
1531
1532 #if defined (CPU_IN_SECURE_STATE)
1533 /**
1534 * @brief Set the DMA channel filtering CID (Isolation configuration). It can be
1535 * - static: the CID passed as parameter is programmed;
1536 * - disabled: the whole register is cleared.
1537 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
1538 * of the HPDMA channel.
1539 * @param pConfig : Pointer on the DMA Isolation structure
1540 * @retval None
1541 */
HAL_DMA_SetIsolationAttributes(DMA_HandleTypeDef * const hdma,DMA_IsolationConfigTypeDef const * const pConfig)1542 HAL_StatusTypeDef HAL_DMA_SetIsolationAttributes(DMA_HandleTypeDef *const hdma,
1543 DMA_IsolationConfigTypeDef const *const pConfig)
1544 {
1545 /* Check the DMA peripheral handle parameter */
1546 if ((hdma == NULL) || (pConfig == NULL))
1547 {
1548 return HAL_ERROR;
1549 }
1550
1551 /* Check the parameters */
1552 assert_param(IS_HPDMA_INSTANCE(hdma->Instance));
1553 assert_param(IS_DMA_ISOLATION_MODE(pConfig->CidFiltering));
1554 assert_param(IS_DMA_ISOLATION_STATIC_CID(pConfig->StaticCid));
1555
1556 /* static CID field value used when filtering is enable */
1557 if ((pConfig->CidFiltering) == DMA_ISOLATION_ON)
1558 {
1559 /* Write static CID configuration */
1560 hdma->Instance->CCIDCFGR = ((pConfig->StaticCid & DMA_CCIDCFGR_SCID_Msk) | DMA_CCIDCFGR_CFEN);
1561 }
1562 else
1563 {
1564 /* CID configuration is off */
1565 hdma->Instance->CCIDCFGR = 0U;
1566 }
1567
1568 return HAL_OK;
1569 }
1570 #endif /* CPU_IN_SECURE_STATE */
1571 /**
1572 * @brief Read the DMA channel filtering CID (Isolation configuration). It can be
1573 * - static: the CID passed as parameter is programmed;
1574 * - disabled: the whole register is cleared.
1575 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
1576 * of the HPDMA channel.
1577 * @param pConfig : Pointer on the DMA Isolation structure
1578 * @retval None
1579 */
HAL_DMA_GetIsolationAttributes(DMA_HandleTypeDef const * const hdma,DMA_IsolationConfigTypeDef * const pConfig)1580 HAL_StatusTypeDef HAL_DMA_GetIsolationAttributes(DMA_HandleTypeDef const *const hdma,
1581 DMA_IsolationConfigTypeDef *const pConfig)
1582 {
1583 uint32_t ccidcfgr;
1584
1585 /* Check the DMA peripheral handle parameter */
1586 if ((hdma == NULL) || (pConfig == NULL))
1587 {
1588 return HAL_ERROR;
1589 }
1590
1591 ccidcfgr = hdma->Instance->CCIDCFGR;
1592
1593 /* Check the parameters */
1594 assert_param(IS_HPDMA_INSTANCE(hdma->Instance));
1595
1596 if ((ccidcfgr & DMA_CCIDCFGR_CFEN) == DMA_CCIDCFGR_CFEN)
1597 {
1598 pConfig->CidFiltering = DMA_ISOLATION_ON;
1599 }
1600 else
1601 {
1602 pConfig->CidFiltering = DMA_ISOLATION_OFF;
1603 }
1604 pConfig->StaticCid = (ccidcfgr & DMA_CCIDCFGR_SCID_Msk);
1605
1606 return HAL_OK;
1607 }
1608
1609
1610 #if defined (CPU_IN_SECURE_STATE)
1611 /**
1612 * @brief Lock the DMA channel security and privilege attribute(s).
1613 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
1614 * specified DMA Channel.
1615 * @retval HAL Status.
1616 */
HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const * const hdma)1617 HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma)
1618 {
1619 DMA_TypeDef *p_dma_instance;
1620 uint32_t channel_idx;
1621
1622 /* Check the DMA peripheral handle parameter */
1623 if (hdma == NULL)
1624 {
1625 return HAL_ERROR;
1626 }
1627
1628 /* Get DMA instance */
1629 p_dma_instance = GET_DMA_INSTANCE(hdma);
1630
1631 /* Get channel index */
1632 channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
1633
1634 /* Lock the DMA channel privilege and security attributes */
1635 p_dma_instance->RCFGLOCKR |= channel_idx;
1636
1637 return HAL_OK;
1638 }
1639 #endif /* CPU_IN_SECURE_STATE */
1640
1641 /**
1642 * @brief Get the security and privilege attribute lock state of a DMA channel.
1643 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
1644 * specified DMA Channel.
1645 * @param pLockState : Pointer to lock state (returned value can be DMA_CHANNEL_ATTRIBUTE_UNLOCKED or
1646 * DMA_CHANNEL_ATTRIBUTE_LOCKED).
1647 * @retval HAL status.
1648 */
HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const * const hdma,uint32_t * const pLockState)1649 HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState)
1650 {
1651 const DMA_TypeDef *p_dma_instance;
1652 uint32_t channel_idx;
1653
1654 /* Check the DMA peripheral handle and lock state parameters */
1655 if ((hdma == NULL) || (pLockState == NULL))
1656 {
1657 return HAL_ERROR;
1658 }
1659
1660 /* Get DMA instance */
1661 p_dma_instance = GET_DMA_INSTANCE(hdma);
1662
1663 /* Get channel index */
1664 channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
1665
1666 /* Get channel lock attribute state */
1667 *pLockState = ((p_dma_instance->RCFGLOCKR & channel_idx) == 0U) ? DMA_CHANNEL_ATTRIBUTE_UNLOCKED : \
1668 DMA_CHANNEL_ATTRIBUTE_LOCKED;
1669
1670 return HAL_OK;
1671 }
1672 /**
1673 * @}
1674 */
1675
1676 /**
1677 * @}
1678 */
1679
1680
1681 /* Private functions -------------------------------------------------------------------------------------------------*/
1682 /** @defgroup DMA_Private_Functions DMA Private Functions
1683 * @brief DMA Private Functions
1684 * @{
1685 */
1686
1687 /**
1688 * @brief Set the DMA channel normal transfer parameters.
1689 * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
1690 * specified DMA Channel.
1691 * @param SrcAddress : The source data address.
1692 * @param DstAddress : The destination data address.
1693 * @param SrcDataSize : The length of data to be transferred from source to destination in bytes.
1694 * @retval None.
1695 */
DMA_SetConfig(DMA_HandleTypeDef const * const hdma,uint32_t SrcAddress,uint32_t DstAddress,uint32_t SrcDataSize)1696 static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma,
1697 uint32_t SrcAddress,
1698 uint32_t DstAddress,
1699 uint32_t SrcDataSize)
1700 {
1701 /* Configure the DMA channel data size */
1702 MODIFY_REG(hdma->Instance->CBR1, DMA_CBR1_BNDT, (SrcDataSize & DMA_CBR1_BNDT));
1703
1704 /* Clear all interrupt flags */
1705 __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
1706 DMA_FLAG_TO);
1707
1708 /* Configure DMA channel source address */
1709 hdma->Instance->CSAR = SrcAddress;
1710
1711 /* Configure DMA channel destination address */
1712 hdma->Instance->CDAR = DstAddress;
1713 }
1714
1715 /**
1716 * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef.
1717 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
1718 * specified DMA Channel.
1719 * @retval None.
1720 */
DMA_Init(DMA_HandleTypeDef const * const hdma)1721 static void DMA_Init(DMA_HandleTypeDef const *const hdma)
1722 {
1723 uint32_t tmpreg;
1724
1725 /* Prepare DMA Channel Control Register (CCR) value *****************************************************************/
1726 tmpreg = hdma->Init.Priority;
1727
1728 /* Write DMA Channel Control Register (CCR) */
1729 MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg);
1730
1731 /* Prepare DMA Channel Transfer Register (CTR1) value ***************************************************************/
1732 tmpreg = hdma->Init.DestInc | hdma->Init.DestDataWidth | hdma->Init.SrcInc | hdma->Init.SrcDataWidth;
1733
1734 /* Add parameters specific to HPDMA and GPDMA */
1735 if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U))
1736 {
1737 tmpreg |= (hdma->Init.TransferAllocatedPort |
1738 (((hdma->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) |
1739 (((hdma->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1));
1740 }
1741
1742 /* Write DMA Channel Transfer Register 1 (CTR1) */
1743 MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg);
1744
1745 /* Prepare DMA Channel Transfer Register 2 (CTR2) value *************************************************************/
1746 tmpreg = hdma->Init.BlkHWRequest | (hdma->Init.Request & DMA_CTR2_REQSEL) | hdma->Init.TransferEventMode;
1747
1748 /* Memory to Peripheral Transfer */
1749 if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
1750 {
1751 if ((IS_HPDMA_INSTANCE(hdma->Instance) != 0U) || (IS_GPDMA_INSTANCE(hdma->Instance) != 0U))
1752 {
1753 tmpreg |= DMA_CTR2_DREQ;
1754 }
1755 }
1756 /* Memory to Memory Transfer */
1757 else if ((hdma->Init.Direction) == DMA_MEMORY_TO_MEMORY)
1758 {
1759 tmpreg |= DMA_CTR2_SWREQ;
1760 }
1761 else
1762 {
1763 /* Nothing to do */
1764 }
1765
1766 /* Set DMA channel operation mode */
1767 tmpreg |= hdma->Init.Mode;
1768
1769 /* Write DMA Channel Transfer Register 2 (CTR2) */
1770 MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM |
1771 DMA_CTR2_PFREQ | DMA_CTR2_BREQ | DMA_CTR2_DREQ | DMA_CTR2_SWREQ |
1772 DMA_CTR2_REQSEL), tmpreg);
1773
1774
1775 /* Write DMA Channel Block Register 1 (CBR1) ************************************************************************/
1776 WRITE_REG(hdma->Instance->CBR1, 0U);
1777
1778 /* If 2D Addressing is supported by current channel */
1779 if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
1780 {
1781 /* Write DMA Channel Transfer Register 3 (CTR3) *******************************************************************/
1782 WRITE_REG(hdma->Instance->CTR3, 0U);
1783
1784 /* Write DMA Channel Block Register 2 (CBR2) **********************************************************************/
1785 WRITE_REG(hdma->Instance->CBR2, 0U);
1786 }
1787
1788 /* Write DMA Channel linked-list address register (CLLR) ************************************************************/
1789 WRITE_REG(hdma->Instance->CLLR, 0U);
1790 }
1791 /**
1792 * @}
1793 */
1794
1795 #endif /* HAL_DMA_MODULE_ENABLED */
1796
1797 /**
1798 * @}
1799 */
1800
1801 /**
1802 * @}
1803 */
1804
