1 /**
2 ******************************************************************************
3 * @file stm32n6xx_hal_dcmipp.c
4 * @author MCD Application Team
5 * @brief DCMIPP HAL module driver
6 * This file provides firmware functions to manage the following
7 * functionalities of the DCMIPP (Digital Camera Interface Pixel Pipeline) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Error functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2023 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### How to use this driver #####
27 ==============================================================================
28 [..]
29 The sequence below describes how to use this driver to capture image
30 from a camera module connected to the DCMIPP Interface.
31 This sequence does not take into account the configuration of the
32 camera module, which should be made before to configure and enable
33 the DCMIPP to capture images.
34
35
36
37 Initialize the DCMIPP and the CSI through HAL_DCMIPP_Init() function.
38
39 *** Mandatory Configuration ***
40 ===================================
41 The configuration of the camera sensor interface, in Parallel or CSI (Camera Serial Interface) modes,
42 involves programming specific parameters to ensure proper functionality.
43 Below is the structured process for configuring each interface type:
44
45 (#)Parallel Mode configuration
46 To configure the camera sensor in Parallel mode, program the following parameters:
47 the Format, the VSPolarity,the HSPolarity, the PCKPolarity, the ExtendedDataMode the SynchroMode,
48 the SynchroCodes of the frame delimiter, the SwapBits and the SwapCycles
49 using HAL_DCMIPP_PARALLEL_SetConfig() function.
50
51 (#)Serial Mode configuration (CSI)
52 To configure the camera in Serial mode, use the following functions to set the corresponding parameters:
53 + The NumberOfLanes, the DataLaneMapping and the PHYBitrate using HAL_DCMIPP_CSI_SetConfig() function.
54 + The DataTypeFormat for the selected Virtual Channel HAL_DCMIPP_CSI_SetVCConfig() function or
55 the DataTypeNB, the DataTypeClass and the DataTypeFormat for the selected Virtual Channel
56 using HAL_DCMIPP_CSI_SetVCFilteringConfig() function.
57 + The DataTypeMode, the DataTypeIDA, the DataTypeIDB using HAL_DCMIPP_CSI_PIPE_SetConfig() function.
58
59 (#)Pipe configuration
60 Regardless of the interface type, the pipe configuration is necessary:
61 + To configure the Pipe , program the following parameters:
62 the FrameRate, the PixelPipePitch and PixelPackerFormat for pixel Pipes using
63 HAL_DCMIPP_PIPE_SetConfig() function.
64
65 (#)Default Shared Data Flow
66 By default, or by invoking HAL_DCMIPP_PIPE_CSI_EnableShare() ,the dataflow of PIPE1 is shared with PIPE2.
67 In this case the VC and DataType are the same as those configured for PIPE1 thus
68 data acquistion can be started for PIPE2 without any additional configuration.
69 (#)Disabling Shared Data Flow
70 The shared dataflow between Pixel Pipes can be disabled by calling HAL_DCMIPP_PIPE_CSI_DisableShare().
71 This action must be performed before starting data acquisition on either pipe
72 In this case the VC and DataType must be configured for Pipe2 separately.
73
74 *** Interrupt mode IO operation ***
75 ===================================
76
77 (##) Parallel Mode
78 (#) Configure Pipe parameters, destination (one or two) and Capture Mode (Snapshot or Continuous) and enable
79 the capture request using one from the following functions:
80 HAL_DCMIPP_PIPE_Start() or HAL_DCMIPP_PIPE_DoubleBufferStart().
81
82 Configure DCMIPP_PIPE1, destination addresses (Y and UV addresses) and Capture Mode (Snapshot or Continuous)
83 and enable the capture request for Semi-planar using one from the following functions :
84 HAL_DCMIPP_PIPE_SemiPlanarStart() or HAL_DCMIPP_PIPE_SemiPlanarDoubleBufferStart().
85
86 Configure DCMIPP_PIPE1, destination addresses (Y, U and V addresses) and Capture Mode (Snapshot or Continuous)
87 and enable the capture request for full-planar buffer using one from the following functions:
88 HAL_DCMIPP_PIPE_FullPlanarStart() or HAL_DCMIPP_PIPE_FullPlanarDoubleBufferStart().
89
90 (##) Serial Mode
91 (#) Configure Pipe parameter, Virtual Channel, destination (one or two) and Capture Mode (Snapshot or Continuous)
92 and enable the capture request using the following functions:
93 HAL_DCMIPP_CSI_PIPE_Start() or HAL_DCMIPP_CSI_PIPE_DoubleBufferStart().
94
95 Configure DCMIPP_PIPE1, Virtual Channel, destination addresses (Y and UV addresses) and Capture Mode
96 (Snapshot or Continuous) and enable the capture request for Semi-planar buffer using
97 the following functions:
98 HAL_DCMIPP_CSI_PIPE_SemiPlanarStart() or HAL_DCMIPP_CSI_PIPE_SemiPlanarDoubleBufferStart().
99
100 Configure DCMIPP_PIPE1, Virtual Channel, destination addresses (Y, U and V addresses) and Capture Mode
101 (Snapshot or Continuous) and enable the capture request for Semi-planar buffer
102 using the following functions:
103 HAL_DCMIPP_CSI_PIPE_FullPlanarStart() or HAL_DCMIPP_CSI_PIPE_FullPlanarDoubleBufferStart().
104
105 (#) Use HAL_DCMIPP_IRQHandler() called under DCMIPP_IRQHandler() interrupt subroutine.
106 (#) At the end of frame capture request HAL_DCMIPP_IRQHandler() function is executed and user can
107 add his own function by customization of function pointer PipeFrameEventCallback (member
108 of DCMIPP handle structure).
109
110 (#) Use HAL_DCMIPP_CSI_IRQHandler() called under CSI_IRQHandler() interrupt subroutine.
111 (#) At the start or the end of frame capture HAL_DCMIPP_CSI_IRQHandler() function is executed and user can
112 add his own function by customization of function pointer StartOfFrameEventCallback or EndOfFrameEventCallback.
113
114 (#) In case of common error, the HAL_DCMIPP_IRQHandler() function calls the callback
115 ErrorCallback, in case of Pipe error the HAL_DCMIPP_IRQHandler() function calls the callback PIPE_ErrorCallback
116 and in case of CSI Line error the HAL_DCMIPP_CSI_IRQHandler() function calls the callback
117 LineErrorCallback.
118
119 (#) The Pipe capture can be suspended and resumed using the following functions
120 HAL_DCMIPP_PIPE_Suspend() and HAL_DCMIPP_PIPE_Resume().
121
122 (#) For Snapshot Mode the capture can be re-enabled using the HAL_DCMIPP_PIPE_EnableCapture();
123
124 (#) Optionally, Program the required configuration through the following parameters:
125 Client, MemoryPageSize, Traffic, MaxOutstandingTransactions, DPREGStart, DPREGEnd
126 and WLRURatio using HAL_DCMIPP_SetIPPlugConfig().
127
128 (#) Optionally, configure and Enable the CROP feature to select a rectangular
129 window from the received image using HAL_DCMIPP_PIPE_SetCropConfig()
130 and HAL_DCMIPP_PIPE_EnableCrop() functions.
131
132 (#) Optionally, configure and Enable the line and bytes decimation features
133 using the following functions HAL_DCMIPP_PIPE_SetLinesDecimationConfig and
134 HAL_DCMIPP_PIPE_SetBytesDecimationConfig.
135
136 (#) Optionally, configure and enable the line event using the function HAL_DCMIPP_PIPE_EnableLineEvent().
137
138 (#) Optionally, configure and enable the Limit event using the function HAL_DCMIPP_PIPE_EnableLimitEvent().
139
140 (#) If needed, reconfigure and change the input pixel format value, the frame rate
141 value, the capture Mode , the destination memory address , the syncunmask values,
142 Multiline value and Limit value using respectively
143 the following functions: HAL_DCMIPP_PIPE_SetInputPixelFormat(), HAL_DCMIPP_PIPE_SetFrameRate(),
144 HAL_DCMIPP_PIPE_SetCaptureMode(), HAL_DCMIPP_PIPE_SetMemoryAddress(), HAL_DCMIPP_SetSyncUnmask(),
145 HAL_DCMIPP_PIPE_EnableLineEvent() and HAL_DCMIPP_PIPE_EnableLimitEvent().
146
147 (#) To read the transferred data counter , use the HAL_DCMIPP_PIPE_GetDataCounter()
148
149 (#) To read and reset the Frame counter of the pipe, use the following functions:
150 HAL_DCMIPP_PIPE_ReadFrameCounter() and HAL_DCMIPP_PIPE_ResetFrameCounter().
151
152 (#) The Pipe capture in parallel mode can be Stopped using HAL_DCMIPP_PIPE_Stop() function.
153 (#) The Pipe capture in serial mode can be Stopped using HAL_DCMIPP_CSI_PIPE_Stop() function.
154 (#) To control the DCMIPP state, use the following function: HAL_DCMIPP_GetState().
155
156 (#) To control the DCMIPP Pipe state, use the following function: HAL_DCMIPP_PIPE_GetState().
157
158 (#) To read the DCMIPP error code, use the following function: HAL_DCMIPP_GetError().
159
160 *** DCMIPP HAL driver macros list ***
161 =============================================
162 [..]
163 Below the list of most used macros in DCMIPP HAL driver :
164
165 (+) __HAL_DCMIPP_GET_FLAG: Get the DCMIPP pending flags.
166 (+) __HAL_DCMIPP_CLEAR_FLAG: Clear the DCMIPP pending flags.
167 (+) __HAL_DCMIPP_ENABLE_IT: Enable the specified DCMIPP interrupts.
168 (+) __HAL_DCMIPP_DISABLE_IT: Disable the specified DCMIPP interrupts.
169 (+) __HAL_DCMIPP_GET_IT_SOURCE: Check whether the specified DCMIPP interrupt is enabled or not.
170 (+) __HAL_DCMIPP_CSI_GET_FLAG: Get the CSI pending flags.
171 (+) __HAL_DCMIPP_CSI_CLEAR_FLAG: Clear the CSI pending flags.
172 (+) __HAL_DCMIPP_CSI_ENABLE_IT: Enable the specified CSI interrupts.
173 (+) __HAL_DCMIPP_CSI_DISABLE_IT: Disable the specified CSI interrupts.
174 (+) __HAL_DCMIPP_CSI_GET_IT_SOURCE: Check whether the specified CSI interrupt is enabled or not.
175
176 *** Callback registration ***
177 ===================================
178 [..]
179 (#) The compilation define USE_HAL_DCMIPP_REGISTER_CALLBACKS when set to 1
180 allows the user to configure dynamically the driver callbacks.
181 Use function @ref HAL_DCMIPP_RegisterCallback() to register a user callback.
182 Use function @ref HAL_DCMIPP_PIPE_RegisterCallback() to register a user pipe callback.
183
184 (#) Function @ref HAL_DCMIPP_RegisterCallback() allows to register following callbacks:
185 (+) ErrorCallback : callback for Error
186 (+) MspInitCallback : DCMIPP MspInit.
187 (+) MspDeInitCallback : DCMIPP MspDeInit.
188 This function takes as parameters the HAL peripheral handle, the Callback ID
189 and a pointer to the user callback function.
190 (#) Function @ref HAL_DCMIPP_PIPE_RegisterCallback() allows to register following callbacks:
191 (+) PIPE_FrameEventCallback : callback for Pipe Frame Event.
192 (+) PIPE_VsyncEventCallback : callback for Pipe Vsync Event.
193 (+) PIPE_LineEventCallback : callback for Pipe Line Event.
194 (+) PIPE_LimitEventCallback : callback for Pipe Limit Event.
195 (+) PIPE_ErrorCallback : callback for Pipe Error
196 This function takes as parameters the HAL peripheral handle, the Callback ID
197 and a pointer to the user callback function.
198
199 (#) Use function @ref HAL_DCMIPP_UnRegisterCallback() to reset a callback to the default
200 weak (surcharged) function.
201 @ref HAL_DCMIPP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
202 and the Callback ID.
203 This function allows to reset following callbacks:
204 (+) ErrorCallback : callback for Error
205 (+) MspInitCallback : DCMIPP MspInit.
206 (+) MspDeInitCallback : DCMIPP MspDeInit.
207 (#) Use function @ref HAL_DCMIPP_PIPE_UnRegisterCallback() to reset a pipe callback to the default
208 weak (surcharged) function.
209 @ref HAL_DCMIPP_PIPE_UnRegisterCallback() takes as parameters the HAL peripheral handle,
210 and the Callback ID.
211 This function allows to reset following callbacks:
212 (+) PIPE_FrameEventCallback : callback for Pipe Frame Event.
213 (+) PIPE_VsyncEventCallback : callback for Pipe Vsync Event.
214 (+) PIPE_LineEventCallback : callback for Pipe Line Event.
215 (+) PIPE_LimitEventCallback : callback for Pipe Limit Event.
216 (+) PIPE_ErrorCallback : callback for Pipe Error
217
218 (#) By default, after the @ref HAL_DCMIPP_Init and if the state is HAL_DCMIPP_STATE_RESET
219 all callbacks are reset to the corresponding legacy weak (surcharged) functions:
220 examples @ref PipeFrameEventCallback(), @ref PipeVsyncEventCallback()
221 Exception done for MspInit and MspDeInit callbacks that are respectively
222 reset to the legacy weak (surcharged) functions in the @ref HAL_DCMIPP_Init
223 and @ref HAL_DCMIPP_DeInit only when these callbacks are null (not registered beforehand)
224 If not, MspInit or MspDeInit are not null, the @ref HAL_DCMIPP_Init and @ref HAL_DCMIPP_DeInit
225 keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
226
227 Callbacks can be registered/unregistered in READY state only.
228 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
229 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
230 during the Init/DeInit.
231 In that case first register the MspInit/MspDeInit user callbacks
232 using @ref HAL_DCMIPP_RegisterCallback before calling @ref HAL_DCMIPP_DeInit
233 or @ref HAL_DCMIPP_Init function.
234
235 When The compilation define USE_HAL_DCMIPP_REGISTER_CALLBACKS is set to 0 or
236 not defined, the callback registering feature is not available
237 and weak (surcharged) callbacks are used.
238
239 [..]
240 (@) You can refer to the DCMIPP HAL driver header file for more useful macros
241 @endverbatim
242 ******************************************************************************
243 */
244
245 /* Includes ------------------------------------------------------------------*/
246 #include "stm32n6xx_hal.h"
247
248 #ifdef HAL_DCMIPP_MODULE_ENABLED
249 #if defined (DCMIPP)
250
251 /** @addtogroup STM32N6xx_HAL_Driver
252 * @{
253 */
254 /** @defgroup DCMIPP DCMIPP
255 * @brief DCMIPP HAL module driver
256 * @{
257 */
258
259 /* Private define ------------------------------------------------------------*/
260 /** @defgroup DCMIPP_Private_Constants DCMIPP Private Constants
261 * @{
262 */
263 #define READ_FIELD(REG, MASK) ((REG) & (MASK))
264
265 #define MATRIX_VALUE11(value) ((((value) & 0x8000U) == 0x8000U) ? ((value) & 0x07FFU) : (value))
266 #define MATRIX_VALUE10(value) ((((value) & 0x8000U) == 0x8000U) ? ((value) & 0x03FFU) : (value))
267 #define GET_MATRIX_VALUE11(value) ((((value) & 0x400U) == 0x400U) ? ((uint16_t)((value) | 0xF800U)) : (value))
268 #define GET_MATRIX_VALUE10(value) ((((value) & 0x200U) == 0x200U) ? ((uint16_t)((value) | 0xFC00U)) : (value))
269 #define DCMIPP_TIMEOUT 1000U /*!< 1s */
270 /**
271 * @}
272 */
273 /* Private typedef -----------------------------------------------------------*/
274 /** @defgroup DCMIPP_Private_TypeDef DCMIPP Private TypeDef
275 * @{
276 */
277 /*
278 * Table of hsfreqrange & osc_freq_target for the Synopsis D-PHY
279 */
280 typedef struct
281 {
282 uint32_t hsfreqrange;
283 uint32_t osc_freq_target;
284 } SNPS_FreqsTypeDef;
285 /**
286 * @}
287 */
288 /* Private macro -------------------------------------------------------------*/
289 /* Private variables ---------------------------------------------------------*/
290 /* Private function prototypes -----------------------------------------------*/
291 /** @defgroup DCMIPP_Private_Functions DCMIPP Private Functions
292 * @{
293 */
294 static void Pipe_Config(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, const DCMIPP_PipeConfTypeDef *pPipeConfig);
295 static void DCMIPP_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress, uint32_t CaptureMode);
296 static void DCMIPP_SetDBMConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress0,
297 uint32_t DstAddress1, uint32_t CaptureMode);
298 static void DCMIPP_EnableCapture(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
299 static HAL_StatusTypeDef DCMIPP_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe);
300 static void DCMIPP_CSI_WritePHYReg(CSI_TypeDef *hcsi, uint32_t reg_msb, uint32_t reg_lsb, uint32_t val);
301 static HAL_StatusTypeDef DCMIPP_CSI_SetVCConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t VirtualChannel);
302 static HAL_StatusTypeDef DCMIPP_CSI_VCStop(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel);
303 /**
304 * @}
305 */
306
307 /* Exported functions --------------------------------------------------------*/
308
309 /** @defgroup DCMIPP_Exported_Functions DCMIPP Exported Functions
310 * @{
311 */
312
313 /** @addtogroup DCMIPP_Initialization_De-Initialization_Functions DCMIPP Initialization De-Initialization Functions
314 * @brief Initialization and De-Initialization Functions
315 * @{
316 */
317
318 /**
319 * @brief Initialize the selected HAL DCMIPP handle and associate a DCMIPP peripheral instance.
320 * @param hdcmipp Pointer to DCMIPP handle
321 * @retval HAL status
322 */
HAL_DCMIPP_Init(DCMIPP_HandleTypeDef * hdcmipp)323 HAL_StatusTypeDef HAL_DCMIPP_Init(DCMIPP_HandleTypeDef *hdcmipp)
324 {
325 uint32_t pipe_index;
326
327 /* Check pointer validity */
328 if (hdcmipp == NULL)
329 {
330 return HAL_ERROR;
331 }
332
333 /* Check function parameters */
334 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
335
336 if (hdcmipp->State == HAL_DCMIPP_STATE_RESET)
337 {
338 /* Init the DCMIPP Callback settings */
339 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
340 /* Reset callback pointers to the weak predefined callbacks */
341 hdcmipp->PIPE_FrameEventCallback = HAL_DCMIPP_PIPE_FrameEventCallback;
342 hdcmipp->PIPE_VsyncEventCallback = HAL_DCMIPP_PIPE_VsyncEventCallback;
343 hdcmipp->PIPE_LineEventCallback = HAL_DCMIPP_PIPE_LineEventCallback;
344 hdcmipp->PIPE_LimitEventCallback = HAL_DCMIPP_PIPE_LimitEventCallback;
345 hdcmipp->PIPE_ErrorCallback = HAL_DCMIPP_PIPE_ErrorCallback;
346 hdcmipp->ErrorCallback = HAL_DCMIPP_ErrorCallback;
347 hdcmipp->LineErrorCallback = HAL_DCMIPP_CSI_LineErrorCallback;
348 hdcmipp->EndOfFrameEventCallback = HAL_DCMIPP_CSI_EndOfFrameEventCallback;
349 hdcmipp->TimerCounterEventCallback = HAL_DCMIPP_CSI_TimerCounterEventCallback;
350 hdcmipp->StartOfFrameEventCallback = HAL_DCMIPP_CSI_StartOfFrameEventCallback;
351 hdcmipp->LineByteEventCallback = HAL_DCMIPP_CSI_LineByteEventCallback;
352 hdcmipp->ClockChangerFifoFullEventCallback = HAL_DCMIPP_CSI_ClockChangerFifoFullEventCallback;
353 hdcmipp->ShortPacketDetectionEventCallback = HAL_DCMIPP_CSI_ShortPacketDetectionEventCallback;
354 if (hdcmipp->MspInitCallback == NULL)
355 {
356 /* Legacy weak MspInit Callback */
357 hdcmipp->MspInitCallback = HAL_DCMIPP_MspInit;
358 }
359 /* Initialize the low level hardware (MSP) */
360 hdcmipp->MspInitCallback(hdcmipp);
361 #else
362 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
363 HAL_DCMIPP_MspInit(hdcmipp);
364 #endif /* (USE_HAL_DCMIPP_REGISTER_CALLBACKS) */
365 }
366
367 /* Change the DCMIPP state */
368 hdcmipp->State = HAL_DCMIPP_STATE_BUSY;
369
370 /* Reset DCMIPP Pipe state */
371 for (pipe_index = 0U; pipe_index < DCMIPP_NUM_OF_PIPES; pipe_index++)
372 {
373 hdcmipp->PipeState[pipe_index] = HAL_DCMIPP_PIPE_STATE_RESET;
374 }
375
376 /* Update error code */
377 hdcmipp->ErrorCode = HAL_DCMIPP_ERROR_NONE;
378
379 /* Update the DCMIPP state*/
380 hdcmipp->State = HAL_DCMIPP_STATE_INIT;
381
382 return HAL_OK;
383 }
384
385 /**
386 * @brief De-initializes the DCMIPP peripheral registers to their default reset values.
387 * @param hdcmipp Pointer to DCMIPP handle
388 * @retval HAL status
389 */
HAL_DCMIPP_DeInit(DCMIPP_HandleTypeDef * hdcmipp)390 HAL_StatusTypeDef HAL_DCMIPP_DeInit(DCMIPP_HandleTypeDef *hdcmipp)
391 {
392 uint32_t pipe_index;
393 CSI_TypeDef *csi_instance;
394 csi_instance = CSI;
395
396 /* Check pointer validity */
397 if (hdcmipp == NULL)
398 {
399 return HAL_ERROR;
400 }
401
402 /* Disable the parallel Interface */
403 if ((hdcmipp->Instance->CMCR & DCMIPP_CMCR_INSEL) == DCMIPP_PARALLEL_MODE)
404 {
405 CLEAR_BIT(hdcmipp->Instance->PRCR, DCMIPP_PRCR_ENABLE);
406 }
407 else
408 {
409 CLEAR_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
410 }
411
412 /* Reset flow selection configuration register for all the available pipes */
413 hdcmipp->Instance->P0FSCR = 0;
414 hdcmipp->Instance->P1FSCR = 0;
415 hdcmipp->Instance->P2FSCR = 0;
416 /* PowerDown the D-PHY_RX lane(s) etc */
417 CLEAR_REG(csi_instance->PCR);
418
419 /* Disable the CSI */
420 CLEAR_BIT(csi_instance->CR, CSI_CR_CSIEN);
421 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
422 if (hdcmipp->MspDeInitCallback == NULL)
423 {
424 hdcmipp->MspDeInitCallback = HAL_DCMIPP_MspDeInit;
425 }
426
427 /* DeInit the low level hardware */
428 hdcmipp->MspDeInitCallback(hdcmipp);
429 #else
430 /* DeInit the low level hardware */
431 HAL_DCMIPP_MspDeInit(hdcmipp);
432 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
433
434 /* Update error code */
435 hdcmipp->ErrorCode = HAL_DCMIPP_ERROR_NONE;
436
437 /* Initialize the DCMIPP state*/
438 hdcmipp->State = HAL_DCMIPP_STATE_RESET;
439
440 /* Reset DCMIPP Pipe state */
441 for (pipe_index = 0U; pipe_index < DCMIPP_NUM_OF_PIPES; pipe_index++)
442 {
443 hdcmipp->PipeState[pipe_index] = HAL_DCMIPP_PIPE_STATE_RESET;
444 }
445
446 return HAL_OK;
447 }
448
449 /**
450 * @brief Initializes the DCMIPP MSP.
451 * @param hdcmipp Pointer to DCMIPP handle
452 * @retval None
453 */
HAL_DCMIPP_MspInit(DCMIPP_HandleTypeDef * hdcmipp)454 __weak void HAL_DCMIPP_MspInit(DCMIPP_HandleTypeDef *hdcmipp)
455 {
456 /* Prevent unused argument(s) compilation warning */
457 UNUSED(hdcmipp);
458
459 /* NOTE : This function Should not be modified, when the callback is needed,
460 the HAL_DCMIPP_MspInit could be implemented in the user file
461 */
462 }
463
464 /**
465 * @brief De-Initializes the DCMIPP MSP.
466 * @param hdcmipp Pointer to DCMIPP handle
467 * @retval None
468 */
HAL_DCMIPP_MspDeInit(DCMIPP_HandleTypeDef * hdcmipp)469 __weak void HAL_DCMIPP_MspDeInit(DCMIPP_HandleTypeDef *hdcmipp)
470 {
471 /* Prevent unused argument(s) compilation warning */
472 UNUSED(hdcmipp);
473
474 /* NOTE : This function Should not be modified, when the callback is needed,
475 the HAL_DCMIPP_MspDeInit could be implemented in the user file
476 */
477 }
478 /**
479 * @}
480 */
481
482 /** @defgroup DCMIPP_Configuration_Functions DCMIPP Configuration Functions
483 * @brief Configuration Functions
484 * @{
485 */
486 /**
487 * @brief Configure the DCMIPP Parallel Interface according to the user parameters.
488 * @param hdcmipp Pointer to DCMIPP handle
489 * @param pParallelConfig pointer to DCMIPP_ParallelConfTypeDef that contains
490 * the parallel Interface configuration information for DCMIPP.
491 * @retval HAL status
492 */
HAL_DCMIPP_PARALLEL_SetConfig(DCMIPP_HandleTypeDef * hdcmipp,const DCMIPP_ParallelConfTypeDef * pParallelConfig)493 HAL_StatusTypeDef HAL_DCMIPP_PARALLEL_SetConfig(DCMIPP_HandleTypeDef *hdcmipp,
494 const DCMIPP_ParallelConfTypeDef *pParallelConfig)
495 {
496 uint32_t prcr_reg;
497 uint32_t prescr_reg;
498
499 /* Check parameters */
500 if ((hdcmipp == NULL) || (pParallelConfig == NULL))
501 {
502 return HAL_ERROR;
503 }
504
505 /* Check function parameters */
506 assert_param(IS_DCMIPP_FORMAT(pParallelConfig->Format));
507 assert_param(IS_DCMIPP_VSPOLARITY(pParallelConfig->VSPolarity));
508 assert_param(IS_DCMIPP_HSPOLARITY(pParallelConfig->HSPolarity));
509 assert_param(IS_DCMIPP_PCKPOLARITY(pParallelConfig->PCKPolarity));
510 assert_param(IS_DCMIPP_EXTENDED_DATA_MODE(pParallelConfig->ExtendedDataMode));
511 assert_param(IS_DCMIPP_SYNC_MODE(pParallelConfig->SynchroMode));
512 assert_param(IS_DCMIPP_SWAP_BITS(pParallelConfig->SwapBits));
513 assert_param(IS_DCMIPP_SWAP_CYCLES(pParallelConfig->SwapCycles));
514
515 /* Check DCMIPP state */
516 if (hdcmipp->State != HAL_DCMIPP_STATE_INIT)
517 {
518 return HAL_ERROR;
519 }
520 else
521 {
522 /* Configures the Format, VS, HS, PCK polarity, ExtendedDataMode, SynchronisationMode, Swap Cycles and bits */
523 prcr_reg = ((pParallelConfig->Format) | \
524 (pParallelConfig->VSPolarity) | \
525 (pParallelConfig->HSPolarity) | \
526 (pParallelConfig->PCKPolarity) | \
527 (pParallelConfig->ExtendedDataMode) | \
528 (pParallelConfig->SynchroMode) | \
529 (pParallelConfig->SwapCycles) | \
530 (pParallelConfig->SwapBits));
531
532 WRITE_REG(hdcmipp->Instance->PRCR, prcr_reg);
533
534 if (pParallelConfig->SynchroMode == DCMIPP_SYNCHRO_EMBEDDED)
535 {
536 /* Set Embedded Sync codes */
537 prescr_reg = (((uint32_t)pParallelConfig->SynchroCodes.FrameEndCode << DCMIPP_PRESCR_FEC_Pos) | \
538 ((uint32_t)pParallelConfig->SynchroCodes.LineEndCode << DCMIPP_PRESCR_LEC_Pos) | \
539 ((uint32_t)pParallelConfig->SynchroCodes.FrameStartCode << DCMIPP_PRESCR_FSC_Pos) | \
540 ((uint32_t)pParallelConfig->SynchroCodes.LineStartCode << DCMIPP_PRESCR_LSC_Pos));
541
542 WRITE_REG(hdcmipp->Instance->PRESCR, prescr_reg);
543
544 /* Set Embedded Sync Unmask codes : All codes are unmasked */
545 WRITE_REG(hdcmipp->Instance->PRESUR, 0xFFFFFFFFU);
546 }
547
548 /* Enable the Synchronization error interrupt on parallel interface */
549 __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PARALLEL_SYNC_ERROR);
550
551 /* Enable Parallel interface */
552 SET_BIT(hdcmipp->Instance->PRCR, DCMIPP_PRCR_ENABLE);
553
554 /* Set Parallel Input Selection */
555 CLEAR_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
556 }
557
558 /* Update the DCMIPP state */
559 hdcmipp->State = HAL_DCMIPP_STATE_READY;
560
561 return HAL_OK;
562 }
563
564 /**
565 * @brief Configure the DCMIPP Serial Interface according to the user parameters.
566 * @param hdcmipp Pointer to DCMIPP handle
567 * @param pCSI_Config pointer to DCMIPP_CSI_ConfTypeDef that contains the Serial Interface
568 * configuration information for DCMIPP.
569 * @retval HAL status
570 */
HAL_DCMIPP_CSI_SetConfig(const DCMIPP_HandleTypeDef * hdcmipp,const DCMIPP_CSI_ConfTypeDef * pCSI_Config)571 HAL_StatusTypeDef HAL_DCMIPP_CSI_SetConfig(const DCMIPP_HandleTypeDef *hdcmipp,
572 const DCMIPP_CSI_ConfTypeDef *pCSI_Config)
573 {
574 CSI_TypeDef *csi_instance;
575 csi_instance = CSI;
576
577 const SNPS_FreqsTypeDef SNPS_Freqs[63] =
578 {
579 { 0x00U, 460U }, /* HAL_CSI_BT_80 */
580 { 0x10U, 460U }, /* HAL_CSI_BT_90 */
581 { 0x20U, 460U }, /* HAL_CSI_BT_100 */
582 { 0x30U, 460U }, /* HAL_CSI_BT_110 */
583 { 0x01U, 460U }, /* HAL_CSI_BT_120 */
584 { 0x11U, 460U }, /* HAL_CSI_BT_130 */
585 { 0x21U, 460U }, /* HAL_CSI_BT_140 */
586 { 0x31U, 460U }, /* HAL_CSI_BT_150 */
587 { 0x02U, 460U }, /* HAL_CSI_BT_160 */
588 { 0x12U, 460U }, /* HAL_CSI_BT_170 */
589 { 0x22U, 460U }, /* HAL_CSI_BT_180 */
590 { 0x32U, 460U }, /* HAL_CSI_BT_190 */
591 { 0x03U, 460U }, /* HAL_CSI_BT_205 */
592 { 0x13U, 460U }, /* HAL_CSI_BT_220 */
593 { 0x23U, 460U }, /* HAL_CSI_BT_235 */
594 { 0x33U, 460U }, /* HAL_CSI_BT_250 */
595 { 0x04U, 460U }, /* HAL_CSI_BT_275 */
596 { 0x14U, 460U }, /* HAL_CSI_BT_300 */
597 { 0x25U, 460U }, /* HAL_CSI_BT_325 */
598 { 0x35U, 460U }, /* HAL_CSI_BT_350 */
599 { 0x05U, 460U }, /* HAL_CSI_BT_400 */
600 { 0x16U, 460U }, /* HAL_CSI_BT_450 */
601 { 0x26U, 460U }, /* HAL_CSI_BT_500 */
602 { 0x37U, 460U }, /* HAL_CSI_BT_550 */
603 { 0x07U, 460U }, /* HAL_CSI_BT_600 */
604 { 0x18U, 460U }, /* HAL_CSI_BT_650 */
605 { 0x28U, 460U }, /* HAL_CSI_BT_700 */
606 { 0x39U, 460U }, /* HAL_CSI_BT_750 */
607 { 0x09U, 460U }, /* HAL_CSI_BT_800 */
608 { 0x19U, 460U }, /* HAL_CSI_BT_850 */
609 { 0x29U, 460U }, /* HAL_CSI_BT_900 */
610 { 0x3AU, 460U }, /* HAL_CSI_BT_950 */
611 { 0x0AU, 460U }, /* HAL_CSI_BT_1000 */
612 { 0x1AU, 460U }, /* HAL_CSI_BT_1050 */
613 { 0x2AU, 460U }, /* HAL_CSI_BT_1100 */
614 { 0x3BU, 460U }, /* HAL_CSI_BT_1150 */
615 { 0x0BU, 460U }, /* HAL_CSI_BT_1200 */
616 { 0x1BU, 460U }, /* HAL_CSI_BT_1250 */
617 { 0x2BU, 460U }, /* HAL_CSI_BT_1300 */
618 { 0x3CU, 460U }, /* HAL_CSI_BT_1350 */
619 { 0x0CU, 460U }, /* HAL_CSI_BT_1400 */
620 { 0x1CU, 460U }, /* HAL_CSI_BT_1450 */
621 { 0x2CU, 460U }, /* HAL_CSI_BT_1500 */
622 { 0x3DU, 285U }, /* HAL_CSI_BT_1550 */
623 { 0x0DU, 295U }, /* HAL_CSI_BT_1600 */
624 { 0x1DU, 304U }, /* HAL_CSI_BT_1650 */
625 { 0x2EU, 313U }, /* HAL_CSI_BT_1700 */
626 { 0x3EU, 322U }, /* HAL_CSI_BT_1750 */
627 { 0x0EU, 331U }, /* HAL_CSI_BT_1800 */
628 { 0x1EU, 341U }, /* HAL_CSI_BT_1850 */
629 { 0x2FU, 350U }, /* HAL_CSI_BT_1900 */
630 { 0x3FU, 359U }, /* HAL_CSI_BT_1950 */
631 { 0x0FU, 368U }, /* HAL_CSI_BT_2000 */
632 { 0x40U, 377U }, /* HAL_CSI_BT_2050 */
633 { 0x41U, 387U }, /* HAL_CSI_BT_2100 */
634 { 0x42U, 396U }, /* HAL_CSI_BT_2150 */
635 { 0x43U, 405U }, /* HAL_CSI_BT_2200 */
636 { 0x44U, 414U }, /* HAL_CSI_BT_2250 */
637 { 0x45U, 423U }, /* HAL_CSI_BT_2300 */
638 { 0x46U, 432U }, /* HAL_CSI_BT_2350 */
639 { 0x47U, 442U }, /* HAL_CSI_BT_2400 */
640 { 0x48U, 451U }, /* HAL_CSI_BT_2450 */
641 { 0x49U, 460U }, /* HAL_CSI_BT_2500 */
642 };
643
644 /* Check parameters */
645 if ((hdcmipp == NULL) || (pCSI_Config == NULL))
646 {
647 return HAL_ERROR;
648 }
649
650 /* Check the parameters */
651 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
652 assert_param(IS_DCMIPP_NUMBER_OF_LANES(pCSI_Config->NumberOfLanes));
653 assert_param(IS_DCMIPP_CSI_DATA_LANE_MAPPING(pCSI_Config->DataLaneMapping));
654 assert_param(IS_DCMIPP_CSI_DATA_PHY_BITRATE(pCSI_Config->PHYBitrate));
655
656 /* Ensure the CSI is disabled */
657 CLEAR_BIT(csi_instance->CR, CSI_CR_CSIEN);
658
659 /* Configure the Lane Merger */
660 if (pCSI_Config->DataLaneMapping == DCMIPP_CSI_PHYSICAL_DATA_LANES)
661 {
662 WRITE_REG(csi_instance->LMCFGR, pCSI_Config->NumberOfLanes | (DCMIPP_CSI_DATA_LANE0 << CSI_LMCFGR_DL0MAP_Pos) | \
663 (DCMIPP_CSI_DATA_LANE1 << CSI_LMCFGR_DL1MAP_Pos));
664 }
665 else if (pCSI_Config->DataLaneMapping == DCMIPP_CSI_INVERTED_DATA_LANES)
666 {
667 WRITE_REG(csi_instance->LMCFGR, pCSI_Config->NumberOfLanes | (DCMIPP_CSI_DATA_LANE1 << CSI_LMCFGR_DL0MAP_Pos) | \
668 (DCMIPP_CSI_DATA_LANE0 << CSI_LMCFGR_DL1MAP_Pos));
669 }
670 else
671 {
672 return HAL_ERROR;
673 }
674
675 /* Enable the CSI */
676 SET_BIT(csi_instance->CR, CSI_CR_CSIEN);
677
678 /* Enable some interrupts, not related to virtual channels - all error cases */
679 __HAL_DCMIPP_CSI_ENABLE_IT(csi_instance, DCMIPP_CSI_IT_CCFIFO | DCMIPP_CSI_IT_SYNCERR | \
680 DCMIPP_CSI_IT_SPKTERR | DCMIPP_CSI_IT_IDERR | \
681 DCMIPP_CSI_IT_SPKT);
682
683 /* Enable D-PHY Interrupts */
684 if (pCSI_Config->NumberOfLanes == DCMIPP_CSI_ONE_DATA_LANE)
685 {
686 if (pCSI_Config->DataLaneMapping == DCMIPP_CSI_PHYSICAL_DATA_LANES)
687 {
688 __HAL_DCMIPP_CSI_DPHY_ENABLE_IT(csi_instance, DCMIPP_CSI_IT_ESOTDL0 | DCMIPP_CSI_IT_ESOTSYNCDL0 |
689 DCMIPP_CSI_IT_EESCDL0 | DCMIPP_CSI_IT_ESYNCESCDL0 |
690 DCMIPP_CSI_IT_ECTRLDL0);
691 }
692 else
693 {
694 __HAL_DCMIPP_CSI_DPHY_ENABLE_IT(csi_instance, DCMIPP_CSI_IT_ESOTDL1 | DCMIPP_CSI_IT_ESOTSYNCDL1 |
695 DCMIPP_CSI_IT_EESCDL1 | DCMIPP_CSI_IT_ESYNCESCDL1 |
696 DCMIPP_CSI_IT_ECTRLDL1);
697 }
698 }
699 else
700 {
701 __HAL_DCMIPP_CSI_DPHY_ENABLE_IT(csi_instance, DCMIPP_CSI_IT_ESOTDL1 | DCMIPP_CSI_IT_ESOTSYNCDL1 |
702 DCMIPP_CSI_IT_EESCDL1 | DCMIPP_CSI_IT_ESYNCESCDL1 |
703 DCMIPP_CSI_IT_ECTRLDL1 |
704 DCMIPP_CSI_IT_ESOTDL0 | DCMIPP_CSI_IT_ESOTSYNCDL0 |
705 DCMIPP_CSI_IT_EESCDL0 | DCMIPP_CSI_IT_ESYNCESCDL0 |
706 DCMIPP_CSI_IT_ECTRLDL0);
707 }
708
709 /* Start D-PHY Configuration */
710 /* Stop the D-PHY */
711 CLEAR_BIT(csi_instance->PRCR, CSI_PRCR_PEN);
712
713 /* Get the D-PHY enabledb but with all lanes disabled */
714 CLEAR_REG(csi_instance-> PCR);
715
716 /* Set the testclk (clock enable) on during 15ns */
717 SET_BIT(csi_instance->PTCR0, CSI_PTCR0_TCKEN);
718
719 HAL_Delay(1);
720
721 CLEAR_REG(csi_instance->PTCR0);
722
723 /* Set hsfreqrange */
724 MODIFY_REG(csi_instance->PFCR, CSI_PFCR_HSFR, (0x28U << CSI_PFCR_CCFR_Pos) |
725 (SNPS_Freqs[pCSI_Config->PHYBitrate].hsfreqrange << CSI_PFCR_HSFR_Pos));
726
727 /* set reg @08 deskew_polarity_rw 1'b1 */
728 DCMIPP_CSI_WritePHYReg(csi_instance, 0x00, 0x08, 0x38);
729
730 /* set reg @0xE4 counter_for_des_en_config_if_rx 0x10 + DLL prog EN */
731 /* This is because 13<= cfgclkfreqrange[5:0]<=38 */
732 DCMIPP_CSI_WritePHYReg(csi_instance, 0x00, 0xe4, 0x11);
733
734 /* set reg @0xe3 & reg @0xe2 value DLL target oscilation freq */
735 /* Based on the table page 77, osc_freq_target */
736 DCMIPP_CSI_WritePHYReg(csi_instance, 0x00, 0xe3, SNPS_Freqs[pCSI_Config->PHYBitrate].osc_freq_target >> 8);
737 DCMIPP_CSI_WritePHYReg(csi_instance, 0x00, 0xe3, SNPS_Freqs[pCSI_Config->PHYBitrate].osc_freq_target & 0xFFU);
738
739 /* set basedir_0 to RX DLD 0 RX, 1 TX. Synopsys 1 RX 0 TX + freq range */
740 WRITE_REG(csi_instance-> PFCR, (0x28U << CSI_PFCR_CCFR_Pos) |
741 (SNPS_Freqs[pCSI_Config->PHYBitrate].hsfreqrange << CSI_PFCR_HSFR_Pos) | CSI_PFCR_DLD);
742
743 /* Enable the D-PHY_RX lane(s) etc */
744 if (pCSI_Config->NumberOfLanes == DCMIPP_CSI_ONE_DATA_LANE)
745 {
746 WRITE_REG(csi_instance->PCR, CSI_PCR_DL0EN | CSI_PCR_CLEN | CSI_PCR_PWRDOWN);
747 }
748 else
749 {
750 WRITE_REG(csi_instance->PCR, CSI_PCR_DL0EN | CSI_PCR_DL1EN | CSI_PCR_CLEN | CSI_PCR_PWRDOWN);
751 }
752
753
754 /* Enable PHY, out of reset */
755 SET_BIT(csi_instance->PRCR, CSI_PRCR_PEN);
756
757 /* Remove the force */
758 CLEAR_REG(csi_instance->PMCR);
759
760 return HAL_OK;
761
762 }
763 /**
764 * @brief Configure the DCMIPP Pipe according to the user parameters.
765 * @param hdcmipp Pointer to DCMIPP handle
766 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
767 * @param pCSI_PipeConfig pointer to DCMIPP_CSI_PIPE_ConfTypeDef that contains
768 * the CSI Pipe configuration information for DCMIPP.
769 * @retval HAL status
770 */
HAL_DCMIPP_CSI_PIPE_SetConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_CSI_PIPE_ConfTypeDef * pCSI_PipeConfig)771 HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
772 const DCMIPP_CSI_PIPE_ConfTypeDef *pCSI_PipeConfig)
773 {
774 uint32_t pxfscr_reg = 0;
775 HAL_DCMIPP_StateTypeDef state;
776
777 /* Check the DCMIPP peripheral handle parameter and pCSI_Config parameter */
778 if ((hdcmipp == NULL) || (pCSI_PipeConfig == NULL))
779 {
780 return HAL_ERROR;
781 }
782
783 /* Check the parameters */
784 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
785 assert_param(IS_DCMIPP_PIPE(Pipe));
786 assert_param(IS_DCMIPP_DATA_TYPE_MODE(pCSI_PipeConfig->DataTypeMode));
787
788 if (Pipe != DCMIPP_PIPE2)
789 {
790 assert_param(IS_DCMIPP_DATA_TYPE_MODE(pCSI_PipeConfig->DataTypeMode));
791
792 if ((pCSI_PipeConfig->DataTypeMode == DCMIPP_DTMODE_DTIDA_OR_DTIDB)
793 || (pCSI_PipeConfig->DataTypeMode == DCMIPP_DTMODE_ALL_EXCEPT_DTIA_DTIB))
794 {
795 assert_param(IS_DCMIPP_DATA_TYPE(pCSI_PipeConfig->DataTypeIDB));
796 }
797 }
798
799 if (pCSI_PipeConfig->DataTypeMode != DCMIPP_DTMODE_ALL)
800 {
801 assert_param(IS_DCMIPP_DATA_TYPE(pCSI_PipeConfig->DataTypeIDA));
802 }
803
804 state = hdcmipp->State;
805 if ((state == HAL_DCMIPP_STATE_INIT) || (state == HAL_DCMIPP_STATE_READY))
806 {
807 if (((pCSI_PipeConfig->DataTypeMode == DCMIPP_DTMODE_ALL) || \
808 (pCSI_PipeConfig->DataTypeMode == DCMIPP_DTMODE_ALL_EXCEPT_DTIA_DTIB)) && (Pipe != DCMIPP_PIPE0))
809 {
810 return HAL_ERROR;
811 }
812
813 /* Add Data Type Mode for the selected Pipe except Pipe2 */
814 if (Pipe != DCMIPP_PIPE2)
815 {
816 pxfscr_reg |= (uint32_t)(pCSI_PipeConfig->DataTypeMode);
817 }
818
819 if (pCSI_PipeConfig->DataTypeMode != DCMIPP_DTMODE_ALL)
820 {
821 /* Add Data Type IDA for the selected Pipe */
822 pxfscr_reg |= (uint32_t)(pCSI_PipeConfig->DataTypeIDA << DCMIPP_P0FSCR_DTIDA_Pos);
823 }
824
825 if ((pCSI_PipeConfig->DataTypeMode == DCMIPP_DTMODE_DTIDA_OR_DTIDB)
826 || (pCSI_PipeConfig->DataTypeMode == DCMIPP_DTMODE_ALL_EXCEPT_DTIA_DTIB))
827 {
828 if (Pipe != DCMIPP_PIPE2)
829 {
830 /* Add Data Type IDB for the selected Pipe except Pipe2 */
831 pxfscr_reg |= (uint32_t)(pCSI_PipeConfig->DataTypeIDB << DCMIPP_P0FSCR_DTIDB_Pos);
832 }
833 }
834
835 if (Pipe == DCMIPP_PIPE0)
836 {
837 MODIFY_REG(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_DTMODE | DCMIPP_P0FSCR_DTIDA |
838 DCMIPP_P0FSCR_DTIDB, pxfscr_reg);
839 }
840 else if (Pipe == DCMIPP_PIPE1)
841 {
842 MODIFY_REG(hdcmipp->Instance->P1FSCR, (DCMIPP_P1FSCR_DTIDA | DCMIPP_P1FSCR_DTIDB |
843 DCMIPP_P1FSCR_DTMODE), pxfscr_reg);
844 }
845 else
846 {
847 MODIFY_REG(hdcmipp->Instance->P2FSCR, DCMIPP_P2FSCR_DTIDA, pxfscr_reg);
848 }
849
850 /* Disable Parallel interface */
851 CLEAR_BIT(hdcmipp->Instance->PRCR, DCMIPP_PRCR_ENABLE);
852
853 /* Set CSI Input Selection */
854 SET_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
855 }
856
857 /* Update the DCMIPP state */
858 hdcmipp->State = HAL_DCMIPP_STATE_READY;
859
860 return HAL_OK;
861 }
862
863 /**
864 * @brief Configure the DCMIPP Virtual Channel according to the user parameters.
865 * @param hdcmipp Pointer to DCMIPP handle
866 * @param VirtualChannel Specifies the virtual channel, can be a value @ref DCMIPP_Virtual_Channel
867 * @param pVCFilteringConfig pointer to DCMIPP_CSI_VCFilteringConfTypeDef that contains
868 * the Virtual Channel Filtering configuration information.
869 * @retval HAL status
870 */
HAL_DCMIPP_CSI_SetVCFilteringConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t VirtualChannel,const DCMIPP_CSI_VCFilteringConfTypeDef * pVCFilteringConfig)871 HAL_StatusTypeDef HAL_DCMIPP_CSI_SetVCFilteringConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel,
872 const DCMIPP_CSI_VCFilteringConfTypeDef *pVCFilteringConfig)
873 {
874 CSI_TypeDef *csi_instance;
875 csi_instance = CSI;
876 uint32_t cfgr1 = 0;
877 uint32_t cfgr2 = 0;
878 uint32_t cfgr3 = 0;
879 uint32_t cfgr4 = 0;
880 uint32_t i;
881 struct dt_cfg
882 {
883 uint32_t *reg;
884 uint32_t offset;
885 } DTCFG[MAX_DATATYPE_NB] =
886 {
887 { &cfgr1, 16 }, /* DT0 */
888 { &cfgr2, 0 }, /* DT1 */
889 { &cfgr2, 16 }, /* DT2 */
890 { &cfgr3, 0 }, /* DT3 */
891 { &cfgr3, 16 }, /* DT4 */
892 { &cfgr4, 0 }, /* DT5 */
893 { &cfgr4, 16 }, /* DT6 */
894 };
895
896 /* Check pointer and input values validity */
897 if ((hdcmipp == NULL) || (pVCFilteringConfig == NULL))
898 {
899 return HAL_ERROR;
900 }
901
902 assert_param(IS_DCMIPP_CSI_DATA_TYPE_NB(pVCFilteringConfig->DataTypeNB));
903
904 for (i = 0; i < pVCFilteringConfig->DataTypeNB; i++)
905 {
906 assert_param(IS_DCMIPP_CSI_DATA_TYPE_FORMAT(pVCFilteringConfig->DataTypeFormat[i]));
907 assert_param(IS_DCMIPP_CSI_DATA_CLASS(pVCFilteringConfig->DataTypeClass[i]));
908
909 *(DTCFG[i].reg) |= (((pVCFilteringConfig->DataTypeClass[i]) << (DTCFG[i].offset)) | \
910 (pVCFilteringConfig->DataTypeFormat[i] << (DTCFG[i].offset + 8U)));
911 cfgr1 |= ((uint32_t)1U << (CSI_VC0CFGR1_DT0EN_Pos + i));
912 }
913
914 switch (VirtualChannel)
915 {
916 case DCMIPP_VIRTUAL_CHANNEL0:
917 {
918 WRITE_REG(csi_instance->VC0CFGR1, cfgr1);
919 WRITE_REG(csi_instance->VC0CFGR2, cfgr2);
920 WRITE_REG(csi_instance->VC0CFGR3, cfgr3);
921 WRITE_REG(csi_instance->VC0CFGR4, cfgr4);
922 break;
923 }
924 case DCMIPP_VIRTUAL_CHANNEL1:
925 {
926 WRITE_REG(csi_instance->VC1CFGR1, cfgr1);
927 WRITE_REG(csi_instance->VC1CFGR2, cfgr2);
928 WRITE_REG(csi_instance->VC1CFGR3, cfgr3);
929 WRITE_REG(csi_instance->VC1CFGR4, cfgr4);
930 break;
931 }
932 case DCMIPP_VIRTUAL_CHANNEL2:
933 {
934 WRITE_REG(csi_instance->VC2CFGR1, cfgr1);
935 WRITE_REG(csi_instance->VC2CFGR2, cfgr2);
936 WRITE_REG(csi_instance->VC2CFGR3, cfgr3);
937 WRITE_REG(csi_instance->VC2CFGR4, cfgr4);
938 break;
939 }
940 case DCMIPP_VIRTUAL_CHANNEL3:
941 {
942 WRITE_REG(csi_instance->VC3CFGR1, cfgr1);
943 WRITE_REG(csi_instance->VC3CFGR2, cfgr2);
944 WRITE_REG(csi_instance->VC3CFGR3, cfgr3);
945 WRITE_REG(csi_instance->VC3CFGR4, cfgr4);
946 break;
947 }
948 default:
949 break;
950 }
951
952 return HAL_OK;
953 }
954
955 /**
956 * @brief Configure the DCMIPP Virtual Channel with the selected Data Type format.
957 * @param hdcmipp Pointer to DCMIPP handle
958 * @param VirtualChannel Specifies the virtual channel, can be a value from @ref DCMIPP_Virtual_Channel
959 * @param DataTypeFormat Specifies the Data Type Format, can be a value from @ref DCMIPP_CSI_DataTypeFormat.
960 * @retval HAL status
961 */
HAL_DCMIPP_CSI_SetVCConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t VirtualChannel,uint32_t DataTypeFormat)962 HAL_StatusTypeDef HAL_DCMIPP_CSI_SetVCConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel,
963 uint32_t DataTypeFormat)
964 {
965 CSI_TypeDef *csi_instance;
966 csi_instance = CSI;
967
968 assert_param(IS_DCMIPP_VCID(VirtualChannel));
969 assert_param(IS_DCMIPP_CSI_DATA_TYPE_FORMAT(DataTypeFormat));
970
971 /* Check pointer and input values validity */
972 if (hdcmipp == NULL)
973 {
974 return HAL_ERROR;
975 }
976
977 /* Set the common format for all data type for the selected virtual channel */
978 switch (VirtualChannel)
979 {
980 case DCMIPP_VIRTUAL_CHANNEL0:
981 {
982 WRITE_REG(csi_instance->VC0CFGR1, (DataTypeFormat << CSI_VC0CFGR1_CDTFT_Pos) | CSI_VC0CFGR1_ALLDT);
983 break;
984 }
985 case DCMIPP_VIRTUAL_CHANNEL1:
986 {
987 WRITE_REG(csi_instance->VC1CFGR1, (DataTypeFormat << CSI_VC1CFGR1_CDTFT_Pos) | CSI_VC1CFGR1_ALLDT);
988 break;
989 }
990 case DCMIPP_VIRTUAL_CHANNEL2:
991 {
992 WRITE_REG(csi_instance->VC2CFGR1, (DataTypeFormat << CSI_VC2CFGR1_CDTFT_Pos) | CSI_VC2CFGR1_ALLDT);
993 break;
994 }
995 case DCMIPP_VIRTUAL_CHANNEL3:
996 {
997 WRITE_REG(csi_instance->VC3CFGR1, (DataTypeFormat << CSI_VC3CFGR1_CDTFT_Pos) | CSI_VC3CFGR1_ALLDT);
998 break;
999 }
1000 default:
1001 break;
1002 }
1003
1004 return HAL_OK;
1005 }
1006
1007 /**
1008 * @brief Configure the pipe according to the user parameters.
1009 * @param hdcmipp Pointer to DCMIPP handle
1010 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1011 * @param pPipeConfig pointer to pipe configuration structure
1012 * @retval HAL status
1013 */
HAL_DCMIPP_PIPE_SetConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_PipeConfTypeDef * pPipeConfig)1014 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
1015 const DCMIPP_PipeConfTypeDef *pPipeConfig)
1016 {
1017 HAL_DCMIPP_PipeStateTypeDef pipe_state;
1018
1019 /* Check the DCMIPP peripheral handle parameter and pPipeConfig parameter */
1020 if ((hdcmipp == NULL) || (pPipeConfig == NULL))
1021 {
1022 return HAL_ERROR;
1023 }
1024
1025 /* Check the parameters */
1026 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
1027 assert_param(IS_DCMIPP_PIPE(Pipe));
1028 assert_param(IS_DCMIPP_FRAME_RATE(pPipeConfig->FrameRate));
1029 if (Pipe != DCMIPP_PIPE0)
1030 {
1031 assert_param(IS_DCMIPP_PIXEL_PACKER_FORMAT(pPipeConfig->PixelPackerFormat));
1032 assert_param(IS_DCMIPP_PIXEL_PIPE_PITCH(pPipeConfig->PixelPipePitch));
1033 }
1034
1035 if ((Pipe == DCMIPP_PIPE2) && ((pPipeConfig->PixelPackerFormat) > DCMIPP_PIXEL_PACKER_FORMAT_YUV422_1))
1036 {
1037 return HAL_ERROR;
1038 }
1039 /* Get Pipe State */
1040 pipe_state = hdcmipp->PipeState[Pipe];
1041
1042 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
1043 {
1044 if ((pipe_state == HAL_DCMIPP_PIPE_STATE_RESET) || (pipe_state == HAL_DCMIPP_PIPE_STATE_ERROR))
1045 {
1046 /* Update the DCMIPP PIPE state */
1047 hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
1048
1049 /* Initialize the DCMIPP Pipe registers */
1050 Pipe_Config(hdcmipp, Pipe, pPipeConfig);
1051
1052 /* Update the DCMIPP pipe state */
1053 hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_READY;
1054 }
1055 else
1056 {
1057 return HAL_ERROR;
1058 }
1059 }
1060 else
1061 {
1062 return HAL_ERROR;
1063 }
1064
1065 return HAL_OK;
1066 }
1067
1068 /**
1069 * @brief Configure the DCMIPP AXI master memory IP-Plug.
1070 * @param hdcmipp Pointer to DCMIPP handle
1071 * @param pIPPlugConfig pointer to IPPLUG configuration structure
1072 * @retval HAL status
1073 */
HAL_DCMIPP_SetIPPlugConfig(DCMIPP_HandleTypeDef * hdcmipp,const DCMIPP_IPPlugConfTypeDef * pIPPlugConfig)1074 HAL_StatusTypeDef HAL_DCMIPP_SetIPPlugConfig(DCMIPP_HandleTypeDef *hdcmipp,
1075 const DCMIPP_IPPlugConfTypeDef *pIPPlugConfig)
1076 {
1077 uint32_t tickstart;
1078
1079 /* Check handle validity */
1080 if ((hdcmipp == NULL) || (pIPPlugConfig == NULL))
1081 {
1082 return HAL_ERROR;
1083 }
1084
1085 /* Check the parameters */
1086 assert_param(IS_DCMIPP_CLIENT(pIPPlugConfig->Client));
1087 assert_param(IS_DCMIPP_DPREG_END(pIPPlugConfig->DPREGEnd));
1088 assert_param(IS_DCMIPP_DPREG_START(pIPPlugConfig->DPREGStart));
1089 assert_param(IS_DCMIPP_MAX_OUTSTANDING_TRANSACTIONS(pIPPlugConfig->MaxOutstandingTransactions));
1090 assert_param(IS_DCMIPP_MEMORY_PAGE_SIZE(pIPPlugConfig->MemoryPageSize));
1091 assert_param(IS_DCMIPP_TRAFFIC(pIPPlugConfig->Traffic));
1092 assert_param(IS_DCMIPP_WLRU_RATIO(pIPPlugConfig->WLRURatio));
1093
1094
1095 if (hdcmipp->State != HAL_DCMIPP_STATE_RESET)
1096 {
1097 /* Request to lock the IP-Plug, to allow reconfiguration */
1098 SET_BIT(hdcmipp->Instance->IPGR2, DCMIPP_IPGR2_PSTART);
1099
1100 tickstart = HAL_GetTick();
1101 do
1102 {
1103 if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
1104 {
1105 return HAL_ERROR;
1106 }
1107 } while ((hdcmipp->Instance->IPGR3 & DCMIPP_IPGR3_IDLE) != DCMIPP_IPGR3_IDLE);
1108 }
1109 else
1110 {
1111 return HAL_ERROR;
1112 }
1113
1114 /* IP-Plug is currently locked and can be reconfigured */
1115
1116 /* Set Memory page size */
1117 hdcmipp->Instance->IPGR1 = (pIPPlugConfig->MemoryPageSize);
1118
1119 /* IP-PLUG Client1 configuration */
1120 switch (pIPPlugConfig->Client)
1121 {
1122 case DCMIPP_CLIENT1:
1123 {
1124 /* Set Traffic : Burst size and Maximum Outstanding transactions */
1125 hdcmipp->Instance->IPC1R1 = (pIPPlugConfig->Traffic |
1126 (pIPPlugConfig->MaxOutstandingTransactions << DCMIPP_IPC1R1_OTR_Pos));
1127
1128 /* Set Ratio arbitration */
1129 hdcmipp->Instance->IPC1R2 = (pIPPlugConfig->WLRURatio << DCMIPP_IPC1R2_WLRU_Pos);
1130
1131 /* Set End word and Start Word of the FIFO of the Clientx */
1132 hdcmipp->Instance->IPC1R3 = ((pIPPlugConfig->DPREGStart << DCMIPP_IPC1R3_DPREGSTART_Pos) |
1133 (pIPPlugConfig->DPREGEnd << DCMIPP_IPC1R3_DPREGEND_Pos));
1134 break;
1135 }
1136 case DCMIPP_CLIENT2:
1137 {
1138 /* Set Traffic : Burst size and Maximum Outstanding transactions */
1139 hdcmipp->Instance->IPC2R1 = (pIPPlugConfig->Traffic |
1140 (pIPPlugConfig->MaxOutstandingTransactions << DCMIPP_IPC2R1_OTR_Pos));
1141
1142 /* Set Ratio arbitration */
1143 hdcmipp->Instance->IPC2R2 = (pIPPlugConfig->WLRURatio << DCMIPP_IPC2R2_WLRU_Pos);
1144
1145 /* Set End word and Start Word of the FIFO of the Clientx */
1146 hdcmipp->Instance->IPC2R3 = ((pIPPlugConfig->DPREGStart << DCMIPP_IPC2R3_DPREGSTART_Pos) |
1147 (pIPPlugConfig->DPREGEnd << DCMIPP_IPC2R3_DPREGEND_Pos));
1148 break;
1149 }
1150 case DCMIPP_CLIENT3:
1151 {
1152 /* Set Traffic : Burst size and Maximum Outstanding transactions */
1153 hdcmipp->Instance->IPC3R1 = (pIPPlugConfig->Traffic |
1154 (pIPPlugConfig->MaxOutstandingTransactions << DCMIPP_IPC3R1_OTR_Pos));
1155
1156 /* Set Ratio arbitration */
1157 hdcmipp->Instance->IPC3R2 = (pIPPlugConfig->WLRURatio << DCMIPP_IPC3R2_WLRU_Pos);
1158
1159 /* Set End word and Start Word of the FIFO of the Clientx */
1160 hdcmipp->Instance->IPC3R3 = ((pIPPlugConfig->DPREGStart << DCMIPP_IPC3R3_DPREGSTART_Pos) |
1161 (pIPPlugConfig->DPREGEnd << DCMIPP_IPC3R3_DPREGEND_Pos));
1162 break;
1163 }
1164 case DCMIPP_CLIENT4:
1165 {
1166 /* Set Traffic : Burst size and Maximum Outstanding transactions */
1167 hdcmipp->Instance->IPC4R1 = (pIPPlugConfig->Traffic |
1168 (pIPPlugConfig->MaxOutstandingTransactions << DCMIPP_IPC4R1_OTR_Pos));
1169
1170 /* Set Ratio arbitration */
1171 hdcmipp->Instance->IPC4R2 = (pIPPlugConfig->WLRURatio << DCMIPP_IPC4R2_WLRU_Pos);
1172
1173 /* Set End word and Start Word of the FIFO of the Clientx */
1174 hdcmipp->Instance->IPC4R3 = ((pIPPlugConfig->DPREGStart << DCMIPP_IPC4R3_DPREGSTART_Pos) |
1175 (pIPPlugConfig->DPREGEnd << DCMIPP_IPC4R3_DPREGEND_Pos));
1176 break;
1177 }
1178 case DCMIPP_CLIENT5:
1179 {
1180 /* Set Traffic : Burst size and Maximum Outstanding transactions */
1181 hdcmipp->Instance->IPC5R1 = (pIPPlugConfig->Traffic |
1182 (pIPPlugConfig->MaxOutstandingTransactions << DCMIPP_IPC5R1_OTR_Pos));
1183
1184 /* Set Ratio arbitration */
1185 hdcmipp->Instance->IPC5R2 = (pIPPlugConfig->WLRURatio << DCMIPP_IPC5R2_WLRU_Pos);
1186
1187 /* Set End word and Start Word of the FIFO of the Clientx */
1188 hdcmipp->Instance->IPC5R3 = ((pIPPlugConfig->DPREGStart << DCMIPP_IPC5R3_DPREGSTART_Pos) |
1189 (pIPPlugConfig->DPREGEnd << DCMIPP_IPC5R3_DPREGEND_Pos));
1190 break;
1191 }
1192 default:
1193 break;
1194 }
1195
1196 /* No lock requested, IP-Plug runs on demand by background HW */
1197 CLEAR_BIT(hdcmipp->Instance->IPGR2, DCMIPP_IPGR2_PSTART);
1198
1199 /* Enable DCMIPP_IT_AXI_TRANSFER_ERR */
1200 __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_AXI_TRANSFER_ERROR);
1201
1202 return HAL_OK;
1203 }
1204
1205 /**
1206 * @}
1207 */
1208
1209 /** @addtogroup DCMIPP_IO_operation_Functions DCMIPP IO operation Functions
1210 * @brief IO operation functions
1211 * @{
1212 */
1213 /**
1214 * @brief Start the DCMIPP capture on the specified pipe
1215 * @param hdcmipp Pointer to DCMIPP handle
1216 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1217 * @param DstAddress the destination address
1218 * @param CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
1219 * @retval HAL status
1220 */
HAL_DCMIPP_PIPE_Start(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t DstAddress,uint32_t CaptureMode)1221 HAL_StatusTypeDef HAL_DCMIPP_PIPE_Start(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress,
1222 uint32_t CaptureMode)
1223 {
1224 uint32_t mode;
1225 assert_param(IS_DCMIPP_PIPE(Pipe));
1226 assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
1227
1228 /* Check pointer validity */
1229 if ((hdcmipp == NULL) || ((DstAddress & 0xFU) != 0U))
1230 {
1231 return HAL_ERROR;
1232 }
1233
1234 mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
1235 if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_PARALLEL_MODE))
1236 {
1237 return HAL_ERROR;
1238 }
1239
1240 /* Set Capture Mode and Destination address for the selected pipe */
1241 DCMIPP_SetConfig(hdcmipp, Pipe, DstAddress, CaptureMode);
1242
1243 /* Enable Capture for the selected Pipe */
1244 DCMIPP_EnableCapture(hdcmipp, Pipe);
1245
1246 return HAL_OK;
1247 }
1248
1249 /**
1250 * @brief Start the DCMIPP capture on the specified pipe with double buffering Mode
1251 * @param hdcmipp Pointer to DCMIPP handle
1252 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1253 * @param DstAddress0 the first destination address
1254 * @param DstAddress1 the second destination address
1255 * @param CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
1256 * @retval HAL status
1257 */
HAL_DCMIPP_PIPE_DoubleBufferStart(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t DstAddress0,uint32_t DstAddress1,uint32_t CaptureMode)1258 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress0,
1259 uint32_t DstAddress1, uint32_t CaptureMode)
1260 {
1261 uint32_t mode;
1262 assert_param(IS_DCMIPP_PIPE(Pipe));
1263 assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
1264
1265 /* Check pointer validity */
1266 if ((hdcmipp == NULL) || ((DstAddress0 & 0xFU) != 0U) || ((DstAddress1 & 0xFU) != 0U))
1267 {
1268 return HAL_ERROR;
1269 }
1270
1271 mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
1272 if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_PARALLEL_MODE))
1273 {
1274 return HAL_ERROR;
1275 }
1276
1277 /* Set Capture Mode and Destination addresses for the selected pipe */
1278 DCMIPP_SetDBMConfig(hdcmipp, Pipe, DstAddress0, DstAddress1, CaptureMode);
1279
1280 /* Enable Capture for the selected Pipe */
1281 DCMIPP_EnableCapture(hdcmipp, Pipe);
1282
1283 return HAL_OK;
1284 }
1285
1286 /**
1287 * @brief Stop DCMIPP capture on the specified pipe
1288 * @param hdcmipp Pointer to DCMIPP handle
1289 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1290 * @retval HAL status
1291 */
HAL_DCMIPP_PIPE_Stop(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)1292 HAL_StatusTypeDef HAL_DCMIPP_PIPE_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
1293 {
1294 HAL_DCMIPP_PipeStateTypeDef pipe_state;
1295
1296 assert_param(IS_DCMIPP_PIPE(Pipe));
1297
1298 /* Check pointer validity */
1299 if (hdcmipp == NULL)
1300 {
1301 return HAL_ERROR;
1302 }
1303
1304 if ((hdcmipp->Instance->CMCR & DCMIPP_CMCR_INSEL) != DCMIPP_PARALLEL_MODE)
1305 {
1306 return HAL_ERROR;
1307 }
1308
1309 /* Get Pipe State */
1310 pipe_state = hdcmipp->PipeState[Pipe];
1311
1312 /* Check DCMIPP Pipe state */
1313 if (pipe_state != HAL_DCMIPP_PIPE_STATE_RESET)
1314 {
1315 if (DCMIPP_Stop(hdcmipp, Pipe) != HAL_OK)
1316 {
1317 return HAL_ERROR;
1318 }
1319
1320 /* Update the DCMIPP pipe State */
1321 hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_READY;
1322 }
1323 else
1324 {
1325 return HAL_ERROR;
1326 }
1327
1328 return HAL_OK;
1329 }
1330
1331 /**
1332 * @brief Start the DCMIPP capture on the specified pipe for semi-planar
1333 * @param hdcmipp Pointer to DCMIPP handle
1334 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1335 * @param pSemiPlanarDstAddress Pointer to the destination addresses
1336 * @param CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
1337 * @note Only DCMIPP_PIPE1 allows semi-planar buffer
1338 * @retval HAL status
1339 */
HAL_DCMIPP_PIPE_SemiPlanarStart(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,DCMIPP_SemiPlanarDstAddressTypeDef * pSemiPlanarDstAddress,uint32_t CaptureMode)1340 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SemiPlanarStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
1341 DCMIPP_SemiPlanarDstAddressTypeDef *pSemiPlanarDstAddress,
1342 uint32_t CaptureMode)
1343 {
1344 uint32_t mode;
1345 assert_param(IS_DCMIPP_PIPE(Pipe));
1346 assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
1347
1348 /* Check pointer validity */
1349 if ((hdcmipp == NULL) || ((pSemiPlanarDstAddress->UVAddress & 0xFU) != 0U) || \
1350 ((pSemiPlanarDstAddress->YAddress & 0xFU) != 0U))
1351 {
1352 return HAL_ERROR;
1353 }
1354
1355 if (Pipe == DCMIPP_PIPE1)
1356 {
1357 mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
1358 if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_PARALLEL_MODE))
1359 {
1360 return HAL_ERROR;
1361 }
1362 /* Set Capture Mode and Destination address for the selected pipe */
1363 DCMIPP_SetConfig(hdcmipp, Pipe, pSemiPlanarDstAddress->YAddress, CaptureMode);
1364
1365 /* Set Auxiliary Destination addresses */
1366 /* Set the destination address */
1367 WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pSemiPlanarDstAddress->UVAddress);
1368
1369 /* Enable Capture for the selected Pipe */
1370 DCMIPP_EnableCapture(hdcmipp, Pipe);
1371 }
1372 else
1373 {
1374 return HAL_ERROR;
1375 }
1376
1377 return HAL_OK;
1378 }
1379 /**
1380 * @brief Start the DCMIPP capture on the specified pipe with double buffering Mode
1381 * @param hdcmipp Pointer to DCMIPP handle
1382 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1383 * @param pSemiPlanarDstAddress0 Pointer to the first destination addresses
1384 * @param pSemiPlanarDstAddress1 Pointer to the second destination addresses
1385 * @param CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
1386 * @note Only DCMIPP_PIPE1 allows semi-planar buffer
1387 * @retval HAL status
1388 */
HAL_DCMIPP_PIPE_SemiPlanarDoubleBufferStart(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,DCMIPP_SemiPlanarDstAddressTypeDef * pSemiPlanarDstAddress0,DCMIPP_SemiPlanarDstAddressTypeDef * pSemiPlanarDstAddress1,uint32_t CaptureMode)1389 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SemiPlanarDoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
1390 DCMIPP_SemiPlanarDstAddressTypeDef
1391 *pSemiPlanarDstAddress0,
1392 DCMIPP_SemiPlanarDstAddressTypeDef
1393 *pSemiPlanarDstAddress1,
1394 uint32_t CaptureMode)
1395 {
1396 uint32_t mode;
1397 assert_param(IS_DCMIPP_PIPE(Pipe));
1398 assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
1399
1400 /* Check pointer validity */
1401 if ((hdcmipp == NULL) || ((pSemiPlanarDstAddress0->YAddress & 0xFU) != 0U) ||
1402 ((pSemiPlanarDstAddress0->UVAddress & 0xFU) != 0U) || ((pSemiPlanarDstAddress1->YAddress & 0xFU) != 0U) ||
1403 ((pSemiPlanarDstAddress1->UVAddress & 0xFU) != 0U))
1404 {
1405 return HAL_ERROR;
1406 }
1407
1408 if (Pipe == DCMIPP_PIPE1)
1409 {
1410 mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
1411 if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_PARALLEL_MODE))
1412 {
1413 return HAL_ERROR;
1414 }
1415
1416 /* Set Capture Mode and Destination addresses for the selected pipe */
1417 DCMIPP_SetDBMConfig(hdcmipp, Pipe, pSemiPlanarDstAddress0->YAddress, pSemiPlanarDstAddress1->YAddress, CaptureMode);
1418
1419 WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pSemiPlanarDstAddress0->UVAddress);
1420 WRITE_REG(hdcmipp->Instance->P1PPM1AR2, pSemiPlanarDstAddress1->UVAddress);
1421
1422 /* Enable Capture for the selected Pipe */
1423 DCMIPP_EnableCapture(hdcmipp, Pipe);
1424 }
1425 else
1426 {
1427 return HAL_ERROR;
1428 }
1429
1430 return HAL_OK;
1431 }
1432 /**
1433 * @brief Start the DCMIPP capture on the specified pipe for semi-planar
1434 * @param hdcmipp Pointer to DCMIPP handle
1435 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1436 * @param pFullPlanarDstAddress Pointer to the destination addresses
1437 * @param CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
1438 * @note Only DCMIPP_PIPE1 allows Full-planar buffer
1439 * @retval HAL status
1440 */
HAL_DCMIPP_PIPE_FullPlanarStart(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,DCMIPP_FullPlanarDstAddressTypeDef * pFullPlanarDstAddress,uint32_t CaptureMode)1441 HAL_StatusTypeDef HAL_DCMIPP_PIPE_FullPlanarStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
1442 DCMIPP_FullPlanarDstAddressTypeDef *pFullPlanarDstAddress,
1443 uint32_t CaptureMode)
1444 {
1445 uint32_t mode;
1446 assert_param(IS_DCMIPP_PIPE(Pipe));
1447 assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
1448
1449 /* Check pointer validity */
1450 if ((hdcmipp == NULL) || ((pFullPlanarDstAddress->YAddress & 0xFU) != 0U) ||
1451 ((pFullPlanarDstAddress->UAddress & 0xFU) != 0U) || ((pFullPlanarDstAddress->VAddress & 0xFU) != 0U))
1452 {
1453 return HAL_ERROR;
1454 }
1455
1456 if (Pipe == DCMIPP_PIPE1)
1457 {
1458 mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
1459 if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_PARALLEL_MODE))
1460 {
1461 return HAL_ERROR;
1462 }
1463
1464 /* Set Capture Mode and Destination address for the selected pipe */
1465 DCMIPP_SetConfig(hdcmipp, Pipe, pFullPlanarDstAddress->YAddress, CaptureMode);
1466
1467 /* Set Auxiliary Destination addresses */
1468 /* Set the destination address */
1469 WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pFullPlanarDstAddress->UAddress);
1470
1471 WRITE_REG(hdcmipp->Instance->P1PPM2AR1, pFullPlanarDstAddress->VAddress);
1472
1473 /* Enable Capture for the selected Pipe */
1474 DCMIPP_EnableCapture(hdcmipp, Pipe);
1475 }
1476 else
1477 {
1478 return HAL_ERROR;
1479 }
1480
1481 return HAL_OK;
1482 }
1483 /**
1484 * @brief Start the DCMIPP capture on the specified pipe with double buffering Mode
1485 * @param hdcmipp Pointer to DCMIPP handle
1486 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1487 * @param pFullPlanarDstAddress0 Pointer to the first destination addresses
1488 * @param pFullPlanarDstAddress1 Pointer to the second destination addresses
1489 * @param CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
1490 * @note Only DCMIPP_PIPE1 allows Full-planar buffer
1491 * @retval HAL status
1492 */
HAL_DCMIPP_PIPE_FullPlanarDoubleBufferStart(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,DCMIPP_FullPlanarDstAddressTypeDef * pFullPlanarDstAddress0,DCMIPP_FullPlanarDstAddressTypeDef * pFullPlanarDstAddress1,uint32_t CaptureMode)1493 HAL_StatusTypeDef HAL_DCMIPP_PIPE_FullPlanarDoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
1494 DCMIPP_FullPlanarDstAddressTypeDef
1495 *pFullPlanarDstAddress0,
1496 DCMIPP_FullPlanarDstAddressTypeDef
1497 *pFullPlanarDstAddress1, uint32_t CaptureMode)
1498 {
1499 uint32_t mode;
1500 assert_param(IS_DCMIPP_PIPE(Pipe));
1501 assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
1502
1503 /* Check pointer validity */
1504 if ((hdcmipp == NULL) || ((pFullPlanarDstAddress0->YAddress & 0xFU) != 0U) ||
1505 ((pFullPlanarDstAddress0->UAddress & 0xFU) != 0U) || ((pFullPlanarDstAddress0->VAddress & 0xFU) != 0U) ||
1506 ((pFullPlanarDstAddress1->YAddress & 0xFU) != 0U) || ((pFullPlanarDstAddress1->UAddress & 0xFU) != 0U) ||
1507 ((pFullPlanarDstAddress1->VAddress & 0xFU) != 0U))
1508 {
1509 return HAL_ERROR;
1510 }
1511
1512 if (Pipe == DCMIPP_PIPE1)
1513 {
1514 mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
1515 if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_PARALLEL_MODE))
1516 {
1517 return HAL_ERROR;
1518 }
1519
1520 /* Set Capture Mode and Destination addresses for the selected pipe */
1521 DCMIPP_SetDBMConfig(hdcmipp, Pipe, pFullPlanarDstAddress0->YAddress, pFullPlanarDstAddress1->YAddress, CaptureMode);
1522
1523 WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pFullPlanarDstAddress0->UAddress);
1524 WRITE_REG(hdcmipp->Instance->P1PPM1AR2, pFullPlanarDstAddress1->UAddress);
1525
1526 WRITE_REG(hdcmipp->Instance->P1PPM2AR1, pFullPlanarDstAddress0->VAddress);
1527 WRITE_REG(hdcmipp->Instance->P1PPM2AR2, pFullPlanarDstAddress1->VAddress);
1528
1529 /* Enable Capture for the selected Pipe */
1530 DCMIPP_EnableCapture(hdcmipp, Pipe);
1531 }
1532 else
1533 {
1534 return HAL_ERROR;
1535 }
1536
1537 return HAL_OK;
1538 }
1539 /**
1540 * @brief Start DCMIPP capture on the specified pipe and the specified Virtual Channel in Serial Mode
1541 * @param hdcmipp Pointer to DCMIPP handle
1542 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1543 * @param VirtualChannel Virtual Channel to be started can be a value from @ref DCMIPP_Virtual_Channel
1544 * @param DstAddress the destination address
1545 * @param CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
1546 * @retval HAL status
1547 */
HAL_DCMIPP_CSI_PIPE_Start(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t VirtualChannel,uint32_t DstAddress,uint32_t CaptureMode)1548 HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_Start(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t VirtualChannel,
1549 uint32_t DstAddress, uint32_t CaptureMode)
1550 {
1551 uint32_t mode;
1552 assert_param(IS_DCMIPP_PIPE(Pipe));
1553 assert_param(IS_DCMIPP_VCID(VirtualChannel));
1554 assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
1555
1556 /* Check pointer validity */
1557 if ((hdcmipp == NULL) || ((DstAddress & 0xFU) != 0U))
1558 {
1559 return HAL_ERROR;
1560 }
1561
1562 mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
1563 if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_SERIAL_MODE))
1564 {
1565 return HAL_ERROR;
1566 }
1567
1568 /* Set Virtual Channel for the selected Pipe */
1569 if (DCMIPP_CSI_SetVCConfig(hdcmipp, Pipe, VirtualChannel) != HAL_OK)
1570 {
1571 return HAL_ERROR;
1572 }
1573
1574 /* Set Capture Mode and Destination address for the selected pipe */
1575 DCMIPP_SetConfig(hdcmipp, Pipe, DstAddress, CaptureMode);
1576
1577 /* Enable Capture for the selected Pipe */
1578 DCMIPP_EnableCapture(hdcmipp, Pipe);
1579
1580 return HAL_OK;
1581 }
1582 /**
1583 * @brief Start DCMIPP capture on the specified pipe and the specified Virtual Channel in Serial Mode
1584 * with double buffering Mode Enabled
1585 * @param hdcmipp Pointer to DCMIPP handle
1586 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1587 * @param VirtualChannel Virtual Channel to be started can be a value from @ref DCMIPP_Virtual_Channel
1588 * @param DstAddress0 1st destination address
1589 * @param DstAddress1 2nd destination address
1590 * @param CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
1591 * @retval HAL status
1592 */
HAL_DCMIPP_CSI_PIPE_DoubleBufferStart(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t VirtualChannel,uint32_t DstAddress0,uint32_t DstAddress1,uint32_t CaptureMode)1593 HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_DoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
1594 uint32_t VirtualChannel, uint32_t DstAddress0,
1595 uint32_t DstAddress1, uint32_t CaptureMode)
1596 {
1597 uint32_t mode;
1598 assert_param(IS_DCMIPP_PIPE(Pipe));
1599 assert_param(IS_DCMIPP_VCID(VirtualChannel));
1600 assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
1601
1602 /* Check pointer validity */
1603 if ((hdcmipp == NULL) || ((DstAddress0 & 0xFU) != 0U) || ((DstAddress1 & 0xFU) != 0U))
1604 {
1605 return HAL_ERROR;
1606 }
1607
1608 mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
1609 if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_SERIAL_MODE))
1610 {
1611 return HAL_ERROR;
1612 }
1613
1614 /* Set Virtual Channel for the selected Pipe */
1615 if (DCMIPP_CSI_SetVCConfig(hdcmipp, Pipe, VirtualChannel) != HAL_OK)
1616 {
1617 return HAL_ERROR;
1618 }
1619
1620 /* Set the Address and CaptureMode for the selected Pipe */
1621 DCMIPP_SetDBMConfig(hdcmipp, Pipe, DstAddress0, DstAddress1, CaptureMode);
1622
1623 /* Enable Capture for the selected Pipe */
1624 DCMIPP_EnableCapture(hdcmipp, Pipe);
1625
1626 return HAL_OK;
1627 }
1628 /**
1629 * @brief Stop DCMIPP capture on the specified pipe and the specified Virtual Channel
1630 * @param hdcmipp Pointer to DCMIPP handle
1631 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1632 * @param VirtualChannel Virtual Channel to be stopped can be a value from @ref DCMIPP_Virtual_Channel
1633 * @retval HAL status
1634 */
HAL_DCMIPP_CSI_PIPE_Stop(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t VirtualChannel)1635 HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t VirtualChannel)
1636 {
1637 HAL_DCMIPP_PipeStateTypeDef pipe_state;
1638 HAL_StatusTypeDef status = HAL_OK;
1639
1640 assert_param(IS_DCMIPP_PIPE(Pipe));
1641 assert_param(IS_DCMIPP_VCID(VirtualChannel));
1642
1643 /* Check pointer validity */
1644 if (hdcmipp == NULL)
1645 {
1646 return HAL_ERROR;
1647 }
1648
1649 if ((hdcmipp->Instance->CMCR & DCMIPP_CMCR_INSEL) != DCMIPP_SERIAL_MODE)
1650 {
1651 return HAL_ERROR;
1652 }
1653
1654 pipe_state = hdcmipp->PipeState[Pipe];
1655
1656 /* Check DCMIPP Pipe state */
1657 if (pipe_state != HAL_DCMIPP_PIPE_STATE_RESET)
1658 {
1659 if (DCMIPP_Stop(hdcmipp, Pipe) != HAL_OK)
1660 {
1661 return HAL_ERROR;
1662 }
1663
1664 if (DCMIPP_CSI_VCStop(hdcmipp, VirtualChannel) != HAL_OK)
1665 {
1666 return HAL_ERROR;
1667 }
1668
1669 /* Update the DCMIPP pipe State */
1670 hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_READY;
1671 }
1672 else
1673 {
1674 status = HAL_ERROR;
1675 }
1676
1677 return status;
1678 }
1679
1680 /**
1681 * @brief Start the DCMIPP capture on the specified pipe for semi-planar in Serial Mode
1682 * @param hdcmipp Pointer to DCMIPP handle
1683 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1684 * @param VirtualChannel Virtual Channel to be started can be a value from @ref DCMIPP_Virtual_Channel
1685 * @param pSemiPlanarDstAddress Pointer to the destination addresses
1686 * @param CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
1687 * @note Only DCMIPP_PIPE1 allows semi-planar buffer
1688 * @retval HAL status
1689 */
HAL_DCMIPP_CSI_PIPE_SemiPlanarStart(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t VirtualChannel,DCMIPP_SemiPlanarDstAddressTypeDef * pSemiPlanarDstAddress,uint32_t CaptureMode)1690 HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_SemiPlanarStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
1691 uint32_t VirtualChannel,
1692 DCMIPP_SemiPlanarDstAddressTypeDef *pSemiPlanarDstAddress,
1693 uint32_t CaptureMode)
1694 {
1695 uint32_t mode;
1696 assert_param(IS_DCMIPP_PIPE(Pipe));
1697 assert_param(IS_DCMIPP_VCID(VirtualChannel));
1698 assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
1699
1700 /* Check pointer validity */
1701 if ((hdcmipp == NULL) || ((pSemiPlanarDstAddress->UVAddress & 0xFU) != 0U) || \
1702 ((pSemiPlanarDstAddress->YAddress & 0xFU) != 0U))
1703 {
1704 return HAL_ERROR;
1705 }
1706
1707 if (Pipe == DCMIPP_PIPE1)
1708 {
1709 mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
1710 if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_SERIAL_MODE))
1711 {
1712 return HAL_ERROR;
1713 }
1714
1715 /* Set Virtual Channel for the selected Pipe */
1716 if (DCMIPP_CSI_SetVCConfig(hdcmipp, Pipe, VirtualChannel) != HAL_OK)
1717 {
1718 return HAL_ERROR;
1719 }
1720
1721 /* Set Capture Mode and Destination address for the selected pipe */
1722 DCMIPP_SetConfig(hdcmipp, Pipe, pSemiPlanarDstAddress->YAddress, CaptureMode);
1723
1724 /* Set Auxiliary Destination addresses */
1725 /* Set the destination address */
1726 WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pSemiPlanarDstAddress->UVAddress);
1727
1728 /* Enable Capture for the selected Pipe */
1729 DCMIPP_EnableCapture(hdcmipp, Pipe);
1730 }
1731 else
1732 {
1733 return HAL_ERROR;
1734 }
1735
1736 return HAL_OK;
1737 }
1738 /**
1739 * @brief Start the DCMIPP capture on the specified pipe with double buffering Mode in Serial Mode
1740 * @param hdcmipp Pointer to DCMIPP handle
1741 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1742 * @param VirtualChannel Virtual Channel to be started can be a value from @ref DCMIPP_Virtual_Channel
1743 * @param pSemiPlanarDstAddress0 Pointer to the first destination addresses
1744 * @param pSemiPlanarDstAddress1 Pointer to the second destination addresses
1745 * @param CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
1746 * @note Only DCMIPP_PIPE1 allows semi-planar buffer
1747 * @retval HAL status
1748 */
HAL_DCMIPP_CSI_PIPE_SemiPlanarDoubleBufferStart(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t VirtualChannel,DCMIPP_SemiPlanarDstAddressTypeDef * pSemiPlanarDstAddress0,DCMIPP_SemiPlanarDstAddressTypeDef * pSemiPlanarDstAddress1,uint32_t CaptureMode)1749 HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_SemiPlanarDoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
1750 uint32_t VirtualChannel,
1751 DCMIPP_SemiPlanarDstAddressTypeDef
1752 *pSemiPlanarDstAddress0,
1753 DCMIPP_SemiPlanarDstAddressTypeDef
1754 *pSemiPlanarDstAddress1, uint32_t CaptureMode)
1755 {
1756 uint32_t mode;
1757 assert_param(IS_DCMIPP_PIPE(Pipe));
1758 assert_param(IS_DCMIPP_VCID(VirtualChannel));
1759 assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
1760
1761 /* Check pointer validity */
1762 if ((hdcmipp == NULL) || ((pSemiPlanarDstAddress0->YAddress & 0xFU) != 0U) ||
1763 ((pSemiPlanarDstAddress0->UVAddress & 0xFU) != 0U) ||
1764 ((pSemiPlanarDstAddress1->YAddress & 0xFU) != 0U) ||
1765 ((pSemiPlanarDstAddress1->UVAddress & 0xFU) != 0U))
1766 {
1767 return HAL_ERROR;
1768 }
1769
1770 if (Pipe == DCMIPP_PIPE1)
1771 {
1772 mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
1773 if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_SERIAL_MODE))
1774 {
1775 return HAL_ERROR;
1776 }
1777
1778 /* Set Virtual Channel for the selected Pipe */
1779 if (DCMIPP_CSI_SetVCConfig(hdcmipp, Pipe, VirtualChannel) != HAL_OK)
1780 {
1781 return HAL_ERROR;
1782 }
1783
1784 /* Set Capture Mode and Destination addresses for the selected pipe */
1785 DCMIPP_SetDBMConfig(hdcmipp, Pipe, pSemiPlanarDstAddress0->YAddress, pSemiPlanarDstAddress1->YAddress, CaptureMode);
1786
1787 WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pSemiPlanarDstAddress0->UVAddress);
1788 WRITE_REG(hdcmipp->Instance->P1PPM1AR2, pSemiPlanarDstAddress1->UVAddress);
1789
1790 /* Enable Capture for the selected Pipe */
1791 DCMIPP_EnableCapture(hdcmipp, Pipe);
1792 }
1793 else
1794 {
1795 return HAL_ERROR;
1796 }
1797
1798 return HAL_OK;
1799 }
1800 /**
1801 * @brief Start the DCMIPP capture on the specified pipe for semi-planar in Serial Mode
1802 * @param hdcmipp Pointer to DCMIPP handle
1803 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1804 * @param VirtualChannel Virtual Channel to be started can be a value from @ref DCMIPP_Virtual_Channel
1805 * @param pFullPlanarDstAddress Pointer to the destination addresses
1806 * @param CaptureMode DCMIPP capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
1807 * @note Only DCMIPP_PIPE1 allows Full-planar buffer
1808 * @retval HAL status
1809 */
HAL_DCMIPP_CSI_PIPE_FullPlanarStart(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t VirtualChannel,DCMIPP_FullPlanarDstAddressTypeDef * pFullPlanarDstAddress,uint32_t CaptureMode)1810 HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_FullPlanarStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
1811 uint32_t VirtualChannel,
1812 DCMIPP_FullPlanarDstAddressTypeDef *pFullPlanarDstAddress,
1813 uint32_t CaptureMode)
1814 {
1815 uint32_t mode;
1816 assert_param(IS_DCMIPP_PIPE(Pipe));
1817 assert_param(IS_DCMIPP_VCID(VirtualChannel));
1818 assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
1819
1820 /* Check pointer validity */
1821 if ((hdcmipp == NULL) || ((pFullPlanarDstAddress->YAddress & 0xFU) != 0U) ||
1822 ((pFullPlanarDstAddress->UAddress & 0xFU) != 0U) ||
1823 ((pFullPlanarDstAddress->VAddress & 0xFU) != 0U))
1824 {
1825 return HAL_ERROR;
1826 }
1827
1828 if (Pipe == DCMIPP_PIPE1)
1829 {
1830 mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
1831 if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_SERIAL_MODE))
1832 {
1833 return HAL_ERROR;
1834 }
1835
1836 /* Set Virtual Channel for the selected Pipe */
1837 if (DCMIPP_CSI_SetVCConfig(hdcmipp, Pipe, VirtualChannel) != HAL_OK)
1838 {
1839 return HAL_ERROR;
1840 }
1841
1842 /* Set Capture Mode and Destination address for the selected pipe */
1843 DCMIPP_SetConfig(hdcmipp, Pipe, pFullPlanarDstAddress->YAddress, CaptureMode);
1844
1845 /* Set Auxiliary Destination addresses */
1846 /* Set the destination address */
1847 WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pFullPlanarDstAddress->UAddress);
1848
1849 WRITE_REG(hdcmipp->Instance->P1PPM2AR1, pFullPlanarDstAddress->VAddress);
1850
1851 /* Enable Capture for the selected Pipe */
1852 DCMIPP_EnableCapture(hdcmipp, Pipe);
1853 }
1854 else
1855 {
1856 return HAL_ERROR;
1857 }
1858
1859 return HAL_OK;
1860 }
1861 /**
1862 * @brief Start the DCMIPP capture on the specified pipe with double buffering Mode in Serial Mode
1863 * @param hdcmipp Pointer to DCMIPP handle
1864 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1865 * @param VirtualChannel Virtual Channel to be started can be a value from @ref DCMIPP_Virtual_Channel
1866 * @param pFullPlanarDstAddress0 Pointer to the first destination addresses
1867 * @param pFullPlanarDstAddress1 Pointer to the second destination addresses
1868 * @param CaptureMode capture mode for the pipe can be a value from @ref DCMIPP_Capture_Mode.
1869 * @note Only DCMIPP_PIPE1 allows Full-planar buffer
1870 * @retval HAL status
1871 */
HAL_DCMIPP_CSI_PIPE_FullPlanarDoubleBufferStart(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t VirtualChannel,DCMIPP_FullPlanarDstAddressTypeDef * pFullPlanarDstAddress0,DCMIPP_FullPlanarDstAddressTypeDef * pFullPlanarDstAddress1,uint32_t CaptureMode)1872 HAL_StatusTypeDef HAL_DCMIPP_CSI_PIPE_FullPlanarDoubleBufferStart(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
1873 uint32_t VirtualChannel,
1874 DCMIPP_FullPlanarDstAddressTypeDef
1875 *pFullPlanarDstAddress0,
1876 DCMIPP_FullPlanarDstAddressTypeDef
1877 *pFullPlanarDstAddress1, uint32_t CaptureMode)
1878 {
1879 uint32_t mode;
1880 assert_param(IS_DCMIPP_PIPE(Pipe));
1881 assert_param(IS_DCMIPP_VCID(VirtualChannel));
1882 assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
1883
1884 /* Check pointer validity */
1885 if ((hdcmipp == NULL) || ((pFullPlanarDstAddress0->YAddress & 0xFU) != 0U) ||
1886 ((pFullPlanarDstAddress0->UAddress & 0xFU) != 0U) || ((pFullPlanarDstAddress0->VAddress & 0xFU) != 0U) ||
1887 ((pFullPlanarDstAddress1->YAddress & 0xFU) != 0U) || ((pFullPlanarDstAddress1->UAddress & 0xFU) != 0U) ||
1888 ((pFullPlanarDstAddress1->VAddress & 0xFU) != 0U))
1889 {
1890 return HAL_ERROR;
1891 }
1892
1893 if (Pipe == DCMIPP_PIPE1)
1894 {
1895 mode = READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL);
1896 if ((hdcmipp->PipeState[Pipe] != HAL_DCMIPP_PIPE_STATE_READY) || (mode != DCMIPP_SERIAL_MODE))
1897 {
1898 return HAL_ERROR;
1899 }
1900
1901 /* Set Virtual Channel for the selected Pipe */
1902 if (DCMIPP_CSI_SetVCConfig(hdcmipp, Pipe, VirtualChannel) != HAL_OK)
1903 {
1904 return HAL_ERROR;
1905 }
1906
1907 /* Set Capture Mode and Destination addresses for the selected pipe */
1908 DCMIPP_SetDBMConfig(hdcmipp, Pipe, pFullPlanarDstAddress0->YAddress, pFullPlanarDstAddress1->YAddress, CaptureMode);
1909
1910 WRITE_REG(hdcmipp->Instance->P1PPM1AR1, pFullPlanarDstAddress0->UAddress);
1911 WRITE_REG(hdcmipp->Instance->P1PPM1AR2, pFullPlanarDstAddress1->UAddress);
1912
1913 WRITE_REG(hdcmipp->Instance->P1PPM2AR1, pFullPlanarDstAddress0->VAddress);
1914 WRITE_REG(hdcmipp->Instance->P1PPM2AR2, pFullPlanarDstAddress1->VAddress);
1915
1916 /* Enable Capture for the selected Pipe */
1917 DCMIPP_EnableCapture(hdcmipp, Pipe);
1918 }
1919 else
1920 {
1921 return HAL_ERROR;
1922 }
1923
1924 return HAL_OK;
1925 }
1926 /**
1927 * @brief Suspend DCMIPP capture on the specified pipe
1928 * @param hdcmipp Pointer to DCMIPP handle
1929 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
1930 * @retval HAL status
1931 */
HAL_DCMIPP_PIPE_Suspend(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)1932 HAL_StatusTypeDef HAL_DCMIPP_PIPE_Suspend(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
1933 {
1934 HAL_DCMIPP_PipeStateTypeDef pipe_state;
1935 uint32_t tickstart;
1936
1937 assert_param(IS_DCMIPP_PIPE(Pipe));
1938
1939 if (hdcmipp == NULL)
1940 {
1941 /* Return Function Status */
1942 return HAL_ERROR;
1943 }
1944
1945 pipe_state = hdcmipp->PipeState[Pipe];
1946
1947 if (Pipe == DCMIPP_PIPE0)
1948 {
1949 /* Check Pipe0 State */
1950 if (pipe_state == HAL_DCMIPP_PIPE_STATE_BUSY)
1951 {
1952 /* Disable Capture Request */
1953 CLEAR_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
1954
1955 /* Change Pipe State */
1956 hdcmipp->PipeState[0] = HAL_DCMIPP_PIPE_STATE_SUSPEND;
1957
1958 /* Poll CPTACT status till No capture currently active */
1959 tickstart = HAL_GetTick();
1960 do
1961 {
1962 if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
1963 {
1964 /* Change Pipe State */
1965 hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_ERROR;
1966
1967 return HAL_ERROR;
1968 }
1969 } while ((hdcmipp->Instance->CMSR1 & DCMIPP_CMSR1_P0CPTACT) != 0U);
1970 }
1971 else
1972 {
1973 /* Return Function Status */
1974 return HAL_ERROR;
1975 }
1976 }
1977 else if (Pipe == DCMIPP_PIPE1)
1978 {
1979 if (pipe_state == HAL_DCMIPP_PIPE_STATE_BUSY)
1980 {
1981 /* Disable Capture Request */
1982 CLEAR_BIT(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTREQ);
1983 /* Change Pipe State */
1984 hdcmipp->PipeState[1] = HAL_DCMIPP_PIPE_STATE_SUSPEND;
1985
1986 /* Poll CPTACT status till No capture currently active */
1987 tickstart = HAL_GetTick();
1988 do
1989 {
1990 if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
1991 {
1992 /* Change Pipe State */
1993 hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_ERROR;
1994
1995 return HAL_ERROR;
1996 }
1997 } while ((hdcmipp->Instance->CMSR1 & DCMIPP_CMSR1_P1CPTACT) != 0U);
1998 }
1999 else
2000 {
2001 /* Return Function Status */
2002 return HAL_ERROR;
2003 }
2004
2005 }
2006 else if (Pipe == DCMIPP_PIPE2)
2007 {
2008 if (pipe_state == HAL_DCMIPP_PIPE_STATE_BUSY)
2009 {
2010 /* Disable Capture Request */
2011 CLEAR_BIT(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTREQ);
2012 /* Change Pipe State */
2013 hdcmipp->PipeState[2] = HAL_DCMIPP_PIPE_STATE_SUSPEND;
2014
2015 /* Poll CPTACT status till No capture currently active */
2016 tickstart = HAL_GetTick();
2017 do
2018 {
2019 if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
2020 {
2021 /* Change Pipe State */
2022 hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_ERROR;
2023
2024 return HAL_ERROR;
2025 }
2026 } while ((hdcmipp->Instance->CMSR1 & DCMIPP_CMSR1_P2CPTACT) != 0U);
2027 }
2028 else
2029 {
2030 /* Return Function Status */
2031 return HAL_ERROR;
2032 }
2033 }
2034 else
2035 {
2036 return HAL_ERROR;
2037 }
2038
2039 /* Return Function Status */
2040 return HAL_OK;
2041 }
2042
2043 /**
2044 * @brief Resume DCMIPP capture on the specified pipe
2045 * @param hdcmipp Pointer to DCMIPP handle
2046 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
2047 * @retval HAL status
2048 */
HAL_DCMIPP_PIPE_Resume(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)2049 HAL_StatusTypeDef HAL_DCMIPP_PIPE_Resume(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
2050 {
2051 HAL_DCMIPP_PipeStateTypeDef pipe_state ;
2052
2053 assert_param(IS_DCMIPP_PIPE(Pipe));
2054
2055 if (hdcmipp == NULL)
2056 {
2057 return HAL_ERROR;
2058 }
2059
2060 pipe_state = hdcmipp->PipeState[Pipe];
2061
2062 if (Pipe == DCMIPP_PIPE0)
2063 {
2064 /* Check Pipe0 State */
2065 if (pipe_state == HAL_DCMIPP_PIPE_STATE_SUSPEND)
2066 {
2067 /* Enable Capture Request */
2068 SET_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
2069
2070 /* Change Pipe State */
2071 hdcmipp->PipeState[0] = HAL_DCMIPP_PIPE_STATE_BUSY;
2072 }
2073 else
2074 {
2075 return HAL_ERROR;
2076 }
2077 }
2078 else if (Pipe == DCMIPP_PIPE1)
2079 {
2080 if (pipe_state == HAL_DCMIPP_PIPE_STATE_SUSPEND)
2081 {
2082 /* Enable Capture Request */
2083 SET_BIT(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTREQ);
2084 /* Change Pipe State */
2085 hdcmipp->PipeState[1] = HAL_DCMIPP_PIPE_STATE_BUSY;
2086 }
2087 else
2088 {
2089 return HAL_ERROR;
2090 }
2091 }
2092 else if (Pipe == DCMIPP_PIPE2)
2093 {
2094 if (pipe_state == HAL_DCMIPP_PIPE_STATE_SUSPEND)
2095 {
2096 /* Enable Capture Request */
2097 SET_BIT(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTREQ);
2098 /* Change Pipe State */
2099 hdcmipp->PipeState[2] = HAL_DCMIPP_PIPE_STATE_BUSY;
2100 }
2101 else
2102 {
2103 return HAL_ERROR;
2104 }
2105 }
2106 else
2107 {
2108 return HAL_ERROR;
2109 }
2110
2111 return HAL_OK;
2112 }
2113
2114 /**
2115 * @}
2116 */
2117
2118 /** @addtogroup DCMIPP_IRQ_and_Callbacks_Functions DCMIPP IRQ and Callbacks Functions
2119 * @brief IRQ and Callbacks functions
2120 * @{
2121 */
2122
2123 /** @addtogroup DCMIPP_IRQHandler_Function IRQHandler Function
2124 * @{
2125 */
2126 /**
2127 * @brief Handles DCMIPP interrupt request.
2128 * @param hdcmipp Pointer to DCMIPP handle
2129 * @retval None
2130 */
HAL_DCMIPP_IRQHandler(DCMIPP_HandleTypeDef * hdcmipp)2131 void HAL_DCMIPP_IRQHandler(DCMIPP_HandleTypeDef *hdcmipp)
2132 {
2133 uint32_t cmsr2flags = READ_REG(hdcmipp->Instance->CMSR2);
2134 uint32_t cmierflags = READ_REG(hdcmipp->Instance->CMIER);
2135
2136 /* ========================= PIPE0 INTERRUPTS ==================== */
2137 /* Limit error on the PIPE0 ********************************************/
2138 if ((cmsr2flags & DCMIPP_FLAG_PIPE0_LIMIT) != 0U)
2139 {
2140 if ((cmierflags & DCMIPP_IT_PIPE0_LIMIT) != 0U)
2141 {
2142 /* Disable Limit error Interrupt for pipe0 */
2143 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LIMIT);
2144
2145 /* Update error code */
2146 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_PIPE0_LIMIT;
2147
2148 /* Clear the Limit error flag */
2149 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_LIMIT);
2150
2151 /* LIMIT Callback */
2152 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2153 hdcmipp->PIPE_LimitEventCallback(hdcmipp, DCMIPP_PIPE0);
2154 #else
2155 HAL_DCMIPP_PIPE_LimitEventCallback(hdcmipp, DCMIPP_PIPE0);
2156 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2157 }
2158 }
2159
2160 /* VSYNC interrupt management **********************************************/
2161 if ((cmsr2flags & DCMIPP_FLAG_PIPE0_VSYNC) != 0U)
2162 {
2163 if ((cmierflags & DCMIPP_IT_PIPE0_VSYNC) != 0U)
2164 {
2165 /* Clear the VSYNC flag for pipe0 */
2166 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_VSYNC);
2167
2168 /* VSYNC Callback */
2169 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2170 hdcmipp->PIPE_VsyncEventCallback(hdcmipp, DCMIPP_PIPE0);
2171 #else
2172 HAL_DCMIPP_PIPE_VsyncEventCallback(hdcmipp, DCMIPP_PIPE0);
2173 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2174 }
2175 }
2176
2177 /* FRAME interrupt management ****************************/
2178 if ((cmsr2flags & DCMIPP_FLAG_PIPE0_FRAME) != 0U)
2179 {
2180 if ((cmierflags & DCMIPP_IT_PIPE0_FRAME) != 0U)
2181 {
2182 /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
2183 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2184 {
2185 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_OVR);
2186
2187 /* Update Pipe State */
2188 hdcmipp->PipeState[0] = HAL_DCMIPP_PIPE_STATE_READY;
2189 }
2190
2191 /* Clear the End of Frame flag */
2192 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_FRAME);
2193
2194 /* Frame Callback */
2195 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2196 hdcmipp->PIPE_FrameEventCallback(hdcmipp, DCMIPP_PIPE0);
2197 #else
2198 HAL_DCMIPP_PIPE_FrameEventCallback(hdcmipp, DCMIPP_PIPE0);
2199 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2200 }
2201 }
2202
2203 /* LINE interrupt management **********************************************/
2204 if ((cmsr2flags & DCMIPP_FLAG_PIPE0_LINE) != 0U)
2205 {
2206 if ((cmierflags & DCMIPP_IT_PIPE0_LINE) != 0U)
2207 {
2208 /* Clear the LINE flag */
2209 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_LINE);
2210
2211 /* LINE Callback */
2212 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2213 hdcmipp->PIPE_LineEventCallback(hdcmipp, DCMIPP_PIPE0);
2214 #else
2215 HAL_DCMIPP_PIPE_LineEventCallback(hdcmipp, DCMIPP_PIPE0);
2216 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2217 }
2218 }
2219
2220 /* Overrun error interrupt for Pipe0 ***************************************/
2221 if ((cmsr2flags & DCMIPP_FLAG_PIPE0_OVR) != 0U)
2222 {
2223 if ((cmierflags & DCMIPP_IT_PIPE0_OVR) != 0U)
2224 {
2225 /* Disable Overrun Error Interrupt for pipe0 */
2226 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_OVR);
2227
2228 /* Update error code */
2229 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_PIPE0_OVR;
2230
2231 /* Clear the overrun error flag */
2232 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE0_OVR);
2233
2234 /* Change DCMIPP Pipe state */
2235 hdcmipp->PipeState[0] = HAL_DCMIPP_PIPE_STATE_ERROR;
2236
2237 /* Error Callback */
2238 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2239 hdcmipp->PIPE_ErrorCallback(hdcmipp, DCMIPP_PIPE0);
2240 #else
2241 HAL_DCMIPP_PIPE_ErrorCallback(hdcmipp, DCMIPP_PIPE0);
2242 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2243 }
2244 }
2245
2246 /* ========================= PIPE1 INTERRUPTS ==================== */
2247 if ((cmsr2flags & DCMIPP_FLAG_PIPE1_LINE) != 0U)
2248 {
2249 if ((cmierflags & DCMIPP_FLAG_PIPE1_LINE) != 0U)
2250 {
2251 /* Clear the End of Frame flag */
2252 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE1_LINE);
2253
2254 /* Frame Callback */
2255 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2256 hdcmipp->PIPE_LineEventCallback(hdcmipp, DCMIPP_PIPE1);
2257 #else
2258 HAL_DCMIPP_PIPE_LineEventCallback(hdcmipp, DCMIPP_PIPE1);
2259 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2260 }
2261 }
2262
2263 /* VSYNC interrupt management **********************************************/
2264 if ((cmsr2flags & DCMIPP_FLAG_PIPE1_VSYNC) != 0U)
2265 {
2266 if ((cmierflags & DCMIPP_IT_PIPE1_VSYNC) != 0U)
2267 {
2268 /* Clear the VSYNC flag */
2269 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE1_VSYNC);
2270
2271 /* VSYNC Callback */
2272 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2273 hdcmipp->PIPE_VsyncEventCallback(hdcmipp, DCMIPP_PIPE1);
2274 #else
2275 HAL_DCMIPP_PIPE_VsyncEventCallback(hdcmipp, DCMIPP_PIPE1);
2276 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2277 }
2278 }
2279
2280 if ((cmsr2flags & DCMIPP_FLAG_PIPE1_FRAME) != 0U)
2281 {
2282 if ((cmierflags & DCMIPP_IT_PIPE1_FRAME) != 0U)
2283 {
2284 /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
2285 if ((hdcmipp->Instance->P1FCTCR & DCMIPP_P1FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2286 {
2287 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE1_FRAME | DCMIPP_IT_PIPE1_VSYNC | DCMIPP_IT_PIPE1_OVR);
2288
2289 /* Update Pipe State */
2290 hdcmipp->PipeState[1] = HAL_DCMIPP_PIPE_STATE_READY;
2291 }
2292
2293 /* Clear the End of Frame flag */
2294 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE1_FRAME);
2295
2296 /* Frame Callback */
2297 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2298 hdcmipp->PIPE_FrameEventCallback(hdcmipp, DCMIPP_PIPE1);
2299 #else
2300 HAL_DCMIPP_PIPE_FrameEventCallback(hdcmipp, DCMIPP_PIPE1);
2301 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2302 }
2303 }
2304
2305 /* Overrun error on the PIPE1 **************************************/
2306 if ((cmsr2flags & DCMIPP_FLAG_PIPE1_OVR) != 0U)
2307 {
2308 if ((cmierflags & DCMIPP_IT_PIPE1_OVR) != 0U)
2309 {
2310 /* Disable Overrun Error Interrupt for pipe1 */
2311 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE1_OVR);
2312
2313 /* Update error code */
2314 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_PIPE1_OVR;
2315
2316 /* Clear the overrun error flag */
2317 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE1_OVR);
2318
2319 /* Change DCMIPP state */
2320 hdcmipp->PipeState[1] = HAL_DCMIPP_PIPE_STATE_ERROR;
2321
2322 /* Error Callback */
2323 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2324 hdcmipp->PIPE_ErrorCallback(hdcmipp, DCMIPP_PIPE1);
2325 #else
2326 HAL_DCMIPP_PIPE_ErrorCallback(hdcmipp, DCMIPP_PIPE1);
2327 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2328 }
2329 }
2330
2331 /* ========================= PIPE2 INTERRUPTS ==================== */
2332 if ((cmsr2flags & DCMIPP_FLAG_PIPE2_LINE) != 0U)
2333 {
2334 if ((cmierflags & DCMIPP_IT_PIPE2_LINE) != 0U)
2335 {
2336 /* Clear the End of Line flag */
2337 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE2_LINE);
2338
2339 /* Frame Callback */
2340 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2341 hdcmipp->PIPE_LineEventCallback(hdcmipp, DCMIPP_PIPE2);
2342 #else
2343 HAL_DCMIPP_PIPE_LineEventCallback(hdcmipp, DCMIPP_PIPE2);
2344 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2345 }
2346 }
2347
2348 /* VSYNC interrupt management **********************************************/
2349 if ((cmsr2flags & DCMIPP_FLAG_PIPE2_VSYNC) != 0U)
2350 {
2351 if ((cmierflags & DCMIPP_IT_PIPE2_VSYNC) != 0U)
2352 {
2353 /* Clear the VSYNC flag */
2354 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE2_VSYNC);
2355
2356 /* VSYNC Callback */
2357 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2358 hdcmipp->PIPE_VsyncEventCallback(hdcmipp, DCMIPP_PIPE2);
2359 #else
2360 HAL_DCMIPP_PIPE_VsyncEventCallback(hdcmipp, DCMIPP_PIPE2);
2361 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2362 }
2363 }
2364
2365 if ((cmsr2flags & DCMIPP_FLAG_PIPE2_FRAME) != 0U)
2366 {
2367 if ((cmierflags & DCMIPP_IT_PIPE2_FRAME) != 0U)
2368 {
2369 /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
2370 if ((hdcmipp->Instance->P2FCTCR & DCMIPP_P2FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2371 {
2372 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE2_FRAME | DCMIPP_IT_PIPE2_VSYNC | DCMIPP_IT_PIPE2_OVR);
2373
2374 /* Update Pipe State */
2375 hdcmipp->PipeState[2] = HAL_DCMIPP_PIPE_STATE_READY;
2376 }
2377
2378 /* Clear the End of Frame flag */
2379 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE2_FRAME);
2380
2381 /* Frame Callback */
2382 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2383 hdcmipp->PIPE_FrameEventCallback(hdcmipp, DCMIPP_PIPE2);
2384 #else
2385 HAL_DCMIPP_PIPE_FrameEventCallback(hdcmipp, DCMIPP_PIPE2);
2386 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2387 }
2388 }
2389 /* Overrun error on the PIPE2 **************************************/
2390 if ((cmsr2flags & DCMIPP_FLAG_PIPE2_OVR) != 0U)
2391 {
2392 if ((cmierflags & DCMIPP_IT_PIPE2_OVR) != 0U)
2393 {
2394 /* Disable Overrun Error Interrupt for pipe1 */
2395 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE2_OVR);
2396
2397 /* Update error code */
2398 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_PIPE2_OVR;
2399
2400 /* Clear the overrun error flag */
2401 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PIPE2_OVR);
2402
2403 /* Change DCMIPP state */
2404 hdcmipp->PipeState[2] = HAL_DCMIPP_PIPE_STATE_ERROR;
2405
2406 /* Error Callback */
2407 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2408 hdcmipp->PIPE_ErrorCallback(hdcmipp, DCMIPP_PIPE2);
2409 #else
2410 HAL_DCMIPP_PIPE_ErrorCallback(hdcmipp, DCMIPP_PIPE2);
2411 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2412 }
2413 }
2414
2415 /* Synchronization Error Interrupt on the parallel interface **************/
2416 if ((cmsr2flags & DCMIPP_FLAG_PARALLEL_SYNC_ERROR) != 0U)
2417 {
2418 if ((cmierflags & DCMIPP_IT_PARALLEL_SYNC_ERROR) != 0U)
2419 {
2420 /* Disable Synchronization error interrupt on parallel interface */
2421 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PARALLEL_SYNC_ERROR);
2422
2423 /* Update error code */
2424 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_PARALLEL_SYNC;
2425
2426 /* Clear the synchronization error flag */
2427 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_PARALLEL_SYNC_ERROR);
2428
2429 /* Change DCMIPP state */
2430 hdcmipp->State = HAL_DCMIPP_STATE_ERROR;
2431
2432 /* Error Callback */
2433 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2434 hdcmipp->ErrorCallback(hdcmipp);
2435 #else
2436 HAL_DCMIPP_ErrorCallback(hdcmipp);
2437 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2438 }
2439 }
2440
2441 /* IPPLUG AXI transfer Error Interrupt *********************************/
2442 if ((cmsr2flags & DCMIPP_FLAG_AXI_TRANSFER_ERROR) != 0U)
2443 {
2444 if ((cmierflags & DCMIPP_IT_AXI_TRANSFER_ERROR) != 0U)
2445 {
2446 /* Disable IPPLUG AXI transfer Error Interrupt */
2447 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_AXI_TRANSFER_ERROR);
2448
2449 /* Update error code */
2450 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_AXI_TRANSFER;
2451
2452 /* Clear the AXI transfer error flag */
2453 __HAL_DCMIPP_CLEAR_FLAG(hdcmipp, DCMIPP_FLAG_AXI_TRANSFER_ERROR);
2454
2455 /* Change DCMIPP state */
2456 hdcmipp->State = HAL_DCMIPP_STATE_ERROR;
2457
2458 /* Error Callback */
2459 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2460 hdcmipp->ErrorCallback(hdcmipp);
2461 #else
2462 HAL_DCMIPP_ErrorCallback(hdcmipp);
2463 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2464 }
2465 }
2466 }
2467
2468 /**
2469 * @brief Handles DCMIPP CSI interrupt request.
2470 * @param hdcmipp Pointer to DCMIPP handle
2471 * @retval None
2472 */
HAL_DCMIPP_CSI_IRQHandler(DCMIPP_HandleTypeDef * hdcmipp)2473 void HAL_DCMIPP_CSI_IRQHandler(DCMIPP_HandleTypeDef *hdcmipp)
2474 {
2475 CSI_TypeDef *csi_instance;
2476 csi_instance = CSI;
2477
2478 /* Read the SR0 register once */
2479 uint32_t sr0flags = READ_REG(csi_instance->SR0);
2480 uint32_t sr1flags = READ_REG(csi_instance->SR1);
2481
2482 uint32_t ier0_flags = READ_REG(csi_instance->IER0);
2483 uint32_t ier1_flags = READ_REG(csi_instance->IER1);
2484
2485 /* Clock changer FIFO full event */
2486 if ((sr0flags & DCMIPP_CSI_FLAG_CCFIFO) != 0U)
2487 {
2488 if ((ier0_flags & DCMIPP_CSI_IT_CCFIFO) != 0U)
2489 {
2490 /* Disable IT */
2491 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_CCFIFO);
2492
2493 /* Clear Flag */
2494 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_CCFIFO);
2495
2496 /* Error Callback */
2497 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2498 hdcmipp->ClockChangerFifoFullEventCallback(hdcmipp);
2499 #else
2500 HAL_DCMIPP_CSI_ClockChangerFifoFullEventCallback(hdcmipp);
2501 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2502 }
2503 }
2504
2505 /*###############################
2506 Byte/Line Counter Interrupt
2507 ##############################*/
2508 if ((sr0flags & DCMIPP_CSI_FLAG_LB3) != 0U)
2509 {
2510 if ((ier0_flags & DCMIPP_CSI_IT_LB3) != 0U)
2511 {
2512 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2513 {
2514 /* Disable IT */
2515 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_LB3);
2516 }
2517
2518 /* Clear Flag */
2519 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_LB3);
2520
2521 /* LineByte Callback */
2522 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2523 hdcmipp->LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER3);
2524 #else
2525 HAL_DCMIPP_CSI_LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER3);
2526 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2527 }
2528 }
2529
2530 if ((sr0flags & DCMIPP_CSI_FLAG_LB2) != 0U)
2531 {
2532 if ((ier0_flags & DCMIPP_CSI_IT_LB2) != 0U)
2533 {
2534 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2535 {
2536 /* Disable IT */
2537 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_LB2);
2538 }
2539
2540 /* Clear Flag */
2541 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_LB2);
2542
2543 /* LineByte Callback */
2544 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2545 hdcmipp->LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER2);
2546 #else
2547 HAL_DCMIPP_CSI_LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER2);
2548 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2549 }
2550 }
2551
2552 if ((sr0flags & DCMIPP_CSI_FLAG_LB1) != 0U)
2553 {
2554 if ((ier0_flags & DCMIPP_CSI_IT_LB1) != 0U)
2555 {
2556 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2557 {
2558 /* Disable IT */
2559 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_LB1);
2560 }
2561
2562 /* Clear Flag */
2563 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_LB1);
2564
2565 /* LineByte Callback */
2566 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2567 hdcmipp->LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER1);
2568 #else
2569 HAL_DCMIPP_CSI_LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER1);
2570 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2571 }
2572 }
2573
2574 if ((sr0flags & DCMIPP_CSI_FLAG_LB0) != 0U)
2575 {
2576 if ((ier0_flags & DCMIPP_CSI_IT_LB0) != 0U)
2577 {
2578 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2579 {
2580 /* Disable IT */
2581 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_LB0);
2582 }
2583
2584 /* Clear Flag */
2585 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_LB0);
2586
2587 /* LineByte Callback */
2588 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2589 hdcmipp->LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER0);
2590 #else
2591 HAL_DCMIPP_CSI_LineByteEventCallback(hdcmipp, DCMIPP_CSI_COUNTER0);
2592 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2593 }
2594 }
2595
2596 /*###############################
2597 End Of Frame
2598 ##############################*/
2599 if ((sr0flags & DCMIPP_CSI_FLAG_EOF3) != 0U)
2600 {
2601 if ((ier0_flags & DCMIPP_CSI_IT_EOF3) != 0U)
2602 {
2603 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2604 {
2605 /* Disable IT */
2606 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_EOF3);
2607 }
2608
2609 /* Clear Flag */
2610 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_EOF3);
2611
2612 /* Error Callback */
2613 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2614 hdcmipp->EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL3);
2615 #else
2616 HAL_DCMIPP_CSI_EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL3);
2617 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2618 }
2619 }
2620
2621 if ((sr0flags & DCMIPP_CSI_FLAG_EOF2) != 0U)
2622 {
2623 if ((ier0_flags & DCMIPP_CSI_IT_EOF2) != 0U)
2624 {
2625 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2626 {
2627 /* Disable IT */
2628 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_EOF2);
2629 }
2630
2631 /* Clear Flag */
2632 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_EOF2);
2633
2634 /* Error Callback */
2635 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2636 hdcmipp->EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL2);
2637 #else
2638 HAL_DCMIPP_CSI_EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL2);
2639 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2640 }
2641 }
2642
2643 if ((sr0flags & DCMIPP_CSI_FLAG_EOF1) != 0U)
2644 {
2645 if ((ier0_flags & DCMIPP_CSI_IT_EOF1) != 0U)
2646 {
2647 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2648 {
2649 /* Disable IT */
2650 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_EOF1);
2651 }
2652
2653 /* Clear Flag */
2654 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_EOF1);
2655
2656 /* Error Callback */
2657 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2658 hdcmipp->EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL1);
2659 #else
2660 HAL_DCMIPP_CSI_EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL1);
2661 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2662 }
2663 }
2664
2665 if ((sr0flags & DCMIPP_CSI_FLAG_EOF0) != 0U)
2666 {
2667 if ((ier0_flags & DCMIPP_CSI_IT_EOF0) != 0U)
2668 {
2669 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2670 {
2671 /* Disable IT */
2672 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_EOF0);
2673 }
2674
2675 /* Clear Flag */
2676 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_EOF0);
2677
2678 /* Error Callback */
2679 #if (USE_HAL_DCMIPP_CSIREGISTER_CALLBACKS == 1)
2680 hdcmipp->EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL0);
2681 #else
2682 HAL_DCMIPP_CSI_EndOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL0);
2683 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2684 }
2685 }
2686
2687 /*###############################
2688 Start Of Frame
2689 ##############################*/
2690 if ((sr0flags & DCMIPP_CSI_FLAG_SOF3) != 0U)
2691 {
2692 if ((ier0_flags & DCMIPP_CSI_IT_SOF3) != 0U)
2693 {
2694 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2695 {
2696 /* Disable IT */
2697 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_SOF3);
2698 }
2699
2700 /* Clear Flag */
2701 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_SOF3);
2702
2703 /* Error Callback */
2704 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2705 hdcmipp->StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL3);
2706 #else
2707 HAL_DCMIPP_CSI_StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL3);
2708 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2709 }
2710 }
2711
2712 if ((sr0flags & DCMIPP_CSI_FLAG_SOF2) != 0U)
2713 {
2714 if ((ier0_flags & DCMIPP_CSI_IT_SOF2) != 0U)
2715 {
2716 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2717 {
2718 /* Disable IT */
2719 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_SOF2);
2720 }
2721
2722 /* Clear Flag */
2723 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_SOF2);
2724
2725 /* Error Callback */
2726 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2727 hdcmipp->StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL2);
2728 #else
2729 HAL_DCMIPP_CSI_StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL2);
2730 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2731 }
2732 }
2733
2734 if ((sr0flags & DCMIPP_CSI_FLAG_SOF1) != 0U)
2735 {
2736 if ((ier0_flags & DCMIPP_CSI_IT_SOF1) != 0U)
2737 {
2738 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2739 {
2740 /* Disable IT */
2741 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_SOF1);
2742 }
2743
2744 /* Clear Flag */
2745 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_SOF1);
2746
2747 /* Error Callback */
2748 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2749 hdcmipp->StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL1);
2750 #else
2751 HAL_DCMIPP_CSI_StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL1);
2752 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2753 }
2754 }
2755
2756 if ((sr0flags & DCMIPP_CSI_FLAG_SOF0) != 0U)
2757 {
2758 if ((ier0_flags & DCMIPP_CSI_IT_SOF0) != 0U)
2759 {
2760 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2761 {
2762 /* Disable IT */
2763 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_SOF0);
2764 }
2765
2766 /* Clear Flag */
2767 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_SOF0);
2768
2769 /* Error Callback */
2770 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2771 hdcmipp->StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL0);
2772 #else
2773 HAL_DCMIPP_CSI_StartOfFrameEventCallback(hdcmipp, DCMIPP_VIRTUAL_CHANNEL0);
2774 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2775 }
2776 }
2777
2778 /*###############################
2779 Timer Interrupt
2780 ##############################*/
2781 if ((sr0flags & DCMIPP_CSI_FLAG_TIM3) != 0U)
2782 {
2783 if ((ier0_flags & DCMIPP_CSI_IT_TIM3) != 0U)
2784 {
2785 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2786 {
2787 /* Disable IT */
2788 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_TIM3);
2789 }
2790
2791 /* Clear Flag */
2792 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_TIM3);
2793
2794 /* Error Callback */
2795 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2796 hdcmipp->TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER3);
2797 #else
2798 HAL_DCMIPP_CSI_TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER3);
2799 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2800 }
2801 }
2802
2803 if ((sr0flags & DCMIPP_CSI_FLAG_TIM2) != 0U)
2804 {
2805 if ((ier0_flags & DCMIPP_CSI_IT_TIM2) != 0U)
2806 {
2807 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2808 {
2809 /* Disable IT */
2810 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_TIM2);
2811 }
2812
2813 /* Clear Flag */
2814 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_TIM2);
2815
2816 /* Error Callback */
2817 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2818 hdcmipp->TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER2);
2819 #else
2820 HAL_DCMIPP_CSI_TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER2);
2821 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2822 }
2823 }
2824
2825 if ((sr0flags & DCMIPP_CSI_FLAG_TIM1) != 0U)
2826 {
2827 if ((ier0_flags & DCMIPP_CSI_IT_TIM1) != 0U)
2828 {
2829 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2830 {
2831 /* Disable IT */
2832 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_TIM1);
2833 }
2834
2835 /* Clear Flag */
2836 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_TIM1);
2837
2838 /* Error Callback */
2839 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2840 hdcmipp->TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER1);
2841 #else
2842 HAL_DCMIPP_CSI_TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER1);
2843 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2844 }
2845 }
2846
2847 if ((sr0flags & DCMIPP_CSI_FLAG_TIM0) != 0U)
2848 {
2849 if ((ier0_flags & DCMIPP_CSI_IT_TIM0) != 0U)
2850 {
2851 if ((hdcmipp->Instance->P0FCTCR & DCMIPP_P0FCTCR_CPTMODE) == DCMIPP_MODE_SNAPSHOT)
2852 {
2853 /* Disable IT */
2854 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_TIM0);
2855 }
2856
2857 /* Clear Flag */
2858 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_TIM0);
2859
2860 /* Error Callback */
2861 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2862 hdcmipp->TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER0);
2863 #else
2864 HAL_DCMIPP_CSI_TimerCounterEventCallback(hdcmipp, DCMIPP_CSI_TIMER0);
2865 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2866 }
2867 }
2868
2869 /* Synchronization error */
2870 if ((sr0flags & DCMIPP_CSI_FLAG_SYNCERR) != 0U)
2871 {
2872 if ((ier0_flags & DCMIPP_CSI_IT_SYNCERR) != 0U)
2873 {
2874 /* Disable IT */
2875 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_SYNCERR);
2876
2877 /* Clear Flag */
2878 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_SYNCERR);
2879
2880 /* Update error code */
2881 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_SYNC;
2882
2883 /* Error Callback */
2884 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2885 hdcmipp->ErrorCallback(hdcmipp);
2886 #else
2887 HAL_DCMIPP_ErrorCallback(hdcmipp);
2888 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2889 }
2890 }
2891
2892 if ((sr0flags & DCMIPP_CSI_FLAG_WDERR) != 0U)
2893 {
2894 if ((ier0_flags & DCMIPP_CSI_IT_WDERR) != 0U)
2895 {
2896 /* Disable IT */
2897 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_WDERR);
2898
2899 /* Clear Flag */
2900 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_WDERR);
2901
2902 /* Update error code */
2903 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_WDG;
2904
2905 /* Error Callback */
2906 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2907 hdcmipp->ErrorCallback(hdcmipp);
2908 #else
2909 HAL_DCMIPP_ErrorCallback(hdcmipp);
2910 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2911 }
2912 }
2913
2914 if ((sr0flags & DCMIPP_CSI_FLAG_SPKTERR) != 0U)
2915 {
2916 if ((ier0_flags & DCMIPP_CSI_IT_SPKTERR) != 0U)
2917 {
2918 /* Disable IT */
2919 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_SPKTERR);
2920
2921 /* Clear Flag */
2922 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_SPKTERR);
2923
2924 /* Update error code */
2925 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_SPKT;
2926
2927 /* Error Callback */
2928 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2929 hdcmipp->ErrorCallback(hdcmipp);
2930 #else
2931 HAL_DCMIPP_ErrorCallback(hdcmipp);
2932 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2933 }
2934 }
2935
2936 if ((sr0flags & DCMIPP_CSI_FLAG_IDERR) != 0U)
2937 {
2938 if ((ier0_flags & DCMIPP_CSI_IT_IDERR) != 0U)
2939 {
2940 /* Disable IT */
2941 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_IDERR);
2942
2943 /* Clear Flag */
2944 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_IDERR);
2945
2946 /* Update error code */
2947 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_DATA_ID;
2948
2949 /* Error Callback */
2950 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2951 hdcmipp->ErrorCallback(hdcmipp);
2952 #else
2953 HAL_DCMIPP_ErrorCallback(hdcmipp);
2954 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2955 }
2956 }
2957
2958 if ((sr0flags & DCMIPP_CSI_FLAG_CECCERR) != 0U)
2959 {
2960 if ((ier0_flags & DCMIPP_CSI_IT_CECCERR) != 0U)
2961 {
2962 /* Disable IT */
2963 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_CECCERR);
2964
2965 /* Clear Flag */
2966 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_CECCERR);
2967
2968 /* Update error code */
2969 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_CECC;
2970
2971 /* Error Callback */
2972 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2973 hdcmipp->ErrorCallback(hdcmipp);
2974 #else
2975 HAL_DCMIPP_ErrorCallback(hdcmipp);
2976 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2977 }
2978 }
2979
2980 if ((sr0flags & DCMIPP_CSI_FLAG_ECCERR) != 0U)
2981 {
2982 if ((ier0_flags & DCMIPP_CSI_IT_ECCERR) != 0U)
2983 {
2984 /* Disable IT */
2985 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ECCERR);
2986
2987 /* Clear Flag */
2988 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_ECCERR);
2989
2990 /* Update error code */
2991 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_ECC;
2992
2993 /* Error Callback */
2994 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
2995 hdcmipp->ErrorCallback(hdcmipp);
2996 #else
2997 HAL_DCMIPP_ErrorCallback(hdcmipp);
2998 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
2999 }
3000 }
3001
3002 if ((sr0flags & DCMIPP_CSI_FLAG_CRCERR) != 0U)
3003 {
3004 if ((ier0_flags & DCMIPP_CSI_IT_CRCERR) != 0U)
3005 {
3006 /* Disable IT */
3007 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_CRCERR);
3008
3009 /* Clear Flag */
3010 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_CRCERR);
3011
3012 /* Update error code */
3013 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_CRC;
3014
3015 /* Error Callback */
3016 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
3017 hdcmipp->ErrorCallback(hdcmipp);
3018 #else
3019 HAL_DCMIPP_ErrorCallback(hdcmipp);
3020 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
3021 }
3022 }
3023
3024 /* Lane 0 Errors */
3025 /* Start Of Transmission error */
3026 if ((sr1flags & DCMIPP_CSI_FLAG_ESOTDL0) != 0U)
3027 {
3028 if ((ier1_flags & DCMIPP_CSI_IT_ESOTDL0) != 0U)
3029 {
3030 /* Disable IT */
3031 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ESOTDL0);
3032
3033 /* Clear Flag */
3034 __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_ESOTDL0);
3035
3036 /* Update error code */
3037 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_SOT;
3038
3039 /* Change CSI state */
3040 hdcmipp->State = HAL_DCMIPP_STATE_ERROR;
3041
3042 /* Error Callback */
3043 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
3044 hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
3045 #else
3046 HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
3047 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
3048 }
3049 }
3050
3051 /* Start Of Transmission Synchronisation error */
3052 if ((sr1flags & DCMIPP_CSI_FLAG_ESOTSYNCDL0) != 0U)
3053 {
3054 if ((ier1_flags & DCMIPP_CSI_IT_ESOTSYNCDL0) != 0U)
3055 {
3056 /* Disable IT */
3057 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ESOTSYNCDL0);
3058
3059 /* Clear Flag */
3060 __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_ESOTSYNCDL0);
3061
3062 /* Update error code */
3063 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_SOT_SYNC;
3064
3065 /* Change CSI state */
3066 hdcmipp->State = HAL_DCMIPP_STATE_ERROR;
3067
3068 /* Error Callback */
3069 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
3070 hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
3071 #else
3072 HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
3073 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
3074 }
3075 }
3076
3077 /* Escape entry error */
3078 if ((sr1flags & DCMIPP_CSI_FLAG_EESCDL0) != 0U)
3079 {
3080 if ((ier1_flags & DCMIPP_CSI_IT_EESCDL0) != 0U)
3081 {
3082 /* Disable IT */
3083 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_EESCDL0);
3084
3085 /* Clear Flag */
3086 __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_EESCDL0);
3087
3088 /* Update error code */
3089 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_DPHY_ESCAPE;
3090
3091 /* Error Callback */
3092 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
3093 hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
3094 #else
3095 HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
3096 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
3097 }
3098 }
3099
3100 /* Low power data transmission synchronization error */
3101 if ((sr1flags & DCMIPP_CSI_FLAG_ESYNCESCDL0) != 0U)
3102 {
3103 if ((ier1_flags & DCMIPP_CSI_IT_ESYNCESCDL0) != 0U)
3104 {
3105 /* Disable IT */
3106 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ESYNCESCDL0);
3107
3108 /* Clear Flag */
3109 __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_ESYNCESCDL0);
3110
3111 /* Update error code */
3112 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_DPHY_LP_SYNC;
3113
3114 /* Error Callback */
3115 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
3116 hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
3117 #else
3118 HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
3119 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
3120 }
3121 }
3122
3123 /* Error control on data line */
3124 if ((sr1flags & DCMIPP_CSI_FLAG_ECTRLDL0) != 0U)
3125 {
3126 if ((ier1_flags & DCMIPP_CSI_IT_ECTRLDL0) != 0U)
3127 {
3128 /* Disable IT */
3129 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ECTRLDL0);
3130
3131 /* Clear Flag */
3132 __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_ECTRLDL0);
3133
3134 /* Update error code */
3135 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_DPHY_CTRL;
3136
3137 /* Error Callback */
3138 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
3139 hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
3140 #else
3141 HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE0);
3142 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
3143 }
3144 }
3145
3146 /* Lane 1 Errors */
3147 /* Start Of Transmission error */
3148 if ((sr1flags & DCMIPP_CSI_FLAG_ESOTDL1) != 0U)
3149 {
3150 if ((ier1_flags & DCMIPP_CSI_IT_ESOTDL1) != 0U)
3151 {
3152 /* Disable IT */
3153 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ESOTDL1);
3154
3155 /* Clear Flag */
3156 __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_ESOTDL1);
3157
3158 /* Update error code */
3159 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_SOT;
3160
3161 /* Change CSI state */
3162 hdcmipp->State = HAL_DCMIPP_STATE_ERROR;
3163
3164 /* Error Callback */
3165 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
3166 hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
3167 #else
3168 HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
3169 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
3170 }
3171 }
3172
3173 /* Start Of Transmission Synchronisation error */
3174 if ((sr1flags & DCMIPP_CSI_FLAG_ESOTSYNCDL1) != 0U)
3175 {
3176 if ((ier1_flags & DCMIPP_CSI_IT_ESOTSYNCDL1) != 0U)
3177 {
3178 /* Disable IT */
3179 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ESOTSYNCDL1);
3180
3181 /* Clear Flag */
3182 __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_ESOTSYNCDL1);
3183
3184 /* Update error code */
3185 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_SOT_SYNC;
3186
3187 /* Change CSI state */
3188 hdcmipp->State = HAL_DCMIPP_STATE_ERROR;
3189
3190 /* Error Callback */
3191 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
3192 hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
3193 #else
3194 HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
3195 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
3196 }
3197 }
3198
3199 /* Escape entry error */
3200 if ((sr1flags & DCMIPP_CSI_FLAG_EESCDL1) != 0U)
3201 {
3202 if ((ier1_flags & DCMIPP_CSI_IT_EESCDL1) != 0U)
3203 {
3204 /* Disable IT */
3205 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_EESCDL1);
3206
3207 /* Clear Flag */
3208 __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_EESCDL1);
3209
3210 /* Update error code */
3211 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_DPHY_ESCAPE;
3212
3213 /* Error Callback */
3214 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
3215 hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
3216 #else
3217 HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
3218 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
3219 }
3220 }
3221
3222 /* Low power data transmission synchronization error */
3223 if ((sr1flags & DCMIPP_CSI_FLAG_ESYNCESCDL1) != 0U)
3224 {
3225 if ((ier1_flags & DCMIPP_CSI_IT_ESYNCESCDL1) != 0U)
3226 {
3227 /* Disable IT */
3228 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ESYNCESCDL1);
3229
3230 /* Clear Flag */
3231 __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_FLAG_ESYNCESCDL1);
3232
3233 /* Update error code */
3234 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_DPHY_LP_SYNC;
3235
3236 /* Error Callback */
3237 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
3238 hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
3239 #else
3240 HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
3241 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
3242 }
3243 }
3244
3245 /* Error control on data line */
3246 if ((sr1flags & DCMIPP_CSI_IT_ECTRLDL1) != 0U)
3247 {
3248 if ((ier1_flags & DCMIPP_CSI_IT_ECTRLDL1) != 0U)
3249 {
3250 /* Disable IT */
3251 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_ECTRLDL1);
3252
3253 /* Clear Flag */
3254 __HAL_DCMIPP_CSI_CLEAR_DPHY_FLAG(csi_instance, DCMIPP_CSI_IT_ECTRLDL1);
3255
3256 /* Update error code */
3257 hdcmipp->ErrorCode |= HAL_DCMIPP_CSI_ERROR_DPHY_CTRL;
3258
3259 /* Error Callback */
3260 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
3261 hdcmipp->LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
3262 #else
3263 HAL_DCMIPP_CSI_LineErrorCallback(hdcmipp, DCMIPP_CSI_DATA_LANE1);
3264 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
3265 }
3266 }
3267
3268 if ((sr0flags & DCMIPP_CSI_FLAG_SPKT) != 0U)
3269 {
3270 if ((ier0_flags & DCMIPP_CSI_IT_SPKT) != 0U)
3271 {
3272 /* Disable IT */
3273 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_SPKT);
3274
3275 /* Clear Flag */
3276 __HAL_DCMIPP_CSI_CLEAR_FLAG(csi_instance, DCMIPP_CSI_FLAG_SPKT);
3277
3278 /* Error Callback */
3279 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
3280 hdcmipp->ShortPacketDetectionEventCallback(hdcmipp);
3281 #else
3282 HAL_DCMIPP_CSI_ShortPacketDetectionEventCallback(hdcmipp);
3283 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
3284 }
3285 }
3286 }
3287 /**
3288 * @}
3289 */
3290
3291 /** @addtogroup DCMIPP_Callback_Functions Callback Functions
3292 * @{
3293 */
3294 /**
3295 * @brief Frame Event callback on the pipe
3296 * @param hdcmipp Pointer to DCMIPP handle
3297 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
3298 * @retval None
3299 */
HAL_DCMIPP_PIPE_FrameEventCallback(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)3300 __weak void HAL_DCMIPP_PIPE_FrameEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
3301 {
3302 /* NOTE : This function Should not be modified, when the callback is needed,
3303 the HAL_DCMIPP_FrameEventDumpPipeCallback could be implemented in the user file
3304 */
3305 /* Prevent unused argument(s) compilation warning */
3306 UNUSED(Pipe);
3307 UNUSED(hdcmipp);
3308 }
3309
3310 /**
3311 * @brief Vsync Event callback on pipe
3312 * @param hdcmipp Pointer to DCMIPP handle
3313 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
3314 * @retval None
3315 */
HAL_DCMIPP_PIPE_VsyncEventCallback(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)3316 __weak void HAL_DCMIPP_PIPE_VsyncEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
3317 {
3318 /* NOTE : This function Should not be modified, when the callback is needed,
3319 the HAL_DCMIPP_VsyncEventDumpPipeCallback could be implemented in the user file
3320 */
3321 /* Prevent unused argument(s) compilation warning */
3322 UNUSED(Pipe);
3323 UNUSED(hdcmipp);
3324 }
3325
3326
3327 /**
3328 * @brief Line Event callback on the pipe
3329 * @param hdcmipp Pointer to DCMIPP handle
3330 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
3331 * @retval None
3332 */
HAL_DCMIPP_PIPE_LineEventCallback(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)3333 __weak void HAL_DCMIPP_PIPE_LineEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
3334 {
3335 /* NOTE : This function Should not be modified, when the callback is needed,
3336 the HAL_DCMIPP_LineEventMainPipeCallback could be implemented in the user file
3337 */
3338 /* Prevent unused argument(s) compilation warning */
3339 UNUSED(Pipe);
3340 UNUSED(hdcmipp);
3341 }
3342
3343 /**
3344 * @brief Limit callback on the Pipe
3345 * @param hdcmipp Pointer to DCMIPP handle
3346 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
3347 * @retval None
3348 */
HAL_DCMIPP_PIPE_LimitEventCallback(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)3349 __weak void HAL_DCMIPP_PIPE_LimitEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
3350 {
3351 /* NOTE : This function Should not be modified, when the callback is needed,
3352 the HAL_DCMIPP_LimitEventDumpPipeCallback could be implemented in the user file
3353 */
3354 /* Prevent unused argument(s) compilation warning */
3355 UNUSED(Pipe);
3356 UNUSED(hdcmipp);
3357 }
3358
3359 /**
3360 * @brief Error callback on the pipe
3361 * @param hdcmipp Pointer to DCMIPP handle
3362 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
3363 * @retval None
3364 */
HAL_DCMIPP_PIPE_ErrorCallback(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)3365 __weak void HAL_DCMIPP_PIPE_ErrorCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
3366 {
3367 /* NOTE : This function Should not be modified, when the callback is needed,
3368 the HAL_DCMIPP_SyncErrorEventCallback could be implemented in the user file
3369 */
3370 /* Prevent unused argument(s) compilation warning */
3371 UNUSED(Pipe);
3372 UNUSED(hdcmipp);
3373 }
3374
3375
3376 /**
3377 * @brief Error callback on DCMIPP
3378 * @param hdcmipp Pointer to DCMIPP handle
3379 * @retval None
3380 */
HAL_DCMIPP_ErrorCallback(DCMIPP_HandleTypeDef * hdcmipp)3381 __weak void HAL_DCMIPP_ErrorCallback(DCMIPP_HandleTypeDef *hdcmipp)
3382 {
3383 /* NOTE : This function Should not be modified, when the callback is needed,
3384 the HAL_DCMIPP_ErrorCallback could be implemented in the user file
3385 */
3386 /* Prevent unused argument(s) compilation warning */
3387 UNUSED(hdcmipp);
3388 }
3389 /**
3390 * @}
3391 */
3392 /** @defgroup DCMIPP_CSI_Exported_Functions_Group3 Callback functions
3393 * @brief Callback (event / error) functions
3394 *
3395 @verbatim
3396 ===============================================================================
3397 ##### Callback functions #####
3398 ===============================================================================
3399 [..] This section provides function called upon:
3400 (+) events triggered by the CSI
3401 (+) errors triggered by the CSI
3402 @endverbatim
3403 * @{
3404 */
3405 /**
3406 * @brief Line Error callback on the Data Lane
3407 * @param hdcmipp Pointer to DCMIPP handle
3408 * @param DataLane
3409 * @retval None
3410 */
HAL_DCMIPP_CSI_LineErrorCallback(DCMIPP_HandleTypeDef * hdcmipp,uint32_t DataLane)3411 __weak void HAL_DCMIPP_CSI_LineErrorCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t DataLane)
3412 {
3413 /* NOTE : This function Should not be modified, when the callback is needed,
3414 the HAL_DCMIPP_CSI_LineErrorCallback could be implemented in the user file
3415 */
3416 UNUSED(DataLane);
3417 UNUSED(hdcmipp);
3418 }
3419 /**
3420 * @brief Clock Changer Fifo Full Event Callback
3421 * @param hdcmipp Pointer to DCMIPP handle
3422 * @retval None
3423 */
HAL_DCMIPP_CSI_ClockChangerFifoFullEventCallback(DCMIPP_HandleTypeDef * hdcmipp)3424 __weak void HAL_DCMIPP_CSI_ClockChangerFifoFullEventCallback(DCMIPP_HandleTypeDef *hdcmipp)
3425 {
3426 /* NOTE : This function Should not be modified, when the callback is needed,
3427 the HAL_DCMIPP_CSI_ClockChangerFifoFullEventCallback could be implemented in the user file
3428 */
3429 UNUSED(hdcmipp);
3430 }
3431 /**
3432 * @brief Short Packet Detection Event Callback
3433 * @param hdcmipp Pointer to DCMIPP handle
3434 * @retval None
3435 */
HAL_DCMIPP_CSI_ShortPacketDetectionEventCallback(DCMIPP_HandleTypeDef * hdcmipp)3436 __weak void HAL_DCMIPP_CSI_ShortPacketDetectionEventCallback(DCMIPP_HandleTypeDef *hdcmipp)
3437 {
3438 /* NOTE : This function Should not be modified, when the callback is needed,
3439 the HAL_DCMIPP_CSI_ShortPacketDetectionEventCallback could be implemented in the user file
3440 */
3441 UNUSED(hdcmipp);
3442 }
3443 /**
3444 * @brief End Of Frame Event Callback
3445 * @param hdcmipp Pointer to DCMIPP handle
3446 * @param VirtualChannel
3447 * @retval None
3448 */
HAL_DCMIPP_CSI_EndOfFrameEventCallback(DCMIPP_HandleTypeDef * hdcmipp,uint32_t VirtualChannel)3449 __weak void HAL_DCMIPP_CSI_EndOfFrameEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel)
3450 {
3451 /* NOTE : This function Should not be modified, when the callback is needed,
3452 the HAL_DCMIPP_CSI_EndOfFrameEventCallback could be implemented in the user file
3453 */
3454 UNUSED(hdcmipp);
3455 UNUSED(VirtualChannel);
3456 }
3457 /**
3458 * @brief Start Of Frame Event Callback
3459 * @param hdcmipp Pointer to DCMIPP handle
3460 * @param VirtualChannel
3461 * @retval None
3462 */
HAL_DCMIPP_CSI_StartOfFrameEventCallback(DCMIPP_HandleTypeDef * hdcmipp,uint32_t VirtualChannel)3463 __weak void HAL_DCMIPP_CSI_StartOfFrameEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel)
3464 {
3465 /* NOTE : This function Should not be modified, when the callback is needed,
3466 the HAL_DCMIPP_CSI_StartOfFrameEventCallback could be implemented in the user file
3467 */
3468 UNUSED(hdcmipp);
3469 UNUSED(VirtualChannel);
3470 }
3471 /**
3472 * @brief Timer Counter Event Callback
3473 * @param hdcmipp Pointer to DCMIPP handle
3474 * @param Timer
3475 * @retval None
3476 */
HAL_DCMIPP_CSI_TimerCounterEventCallback(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Timer)3477 __weak void HAL_DCMIPP_CSI_TimerCounterEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Timer)
3478 {
3479 /* NOTE : This function Should not be modified, when the callback is needed,
3480 the HAL_DCMIPP_CSI_TimerCounterEventCallback could be implemented in the user file
3481 */
3482 UNUSED(hdcmipp);
3483 UNUSED(Timer);
3484 }
3485 /**
3486 * @brief Line Byte Event Callback
3487 * @param hdcmipp Pointer to DCMIPP handle
3488 * @param Counter
3489 * @retval None
3490 */
HAL_DCMIPP_CSI_LineByteEventCallback(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Counter)3491 __weak void HAL_DCMIPP_CSI_LineByteEventCallback(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter)
3492 {
3493 /* NOTE : This function Should not be modified, when the callback is needed,
3494 the HAL_DCMIPP_CSI_LineByteEventCallback could be implemented in the user file
3495 */
3496 UNUSED(hdcmipp);
3497 UNUSED(Counter);
3498 }
3499 /**
3500 * @}
3501 */
3502
3503 /** @addtogroup DCMIPP_RegisterCallback_Functions Register Callback Functions
3504 * @{
3505 */
3506 #if (USE_HAL_DCMIPP_REGISTER_CALLBACKS == 1)
3507 /**
3508 * @brief Register a User DCMIPP Callback
3509 * To be used instead of the weak (surcharged) predefined callback
3510 * @param hdcmipp Pointer to DCMIPP handle
3511 * @param CallbackID ID of the callback to be registered
3512 * This parameter can be one of the following values:
3513 * @arg @ref HAL_DCMIPP_ERROR_CB_ID DCMIPP Error callback ID
3514 * @arg @ref HAL_DCMIPP_MSPINIT_CB_ID DCMIPP MspInit callback ID
3515 * @arg @ref HAL_DCMIPP_MSPDEINIT_CB_ID DCMIPP MspDeInit callback ID
3516 * @param pCallback pointer to the Callback function
3517 * @retval status
3518 */
HAL_DCMIPP_RegisterCallback(DCMIPP_HandleTypeDef * hdcmipp,HAL_DCMIPP_CallbackIDTypeDef CallbackID,pDCMIPP_CallbackTypeDef pCallback)3519 HAL_StatusTypeDef HAL_DCMIPP_RegisterCallback(DCMIPP_HandleTypeDef *hdcmipp, HAL_DCMIPP_CallbackIDTypeDef CallbackID,
3520 pDCMIPP_CallbackTypeDef pCallback)
3521 {
3522
3523 HAL_StatusTypeDef status = HAL_OK;
3524
3525 if (pCallback == NULL)
3526 {
3527 /* Update the error code */
3528 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
3529 return HAL_ERROR;
3530 }
3531
3532 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
3533 {
3534 switch (CallbackID)
3535 {
3536 case HAL_DCMIPP_MSPINIT_CB_ID :
3537 hdcmipp->MspInitCallback = pCallback;
3538 break;
3539
3540 case HAL_DCMIPP_MSPDEINIT_CB_ID :
3541 hdcmipp->MspDeInitCallback = pCallback;
3542 break;
3543
3544 case HAL_DCMIPP_ERROR_CB_ID :
3545 hdcmipp->ErrorCallback = pCallback;
3546 break;
3547
3548 default :
3549 /* Update the error code */
3550 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
3551 /* update return status */
3552 status = HAL_ERROR;
3553 break;
3554 }
3555 }
3556 else if (hdcmipp->State == HAL_DCMIPP_STATE_RESET)
3557 {
3558 switch (CallbackID)
3559 {
3560 case HAL_DCMIPP_MSPINIT_CB_ID :
3561 hdcmipp->MspInitCallback = pCallback;
3562 break;
3563
3564 case HAL_DCMIPP_MSPDEINIT_CB_ID :
3565 hdcmipp->MspDeInitCallback = pCallback;
3566 break;
3567
3568 default :
3569 /* Update the error code */
3570 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
3571 /* update return status */
3572 status = HAL_ERROR;
3573 break;
3574 }
3575 }
3576 else
3577 {
3578 /* Update the error code */
3579 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
3580 /* update return status */
3581 status = HAL_ERROR;
3582 }
3583
3584 return status;
3585 }
3586
3587 /**
3588 * @brief Unregister a User DCMIPP Callback
3589 * DCMIPP Callback is redirected to the weak (surcharged) predefined callback
3590 * @param hdcmipp Pointer to DCMIPP handle
3591 * @param CallbackID ID of the callback to be unregistered
3592 * This parameter can be one of the following values:
3593 * @arg @ref HAL_DCMIPP_ERROR_CB_ID DCMIPP Error callback ID
3594 * @arg @ref HAL_DCMIPP_MSPINIT_CB_ID DCMIPP MspInit callback ID
3595 * @arg @ref HAL_DCMIPP_MSPDEINIT_CB_ID DCMIPP MspDeInit callback ID
3596 * @retval status
3597 */
HAL_DCMIPP_UnRegisterCallback(DCMIPP_HandleTypeDef * hdcmipp,HAL_DCMIPP_CallbackIDTypeDef CallbackID)3598 HAL_StatusTypeDef HAL_DCMIPP_UnRegisterCallback(DCMIPP_HandleTypeDef *hdcmipp, HAL_DCMIPP_CallbackIDTypeDef CallbackID)
3599 {
3600 HAL_StatusTypeDef status = HAL_OK;
3601
3602 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
3603 {
3604 switch (CallbackID)
3605 {
3606 case HAL_DCMIPP_MSPINIT_CB_ID :
3607 hdcmipp->MspInitCallback = HAL_DCMIPP_MspInit; /* Legacy weak (surcharged) Msp Init */
3608 break;
3609
3610 case HAL_DCMIPP_MSPDEINIT_CB_ID :
3611 hdcmipp->MspDeInitCallback = HAL_DCMIPP_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
3612 break;
3613
3614 default :
3615 /* Update the error code */
3616 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
3617 /* update return status */
3618 status = HAL_ERROR;
3619 break;
3620 }
3621 }
3622 else if (hdcmipp->State == HAL_DCMIPP_STATE_RESET)
3623 {
3624 switch (CallbackID)
3625 {
3626 case HAL_DCMIPP_MSPINIT_CB_ID :
3627 hdcmipp->MspInitCallback = HAL_DCMIPP_MspInit; /* Legacy weak (surcharged) Msp Init */
3628 break;
3629
3630 case HAL_DCMIPP_MSPDEINIT_CB_ID :
3631 hdcmipp->MspDeInitCallback = HAL_DCMIPP_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
3632 break;
3633
3634 default :
3635 /* Update the error code */
3636 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
3637 /* update return status */
3638 status = HAL_ERROR;
3639 break;
3640 }
3641 }
3642 else
3643 {
3644 /* Update the error code */
3645 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
3646 /* update return status */
3647 status = HAL_ERROR;
3648 }
3649
3650 return status;
3651 }
3652
3653 /**
3654 * @brief Register a User DCMIPP Pipe Callback
3655 * To be used instead of the weak (surcharged) predefined callback
3656 * @param hdcmipp Pointer to DCMIPP handle
3657 * @param CallbackID ID of the callback to be registered
3658 * This parameter can be one of the following values:
3659 * @arg @ref HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID DCMIPP Pipe Frame event callback ID
3660 * @arg @ref HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID DCMIPP Pipe Vsync event callback ID
3661 * @arg @ref HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID DCMIPP Pipe Line event callback ID
3662 * @arg @ref HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID DCMIPP Pipe Limit event callback ID
3663 * @arg @ref HAL_DCMIPP_PIPE_ERROR_CB_ID DCMIPP Pipe Error callback ID
3664 * @param pCallback pointer to the Pipe Callback function
3665 * @retval status
3666 */
HAL_DCMIPP_PIPE_RegisterCallback(DCMIPP_HandleTypeDef * hdcmipp,HAL_DCMIPP_PIPE_CallbackIDTypeDef CallbackID,pDCMIPP_PIPE_CallbackTypeDef pCallback)3667 HAL_StatusTypeDef HAL_DCMIPP_PIPE_RegisterCallback(DCMIPP_HandleTypeDef *hdcmipp,
3668 HAL_DCMIPP_PIPE_CallbackIDTypeDef CallbackID,
3669 pDCMIPP_PIPE_CallbackTypeDef pCallback)
3670 {
3671 HAL_StatusTypeDef status = HAL_OK;
3672
3673 if (pCallback == NULL)
3674 {
3675 /* Update the error code */
3676 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
3677 return HAL_ERROR;
3678 }
3679
3680 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
3681 {
3682 switch (CallbackID)
3683 {
3684 case HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID :
3685 hdcmipp->PIPE_FrameEventCallback = pCallback;
3686 break;
3687
3688 case HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID :
3689 hdcmipp->PIPE_VsyncEventCallback = pCallback;
3690 break;
3691
3692 case HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID :
3693 hdcmipp->PIPE_LineEventCallback = pCallback;
3694 break;
3695
3696 case HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID :
3697 hdcmipp->PIPE_LimitEventCallback = pCallback;
3698 break;
3699
3700 case HAL_DCMIPP_PIPE_ERROR_CB_ID :
3701 hdcmipp->PIPE_ErrorCallback = pCallback;
3702 break;
3703
3704 default :
3705 /* Update the error code */
3706 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
3707 /* update return status */
3708 status = HAL_ERROR;
3709 break;
3710 }
3711 }
3712 else
3713 {
3714 /* Update the error code */
3715 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
3716 /* update return status */
3717 status = HAL_ERROR;
3718 }
3719
3720 return status;
3721 }
3722
3723 /**
3724 * @brief UnRegister a User DCMIPP Pipe Callback
3725 * DCMIPP Callback is redirected to the weak (surcharged) predefined callback
3726 * @param hdcmipp Pointer to DCMIPP handle
3727 * @param CallbackID ID of the callback to be unregistered
3728 * This parameter can be one of the following values:
3729 * @arg @ref HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID DCMIPP Pipe Frame event callback ID
3730 * @arg @ref HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID DCMIPP Pipe Vsync event callback ID
3731 * @arg @ref HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID DCMIPP Pipe Line event callback ID
3732 * @arg @ref HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID DCMIPP Pipe Limit event callback ID
3733 * @arg @ref HAL_DCMIPP_PIPE_ERROR_CB_ID DCMIPP Pipe Error callback ID
3734 * @retval status
3735 */
HAL_DCMIPP_PIPE_UnRegisterCallback(DCMIPP_HandleTypeDef * hdcmipp,HAL_DCMIPP_PIPE_CallbackIDTypeDef CallbackID)3736 HAL_StatusTypeDef HAL_DCMIPP_PIPE_UnRegisterCallback(DCMIPP_HandleTypeDef *hdcmipp,
3737 HAL_DCMIPP_PIPE_CallbackIDTypeDef CallbackID)
3738 {
3739 HAL_StatusTypeDef status = HAL_OK;
3740
3741 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
3742 {
3743 switch (CallbackID)
3744 {
3745 case HAL_DCMIPP_PIPE_FRAME_EVENT_CB_ID :
3746 hdcmipp->PIPE_FrameEventCallback = HAL_DCMIPP_PIPE_FrameEventCallback;
3747 break;
3748
3749 case HAL_DCMIPP_PIPE_VSYNC_EVENT_CB_ID :
3750 hdcmipp->PIPE_VsyncEventCallback = HAL_DCMIPP_PIPE_VsyncEventCallback;
3751 break;
3752
3753 case HAL_DCMIPP_PIPE_LINE_EVENT_CB_ID :
3754 hdcmipp->PIPE_LineEventCallback = HAL_DCMIPP_PIPE_LineEventCallback;
3755 break;
3756
3757 case HAL_DCMIPP_PIPE_LIMIT_EVENT_CB_ID :
3758 hdcmipp->PIPE_LimitEventCallback = HAL_DCMIPP_PIPE_LimitEventCallback;
3759 break;
3760
3761 case HAL_DCMIPP_PIPE_ERROR_CB_ID :
3762 hdcmipp->PIPE_ErrorCallback = HAL_DCMIPP_PIPE_ErrorCallback;
3763 break;
3764
3765 default :
3766 /* Update the error code */
3767 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
3768 /* update return status */
3769 status = HAL_ERROR;
3770 break;
3771 }
3772 }
3773 else
3774 {
3775 /* Update the error code */
3776 hdcmipp->ErrorCode |= HAL_DCMIPP_ERROR_INVALID_CALLBACK;
3777 /* update return status */
3778 status = HAL_ERROR;
3779 }
3780
3781 return status;
3782 }
3783 #endif /* USE_HAL_DCMIPP_REGISTER_CALLBACKS */
3784 /**
3785 * @}
3786 */
3787 /**
3788 * @}
3789 */
3790 /**
3791 * The DCMIPP pipe peripheral can be configured using a set of functions that allow
3792 *
3793 */
3794
3795 /**
3796 * Crop Feature : Allows setting and managing the crop coordinates to capture a specific area of the image.
3797 * - HAL_DCMIPP_PIPE_SetCropConfig() : Configure the DCMI crop coordinates.
3798 * - HAL_DCMIPP_PIPE_EnableCrop() : Enable the cropping feature.
3799 * - HAL_DCMIPP_PIPE_DisableCrop() : Disable the cropping feature.
3800 */
3801 /** @defgroup DCMIPP_Crop_Functions DCMIPP Crop Functions
3802 * @{
3803 */
3804 /**
3805 * @brief Configures cropping for the specified DCMIPP pipe according to the user parameters
3806 * @param hdcmipp Pointer to DCMIPP handle
3807 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
3808 * @param pCropConfig pointer to DCMIPP_CropConfTypeDef structure that contains
3809 * the configuration information for Crop.
3810 * @retval HAL status
3811 */
HAL_DCMIPP_PIPE_SetCropConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_CropConfTypeDef * pCropConfig)3812 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetCropConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
3813 const DCMIPP_CropConfTypeDef *pCropConfig)
3814 {
3815 uint32_t tmp;
3816
3817 /* Check handle validity */
3818 if ((hdcmipp == NULL) || (pCropConfig == NULL))
3819 {
3820 return HAL_ERROR;
3821 }
3822
3823 assert_param(IS_DCMIPP_PIPE(Pipe));
3824 assert_param(IS_DCMIPP_PIPE_CROP_AREA(pCropConfig->PipeArea));
3825 assert_param(IS_DCMIPP_PIPE_CROP_HSTART(pCropConfig->HStart));
3826 assert_param(IS_DCMIPP_PIPE_CROP_HSIZE(pCropConfig->HSize));
3827 assert_param(IS_DCMIPP_PIPE_CROP_VSIZE(pCropConfig->VSize));
3828 assert_param(IS_DCMIPP_PIPE_CROP_VSTART(pCropConfig->VStart));
3829
3830 /* Check the DCMIPP State */
3831 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
3832 {
3833
3834 if (Pipe == DCMIPP_PIPE0)
3835 {
3836 tmp = READ_REG(hdcmipp->Instance->PRCR);
3837
3838 /* Verify for parallel mode with jpeg format , no Line Crop enable */
3839 if (((tmp & DCMIPP_PRCR_ENABLE) == DCMIPP_PRCR_ENABLE) && ((tmp & DCMIPP_PRCR_FORMAT) == DCMIPP_FORMAT_BYTE))
3840 {
3841 return HAL_ERROR;
3842 }
3843 else
3844 {
3845 /* Set Cropping horizontal and vertical start for Pipe0 */
3846 MODIFY_REG(hdcmipp->Instance->P0SCSTR, DCMIPP_P0SCSTR_HSTART | DCMIPP_P0SCSTR_VSTART,
3847 (pCropConfig->HStart << DCMIPP_P0SCSTR_HSTART_Pos) |
3848 (pCropConfig->VStart << DCMIPP_P0SCSTR_VSTART_Pos));
3849
3850 /* Set Cropping horizontal and vertical width for Pipe0 */
3851 /* Set crop Area (Inner or outer) for Pipe0 */
3852 MODIFY_REG(hdcmipp->Instance->P0SCSZR, DCMIPP_P0SCSZR_HSIZE | DCMIPP_P0SCSZR_VSIZE | DCMIPP_P0SCSZR_POSNEG,
3853 (pCropConfig->HSize << DCMIPP_P0SCSZR_HSIZE_Pos) | (pCropConfig->VSize << DCMIPP_P0SCSZR_VSIZE_Pos) |
3854 (pCropConfig->PipeArea));
3855 }
3856 }
3857 else if (Pipe == DCMIPP_PIPE1)
3858 {
3859 /* Set Cropping horizontal and vertical start for Pipe1 */
3860 MODIFY_REG(hdcmipp->Instance->P1CRSTR, DCMIPP_P1CRSTR_HSTART | DCMIPP_P1CRSTR_VSTART,
3861 (pCropConfig->HStart << DCMIPP_P1CRSTR_HSTART_Pos) | \
3862 (pCropConfig->VStart << DCMIPP_P1CRSTR_VSTART_Pos));
3863
3864 /* Set Cropping horizontal and vertical width for Pipe1 */
3865 MODIFY_REG(hdcmipp->Instance->P1CRSZR, DCMIPP_P1CRSZR_HSIZE | DCMIPP_P1CRSZR_VSIZE,
3866 (pCropConfig->HSize << DCMIPP_P1CRSZR_HSIZE_Pos) | (pCropConfig->VSize << DCMIPP_P1CRSZR_VSIZE_Pos));
3867 }
3868 else if (Pipe == DCMIPP_PIPE2)
3869 {
3870 /* Set Cropping horizontal and vertical start for Pipe2 */
3871 MODIFY_REG(hdcmipp->Instance->P2CRSTR, DCMIPP_P2CRSTR_HSTART | DCMIPP_P2CRSTR_VSTART,
3872 (pCropConfig->HStart << DCMIPP_P2CRSTR_HSTART_Pos) | \
3873 (pCropConfig->VStart << DCMIPP_P2CRSTR_VSTART_Pos));
3874
3875 /* Set Cropping horizontal and vertical width for Pipe2 */
3876 MODIFY_REG(hdcmipp->Instance->P2CRSZR, DCMIPP_P2CRSZR_HSIZE | DCMIPP_P2CRSZR_VSIZE,
3877 (pCropConfig->HSize << DCMIPP_P2CRSZR_HSIZE_Pos) | (pCropConfig->VSize << DCMIPP_P2CRSZR_VSIZE_Pos));
3878 }
3879 else
3880 {
3881 return HAL_ERROR;
3882 }
3883 }
3884 else
3885 {
3886 return HAL_ERROR;
3887 }
3888
3889 return HAL_OK;
3890 }
3891
3892 /**
3893 * @brief Enables the cropping for the specified DCMIPP pipe.
3894 * @param hdcmipp Pointer to DCMIPP handle
3895 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
3896 * @note Cropping cannot be enabled in parallel mode with JPEG Format
3897 * @retval HAL status
3898 */
HAL_DCMIPP_PIPE_EnableCrop(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)3899 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableCrop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
3900 {
3901 uint32_t tmp;
3902
3903 assert_param(IS_DCMIPP_PIPE(Pipe));
3904
3905 /* Check handle validity */
3906 if (hdcmipp == NULL)
3907 {
3908 return HAL_ERROR;
3909 }
3910
3911 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
3912 {
3913 if (Pipe == DCMIPP_PIPE0)
3914 {
3915 /* This bit must be kept cleared if the input format is JPEG */
3916 /* Verify for parallel mode with jpeg format , no Line Crop enable */
3917
3918 tmp = READ_REG(hdcmipp->Instance->PRCR);
3919
3920 if (((tmp & DCMIPP_PRCR_ENABLE) == DCMIPP_PRCR_ENABLE) && ((tmp & DCMIPP_PRCR_FORMAT) == DCMIPP_FORMAT_BYTE))
3921 {
3922 return HAL_ERROR;
3923 }
3924 else
3925 {
3926 SET_BIT(hdcmipp->Instance->P0SCSZR, DCMIPP_P0SCSZR_ENABLE);
3927 }
3928 }
3929 else if (Pipe == DCMIPP_PIPE1)
3930 {
3931 /* Verify Crop line is disabled */
3932 if (hdcmipp->Instance->P1SRCR != DCMIPP_P1SRCR_CROPEN)
3933 {
3934 SET_BIT(hdcmipp->Instance->P1CRSZR, DCMIPP_P1CRSZR_ENABLE);
3935 }
3936 else
3937 {
3938 return HAL_ERROR;
3939 }
3940 }
3941 else if (Pipe == DCMIPP_PIPE2)
3942 {
3943 SET_BIT(hdcmipp->Instance->P2CRSZR, DCMIPP_P2CRSZR_ENABLE);
3944 }
3945 else
3946 {
3947 return HAL_ERROR;
3948 }
3949 }
3950 else
3951 {
3952 return HAL_ERROR;
3953 }
3954
3955 return HAL_OK;
3956 }
3957
3958 /**
3959 * @brief Disable the cropping for the specified DCMIPP pipe.
3960 * @param hdcmipp Pointer to DCMIPP handle
3961 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
3962 * @retval HAL status
3963 */
HAL_DCMIPP_PIPE_DisableCrop(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)3964 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableCrop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
3965 {
3966 assert_param(IS_DCMIPP_PIPE(Pipe));
3967
3968 /* Check handle validity */
3969 if (hdcmipp == NULL)
3970 {
3971 return HAL_ERROR;
3972 }
3973
3974 if (Pipe == DCMIPP_PIPE0)
3975 {
3976 CLEAR_BIT(hdcmipp->Instance->P0SCSZR, DCMIPP_P0SCSZR_ENABLE);
3977 }
3978 else if (Pipe == DCMIPP_PIPE1)
3979 {
3980 CLEAR_BIT(hdcmipp->Instance->P1CRSZR, DCMIPP_P1CRSZR_ENABLE);
3981 }
3982 else if (Pipe == DCMIPP_PIPE2)
3983 {
3984 CLEAR_BIT(hdcmipp->Instance->P2CRSZR, DCMIPP_P2CRSZR_ENABLE);
3985 }
3986 else
3987 {
3988 return HAL_ERROR;
3989 }
3990
3991 return HAL_OK;
3992 }
3993 /**
3994 * @}
3995 */
3996
3997 /** @defgroup DCMIPP_Decimation_Functions DCMIPP Decimation Functions
3998 * @{
3999 */
4000 /**
4001 * Decimation Feature
4002 * - Horizontal resolution :
4003 * - HAL_DCMIPP_PIPE_SetBytesDecimationConfig() : Set the bytes decimation.
4004 * - Vertical resolution :
4005 * - HAL_DCMIPP_PIPE_SetLinesDecimationConfig() : Set the lines decimation.
4006 */
4007 /**
4008 * @brief Configure the Bytes decimation for the selected Pipe.
4009 * @param hdcmipp Pointer to DCMIPP handle
4010 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4011 * @param SelectStart can a be value from @ref DCMIPP_Byte_Start_Mode
4012 * @param SelectMode can be a value from @ref DCMIPP_Byte_Select_Mode
4013 * @retval HAL status
4014 */
HAL_DCMIPP_PIPE_SetBytesDecimationConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t SelectStart,uint32_t SelectMode)4015 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetBytesDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
4016 uint32_t SelectStart, uint32_t SelectMode)
4017 {
4018 uint32_t tmp;
4019
4020 assert_param(IS_DCMIPP_PIPE(Pipe));
4021 assert_param(IS_DCMIPP_BYTE_SELECT_START(SelectStart));
4022 assert_param(IS_DCMIPP_BYTE_SELECT_MODE(SelectMode));
4023
4024 /* Check handle validity */
4025 if (hdcmipp == NULL)
4026 {
4027 return HAL_ERROR;
4028 }
4029
4030 if (Pipe == DCMIPP_PIPE0)
4031 {
4032 /* OEBS : This bit works in conjunction with BSM field (BSM != 00) */
4033 /* Modes 10 and 11 work only with EDM [2:0] = 000 into the DCMIPP_PRCR */
4034 tmp = (hdcmipp->Instance->PRCR & DCMIPP_PRCR_EDM);
4035
4036 if (((SelectStart == DCMIPP_OEBS_EVEN) && (SelectMode > DCMIPP_BSM_ALL)) || \
4037 ((SelectMode > DCMIPP_BSM_DATA_OUT_2) && (tmp != DCMIPP_INTERFACE_8BITS)))
4038 {
4039 return HAL_ERROR;
4040 }
4041 else
4042 {
4043 /* Set Bytes select Start and Bytes select Mode */
4044 MODIFY_REG(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_BSM | DCMIPP_P0PPCR_OEBS, (SelectStart | SelectMode));
4045 }
4046 }
4047 else
4048 {
4049 return HAL_ERROR;
4050 }
4051
4052 return HAL_OK;
4053 }
4054
4055 /**
4056 * @brief Configure the Lines decimation for the selected Pipe.
4057 * @param hdcmipp Pointer to DCMIPP handle
4058 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4059 * @param SelectStart can a be value from @ref DCMIPP_Line_Start_Mode
4060 * @param SelectMode can be a value from @ref DCMIPP_Line_Select_Mode
4061 * @retval HAL status
4062 */
HAL_DCMIPP_PIPE_SetLinesDecimationConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t SelectStart,uint32_t SelectMode)4063 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetLinesDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
4064 uint32_t SelectStart, uint32_t SelectMode)
4065 {
4066 assert_param(IS_DCMIPP_PIPE(Pipe));
4067 assert_param(IS_DCMIPP_LINE_SELECT_MODE(SelectMode));
4068 assert_param(IS_DCMIPP_LINE_SELECT_START(SelectStart));
4069
4070 /* Check handle validity */
4071 if (hdcmipp == NULL)
4072 {
4073 return HAL_ERROR;
4074 }
4075
4076 if (Pipe == DCMIPP_PIPE0)
4077 {
4078 /* This bit works in conjunction with LSM field (LSM = 1) */
4079 if ((SelectStart == DCMIPP_OELS_EVEN) && (SelectMode == DCMIPP_LSM_ALTERNATE_2))
4080 {
4081 return HAL_ERROR;
4082 }
4083 else
4084 {
4085 /* Set Lines select Start and Bytes select Mode */
4086 MODIFY_REG(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_LSM | DCMIPP_P0PPCR_OELS, (SelectStart | SelectMode));
4087 }
4088 }
4089 else
4090 {
4091 return HAL_ERROR;
4092 }
4093 return HAL_OK;
4094 }
4095 /**
4096 * @}
4097 */
4098
4099 /** @defgroup DCMIPP_LimitEvent_Functions DCMIPP Limit Event Functions
4100 * @{
4101 */
4102 /**
4103 * @brief Define the Data dump limit for the selected Pipe.
4104 * @param hdcmipp Pointer to DCMIPP handle
4105 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4106 * @param Limit Data dump Limit.
4107 * @retval HAL status
4108 */
HAL_DCMIPP_PIPE_EnableLimitEvent(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t Limit)4109 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLimitEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Limit)
4110 {
4111 assert_param(IS_DCMIPP_PIPE(Pipe));
4112 assert_param(IS_DCMIPP_DATA_LIMIT(Limit));
4113
4114 /* Check Parameters */
4115 if (hdcmipp == NULL)
4116 {
4117 return HAL_ERROR;
4118 }
4119
4120 if (Pipe == DCMIPP_PIPE0)
4121 {
4122 /* Set and enable data limit on Pipe 0 */
4123 WRITE_REG(hdcmipp->Instance->P0DCLMTR, (Limit << DCMIPP_P0DCLMTR_LIMIT_Pos) | DCMIPP_P0DCLMTR_ENABLE);
4124
4125 /* Enable Limit Interrupt for pipe0 */
4126 __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LIMIT);
4127 }
4128 else
4129 {
4130 return HAL_ERROR;
4131 }
4132
4133 return HAL_OK;
4134 }
4135
4136 /**
4137 * @brief Disable the the Limit interrupt.
4138 * @param hdcmipp Pointer to DCMIPP handle
4139 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4140 * @retval HAL status
4141 */
HAL_DCMIPP_PIPE_DisableLimitEvent(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4142 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLimitEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4143 {
4144 assert_param(IS_DCMIPP_PIPE(Pipe));
4145
4146 /* Check Parameters */
4147 if (hdcmipp == NULL)
4148 {
4149 return HAL_ERROR;
4150 }
4151
4152 if (Pipe == DCMIPP_PIPE0)
4153 {
4154 /* Disable data limit on Pipe 0 */
4155 CLEAR_BIT(hdcmipp->Instance->P0DCLMTR, DCMIPP_P0DCLMTR_ENABLE);
4156
4157 /* Disable Limit Interrupt for pipe0 */
4158 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LIMIT);
4159 }
4160 else
4161 {
4162 return HAL_ERROR;
4163 }
4164
4165 return HAL_OK;
4166 }
4167
4168 /**
4169 * @brief Configures the ISP decimation for the specified pipe according to the used parameters.
4170 * @param hdcmipp Pointer to DCMIPP handle
4171 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4172 * @param pDecConfig pointer to DCMIPP_DecimationConfTypeDef structure that contains the decimation information
4173 * @retval HAL status
4174 */
HAL_DCMIPP_PIPE_SetISPDecimationConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_DecimationConfTypeDef * pDecConfig)4175 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
4176 const DCMIPP_DecimationConfTypeDef *pDecConfig)
4177 {
4178 assert_param(IS_DCMIPP_PIPE(Pipe));
4179 assert_param(IS_DCMIPP_VRATIO(pDecConfig->VRatio));
4180 assert_param(IS_DCMIPP_HRATIO(pDecConfig->HRatio));
4181
4182 /* Check handle validity */
4183 if ((hdcmipp == NULL) || (pDecConfig == NULL))
4184 {
4185 return HAL_ERROR;
4186 }
4187
4188 /* Set Decimation Type , Vertical and Horizontal Ratio */
4189 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
4190 {
4191 if (Pipe == DCMIPP_PIPE1)
4192 {
4193 MODIFY_REG(hdcmipp->Instance->P1DECR, DCMIPP_P1DECR_VDEC | DCMIPP_P1DECR_HDEC,
4194 (pDecConfig->VRatio | pDecConfig->HRatio));
4195 }
4196 else
4197 {
4198 return HAL_ERROR;
4199 }
4200 }
4201 else
4202 {
4203 return HAL_ERROR;
4204 }
4205
4206
4207 return HAL_OK;
4208 }
4209
4210 /**
4211 * @brief Enable the ISP decimation for the specified pipe
4212 * @param hdcmipp Pointer to DCMIPP handle
4213 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4214 * @retval HAL status
4215 */
HAL_DCMIPP_PIPE_EnableISPDecimation(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4216 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPDecimation(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4217 {
4218 assert_param(IS_DCMIPP_PIPE(Pipe));
4219
4220 /* Check handle validity */
4221 if (hdcmipp == NULL)
4222 {
4223 return HAL_ERROR;
4224 }
4225
4226 /* Enable decimation */
4227 if (Pipe == DCMIPP_PIPE1)
4228 {
4229 SET_BIT(hdcmipp->Instance->P1DECR, DCMIPP_P1DECR_ENABLE);
4230 }
4231 else
4232 {
4233 return HAL_ERROR;
4234 }
4235
4236 return HAL_OK;
4237 }
4238
4239 /**
4240 * @brief Disable the ISP decimation for the specified pipe
4241 * @param hdcmipp Pointer to DCMIPP handle
4242 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4243 * @retval HAL status
4244 */
HAL_DCMIPP_PIPE_DisableISPDecimation(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4245 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPDecimation(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4246 {
4247 assert_param(IS_DCMIPP_PIPE(Pipe));
4248
4249 /* Check handle validity */
4250 if (hdcmipp == NULL)
4251 {
4252 return HAL_ERROR;
4253 }
4254
4255 /* Enable decimation */
4256 if (Pipe == DCMIPP_PIPE1)
4257 {
4258 CLEAR_BIT(hdcmipp->Instance->P1DECR, DCMIPP_P1DECR_ENABLE);
4259 }
4260 else
4261 {
4262 return HAL_ERROR;
4263 }
4264
4265 return HAL_OK;
4266 }
4267
4268 /**
4269 * @brief Configures the decimation for the specified pipe according to the used parameters.
4270 * @param hdcmipp Pointer to DCMIPP handle
4271 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4272 * @param pDecConfig pointer to DCMIPP_DecimationConfTypeDef structure that contains the decimation information
4273 * @retval HAL status
4274 */
HAL_DCMIPP_PIPE_SetDecimationConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_DecimationConfTypeDef * pDecConfig)4275 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetDecimationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
4276 const DCMIPP_DecimationConfTypeDef *pDecConfig)
4277 {
4278 /* Check handle validity */
4279 if (hdcmipp == NULL)
4280 {
4281 return HAL_ERROR;
4282 }
4283
4284 assert_param(IS_DCMIPP_PIPE(Pipe));
4285 assert_param(IS_DCMIPP_VRATIO(pDecConfig->VRatio));
4286 assert_param(IS_DCMIPP_HRATIO(pDecConfig->HRatio));
4287
4288 /* Check DCMIPP State */
4289 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
4290 {
4291 /* Set Decimation Type , Vertical and Horizontal Ratio */
4292 if (Pipe == DCMIPP_PIPE1)
4293 {
4294 MODIFY_REG(hdcmipp->Instance->P1DCCR, DCMIPP_P1DCCR_VDEC | DCMIPP_P1DCCR_HDEC,
4295 (pDecConfig->VRatio | pDecConfig->HRatio));
4296 }
4297 else if (Pipe == DCMIPP_PIPE2)
4298 {
4299 MODIFY_REG(hdcmipp->Instance->P2DCCR, DCMIPP_P2DCCR_VDEC | DCMIPP_P2DCCR_HDEC,
4300 (pDecConfig->VRatio | pDecConfig->HRatio));
4301 }
4302 else
4303 {
4304 return HAL_ERROR;
4305 }
4306 }
4307 else
4308 {
4309 return HAL_ERROR;
4310 }
4311
4312 return HAL_OK;
4313 }
4314
4315 /**
4316 * @brief Enable the DCMIPP Decimation for the specified pipe.
4317 * @param hdcmipp Pointer to DCMIPP handle
4318 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4319 * @retval HAL status
4320 */
HAL_DCMIPP_PIPE_EnableDecimation(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4321 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableDecimation(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4322 {
4323 /* Check handle validity */
4324 if (hdcmipp == NULL)
4325 {
4326 return HAL_ERROR;
4327 }
4328
4329 assert_param(IS_DCMIPP_PIPE(Pipe));
4330
4331 /* Enable decimation */
4332 if (Pipe == DCMIPP_PIPE1)
4333 {
4334 SET_BIT(hdcmipp->Instance->P1DCCR, DCMIPP_P1DCCR_ENABLE);
4335 }
4336 else if (Pipe == DCMIPP_PIPE2)
4337 {
4338 SET_BIT(hdcmipp->Instance->P2DCCR, DCMIPP_P2DCCR_ENABLE);
4339 }
4340 else
4341 {
4342 return HAL_ERROR;
4343 }
4344
4345 return HAL_OK;
4346 }
4347
4348 /**
4349 * @brief Disable the DCMIPP Decimation for the specified pipe.
4350 * @param hdcmipp Pointer to DCMIPP handle
4351 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4352 * @retval HAL status
4353 */
HAL_DCMIPP_PIPE_DisableDecimation(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4354 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableDecimation(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4355 {
4356 /* Check handle validity */
4357 if (hdcmipp == NULL)
4358 {
4359 return HAL_ERROR;
4360 }
4361
4362 assert_param(IS_DCMIPP_PIPE(Pipe));
4363
4364 /* Enable decimation */
4365 if (Pipe == DCMIPP_PIPE1)
4366 {
4367 CLEAR_BIT(hdcmipp->Instance->P1DCCR, DCMIPP_P1DCCR_ENABLE);
4368 }
4369 else if (Pipe == DCMIPP_PIPE2)
4370 {
4371 CLEAR_BIT(hdcmipp->Instance->P2DCCR, DCMIPP_P2DCCR_ENABLE);
4372 }
4373 else
4374 {
4375 return HAL_ERROR;
4376 }
4377
4378 return HAL_OK;
4379 }
4380
4381 /**
4382 * Downsize Feature :
4383 * - HAL_DCMIPP_PIPE_SetDownsizeConfig() : Set the Downsize configuration.
4384 * - HAL_DCMIPP_PIPE_EnableDownsize() : Enable the Downsize feature.
4385 * - HAL_DCMIPP_PIPE_DisableDownsize() : Disable the Downsize feature.
4386 */
4387 /**
4388 * @brief Configures Downsize for the specified DCMIPP pipe according to the user parameters
4389 * @param hdcmipp Pointer to DCMIPP handle
4390 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4391 * @param pDownsizeConfig pointer to the DCMIPP_DownsizeTypeDef structure that contains Downsize information
4392 * @retval HAL status
4393 */
HAL_DCMIPP_PIPE_SetDownsizeConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_DownsizeTypeDef * pDownsizeConfig)4394 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetDownsizeConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
4395 const DCMIPP_DownsizeTypeDef *pDownsizeConfig)
4396 {
4397 /* Check handle validity */
4398 if ((hdcmipp == NULL) || (pDownsizeConfig == NULL))
4399 {
4400 return HAL_ERROR;
4401 }
4402
4403 /* Check parameters */
4404 assert_param(IS_DCMIPP_PIPE(Pipe));
4405 assert_param(IS_DCMIPP_DOWSIZE_DIV_FACTOR(pDownsizeConfig->HDivFactor));
4406 assert_param(IS_DCMIPP_DOWSIZE_DIV_FACTOR(pDownsizeConfig->VDivFactor));
4407 assert_param(IS_DCMIPP_DOWSIZE_RATIO(pDownsizeConfig->HRatio));
4408 assert_param(IS_DCMIPP_DOWSIZE_RATIO(pDownsizeConfig->VRatio));
4409 assert_param(IS_DCMIPP_DOWSIZE_SIZE(pDownsizeConfig->HSize));
4410 assert_param(IS_DCMIPP_DOWSIZE_SIZE(pDownsizeConfig->VSize));
4411
4412 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
4413 {
4414 if (Pipe == DCMIPP_PIPE1)
4415 {
4416 /* Set Vertical and Horizontal division */
4417 MODIFY_REG(hdcmipp->Instance->P1DSCR, (DCMIPP_P1DSCR_HDIV | DCMIPP_P1DSCR_VDIV),
4418 ((pDownsizeConfig->HDivFactor << DCMIPP_P1DSCR_HDIV_Pos) | \
4419 (pDownsizeConfig->VDivFactor << DCMIPP_P1DSCR_VDIV_Pos)));
4420
4421 /* Set Vertical and Horizontal Ratio */
4422 WRITE_REG(hdcmipp->Instance->P1DSRTIOR, (pDownsizeConfig->HRatio << DCMIPP_P1DSRTIOR_HRATIO_Pos) | \
4423 (pDownsizeConfig->VRatio << DCMIPP_P1DSRTIOR_VRATIO_Pos));
4424
4425 /* Set Downsize Destination size */
4426 MODIFY_REG(hdcmipp->Instance->P1DSSZR, DCMIPP_P1DSSZR_HSIZE | DCMIPP_P1DSSZR_VSIZE,
4427 (pDownsizeConfig->HSize << DCMIPP_P1DSSZR_HSIZE_Pos) | \
4428 (pDownsizeConfig->VSize << DCMIPP_P1DSSZR_VSIZE_Pos));
4429 }
4430 else if (Pipe == DCMIPP_PIPE2)
4431 {
4432 /* Set Vertical and Horizontal division */
4433 MODIFY_REG(hdcmipp->Instance->P2DSCR, DCMIPP_P2DSCR_HDIV | DCMIPP_P2DSCR_VDIV,
4434 (pDownsizeConfig->HDivFactor << DCMIPP_P2DSCR_HDIV_Pos) | \
4435 (pDownsizeConfig->VDivFactor << DCMIPP_P2DSCR_VDIV_Pos));
4436
4437 /* Set Vertical and Horizontal Ratio */
4438 WRITE_REG(hdcmipp->Instance->P2DSRTIOR, (pDownsizeConfig->HRatio << DCMIPP_P2DSRTIOR_HRATIO_Pos) | \
4439 (pDownsizeConfig->VRatio << DCMIPP_P2DSRTIOR_VRATIO_Pos));
4440
4441 /* Set Downsize Destination size */
4442 MODIFY_REG(hdcmipp->Instance->P2DSSZR, DCMIPP_P2DSSZR_HSIZE | DCMIPP_P2DSSZR_VSIZE,
4443 (pDownsizeConfig->HSize << DCMIPP_P2DSSZR_HSIZE_Pos) | \
4444 (pDownsizeConfig->VSize << DCMIPP_P2DSSZR_VSIZE_Pos));
4445 }
4446 else
4447 {
4448 return HAL_ERROR;
4449 }
4450 }
4451 else
4452 {
4453 return HAL_ERROR;
4454 }
4455
4456 return HAL_OK;
4457 }
4458
4459 /**
4460 * @brief Enable the Downsize for the specified DCMIPP pipe.
4461 * @param hdcmipp Pointer to DCMIPP handle
4462 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4463 * @retval HAL status
4464 */
HAL_DCMIPP_PIPE_EnableDownsize(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4465 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableDownsize(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4466 {
4467 /* Check handle validity */
4468 if (hdcmipp == NULL)
4469 {
4470 return HAL_ERROR;
4471 }
4472
4473 /* Check Parameters */
4474 assert_param(IS_DCMIPP_PIPE(Pipe));
4475
4476 if (Pipe == DCMIPP_PIPE1)
4477 {
4478 SET_BIT(hdcmipp->Instance->P1DSCR, DCMIPP_P1DSCR_ENABLE);
4479 }
4480 else if (Pipe == DCMIPP_PIPE2)
4481 {
4482 SET_BIT(hdcmipp->Instance->P2DSCR, DCMIPP_P2DSCR_ENABLE);
4483 }
4484 else
4485 {
4486 return HAL_ERROR;
4487 }
4488
4489 return HAL_OK;
4490 }
4491
4492 /**
4493 * @brief Disable the Downsize for the specified DCMIPP pipe.
4494 * @param hdcmipp Pointer to DCMIPP handle
4495 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4496 * @retval HAL status
4497 */
HAL_DCMIPP_PIPE_DisableDownsize(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4498 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableDownsize(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4499 {
4500 /* Check handle validity */
4501 if (hdcmipp == NULL)
4502 {
4503 return HAL_ERROR;
4504 }
4505
4506 /* Check Parameters */
4507 assert_param(IS_DCMIPP_PIPE(Pipe));
4508
4509 if (Pipe == DCMIPP_PIPE1)
4510 {
4511 CLEAR_BIT(hdcmipp->Instance->P1DSCR, DCMIPP_P1DSCR_ENABLE);
4512 }
4513 else if (Pipe == DCMIPP_PIPE2)
4514 {
4515 CLEAR_BIT(hdcmipp->Instance->P2DSCR, DCMIPP_P2DSCR_ENABLE);
4516 }
4517 else
4518 {
4519 return HAL_ERROR;
4520 }
4521
4522 return HAL_OK;
4523 }
4524
4525 /**
4526 * @brief Enable the Gamma Conversion for the specified DCMIPP pipe.
4527 * @param hdcmipp Pointer to DCMIPP handle
4528 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4529 * @retval HAL status
4530 */
HAL_DCMIPP_PIPE_EnableGammaConversion(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4531 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableGammaConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4532 {
4533 /* Check handles validity */
4534 if (hdcmipp == NULL)
4535 {
4536 return HAL_ERROR;
4537 }
4538
4539 /* Check Parameters */
4540 assert_param(IS_DCMIPP_PIPE(Pipe));
4541
4542 if (Pipe == DCMIPP_PIPE1)
4543 {
4544 SET_BIT(hdcmipp->Instance->P1GMCR, DCMIPP_P1GMCR_ENABLE);
4545 }
4546 else if (Pipe == DCMIPP_PIPE2)
4547 {
4548 SET_BIT(hdcmipp->Instance->P2GMCR, DCMIPP_P2GMCR_ENABLE);
4549 }
4550 else
4551 {
4552 return HAL_ERROR;
4553 }
4554
4555 return HAL_OK;
4556 }
4557
4558 /**
4559 * @brief Disable the Gamma Conversion for the specified DCMIPP pipe.
4560 * @param hdcmipp Pointer to DCMIPP handle
4561 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4562 * @retval HAL status
4563 */
HAL_DCMIPP_PIPE_DisableGammaConversion(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4564 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableGammaConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4565 {
4566 /* Check handles validity */
4567 if (hdcmipp == NULL)
4568 {
4569 return HAL_ERROR;
4570 }
4571
4572 /* Check Parameters */
4573 assert_param(IS_DCMIPP_PIPE(Pipe));
4574
4575 if (Pipe == DCMIPP_PIPE1)
4576 {
4577 CLEAR_BIT(hdcmipp->Instance->P1GMCR, DCMIPP_P1GMCR_ENABLE);
4578 }
4579 else if (Pipe == DCMIPP_PIPE2)
4580 {
4581 CLEAR_BIT(hdcmipp->Instance->P2GMCR, DCMIPP_P2GMCR_ENABLE);
4582 }
4583 else
4584 {
4585 return HAL_ERROR;
4586 }
4587
4588 return HAL_OK;
4589 }
4590
4591 /**
4592 * @brief Check if Gamma Conversion is enabled.
4593 * @param hdcmipp Pointer to DCMIPP handle
4594 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4595 * @retval State of bit (1 or 0).
4596 */
HAL_DCMIPP_PIPE_IsEnabledGammaConversion(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4597 uint32_t HAL_DCMIPP_PIPE_IsEnabledGammaConversion(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4598 {
4599 /* Check parameters */
4600 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
4601 assert_param(IS_DCMIPP_PIPE(Pipe));
4602
4603 if (Pipe == DCMIPP_PIPE1)
4604 {
4605 return ((READ_BIT(hdcmipp->Instance->P1GMCR, DCMIPP_P1GMCR_ENABLE) == DCMIPP_P1GMCR_ENABLE) ? 1U : 0U);
4606 }
4607 else if (Pipe == DCMIPP_PIPE2)
4608 {
4609 return ((READ_BIT(hdcmipp->Instance->P2GMCR, DCMIPP_P2GMCR_ENABLE) == DCMIPP_P2GMCR_ENABLE) ? 1U : 0U);
4610 }
4611 else
4612 {
4613 /* State Disabled */
4614 return 0;
4615 }
4616 }
4617
4618 /**
4619 * @brief Configures the ISP Raw Bayer to RGB for the specified DCMIPP pipe according to the user parameters
4620 * @param hdcmipp Pointer to DCMIPP handle
4621 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4622 * @param pRawBayer2RGBConfig pointer to DCMIPP_RawBayer2RGBConfTypeDef structure that contains the Raw Bayer to RGB
4623 * information.
4624 * @retval HAL status
4625 */
HAL_DCMIPP_PIPE_SetISPRawBayer2RGBConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_RawBayer2RGBConfTypeDef * pRawBayer2RGBConfig)4626 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPRawBayer2RGBConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
4627 const DCMIPP_RawBayer2RGBConfTypeDef *pRawBayer2RGBConfig)
4628 {
4629 uint32_t p1dmcr_reg;
4630
4631 /* Check handles validity */
4632 if ((hdcmipp == NULL) || (pRawBayer2RGBConfig == NULL))
4633 {
4634 return HAL_ERROR;
4635 }
4636
4637 /* Check Parameters */
4638 assert_param(IS_DCMIPP_PIPE(Pipe));
4639 assert_param(IS_DCMIPP_RAWBAYER2RGB_RAW_TYPE(pRawBayer2RGBConfig->RawBayerType));
4640 assert_param(IS_DCMIPP_RAWBAYER2RGB_STRENGTH(pRawBayer2RGBConfig->PeakStrength));
4641 assert_param(IS_DCMIPP_RAWBAYER2RGB_STRENGTH(pRawBayer2RGBConfig->VLineStrength));
4642 assert_param(IS_DCMIPP_RAWBAYER2RGB_STRENGTH(pRawBayer2RGBConfig->HLineStrength));
4643 assert_param(IS_DCMIPP_RAWBAYER2RGB_STRENGTH(pRawBayer2RGBConfig->EdgeStrength));
4644
4645 if (Pipe == DCMIPP_PIPE1)
4646 {
4647
4648 p1dmcr_reg = ((pRawBayer2RGBConfig->RawBayerType) | \
4649 (pRawBayer2RGBConfig->PeakStrength << DCMIPP_P1DMCR_PEAK_Pos) | \
4650 (pRawBayer2RGBConfig->EdgeStrength << DCMIPP_P1DMCR_EDGE_Pos) | \
4651 (pRawBayer2RGBConfig->VLineStrength << DCMIPP_P1DMCR_LINEV_Pos) | \
4652 (pRawBayer2RGBConfig->HLineStrength << DCMIPP_P1DMCR_LINEH_Pos));
4653
4654
4655 MODIFY_REG(hdcmipp->Instance->P1DMCR, DCMIPP_P1DMCR_TYPE | DCMIPP_P1DMCR_PEAK | DCMIPP_P1DMCR_LINEV | \
4656 DCMIPP_P1DMCR_LINEH | DCMIPP_P1DMCR_EDGE, p1dmcr_reg);
4657
4658 }
4659 else
4660 {
4661 return HAL_ERROR;
4662 }
4663
4664 return HAL_OK;
4665 }
4666
4667 /**
4668 * @brief Enable the ISP Raw Bayer to RGB for the specified DCMIPP pipe
4669 * @param hdcmipp Pointer to DCMIPP handle
4670 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4671 * @retval HAL status
4672 */
HAL_DCMIPP_PIPE_EnableISPRawBayer2RGB(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4673 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPRawBayer2RGB(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4674 {
4675 /* Check handles validity */
4676 if (hdcmipp == NULL)
4677 {
4678 return HAL_ERROR;
4679 }
4680
4681 /* Check parameters */
4682 assert_param(IS_DCMIPP_PIPE(Pipe));
4683
4684 if (Pipe == DCMIPP_PIPE1)
4685 {
4686 SET_BIT(hdcmipp->Instance->P1DMCR, DCMIPP_P1DMCR_ENABLE);
4687 }
4688 else
4689 {
4690 return HAL_ERROR;
4691 }
4692
4693 return HAL_OK;
4694 }
4695
4696 /**
4697 * @brief Disable the ISP Raw Bayer to RGB for the specified DCMIPP pipe
4698 * @param hdcmipp Pointer to DCMIPP handle
4699 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4700 * @retval HAL status
4701 */
HAL_DCMIPP_PIPE_DisableISPRawBayer2RGB(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4702 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPRawBayer2RGB(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4703 {
4704 /* Check handles validity */
4705 if (hdcmipp == NULL)
4706 {
4707 return HAL_ERROR;
4708 }
4709
4710 /* Check parameters */
4711 assert_param(IS_DCMIPP_PIPE(Pipe));
4712
4713 if (Pipe == DCMIPP_PIPE1)
4714 {
4715 CLEAR_BIT(hdcmipp->Instance->P1DMCR, DCMIPP_P1DMCR_ENABLE);
4716 }
4717 else
4718 {
4719 return HAL_ERROR;
4720 }
4721
4722 return HAL_OK;
4723 }
4724
4725 /**
4726 * @brief Configures the ISP Statistic Removal for the specified DCMIPP pipe.
4727 * @param hdcmipp Pointer to DCMIPP handle
4728 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4729 * @param NbFirstLines number of lines to skip at the top of the image
4730 * @param NbLastLines number of valid image line to keep after the skipped first lines
4731 * @retval HAL status
4732 */
HAL_DCMIPP_PIPE_SetISPRemovalStatisticConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t NbFirstLines,uint32_t NbLastLines)4733 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPRemovalStatisticConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
4734 uint32_t NbFirstLines, uint32_t NbLastLines)
4735 {
4736 uint32_t p1srcr_reg;
4737
4738 /* Check handles validity */
4739 if (hdcmipp == NULL)
4740 {
4741 return HAL_ERROR;
4742 }
4743
4744 /* Check parameters */
4745 assert_param(IS_DCMIPP_PIPE(Pipe));
4746 assert_param(IS_DCMIPP_NB_FIRST_LINES(NbFirstLines));
4747 assert_param(IS_DCMIPP_NB_LAST_LINES(NbLastLines));
4748
4749 if (Pipe == DCMIPP_PIPE1)
4750 {
4751 p1srcr_reg = ((NbFirstLines << DCMIPP_P1SRCR_FIRSTLINEDEL_Pos) | (NbLastLines << DCMIPP_P1SRCR_LASTLINE_Pos));
4752
4753 MODIFY_REG(hdcmipp->Instance->P1SRCR, (DCMIPP_P1SRCR_FIRSTLINEDEL | DCMIPP_P1SRCR_LASTLINE), p1srcr_reg);
4754 }
4755 else
4756 {
4757 return HAL_ERROR;
4758 }
4759
4760 return HAL_OK;
4761 }
4762
4763 /**
4764 * @brief Enable the ISP Statisic Removal for the specified DCMIPP pipe.
4765 * @param hdcmipp Pointer to DCMIPP handle
4766 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4767 * @retval HAL status
4768 */
HAL_DCMIPP_PIPE_EnableISPRemovalStatistic(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4769 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPRemovalStatistic(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4770 {
4771 /* Check handles validity */
4772 if (hdcmipp == NULL)
4773 {
4774 return HAL_ERROR;
4775 }
4776
4777 if (Pipe == DCMIPP_PIPE1)
4778 {
4779 SET_BIT(hdcmipp->Instance->P1SRCR, DCMIPP_P1SRCR_CROPEN);
4780 }
4781 else
4782 {
4783 return HAL_ERROR;
4784 }
4785
4786 return HAL_OK;
4787 }
4788
4789 /**
4790 * @brief Disable the ISP Statisic Removal for the specified DCMIPP pipe.
4791 * @param hdcmipp Pointer to DCMIPP handle
4792 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4793 * @retval HAL status
4794 */
HAL_DCMIPP_PIPE_DisableISPRemovalStatistic(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4795 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPRemovalStatistic(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4796 {
4797 /* Check handles validity */
4798 if (hdcmipp == NULL)
4799 {
4800 return HAL_ERROR;
4801 }
4802
4803 if (Pipe == DCMIPP_PIPE1)
4804 {
4805 CLEAR_BIT(hdcmipp->Instance->P1SRCR, DCMIPP_P1SRCR_CROPEN);
4806 }
4807 else
4808 {
4809 return HAL_ERROR;
4810 }
4811
4812 return HAL_OK;
4813 }
4814
4815 /**
4816 * A set of functions allowing to configure the DCMIPP pipe peripheral for the ISP block:
4817 * - ISP Bad Pixel Removal Feature:
4818 * HAL_DCMIPP_PIPE_SetISPBadPixelRemovalConfig() : Set the Bad Pixel Removal configuration.
4819 * HAL_DCMIPP_PIPE_EnableISPBadPixelRemoval() : Enable the Bad Pixel Removal.
4820 * HAL_DCMIPP_PIPE_DisableISPBadPixelRemoval() : Disable the Bad Pixel Removal.
4821 * HAL_DCMIPP_PIPE_GetISPBadPixelRemovalConfig() : Get the Bad Pixel Removal configuration.
4822 * HAL_DCMIPP_PIPE_IsEnabledISPBadPixelRemoval() : Check the status of Bad Pixel Removal.
4823 * HAL_DCMIPP_PIPE_GetISPRemovedBadPixelCounter() : Get the Bad Pixel Removal counter.
4824 */
4825 /**
4826 * @brief Configure the ISP Bad Pixel Removal for the specified DCMIPP pipe.
4827 * @param hdcmipp Pointer to DCMIPP handle
4828 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4829 * @param Strength Specifies the removal strength, can be a value from @ref DCMIPP_Bad_Pixel_Removal_Strength
4830 * @retval HAL status
4831 */
HAL_DCMIPP_PIPE_SetISPBadPixelRemovalConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t Strength)4832 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPBadPixelRemovalConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
4833 uint32_t Strength)
4834 {
4835 /* Check handles validity */
4836 if (hdcmipp == NULL)
4837 {
4838 return HAL_ERROR;
4839 }
4840
4841 /* Check parameters */
4842 assert_param(IS_DCMIPP_PIPE(Pipe));
4843 assert_param(IS_DCMIPP_BAD_PXL_REMOVAL_STRENGTH(Strength));
4844
4845 if (Pipe == DCMIPP_PIPE1)
4846 {
4847 MODIFY_REG(hdcmipp->Instance->P1BPRCR, DCMIPP_P1BPRCR_STRENGTH, Strength << DCMIPP_P1BPRCR_STRENGTH_Pos);
4848 }
4849 else
4850 {
4851 return HAL_ERROR;
4852 }
4853
4854 return HAL_OK;
4855 }
4856
4857 /**
4858 * @brief Enable the ISP Bad Pixel Removal for the specified DCMIPP pipe.
4859 * @param hdcmipp Pointer to DCMIPP handle
4860 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4861 * @retval HAL status
4862 */
HAL_DCMIPP_PIPE_EnableISPBadPixelRemoval(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4863 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPBadPixelRemoval(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4864 {
4865 /* Check handles validity */
4866 if (hdcmipp == NULL)
4867 {
4868 return HAL_ERROR;
4869 }
4870
4871 /* Check parameters */
4872 assert_param(IS_DCMIPP_PIPE(Pipe));
4873
4874 if (Pipe == DCMIPP_PIPE1)
4875 {
4876 SET_BIT(hdcmipp->Instance->P1BPRCR, DCMIPP_P1BPRCR_ENABLE);
4877 }
4878 else
4879 {
4880 return HAL_ERROR;
4881 }
4882
4883 return HAL_OK;
4884 }
4885
4886 /**
4887 * @brief Disable the ISP Bad Pixel Removal for the specified DCMIPP pipe.
4888 * @param hdcmipp Pointer to DCMIPP handle
4889 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4890 * @retval HAL status
4891 */
HAL_DCMIPP_PIPE_DisableISPBadPixelRemoval(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4892 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPBadPixelRemoval(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4893 {
4894 /* Check handles validity */
4895 if (hdcmipp == NULL)
4896 {
4897 return HAL_ERROR;
4898 }
4899
4900 /* Check parameters */
4901 assert_param(IS_DCMIPP_PIPE(Pipe));
4902
4903 if (Pipe == DCMIPP_PIPE1)
4904 {
4905 CLEAR_BIT(hdcmipp->Instance->P1BPRCR, DCMIPP_P1BPRCR_ENABLE);
4906 }
4907 else
4908 {
4909 return HAL_ERROR;
4910 }
4911
4912 return HAL_OK;
4913 }
4914 /**
4915 * @brief Retrieve the ISP bad pixel removal strength configuration for a specified DCMIPP pipe.
4916 * @param hdcmipp Pointer to DCMIPP handle
4917 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4918 * @retval The strength of the bad pixel removal process.
4919 */
HAL_DCMIPP_PIPE_GetISPBadPixelRemovalConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4920 uint32_t HAL_DCMIPP_PIPE_GetISPBadPixelRemovalConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4921 {
4922 /* Check parameters */
4923 assert_param(IS_DCMIPP_PIPE(Pipe));
4924
4925 return (((READ_REG(hdcmipp->Instance->P1BPRCR)) & DCMIPP_P1BPRCR_STRENGTH) >> DCMIPP_P1BPRCR_STRENGTH_Pos);
4926 }
4927 /**
4928 * @brief Check if ISP Bad Pixel Removal is enabled or not
4929 * @param hdcmipp Pointer to DCMIPP handle
4930 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4931 * @retval State of bit (1 or 0).
4932 */
HAL_DCMIPP_PIPE_IsEnabledISPBadPixelRemoval(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)4933 uint32_t HAL_DCMIPP_PIPE_IsEnabledISPBadPixelRemoval(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
4934 {
4935 /* Check parameters */
4936 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
4937 assert_param(IS_DCMIPP_PIPE(Pipe));
4938
4939 if (Pipe == DCMIPP_PIPE1)
4940 {
4941 return ((READ_BIT(hdcmipp->Instance->P1BPRCR, DCMIPP_P1BPRCR_ENABLE) == DCMIPP_P1BPRCR_ENABLE) ? 1U : 0U);
4942 }
4943 else
4944 {
4945 /* State Disabled */
4946 return 0;
4947 }
4948 }
4949 /**
4950 * @brief Get the number of the corrected Bad Pixel in the last frame
4951 * @param hdcmipp Pointer to DCMIPP handle
4952 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4953 * @param pCounter pointer receiving the number of corrected bad pixels
4954 * @retval HAL status
4955 */
HAL_DCMIPP_PIPE_GetISPRemovedBadPixelCounter(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t * pCounter)4956 HAL_StatusTypeDef HAL_DCMIPP_PIPE_GetISPRemovedBadPixelCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
4957 uint32_t *pCounter)
4958 {
4959 /* Check handles validity */
4960 if ((hdcmipp == NULL) || (pCounter == NULL))
4961 {
4962 return HAL_ERROR;
4963 }
4964
4965 /* Check parameters */
4966 assert_param(IS_DCMIPP_PIPE(Pipe));
4967
4968 /* Check the DCMIPP State */
4969 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
4970 {
4971 *pCounter = READ_REG(hdcmipp->Instance->P1BPRSR & DCMIPP_P1BPRSR_BADCNT);
4972 }
4973 else
4974 {
4975 return HAL_ERROR;
4976 }
4977
4978 return HAL_OK;
4979 }
4980 /**
4981 * Region Of Interest Feature :
4982 * - HAL_DCMIPP_PIPE_SetRegionOfInterestConfig() : Set the Region Of Interest configuration.
4983 * - HAL_DCMIPP_PIPE_EnableRegionOfInterest() : Enable the Region Of Interest.
4984 * - HAL_DCMIPP_PIPE_DisableRegionOfInterest() : Disable the Region Of Interest.
4985 */
4986 /**
4987 * @brief Configure the Region Of Interest for the specified DCMIPP pipe according to the user parameters
4988 * @param hdcmipp Pointer to DCMIPP handle
4989 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
4990 * @param pROIConfig pointer to a DCMIPP_RegionOfInterestConfTypeDef structure that contains
4991 * the configuration information for the ROI.
4992 * @retval HAL status
4993 */
HAL_DCMIPP_PIPE_SetRegionOfInterestConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_RegionOfInterestConfTypeDef * pROIConfig)4994 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetRegionOfInterestConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
4995 const DCMIPP_RegionOfInterestConfTypeDef *pROIConfig)
4996 {
4997 uint32_t region_index;
4998 DCMIPP_Region_TypeDef *region;
4999 uint32_t address;
5000
5001 /* Check handles validity */
5002 if (hdcmipp == NULL)
5003 {
5004 return HAL_ERROR;
5005 }
5006
5007 /* Check Parameters */
5008 assert_param(IS_DCMIPP_PIPE(Pipe));
5009 assert_param(IS_DCMIPP_ROI(pROIConfig->RegionOfInterest));
5010 assert_param(IS_DCMIPP_ROI_START(pROIConfig->HStart));
5011 assert_param(IS_DCMIPP_ROI_START(pROIConfig->VStart));
5012 assert_param(IS_DCMIPP_ROI_SIZE(pROIConfig->HSize));
5013 assert_param(IS_DCMIPP_ROI_SIZE(pROIConfig->VSize));
5014 assert_param(IS_DCMIPP_ROI_COLOR(pROIConfig->ColorLineBlue));
5015 assert_param(IS_DCMIPP_ROI_COLOR(pROIConfig->ColorLineGreen));
5016 assert_param(IS_DCMIPP_ROI_COLOR(pROIConfig->ColorLineRed));
5017 assert_param(IS_DCMIPP_ROI_LINE_WIDTH(pROIConfig->LineSizeWidth));
5018
5019 region_index = pROIConfig->RegionOfInterest;
5020
5021 if ((Pipe == DCMIPP_PIPE1) || (Pipe == DCMIPP_PIPE2))
5022 {
5023
5024 if (Pipe == DCMIPP_PIPE1)
5025 {
5026 address = (uint32_t) &(hdcmipp->Instance->P1RIxCR1) + (0x8U * (region_index - 1U));
5027
5028 region = (DCMIPP_Region_TypeDef *)address;
5029
5030 /* Set Line Width for the selected ROI */
5031 MODIFY_REG(hdcmipp->Instance->P1CMRICR, 0x000003U, pROIConfig->LineSizeWidth);
5032 }
5033 else
5034 {
5035 address = (uint32_t)&hdcmipp->Instance->P2RIxCR1 + (0x8U * (region_index - 1U));
5036
5037 region = (DCMIPP_Region_TypeDef *)address;
5038
5039 /* Set Line Width for the selected ROI */
5040 MODIFY_REG(hdcmipp->Instance->P2CMRICR, 0x000003U, pROIConfig->LineSizeWidth);
5041 }
5042
5043 /* Set Offsets Linesize and color */
5044 MODIFY_REG(region->PxRIxCR1, 0x3FFFFFFFU, (((uint32_t)pROIConfig->ColorLineBlue << 12U) |
5045 ((uint32_t)pROIConfig->ColorLineGreen << 14U) |
5046 ((uint32_t)pROIConfig->ColorLineRed << 28U) | \
5047 ((uint32_t)pROIConfig->VStart << 16U) | (pROIConfig->HStart)));
5048
5049 /* Set window size */
5050 MODIFY_REG(region->PxRIxCR2, 0xFFF0FFFU, ((uint32_t)pROIConfig->VSize << 16U) | pROIConfig->HSize);
5051
5052 }
5053 else
5054 {
5055 return HAL_ERROR;
5056 }
5057
5058 return HAL_OK;
5059 }
5060
5061 /**
5062 * @brief Enable the Region Of Interest for the specified DCMIPP pipe
5063 * @param hdcmipp Pointer to DCMIPP handle
5064 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5065 * @param Region Specifies the region, can be a value from @ref DCMIPP_Region_Of_Interest
5066 * @retval HAL status
5067 */
HAL_DCMIPP_PIPE_EnableRegionOfInterest(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t Region)5068 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableRegionOfInterest(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Region)
5069 {
5070 /* Check handles validity */
5071 if (hdcmipp == NULL)
5072 {
5073 return HAL_ERROR;
5074 }
5075
5076 /* Check Parameters */
5077 assert_param(IS_DCMIPP_PIPE(Pipe));
5078
5079 if (Pipe == DCMIPP_PIPE1)
5080 {
5081 /* Enable ROI */
5082 MODIFY_REG(hdcmipp->Instance->P1CMRICR, 0xFF0001U, ((uint32_t)1U << (16U + (Region - 1U))));
5083 }
5084 else if (Pipe == DCMIPP_PIPE2)
5085 {
5086 /* Enable ROI */
5087 MODIFY_REG(hdcmipp->Instance->P2CMRICR, 0xFF0001U, ((uint32_t)1U << (16U + (Region - 1U))));
5088 }
5089 else
5090 {
5091 return HAL_ERROR;
5092 }
5093
5094 return HAL_OK;
5095 }
5096
5097 /**
5098 * @brief Disable the Region Of Interest for the specified DCMIPP pipe
5099 * @param hdcmipp Pointer to DCMIPP handle
5100 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5101 * @param Region Specifies the region, can be a value from @ref DCMIPP_Region_Of_Interest
5102 * @retval HAL status
5103 */
HAL_DCMIPP_PIPE_DisableRegionOfInterest(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t Region)5104 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableRegionOfInterest(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
5105 uint32_t Region)
5106 {
5107 /* Check handles validity */
5108 if (hdcmipp == NULL)
5109 {
5110 return HAL_ERROR;
5111 }
5112
5113 /* Check Parameters */
5114 assert_param(IS_DCMIPP_PIPE(Pipe));
5115
5116 if (Pipe == DCMIPP_PIPE1)
5117 {
5118 /* Disable ROI */
5119 hdcmipp->Instance->P1CMRICR &= ~(1U << (16U + (Region - 1U)));
5120 }
5121 else if (Pipe == DCMIPP_PIPE2)
5122 {
5123 /* Disable ROI */
5124 hdcmipp->Instance->P2CMRICR &= ~(1U << (16U + (Region - 1U)));
5125 }
5126 else
5127 {
5128 return HAL_ERROR;
5129 }
5130
5131 return HAL_OK;
5132 }
5133
5134 /**
5135 * @brief Configure the ISP Color conversion for the selected DCMIPP Pipe according to the user parameters.
5136 * @param hdcmipp Pointer to DCMIPP handle
5137 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5138 * @param pColorConversionConfig pointer to DCMIPP_ColorConversionConfTypeDef structure that contains
5139 * color conversion information.
5140 * @retval HAL status
5141 */
HAL_DCMIPP_PIPE_SetISPColorConversionConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_ColorConversionConfTypeDef * pColorConversionConfig)5142 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPColorConversionConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
5143 const DCMIPP_ColorConversionConfTypeDef
5144 *pColorConversionConfig)
5145 {
5146 uint32_t p1cccr_reg;
5147 uint16_t tmp1;
5148 uint16_t tmp2;
5149
5150 /* Check handles validity */
5151 if ((hdcmipp == NULL) || (pColorConversionConfig == NULL))
5152 {
5153 return HAL_ERROR;
5154 }
5155
5156 /* Check parameters */
5157 assert_param(IS_DCMIPP_PIPE(Pipe));
5158 assert_param(IS_FUNCTIONAL_STATE(pColorConversionConfig->ClampOutputSamples));
5159 assert_param(IS_DCMIPP_OUTPUT_SAMPLES_TYPES(pColorConversionConfig->OutputSamplesType));
5160 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RR));
5161 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RG));
5162 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RB));
5163 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RA));
5164 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GR));
5165 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GG));
5166 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GB));
5167 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GA));
5168 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BR));
5169 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BG));
5170 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BB));
5171 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BA));
5172
5173 if (Pipe == DCMIPP_PIPE1)
5174 {
5175 /* Set Clamp and Type */
5176 p1cccr_reg = ((uint32_t)pColorConversionConfig->ClampOutputSamples << DCMIPP_P1CCCR_CLAMP_Pos) | \
5177 ((uint32_t)pColorConversionConfig->OutputSamplesType);
5178
5179 MODIFY_REG(hdcmipp->Instance->P1CCCR, DCMIPP_P1CCCR_CLAMP | DCMIPP_P1CCCR_TYPE, p1cccr_reg);
5180
5181 tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->RR);
5182 tmp2 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->RG);
5183
5184 /* Set Coefficient row 1 columns 1 2 3 and the added column of the matrix */
5185 MODIFY_REG(hdcmipp->Instance->P1CCRR1, DCMIPP_P1CCRR1_RR | DCMIPP_P1CCRR1_RG,
5186 (((uint32_t)tmp1) << DCMIPP_P1CCRR1_RR_Pos) | (((uint32_t)tmp2) << DCMIPP_P1CCRR1_RG_Pos));
5187
5188 tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->RB);
5189 tmp2 = MATRIX_VALUE10((uint16_t)pColorConversionConfig->RA);
5190
5191 MODIFY_REG(hdcmipp->Instance->P1CCRR2, DCMIPP_P1CCRR2_RB | DCMIPP_P1CCRR2_RA,
5192 ((uint32_t)tmp1 << DCMIPP_P1CCRR2_RB_Pos) | ((uint32_t)tmp2 << DCMIPP_P1CCRR2_RA_Pos));
5193
5194 tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->GG);
5195 tmp2 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->GR);
5196
5197
5198 /* Set Coefficient row 2 columns 1 2 3 and the added column of the matrix */
5199 MODIFY_REG(hdcmipp->Instance->P1CCGR1, DCMIPP_P1CCGR1_GR | DCMIPP_P1CCGR1_GG,
5200 ((uint32_t)tmp1 << DCMIPP_P1CCGR1_GG_Pos) | ((uint32_t)tmp2 << DCMIPP_P1CCGR1_GR_Pos));
5201
5202 tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->GB);
5203 tmp2 = MATRIX_VALUE10((uint16_t)pColorConversionConfig->GA);
5204
5205 MODIFY_REG(hdcmipp->Instance->P1CCGR2, DCMIPP_P1CCGR2_GB | DCMIPP_P1CCGR2_GA,
5206 ((uint32_t)tmp1 << DCMIPP_P1CCGR2_GB_Pos) | ((uint32_t)tmp2 << DCMIPP_P1CCGR2_GA_Pos));
5207
5208 tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->BR);
5209 tmp2 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->BG);
5210
5211 /* Set Coefficient row 3 columns 1 2 3 and the added column of the matrix */
5212 MODIFY_REG(hdcmipp->Instance->P1CCBR1, DCMIPP_P1CCBR1_BR | DCMIPP_P1CCBR1_BG,
5213 ((uint32_t)tmp1 << DCMIPP_P1CCBR1_BR_Pos) | ((uint32_t)tmp2 << DCMIPP_P1CCBR1_BG_Pos));
5214
5215 tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->BB);
5216 tmp2 = MATRIX_VALUE10((uint16_t)pColorConversionConfig->BA);
5217
5218 MODIFY_REG(hdcmipp->Instance->P1CCBR2, DCMIPP_P1CCBR2_BB | DCMIPP_P1CCBR2_BA,
5219 (((uint32_t)tmp1) << DCMIPP_P1CCBR2_BB_Pos) | (((uint32_t)tmp2) << DCMIPP_P1CCBR2_BA_Pos));
5220 }
5221 else
5222 {
5223 return HAL_ERROR;
5224 }
5225
5226 return HAL_OK;
5227 }
5228 /**
5229 * @brief Enable the ISP Color conversion for the selected DCMIPP Pipe
5230 * @param hdcmipp Pointer to DCMIPP handle
5231 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5232 * @retval HAL status
5233 */
HAL_DCMIPP_PIPE_EnableISPColorConversion(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)5234 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPColorConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
5235 {
5236 /* Check handle validity */
5237 if (hdcmipp == NULL)
5238 {
5239 return HAL_ERROR;
5240 }
5241
5242 /* Check parameters */
5243 assert_param(IS_DCMIPP_PIPE(Pipe));
5244
5245 if (Pipe == DCMIPP_PIPE1)
5246 {
5247 SET_BIT(hdcmipp->Instance->P1CCCR, DCMIPP_P1CCCR_ENABLE);
5248 }
5249 else
5250 {
5251 return HAL_ERROR;
5252 }
5253
5254 return HAL_OK;
5255 }
5256 /**
5257 * @brief Disable the ISP Color conversion for the selected DCMIPP Pipe
5258 * @param hdcmipp Pointer to DCMIPP handle
5259 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5260 * @retval HAL status
5261 */
HAL_DCMIPP_PIPE_DisableISPColorConversion(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)5262 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPColorConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
5263 {
5264 /* Check handle validity */
5265 if (hdcmipp == NULL)
5266 {
5267 return HAL_ERROR;
5268 }
5269
5270 /* Check parameters */
5271 assert_param(IS_DCMIPP_PIPE(Pipe));
5272
5273 if (Pipe == DCMIPP_PIPE1)
5274 {
5275 CLEAR_BIT(hdcmipp->Instance->P1CCCR, DCMIPP_P1CCCR_ENABLE);
5276 }
5277 else
5278 {
5279 return HAL_ERROR;
5280 }
5281
5282 return HAL_OK;
5283 }
5284 /**
5285 * YUV Conversion Feature :
5286 * - HAL_DCMIPP_PIPE_SetYUVConversionConfig() : Set the YUV conversion configuration.
5287 * - HAL_DCMIPP_PIPE_EnableYUVConversion() : Enable YUV conversion configuration.
5288 * - HAL_DCMIPP_PIPE_DisableYUVConversion() : Disable YUV conversion configuration.
5289 */
5290 /**
5291 * @brief Configure the YUV conversion for the selected DCMIPP Pipe according to the user parameters.
5292 * @param hdcmipp Pointer to DCMIPP handle
5293 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5294 * @param pColorConversionConfig pointer to DCMIPP_ColorConversionConfTypeDef structure that contains
5295 * color conversion information.
5296 * @retval HAL status
5297 */
HAL_DCMIPP_PIPE_SetYUVConversionConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_ColorConversionConfTypeDef * pColorConversionConfig)5298 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetYUVConversionConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
5299 const DCMIPP_ColorConversionConfTypeDef
5300 *pColorConversionConfig)
5301 {
5302 uint32_t p1yuvcr_reg;
5303 uint16_t tmp1;
5304 uint16_t tmp2;
5305
5306 /* Check handles validity */
5307 if ((hdcmipp == NULL) || (pColorConversionConfig == NULL))
5308 {
5309 return HAL_ERROR;
5310 }
5311
5312 /* Check parameters */
5313 assert_param(IS_DCMIPP_PIPE(Pipe));
5314 assert_param(IS_FUNCTIONAL_STATE(pColorConversionConfig->ClampOutputSamples));
5315 assert_param(IS_DCMIPP_OUTPUT_SAMPLES_TYPES(pColorConversionConfig->OutputSamplesType));
5316 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RR));
5317 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RG));
5318 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RB));
5319 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->RA));
5320 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GR));
5321 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GG));
5322 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GB));
5323 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->GA));
5324 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BR));
5325 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BG));
5326 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BB));
5327 assert_param(IS_DCMIPP_COLOR_CONVERSION_COEF(pColorConversionConfig->BA));
5328
5329 if (Pipe == DCMIPP_PIPE1)
5330 {
5331 /* Set Clamp and Type */
5332 p1yuvcr_reg = ((uint32_t)pColorConversionConfig->OutputSamplesType | \
5333 ((uint32_t)pColorConversionConfig->ClampOutputSamples << DCMIPP_P1YUVCR_CLAMP_Pos));
5334
5335 MODIFY_REG(hdcmipp->Instance->P1YUVCR, DCMIPP_P1YUVCR_CLAMP | DCMIPP_P1YUVCR_TYPE, p1yuvcr_reg);
5336
5337 tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->RR);
5338 tmp2 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->RG);
5339
5340 /* Set Coefficient row 1 columns 1 2 3 and the added column of the matrix */
5341 MODIFY_REG(hdcmipp->Instance->P1YUVRR1, DCMIPP_P1YUVRR1_RR | DCMIPP_P1YUVRR1_RG,
5342 (((uint32_t)tmp1) << DCMIPP_P1YUVRR1_RR_Pos) | (((uint32_t)tmp2) << DCMIPP_P1YUVRR1_RG_Pos));
5343
5344 tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->RB);
5345 tmp2 = MATRIX_VALUE10((uint16_t)pColorConversionConfig->RA);
5346
5347 MODIFY_REG(hdcmipp->Instance->P1YUVRR2, DCMIPP_P1YUVRR2_RB | DCMIPP_P1YUVRR2_RA,
5348 (((uint32_t)tmp1) << DCMIPP_P1YUVRR2_RB_Pos) | (((uint32_t)tmp2) << DCMIPP_P1YUVRR2_RA_Pos));
5349
5350 tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->GR);
5351 tmp2 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->GG);
5352
5353 /* Set Coefficient row 2 columns 1 2 3 and the added column of the matrix */
5354 MODIFY_REG(hdcmipp->Instance->P1YUVGR1, DCMIPP_P1YUVGR1_GR | DCMIPP_P1YUVGR1_GG,
5355 (((uint32_t)tmp1) << DCMIPP_P1YUVGR1_GR_Pos) | (((uint32_t)tmp2) << DCMIPP_P1YUVGR1_GG_Pos));
5356
5357 tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->GB);
5358 tmp2 = MATRIX_VALUE10((uint16_t)pColorConversionConfig->GA);
5359
5360 MODIFY_REG(hdcmipp->Instance->P1YUVGR2, DCMIPP_P1YUVGR2_GB | DCMIPP_P1YUVGR2_GA,
5361 (((uint32_t)tmp1) << DCMIPP_P1YUVGR2_GB_Pos) | (((uint32_t)tmp2) << DCMIPP_P1YUVGR2_GA_Pos));
5362
5363 tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->BR);
5364 tmp2 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->BG);
5365
5366 /* Set Coefficient row 3 columns 1 2 3 and the added column of the matrix */
5367 MODIFY_REG(hdcmipp->Instance->P1YUVBR1, DCMIPP_P1YUVBR1_BR | DCMIPP_P1YUVBR1_BG,
5368 (((uint32_t)tmp1) << DCMIPP_P1YUVBR1_BR_Pos) | (((uint32_t)tmp2) << DCMIPP_P1YUVBR1_BG_Pos));
5369
5370 tmp1 = MATRIX_VALUE11((uint16_t)pColorConversionConfig->BB);
5371 tmp2 = MATRIX_VALUE10((uint16_t)pColorConversionConfig->BA);
5372
5373 MODIFY_REG(hdcmipp->Instance->P1YUVBR2, DCMIPP_P1YUVBR2_BB | DCMIPP_P1YUVBR2_BA,
5374 (((uint32_t)tmp1) << DCMIPP_P1YUVBR2_BB_Pos) | (((uint32_t)tmp2) << DCMIPP_P1YUVBR2_BA_Pos));
5375 }
5376 else
5377 {
5378 return HAL_ERROR;
5379 }
5380
5381 return HAL_OK;
5382 }
5383 /**
5384 * @brief Enable the YUV conversion for the selected DCMIPP Pipe
5385 * @param hdcmipp Pointer to DCMIPP handle
5386 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5387 * @retval HAL status
5388 */
HAL_DCMIPP_PIPE_EnableYUVConversion(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)5389 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableYUVConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
5390 {
5391 /* Check handle validity */
5392 if (hdcmipp == NULL)
5393 {
5394 return HAL_ERROR;
5395 }
5396
5397 /* Check parameters */
5398 assert_param(IS_DCMIPP_PIPE(Pipe));
5399
5400 if (Pipe == DCMIPP_PIPE1)
5401 {
5402 SET_BIT(hdcmipp->Instance->P1YUVCR, DCMIPP_P1YUVCR_ENABLE);
5403 }
5404 else
5405 {
5406 return HAL_ERROR;
5407 }
5408
5409 return HAL_OK;
5410 }
5411 /**
5412 * @brief Disable the YUV conversion for the selected DCMIPP Pipe
5413 * @param hdcmipp Pointer to DCMIPP handle
5414 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5415 * @retval HAL status
5416 */
HAL_DCMIPP_PIPE_DisableYUVConversion(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)5417 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableYUVConversion(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
5418 {
5419 /* Check handle validity */
5420 if (hdcmipp == NULL)
5421 {
5422 return HAL_ERROR;
5423 }
5424
5425 /* Check parameters */
5426 assert_param(IS_DCMIPP_PIPE(Pipe));
5427
5428 if (Pipe == DCMIPP_PIPE1)
5429 {
5430 CLEAR_BIT(hdcmipp->Instance->P1YUVCR, DCMIPP_P1YUVCR_ENABLE);
5431 }
5432 else
5433 {
5434 return HAL_ERROR;
5435 }
5436
5437 return HAL_OK;
5438 }
5439 /**
5440 * A set of functions allowing to configure the DCMIPP pipe peripheral for the ISP block:
5441 * - ISP Black Level Calibration Feature:
5442 * HAL_DCMIPP_PIPE_SetISPBlackLevelCalibrationConfig() : Set the Black Level Calibration configuration.
5443 * HAL_DCMIPP_PIPE_EnableISPBlackLevelCalibration() : Enable the Black Level Calibration.
5444 * HAL_DCMIPP_PIPE_DisableISPBlackLevelCalibration() : Disable the Black Level Calibration.
5445 * HAL_DCMIPP_PIPE_GetISPBlackLevelCalibrationConfig() : Get the Black Level Calibration configuration.
5446 * HAL_DCMIPP_PIPE_IsEnabledISPBlackLevelCalibration() : Check the status of Black Level Calibration.
5447 */
5448 /**
5449 * @brief Configure the ISP Black Level Calibration for the selected DCMIPP Pipe according to the user parameters.
5450 * @param hdcmipp Pointer to DCMIPP handle
5451 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5452 * @param pBlackLevelConfig pointer to DCMIPP_BlackLevelConfTypeDef structure that contains black level
5453 * calibration information
5454 * @retval HAL status
5455 */
HAL_DCMIPP_PIPE_SetISPBlackLevelCalibrationConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_BlackLevelConfTypeDef * pBlackLevelConfig)5456 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPBlackLevelCalibrationConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
5457 const DCMIPP_BlackLevelConfTypeDef
5458 *pBlackLevelConfig)
5459 {
5460 /* Check handles validity */
5461 if ((hdcmipp == NULL) || (pBlackLevelConfig == NULL))
5462 {
5463 return HAL_ERROR;
5464 }
5465
5466 /* Check parameters */
5467 assert_param(IS_DCMIPP_PIPE(Pipe));
5468
5469 if (Pipe == DCMIPP_PIPE1)
5470 {
5471 MODIFY_REG(hdcmipp->Instance->P1BLCCR, DCMIPP_P1BLCCR_BLCR | DCMIPP_P1BLCCR_BLCG | DCMIPP_P1BLCCR_BLCB,
5472 (((uint32_t)pBlackLevelConfig->RedCompBlackLevel << DCMIPP_P1BLCCR_BLCR_Pos) | \
5473 ((uint32_t)pBlackLevelConfig->GreenCompBlackLevel << DCMIPP_P1BLCCR_BLCG_Pos) | \
5474 ((uint32_t)pBlackLevelConfig->BlueCompBlackLevel << DCMIPP_P1BLCCR_BLCB_Pos)));
5475 }
5476 else
5477 {
5478 return HAL_ERROR;
5479 }
5480
5481 return HAL_OK;
5482 }
5483 /**
5484 * @brief Enable the ISP Black Level Calibration for the selected DCMIPP Pipe
5485 * @param hdcmipp Pointer to DCMIPP handle
5486 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5487 * @retval HAL status
5488 */
HAL_DCMIPP_PIPE_EnableISPBlackLevelCalibration(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)5489 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPBlackLevelCalibration(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
5490 {
5491 /* Check handle validity */
5492 if (hdcmipp == NULL)
5493 {
5494 return HAL_ERROR;
5495 }
5496
5497 /* Check parameters */
5498 assert_param(IS_DCMIPP_PIPE(Pipe));
5499
5500 if (Pipe == DCMIPP_PIPE1)
5501 {
5502 SET_BIT(hdcmipp->Instance->P1BLCCR, DCMIPP_P1BLCCR_ENABLE);
5503 }
5504 else
5505 {
5506 return HAL_ERROR;
5507 }
5508
5509 return HAL_OK;
5510 }
5511 /**
5512 * @brief Disable the ISP Black Level Calibration for the selected DCMIPP Pipe
5513 * @param hdcmipp Pointer to DCMIPP handle
5514 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5515 * @retval HAL status
5516 */
HAL_DCMIPP_PIPE_DisableISPBlackLevelCalibration(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)5517 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPBlackLevelCalibration(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
5518 {
5519 /* Check handle validity */
5520 if (hdcmipp == NULL)
5521 {
5522 return HAL_ERROR;
5523 }
5524
5525 /* Check parameters */
5526 assert_param(IS_DCMIPP_PIPE(Pipe));
5527
5528 if (Pipe == DCMIPP_PIPE1)
5529 {
5530 CLEAR_BIT(hdcmipp->Instance->P1BLCCR, DCMIPP_P1BLCCR_ENABLE);
5531 }
5532 else
5533 {
5534 return HAL_ERROR;
5535 }
5536
5537 return HAL_OK;
5538 }
5539 /**
5540 * @brief Retrieve the ISP black level calibration configuration for a specified DCMIPP pipe.
5541 * @param hdcmipp Pointer to DCMIPP handle
5542 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5543 * @param pBlackLevelConfig Pointer to a DCMIPP_BlackLevelConfTypeDef structure that will be
5544 * filled with the black level calibration configuration of the specified pipe.
5545 * @retval None
5546 */
HAL_DCMIPP_PIPE_GetISPBlackLevelCalibrationConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,DCMIPP_BlackLevelConfTypeDef * pBlackLevelConfig)5547 void HAL_DCMIPP_PIPE_GetISPBlackLevelCalibrationConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
5548 DCMIPP_BlackLevelConfTypeDef *pBlackLevelConfig)
5549 {
5550 uint32_t p1blccr_reg;
5551 /* Check parameters */
5552 assert_param(IS_DCMIPP_PIPE(Pipe));
5553
5554 if (Pipe == DCMIPP_PIPE1)
5555 {
5556 p1blccr_reg = READ_REG(hdcmipp->Instance->P1BLCCR);
5557 pBlackLevelConfig->BlueCompBlackLevel = (uint8_t)((p1blccr_reg & DCMIPP_P1BLCCR_BLCB) >> DCMIPP_P1BLCCR_BLCB_Pos);
5558 pBlackLevelConfig->GreenCompBlackLevel = (uint8_t)((p1blccr_reg & DCMIPP_P1BLCCR_BLCG) >> DCMIPP_P1BLCCR_BLCG_Pos);
5559 pBlackLevelConfig->RedCompBlackLevel = (uint8_t)((p1blccr_reg & DCMIPP_P1BLCCR_BLCR) >> DCMIPP_P1BLCCR_BLCR_Pos);
5560 }
5561 }
5562
5563 /**
5564 * @brief Check if ISP Black Level Calibration is enabled or not
5565 * @param hdcmipp Pointer to DCMIPP handle
5566 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5567 * @retval State of bit (1 or 0).
5568 */
HAL_DCMIPP_PIPE_IsEnabledISPBlackLevelCalibration(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)5569 uint32_t HAL_DCMIPP_PIPE_IsEnabledISPBlackLevelCalibration(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
5570 {
5571 /* Check parameters */
5572 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
5573 assert_param(IS_DCMIPP_PIPE(Pipe));
5574
5575 if (Pipe == DCMIPP_PIPE1)
5576 {
5577 return ((READ_BIT(hdcmipp->Instance->P1BLCCR, DCMIPP_P1BLCCR_ENABLE) == DCMIPP_P1BLCCR_ENABLE) ? 1U : 0U);
5578 }
5579 else
5580 {
5581 /* State Disabled */
5582 return 0;
5583 }
5584 }
5585 /**
5586 * @brief Configure the ISP statistic extraction module for the selected DCMIPP Pipe according to the user parameters.
5587 * @param hdcmipp Pointer to DCMIPP handle
5588 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5589 * @param ModuleID Specifies the Module ID, can be a value from
5590 * @ref DCMIPP_Statistics_Extraction_Module_ID.
5591 * @param pStatisticExtractionConfig Pointer to DCMIPP_StatisticExtractionConfTypeDef structure
5592 that contains statistic extraction information
5593 * @retval HAL status
5594 */
HAL_DCMIPP_PIPE_SetISPStatisticExtractionConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint8_t ModuleID,const DCMIPP_StatisticExtractionConfTypeDef * pStatisticExtractionConfig)5595 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPStatisticExtractionConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
5596 uint8_t ModuleID, const
5597 DCMIPP_StatisticExtractionConfTypeDef
5598 *pStatisticExtractionConfig)
5599 {
5600 uint32_t p1stxcr_reg;
5601
5602 /* Check handle validity */
5603 if ((hdcmipp == NULL) || (pStatisticExtractionConfig == NULL))
5604 {
5605 return HAL_ERROR;
5606 }
5607
5608 /* Check parameters */
5609 assert_param(IS_DCMIPP_PIPE(Pipe));
5610 assert_param(IS_DCMIPP_STAT_EXTRACTION_MODULE(ModuleID));
5611 assert_param(IS_DCMIPP_STAT_EXTRACTION_BINS(pStatisticExtractionConfig->Bins));
5612 assert_param(IS_DCMIPP_STAT_EXTRACTION_SOURCE(pStatisticExtractionConfig->Source));
5613 assert_param(IS_DCMIPP_STAT_EXTRACTION_MODE(pStatisticExtractionConfig->Mode));
5614
5615 if (Pipe == DCMIPP_PIPE1)
5616 {
5617 p1stxcr_reg = (pStatisticExtractionConfig->Mode) | (pStatisticExtractionConfig->Source) | \
5618 (pStatisticExtractionConfig->Bins);
5619
5620 switch (ModuleID)
5621 {
5622 case DCMIPP_STATEXT_MODULE1:
5623 MODIFY_REG(hdcmipp->Instance->P1ST1CR, DCMIPP_P1ST1CR_BINS | DCMIPP_P1ST1CR_SRC | \
5624 DCMIPP_P1ST1CR_MODE, p1stxcr_reg);
5625 break;
5626 case DCMIPP_STATEXT_MODULE2:
5627 MODIFY_REG(hdcmipp->Instance->P1ST2CR, DCMIPP_P1ST2CR_BINS | DCMIPP_P1ST2CR_SRC | \
5628 DCMIPP_P1ST2CR_MODE, p1stxcr_reg);
5629 break;
5630 default:
5631 /* DCMIPP_STATEXT_MODULE3 */
5632 MODIFY_REG(hdcmipp->Instance->P1ST3CR, DCMIPP_P1ST3CR_BINS | DCMIPP_P1ST3CR_SRC | \
5633 DCMIPP_P1ST3CR_MODE, p1stxcr_reg);
5634 break;
5635 }
5636 }
5637 else
5638 {
5639 return HAL_ERROR;
5640 }
5641
5642 return HAL_OK;
5643 }
5644 /**
5645 * @brief Configures the area for statistics extraction for the selected DCMIPP Pipe according to the user parameters.
5646 * @param hdcmipp Pointer to DCMIPP handle
5647 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5648 * @param pStatisticExtractionAreaConfig Pointer to DCMIPP_StatisticExtractionAreaConfTypeDef structure
5649 that contains statistic extraction Area information
5650 * @retval HAL status
5651 */
HAL_DCMIPP_PIPE_SetISPAreaStatisticExtractionConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_StatisticExtractionAreaConfTypeDef * pStatisticExtractionAreaConfig)5652 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPAreaStatisticExtractionConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
5653 const DCMIPP_StatisticExtractionAreaConfTypeDef
5654 *pStatisticExtractionAreaConfig)
5655 {
5656 /* Check handle validity */
5657 if ((hdcmipp == NULL) || (pStatisticExtractionAreaConfig == NULL))
5658 {
5659 return HAL_ERROR;
5660 }
5661
5662 /* Check parameters */
5663 assert_param(IS_DCMIPP_PIPE(Pipe));
5664 assert_param(IS_DCMIPP_PIPE_STAT_EXTRACTION_START(pStatisticExtractionAreaConfig->HStart));
5665 assert_param(IS_DCMIPP_PIPE_STAT_EXTRACTION_START(pStatisticExtractionAreaConfig->VStart));
5666 assert_param(IS_DCMIPP_PIPE_STAT_EXTRACTION_SIZE(pStatisticExtractionAreaConfig->HSize));
5667 assert_param(IS_DCMIPP_PIPE_STAT_EXTRACTION_SIZE(pStatisticExtractionAreaConfig->VSize));
5668
5669 if (Pipe == DCMIPP_PIPE1)
5670 {
5671 MODIFY_REG(hdcmipp->Instance->P1STSTR, DCMIPP_P1STSTR_HSTART | DCMIPP_P1STSTR_VSTART,
5672 (pStatisticExtractionAreaConfig->HStart << DCMIPP_P1STSTR_HSTART_Pos) | \
5673 (pStatisticExtractionAreaConfig->VStart << DCMIPP_P1STSTR_VSTART_Pos));
5674
5675 MODIFY_REG(hdcmipp->Instance->P1STSZR, DCMIPP_P1STSZR_HSIZE | DCMIPP_P1STSZR_VSIZE,
5676 (pStatisticExtractionAreaConfig->HSize << DCMIPP_P1STSZR_HSIZE_Pos) | \
5677 (pStatisticExtractionAreaConfig->VSize << DCMIPP_P1STSZR_VSIZE_Pos));
5678 }
5679 else
5680 {
5681 return HAL_ERROR;
5682 }
5683
5684 return HAL_OK;
5685 }
5686 /**
5687 * @brief Enable the selected statistic extraction module for the selected DCMIPP Pipe
5688 * @param hdcmipp Pointer to DCMIPP handle
5689 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5690 * @param ModuleID Specifies the Module ID, can be a value from @ref DCMIPP_Statistics_Extraction_Module_ID.
5691 * @retval HAL status
5692 */
HAL_DCMIPP_PIPE_EnableISPStatisticExtraction(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint8_t ModuleID)5693 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPStatisticExtraction(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
5694 uint8_t ModuleID)
5695 {
5696 /* Check handle validity */
5697 if (hdcmipp == NULL)
5698 {
5699 return HAL_ERROR;
5700 }
5701
5702 /* Check parameters */
5703 assert_param(IS_DCMIPP_PIPE(Pipe));
5704 assert_param(IS_DCMIPP_STAT_EXTRACTION_MODULE(ModuleID));
5705
5706 if (Pipe == DCMIPP_PIPE1)
5707 {
5708 switch (ModuleID)
5709 {
5710 case DCMIPP_STATEXT_MODULE1:
5711 SET_BIT(hdcmipp->Instance->P1ST1CR, DCMIPP_P1ST1CR_ENABLE);
5712 break;
5713 case DCMIPP_STATEXT_MODULE2:
5714 SET_BIT(hdcmipp->Instance->P1ST2CR, DCMIPP_P1ST2CR_ENABLE);
5715 break;
5716 default:
5717 /* DCMIPP_STATEXT_MODULE3 */
5718 SET_BIT(hdcmipp->Instance->P1ST3CR, DCMIPP_P1ST3CR_ENABLE);
5719 break;
5720 }
5721 }
5722 else
5723 {
5724 return HAL_ERROR;
5725 }
5726
5727 return HAL_OK;
5728 }
5729
5730 /**
5731 * @brief Disable the selected statistic extraction module for the selected DCMIPP Pipe
5732 * @param hdcmipp Pointer to DCMIPP handle
5733 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5734 * @param ModuleID Specifies the Module ID, can be a value from @ref DCMIPP_Statistics_Extraction_Module_ID.
5735 * @retval HAL status
5736 */
HAL_DCMIPP_PIPE_DisableISPStatisticExtraction(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint8_t ModuleID)5737 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPStatisticExtraction(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
5738 uint8_t ModuleID)
5739 {
5740 /* Check handle validity */
5741 if (hdcmipp == NULL)
5742 {
5743 return HAL_ERROR;
5744 }
5745
5746 /* Check parameters */
5747 assert_param(IS_DCMIPP_PIPE(Pipe));
5748 assert_param(IS_DCMIPP_STAT_EXTRACTION_MODULE(ModuleID));
5749
5750 if (Pipe == DCMIPP_PIPE1)
5751 {
5752 switch (ModuleID)
5753 {
5754 case DCMIPP_STATEXT_MODULE1:
5755 CLEAR_BIT(hdcmipp->Instance->P1ST1CR, DCMIPP_P1ST1CR_ENABLE);
5756 break;
5757 case DCMIPP_STATEXT_MODULE2:
5758 CLEAR_BIT(hdcmipp->Instance->P1ST2CR, DCMIPP_P1ST2CR_ENABLE);
5759 break;
5760 case DCMIPP_STATEXT_MODULE3:
5761 CLEAR_BIT(hdcmipp->Instance->P1ST3CR, DCMIPP_P1ST3CR_ENABLE);
5762 break;
5763 default:
5764 break;
5765 }
5766
5767 }
5768 else
5769 {
5770 return HAL_ERROR;
5771 }
5772
5773 return HAL_OK;
5774 }
5775
5776 /**
5777 * @brief Enable the ISP statistic extraction for the selected DCMIPP Pipe
5778 * @param hdcmipp Pointer to DCMIPP handle
5779 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5780 * @retval HAL status
5781 */
HAL_DCMIPP_PIPE_EnableISPAreaStatisticExtraction(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)5782 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPAreaStatisticExtraction(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
5783 {
5784 /* Check handle validity */
5785 if (hdcmipp == NULL)
5786 {
5787 return HAL_ERROR;
5788 }
5789
5790 /* Check parameters */
5791 assert_param(IS_DCMIPP_PIPE(Pipe));
5792
5793 if (Pipe == DCMIPP_PIPE1)
5794 {
5795 /* Crop line enable */
5796 SET_BIT(hdcmipp->Instance->P1STSZR, DCMIPP_P1STSZR_CROPEN);
5797 }
5798 else
5799 {
5800 return HAL_ERROR;
5801 }
5802
5803 return HAL_OK;
5804 }
5805 /**
5806 * @brief Disable the ISP statistic extraction for the selected DCMIPP Pipe
5807 * @param hdcmipp Pointer to DCMIPP handle
5808 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5809 * @retval HAL status
5810 */
HAL_DCMIPP_PIPE_DisableISPAreaStatisticExtraction(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)5811 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPAreaStatisticExtraction(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
5812 {
5813 /* Check handle validity */
5814 if (hdcmipp == NULL)
5815 {
5816 return HAL_ERROR;
5817 }
5818
5819 /* Check parameters */
5820 assert_param(IS_DCMIPP_PIPE(Pipe));
5821
5822 if (Pipe == DCMIPP_PIPE1)
5823 {
5824 CLEAR_BIT(hdcmipp->Instance->P1STSZR, DCMIPP_P1STSZR_CROPEN);
5825 }
5826 else
5827 {
5828 return HAL_ERROR;
5829 }
5830
5831 return HAL_OK;
5832 }
5833 /**
5834 * @brief Configure the ISP Exposure for the selected DCMIPP Pipe according to the user parameters
5835 * @param hdcmipp Pointer to DCMIPP handle
5836 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5837 * @param pExposureConfig pointer to the DCMIPP_ExposureConfTypeDef structure that contains the exposure information
5838 * @retval HAL status
5839 */
HAL_DCMIPP_PIPE_SetISPExposureConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_ExposureConfTypeDef * pExposureConfig)5840 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPExposureConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
5841 const DCMIPP_ExposureConfTypeDef *pExposureConfig)
5842 {
5843
5844 /* Check handle validity */
5845 if ((hdcmipp == NULL) || (pExposureConfig == NULL))
5846 {
5847 return HAL_ERROR;
5848 }
5849
5850 /* Check parameters */
5851 assert_param(IS_DCMIPP_PIPE(Pipe));
5852 assert_param(IS_DCMIPP_EXPOSURE_SHF(pExposureConfig->ShiftRed));
5853 assert_param(IS_DCMIPP_EXPOSURE_SHF(pExposureConfig->ShiftGreen));
5854 assert_param(IS_DCMIPP_EXPOSURE_SHF(pExposureConfig->ShiftBlue));
5855
5856 if (Pipe == DCMIPP_PIPE1)
5857 {
5858 MODIFY_REG(hdcmipp->Instance->P1EXCR1, DCMIPP_P1EXCR1_SHFR | DCMIPP_P1EXCR1_MULTR,
5859 (((uint32_t)pExposureConfig->ShiftRed << DCMIPP_P1EXCR1_SHFR_Pos) | \
5860 ((uint32_t)pExposureConfig->MultiplierRed << DCMIPP_P1EXCR1_MULTR_Pos)));
5861
5862 WRITE_REG(hdcmipp->Instance->P1EXCR2, (((uint32_t)pExposureConfig->ShiftGreen << DCMIPP_P1EXCR2_SHFG_Pos) | \
5863 ((uint32_t)pExposureConfig->MultiplierGreen << DCMIPP_P1EXCR2_MULTG_Pos) | \
5864 ((uint32_t)pExposureConfig->ShiftBlue << DCMIPP_P1EXCR2_SHFB_Pos) | \
5865 ((uint32_t)pExposureConfig->MultiplierBlue << DCMIPP_P1EXCR2_MULTB_Pos)));
5866 }
5867 else
5868 {
5869 return HAL_ERROR;
5870 }
5871
5872 return HAL_OK;
5873 }
5874 /**
5875 * @brief Enable the ISP Exposure for the selected DCMIPP Pipe
5876 * @param hdcmipp Pointer to DCMIPP handle
5877 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5878 * @retval HAL status
5879 */
HAL_DCMIPP_PIPE_EnableISPExposure(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)5880 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPExposure(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
5881 {
5882 /* Check handle validity */
5883 if (hdcmipp == NULL)
5884 {
5885 return HAL_ERROR;
5886 }
5887
5888 /* Check parameters */
5889 assert_param(IS_DCMIPP_PIPE(Pipe));
5890
5891 if (Pipe == DCMIPP_PIPE1)
5892 {
5893 SET_BIT(hdcmipp->Instance->P1EXCR1, DCMIPP_P1EXCR1_ENABLE);
5894 }
5895 else
5896 {
5897 return HAL_ERROR;
5898 }
5899
5900 return HAL_OK;
5901 }
5902 /**
5903 * @brief Disable the ISP Exposure for the selected DCMIPP Pipe
5904 * @param hdcmipp Pointer to DCMIPP handle
5905 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5906 * @retval HAL status
5907 */
HAL_DCMIPP_PIPE_DisableISPExposure(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)5908 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPExposure(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
5909 {
5910 /* Check handle validity */
5911 if (hdcmipp == NULL)
5912 {
5913 return HAL_ERROR;
5914 }
5915
5916 /* Check parameters */
5917 assert_param(IS_DCMIPP_PIPE(Pipe));
5918
5919 if (Pipe == DCMIPP_PIPE1)
5920 {
5921 CLEAR_BIT(hdcmipp->Instance->P1EXCR1, DCMIPP_P1EXCR1_ENABLE);
5922 }
5923 else
5924 {
5925 return HAL_ERROR;
5926 }
5927
5928 return HAL_OK;
5929 }
5930 /**
5931 * @brief Configure the ISP Contrast for the selected DCMIPP Pipe according to the user parameters
5932 * @param hdcmipp Pointer to DCMIPP handle
5933 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5934 * @param pContrastConfig pointer to the DCMIPP_ContrastConfTypeDef structure that contains contrast information
5935 * @retval HAL status
5936 */
HAL_DCMIPP_PIPE_SetISPCtrlContrastConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_ContrastConfTypeDef * pContrastConfig)5937 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetISPCtrlContrastConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
5938 const DCMIPP_ContrastConfTypeDef *pContrastConfig)
5939 {
5940 /* Check handle validity */
5941 if ((hdcmipp == NULL) || (pContrastConfig == NULL))
5942 {
5943 return HAL_ERROR;
5944 }
5945
5946 /* Check parameters */
5947 assert_param(IS_DCMIPP_PIPE(Pipe));
5948 assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_0));
5949 assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_32));
5950 assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_64));
5951 assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_96));
5952 assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_128));
5953 assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_160));
5954 assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_192));
5955 assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_224));
5956 assert_param(IS_DCMIPP_LUMINANCE(pContrastConfig->LUM_256));
5957
5958 if (Pipe == DCMIPP_PIPE1)
5959 {
5960
5961 MODIFY_REG(hdcmipp->Instance->P1CTCR1, DCMIPP_P1CTCR1_LUM0,
5962 (uint32_t)pContrastConfig->LUM_0 << DCMIPP_P1CTCR1_LUM0_Pos);
5963
5964 WRITE_REG(hdcmipp->Instance->P1CTCR2, (((uint32_t)pContrastConfig->LUM_32 << DCMIPP_P1CTCR2_LUM1_Pos) |
5965 ((uint32_t)pContrastConfig->LUM_64 << DCMIPP_P1CTCR2_LUM2_Pos) |
5966 ((uint32_t)pContrastConfig->LUM_96 << DCMIPP_P1CTCR2_LUM3_Pos) |
5967 ((uint32_t)pContrastConfig->LUM_128 << DCMIPP_P1CTCR2_LUM4_Pos)));
5968
5969 WRITE_REG(hdcmipp->Instance->P1CTCR3, (((uint32_t)pContrastConfig->LUM_160 << DCMIPP_P1CTCR3_LUM5_Pos) |
5970 ((uint32_t)pContrastConfig->LUM_192 << DCMIPP_P1CTCR3_LUM6_Pos) |
5971 ((uint32_t)pContrastConfig->LUM_224 << DCMIPP_P1CTCR3_LUM7_Pos) |
5972 ((uint32_t)pContrastConfig->LUM_256 << DCMIPP_P1CTCR3_LUM8_Pos)));
5973 }
5974 else
5975 {
5976 return HAL_ERROR;
5977 }
5978
5979 return HAL_OK;
5980 }
5981 /**
5982 * @brief Enable the ISP Contrast for the selected DCMIPP Pipe
5983 * @param hdcmipp Pointer to DCMIPP handle
5984 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
5985 * @retval HAL status
5986 */
HAL_DCMIPP_PIPE_EnableISPCtrlContrast(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)5987 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableISPCtrlContrast(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
5988 {
5989 /* Check handle validity */
5990 if (hdcmipp == NULL)
5991 {
5992 return HAL_ERROR;
5993 }
5994
5995 /* Check parameters */
5996 assert_param(IS_DCMIPP_PIPE(Pipe));
5997
5998 if (Pipe == DCMIPP_PIPE1)
5999 {
6000 SET_BIT(hdcmipp->Instance->P1CTCR1, DCMIPP_P1CTCR1_ENABLE);
6001 }
6002 else
6003 {
6004 return HAL_ERROR;
6005 }
6006
6007 return HAL_OK;
6008 }
6009 /**
6010 * @brief Disable the ISP Contrast for the selected DCMIPP Pipe
6011 * @param hdcmipp Pointer to DCMIPP handle
6012 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6013 * @retval HAL status
6014 */
HAL_DCMIPP_PIPE_DisableISPCtrlContrast(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6015 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableISPCtrlContrast(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6016 {
6017 /* Check handle validity */
6018 if (hdcmipp == NULL)
6019 {
6020 return HAL_ERROR;
6021 }
6022
6023 /* Check parameters */
6024 assert_param(IS_DCMIPP_PIPE(Pipe));
6025
6026 if (Pipe == DCMIPP_PIPE1)
6027 {
6028 CLEAR_BIT(hdcmipp->Instance->P1CTCR1, DCMIPP_P1CTCR1_ENABLE);
6029 }
6030 else
6031 {
6032 return HAL_ERROR;
6033 }
6034
6035 return HAL_OK;
6036 }
6037 /**
6038 * @}
6039 */
6040 /** @defgroup DCMIPP_PeripheralControl_Functions DCMIPP Peripheral Control Functions
6041 * @{
6042 */
6043 /**
6044 * @brief Reconfigure the Frame Rate for the selected pipe
6045 * @param hdcmipp Pointer to DCMIPP handle
6046 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6047 * @param FrameRate the new Frame Rate, can be a value from @ref DCMIPP_Frame_Rates
6048 * @retval HAL status
6049 */
HAL_DCMIPP_PIPE_SetFrameRate(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t FrameRate)6050 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetFrameRate(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t FrameRate)
6051 {
6052 /* Check Parameters */
6053 if (hdcmipp == NULL)
6054 {
6055 return HAL_ERROR;
6056 }
6057
6058 /* Check parameters */
6059 assert_param(IS_DCMIPP_PIPE(Pipe));
6060 assert_param(IS_DCMIPP_FRAME_RATE(FrameRate));
6061
6062 /* Set Frame Rate for the Pipe */
6063 if (Pipe == DCMIPP_PIPE0)
6064 {
6065 MODIFY_REG(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_FRATE, FrameRate);
6066 }
6067 else if (Pipe == DCMIPP_PIPE1)
6068 {
6069 MODIFY_REG(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_FRATE, FrameRate);
6070 }
6071 else if (Pipe == DCMIPP_PIPE2)
6072 {
6073 MODIFY_REG(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_FRATE, FrameRate);
6074 }
6075 else
6076 {
6077 return HAL_ERROR;
6078 }
6079
6080 return HAL_OK;
6081 }
6082 /**
6083 * @brief Reconfigure the Pitch for the selected pipe
6084 * @param hdcmipp Pointer to DCMIPP handle
6085 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6086 * @param LinePitch the new Pitch value.
6087 * @retval HAL status
6088 */
HAL_DCMIPP_PIPE_SetPitch(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t LinePitch)6089 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetPitch(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t LinePitch)
6090 {
6091 /* Check Parameters */
6092 if (hdcmipp == NULL)
6093 {
6094 return HAL_ERROR;
6095 }
6096
6097 /* Check parameters */
6098 assert_param(IS_DCMIPP_PIPE(Pipe));
6099 assert_param(IS_DCMIPP_PIXEL_PIPE_PITCH(LinePitch));
6100
6101 /* Set Pixel Pipe Pitch for the Pipe */
6102 if (Pipe == DCMIPP_PIPE1)
6103 {
6104 MODIFY_REG(hdcmipp->Instance->P1PPM0PR, DCMIPP_P1PPM0PR_PITCH, LinePitch << DCMIPP_P1PPM0PR_PITCH_Pos);
6105 }
6106 else if (Pipe == DCMIPP_PIPE2)
6107 {
6108 MODIFY_REG(hdcmipp->Instance->P2PPM0PR, DCMIPP_P2PPM0PR_PITCH, LinePitch << DCMIPP_P2PPM0PR_PITCH_Pos);
6109 }
6110 else
6111 {
6112 return HAL_ERROR;
6113 }
6114
6115 return HAL_OK;
6116 }
6117 /**
6118 * @brief Reconfigure the PixelPackerFormat for the selected pipe
6119 * @param hdcmipp Pointer to DCMIPP handle
6120 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6121 * @param PixelPackerFormat the new Pixel Packer Format value.
6122 * @retval HAL status
6123 */
HAL_DCMIPP_PIPE_SetPixelPackerFormat(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t PixelPackerFormat)6124 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetPixelPackerFormat(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
6125 uint32_t PixelPackerFormat)
6126 {
6127 /* Check Parameters */
6128 if (hdcmipp == NULL)
6129 {
6130 return HAL_ERROR;
6131 }
6132
6133 /* Check parameters */
6134 assert_param(IS_DCMIPP_PIPE(Pipe));
6135 assert_param(IS_DCMIPP_PIXEL_PACKER_FORMAT(PixelPackerFormat));
6136
6137 /* Set Pixel Pipe Pitch for the Pipe */
6138 if (Pipe == DCMIPP_PIPE1)
6139 {
6140 /* Configure the pixel packer */
6141 MODIFY_REG(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_FORMAT, PixelPackerFormat);
6142 }
6143 else if (Pipe == DCMIPP_PIPE2)
6144 {
6145 MODIFY_REG(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_FORMAT, PixelPackerFormat);
6146 }
6147 else
6148 {
6149 return HAL_ERROR;
6150 }
6151
6152 return HAL_OK;
6153 }
6154 /**
6155 * @brief Reconfigure Capture Mode for the selected pipe
6156 * @param hdcmipp Pointer to DCMIPP handle
6157 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6158 * @param CaptureMode the new Capture Mode, can be a value from @ref DCMIPP_Capture_Mode
6159 * @retval HAL status
6160 */
HAL_DCMIPP_PIPE_SetCaptureMode(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t CaptureMode)6161 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetCaptureMode(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t CaptureMode)
6162 {
6163 /* Check Parameters */
6164 if (hdcmipp == NULL)
6165 {
6166 return HAL_ERROR;
6167 }
6168
6169 assert_param(IS_DCMIPP_PIPE(Pipe));
6170 assert_param(IS_DCMIPP_CAPTURE_MODE(CaptureMode));
6171
6172
6173 /* Set Capture Mode */
6174 if (Pipe == DCMIPP_PIPE0)
6175 {
6176 MODIFY_REG(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTMODE, CaptureMode);
6177 }
6178 else if (Pipe == DCMIPP_PIPE1)
6179 {
6180 MODIFY_REG(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTMODE, CaptureMode);
6181 }
6182 else if (Pipe == DCMIPP_PIPE2)
6183 {
6184 MODIFY_REG(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTMODE, CaptureMode);
6185 }
6186 else
6187 {
6188 return HAL_ERROR;
6189 }
6190
6191 return HAL_OK;
6192 }
6193 /**
6194 * @brief Re-Enable Capture for the selected pipe
6195 * @param hdcmipp Pointer to DCMIPP handle
6196 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6197 * @retval HAL status
6198 */
HAL_DCMIPP_PIPE_EnableCapture(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6199 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableCapture(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6200 {
6201 /* Check Parameters */
6202 if (hdcmipp == NULL)
6203 {
6204 return HAL_ERROR;
6205 }
6206
6207 /* Request Capture for the chosen Pipe */
6208
6209 if (Pipe == DCMIPP_PIPE0)
6210 {
6211 SET_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
6212 }
6213 else if (Pipe == DCMIPP_PIPE1)
6214 {
6215 SET_BIT(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTREQ);
6216 }
6217 else if (Pipe == DCMIPP_PIPE2)
6218 {
6219 SET_BIT(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTREQ);
6220 }
6221 else
6222 {
6223 return HAL_ERROR;
6224 }
6225
6226 return HAL_OK;
6227 }
6228 /**
6229 * @brief Reconfigure the destination memory address for the selected pipe
6230 * @param hdcmipp Pointer to DCMIPP handle
6231 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6232 * @param Memory the destination address to be changed can be value from @ref DCMIPP_Memory.
6233 * @param DstAddress the new destination address
6234 * @retval HAL status
6235 */
HAL_DCMIPP_PIPE_SetMemoryAddress(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t Memory,uint32_t DstAddress)6236 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetMemoryAddress(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Memory,
6237 uint32_t DstAddress)
6238 {
6239 /* Check Parameters */
6240 if (hdcmipp == NULL)
6241 {
6242 return HAL_ERROR;
6243 }
6244
6245 assert_param(IS_DCMIPP_PIPE(Pipe));
6246 assert_param(IS_DCMIPP_MEMORY_ADDRESS(Memory));
6247
6248 /* Request Capture for the chosen Pipe */
6249
6250 if (Pipe == DCMIPP_PIPE0)
6251 {
6252 if (Memory == DCMIPP_MEMORY_ADDRESS_0)
6253 {
6254 /* Set Memory0 destination addresses for pipe0 */
6255 WRITE_REG(hdcmipp->Instance->P0PPM0AR1, DstAddress);
6256 }
6257 else
6258 {
6259 if ((hdcmipp->Instance->P0PPCR & DCMIPP_P0PPCR_DBM) == DCMIPP_P0PPCR_DBM)
6260 {
6261 /* Set Memory1 destination addresses for pipe0 */
6262 WRITE_REG(hdcmipp->Instance->P0PPM0AR2, DstAddress);
6263 }
6264 else
6265 {
6266 return HAL_ERROR;
6267 }
6268 }
6269 }
6270 else if (Pipe == DCMIPP_PIPE1)
6271 {
6272 if (Memory == DCMIPP_MEMORY_ADDRESS_0)
6273 {
6274 /* Set Memory0 destination addresses for pipe1 */
6275 WRITE_REG(hdcmipp->Instance->P1PPM0AR1, DstAddress);
6276 }
6277 else
6278 {
6279 /* Set Memory1 destination addresses for pipe1 */
6280 WRITE_REG(hdcmipp->Instance->P1PPM0AR2, DstAddress);
6281 }
6282 }
6283 else if (Pipe == DCMIPP_PIPE2)
6284 {
6285 if (Memory == DCMIPP_MEMORY_ADDRESS_0)
6286 {
6287 /* Set Memory0 destination addresses for pipe2 */
6288 WRITE_REG(hdcmipp->Instance->P2PPM0AR1, DstAddress);
6289 }
6290 else
6291 {
6292 /* Set Memory1 destination addresses for pipe2 */
6293 WRITE_REG(hdcmipp->Instance->P2PPM0AR2, DstAddress);
6294 }
6295 }
6296 else
6297 {
6298 return HAL_ERROR;
6299 }
6300
6301 return HAL_OK;
6302
6303 }
6304 /**
6305 * @brief Reconfigure the input pixel format for the selected pipe
6306 * @param hdcmipp Pointer to DCMIPP handle
6307 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6308 * @param InputPixelFormat new pixel format, can be a value from @ref DCMIPP_Format
6309 * @retval HAL status
6310 */
HAL_DCMIPP_PIPE_PARALLEL_SetInputPixelFormat(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t InputPixelFormat)6311 HAL_StatusTypeDef HAL_DCMIPP_PIPE_PARALLEL_SetInputPixelFormat(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
6312 uint32_t InputPixelFormat)
6313 {
6314 assert_param(IS_DCMIPP_PIPE(Pipe));
6315 assert_param(IS_DCMIPP_FORMAT(InputPixelFormat));
6316
6317 if (hdcmipp == NULL)
6318 {
6319 return HAL_ERROR;
6320 }
6321
6322 if (Pipe == DCMIPP_PIPE0)
6323 {
6324 /* Set Frame Rate */
6325 MODIFY_REG(hdcmipp->Instance->PRCR, DCMIPP_PRCR_FORMAT, InputPixelFormat);
6326 }
6327 else
6328 {
6329 return HAL_ERROR;
6330 }
6331
6332 return HAL_OK;
6333 }
6334 /**
6335 * @brief Set embedded synchronization delimiters unmasks.
6336 * @param hdcmipp Pointer to DCMIPP handle
6337 * @param SyncUnmask Pointer to a DCMIPP_EmbeddedSyncUnmaskTypeDef structure that contains
6338 * the embedded synchronization delimiters unmasks.
6339 * @retval HAL status
6340 */
HAL_DCMIPP_PARALLEL_SetSyncUnmask(DCMIPP_HandleTypeDef * hdcmipp,const DCMIPP_EmbeddedSyncUnmaskTypeDef * SyncUnmask)6341 HAL_StatusTypeDef HAL_DCMIPP_PARALLEL_SetSyncUnmask(DCMIPP_HandleTypeDef *hdcmipp,
6342 const DCMIPP_EmbeddedSyncUnmaskTypeDef *SyncUnmask)
6343 {
6344 uint32_t presur_reg;
6345 uint32_t prcr_reg;
6346
6347 /* Check pointer validity */
6348 if ((hdcmipp == NULL) || (SyncUnmask == NULL))
6349 {
6350 return HAL_ERROR;
6351 }
6352
6353 /* Check the DCMIPP State */
6354 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
6355 {
6356 prcr_reg = hdcmipp->Instance->PRCR;
6357 /* Check that parallel and Embedded synchronisation modes are configured */
6358 if (((prcr_reg & DCMIPP_PRCR_ESS) == DCMIPP_SYNCHRO_EMBEDDED) && \
6359 ((prcr_reg & DCMIPP_PRCR_ENABLE) == DCMIPP_PRCR_ENABLE))
6360 {
6361 /* Configure DCMIPP embedded synchronization unmask register */
6362 presur_reg = (((uint32_t)SyncUnmask->FrameStartUnmask << DCMIPP_PRESUR_FSU_Pos) | \
6363 ((uint32_t)SyncUnmask->LineStartUnmask << DCMIPP_PRESUR_LSU_Pos) | \
6364 ((uint32_t)SyncUnmask->LineEndUnmask << DCMIPP_PRESUR_LEU_Pos) | \
6365 ((uint32_t)SyncUnmask->FrameEndUnmask << DCMIPP_PRESUR_FEU_Pos));
6366
6367 WRITE_REG(hdcmipp->Instance->PRESUR, presur_reg);
6368 }
6369 else
6370 {
6371 return HAL_ERROR;
6372 }
6373 }
6374 else
6375 {
6376 return HAL_ERROR;
6377 }
6378
6379 return HAL_OK;
6380 }
6381 /**
6382 * @brief Enable the swapping of color components for the specified DCMIPP pipe.
6383 * @param hdcmipp Pointer to DCMIPP handle
6384 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6385 * @retval HAL status
6386 */
HAL_DCMIPP_PIPE_EnableComponentsSwap(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6387 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableComponentsSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6388 {
6389 assert_param(IS_DCMIPP_PIPE(Pipe));
6390
6391 if (hdcmipp == NULL)
6392 {
6393 return HAL_ERROR;
6394 }
6395
6396 if ((Pipe == DCMIPP_PIPE1) || (Pipe == DCMIPP_PIPE2))
6397 {
6398 /* Verify DCMIPP State */
6399 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
6400 {
6401 SET_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_SWAPRB);
6402 }
6403 else
6404 {
6405 return HAL_ERROR;
6406 }
6407 }
6408 else
6409 {
6410 return HAL_ERROR;
6411 }
6412
6413 return HAL_OK;
6414 }
6415 /**
6416 * @brief Disable the swapping of color components for the specified DCMIPP pipe.
6417 * @param hdcmipp Pointer to DCMIPP handle
6418 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6419 * @retval HAL status
6420 */
HAL_DCMIPP_PIPE_DisableComponentsSwap(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6421 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableComponentsSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6422 {
6423 assert_param(IS_DCMIPP_PIPE(Pipe));
6424
6425 if (hdcmipp == NULL)
6426 {
6427 return HAL_ERROR;
6428 }
6429
6430 if ((Pipe == DCMIPP_PIPE1) || (Pipe == DCMIPP_PIPE2))
6431 {
6432 /* Verify DCMIPP State */
6433 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
6434 {
6435 CLEAR_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_SWAPRB);
6436 }
6437 else
6438 {
6439 return HAL_ERROR;
6440 }
6441 }
6442 else
6443 {
6444 return HAL_ERROR;
6445 }
6446
6447 return HAL_OK;
6448 }
6449 /**
6450 * @brief Enable the swapping of red and blue color components for the specified DCMIPP pipe.
6451 * @param hdcmipp Pointer to DCMIPP handle
6452 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6453 * @retval HAL status.
6454 */
HAL_DCMIPP_PIPE_EnableRedBlueSwap(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6455 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableRedBlueSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6456 {
6457 assert_param(IS_DCMIPP_PIPE(Pipe));
6458
6459 if (hdcmipp == NULL)
6460 {
6461 return HAL_ERROR;
6462 }
6463
6464 /* Verify DCMIPP State */
6465 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
6466 {
6467 if (Pipe == DCMIPP_PIPE1)
6468 {
6469 SET_BIT(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_SWAPRB);
6470 }
6471 else if (Pipe == DCMIPP_PIPE2)
6472 {
6473 SET_BIT(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_SWAPRB);
6474 }
6475 else
6476 {
6477 return HAL_ERROR;
6478 }
6479 }
6480
6481 return HAL_OK;
6482 }
6483 /**
6484 * @brief Disable the swapping of red and blue color components for the specified DCMIPP pipe.
6485 * @param hdcmipp Pointer to DCMIPP handle
6486 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6487 * @retval HAL status.
6488 */
HAL_DCMIPP_PIPE_DisableRedBlueSwap(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6489 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableRedBlueSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6490 {
6491 assert_param(IS_DCMIPP_PIPE(Pipe));
6492
6493 if (hdcmipp == NULL)
6494 {
6495 return HAL_ERROR;
6496 }
6497
6498 /* Verify DCMIPP State */
6499 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
6500 {
6501 if (Pipe == DCMIPP_PIPE1)
6502 {
6503 CLEAR_BIT(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_SWAPRB);
6504 }
6505 else if (Pipe == DCMIPP_PIPE2)
6506 {
6507 CLEAR_BIT(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_SWAPRB);
6508 }
6509 else
6510 {
6511 return HAL_ERROR;
6512 }
6513 }
6514
6515 return HAL_OK;
6516 }
6517 /**
6518 * @brief Enable the swapping of YUV color components for the specified DCMIPP pipe.
6519 * @param hdcmipp Pointer to DCMIPP handle
6520 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6521 * @retval HAL status.
6522 */
HAL_DCMIPP_PIPE_EnableYUVSwap(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6523 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableYUVSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6524 {
6525 assert_param(IS_DCMIPP_PIPE(Pipe));
6526
6527 if (hdcmipp == NULL)
6528 {
6529 return HAL_ERROR;
6530 }
6531
6532 /* Verify DCMIPP State */
6533 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
6534 {
6535 if (Pipe == DCMIPP_PIPE0)
6536 {
6537 SET_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_SWAPYUV);
6538 }
6539 else
6540 {
6541 return HAL_ERROR;
6542 }
6543 }
6544
6545 return HAL_OK;
6546 }
6547 /**
6548 * @brief Disable the swapping of YUV color components for the specified DCMIPP pipe.
6549 * @param hdcmipp Pointer to DCMIPP handle
6550 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6551 * @retval HAL status.
6552 */
HAL_DCMIPP_PIPE_DisableYUVSwap(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6553 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableYUVSwap(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6554 {
6555 assert_param(IS_DCMIPP_PIPE(Pipe));
6556
6557 if (hdcmipp == NULL)
6558 {
6559 return HAL_ERROR;
6560 }
6561
6562 /* Verify DCMIPP State */
6563 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
6564 {
6565 if (Pipe == DCMIPP_PIPE0)
6566 {
6567 CLEAR_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_SWAPYUV);
6568 }
6569 else
6570 {
6571 return HAL_ERROR;
6572 }
6573 }
6574
6575 return HAL_OK;
6576 }
6577 /**
6578 * @}
6579 */
6580 /** @defgroup DCMIPP_Line_Event_Functions DCMIPP Line Event Functions
6581 * @{
6582 */
6583 /**
6584 * Lines Event Feature:
6585 * - HAL_DCMIPP_PIPE_EnableLineEvent() : Enable the Line event for the selected Line.
6586 * - HAL_DCMIPP_PIPE_DisableLineEvent() : Disable the Line event for the selected Line.
6587 * Lines Wrapping Feature:
6588 * - HAL_DCMIPP_PIPE_SetLineWrappingConfig(): Configure the Line Mult Address Wrapping.
6589 * - HAL_DCMIPP_PIPE_EnableLineWrapping() : Enable the Line Mult Address Wrapping.
6590 * - HAL_DCMIPP_PIPE_DisableLineWrapping() : Disable the Line Mult Address Wrapping.
6591 */
6592 /**
6593 * @brief Configures the position of the line interrupt.
6594 * @param hdcmipp Pointer to DCMIPP handle
6595 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6596 * @param Line Line Interrupt Position.
6597 * @retval HAL status
6598 */
HAL_DCMIPP_PIPE_EnableLineEvent(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t Line)6599 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLineEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t Line)
6600 {
6601 assert_param(IS_DCMIPP_PIPE(Pipe));
6602 assert_param(IS_DCMIPP_PIPE_MULTILINE(Line));
6603
6604 if (Pipe == DCMIPP_PIPE0)
6605 {
6606 /* Set MultiLine configuration */
6607 MODIFY_REG(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_LINEMULT, Line);
6608
6609 /* Enable Multiline Interrupt */
6610 __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LINE);
6611 }
6612 else if (Pipe == DCMIPP_PIPE1)
6613 {
6614 /* Set MultiLine configuration */
6615 MODIFY_REG(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_LINEMULT, Line);
6616
6617 /* Enable Multiline Interrupt */
6618 __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE1_LINE);
6619 }
6620 else if (Pipe == DCMIPP_PIPE2)
6621 {
6622 /* Set MultiLine configuration */
6623 MODIFY_REG(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_LINEMULT, Line);
6624
6625 /* Enable Multiline Interrupt */
6626 __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE2_LINE);
6627 }
6628 else
6629 {
6630 return HAL_ERROR;
6631 }
6632
6633 return HAL_OK;
6634 }
6635 /**
6636 * @brief Disable the the line event interrupt.
6637 * @param hdcmipp Pointer to DCMIPP handle
6638 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6639 * @retval HAL status
6640 */
HAL_DCMIPP_PIPE_DisableLineEvent(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6641 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLineEvent(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6642 {
6643 assert_param(IS_DCMIPP_PIPE(Pipe));
6644
6645 /* Disable Multiline Interrupt */
6646 if (Pipe == DCMIPP_PIPE0)
6647 {
6648 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_LINE);
6649 }
6650 else if (Pipe == DCMIPP_PIPE1)
6651 {
6652 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE1_LINE);
6653 }
6654 else if (Pipe == DCMIPP_PIPE2)
6655 {
6656 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE2_LINE);
6657 }
6658 else
6659 {
6660 return HAL_ERROR;
6661 }
6662
6663 return HAL_OK;
6664 }
6665 /**
6666 * @brief Configure the DCMIPP Line Mult Address Wrapping for the the specified DCMIPP pipe
6667 * @param hdcmipp Pointer to DCMIPP handle
6668 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6669 * @param AddressWrap Line Mult Address Wrapping Modulo can be a value from @ref DCMIPP_LineWrapAddress
6670 * @retval HAL status
6671 */
HAL_DCMIPP_PIPE_SetLineWrappingConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t AddressWrap)6672 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetLineWrappingConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
6673 uint32_t AddressWrap)
6674 {
6675 if (hdcmipp == NULL)
6676 {
6677 return HAL_ERROR;
6678 }
6679
6680 /* Check Parameters */
6681 assert_param(IS_DCMIPP_PIPE(Pipe));
6682 assert_param(IS_DCMIPP_ADDRESS_WRAP(AddressWrap));
6683
6684 /* Line Wrappping Modulo configuration */
6685 if (Pipe == DCMIPP_PIPE1)
6686 {
6687 MODIFY_REG(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_LMAWM, AddressWrap);
6688 }
6689 else if (Pipe == DCMIPP_PIPE2)
6690 {
6691 MODIFY_REG(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_LMAWM, AddressWrap);
6692 }
6693 else
6694 {
6695 return HAL_ERROR;
6696 }
6697
6698 return HAL_OK;
6699 }
6700 /**
6701 * @brief Enable the DCMIPP Line Mult Address Wrapping for the chosen Pipe
6702 * @param hdcmipp Pointer to DCMIPP handle
6703 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6704 * @retval HAL status
6705 */
HAL_DCMIPP_PIPE_EnableLineWrapping(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6706 HAL_StatusTypeDef HAL_DCMIPP_PIPE_EnableLineWrapping(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6707 {
6708
6709 if (hdcmipp == NULL)
6710 {
6711 return HAL_ERROR;
6712 }
6713
6714 /* Check parameters */
6715 assert_param(IS_DCMIPP_PIPE(Pipe));
6716
6717 /* Line Wrappping Modulo Enable */
6718 if (Pipe == DCMIPP_PIPE1)
6719 {
6720 SET_BIT(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_LMAWE);
6721 }
6722 else if (Pipe == DCMIPP_PIPE2)
6723 {
6724 SET_BIT(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_LMAWE);
6725 }
6726 else
6727 {
6728 return HAL_ERROR;
6729 }
6730
6731 return HAL_OK;
6732 }
6733 /**
6734 * @brief Disable the DCMIPP Line Mult Address Wrapping for the the specified DCMIPP pipe
6735 * @param hdcmipp Pointer to DCMIPP handle
6736 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6737 * @retval HAL status
6738 */
HAL_DCMIPP_PIPE_DisableLineWrapping(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6739 HAL_StatusTypeDef HAL_DCMIPP_PIPE_DisableLineWrapping(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6740 {
6741 if (hdcmipp == NULL)
6742 {
6743 return HAL_ERROR;
6744 }
6745
6746 /* Check parameters */
6747 assert_param(IS_DCMIPP_PIPE(Pipe));
6748
6749 /* Line Multt Address Wrapping Enable */
6750 if (Pipe == DCMIPP_PIPE1)
6751 {
6752 CLEAR_BIT(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_LMAWE);
6753 }
6754 else if (Pipe == DCMIPP_PIPE2)
6755 {
6756 CLEAR_BIT(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_LMAWE);
6757 }
6758 else
6759 {
6760 return HAL_ERROR;
6761 }
6762
6763 return HAL_OK;
6764 }
6765 /**
6766 * A set of functions allowing to configure the DCMIPP CSI pipe peripheral:
6767 * - HAL_DCMIPP_PIPE_CSI_EnableShare() : Enable sharing the image processing block for PIPE2
6768 * - HAL_DCMIPP_PIPE_CSI_DisableShare() : Disable sharing the image processing block for PIPE2
6769 * - HAL_DCMIPP_PIPE_CSI_ForceDataTypeFormat() : Forces a specific data type format
6770 * - HAL_DCMIPP_PIPE_CSI_EnableHeader() : Enable the header dump for PIPE0
6771 * - HAL_DCMIPP_PIPE_CSI_DisableHeader() : Disable the header dump for PIPE0
6772 */
6773 /**
6774 * @brief Enable Share between DCMIPP_PIPE1 and DCMIPP_PIPE2
6775 * @param hdcmipp Pointer to DCMIPP handle
6776 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6777 * @retval HAL status
6778 */
HAL_DCMIPP_PIPE_CSI_EnableShare(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6779 HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_EnableShare(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6780 {
6781 assert_param(IS_DCMIPP_PIPE(Pipe));
6782 uint32_t tmp1;
6783 uint32_t tmp2;
6784
6785 if (Pipe == DCMIPP_PIPE2)
6786 {
6787 /* check that Pipe1 and pipe2 are disabled */
6788 tmp1 = hdcmipp->Instance->P2FSCR;
6789 tmp2 = hdcmipp->Instance->P1FSCR;
6790 if (((tmp1 & DCMIPP_P2FSCR_PIPEN) == DCMIPP_P2FSCR_PIPEN) || ((tmp2 & DCMIPP_P1FSCR_PIPEN) == DCMIPP_P1FSCR_PIPEN))
6791 {
6792 return HAL_ERROR;
6793 }
6794 else
6795 {
6796 /* Pipe2 receives the same data as Pipe1 */
6797 CLEAR_BIT(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_PIPEDIFF);
6798 }
6799 }
6800 else
6801 {
6802 return HAL_ERROR;
6803 }
6804
6805 return HAL_OK;
6806 }
6807 /**
6808 * @brief Disable Share between DCMIPP_PIPE1 and DCMIPP_PIPE2
6809 * @param hdcmipp Pointer to DCMIPP handle
6810 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6811 * @retval HAL status
6812 */
HAL_DCMIPP_PIPE_CSI_DisableShare(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6813 HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_DisableShare(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6814 {
6815 assert_param(IS_DCMIPP_PIPE(Pipe));
6816 uint32_t tmp1;
6817 uint32_t tmp2;
6818
6819 if (Pipe == DCMIPP_PIPE2)
6820 {
6821 tmp1 = hdcmipp->Instance->P2FSCR;
6822 tmp2 = hdcmipp->Instance->P1FSCR;
6823 /* check that Pipe1 and pipe2 are disabled */
6824 if (((tmp1 & DCMIPP_P2FSCR_PIPEN) == DCMIPP_P2FSCR_PIPEN) || ((tmp2 & DCMIPP_P1FSCR_PIPEN) == DCMIPP_P1FSCR_PIPEN))
6825 {
6826 return HAL_ERROR;
6827 }
6828 else
6829 {
6830 /* Differentiates Pipe2 from pipe1 */
6831 SET_BIT(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_PIPEDIFF);
6832 }
6833 }
6834 else
6835 {
6836 return HAL_ERROR;
6837 }
6838
6839 return HAL_OK;
6840 }
6841 /**
6842 * @brief Force Data Type Format for the selected Pipe
6843 * @param hdcmipp Pointer to DCMIPP handle
6844 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6845 * @param DataTypeFormat Specifies the Data Type Format, can be a value from @ref DCMIPP_DataType
6846 * @retval HAL status
6847 */
HAL_DCMIPP_PIPE_CSI_ForceDataTypeFormat(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t DataTypeFormat)6848 HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_ForceDataTypeFormat(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
6849 uint32_t DataTypeFormat)
6850 {
6851 assert_param(IS_DCMIPP_PIPE(Pipe));
6852 assert_param(IS_DCMIPP_DATA_TYPE(DataTypeFormat));
6853
6854 if (Pipe == DCMIPP_PIPE1)
6855 {
6856 /* Force data type format */
6857 MODIFY_REG(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_FDTF, DataTypeFormat << DCMIPP_P1FSCR_FDTF_Pos);
6858
6859 /* Force data type format enable */
6860 SET_BIT(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_FDTFEN);
6861 }
6862 else if (Pipe == DCMIPP_PIPE2)
6863 {
6864 /* Check that PIPEDIFF is enabled */
6865 if ((hdcmipp->Instance->P2FSCR & DCMIPP_P1FSCR_PIPEDIFF) == DCMIPP_P1FSCR_PIPEDIFF)
6866 {
6867 /* Force data type format */
6868 MODIFY_REG(hdcmipp->Instance->P2FSCR, DCMIPP_P1FSCR_FDTF, DataTypeFormat << DCMIPP_P1FSCR_FDTF_Pos);
6869
6870 /* Force data type format enable */
6871 SET_BIT(hdcmipp->Instance->P2FSCR, DCMIPP_P1FSCR_FDTFEN);
6872 }
6873 else
6874 {
6875 return HAL_ERROR;
6876 }
6877 }
6878 else
6879 {
6880 return HAL_ERROR;
6881 }
6882
6883 return HAL_OK;
6884 }
6885 /**
6886 * @brief Reconfigure the Data Type Mode
6887 * @param hdcmipp Pointer to DCMIPP handle
6888 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6889 * @param DataTypeMode Specifies the Data Type Mode, can be a value from @ref DCMIPP_DataTypeMode
6890 * @retval HAL status
6891 */
HAL_DCMIPP_PIPE_CSI_SetDTMode(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t DataTypeMode)6892 HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_SetDTMode(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DataTypeMode)
6893 {
6894 assert_param(IS_DCMIPP_PIPE(Pipe));
6895 assert_param(IS_DCMIPP_DATA_TYPE_MODE(DataTypeMode));
6896
6897 if (Pipe == DCMIPP_PIPE0)
6898 {
6899 MODIFY_REG(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_DTMODE, DataTypeMode << DCMIPP_P0FSCR_DTMODE_Pos);
6900 }
6901 else if (Pipe == DCMIPP_PIPE1)
6902 {
6903 MODIFY_REG(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_DTMODE, DataTypeMode << DCMIPP_P1FSCR_DTMODE_Pos);
6904 }
6905 else
6906 {
6907 return HAL_ERROR;
6908 }
6909
6910 return HAL_OK;
6911 }
6912 /**
6913 * @brief Reconfigure the Data Type Selection
6914 * @param hdcmipp Pointer to DCMIPP handle
6915 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6916 * @param DataTypeID Specifies the Data Type ID, can be a value from @ref DCMIPP_DataTypeSelection
6917 * @param DataType Specifies the Data Type Format, can be a value from @ref DCMIPP_DataType
6918 * @retval HAL status
6919 */
HAL_DCMIPP_PIPE_CSI_SetDTSelection(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t DataTypeID,uint32_t DataType)6920 HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_SetDTSelection(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DataTypeID,
6921 uint32_t DataType)
6922 {
6923 uint32_t pxfscr_dtid_Msk;
6924
6925 assert_param(IS_DCMIPP_PIPE(Pipe));
6926 assert_param(IS_DCMIPP_DATA_TYPE(DataType));
6927
6928 if (DataTypeID == DCMIPP_DTSELECT_IDA)
6929 {
6930 pxfscr_dtid_Msk = DCMIPP_P0FSCR_DTIDA_Msk;
6931 }
6932 else /* DATA_TYPE_SELECTION_IDB */
6933 {
6934 pxfscr_dtid_Msk = DCMIPP_P0FSCR_DTIDB_Pos;
6935 }
6936
6937 if (Pipe == DCMIPP_PIPE0)
6938 {
6939 MODIFY_REG(hdcmipp->Instance->P0FSCR, pxfscr_dtid_Msk, DataType << DataTypeID);
6940 }
6941 else if (Pipe == DCMIPP_PIPE1)
6942 {
6943 MODIFY_REG(hdcmipp->Instance->P1FSCR, pxfscr_dtid_Msk, DataType << DataTypeID);
6944 }
6945 else if (Pipe == DCMIPP_PIPE2)
6946 {
6947 if (DataTypeID == DCMIPP_DTSELECT_IDA)
6948 {
6949 MODIFY_REG(hdcmipp->Instance->P2FSCR, pxfscr_dtid_Msk, DataType << DataTypeID);
6950 }
6951 else
6952 {
6953 return HAL_ERROR;
6954 }
6955 }
6956 else
6957 {
6958 return HAL_ERROR;
6959 }
6960
6961 return HAL_OK;
6962 }
6963 /**
6964 * @brief Enable CSI Header dump for the selected DCMIPP Pipe
6965 * @param hdcmipp Pointer to DCMIPP handle
6966 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6967 * @retval HAL status
6968 */
HAL_DCMIPP_PIPE_CSI_EnableHeader(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6969 HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_EnableHeader(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6970 {
6971 assert_param(IS_DCMIPP_PIPE(Pipe));
6972
6973 if (Pipe == DCMIPP_PIPE0)
6974 {
6975 SET_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_HEADEREN);
6976 }
6977 else
6978 {
6979 return HAL_ERROR;
6980 }
6981
6982 return HAL_OK;
6983 }
6984 /**
6985 * @brief Disable CSI Header dump for the selected DCMIPP Pipe
6986 * @param hdcmipp Pointer to DCMIPP handle
6987 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
6988 * @retval HAL status
6989 */
HAL_DCMIPP_PIPE_CSI_DisableHeader(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)6990 HAL_StatusTypeDef HAL_DCMIPP_PIPE_CSI_DisableHeader(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
6991 {
6992 assert_param(IS_DCMIPP_PIPE(Pipe));
6993
6994 if (Pipe == DCMIPP_PIPE0)
6995 {
6996 CLEAR_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_HEADEREN);
6997 }
6998 else
6999 {
7000 return HAL_ERROR;
7001 }
7002
7003 return HAL_OK;
7004 }
7005 /**
7006 * @}
7007 */
7008 /** @defgroup DCMIPP_Frame_Counter_Functions DCMIPP Frame Counter Functions
7009 * @{
7010 */
7011 /**
7012 * @brief Associate the frame counter to the selected DCMIPP pipe.
7013 * @param hdcmipp Pointer to DCMIPP handle
7014 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7015 * @retval HAL status
7016 */
HAL_DCMIPP_PIPE_SetFrameCounterConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)7017 HAL_StatusTypeDef HAL_DCMIPP_PIPE_SetFrameCounterConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
7018 {
7019 assert_param(IS_DCMIPP_PIPE(Pipe));
7020
7021 /* Check pointer validity */
7022 if (hdcmipp == NULL)
7023 {
7024 return HAL_ERROR;
7025 }
7026
7027 /* Check parameters */
7028 assert_param(IS_DCMIPP_PIPE(Pipe));
7029
7030 /* Check the DCMIPP State */
7031 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
7032 {
7033 /* Configure Pipe Selection for the frame counter */
7034 MODIFY_REG(hdcmipp->Instance->CMCR, DCMIPP_CMCR_PSFC, Pipe << DCMIPP_CMCR_PSFC_Pos);
7035 }
7036 else
7037 {
7038 return HAL_ERROR;
7039 }
7040
7041 return HAL_OK;
7042 }
7043 /**
7044 * @brief Reset the DCMIPP Pipe frame counter
7045 * @param hdcmipp Pointer to DCMIPP handle
7046 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7047 * @retval HAL status
7048 */
HAL_DCMIPP_PIPE_ResetFrameCounter(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)7049 HAL_StatusTypeDef HAL_DCMIPP_PIPE_ResetFrameCounter(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
7050 {
7051
7052 /* Check pointer validity */
7053 if (hdcmipp == NULL)
7054 {
7055 return HAL_ERROR;
7056 }
7057
7058 /* Check parameters */
7059 assert_param(IS_DCMIPP_PIPE(Pipe));
7060
7061 /* Check the DCMIPP State */
7062 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
7063 {
7064 /* Clear Frame counter */
7065 SET_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_CFC);
7066 }
7067 else
7068 {
7069 return HAL_ERROR;
7070 }
7071
7072 return HAL_OK;
7073 }
7074 /**
7075 * @brief Read the DCMIPP frame counter
7076 * @param hdcmipp Pointer to DCMIPP handle
7077 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7078 * @param pCounter pointer to store the value of the frame counter
7079 * @retval HAL status
7080 */
HAL_DCMIPP_PIPE_ReadFrameCounter(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t * pCounter)7081 HAL_StatusTypeDef HAL_DCMIPP_PIPE_ReadFrameCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
7082 uint32_t *pCounter)
7083 {
7084
7085 /* Check parameters */
7086 assert_param(IS_DCMIPP_PIPE(Pipe));
7087
7088 /* Check pointer validity */
7089 if ((hdcmipp == NULL) || (pCounter == NULL))
7090 {
7091 return HAL_ERROR;
7092 }
7093
7094 /* Check the DCMIPP State */
7095 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
7096 {
7097 /* Read frame counter */
7098 *pCounter = READ_REG(hdcmipp->Instance->CMFRCR);
7099 }
7100 else
7101 {
7102 return HAL_ERROR;
7103 }
7104
7105 return HAL_OK;
7106 }
7107 /**
7108 * @}
7109 */
7110
7111 /** @defgroup DCMIPP_Data_Counter_Functions DCMIPP Data Counter Functions
7112 * @{
7113 */
7114 /**
7115 * @brief Read Number of data dumped during the frame.
7116 * @param hdcmipp Pointer to DCMIPP handle
7117 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7118 * @param pCounter pointer to amount of word transferred
7119 * @note Data Counter is available only on DCMIPP_PIPE0. The counter saturates at 0x3FFFFFF.
7120 * @note Granularity is 32-bit for all the formats except for the
7121 * byte stream formats (e.g. JPEG) having byte granularity
7122 * @retval Status
7123 */
HAL_DCMIPP_PIPE_GetDataCounter(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t * pCounter)7124 HAL_StatusTypeDef HAL_DCMIPP_PIPE_GetDataCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
7125 uint32_t *pCounter)
7126 {
7127 /* Check parameters */
7128 assert_param(IS_DCMIPP_PIPE(Pipe));
7129
7130 /* Check pointer validity */
7131 if ((hdcmipp == NULL) || (pCounter == NULL))
7132 {
7133 return HAL_ERROR;
7134 }
7135
7136 /* Check the DCMIPP State */
7137 if (hdcmipp->State == HAL_DCMIPP_STATE_READY)
7138 {
7139 /* Read Pipe0 dump counter register */
7140 *pCounter = READ_REG(hdcmipp->Instance->P0DCCNTR);
7141 }
7142 else
7143 {
7144 return HAL_ERROR;
7145 }
7146
7147 return HAL_OK;
7148 }
7149 /**
7150 * @brief Get the Statistic accumulated value for the selected module
7151 * @param hdcmipp Pointer to DCMIPP handle
7152 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7153 * @param ModuleID Specifies the Module ID, can be a value from @ref DCMIPP_Statistics_Extraction_Module_ID.
7154 * @param pCounter pointer to receive the accumulated value
7155 * @retval HAL status
7156 */
HAL_DCMIPP_PIPE_GetISPAccumulatedStatisticsCounter(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint8_t ModuleID,uint32_t * pCounter)7157 HAL_StatusTypeDef HAL_DCMIPP_PIPE_GetISPAccumulatedStatisticsCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
7158 uint8_t ModuleID, uint32_t *pCounter)
7159 {
7160
7161 /* Check handle validity */
7162 if ((hdcmipp == NULL) || (pCounter == NULL))
7163 {
7164 return HAL_ERROR;
7165 }
7166
7167 /* Check parameters */
7168 assert_param(IS_DCMIPP_PIPE(Pipe));
7169 assert_param(IS_DCMIPP_STAT_EXTRACTION_MODULE(ModuleID));
7170
7171 if (Pipe == DCMIPP_PIPE1)
7172 {
7173 switch (ModuleID)
7174 {
7175 case DCMIPP_STATEXT_MODULE1:
7176 *pCounter = (READ_REG(hdcmipp->Instance->P1ST1SR & DCMIPP_P1ST1SR_ACCU));
7177 break;
7178 case DCMIPP_STATEXT_MODULE2:
7179 *pCounter = (READ_REG(hdcmipp->Instance->P1ST2SR & DCMIPP_P1ST2SR_ACCU));
7180 break;
7181 case DCMIPP_STATEXT_MODULE3:
7182 *pCounter = (READ_REG(hdcmipp->Instance->P1ST3SR & DCMIPP_P1ST3SR_ACCU));
7183 break;
7184 default:
7185 break;
7186 }
7187 }
7188 else
7189 {
7190 return HAL_ERROR;
7191 }
7192
7193 return HAL_OK;
7194 }
7195 /**
7196 * @brief Get the current operating mode of the DCMIPP
7197 * @param hdcmipp Pointer to DCMIPP handle
7198 * @retval Returns the current operating mode of the DCMIPP can be a value from @ref DCMIPP_modes.
7199 */
HAL_DCMIPP_GetMode(const DCMIPP_HandleTypeDef * hdcmipp)7200 uint32_t HAL_DCMIPP_GetMode(const DCMIPP_HandleTypeDef *hdcmipp)
7201 {
7202 /* Check parameters */
7203 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
7204
7205 /* Read the configured Mode */
7206 return READ_BIT(hdcmipp->Instance->CMCR, DCMIPP_CMCR_INSEL) ;
7207 }
7208 /**
7209 * @brief Get the destination address of the last captured frame
7210 * @param hdcmipp Pointer to DCMIPP handle
7211 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7212 * @param MemoryAddress Specifies the memory address to be retrieved , can be a value from @ref DCMIPP_Memory
7213 * @retval Returns the last destination address.
7214 */
HAL_DCMIPP_PIPE_GetMemoryAddress(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t MemoryAddress)7215 uint32_t HAL_DCMIPP_PIPE_GetMemoryAddress(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t MemoryAddress)
7216 {
7217 /* Check parameters */
7218 assert_param(IS_DCMIPP_PIPE(Pipe));
7219 assert_param(IS_DCMIPP_MEMORY_ADDRESS(MemoryAddress));
7220 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
7221
7222 /* Get the memory address status */
7223 if (Pipe == DCMIPP_PIPE0)
7224 {
7225 /* DCMIPP Pipe0 status Memory0 address */
7226 return READ_REG(hdcmipp->Instance->P0STM0AR);
7227 }
7228 else if (Pipe == DCMIPP_PIPE1)
7229 {
7230 if (MemoryAddress == DCMIPP_MEMORY_ADDRESS_0)
7231 {
7232 /* DCMIPP Pipe1 status Memory0 address */
7233 return READ_REG(hdcmipp->Instance->P1STM0AR);
7234 }
7235 else if (MemoryAddress == DCMIPP_MEMORY_ADDRESS_1)
7236 {
7237 /* DCMIPP Pipe1 status Memory1 address */
7238 return READ_REG(hdcmipp->Instance->P1STM1AR);
7239 }
7240 else /* DCMIPP_MEMORY2_ADDRESS */
7241 {
7242 return READ_REG(hdcmipp->Instance->P1STM2AR);
7243 }
7244 }
7245 else
7246 {
7247 /* DCMIPP Pipe2 status Memory0 address */
7248 return READ_REG(hdcmipp->Instance->P2STM0AR);
7249 }
7250 }
7251 /**
7252 * @}
7253 */
7254 /** @defgroup DCMIPP_Exported_Functions_Group6 Peripheral get config functions
7255 * @{
7256 */
7257 /**
7258 * @brief Retrieve the ISP decimation configuration for a specified DCMIPP pipe.
7259 * @param hdcmipp Pointer to DCMIPP handle
7260 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7261 * @param pDecConfig Pointer to a DCMIPP_DecimationConfTypeDef structure that will be
7262 * filled with the decimation configuration of the specified pipe.
7263 * @retval None
7264 */
HAL_DCMIPP_PIPE_GetISPDecimationConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,DCMIPP_DecimationConfTypeDef * pDecConfig)7265 void HAL_DCMIPP_PIPE_GetISPDecimationConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
7266 DCMIPP_DecimationConfTypeDef *pDecConfig)
7267 {
7268 uint32_t p1decr;
7269 /* Check parameters */
7270 assert_param(IS_DCMIPP_PIPE(Pipe));
7271
7272 if (Pipe == DCMIPP_PIPE1)
7273 {
7274 p1decr = READ_REG(hdcmipp->Instance->P1DECR);
7275 pDecConfig->HRatio = (p1decr & DCMIPP_P1DECR_HDEC);
7276 pDecConfig->VRatio = (p1decr & DCMIPP_P1DECR_VDEC);
7277 }
7278 }
7279
7280 /**
7281 * @brief Retrieve the ISP control statistic extraction configuration for a specified DCMIPP pipe and module.
7282 * @param hdcmipp Pointer to DCMIPP handle
7283 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7284 * @param ModuleID Specifies the Module ID, can be a value from
7285 * DCMIPP_Statistics_Extraction_Module_ID.
7286 * @param pStatisticExtractionConfig Pointer to a DCMIPP_StatisticExtractionConfTypeDef structure
7287 * that will be filled with the statistic extraction configuration
7288 * of the specified module.
7289 * @retval None
7290 */
HAL_DCMIPP_PIPE_GetISPStatisticExtractionConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint8_t ModuleID,DCMIPP_StatisticExtractionConfTypeDef * pStatisticExtractionConfig)7291 void HAL_DCMIPP_PIPE_GetISPStatisticExtractionConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
7292 uint8_t ModuleID,
7293 DCMIPP_StatisticExtractionConfTypeDef
7294 *pStatisticExtractionConfig)
7295 {
7296 uint32_t tmp;
7297 /* Check parameters */
7298 assert_param(IS_DCMIPP_PIPE(Pipe));
7299
7300 if (Pipe == DCMIPP_PIPE1)
7301 {
7302 switch (ModuleID)
7303 {
7304 case DCMIPP_STATEXT_MODULE1:
7305 tmp = READ_REG(hdcmipp->Instance->P1ST1CR);
7306 break;
7307 case DCMIPP_STATEXT_MODULE2:
7308 tmp = READ_REG(hdcmipp->Instance->P1ST2CR);
7309 break;
7310 default:
7311 /* DCMIPP_STATEXT_MODULE3 */
7312 tmp = READ_REG(hdcmipp->Instance->P1ST3CR);
7313 break;
7314 }
7315
7316 pStatisticExtractionConfig->Bins = ((tmp & DCMIPP_P1ST1CR_BINS));
7317 pStatisticExtractionConfig->Mode = ((tmp & DCMIPP_P1ST1CR_MODE));
7318 pStatisticExtractionConfig->Source = ((tmp & DCMIPP_P1ST1CR_SRC));
7319 }
7320 }
7321 /**
7322 * @brief Retrieve the ISP area statistic extraction configuration for a specified DCMIPP pipe.
7323 * @param hdcmipp Pointer to DCMIPP handle
7324 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes.
7325 * @param pStatisticExtractionAreaConfig Pointer to a DCMIPP_StatisticExtractionAreaConfTypeDef structure
7326 * that will be filled with the area statistic extraction configuration
7327 * of the specified pipe.
7328 * @retval None
7329 */
HAL_DCMIPP_PIPE_GetISPAreaStatisticExtractionConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,DCMIPP_StatisticExtractionAreaConfTypeDef * pStatisticExtractionAreaConfig)7330 void HAL_DCMIPP_PIPE_GetISPAreaStatisticExtractionConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
7331 DCMIPP_StatisticExtractionAreaConfTypeDef
7332 *pStatisticExtractionAreaConfig)
7333 {
7334 uint32_t tmp;
7335 /* Check parameters */
7336 assert_param(IS_DCMIPP_PIPE(Pipe));
7337
7338 if (Pipe == DCMIPP_PIPE1)
7339 {
7340 tmp = READ_REG(hdcmipp->Instance->P1STSTR);
7341 pStatisticExtractionAreaConfig->HStart = ((tmp & DCMIPP_P1STSTR_HSTART) >> DCMIPP_P1STSTR_HSTART_Pos);
7342 pStatisticExtractionAreaConfig->VStart = ((tmp & DCMIPP_P1STSTR_VSTART) >> DCMIPP_P1STSTR_VSTART_Pos);
7343
7344 tmp = READ_REG(hdcmipp->Instance->P1STSZR);
7345 pStatisticExtractionAreaConfig->VSize = ((tmp & DCMIPP_P1STSZR_VSIZE) >> DCMIPP_P1STSZR_VSIZE_Pos);
7346 pStatisticExtractionAreaConfig->HSize = ((tmp & DCMIPP_P1STSZR_HSIZE) >> DCMIPP_P1STSZR_HSIZE_Pos);
7347 }
7348 }
7349 /**
7350 * @brief Retrieve the ISP control contrast configuration for a specified DCMIPP pipe.
7351 * @param hdcmipp Pointer to DCMIPP handle
7352 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7353 * @param pContrastConfig Pointer to a DCMIPP_ContrastConfTypeDef structure that will be
7354 * filled with the contrast configuration of the specified pipe.
7355 * @retval None
7356 */
HAL_DCMIPP_PIPE_GetISPCtrlContrastConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,DCMIPP_ContrastConfTypeDef * pContrastConfig)7357 void HAL_DCMIPP_PIPE_GetISPCtrlContrastConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
7358 DCMIPP_ContrastConfTypeDef *pContrastConfig)
7359 {
7360 uint32_t tmp;
7361
7362 /* Check parameters */
7363 assert_param(IS_DCMIPP_PIPE(Pipe));
7364
7365 if (Pipe == DCMIPP_PIPE1)
7366 {
7367 tmp = READ_REG(hdcmipp->Instance->P1CTCR1);
7368
7369 pContrastConfig->LUM_0 = (uint8_t)((tmp & DCMIPP_P1CTCR1_LUM0) >> DCMIPP_P1CTCR1_LUM0_Pos);
7370
7371 tmp = READ_REG(hdcmipp->Instance->P1CTCR2);
7372 pContrastConfig->LUM_32 = (uint8_t)((tmp & DCMIPP_P1CTCR2_LUM1) >> DCMIPP_P1CTCR2_LUM1_Pos);
7373 pContrastConfig->LUM_64 = (uint8_t)((tmp & DCMIPP_P1CTCR2_LUM2) >> DCMIPP_P1CTCR2_LUM2_Pos);
7374 pContrastConfig->LUM_96 = (uint8_t)((tmp & DCMIPP_P1CTCR2_LUM3) >> DCMIPP_P1CTCR2_LUM3_Pos);
7375 pContrastConfig->LUM_128 = (uint8_t)((tmp & DCMIPP_P1CTCR2_LUM4) >> DCMIPP_P1CTCR2_LUM4_Pos);
7376
7377 tmp = READ_REG(hdcmipp->Instance->P1CTCR3);
7378 pContrastConfig->LUM_160 = (uint8_t)((tmp & DCMIPP_P1CTCR3_LUM5) >> DCMIPP_P1CTCR3_LUM5_Pos);
7379 pContrastConfig->LUM_192 = (uint8_t)((tmp & DCMIPP_P1CTCR3_LUM6) >> DCMIPP_P1CTCR3_LUM6_Pos);
7380 pContrastConfig->LUM_224 = (uint8_t)((tmp & DCMIPP_P1CTCR3_LUM7) >> DCMIPP_P1CTCR3_LUM7_Pos);
7381 pContrastConfig->LUM_256 = (uint8_t)((tmp & DCMIPP_P1CTCR3_LUM8) >> DCMIPP_P1CTCR3_LUM8_Pos);
7382 }
7383 }
7384 /**
7385 * @brief Retrieve the ISP exposure configuration for a specified DCMIPP pipe.
7386 * @param hdcmipp Pointer to DCMIPP handle
7387 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7388 * @param pExposureConfig Pointer to a DCMIPP_ExposureConfTypeDef structure that will be
7389 * filled with the exposure configuration of the specified pipe.
7390 * @retval None
7391 */
HAL_DCMIPP_PIPE_GetISPExposureConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,DCMIPP_ExposureConfTypeDef * pExposureConfig)7392 void HAL_DCMIPP_PIPE_GetISPExposureConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
7393 DCMIPP_ExposureConfTypeDef *pExposureConfig)
7394 {
7395 uint32_t tmp;
7396
7397 /* Check parameters */
7398 assert_param(IS_DCMIPP_PIPE(Pipe));
7399
7400 if (Pipe == DCMIPP_PIPE1)
7401 {
7402 tmp = READ_REG(hdcmipp->Instance->P1EXCR2);
7403
7404 pExposureConfig->MultiplierBlue = (uint8_t)((tmp & DCMIPP_P1EXCR2_MULTB) >> DCMIPP_P1EXCR2_MULTB_Pos);
7405 pExposureConfig->ShiftBlue = (uint8_t)((tmp & DCMIPP_P1EXCR2_SHFB) >> DCMIPP_P1EXCR2_SHFB_Pos);
7406 pExposureConfig->ShiftGreen = (uint8_t)((tmp & DCMIPP_P1EXCR2_SHFG) >> DCMIPP_P1EXCR2_SHFG_Pos);
7407 pExposureConfig->MultiplierGreen = (uint8_t)((tmp & DCMIPP_P1EXCR2_MULTG) >> DCMIPP_P1EXCR2_MULTG_Pos);
7408
7409 tmp = READ_REG(hdcmipp->Instance->P1EXCR1);
7410
7411 pExposureConfig->MultiplierRed = (uint8_t)((tmp & DCMIPP_P1EXCR1_MULTR) >> DCMIPP_P1EXCR1_MULTR_Pos);
7412 pExposureConfig->ShiftRed = (uint8_t)((tmp & DCMIPP_P1EXCR1_SHFR) >> DCMIPP_P1EXCR1_SHFR_Pos);
7413 }
7414 }
7415 /**
7416 * @brief Retrieve the ISP Raw Bayer to RGB conversion configuration for a specified DCMIPP pipe.
7417 * @param hdcmipp Pointer to DCMIPP handle
7418 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7419 * @param pRawBayer2RGBConfig Pointer to a DCMIPP_RawBayer2RGBConfTypeDef structure that will be
7420 * filled with the Raw Bayer to RGB conversion configuration of the specified pipe.
7421 * @retval None
7422 */
HAL_DCMIPP_PIPE_GetISPRawBayer2RGBConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,DCMIPP_RawBayer2RGBConfTypeDef * pRawBayer2RGBConfig)7423 void HAL_DCMIPP_PIPE_GetISPRawBayer2RGBConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
7424 DCMIPP_RawBayer2RGBConfTypeDef *pRawBayer2RGBConfig)
7425 {
7426 uint32_t p1dmcr_reg;
7427 /* Check parameters */
7428 assert_param(IS_DCMIPP_PIPE(Pipe));
7429
7430 if (Pipe == DCMIPP_PIPE1)
7431 {
7432 p1dmcr_reg = READ_REG(hdcmipp->Instance->P1DMCR);
7433
7434 pRawBayer2RGBConfig->EdgeStrength = ((p1dmcr_reg & DCMIPP_P1DMCR_EDGE) >> DCMIPP_P1DMCR_EDGE_Pos);
7435 pRawBayer2RGBConfig->HLineStrength = ((p1dmcr_reg & DCMIPP_P1DMCR_LINEH) >> DCMIPP_P1DMCR_LINEH_Pos);
7436 pRawBayer2RGBConfig->PeakStrength = ((p1dmcr_reg & DCMIPP_P1DMCR_PEAK) >> DCMIPP_P1DMCR_PEAK_Pos);
7437 pRawBayer2RGBConfig->RawBayerType = (p1dmcr_reg & DCMIPP_P1DMCR_TYPE);
7438 pRawBayer2RGBConfig->VLineStrength = ((p1dmcr_reg & DCMIPP_P1DMCR_LINEV) >> DCMIPP_P1DMCR_LINEV_Pos);
7439 }
7440 }
7441 /**
7442 * @brief Retrieve the ISP color conversion configuration for a specified DCMIPP pipe.
7443 * @param hdcmipp Pointer to DCMIPP handle
7444 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7445 * @param pColorConversionConfig Pointer to a DCMIPP_ColorConversionConfTypeDef structure that will be
7446 * filled with the color conversion configuration of the specified pipe.
7447 * @retval None
7448 */
HAL_DCMIPP_PIPE_GetISPColorConversionConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,DCMIPP_ColorConversionConfTypeDef * pColorConversionConfig)7449 void HAL_DCMIPP_PIPE_GetISPColorConversionConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
7450 DCMIPP_ColorConversionConfTypeDef *pColorConversionConfig)
7451 {
7452 uint16_t tmp;
7453
7454 /* Check parameters */
7455 assert_param(IS_DCMIPP_PIPE(Pipe));
7456
7457 if (Pipe == DCMIPP_PIPE1)
7458 {
7459 tmp = (uint16_t)READ_REG(hdcmipp->Instance->P1CCCR);
7460
7461 UNUSED(tmp);
7462
7463 pColorConversionConfig->ClampOutputSamples = (((tmp & DCMIPP_P1CCCR_CLAMP) >> DCMIPP_P1YUVCR_CLAMP_Pos) != 0U)
7464 ? ENABLE : DISABLE;
7465 pColorConversionConfig->OutputSamplesType = (uint8_t)(tmp & DCMIPP_P1CCCR_TYPE);
7466
7467 /* Get Coefficient row 1 columns 1 2 3 and the added column of the matrix */
7468 tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCRR1, DCMIPP_P1CCRR1_RG) >> DCMIPP_P1CCRR1_RG_Pos);
7469 pColorConversionConfig->RG = (int16_t)GET_MATRIX_VALUE11(tmp);
7470
7471 tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCRR1, DCMIPP_P1CCRR1_RR) >> DCMIPP_P1CCRR1_RR_Pos);
7472 pColorConversionConfig->RR = (int16_t)GET_MATRIX_VALUE11(tmp);
7473
7474 tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCRR2, DCMIPP_P1CCRR2_RA) >> DCMIPP_P1CCRR2_RA_Pos);
7475 pColorConversionConfig->RA = (int16_t)GET_MATRIX_VALUE10(tmp);
7476
7477 tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCRR2, DCMIPP_P1CCRR2_RB) >> DCMIPP_P1CCRR2_RB_Pos);
7478 pColorConversionConfig->RB = (int16_t)GET_MATRIX_VALUE11(tmp);
7479
7480 /* Get Coefficient row 2 columns 1 2 3 and the added column of the matrix */
7481 tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCGR1, DCMIPP_P1CCGR1_GG) >> DCMIPP_P1CCGR1_GG_Pos);
7482 pColorConversionConfig->GG = (int16_t)GET_MATRIX_VALUE11(tmp);
7483
7484 tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCGR1, DCMIPP_P1CCGR1_GR) >> DCMIPP_P1CCGR1_GR_Pos);
7485 pColorConversionConfig->GR = (int16_t)GET_MATRIX_VALUE11(tmp);
7486
7487 tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCGR2, DCMIPP_P1CCGR2_GA) >> DCMIPP_P1CCGR2_GA_Pos);
7488 pColorConversionConfig->GA = (int16_t)GET_MATRIX_VALUE10(tmp);
7489
7490 tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCGR2, DCMIPP_P1CCGR2_GB) >> DCMIPP_P1CCGR2_GB_Pos);
7491 pColorConversionConfig->GB = (int16_t)GET_MATRIX_VALUE11(tmp);
7492
7493 /* Get Coefficient row 3 columns 1 2 3 and the added column of the matrix */
7494 tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCBR2, DCMIPP_P1CCBR2_BA) >> DCMIPP_P1CCBR2_BA_Pos);
7495 pColorConversionConfig->BA = (int16_t)GET_MATRIX_VALUE10(tmp);
7496
7497 tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCBR2, DCMIPP_P1CCBR2_BB) >> DCMIPP_P1CCBR2_BB_Pos);
7498 pColorConversionConfig->BB = (int16_t)GET_MATRIX_VALUE11(tmp);
7499
7500 tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCBR1, DCMIPP_P1CCBR1_BG) >> DCMIPP_P1CCBR1_BG_Pos);
7501 pColorConversionConfig->BG = (int16_t)GET_MATRIX_VALUE11(tmp);
7502
7503 tmp = (uint16_t)(READ_FIELD(hdcmipp->Instance->P1CCBR1, DCMIPP_P1CCBR1_BR) >> DCMIPP_P1CCBR1_BR_Pos);
7504 pColorConversionConfig->BR = (int16_t)GET_MATRIX_VALUE11(tmp);
7505 }
7506 }
7507 /**
7508 * @brief Retrieve the ISP Statistic Removal configuration for a specified DCMIPP pipe.
7509 * @param hdcmipp Pointer to DCMIPP handle
7510 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7511 * @param NbFirstLines Pointer to a uint32_t variable that will be filled with the number
7512 * of first lines to be removed from the statistics computation.
7513 * @param NbLastLines Pointer to a uint32_t variable that will be filled with the number
7514 * of last lines to be removed from the statistics computation.
7515 * @retval None
7516 */
HAL_DCMIPP_PIPE_GetISPRemovalStatisticConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t * NbFirstLines,uint32_t * NbLastLines)7517 void HAL_DCMIPP_PIPE_GetISPRemovalStatisticConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
7518 uint32_t *NbFirstLines, uint32_t *NbLastLines)
7519 {
7520 uint32_t tmp;
7521
7522 /* Check parameters */
7523 assert_param(IS_DCMIPP_PIPE(Pipe));
7524
7525 if (Pipe == DCMIPP_PIPE1)
7526 {
7527 tmp = READ_REG(hdcmipp->Instance->P1SRCR);
7528
7529 *NbFirstLines = ((tmp & DCMIPP_P1SRCR_FIRSTLINEDEL) >> DCMIPP_P1SRCR_FIRSTLINEDEL_Pos);
7530
7531 *NbLastLines = (tmp & DCMIPP_P1SRCR_LASTLINE);
7532 }
7533 }
7534 /**
7535 * @brief Check if the ISP Statistic Removal is enabled or not
7536 * @param hdcmipp Pointer to DCMIPP handle
7537 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7538 * @retval State of bit (1 or 0).
7539 */
HAL_DCMIPP_PIPE_IsEnabledISPRemovalStatistic(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)7540 uint32_t HAL_DCMIPP_PIPE_IsEnabledISPRemovalStatistic(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
7541 {
7542 /* Check parameters */
7543 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
7544 assert_param(IS_DCMIPP_PIPE(Pipe));
7545
7546 return ((READ_BIT(hdcmipp->Instance->P1SRCR, DCMIPP_P1SRCR_CROPEN) == DCMIPP_P1SRCR_CROPEN) ? 1U : 0U);
7547 }
7548 /**
7549 * @brief Check if ISP Decimation is enabled or not
7550 * @param hdcmipp Pointer to DCMIPP handle
7551 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7552 * @retval State of bit (1 or 0).
7553 */
HAL_DCMIPP_PIPE_IsEnabledISPDecimation(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)7554 uint32_t HAL_DCMIPP_PIPE_IsEnabledISPDecimation(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
7555 {
7556 /* Check parameters */
7557 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
7558 assert_param(IS_DCMIPP_PIPE(Pipe));
7559
7560 if (Pipe == DCMIPP_PIPE1)
7561 {
7562 return ((READ_BIT(hdcmipp->Instance->P1DECR, DCMIPP_P1DECR_ENABLE) == DCMIPP_P1DECR_ENABLE) ? 1U : 0U);
7563 }
7564 else
7565 {
7566 /* State Disabled */
7567 return 0;
7568 }
7569 }
7570 /**
7571 * @brief Check if ISP Exposure is enabled or not
7572 * @param hdcmipp Pointer to DCMIPP handle
7573 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7574 * @retval State of bit (1 or 0).
7575 */
HAL_DCMIPP_PIPE_IsEnabledISPExposure(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)7576 uint32_t HAL_DCMIPP_PIPE_IsEnabledISPExposure(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
7577 {
7578 /* Check parameters */
7579 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
7580 assert_param(IS_DCMIPP_PIPE(Pipe));
7581
7582 if (Pipe == DCMIPP_PIPE1)
7583 {
7584 return ((READ_BIT(hdcmipp->Instance->P1EXCR1, DCMIPP_P1EXCR1_ENABLE) == DCMIPP_P1EXCR1_ENABLE) ? 1U : 0U);
7585 }
7586 else
7587 {
7588 /* State Disabled */
7589 return 0;
7590 }
7591 }
7592 /**
7593 * @brief Check if ISP RawBayer to RGB is enabled or not
7594 * @param hdcmipp Pointer to DCMIPP handle
7595 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7596 * @retval State of bit (1 or 0).
7597 */
HAL_DCMIPP_PIPE_IsEnabledISPRawBayer2RGB(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)7598 uint32_t HAL_DCMIPP_PIPE_IsEnabledISPRawBayer2RGB(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
7599 {
7600 /* Check parameters */
7601 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
7602 assert_param(IS_DCMIPP_PIPE(Pipe));
7603
7604 if (Pipe == DCMIPP_PIPE1)
7605 {
7606 return ((READ_BIT(hdcmipp->Instance->P1DMCR, DCMIPP_P1DMCR_ENABLE) == DCMIPP_P1DMCR_ENABLE) ? 1U : 0U);
7607 }
7608 else
7609 {
7610 /* State Disabled */
7611 return 0;
7612 }
7613 }
7614 /**
7615 * @brief Check if ISP color conversion is enabled
7616 * @param hdcmipp Pointer to DCMIPP handle
7617 * @param Pipe Pipe to be checked
7618 * @retval State of bit (1 or 0).
7619 */
HAL_DCMIPP_PIPE_IsEnabledISPColorConversion(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)7620 uint32_t HAL_DCMIPP_PIPE_IsEnabledISPColorConversion(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
7621 {
7622 /* Check parameters */
7623 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
7624 assert_param(IS_DCMIPP_PIPE(Pipe));
7625
7626 if (Pipe == DCMIPP_PIPE1)
7627 {
7628 return ((READ_BIT(hdcmipp->Instance->P1CCCR, DCMIPP_P1CCCR_ENABLE) == DCMIPP_P1CCCR_ENABLE) ? 1U : 0U);
7629 }
7630 else
7631 {
7632 /* State Disabled */
7633 return 0;
7634 }
7635 }
7636 /**
7637 * @brief Check if ISP contrast is enabled or not
7638 * @param hdcmipp Pointer to DCMIPP handle
7639 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7640 * @retval State of bit (1 or 0).
7641 */
HAL_DCMIPP_PIPE_IsEnabledISPCtrlContrast(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)7642 uint32_t HAL_DCMIPP_PIPE_IsEnabledISPCtrlContrast(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
7643 {
7644 /* Check parameters */
7645 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
7646 assert_param(IS_DCMIPP_PIPE(Pipe));
7647
7648 if (Pipe == DCMIPP_PIPE1)
7649 {
7650 return ((READ_BIT(hdcmipp->Instance->P1CTCR1, DCMIPP_P1CTCR1_ENABLE) == DCMIPP_P1CTCR1_ENABLE) ? 1U : 0U);
7651 }
7652 else
7653 {
7654 /* State Disabled */
7655 return 0;
7656 }
7657 }
7658 /**
7659 * @brief Check if ISP Statistic Extraction Module is enabled or not
7660 * @param hdcmipp Pointer to DCMIPP handle
7661 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7662 * @param ModuleID Specifies the Module ID, can be a value from
7663 * @ref DCMIPP_Statistics_Extraction_Module_ID.
7664 * @retval State of bit (1 or 0).
7665 */
HAL_DCMIPP_PIPE_IsEnabledISPStatisticExtraction(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint8_t ModuleID)7666 uint32_t HAL_DCMIPP_PIPE_IsEnabledISPStatisticExtraction(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe,
7667 uint8_t ModuleID)
7668 {
7669 /* Check parameters */
7670 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
7671 assert_param(IS_DCMIPP_PIPE(Pipe));
7672
7673 if (Pipe == DCMIPP_PIPE1)
7674 {
7675 switch (ModuleID)
7676 {
7677 case DCMIPP_STATEXT_MODULE2:
7678 return ((READ_BIT(hdcmipp->Instance->P1ST2CR, DCMIPP_P1ST2CR_ENABLE) == DCMIPP_P1ST2CR_ENABLE) ? 1U : 0U);
7679 break;
7680 case DCMIPP_STATEXT_MODULE3:
7681 return ((READ_BIT(hdcmipp->Instance->P1ST3CR, DCMIPP_P1ST3CR_ENABLE) == DCMIPP_P1ST3CR_ENABLE) ? 1U : 0U);
7682 break;
7683 default:
7684 /* DCMIPP_STATEXT_MODULE1 */
7685 return ((READ_BIT(hdcmipp->Instance->P1ST1CR, DCMIPP_P1ST1CR_ENABLE) == DCMIPP_P1ST1CR_ENABLE) ? 1U : 0U);
7686 break;
7687 }
7688 }
7689 else
7690 {
7691 /* State Disabled */
7692 return 0;
7693 }
7694 }
7695 /**
7696 * @brief Check if ISP Area Statistic Extraction is enabled or not
7697 * @param hdcmipp Pointer to DCMIPP handle
7698 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7699 * @retval State of bit (1 or 0).
7700 */
HAL_DCMIPP_PIPE_IsEnabledISPAreaStatisticExtraction(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)7701 uint32_t HAL_DCMIPP_PIPE_IsEnabledISPAreaStatisticExtraction(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
7702 {
7703 /* Check parameters */
7704 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
7705 assert_param(IS_DCMIPP_PIPE(Pipe));
7706
7707 if (Pipe == DCMIPP_PIPE1)
7708 {
7709 return ((READ_BIT(hdcmipp->Instance->P1STSZR, DCMIPP_P1STSZR_CROPEN) == DCMIPP_P1STSZR_CROPEN) ? 1UL : 0UL);
7710
7711 }
7712 else
7713 {
7714 /* State Disabled */
7715 return 0;
7716 }
7717 }
7718 /**
7719 * A set of functions allowing to configure the DCMIPP CSI Virtual Channel:
7720 * - HAL_DCMIPP_CSI_SetLineByteCounterConfig() : Set Line/Byte counter configuration per virtual Channel
7721 * - HAL_DCMIPP_CSI_EnableLineByteCounter() : Enable Line/Byte counter per counter (up to 4)
7722 * - HAL_DCMIPP_CSI_DisableLineByteCounter() : Disable Line/Byte counter per counter (up to 4)
7723 *
7724 * - HAL_DCMIPP_CSI_SetTimerConfig() : Set timer configuration per virtual Channel
7725 * - HAL_DCMIPP_CSI_EnableTimer() : Enable timer (up to 4)
7726 * - HAL_DCMIPP_CSI_DisableTimer() : Disable timer (up to 4)
7727 * - HAL_DCMIPP_CSI_SetWatchdogCounterConfig() : Set Watchdog configuration
7728 */
7729 /**
7730 * @brief Configure the DCMIPP CSI Line/Byte Counter for the selected counter according to the user parameters.
7731 * @param hdcmipp Pointer to DCMIPP handle
7732 * @param Counter Specifies the counter, can be a value from @ref DCMIPP_CSI_Counter
7733 * @param pLineByteConfig Pointer to DCMIPP_CSI_LineByteCounterConfTypeDef that contains the Line/Byte Counter
7734 * configuration information for CSI.
7735 * @retval HAL status
7736 */
HAL_DCMIPP_CSI_SetLineByteCounterConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Counter,const DCMIPP_CSI_LineByteCounterConfTypeDef * pLineByteConfig)7737 HAL_StatusTypeDef HAL_DCMIPP_CSI_SetLineByteCounterConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter,
7738 const DCMIPP_CSI_LineByteCounterConfTypeDef *pLineByteConfig)
7739 {
7740 CSI_TypeDef *csi_instance;
7741 csi_instance = CSI;
7742 uint32_t prgitr_lbxvc_msk = (CSI_PRGITR_LB0VC << (Counter * 4U));
7743 uint32_t prgitr_lbxvc_pos = CSI_PRGITR_LB0VC_Pos + (Counter * 4U);
7744
7745 /* Check pointer validity */
7746 if ((hdcmipp == NULL) || (pLineByteConfig == NULL))
7747 {
7748 return HAL_ERROR;
7749 }
7750
7751 assert_param(IS_DCMIPP_ALL_INSTANCE(hdcmipp->Instance));
7752 assert_param(IS_DCMIPP_CSI_COUNTER(Counter));
7753 assert_param(IS_DCMIPP_CSI_LINE_COUNTER(pLineByteConfig->LineCounter));
7754 assert_param(IS_DCMIPP_CSI_BYTE_COUNTER(pLineByteConfig->ByteCounter));
7755 assert_param(IS_DCMIPP_VCID(pLineByteConfig->VirtualChannel));
7756
7757 switch (Counter)
7758 {
7759 case DCMIPP_CSI_COUNTER0:
7760 WRITE_REG(csi_instance->LB0CFGR, (pLineByteConfig->LineCounter << CSI_LB0CFGR_LINECNT_Pos) | \
7761 pLineByteConfig->ByteCounter);
7762 break;
7763 case DCMIPP_CSI_COUNTER1:
7764 WRITE_REG(csi_instance->LB1CFGR, (pLineByteConfig->LineCounter << CSI_LB1CFGR_LINECNT_Pos) | \
7765 pLineByteConfig->ByteCounter);
7766 break;
7767 case DCMIPP_CSI_COUNTER2:
7768 WRITE_REG(csi_instance->LB2CFGR, (pLineByteConfig->LineCounter << CSI_LB2CFGR_LINECNT_Pos) | \
7769 pLineByteConfig->ByteCounter);
7770 break;
7771 case DCMIPP_CSI_COUNTER3:
7772 WRITE_REG(csi_instance->LB3CFGR, (pLineByteConfig->LineCounter << CSI_LB3CFGR_LINECNT_Pos) | \
7773 pLineByteConfig->ByteCounter);
7774 break;
7775 default:
7776 break;
7777 }
7778
7779 /* Link the Line/Byte Counter to the selected virtual channel */
7780 MODIFY_REG(csi_instance->PRGITR, prgitr_lbxvc_msk, pLineByteConfig->VirtualChannel << prgitr_lbxvc_pos);
7781
7782 return HAL_OK;
7783 }
7784 /**
7785 * @brief Enable the selected DCMIPP CSI Line/Byte Counter.
7786 * @param hdcmipp Pointer to DCMIPP handle
7787 * @param Counter Specifies the counter, can be a value from @ref DCMIPP_CSI_Counter
7788 * @retval HAL status
7789 */
HAL_DCMIPP_CSI_EnableLineByteCounter(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Counter)7790 HAL_StatusTypeDef HAL_DCMIPP_CSI_EnableLineByteCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter)
7791 {
7792 CSI_TypeDef *csi_instance;
7793 csi_instance = CSI;
7794
7795 assert_param(IS_DCMIPP_CSI_COUNTER(Counter));
7796
7797 /* Check pointer validity */
7798 if (hdcmipp == NULL)
7799 {
7800 return HAL_ERROR;
7801 }
7802
7803 /* Enable the Line/Byte Counter IT */
7804 __HAL_DCMIPP_CSI_ENABLE_IT(csi_instance, DCMIPP_CSI_IT_LB0 << Counter);
7805
7806 /* Enable the selected counter */
7807 SET_BIT(csi_instance->PRGITR, CSI_PRGITR_LB0EN << (Counter * 4U));
7808
7809 return HAL_OK;
7810 }
7811 /**
7812 * @brief Disable the selected DCMIPP CSI Line/Byte Counter.
7813 * @param hdcmipp Pointer to DCMIPP handle
7814 * @param Counter Specifies the counter, can be a value from @ref DCMIPP_CSI_Counter
7815 * @retval HAL status
7816 */
HAL_DCMIPP_CSI_DisableLineByteCounter(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Counter)7817 HAL_StatusTypeDef HAL_DCMIPP_CSI_DisableLineByteCounter(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter)
7818 {
7819 CSI_TypeDef *csi_instance;
7820 csi_instance = CSI;
7821
7822 assert_param(IS_DCMIPP_CSI_COUNTER(Counter));
7823
7824 /* Check pointer validity */
7825 if (hdcmipp == NULL)
7826 {
7827 return HAL_ERROR;
7828 }
7829
7830 /* Disable the Line/Byte Counter IT */
7831 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_LB0 << Counter);
7832
7833 /* Disable the selected counter */
7834 CLEAR_BIT(csi_instance->PRGITR, CSI_PRGITR_LB0EN << (Counter * 4U));
7835
7836 return HAL_OK;
7837 }
7838 /**
7839 * @brief Configure the DCMIPP CSI Timer for the selected timer according to the user parameters.
7840 * @param hdcmipp Pointer to DCMIPP handle
7841 * @param Timer Specifies the Timer, can be a value from @ref DCMIPP_CSI_Timer
7842 * @param TimerConfig Pointer to DCMIPP_CSI_TimerConfTypeDef that contains the timer
7843 * configuration information for CSI.
7844 * @retval HAL status
7845 */
HAL_DCMIPP_CSI_SetTimerConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Timer,const DCMIPP_CSI_TimerConfTypeDef * TimerConfig)7846 HAL_StatusTypeDef HAL_DCMIPP_CSI_SetTimerConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Timer,
7847 const DCMIPP_CSI_TimerConfTypeDef *TimerConfig)
7848 {
7849 CSI_TypeDef *csi_instance;
7850 csi_instance = CSI;
7851
7852 uint32_t prgitr_lbx_index = CSI_PRGITR_TIM0VC_Pos + (Timer * 4U);
7853 uint32_t prgitr_lbxvc_msk = (CSI_PRGITR_TIM0VC << (Timer * 4U));
7854 uint32_t startpoint_pos = CSI_PRGITR_TIM0EOF_Pos + (Timer * 4U);
7855
7856 /* Check pointer validity */
7857 if ((hdcmipp == NULL) || (TimerConfig == NULL))
7858 {
7859 return HAL_ERROR;
7860 }
7861
7862 assert_param(IS_DCMIPP_VCID(TimerConfig->VirtualChannel));
7863 assert_param(IS_DCMIPP_CSI_TIMER(Timer));
7864 assert_param(IS_DCMIPP_CSI_TIMER_START(TimerConfig->StartPoint));
7865
7866 /* Set counter value and the start point for the selected timer */
7867 switch (Timer)
7868 {
7869 case DCMIPP_CSI_TIMER0:
7870 WRITE_REG(csi_instance->TIM0CFGR, TimerConfig->Count);
7871 break;
7872 case DCMIPP_CSI_TIMER1:
7873 WRITE_REG(csi_instance->TIM1CFGR, TimerConfig->Count);
7874 break;
7875 case DCMIPP_CSI_TIMER2:
7876 WRITE_REG(csi_instance->TIM2CFGR, TimerConfig->Count);
7877 break;
7878 case DCMIPP_CSI_TIMER3:
7879 WRITE_REG(csi_instance->TIM3CFGR, TimerConfig->Count);
7880 break;
7881 default:
7882 break;
7883 }
7884
7885 SET_BIT(csi_instance->PRGITR, TimerConfig->StartPoint << startpoint_pos);
7886
7887 /* Link the timer to the selected virtual channel */
7888 MODIFY_REG(csi_instance->PRGITR, prgitr_lbxvc_msk, (TimerConfig->VirtualChannel) << prgitr_lbx_index);
7889
7890 return HAL_OK;
7891
7892 }
7893 /**
7894 * @brief Enable the selected DCMIPP CSI Timer.
7895 * @param hdcmipp Pointer to DCMIPP handle
7896 * @param Timer Specifies the Timer, can be a value from @ref DCMIPP_CSI_Timer
7897 * @retval HAL status
7898 */
HAL_DCMIPP_CSI_EnableTimer(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Timer)7899 HAL_StatusTypeDef HAL_DCMIPP_CSI_EnableTimer(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Timer)
7900 {
7901 CSI_TypeDef *csi_instance;
7902 csi_instance = CSI;
7903
7904 assert_param(IS_DCMIPP_CSI_TIMER(Timer));
7905
7906 /* Check pointer validity */
7907 if (hdcmipp == NULL)
7908 {
7909 return HAL_ERROR;
7910 }
7911
7912 /* Enable the Timer x IT */
7913 __HAL_DCMIPP_CSI_ENABLE_IT(csi_instance, DCMIPP_CSI_IT_TIM0 << Timer);
7914
7915 /* Enable the selected timer */
7916 SET_BIT(csi_instance->PRGITR, CSI_PRGITR_TIM0EN << (Timer * 4U));
7917
7918 return HAL_OK;
7919 }
7920 /**
7921 * @brief Disable the selected DCMIPP CSI Timer.
7922 * @param hdcmipp Pointer to DCMIPP handle
7923 * @param Timer Specifies the Timer, can be a value from @ref DCMIPP_CSI_Timer
7924 * @retval HAL status
7925 */
HAL_DCMIPP_CSI_DisableTimer(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Timer)7926 HAL_StatusTypeDef HAL_DCMIPP_CSI_DisableTimer(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Timer)
7927 {
7928 CSI_TypeDef *csi_instance;
7929 csi_instance = CSI;
7930
7931 assert_param(IS_DCMIPP_CSI_TIMER(Timer));
7932
7933 /* Check pointer validity */
7934 if (hdcmipp == NULL)
7935 {
7936 return HAL_ERROR;
7937 }
7938
7939 /* Disable the Line/Byte Counter IT */
7940 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, DCMIPP_CSI_IT_TIM0 << Timer);
7941
7942 /* Disable the selected counter */
7943 CLEAR_BIT(csi_instance->PRGITR, CSI_PRGITR_TIM0EN << (Timer * 4U));
7944
7945 return HAL_OK;
7946 }
7947 /**
7948 * @brief Configure the DCMIPP CSI Watchdog counter.
7949 * @param hdcmipp Pointer to DCMIPP handle
7950 * @param Counter Specifies the watchdog counter value
7951 * @retval HAL status
7952 */
HAL_DCMIPP_CSI_SetWatchdogCounterConfig(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Counter)7953 HAL_StatusTypeDef HAL_DCMIPP_CSI_SetWatchdogCounterConfig(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Counter)
7954 {
7955 CSI_TypeDef *csi_instance;
7956 csi_instance = CSI;
7957
7958 UNUSED(hdcmipp);
7959
7960 /* Configure the watchdog counter */
7961 WRITE_REG(csi_instance->WDR, Counter);
7962
7963 /* Enable the watchdog IT */
7964 __HAL_DCMIPP_CSI_ENABLE_IT(csi_instance, DCMIPP_CSI_IT_WDERR);
7965
7966 return HAL_OK;
7967 }
7968
7969 /**
7970 * @}
7971 */
7972
7973 /** @defgroup DCMIPP_State_and_Error_Functions DCMIPP State and Error Functions
7974 * @{
7975 */
7976
7977 /**
7978 * @brief Return the DCMIPP state
7979 * @param hdcmipp Pointer to DCMIPP handle
7980 * @retval HAL state
7981 */
HAL_DCMIPP_GetState(const DCMIPP_HandleTypeDef * hdcmipp)7982 HAL_DCMIPP_StateTypeDef HAL_DCMIPP_GetState(const DCMIPP_HandleTypeDef *hdcmipp)
7983 {
7984 return hdcmipp->State;
7985 }
7986 /**
7987 * @brief Return the DCMIPP error code
7988 * @param hdcmipp Pointer to DCMIPP handle
7989 * @retval DCMIPP Error Code
7990 */
HAL_DCMIPP_GetError(const DCMIPP_HandleTypeDef * hdcmipp)7991 uint32_t HAL_DCMIPP_GetError(const DCMIPP_HandleTypeDef *hdcmipp)
7992 {
7993 return hdcmipp->ErrorCode;
7994 }
7995 /**
7996 * @brief Return the DCMIPP state
7997 * @param hdcmipp Pointer to DCMIPP handle
7998 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
7999 * @retval HAL state
8000 */
HAL_DCMIPP_PIPE_GetState(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)8001 HAL_DCMIPP_PipeStateTypeDef HAL_DCMIPP_PIPE_GetState(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
8002 {
8003 /* Check Parameters */
8004 assert_param(IS_DCMIPP_PIPE(Pipe));
8005
8006 return hdcmipp->PipeState[Pipe];
8007 }
8008
8009 /**
8010 * @}
8011 */
8012
8013 /**
8014 * @}
8015 */
8016
8017 /* Private functions ---------------------------------------------------------*/
8018 /** @defgroup DCMIPP_Private_Functions DCMIPP Private Functions
8019 * @{
8020 */
8021 /**
8022 * @brief Configure the selected Pipe
8023 * @param hdcmipp Pointer to DCMIPP handle
8024 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
8025 * @param pPipeConfig pointer to the DCMIPP_PipeConfTypeDef structure that contains
8026 * the configuration information for the pipe.
8027 * @retval None
8028 */
Pipe_Config(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,const DCMIPP_PipeConfTypeDef * pPipeConfig)8029 static void Pipe_Config(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, const DCMIPP_PipeConfTypeDef *pPipeConfig)
8030 {
8031 if (Pipe == DCMIPP_PIPE0)
8032 {
8033 /* Configure Pipe0 */
8034 /* Configure Frame Rate */
8035 MODIFY_REG(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_FRATE, pPipeConfig->FrameRate);
8036 }
8037 else if (Pipe == DCMIPP_PIPE1)
8038 {
8039 /* Configure Pipe1 */
8040 /* Configure Frame Rate */
8041 MODIFY_REG(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_FRATE, pPipeConfig->FrameRate);
8042
8043 /* Configure the pixel packer */
8044 MODIFY_REG(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_FORMAT, pPipeConfig->PixelPackerFormat);
8045
8046 /* Configure Pixel Pipe Pitch */
8047 MODIFY_REG(hdcmipp->Instance->P1PPM0PR, DCMIPP_P1PPM0PR_PITCH,
8048 pPipeConfig->PixelPipePitch << DCMIPP_P1PPM0PR_PITCH_Pos);
8049
8050 if ((pPipeConfig->PixelPackerFormat == DCMIPP_PIXEL_PACKER_FORMAT_YUV422_2) ||
8051 (pPipeConfig->PixelPackerFormat == DCMIPP_PIXEL_PACKER_FORMAT_YUV420_2))
8052 {
8053 MODIFY_REG(hdcmipp->Instance->P1PPM1PR, DCMIPP_P1PPM1PR_PITCH,
8054 pPipeConfig->PixelPipePitch << DCMIPP_P1PPM1PR_PITCH_Pos);
8055 }
8056 else if (pPipeConfig->PixelPackerFormat == DCMIPP_PIXEL_PACKER_FORMAT_YUV420_3)
8057 {
8058 MODIFY_REG(hdcmipp->Instance->P1PPM1PR, DCMIPP_P1PPM1PR_PITCH,
8059 ((pPipeConfig->PixelPipePitch) / 2U) << DCMIPP_P1PPM1PR_PITCH_Pos);
8060 }
8061 else
8062 {
8063 /* Nothing to do */
8064 }
8065 }
8066 else
8067 {
8068 /* Configure Pipe2 */
8069 /* Configure Frame Rate */
8070 MODIFY_REG(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_FRATE, pPipeConfig->FrameRate);
8071
8072 /* Configure the pixel packer */
8073 MODIFY_REG(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_FORMAT, pPipeConfig->PixelPackerFormat);
8074
8075 /* Configure Pixel Pipe Pitch */
8076 MODIFY_REG(hdcmipp->Instance->P2PPM0PR, DCMIPP_P2PPM0PR_PITCH,
8077 pPipeConfig->PixelPipePitch << DCMIPP_P2PPM0PR_PITCH_Pos);
8078 }
8079 }
8080 /**
8081 * @brief Write register into the D-PHY via the Test registers
8082 * @param hcsi Pointer to CSI_TypeDef instance registers structure
8083 * @param reg_msb specifies the test code MSB in testdin (PHY Control Interface)
8084 * @param reg_lsb specifies the testcode LSB in testdin
8085 * @param val specifies the page offset in testdin
8086 * @retval None
8087 */
DCMIPP_CSI_WritePHYReg(CSI_TypeDef * hcsi,uint32_t reg_msb,uint32_t reg_lsb,uint32_t val)8088 static void DCMIPP_CSI_WritePHYReg(CSI_TypeDef *hcsi, uint32_t reg_msb, uint32_t reg_lsb, uint32_t val)
8089 {
8090 /* Based on sequence described at section 5.2.3.2 of DesignWave document */
8091 /* For writing the 4-bit testcode MSBs */
8092 /* Set testen to high */
8093 SET_BIT(hcsi->PTCR1, CSI_PTCR1_TWM);
8094
8095 /* Set testclk to high */
8096 SET_BIT(hcsi->PTCR0, CSI_PTCR0_TCKEN);
8097
8098 /* Place 0x00 in testdin */
8099 SET_BIT(hcsi->PTCR1, CSI_PTCR1_TWM);
8100
8101 /* Set testclk to low (with the falling edge on testclk, the testdin signal content is latched internally) */
8102 CLEAR_REG(hcsi->PTCR0);
8103
8104 /* Set testen to low */
8105 CLEAR_REG(hcsi->PTCR1);
8106
8107 /* Place the 8-bit word corresponding to the testcode MSBs in testdin */
8108 SET_BIT(hcsi->PTCR1, reg_msb & 0xFFU);
8109
8110 /* Set testclk to high */
8111 SET_BIT(hcsi->PTCR0, CSI_PTCR0_TCKEN);
8112
8113 /* For writing the 8-bit testcode LSBs */
8114 /* Set testclk to low */
8115 CLEAR_REG(hcsi->PTCR0);
8116
8117 /* Set testen to high */
8118 SET_BIT(hcsi->PTCR1, CSI_PTCR1_TWM);
8119
8120 /* Set testclk to high */
8121 SET_BIT(hcsi->PTCR0, CSI_PTCR0_TCKEN);
8122
8123 /* Place the 8-bit word test data in testdin */
8124 SET_BIT(hcsi->PTCR1, CSI_PTCR1_TWM | (reg_lsb & 0xFFU));
8125
8126 /* Set testclk to low (with the falling edge on testclk, the testdin signal content is latched internally) */
8127 CLEAR_REG(hcsi->PTCR0);
8128
8129 /* Set testen to low */
8130 CLEAR_REG(hcsi->PTCR1);
8131
8132 /* For writing the data */
8133 /* Place the 8-bit word corresponding to the page offset in testdin */
8134 SET_BIT(hcsi->PTCR1, val & 0xFFU);
8135
8136 /* Set testclk to high (test data is programmed internally */
8137 SET_BIT(hcsi->PTCR0, CSI_PTCR0_TCKEN);
8138
8139 /* Finish by setting testclk to low */
8140 CLEAR_REG(hcsi->PTCR0);
8141 }
8142 /**
8143 * @brief Configure the destination address and capture mode for the selected pipe
8144 * @param hdcmipp Pointer to DCMIPP handle
8145 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
8146 * @param DstAddress Specifies the destination memory address for the captured data.
8147 * @param CaptureMode Specifies the capture mode to be set for the pipe.
8148 * @retval None
8149 */
DCMIPP_SetConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t DstAddress,uint32_t CaptureMode)8150 static void DCMIPP_SetConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress, uint32_t CaptureMode)
8151 {
8152 if (Pipe == DCMIPP_PIPE0)
8153 {
8154 /* Update the DCMIPP pipe State */
8155 hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
8156
8157 /* Set the capture mode */
8158 hdcmipp->Instance->P0FCTCR |= CaptureMode;
8159
8160 /* Set the destination address */
8161 WRITE_REG(hdcmipp->Instance->P0PPM0AR1, DstAddress);
8162
8163 /* Enable all required interrupts lines for the PIPE0 */
8164 __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_OVR |
8165 DCMIPP_IT_AXI_TRANSFER_ERROR);
8166 }
8167 else if (Pipe == DCMIPP_PIPE1)
8168 {
8169 /* Update the DCMIPP pipe State */
8170 hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
8171
8172 /* Set the capture mode */
8173 hdcmipp->Instance->P1FCTCR |= CaptureMode;
8174
8175 /* Set the destination address */
8176 WRITE_REG(hdcmipp->Instance->P1PPM0AR1, DstAddress);
8177
8178 /* Enable all required interrupts lines for the PIPE1 */
8179 __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE1_FRAME | DCMIPP_IT_PIPE1_OVR | DCMIPP_IT_PIPE1_VSYNC |
8180 DCMIPP_IT_AXI_TRANSFER_ERROR);
8181 }
8182 else
8183 {
8184 /* Update the DCMIPP pipe State */
8185 hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
8186
8187 /* Set the capture mode */
8188 hdcmipp->Instance->P2FCTCR |= CaptureMode;
8189
8190 /* Set the destination address */
8191 WRITE_REG(hdcmipp->Instance->P2PPM0AR1, DstAddress);
8192
8193 /* Enable all required interrupts lines for the PIPE2 */
8194 __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE2_FRAME | DCMIPP_IT_PIPE2_OVR | DCMIPP_IT_PIPE2_VSYNC |
8195 DCMIPP_IT_AXI_TRANSFER_ERROR);
8196 }
8197 }
8198 /**
8199 * @brief Configure the destination addresses and capture mode for the selected pipe for Double Buffering Mode
8200 * @param hdcmipp Pointer to DCMIPP handle
8201 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
8202 * @param DstAddress0 Specifies the first destination memory address for the captured data.
8203 * @param DstAddress1 Specifies the second destination memory address for the captured data.
8204 * @param CaptureMode Specifies the capture mode to be set for the pipe.
8205 * @retval None
8206 */
DCMIPP_SetDBMConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t DstAddress0,uint32_t DstAddress1,uint32_t CaptureMode)8207 static void DCMIPP_SetDBMConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t DstAddress0,
8208 uint32_t DstAddress1, uint32_t CaptureMode)
8209 {
8210 if (Pipe == DCMIPP_PIPE0)
8211 {
8212 /* Update the DCMIPP pipe State */
8213 hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
8214
8215 /* Set the capture mode */
8216 hdcmipp->Instance->P0FCTCR |= CaptureMode;
8217
8218 /* Set the destination address */
8219 WRITE_REG(hdcmipp->Instance->P0PPM0AR1, DstAddress0);
8220
8221 /* Set the second destination address */
8222 WRITE_REG(hdcmipp->Instance->P0PPM0AR2, DstAddress1);
8223
8224 /* Enable Double buffering Mode */
8225 SET_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_DBM);
8226
8227 /* Enable all required interrupts lines for the Pipe0 */
8228 __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_OVR);
8229 }
8230 else if (Pipe == DCMIPP_PIPE1)
8231 {
8232 /* Update the DCMIPP pipe State */
8233 hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
8234
8235 /* Set the capture mode */
8236 hdcmipp->Instance->P1FCTCR |= CaptureMode;
8237
8238 /* Set the destination address */
8239 WRITE_REG(hdcmipp->Instance->P1PPM0AR1, DstAddress0);
8240
8241 /* Set the second destination address */
8242 WRITE_REG(hdcmipp->Instance->P1PPM0AR2, DstAddress1);
8243
8244 /* Enable Double buffering Mode */
8245 SET_BIT(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_DBM);
8246
8247 /* Enable all required interrupts lines for the Pipe1 */
8248 __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE1_FRAME | DCMIPP_IT_PIPE1_VSYNC | DCMIPP_IT_PIPE1_OVR);
8249 }
8250 else
8251 {
8252 /* Update the DCMIPP pipe State */
8253 hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
8254
8255 /* Set the capture mode */
8256 hdcmipp->Instance->P2FCTCR |= CaptureMode;
8257
8258 /* Set the destination address */
8259 WRITE_REG(hdcmipp->Instance->P2PPM0AR1, DstAddress0);
8260
8261 /* Set the second destination address */
8262 WRITE_REG(hdcmipp->Instance->P2PPM0AR2, DstAddress1);
8263
8264 /* Enable Double buffering Mode */
8265 SET_BIT(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_DBM);
8266
8267 /* Enable all required interrupts lines for the Pipe2 */
8268 __HAL_DCMIPP_ENABLE_IT(hdcmipp, DCMIPP_IT_PIPE2_FRAME | DCMIPP_IT_PIPE2_VSYNC | DCMIPP_IT_PIPE2_OVR);
8269 }
8270 }
8271 /**
8272 * @brief Enable the capture for the specified DCMIPP pipe.
8273 * @param hdcmipp Pointer to DCMIPP handle
8274 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
8275 * @retval None
8276 */
DCMIPP_EnableCapture(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)8277 static void DCMIPP_EnableCapture(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
8278 {
8279 if (Pipe == DCMIPP_PIPE0)
8280 {
8281 /* Activate the Pipe */
8282 SET_BIT(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_PIPEN);
8283
8284 /* Start the capture */
8285 SET_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
8286 }
8287 else if (Pipe == DCMIPP_PIPE1)
8288 {
8289 /* Update the DCMIPP pipe State */
8290 hdcmipp->PipeState[Pipe] = HAL_DCMIPP_PIPE_STATE_BUSY;
8291
8292 /* Activate the Pipe */
8293 SET_BIT(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_PIPEN);
8294
8295 /* Start the capture */
8296 SET_BIT(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTREQ);
8297 }
8298 else
8299 {
8300 /* Activate the Pipe */
8301 SET_BIT(hdcmipp->Instance->P2FSCR, DCMIPP_P2FSCR_PIPEN);
8302
8303 /* Start the capture */
8304 SET_BIT(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTREQ);
8305 }
8306 }
8307 /**
8308 * @brief Stop the capture for the specified DCMIPP pipe.
8309 * @param hdcmipp Pointer to DCMIPP handle
8310 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
8311 * @retval HAL status
8312 */
DCMIPP_Stop(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe)8313 static HAL_StatusTypeDef DCMIPP_Stop(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe)
8314 {
8315 uint32_t tickstart;
8316
8317 if (Pipe == DCMIPP_PIPE0)
8318 {
8319 /* Stop the capture */
8320 CLEAR_BIT(hdcmipp->Instance->P0FCTCR, DCMIPP_P0FCTCR_CPTREQ);
8321
8322 /* Poll CPTACT status till No capture currently active */
8323 tickstart = HAL_GetTick();
8324 do
8325 {
8326 if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
8327 {
8328 return HAL_ERROR;
8329 }
8330 } while ((hdcmipp->Instance->CMSR1 & DCMIPP_CMSR1_P0CPTACT) != 0U);
8331
8332 /* Disable DBM when enabled */
8333 if ((hdcmipp->Instance->P0PPCR & DCMIPP_P0PPCR_DBM) == DCMIPP_P0PPCR_DBM)
8334 {
8335 CLEAR_BIT(hdcmipp->Instance->P0PPCR, DCMIPP_P0PPCR_DBM);
8336 }
8337
8338 /* Disable the pipe */
8339 CLEAR_BIT(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_PIPEN);
8340
8341 /* Disable all interrupts for this pipe */
8342 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE0_FRAME | DCMIPP_IT_PIPE0_VSYNC | DCMIPP_IT_PIPE0_LINE | \
8343 DCMIPP_IT_PIPE0_LIMIT | DCMIPP_IT_PIPE0_OVR);
8344
8345 }
8346 else if (Pipe == DCMIPP_PIPE1)
8347 {
8348 /* Stop the capture */
8349 CLEAR_BIT(hdcmipp->Instance->P1FCTCR, DCMIPP_P1FCTCR_CPTREQ);
8350
8351 /* Poll CPTACT status till No capture currently active */
8352 tickstart = HAL_GetTick();
8353 do
8354 {
8355 if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
8356 {
8357 return HAL_ERROR;
8358 }
8359 } while ((hdcmipp->Instance->CMSR1 & DCMIPP_CMSR1_P1CPTACT) != 0U);
8360
8361 /* Disable DBM when enabled */
8362 if ((hdcmipp->Instance->P1PPCR & DCMIPP_P1PPCR_DBM) == DCMIPP_P1PPCR_DBM)
8363 {
8364 CLEAR_BIT(hdcmipp->Instance->P1PPCR, DCMIPP_P1PPCR_DBM);
8365 }
8366
8367 /* Disable the pipe */
8368 CLEAR_BIT(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_PIPEN);
8369
8370 /* Disable all interrupts for this pipe */
8371 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE1_FRAME | DCMIPP_IT_PIPE1_VSYNC | DCMIPP_IT_PIPE1_LINE | \
8372 DCMIPP_IT_PIPE1_OVR);
8373
8374 }
8375 else
8376 {
8377 /* Stop the capture */
8378 CLEAR_BIT(hdcmipp->Instance->P2FCTCR, DCMIPP_P2FCTCR_CPTREQ);
8379
8380 /* Poll CPTACT status till No capture currently active */
8381 tickstart = HAL_GetTick();
8382 do
8383 {
8384 if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
8385 {
8386 return HAL_ERROR;
8387 }
8388 } while ((hdcmipp->Instance->CMSR1 & DCMIPP_CMSR1_P2CPTACT) != 0U);
8389
8390 /* Disable the pipe */
8391 CLEAR_BIT(hdcmipp->Instance->P2FSCR, DCMIPP_P2FSCR_PIPEN);
8392
8393 /* Disable DBM when enabled */
8394 if ((hdcmipp->Instance->P2PPCR & DCMIPP_P2PPCR_DBM) == DCMIPP_P2PPCR_DBM)
8395 {
8396 CLEAR_BIT(hdcmipp->Instance->P2PPCR, DCMIPP_P2PPCR_DBM);
8397 }
8398
8399 /* Disable all interrupts for this pipe */
8400 __HAL_DCMIPP_DISABLE_IT(hdcmipp, DCMIPP_IT_PIPE2_FRAME | DCMIPP_IT_PIPE2_VSYNC | DCMIPP_IT_PIPE2_LINE | \
8401 DCMIPP_IT_PIPE2_OVR);
8402
8403 }
8404
8405 return HAL_OK;
8406 }
8407 /**
8408 * @brief Configure and enable the specified CSI virtual channel for a DCMIPP pipe.
8409 * @param hdcmipp Pointer to DCMIPP handle
8410 * @param Pipe Specifies the DCMIPP pipe, can be a value from @ref DCMIPP_Pipes
8411 * @param VirtualChannel Specifies the virtual channel, can be a value from @ref DCMIPP_Virtual_Channel
8412 */
DCMIPP_CSI_SetVCConfig(DCMIPP_HandleTypeDef * hdcmipp,uint32_t Pipe,uint32_t VirtualChannel)8413 static HAL_StatusTypeDef DCMIPP_CSI_SetVCConfig(DCMIPP_HandleTypeDef *hdcmipp, uint32_t Pipe, uint32_t VirtualChannel)
8414 {
8415 CSI_TypeDef *csi_instance;
8416 csi_instance = CSI;
8417 uint32_t tickstart;
8418
8419 /* Set Virtual Channel ID for the selected Pipe */
8420 if (Pipe == DCMIPP_PIPE0)
8421 {
8422 MODIFY_REG(hdcmipp->Instance->P0FSCR, DCMIPP_P0FSCR_VC, VirtualChannel << DCMIPP_P0FSCR_VC_Pos);
8423 }
8424 else if (Pipe == DCMIPP_PIPE1)
8425 {
8426 MODIFY_REG(hdcmipp->Instance->P1FSCR, DCMIPP_P1FSCR_VC, VirtualChannel << DCMIPP_P1FSCR_VC_Pos);
8427 }
8428 else
8429 {
8430 /* Those bit fields are meaningful when PIPEDIFF = 1: Pipe1, Pipe2 is fully independent */
8431 if ((hdcmipp->Instance->P1FSCR & DCMIPP_P1FSCR_PIPEDIFF) == DCMIPP_P1FSCR_PIPEDIFF)
8432 {
8433 /* Set Virtual Channel ID and DTIDA for Pipe2 */
8434 MODIFY_REG(hdcmipp->Instance->P2FSCR, DCMIPP_P2FSCR_VC, VirtualChannel << DCMIPP_P2FSCR_VC_Pos);
8435 }
8436 }
8437
8438 /* Enable the selected virtual channel */
8439 switch (VirtualChannel)
8440 {
8441 case DCMIPP_VIRTUAL_CHANNEL1:
8442 SET_BIT(csi_instance->CR, CSI_CR_VC1START);
8443 break;
8444 case DCMIPP_VIRTUAL_CHANNEL2:
8445 SET_BIT(csi_instance->CR, CSI_CR_VC2START);
8446 break;
8447 case DCMIPP_VIRTUAL_CHANNEL3:
8448 SET_BIT(csi_instance->CR, CSI_CR_VC3START);
8449 break;
8450 default:
8451 /* DCMIPP_VIRTUAL_CHANNEL0: */
8452 SET_BIT(csi_instance->CR, CSI_CR_VC0START);
8453 break;
8454 }
8455
8456 /* wait for the selected virtual channel active state */
8457 tickstart = HAL_GetTick();
8458 do
8459 {
8460 if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
8461 {
8462 return HAL_ERROR;
8463 }
8464 } while ((csi_instance->SR0 & (CSI_SR0_VC0STATEF << VirtualChannel)) != (CSI_SR0_VC0STATEF << VirtualChannel));
8465
8466 /* Enable the SOF and EOF interrupts for the selected virtual channel */
8467 __HAL_DCMIPP_CSI_ENABLE_IT(csi_instance, (DCMIPP_CSI_IT_EOF0 << VirtualChannel) | \
8468 (DCMIPP_CSI_IT_SOF0 << VirtualChannel));
8469 return HAL_OK;
8470 }
8471 /**
8472 * @brief Stop the specified CSI virtual channel.
8473 * @param hdcmipp Pointer to DCMIPP handle
8474 * @param VirtualChannel Specifies the virtual channel, can be a value from @ref DCMIPP_Virtual_Channel
8475 */
DCMIPP_CSI_VCStop(const DCMIPP_HandleTypeDef * hdcmipp,uint32_t VirtualChannel)8476 static HAL_StatusTypeDef DCMIPP_CSI_VCStop(const DCMIPP_HandleTypeDef *hdcmipp, uint32_t VirtualChannel)
8477 {
8478 CSI_TypeDef *csi_instance;
8479 csi_instance = CSI;
8480 uint32_t tickstart;
8481
8482 UNUSED(hdcmipp);
8483
8484 /* Enable the selected virtual channel */
8485 switch (VirtualChannel)
8486 {
8487 case DCMIPP_VIRTUAL_CHANNEL1:
8488 SET_BIT(csi_instance->CR, CSI_CR_VC1STOP);
8489 break;
8490 case DCMIPP_VIRTUAL_CHANNEL2:
8491 SET_BIT(csi_instance->CR, CSI_CR_VC2STOP);
8492 break;
8493 case DCMIPP_VIRTUAL_CHANNEL3:
8494 SET_BIT(csi_instance->CR, CSI_CR_VC3STOP);
8495 break;
8496 default:
8497 /* DCMIPP_VIRTUAL_CHANNEL0: */
8498 SET_BIT(csi_instance->CR, CSI_CR_VC0STOP);
8499 break;
8500 }
8501
8502 /* wait for the selected virtual channel active state */
8503 tickstart = HAL_GetTick();
8504 do
8505 {
8506 if ((HAL_GetTick() - tickstart) > DCMIPP_TIMEOUT)
8507 {
8508 return HAL_ERROR;
8509 }
8510 } while ((csi_instance->SR0 & (CSI_SR0_VC0STATEF << VirtualChannel)) == (CSI_SR0_VC0STATEF << VirtualChannel));
8511
8512
8513 /* Enable the SOF and EOF interrupts for the selected virtual channel */
8514 __HAL_DCMIPP_CSI_DISABLE_IT(csi_instance, (DCMIPP_CSI_IT_EOF0 << VirtualChannel) | \
8515 (DCMIPP_CSI_IT_SOF0 << VirtualChannel));
8516 return HAL_OK;
8517 }
8518 /**
8519 * @}
8520 */
8521
8522 /**
8523 * @}
8524 */
8525 /**
8526 * @}
8527 */
8528 #endif /* DCMIPP */
8529 #endif /* HAL_DCMIPP_MODULE_ENABLED */
8530
8531
