1 /**
2 ******************************************************************************
3 * @file stm32n6xx_hal_cryp.c
4 * @author MCD Application Team
5 * @brief CRYP HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Cryptography (CRYP) peripheral:
8 * + Initialization and de-initialization functions
9 * + AES processing functions
10 * + DMA callback functions
11 * + CRYP IRQ handler management
12 * + Peripheral State functions
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2023 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### How to use this driver #####
28 ==============================================================================
29 [..]
30 The CRYP HAL driver can be used in CRYP IP as follows:
31
32 (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
33 (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
34 (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
35 (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
36 (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
37 (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
38 (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
39 (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
40 (+++) Configure and enable two DMA streams one for managing data transfer from
41 memory to peripheral (input stream) and another stream for managing data
42 transfer from peripheral to memory (output stream)
43 (+++) Associate the initialized DMA handle to the CRYP DMA handle
44 using __HAL_LINKDMA()
45 (+++) Configure the priority and enable the NVIC for the transfer complete
46 interrupt on the two DMA Streams. The output stream should have higher
47 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
48
49 (#)Initialize the CRYP according to the specified parameters :
50 (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
51 (##) The key size: 128, 192 or 256.
52 (##) The AlgoMode AES Algorithm ECB/CBC/CTR/GCM or CCM.
53 (##) The initialization vector (counter). It is not used in ECB mode.
54 (##) The key buffer used for encryption/decryption.
55 (##) The Header used only in AES GCM and CCM Algorithm for authentication.
56 (##) The HeaderSize used to give size of header buffer in words or bytes, depending upon
57 HeaderWidthUnit field.
58 (##) The HeaderWidthUnit field. It specifies whether the header length
59 (##) The HeaderSize The size of header buffer in word.
60 (##) The B0 block is the first authentication block used only in AES CCM mode.
61
62 (#)Three processing (encryption/decryption) functions are available:
63 (##) Polling mode: encryption and decryption APIs are blocking functions
64 i.e. they process the data and wait till the processing is finished,
65 e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
66 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
67 i.e. they process the data under interrupt,
68 e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
69 (##) DMA mode: encryption and decryption APIs are not blocking functions
70 i.e. the data transfer is ensured by DMA,
71 e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
72
73 (#)When the processing function is called at first time after HAL_CRYP_Init()
74 the CRYP peripheral is configured and processes the buffer in input.
75 At second call, no need to Initialize the CRYP, user have to get current configuration via
76 HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
77 new parameters, finally user can start encryption/decryption.
78
79 (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
80
81 (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
82 without having to configure again the Key or the Initialization Vector between each API call,
83 the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
84 Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(),
85 HAL_CRYP_Encrypt_DMA()or HAL_CRYP_Decrypt_DMA().
86
87 [..]
88 The cryptographic processor supports following standards:
89 (#) The advanced encryption standard (AES) supported by CRYP:
90 (##)128-bit data block processing
91 (##) chaining modes supported :
92 (+++) Electronic Code Book(ECB)
93 (+++) Cipher Block Chaining (CBC)
94 (+++) Counter mode (CTR)
95 (+++) Galois/counter mode (GCM/GMAC)
96 (+++) Counter with Cipher Block Chaining-Message(CCM)
97 (##) keys length Supported :
98 (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
99
100 [..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
101 (#) Algorithm supported :
102 (##) Galois/counter mode (GCM)
103 (##) Galois message authentication code (GMAC) :is exactly the same as
104 GCM algorithm composed only by an header.
105 (#) Four phases are performed in GCM :
106 (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
107 (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
108 computation only.
109 (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
110 encryption + data XORing. It works in a similar way for ciphertext (C).
111 (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
112 HAL_CRYPEx_AESGCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond
113 to the Tag. user should consider only part of this 4 words, if Tag length is less than 128 bits.
114 (#) structure of message construction in GCM is defined as below :
115 (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
116 (##) The authenticated header A (also knows as Additional Authentication Data AAD)
117 this part of the message is only authenticated, not encrypted.
118 (##) The plaintext message P is both authenticated and encrypted as ciphertext.
119 GCM standard specifies that ciphertext has same bit length as the plaintext.
120 (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
121 (on 64 bits)
122
123 [..] This section describe The AES Counter with Cipher Block Chaining-Message
124 Authentication Code (CCM) supported by both CRYP IP:
125 (#) Specific parameters for CCM :
126
127 (##) B0 block : According to NIST Special Publication 800-38C,
128 The first block B0 is formatted as follows, where l(m) is encoded in
129 most-significant-byte first order(see below table 3)
130
131 (+++) Q: a bit string representation of the octet length of P (plaintext)
132 (+++) q The octet length of the binary representation of the octet length of the payload
133 (+++) A nonce (N), n The octet length of the where n+q=15.
134 (+++) Flags: most significant octet containing four flags for control information,
135 (+++) t The octet length of the MAC.
136 (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
137 the associated data length expressed in bytes (a) defined as below:
138 (+++) If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
139 (+++) If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
140 (+++) If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
141 (##) CTRx block : control blocks
142 (+++) Generation of CTR1 from first block B0 information :
143 equal to B0 with first 5 bits zeroed and most significant bits storing octet
144 length of P also zeroed, then incremented by one ( see below Table 4)
145 (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.
146
147 (#) Four phases are performed in CCM for CRYP IP:
148 (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
149 (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
150 computation only.
151 (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
152 encryption + data XORing. It works in a similar way for ciphertext (C).
153 (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
154 HAL_CRYPEx_AESCCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond to the Tag.
155 user should consider only part of this 4 words, if Tag length is less than 128 bits
156
157 *** Callback registration ***
158 =============================
159
160 [..]
161 The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
162 allows the user to configure dynamically the driver callbacks.
163 Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
164 to register an interrupt callback.
165
166 [..]
167 Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
168 (+) InCpltCallback : Input FIFO transfer completed callback.
169 (+) OutCpltCallback : Output FIFO transfer completed callback.
170 (+) ErrorCallback : callback for error detection.
171 (+) MspInitCallback : CRYP MspInit.
172 (+) MspDeInitCallback : CRYP MspDeInit.
173 This function takes as parameters the HAL peripheral handle, the Callback ID
174 and a pointer to the user callback function.
175
176 [..]
177 Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
178 weak function.
179 @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
180 and the Callback ID.
181 This function allows to reset following callbacks:
182 (+) InCpltCallback : Input FIFO transfer completed callback.
183 (+) OutCpltCallback : Output FIFO transfer completed callback.
184 (+) ErrorCallback : callback for error detection.
185 (+) MspInitCallback : CRYP MspInit.
186 (+) MspDeInitCallback : CRYP MspDeInit.
187
188 [..]
189 By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
190 all callbacks are set to the corresponding weak functions :
191 examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
192 Exception done for MspInit and MspDeInit functions that are
193 reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
194 these callbacks are null (not registered beforehand).
195 if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
196 keep and use the user MspInit/MspDeInit functions (registered beforehand)
197
198 [..]
199 Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
200 Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
201 in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
202 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
203 In that case first register the MspInit/MspDeInit user callbacks
204 using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
205 or @ref HAL_CRYP_Init() function.
206
207 [..]
208 When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
209 not defined, the callback registration feature is not available and all callbacks
210 are set to the corresponding weak functions.
211
212 @endverbatim
213
214 Table 1. Initial Counter Block (ICB)
215 +-------------------------------------------------------+
216 | Initialization vector (IV) | Counter |
217 |----------------|----------------|-----------|---------|
218 127 95 63 31 0
219
220
221 Bit Number Register Contents
222 ---------- --------------- -----------
223 127 ...96 CRYP_IV1R[31:0] ICB[127:96]
224 95 ...64 CRYP_IV1L[31:0] B0[95:64]
225 63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
226 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
227
228 Table 2. GCM last block definition
229
230 +-------------------------------------------------------------------+
231 | Bit[0] | Bit[32] | Bit[64] | Bit[96] |
232 |-----------|--------------------|-----------|----------------------|
233 | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
234 |-----------|--------------------|-----------|----------------------|
235
236 Table 3. B0 block
237 Octet Number Contents
238 ------------ ---------
239 0 Flags
240 1 ... 15-q Nonce N
241 16-q ... 15 Q
242
243 the Flags field is formatted as follows:
244
245 Bit Number Contents
246 ---------- ----------------------
247 7 Reserved (always zero)
248 6 Adata
249 5 ... 3 (t-2)/2
250 2 ... 0 [q-1]3
251
252 Table 4. CTRx block
253 Bit Number Register Contents
254 ---------- --------------- -----------
255 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
256 bit 0 that is set to 1
257 95 ...64 CRYP_IV1L[31:0] B0[95:64]
258 63 ... 32 CRYP_IV0R[31:0] B0[63:32]
259 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
260 */
261
262 /* Includes ------------------------------------------------------------------*/
263 #include "stm32n6xx_hal.h"
264
265 /** @addtogroup STM32N6xx_HAL_Driver
266 * @{
267 */
268
269 #if defined (CRYP)
270
271 /** @defgroup CRYP CRYP
272 * @brief CRYP HAL module driver.
273 * @{
274 */
275
276
277 #ifdef HAL_CRYP_MODULE_ENABLED
278
279 /* Private typedef -----------------------------------------------------------*/
280 /* Private define ------------------------------------------------------------*/
281 /** @addtogroup CRYP_Private_Defines
282 * @{
283 */
284 #define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/
285 #define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is
286 299 clock cycles.*/
287 #define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
288
289 #define CRYP_GENERAL_TIMEOUT 500U
290
291 #define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
292 #define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
293 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
294 #define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */
295 #define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U /*!< GCM/CCM payload phase is suspended */
296 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
297 #define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in
298 DMA mode */
299
300 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
301 #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
302 #define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */
303 #define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */
304 #define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */
305 #endif /* USE_HAL_CRYP_ONLY */
306
307 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
308 #define SAES_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
309 #define SAES_PHASE_HEADER SAES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
310 #define SAES_PHASE_PAYLOAD SAES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
311 #define SAES_PHASE_FINAL SAES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
312 #endif /* USE_HAL_SAES_ONLY */
313
314 /* CTR1 information to use in CCM algorithm */
315 #define CRYP_CCM_CTR1_0 0x07FFFFFFU
316 #define CRYP_CCM_CTR1_1 0xFFFFFF00U
317 #define CRYP_CCM_CTR1_2 0x00000001U
318
319 #define IT_SUSPENDED 0x00000000U
320 #define DMA_SUSPENDED 0x00000001U
321
322 #define ALGOMODE_CRYP_TO_CHMOD_SAES 0
323 #define ALGOMODE_SAES_TO_CHMOD_CRYP 1
324 /**
325 * @}
326 */
327
328
329 /* Private macro -------------------------------------------------------------*/
330 /** @addtogroup CRYP_Private_Macros
331 * @{
332 */
333
334 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
335 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{MODIFY_REG(((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR, \
336 CRYP_CR_GCM_CCMPH, (__PHASE__)); \
337 }while(0)
338 #endif /* USE_HAL_CRYP_ONLY */
339
340 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
341 #define SAES_SET_PHASE(__HANDLE__, __PHASE__) do{MODIFY_REG(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, \
342 SAES_CR_GCMPH, (__PHASE__)); \
343 }while(0)
344 #endif /* USE_HAL_SAES_ONLY */
345
346 #define CRYP_FIFO_FLUSH(__HANDLE__) (((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR |= CRYP_CR_FFLUSH)
347
348 #define SAES_IP_RESET(__HANDLE__) do { \
349 __IO uint32_t tmpreg; \
350 SET_BIT(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, SAES_CR_IPRST); \
351 /* Delay after an SAES peripheral IPRST */ \
352 tmpreg = READ_BIT(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, \
353 SAES_CR_IPRST); \
354 CLEAR_BIT(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, SAES_CR_IPRST); \
355 UNUSED(tmpreg); \
356 } while(0)
357
358 /**
359 * @}
360 */
361
362 /* Private struct -------------------------------------------------------------*/
363 /* Private variables ---------------------------------------------------------*/
364 /* Private function prototypes -----------------------------------------------*/
365 /** @addtogroup CRYP_Private_Functions_prototypes
366 * @{
367 */
368
369 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
370 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
371 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
372 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
373 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
374 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
375 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
376 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
377 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
378 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
379 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
380 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
381 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
382 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
383 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
384 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
385 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
386 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
387 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
388 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
389 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
390 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
391 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
392 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
393 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
394 #endif /* USE_HAL_CRYP_ONLY */
395 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
396 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
397 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
398 #endif /* USE_HAL_SAES_ONLY */
399 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
400 static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output);
401 static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input);
402 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
403 static void CRYP_Read_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t Algorithm);
404 #endif /* USE_HAL_CRYP_ONLY */
405 static void CRYP_Write_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t Algorithm);
406 static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp);
407 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
408 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
409 static uint32_t CRYP_SAES_AlgoConversion(uint32_t algo, uint32_t order);
410 #endif /* USE_HAL_SAES_ONLY */
411 /**
412 * @}
413 */
414
415 /* Exported functions ---------------------------------------------------------*/
416
417 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
418 * @{
419 */
420
421
422 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
423 * @brief CRYP Initialization and Configuration functions.
424 *
425 @verbatim
426 ========================================================================================
427 ##### Initialization, de-initialization and Set and Get configuration functions #####
428 ========================================================================================
429 [..] This section provides functions allowing to:
430 (+) Initialize the CRYP
431 (+) DeInitialize the CRYP
432 (+) Initialize the CRYP MSP
433 (+) DeInitialize the CRYP MSP
434 (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
435 Parameters which are configured in This section are :
436 (++) Key size
437 (++) Data Type : 32, 16, 8 or 1 bit
438 ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
439 (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
440
441
442 @endverbatim
443 * @{
444 */
445
446
447 /**
448 * @brief Initializes the CRYP according to the specified
449 * parameters in the CRYP_ConfigTypeDef and creates the associated handle.
450 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
451 * the configuration information for CRYP module
452 * @retval HAL status
453 */
HAL_CRYP_Init(CRYP_HandleTypeDef * hcryp)454 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
455 {
456 /* Check the CRYP handle allocation */
457 if (hcryp == NULL)
458 {
459 return HAL_ERROR;
460 }
461
462 #if ((USE_HAL_CRYP_ONLY == 1) && (USE_HAL_SAES_ONLY == 0))
463 if (IS_SAES_INSTANCE(hcryp->Instance))
464 {
465 return HAL_ERROR;
466 }
467 #endif /* USE_HAL_CRYP_ONLY */
468
469 #if ((USE_HAL_CRYP_ONLY == 0) && (USE_HAL_SAES_ONLY == 1))
470 if (IS_CRYP_INSTANCE(hcryp->Instance))
471 {
472 return HAL_ERROR;
473 }
474 #endif /* USE_HAL_SAES_ONLY */
475
476 /* Check parameters */
477 #ifdef USE_FULL_ASSERT
478 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
479 if (IS_CRYP_INSTANCE(hcryp->Instance))
480 {
481 assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
482 assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
483 assert_param(IS_CRYP_KEYMODE(hcryp->Init.KeyMode));
484 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
485 {
486 return HAL_ERROR; /* CRYP does not support BYTE as header width unit */
487 }
488 }
489 #endif /* USE_HAL_CRYP_ONLY */
490 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
491 if (IS_SAES_INSTANCE(hcryp->Instance))
492 {
493 assert_param(IS_SAES_KEYSIZE(hcryp->Init.KeySize));
494 assert_param(IS_SAES_ALGORITHM(hcryp->Init.Algorithm));
495 assert_param(IS_SAES_KEYMODE(hcryp->Init.KeyMode));
496 assert_param(IS_SAES_KEYPROT(hcryp->Init.KeyProtection));
497 assert_param(IS_SAES_KEYSEL(hcryp->Init.KeySelect));
498 }
499 #endif /* USE_HAL_SAES_ONLY */
500 assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
501 assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
502 #endif /* USE_FULL_ASSERT */
503
504 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
505 if (hcryp->State == HAL_CRYP_STATE_RESET)
506 {
507 /* Allocate lock resource and initialize it */
508 hcryp->Lock = HAL_UNLOCKED;
509
510 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy InCpltCallback */
511 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy OutCpltCallback */
512 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy ErrorCallback */
513
514 if (hcryp->MspInitCallback == NULL)
515 {
516 hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy MspInit */
517 }
518
519 /* Init the low level hardware */
520 hcryp->MspInitCallback(hcryp);
521 }
522 #else
523 if (hcryp->State == HAL_CRYP_STATE_RESET)
524 {
525 /* Allocate lock resource and initialize it */
526 hcryp->Lock = HAL_UNLOCKED;
527
528 /* Init the low level hardware */
529 HAL_CRYP_MspInit(hcryp);
530 }
531 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
532
533 /* Set the key size, data type and algorithm */
534 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
535 if (IS_CRYP_INSTANCE(hcryp->Instance))
536 {
537 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR,
538 CRYP_CR_KMOD | CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
539 hcryp->Init.KeyMode | hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
540 }
541 #endif /* USE_HAL_CRYP_ONLY */
542 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
543 if (IS_SAES_INSTANCE(hcryp->Instance))
544 {
545 /* Reset of SAES */
546 SAES_IP_RESET(hcryp);
547
548 /* Wait for BUSY flag to go to 0 */
549 if (CRYP_WaitOnBUSYFlag(hcryp, CRYP_GENERAL_TIMEOUT) != HAL_OK)
550 {
551 /* Disable the CRYP peripheral clock */
552 __HAL_CRYP_DISABLE(hcryp);
553
554 /* Change state */
555 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
556 hcryp->State = HAL_CRYP_STATE_READY;
557
558 /* Process unlocked */
559 __HAL_UNLOCK(hcryp);
560 return HAL_ERROR;
561 }
562
563 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR,
564 SAES_CR_KEYSEL | SAES_CR_KMOD | SAES_CR_KEYPROT | SAES_CR_DATATYPE | SAES_CR_KEYSIZE | SAES_CR_CHMOD,
565 hcryp->Init.KeySelect | hcryp->Init.KeyMode | hcryp->Init.KeyProtection | \
566 SAES_CONV_DATATYPE(hcryp->Init.DataType) | SAES_CONV_KEYSIZE(hcryp->Init.KeySize) | \
567 CRYP_SAES_AlgoConversion(hcryp->Init.Algorithm, ALGOMODE_CRYP_TO_CHMOD_SAES));
568 }
569 #endif /* USE_HAL_CRYP_ONLY */
570
571 /* Read Device ID to indicate CRYP1 IP Version */
572 hcryp->Version = HAL_GetREVID();
573
574 /* Reset Error Code field */
575 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
576
577 /* Reset peripheral Key and IV configuration flag */
578 hcryp->KeyIVConfig = 0U;
579
580 /* Change the CRYP state */
581 hcryp->State = HAL_CRYP_STATE_READY;
582
583 /* Set the default CRYP phase */
584 hcryp->Phase = CRYP_PHASE_READY;
585
586 /* Return function status */
587 return HAL_OK;
588 }
589
590 /**
591 * @brief De-Initializes the CRYP peripheral.
592 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
593 * the configuration information for CRYP module
594 * @retval HAL status
595 */
HAL_CRYP_DeInit(CRYP_HandleTypeDef * hcryp)596 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
597 {
598 /* Check the CRYP handle allocation */
599 if (hcryp == NULL)
600 {
601 return HAL_ERROR;
602 }
603
604 #if ((USE_HAL_CRYP_ONLY == 1) && (USE_HAL_SAES_ONLY == 0))
605 if (IS_SAES_INSTANCE(hcryp->Instance))
606 {
607 return HAL_ERROR;
608 }
609 #endif /* USE_HAL_CRYP_ONLY */
610
611 #if ((USE_HAL_CRYP_ONLY == 0) && (USE_HAL_SAES_ONLY == 1))
612 if (IS_CRYP_INSTANCE(hcryp->Instance))
613 {
614 return HAL_ERROR;
615 }
616 #endif /* USE_HAL_SAES_ONLY */
617
618 /* Set the default CRYP phase */
619 hcryp->Phase = CRYP_PHASE_READY;
620
621 /* Reset CrypInCount and CrypOutCount */
622 hcryp->CrypInCount = 0;
623 hcryp->CrypOutCount = 0;
624 hcryp->CrypHeaderCount = 0;
625
626 /* Disable the CRYP peripheral clock */
627 __HAL_CRYP_DISABLE(hcryp);
628
629 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
630 if (hcryp->MspDeInitCallback == NULL)
631 {
632 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy MspDeInit */
633 }
634 /* DeInit the low level hardware */
635 hcryp->MspDeInitCallback(hcryp);
636
637 #else
638 /* DeInit the low level hardware: CLOCK, NVIC.*/
639 HAL_CRYP_MspDeInit(hcryp);
640 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
641
642 /* Change the CRYP state */
643 hcryp->State = HAL_CRYP_STATE_RESET;
644
645 /* Release Lock */
646 __HAL_UNLOCK(hcryp);
647
648 /* Return function status */
649 return HAL_OK;
650 }
651
652 /**
653 * @brief Configure the CRYP according to the specified
654 * parameters in the CRYP_ConfigTypeDef
655 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
656 * @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains
657 * the configuration information for CRYP module
658 * @retval HAL status
659 */
HAL_CRYP_SetConfig(CRYP_HandleTypeDef * hcryp,CRYP_ConfigTypeDef * pConf)660 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
661 {
662 /* Check the CRYP handle allocation */
663 if ((hcryp == NULL) || (pConf == NULL))
664 {
665 return HAL_ERROR;
666 }
667
668 /* Check parameters */
669 #ifdef USE_FULL_ASSERT
670 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
671 if (IS_CRYP_INSTANCE(hcryp->Instance))
672 {
673 assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
674 assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
675 assert_param(IS_CRYP_KEYMODE(pConf->KeyMode));
676 if (pConf->HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
677 {
678 return HAL_ERROR; /* CRYP does not support BYTE as header width unit */
679 }
680 }
681 #endif /* USE_HAL_CRYP_ONLY */
682 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
683 if (IS_SAES_INSTANCE(hcryp->Instance))
684 {
685 assert_param(IS_SAES_KEYSIZE(pConf->KeySize));
686 assert_param(IS_SAES_ALGORITHM(pConf->Algorithm));
687 assert_param(IS_SAES_KEYMODE(pConf->KeyMode));
688 assert_param(IS_SAES_KEYPROT(hcryp->Init.KeyProtection));
689 assert_param(IS_SAES_KEYSEL(pConf->KeySelect));
690 }
691 #endif /* USE_HAL_SAES_ONLY */
692 assert_param(IS_CRYP_DATATYPE(pConf->DataType));
693 assert_param(IS_CRYP_INIT(pConf->KeyIVConfigSkip));
694 #endif /* USE_FULL_ASSERT */
695
696
697 if (hcryp->State == HAL_CRYP_STATE_READY)
698 {
699 /* Change the CRYP state */
700 hcryp->State = HAL_CRYP_STATE_BUSY;
701
702 /* Process locked */
703 __HAL_LOCK(hcryp);
704
705 /* Set CRYP parameters */
706 hcryp->Init.DataType = pConf->DataType;
707 hcryp->Init.pKey = pConf->pKey;
708 hcryp->Init.Algorithm = pConf->Algorithm;
709 hcryp->Init.KeySize = pConf->KeySize;
710 hcryp->Init.pInitVect = pConf->pInitVect;
711 hcryp->Init.Header = pConf->Header;
712 hcryp->Init.HeaderSize = pConf->HeaderSize;
713 hcryp->Init.B0 = pConf->B0;
714 hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
715 hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
716 hcryp->Init.KeyMode = pConf->KeyMode;
717 hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
718 hcryp->Init.KeySelect = pConf->KeySelect;
719 hcryp->Init.KeyProtection = pConf->KeyProtection;
720
721 /* Set the key size, data type, algo Mode and operating mode*/
722 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
723 if (IS_CRYP_INSTANCE(hcryp->Instance))
724 {
725 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
726 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
727 }
728 #endif /* USE_HAL_CRYP_ONLY */
729 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
730 if (IS_SAES_INSTANCE(hcryp->Instance))
731 {
732 /*in case of HSW, HW, SW or AHK key selection, we should specify Key mode selection (SAES_CR_KMOD) */
733 if ((hcryp->Init.KeySelect != CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_WRAPPED))
734 {
735 /* Set key mode selection (Normal, Wrapped or Shared key )*/
736 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_WRAPPED);
737 }
738
739 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, \
740 SAES_CR_KEYSEL | SAES_CR_KMOD | SAES_CR_KEYPROT | SAES_CR_DATATYPE | SAES_CR_KEYSIZE | SAES_CR_CHMOD,
741 hcryp->Init.KeySelect | hcryp->Init.KeyMode | hcryp->Init.KeyProtection | \
742 SAES_CONV_DATATYPE(hcryp->Init.DataType) | SAES_CONV_KEYSIZE(hcryp->Init.KeySize) | \
743 CRYP_SAES_AlgoConversion(hcryp->Init.Algorithm, ALGOMODE_CRYP_TO_CHMOD_SAES));
744 }
745 #endif /* USE_HAL_SAES_ONLY */
746
747 /* Process Unlocked */
748 __HAL_UNLOCK(hcryp);
749
750 /* Reset Error Code field */
751 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
752
753 /* Change the CRYP state */
754 hcryp->State = HAL_CRYP_STATE_READY;
755
756 /* Set the default CRYP phase */
757 hcryp->Phase = CRYP_PHASE_READY;
758
759 /* Return function status */
760 return HAL_OK;
761 }
762 else
763 {
764 /* Process Unlocked */
765 __HAL_UNLOCK(hcryp);
766
767 /* Busy error code field */
768 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
769 return HAL_ERROR;
770 }
771 }
772
773 /**
774 * @brief Get CRYP Configuration parameters in associated handle.
775 * @param pConf: pointer to a CRYP_ConfigTypeDef structure
776 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
777 * the configuration information for CRYP module
778 * @retval HAL status
779 */
HAL_CRYP_GetConfig(CRYP_HandleTypeDef * hcryp,CRYP_ConfigTypeDef * pConf)780 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
781 {
782 /* Check the CRYP handle allocation */
783 if ((hcryp == NULL) || (pConf == NULL))
784 {
785 return HAL_ERROR;
786 }
787
788 if (hcryp->State == HAL_CRYP_STATE_READY)
789 {
790 /* Change the CRYP state */
791 hcryp->State = HAL_CRYP_STATE_BUSY;
792
793 /* Process locked */
794 __HAL_LOCK(hcryp);
795
796 /* Get CRYP parameters */
797 pConf->DataType = hcryp->Init.DataType;
798 pConf->pKey = hcryp->Init.pKey;
799 pConf->Algorithm = hcryp->Init.Algorithm;
800 pConf->KeySize = hcryp->Init.KeySize ;
801 pConf->pInitVect = hcryp->Init.pInitVect;
802 pConf->Header = hcryp->Init.Header ;
803 pConf->HeaderSize = hcryp->Init.HeaderSize;
804 pConf->B0 = hcryp->Init.B0;
805 pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
806 pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
807 pConf->KeyMode = hcryp->Init.KeyMode;
808 pConf->KeySelect = hcryp->Init.KeySelect;
809 hcryp->Init.KeyProtection = pConf->KeyProtection;
810 pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
811
812 /* Process Unlocked */
813 __HAL_UNLOCK(hcryp);
814
815 /* Change the CRYP state */
816 hcryp->State = HAL_CRYP_STATE_READY;
817
818 /* Return function status */
819 return HAL_OK;
820 }
821 else
822 {
823 /* Process Unlocked */
824 __HAL_UNLOCK(hcryp);
825
826 /* Busy error code field */
827 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
828 return HAL_ERROR;
829 }
830 }
831 /**
832 * @brief Initializes the CRYP MSP.
833 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
834 * the configuration information for CRYP module
835 * @retval None
836 */
HAL_CRYP_MspInit(CRYP_HandleTypeDef * hcryp)837 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
838 {
839 /* Prevent unused argument(s) compilation warning */
840 UNUSED(hcryp);
841
842 /* NOTE : This function Should not be modified, when the callback is needed,
843 the HAL_CRYP_MspInit could be implemented in the user file
844 */
845 }
846
847 /**
848 * @brief DeInitializes CRYP MSP.
849 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
850 * the configuration information for CRYP module
851 * @retval None
852 */
HAL_CRYP_MspDeInit(CRYP_HandleTypeDef * hcryp)853 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
854 {
855 /* Prevent unused argument(s) compilation warning */
856 UNUSED(hcryp);
857
858 /* NOTE : This function Should not be modified, when the callback is needed,
859 the HAL_CRYP_MspDeInit could be implemented in the user file
860 */
861 }
862
863 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
864 /**
865 * @brief Register a User CRYP Callback
866 * To be used instead of the weak predefined callback
867 * @param hcryp cryp handle
868 * @param CallbackID ID of the callback to be registered
869 * This parameter can be one of the following values:
870 * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
871 * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
872 * @arg @ref HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID
873 * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
874 * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
875 * @param pCallback pointer to the Callback function
876 * @retval status
877 */
HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef * hcryp,HAL_CRYP_CallbackIDTypeDef CallbackID,pCRYP_CallbackTypeDef pCallback)878 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
879 pCRYP_CallbackTypeDef pCallback)
880 {
881 HAL_StatusTypeDef status = HAL_OK;
882
883 if (pCallback == NULL)
884 {
885 /* Update the error code */
886 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
887
888 return HAL_ERROR;
889 }
890 /* Process locked */
891 __HAL_LOCK(hcryp);
892
893 if (hcryp->State == HAL_CRYP_STATE_READY)
894 {
895 switch (CallbackID)
896 {
897 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
898 hcryp->InCpltCallback = pCallback;
899 break;
900
901 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
902 hcryp->OutCpltCallback = pCallback;
903 break;
904
905 case HAL_CRYP_ERROR_CB_ID :
906 hcryp->ErrorCallback = pCallback;
907 break;
908
909 case HAL_CRYP_MSPINIT_CB_ID :
910 hcryp->MspInitCallback = pCallback;
911 break;
912
913 case HAL_CRYP_MSPDEINIT_CB_ID :
914 hcryp->MspDeInitCallback = pCallback;
915 break;
916
917 default :
918 /* Update the error code */
919 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
920 /* Return error status */
921 status = HAL_ERROR;
922 break;
923 }
924 }
925 else if (hcryp->State == HAL_CRYP_STATE_RESET)
926 {
927 switch (CallbackID)
928 {
929 case HAL_CRYP_MSPINIT_CB_ID :
930 hcryp->MspInitCallback = pCallback;
931 break;
932
933 case HAL_CRYP_MSPDEINIT_CB_ID :
934 hcryp->MspDeInitCallback = pCallback;
935 break;
936
937 default :
938 /* Update the error code */
939 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
940 /* Return error status */
941 status = HAL_ERROR;
942 break;
943 }
944 }
945 else
946 {
947 /* Update the error code */
948 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
949 /* Return error status */
950 status = HAL_ERROR;
951 }
952
953 /* Release Lock */
954 __HAL_UNLOCK(hcryp);
955
956 return status;
957 }
958
959 /**
960 * @brief Unregister an CRYP Callback
961 * CRYP callback is redirected to the weak predefined callback
962 * @param hcryp cryp handle
963 * @param CallbackID ID of the callback to be unregistered
964 * This parameter can be one of the following values:
965 * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
966 * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
967 * @arg @ref HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID
968 * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
969 * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
970 * @retval status
971 */
HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef * hcryp,HAL_CRYP_CallbackIDTypeDef CallbackID)972 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
973 {
974 HAL_StatusTypeDef status = HAL_OK;
975
976 /* Process locked */
977 __HAL_LOCK(hcryp);
978
979 if (hcryp->State == HAL_CRYP_STATE_READY)
980 {
981 switch (CallbackID)
982 {
983 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
984 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy InCpltCallback */
985 break;
986
987 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
988 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy OutCpltCallback */
989 break;
990
991 case HAL_CRYP_ERROR_CB_ID :
992 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy ErrorCallback */
993 break;
994
995 case HAL_CRYP_MSPINIT_CB_ID :
996 hcryp->MspInitCallback = HAL_CRYP_MspInit;
997 break;
998
999 case HAL_CRYP_MSPDEINIT_CB_ID :
1000 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
1001 break;
1002
1003 default :
1004 /* Update the error code */
1005 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
1006 /* Return error status */
1007 status = HAL_ERROR;
1008 break;
1009 }
1010 }
1011 else if (hcryp->State == HAL_CRYP_STATE_RESET)
1012 {
1013 switch (CallbackID)
1014 {
1015 case HAL_CRYP_MSPINIT_CB_ID :
1016 hcryp->MspInitCallback = HAL_CRYP_MspInit;
1017 break;
1018
1019 case HAL_CRYP_MSPDEINIT_CB_ID :
1020 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
1021 break;
1022
1023 default :
1024 /* Update the error code */
1025 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
1026 /* Return error status */
1027 status = HAL_ERROR;
1028 break;
1029 }
1030 }
1031 else
1032 {
1033 /* Update the error code */
1034 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;;
1035 /* Return error status */
1036 status = HAL_ERROR;
1037 }
1038
1039 /* Release Lock */
1040 __HAL_UNLOCK(hcryp);
1041
1042 return status;
1043 }
1044 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
1045
1046
1047 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
1048 /**
1049 * @brief Request CRYP processing suspension when in interruption mode.
1050 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1051 * the configuration information for CRYP module.
1052 * @note Set the handle field SuspendRequest to the appropriate value so that
1053 * the on-going CRYP processing is suspended as soon as the required
1054 * conditions are met.
1055 * @note HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done
1056 * in non-blocking interrupt mode.
1057 * @retval None
1058 */
HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef * hcryp)1059 void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp)
1060 {
1061 /* Set Handle SuspendRequest field */
1062 hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
1063 }
1064
1065 /**
1066 * @brief Request CRYP processing suspension when in DMA mode.
1067 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1068 * the configuration information for CRYP module.
1069 * @note Set the handle field SuspendRequest to the appropriate value so that
1070 * the on-going CRYP processing is suspended as soon as the required
1071 * conditions are met.
1072 * @note HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done
1073 * in non-blocking DMA mode.
1074 * @retval None
1075 */
HAL_CRYP_DMAProcessSuspend(CRYP_HandleTypeDef * hcryp)1076 HAL_StatusTypeDef HAL_CRYP_DMAProcessSuspend(CRYP_HandleTypeDef *hcryp)
1077 {
1078 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1079 uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
1080 #endif /* USE_HAL_SAES_ONLY */
1081 uint32_t tmp_remaining_DMATransferSize_inWords;
1082 uint32_t tmp_initial_DMATransferSize_inWords;
1083
1084 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1085 if (IS_CRYP_INSTANCE(hcryp->Instance))
1086 {
1087 /* Stop the DMA transfers to the IN FIFO by clearing to 0 the DIEN bit in
1088 the CRYP_DMACR register */
1089 ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (~CRYP_DMACR_DIEN);
1090
1091 /* Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the
1092 CRYP_SR) and the BUSY bit is cleared */
1093 while (((((CRYP_TypeDef *)(hcryp->Instance))->SR) & (CRYP_SR_IFEM | CRYP_SR_OFNE | CRYP_SR_BUSY)) != CRYP_SR_IFEM)
1094 {
1095 /* nothing todo */
1096 }
1097
1098 /* Stop the DMA transfers from the OUT FIFO by clearing to 0 the DOEN
1099 bit in the CRYP_DMACR register */
1100 ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (~CRYP_DMACR_DOEN);
1101
1102 /* Disable the CRYP peripheral */
1103 __HAL_CRYP_DISABLE(hcryp);
1104 }
1105 #endif /* USE_HAL_CRYP_ONLY */
1106 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1107 if (IS_SAES_INSTANCE(hcryp->Instance))
1108 {
1109 /* Stop the DMA transfer to the IN FIFO by clearing the DMAINEN bit of the SAES_CR register */
1110 (((SAES_TypeDef *)(hcryp->Instance)))->CR &= (~SAES_CR_DMAINEN);
1111
1112 /* Wait for CCF flag to be raised */
1113 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
1114 {
1115 /* Disable the CRYP peripheral clock */
1116 __HAL_CRYP_DISABLE(hcryp);
1117
1118 /* Change state */
1119 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
1120 hcryp->State = HAL_CRYP_STATE_READY;
1121
1122 /* Process unlocked */
1123 __HAL_UNLOCK(hcryp);
1124 /*Call registered error callback*/
1125 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
1126 hcryp->ErrorCallback(hcryp);
1127 #else
1128 /*Call legacy error callback*/
1129 HAL_CRYP_ErrorCallback(hcryp);
1130 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
1131 }
1132
1133 /* Stop the DMA transfer from the OUT FIFO by clearing the DMAOUTEN bit of the SAES_CR register */
1134 ((SAES_TypeDef *)(hcryp->Instance))->CR &= (~SAES_CR_DMAOUTEN);
1135
1136 /* Clear the CCF flag by setting the CCF bit of the SAES_ICR register */
1137 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
1138 }
1139 #endif /* USE_HAL_SAES_ONLY */
1140
1141 /* At this point, DMA interface is disabled and no transfer is on-going */
1142 /* Retrieve from the DMA handle how many words remain to be read and written */
1143 /* DMA3 used, DMA_CBR1_BNDT in bytes, DMA_CSR_FIFOL in words */
1144 tmp_remaining_DMATransferSize_inWords = ((((DMA_Channel_TypeDef *)hcryp->hdmain->Instance)->CBR1) & \
1145 DMA_CBR1_BNDT) / 4U;
1146 tmp_remaining_DMATransferSize_inWords += ((((DMA_Channel_TypeDef *)hcryp->hdmain->Instance)->CSR) & \
1147 DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos;
1148
1149 /* Disable DMA channels */
1150 /* Note that the Abort function will
1151 - Clear the transfer error flags
1152 - Unlock
1153 - Set the State
1154 */
1155 if (HAL_DMA_Abort(hcryp->hdmain) != HAL_OK)
1156 {
1157 return HAL_ERROR;
1158 }
1159 if (HAL_DMA_Abort(hcryp->hdmaout) != HAL_OK)
1160 {
1161 return HAL_ERROR;
1162 }
1163
1164 /* Compute how many words were supposed to be transferred by DMA */
1165 /* hcryp->CrypInCount is in bytes, must be a multiple of 4 (no padding handled for ECB or CBC) */
1166 tmp_initial_DMATransferSize_inWords = ((uint32_t) hcryp->Size / 4U);
1167
1168 /* Accordingly, update the input and output pointers that points at the next word to be
1169 transferred to the Peripheral by DMA or read from the Peripheral by the DMA */
1170 hcryp->pCrypInBuffPtr += (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
1171 hcryp->pCrypOutBuffPtr += (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
1172
1173 /* And store in CrypInCount the remaining size to transfer (in words) */
1174 hcryp->CrypInCount = (uint16_t)tmp_remaining_DMATransferSize_inWords;
1175 hcryp->CrypOutCount = (uint16_t)tmp_remaining_DMATransferSize_inWords;
1176 hcryp->State = HAL_CRYP_STATE_SUSPENDED;
1177
1178 return HAL_OK;
1179
1180 }
1181
1182
1183 /**
1184 * @brief CRYP processing suspension and peripheral internal parameters storage.
1185 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1186 * the configuration information for CRYP module
1187 * @note peripheral internal parameters are stored to be readily available when
1188 * suspended processing is resumed later on.
1189 * @retval HAL status
1190 */
HAL_CRYP_Suspend(CRYP_HandleTypeDef * hcryp)1191 HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
1192 {
1193 HAL_CRYP_STATETypeDef state;
1194 uint32_t tmp_SAES_CR_DMAIN_bit;
1195
1196 /* Request suspension */
1197 /* Check whether the processing is in DMA mode or not */
1198 tmp_SAES_CR_DMAIN_bit = (((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_DMAINEN);
1199 if ((((((CRYP_TypeDef *)(hcryp->Instance))->DMACR & CRYP_DMACR_DIEN) == CRYP_DMACR_DIEN) \
1200 && (IS_CRYP_INSTANCE(hcryp->Instance))) || \
1201 ((tmp_SAES_CR_DMAIN_bit == SAES_CR_DMAINEN) && (IS_SAES_INSTANCE(hcryp->Instance))))
1202 {
1203 if (HAL_CRYP_DMAProcessSuspend(hcryp) != HAL_OK)
1204 {
1205 return HAL_ERROR;
1206 }
1207 hcryp->SuspendedProcessing = DMA_SUSPENDED;
1208 }
1209 else
1210 {
1211 HAL_CRYP_ProcessSuspend(hcryp);
1212 hcryp->SuspendedProcessing = IT_SUSPENDED;
1213 }
1214
1215 do
1216 {
1217 state = HAL_CRYP_GetState(hcryp);
1218 } while ((state != HAL_CRYP_STATE_SUSPENDED) && (state != HAL_CRYP_STATE_READY));
1219
1220 /* Make sure there is no unwanted suspension */
1221 hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
1222
1223 if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY)
1224 {
1225 /* Processing was already over or was about to end. No suspension done */
1226 return HAL_ERROR;
1227 }
1228 else
1229 {
1230 if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
1231 (hcryp->Init.Algorithm == CRYP_AES_CTR) || \
1232 (hcryp->Init.Algorithm == CRYP_AES_GCM) || \
1233 (hcryp->Init.Algorithm == CRYP_AES_CCM))
1234 {
1235 /* Save Initialisation Vector registers */
1236 CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
1237 }
1238
1239 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1240 if (IS_CRYP_INSTANCE(hcryp->Instance))
1241 {
1242 /* Save Control register */
1243 hcryp->CR_saved = ((CRYP_TypeDef *)(hcryp->Instance))->CR;
1244
1245 /* Save context swap registers */
1246 if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
1247 {
1248 CRYP_Read_ContextSwapRegisters(hcryp, hcryp->SUSPxR_saved, hcryp->Init.Algorithm);
1249 }
1250 }
1251 #endif /* USE_HAL_CRYP_ONLY */
1252 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1253 if (IS_SAES_INSTANCE(hcryp->Instance))
1254 {
1255 /* Disable AES */
1256 __HAL_CRYP_DISABLE(hcryp);
1257
1258 /* Clear keys */
1259 ((SAES_TypeDef *)(hcryp->Instance))->KEYR7 = 0x0U;
1260 ((SAES_TypeDef *)(hcryp->Instance))->KEYR6 = 0x0U;
1261 ((SAES_TypeDef *)(hcryp->Instance))->KEYR5 = 0x0U;
1262 ((SAES_TypeDef *)(hcryp->Instance))->KEYR4 = 0x0U;
1263 ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = 0x0U;
1264 ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = 0x0U;
1265 ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = 0x0U;
1266 ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = 0x0U;
1267
1268 /* Save Control register */
1269 hcryp->CR_saved = ((SAES_TypeDef *)(hcryp->Instance))->CR;
1270 }
1271 #endif /* USE_HAL_SAES_ONLY */
1272
1273 /* Save low-priority block CRYP handle parameters */
1274 hcryp->Init_saved = hcryp->Init;
1275 hcryp->pCrypInBuffPtr_saved = hcryp->pCrypInBuffPtr;
1276 hcryp->pCrypOutBuffPtr_saved = hcryp->pCrypOutBuffPtr;
1277 hcryp->CrypInCount_saved = hcryp->CrypInCount;
1278 hcryp->CrypOutCount_saved = hcryp->CrypOutCount;
1279 hcryp->Phase_saved = hcryp->Phase;
1280 hcryp->State_saved = hcryp->State;
1281 hcryp->Size_saved = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? \
1282 (hcryp->Size / 4U) : hcryp->Size);
1283 hcryp->SizesSum_saved = hcryp->SizesSum;
1284 hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount;
1285 hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
1286 }
1287 return HAL_OK;
1288 }
1289
1290
1291 /**
1292 * @brief CRYP processing resumption.
1293 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1294 * the configuration information for CRYP module
1295 * @note Processing restarts at the exact point where it was suspended, based
1296 * on the parameters saved at suspension time.
1297 * @retval HAL status
1298 */
HAL_CRYP_Resume(CRYP_HandleTypeDef * hcryp)1299 HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
1300 {
1301 /* Check the CRYP handle allocation */
1302 if (hcryp == NULL)
1303 {
1304 return HAL_ERROR;
1305 }
1306
1307 if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED)
1308 {
1309 /* CRYP was not suspended */
1310 return HAL_ERROR;
1311 }
1312 else
1313 {
1314 /* Restore low-priority block CRYP handle parameters */
1315 hcryp->Init = hcryp->Init_saved;
1316 hcryp->State = hcryp->State_saved;
1317 hcryp->Phase = hcryp->Phase_saved;
1318 hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved;
1319
1320 /* Restore low-priority block CRYP handle parameters */
1321 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1322 {
1323 hcryp->Init.pInitVect = hcryp->IV_saved;
1324 }
1325 /* Set State to reset to trigger a HAL_CRYP_MspInit() call in HAL_CRYP_Init() */
1326 __HAL_CRYP_RESET_HANDLE_STATE(hcryp);
1327 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1328 if (IS_CRYP_INSTANCE(hcryp->Instance))
1329 {
1330 ((CRYP_TypeDef *)(hcryp->Instance))->CR |= CRYP_CR_IPRST;
1331 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= (~CRYP_CR_IPRST);
1332 }
1333 #endif /* USE_HAL_CRYP_ONLY */
1334 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1335 if (IS_SAES_INSTANCE(hcryp->Instance))
1336 {
1337 ((SAES_TypeDef *)(hcryp->Instance))->CR |= SAES_CR_IPRST;
1338 ((SAES_TypeDef *)(hcryp->Instance))->CR &= (~SAES_CR_IPRST);
1339 }
1340 #endif /* USE_HAL_SAES_ONLY */
1341
1342 /* Peripheral must be disabled */
1343 __HAL_CRYP_DISABLE(hcryp);
1344
1345 if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || \
1346 (hcryp->Init.Algorithm == CRYP_AES_CBC) || \
1347 (hcryp->Init.Algorithm == CRYP_AES_CTR))
1348 {
1349 (void) HAL_CRYP_Init(hcryp);
1350 }
1351 else
1352 {
1353 /* The following lines are applicable to CRYP peripheral only */
1354
1355 /* Configure again the cryptographic processor with the initial setting in CRYP_CR */
1356 ((CRYP_TypeDef *)(hcryp->Instance))->CR = hcryp->CR_saved;
1357
1358 /* Configure again the key registers */
1359 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1360
1361 /* Restore context swap registers */
1362 CRYP_Write_ContextSwapRegisters(hcryp, hcryp->SUSPxR_saved, hcryp->Init.Algorithm);
1363
1364 /* Restore IV registers */
1365 CRYP_Write_IVRegisters(hcryp, hcryp->IV_saved);
1366
1367 /* At the same time, set handle state back to READY to be able to resume the AES calculations
1368 without the processing APIs returning HAL_BUSY when called. */
1369 hcryp->State = HAL_CRYP_STATE_READY;
1370 }
1371
1372 if (hcryp->SuspendedProcessing == DMA_SUSPENDED)
1373 {
1374 if (((IS_CRYP_INSTANCE(hcryp->Instance)) && \
1375 (READ_BIT(hcryp->CR_saved, CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)) || \
1376 ((IS_SAES_INSTANCE(hcryp->Instance)) && \
1377 (READ_BIT(hcryp->CR_saved, SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)))
1378 {
1379 if (HAL_CRYP_Encrypt_DMA(hcryp, hcryp->pCrypInBuffPtr_saved, (uint16_t) hcryp->CrypInCount_saved,
1380 hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
1381 {
1382 return HAL_ERROR;
1383 }
1384 }
1385 else
1386 {
1387 if (HAL_CRYP_Decrypt_DMA(hcryp, hcryp->pCrypInBuffPtr_saved, (uint16_t) hcryp->CrypInCount_saved,
1388 hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
1389 {
1390 return HAL_ERROR;
1391 }
1392 }
1393 }
1394 else
1395 {
1396 /* Resume low-priority block processing under IT */
1397 hcryp->ResumingFlag = 1U;
1398
1399 if (((IS_CRYP_INSTANCE(hcryp->Instance)) &&
1400 (READ_BIT(hcryp->CR_saved, CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)) || \
1401 ((IS_SAES_INSTANCE(hcryp->Instance)) && \
1402 (READ_BIT(hcryp->CR_saved, SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)))
1403 {
1404 if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved,
1405 hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
1406 {
1407 return HAL_ERROR;
1408 }
1409 }
1410 else
1411 {
1412 if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved,
1413 hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
1414 {
1415 return HAL_ERROR;
1416 }
1417 }
1418 }
1419 }
1420 return HAL_OK;
1421 }
1422 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
1423
1424 /**
1425 * @}
1426 */
1427
1428 /** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
1429 * @brief CRYP processing functions.
1430 *
1431 @verbatim
1432 ==============================================================================
1433 ##### Encrypt Decrypt functions #####
1434 ==============================================================================
1435 [..] This section provides API allowing to Encrypt/Decrypt Data following
1436 Standard AES algorithm configured by the user:
1437
1438 (+) Standard AES supported by CRYP1 IP, list of Algorithm supported:
1439 (++) Electronic Code Book(ECB)
1440 (++) Cipher Block Chaining (CBC)
1441 (++) Counter mode (CTR)
1442 (++) Cipher Block Chaining (CBC)
1443 (++) Counter mode (CTR)
1444 (++) Galois/counter mode (GCM)
1445 (++) Counter with Cipher Block Chaining-Message(CCM)
1446 [..] Three processing functions are available:
1447 (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
1448 (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
1449 (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
1450
1451 @endverbatim
1452 * @{
1453 */
1454
1455
1456 /**
1457 * @brief Encryption mode.
1458 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1459 * the configuration information for CRYP module
1460 * @param Input: Pointer to the input buffer (plaintext)
1461 * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit.
1462 * @param Output: Pointer to the output buffer(ciphertext)
1463 * @param Timeout: Specify Timeout value
1464 * @retval HAL status
1465 */
HAL_CRYP_Encrypt(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output,uint32_t Timeout)1466 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
1467 uint32_t Timeout)
1468 {
1469 uint32_t algo = 0U;
1470 HAL_StatusTypeDef status;
1471
1472 if (hcryp->State == HAL_CRYP_STATE_READY)
1473 {
1474 /* Change state Busy */
1475 hcryp->State = HAL_CRYP_STATE_BUSY;
1476
1477 /* Process locked */
1478 __HAL_LOCK(hcryp);
1479
1480 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1481 hcryp->CrypInCount = 0U;
1482 hcryp->CrypOutCount = 0U;
1483 hcryp->pCrypInBuffPtr = Input;
1484 hcryp->pCrypOutBuffPtr = Output;
1485
1486 /* Calculate Size parameter in Byte*/
1487 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1488 {
1489 hcryp->Size = Size * 4U;
1490 }
1491 else
1492 {
1493 hcryp->Size = Size;
1494 }
1495
1496 /* Set Encryption operating mode*/
1497 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1498 if (IS_CRYP_INSTANCE(hcryp->Instance))
1499 {
1500 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1501
1502 /* algo get algorithm selected */
1503 algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
1504 }
1505 #endif /* USE_HAL_CRYP_ONLY */
1506 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1507 if (IS_SAES_INSTANCE(hcryp->Instance))
1508 {
1509 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_ENCRYPT);
1510
1511 /* algo get algorithm selected */
1512 algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
1513 ALGOMODE_SAES_TO_CHMOD_CRYP);
1514 }
1515 #endif /* USE_HAL_SAES_ONLY */
1516
1517 switch (algo)
1518 {
1519 case CRYP_AES_ECB:
1520 case CRYP_AES_CBC:
1521 case CRYP_AES_CTR:
1522
1523 /* AES encryption */
1524 status = CRYP_AES_Encrypt(hcryp, Timeout);
1525 break;
1526
1527 case CRYP_AES_GCM:
1528
1529 /* AES GCM encryption */
1530 status = CRYP_AESGCM_Process(hcryp, Timeout);
1531 break;
1532
1533 case CRYP_AES_CCM:
1534
1535 /* AES CCM encryption */
1536 status = CRYP_AESCCM_Process(hcryp, Timeout);
1537 break;
1538
1539 default:
1540 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1541 status = HAL_ERROR;
1542 break;
1543 }
1544
1545 if (status == HAL_OK)
1546 {
1547 /* Change the CRYP peripheral state */
1548 hcryp->State = HAL_CRYP_STATE_READY;
1549
1550 /* Process unlocked */
1551 __HAL_UNLOCK(hcryp);
1552 }
1553 }
1554 else
1555 {
1556 /* Process unlocked */
1557 __HAL_UNLOCK(hcryp);
1558
1559 /* Busy error code field */
1560 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1561 status = HAL_ERROR;
1562 }
1563
1564 /* Return function status */
1565 return status ;
1566 }
1567
1568 /**
1569 * @brief Decryption mode.
1570 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1571 * the configuration information for CRYP module
1572 * @param Input: Pointer to the input buffer (ciphertext )
1573 * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
1574 * @param Output: Pointer to the output buffer(plaintext)
1575 * @param Timeout: Specify Timeout value
1576 * @retval HAL status
1577 */
HAL_CRYP_Decrypt(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output,uint32_t Timeout)1578 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
1579 uint32_t Timeout)
1580 {
1581 HAL_StatusTypeDef status;
1582 uint32_t algo = 0U;
1583
1584 if (hcryp->State == HAL_CRYP_STATE_READY)
1585 {
1586 /* Change state Busy */
1587 hcryp->State = HAL_CRYP_STATE_BUSY;
1588
1589 /* Process locked */
1590 __HAL_LOCK(hcryp);
1591
1592 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1593 hcryp->CrypInCount = 0U;
1594 hcryp->CrypOutCount = 0U;
1595 hcryp->pCrypInBuffPtr = Input;
1596 hcryp->pCrypOutBuffPtr = Output;
1597
1598 /* Calculate Size parameter in Byte*/
1599 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1600 {
1601 hcryp->Size = Size * 4U;
1602 }
1603 else
1604 {
1605 hcryp->Size = Size;
1606 }
1607
1608 /* Set Decryption operating mode*/
1609 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1610 if (IS_CRYP_INSTANCE(hcryp->Instance))
1611 {
1612 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1613
1614 /* algo get algorithm selected */
1615 algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
1616 }
1617 #endif /* USE_HAL_CRYP_ONLY */
1618 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1619 if (IS_SAES_INSTANCE(hcryp->Instance))
1620 {
1621 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
1622
1623 /* algo get algorithm selected */
1624 algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
1625 ALGOMODE_SAES_TO_CHMOD_CRYP);
1626 }
1627 #endif /* USE_HAL_SAES_ONLY */
1628
1629 switch (algo)
1630 {
1631 case CRYP_AES_ECB:
1632 case CRYP_AES_CBC:
1633 case CRYP_AES_CTR:
1634
1635 /* AES decryption */
1636 status = CRYP_AES_Decrypt(hcryp, Timeout);
1637 break;
1638
1639 case CRYP_AES_GCM:
1640
1641 /* AES GCM decryption */
1642 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1643 break;
1644
1645 case CRYP_AES_CCM:
1646
1647 /* AES CCM decryption */
1648 status = CRYP_AESCCM_Process(hcryp, Timeout);
1649 break;
1650
1651 default:
1652 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1653 status = HAL_ERROR;
1654 break;
1655 }
1656
1657 if (status == HAL_OK)
1658 {
1659 /* Change the CRYP peripheral state */
1660 hcryp->State = HAL_CRYP_STATE_READY;
1661
1662 /* Process unlocked */
1663 __HAL_UNLOCK(hcryp);
1664 }
1665 }
1666 else
1667 {
1668 /* Process unlocked */
1669 __HAL_UNLOCK(hcryp);
1670
1671 /* Busy error code field */
1672 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1673 status = HAL_ERROR;
1674 }
1675
1676 /* Return function status */
1677 return status;
1678 }
1679
1680 /**
1681 * @brief Encryption in interrupt mode.
1682 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1683 * the configuration information for CRYP module
1684 * @param Input: Pointer to the input buffer (plaintext)
1685 * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
1686 * @param Output: Pointer to the output buffer(ciphertext)
1687 * @retval HAL status
1688 */
HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1689 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1690 {
1691 uint32_t algo = 0U;
1692 HAL_StatusTypeDef status;
1693
1694 if (hcryp->State == HAL_CRYP_STATE_READY)
1695 {
1696 /* Change state Busy */
1697 hcryp->State = HAL_CRYP_STATE_BUSY;
1698
1699 /* Process locked */
1700 __HAL_LOCK(hcryp);
1701
1702 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1703 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
1704 if (hcryp->ResumingFlag == 1U)
1705 {
1706 hcryp->ResumingFlag = 0U;
1707 hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
1708 hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
1709 }
1710 else
1711 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
1712 {
1713 hcryp->CrypInCount = 0U;
1714 hcryp->CrypOutCount = 0U;
1715 }
1716
1717 hcryp->pCrypInBuffPtr = Input;
1718 hcryp->pCrypOutBuffPtr = Output;
1719
1720 /* Calculate Size parameter in Byte*/
1721 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1722 {
1723 hcryp->Size = Size * 4U;
1724 }
1725 else
1726 {
1727 hcryp->Size = Size;
1728 }
1729
1730 /* Set encryption operating mode*/
1731 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1732 if (IS_CRYP_INSTANCE(hcryp->Instance))
1733 {
1734 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1735
1736 /* algo get algorithm selected */
1737 algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
1738 }
1739 #endif /* USE_HAL_CRYP_ONLY */
1740 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1741 if (IS_SAES_INSTANCE(hcryp->Instance))
1742 {
1743 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_ENCRYPT);
1744
1745 /* algo get algorithm selected */
1746 algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
1747 ALGOMODE_SAES_TO_CHMOD_CRYP);
1748 }
1749 #endif /* USE_HAL_SAES_ONLY */
1750
1751 switch (algo)
1752 {
1753 case CRYP_AES_ECB:
1754 case CRYP_AES_CBC:
1755 case CRYP_AES_CTR:
1756
1757 status = CRYP_AES_Encrypt_IT(hcryp);
1758 break;
1759
1760 case CRYP_AES_GCM:
1761
1762 status = CRYP_AESGCM_Process_IT(hcryp) ;
1763 break;
1764
1765 case CRYP_AES_CCM:
1766
1767 status = CRYP_AESCCM_Process_IT(hcryp);
1768 break;
1769
1770 default:
1771 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1772 status = HAL_ERROR;
1773 break;
1774 }
1775 }
1776 else
1777 {
1778 /* Busy error code field */
1779 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1780 status = HAL_ERROR;
1781 }
1782
1783 /* Return function status */
1784 return status ;
1785 }
1786
1787 /**
1788 * @brief Decryption in interrupt mode.
1789 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1790 * the configuration information for CRYP module
1791 * @param Input: Pointer to the input buffer (ciphertext )
1792 * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
1793 * @param Output: Pointer to the output buffer(plaintext)
1794 * @retval HAL status
1795 */
HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1796 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1797 {
1798 uint32_t algo = 0U;
1799 HAL_StatusTypeDef status;
1800
1801 if (hcryp->State == HAL_CRYP_STATE_READY)
1802 {
1803 /* Change state Busy */
1804 hcryp->State = HAL_CRYP_STATE_BUSY;
1805
1806 /* Process locked */
1807 __HAL_LOCK(hcryp);
1808
1809 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1810 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
1811 if (hcryp->ResumingFlag == 1U)
1812 {
1813 hcryp->ResumingFlag = 0U;
1814 hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
1815 hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
1816 }
1817 else
1818 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
1819 {
1820 hcryp->CrypInCount = 0U;
1821 hcryp->CrypOutCount = 0U;
1822 }
1823 hcryp->pCrypInBuffPtr = Input;
1824 hcryp->pCrypOutBuffPtr = Output;
1825
1826 /* Calculate Size parameter in Byte*/
1827 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1828 {
1829 hcryp->Size = Size * 4U;
1830 }
1831 else
1832 {
1833 hcryp->Size = Size;
1834 }
1835
1836 /* Set decryption operating mode*/
1837 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1838 if (IS_CRYP_INSTANCE(hcryp->Instance))
1839 {
1840 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1841
1842 /* algo get algorithm selected */
1843 algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
1844 }
1845 #endif /* USE_HAL_CRYP_ONLY */
1846 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1847 if (IS_SAES_INSTANCE(hcryp->Instance))
1848 {
1849 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
1850
1851 /* algo get algorithm selected */
1852 algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
1853 ALGOMODE_SAES_TO_CHMOD_CRYP);
1854 }
1855 #endif /* USE_HAL_SAES_ONLY */
1856
1857 switch (algo)
1858 {
1859 case CRYP_AES_ECB:
1860 case CRYP_AES_CBC:
1861 case CRYP_AES_CTR:
1862
1863 /* AES decryption */
1864 status = CRYP_AES_Decrypt_IT(hcryp);
1865 break;
1866
1867 case CRYP_AES_GCM:
1868
1869 /* AES GCM decryption */
1870 status = CRYP_AESGCM_Process_IT(hcryp) ;
1871 break;
1872
1873 case CRYP_AES_CCM:
1874
1875 /* AES CCMdecryption */
1876 status = CRYP_AESCCM_Process_IT(hcryp);
1877 break;
1878
1879 default:
1880 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1881 status = HAL_ERROR;
1882 break;
1883 }
1884 }
1885 else
1886 {
1887 /* Busy error code field */
1888 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1889 status = HAL_ERROR;
1890 }
1891
1892 /* Return function status */
1893 return status;
1894 }
1895
1896 /**
1897 * @brief Encryption in DMA mode.
1898 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1899 * the configuration information for CRYP module
1900 * @param Input: Pointer to the input buffer (plaintext)
1901 * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
1902 * @param Output: Pointer to the output buffer(ciphertext)
1903 * @retval HAL status
1904 */
HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1905 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1906 {
1907 HAL_StatusTypeDef status = HAL_OK;
1908 uint32_t algo = 0U;
1909 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
1910 uint32_t tickstart;
1911
1912 if (hcryp->State == HAL_CRYP_STATE_READY)
1913 {
1914 /* Change state Busy */
1915 hcryp->State = HAL_CRYP_STATE_BUSY;
1916
1917 /* Process locked */
1918 __HAL_LOCK(hcryp);
1919
1920 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1921 hcryp->CrypInCount = 0U;
1922 hcryp->CrypOutCount = 0U;
1923 hcryp->pCrypInBuffPtr = Input;
1924 hcryp->pCrypOutBuffPtr = Output;
1925
1926 /* Calculate Size parameter in Byte*/
1927 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1928 {
1929 hcryp->Size = Size * 4U;
1930 }
1931 else
1932 {
1933 hcryp->Size = Size;
1934 }
1935
1936 /* Set Encryption operating mode*/
1937 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1938 if (IS_CRYP_INSTANCE(hcryp->Instance))
1939 {
1940 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1941
1942 /* algo get algorithm selected */
1943 algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
1944 }
1945 #endif /* USE_HAL_CRYP_ONLY */
1946 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1947 if (IS_SAES_INSTANCE(hcryp->Instance))
1948 {
1949 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_ENCRYPT);
1950
1951 /* algo get algorithm selected */
1952 algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
1953 ALGOMODE_SAES_TO_CHMOD_CRYP);
1954 }
1955 #endif /* USE_HAL_SAES_ONLY */
1956
1957 switch (algo)
1958 {
1959 case CRYP_AES_ECB:
1960 case CRYP_AES_CBC:
1961 case CRYP_AES_CTR:
1962
1963 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1964 {
1965 if (hcryp->KeyIVConfig == 1U)
1966 {
1967 /* If the Key and IV configuration has to be done only once
1968 and if it has already been done, skip it */
1969 DoKeyIVConfig = 0U;
1970 }
1971 else
1972 {
1973 /* If the Key and IV configuration has to be done only once
1974 and if it has not been done already, do it and set KeyIVConfig
1975 to keep track it won't have to be done again next time */
1976 hcryp->KeyIVConfig = 1U;
1977 }
1978 }
1979
1980 if (DoKeyIVConfig == 1U)
1981 {
1982 /* Set the Key */
1983 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
1984 {
1985 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1986 }
1987
1988 /* Get tick */
1989 tickstart = HAL_GetTick();
1990
1991 while (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEYVALID) == 0x0U)
1992 {
1993 /* Check for the Timeout */
1994 if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT)
1995 {
1996 /* Disable the CRYP peripheral clock */
1997 __HAL_CRYP_DISABLE(hcryp);
1998
1999 /* Change state */
2000 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2001 hcryp->State = HAL_CRYP_STATE_READY;
2002
2003 /* Process unlocked */
2004 __HAL_UNLOCK(hcryp);
2005 return HAL_ERROR;
2006 }
2007 }
2008
2009 /* Set the Initialization Vector*/
2010 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2011 {
2012 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2013 if (IS_CRYP_INSTANCE(hcryp->Instance))
2014 {
2015 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2016 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2017 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2018 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2019 }
2020 #endif /* USE_HAL_CRYP_ONLY */
2021 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2022 if (IS_SAES_INSTANCE(hcryp->Instance))
2023 {
2024 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2025 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2026 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2027 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2028 }
2029 #endif /* USE_HAL_SAES_ONLY */
2030 }
2031
2032 } /* if (DoKeyIVConfig == 1U) */
2033
2034 /* Set the phase */
2035 hcryp->Phase = CRYP_PHASE_PROCESS;
2036
2037 /* Start DMA process transfer for AES */
2038 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size, (uint32_t)(hcryp->pCrypOutBuffPtr));
2039 break;
2040
2041 case CRYP_AES_GCM:
2042
2043 /* AES GCM encryption */
2044 status = CRYP_AESGCM_Process_DMA(hcryp);
2045 break;
2046
2047 case CRYP_AES_CCM:
2048
2049 /* AES CCM encryption */
2050 status = CRYP_AESCCM_Process_DMA(hcryp);
2051 break;
2052
2053 default:
2054 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
2055 status = HAL_ERROR;
2056 break;
2057 }
2058 }
2059 else
2060 {
2061 /* Busy error code field */
2062 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
2063 status = HAL_ERROR;
2064 }
2065
2066 /* Return function status */
2067 return status;
2068 }
2069
2070 /**
2071 * @brief Decryption in DMA mode.
2072 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2073 * the configuration information for CRYP module
2074 * @param Input: Pointer to the input buffer (ciphertext )
2075 * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
2076 * @param Output: Pointer to the output buffer(plaintext)
2077 * @retval HAL status
2078 */
HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)2079 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
2080 {
2081 uint32_t algo = 0U;
2082 HAL_StatusTypeDef status;
2083
2084 if (hcryp->State == HAL_CRYP_STATE_READY)
2085 {
2086 /* Change state Busy */
2087 hcryp->State = HAL_CRYP_STATE_BUSY;
2088
2089 /* Process locked */
2090 __HAL_LOCK(hcryp);
2091
2092 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
2093 hcryp->CrypInCount = 0U;
2094 hcryp->CrypOutCount = 0U;
2095 hcryp->pCrypInBuffPtr = Input;
2096 hcryp->pCrypOutBuffPtr = Output;
2097
2098 /* Calculate Size parameter in Byte*/
2099 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
2100 {
2101 hcryp->Size = Size * 4U;
2102 }
2103 else
2104 {
2105 hcryp->Size = Size;
2106 }
2107
2108 /* Set decryption operating mode*/
2109 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2110 if (IS_CRYP_INSTANCE(hcryp->Instance))
2111 {
2112 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
2113
2114 /* algo get algorithm selected */
2115 algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
2116 }
2117 #endif /* USE_HAL_CRYP_ONLY */
2118 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2119 if (IS_SAES_INSTANCE(hcryp->Instance))
2120 {
2121 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
2122
2123 /* algo get algorithm selected */
2124 algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
2125 ALGOMODE_SAES_TO_CHMOD_CRYP);
2126 }
2127 #endif /* USE_HAL_SAES_ONLY */
2128
2129 switch (algo)
2130 {
2131 case CRYP_AES_ECB:
2132 case CRYP_AES_CBC:
2133 case CRYP_AES_CTR:
2134
2135 /* AES decryption */
2136 status = CRYP_AES_Decrypt_DMA(hcryp);
2137 break;
2138
2139 case CRYP_AES_GCM:
2140
2141 /* AES GCM decryption */
2142 status = CRYP_AESGCM_Process_DMA(hcryp);
2143
2144 break;
2145
2146 case CRYP_AES_CCM:
2147
2148 /* AES CCM decryption */
2149 status = CRYP_AESCCM_Process_DMA(hcryp);
2150 break;
2151
2152 default:
2153 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
2154 status = HAL_ERROR;
2155 break;
2156 }
2157 }
2158 else
2159 {
2160 /* Busy error code field */
2161 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
2162 status = HAL_ERROR;
2163 }
2164
2165 /* Return function status */
2166 return status;
2167 }
2168
2169 /**
2170 * @}
2171 */
2172
2173 /** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
2174 * @brief CRYP IRQ handler.
2175 *
2176 @verbatim
2177 ==============================================================================
2178 ##### CRYP IRQ handler management #####
2179 ==============================================================================
2180 [..] This section provides CRYP IRQ handler and callback functions.
2181 (+) HAL_CRYP_IRQHandler CRYP interrupt request
2182 (+) HAL_CRYP_InCpltCallback input data transfer complete callback
2183 (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
2184 (+) HAL_CRYP_ErrorCallback CRYP error callback
2185 (+) HAL_CRYP_GetState return the CRYP state
2186 (+) HAL_CRYP_GetError return the CRYP error code
2187 @endverbatim
2188 * @{
2189 */
2190
2191 /**
2192 * @brief This function handles cryptographic interrupt request.
2193 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2194 * the configuration information for CRYP module
2195 * @retval None
2196 */
HAL_CRYP_IRQHandler(CRYP_HandleTypeDef * hcryp)2197 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
2198 {
2199 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2200 if (IS_CRYP_INSTANCE(hcryp->Instance))
2201 {
2202 uint32_t itstatus = ((CRYP_TypeDef *)(hcryp->Instance))->MISR;
2203
2204 if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U)
2205 {
2206 if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC)
2207 || (hcryp->Init.Algorithm == CRYP_AES_CTR))
2208 {
2209 CRYP_AES_IT(hcryp); /*AES*/
2210 }
2211
2212 else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
2213 {
2214 /* if header phase */
2215 if ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
2216 {
2217 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2218 }
2219 else /* if payload phase */
2220 {
2221 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2222 }
2223 }
2224 else
2225 {
2226 /* Nothing to do */
2227 }
2228 }
2229 }
2230 #endif /* USE_HAL_CRYP_ONLY */
2231 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2232 if (IS_SAES_INSTANCE(hcryp->Instance))
2233 {
2234 /* Check if Read or write error occurred */
2235 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RWEIE) != RESET)
2236 {
2237 /* If write Error occurred */
2238 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_WRERR) != RESET)
2239 {
2240 hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
2241 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
2242 }
2243 /* If read Error occurred */
2244 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RDERR) != RESET)
2245 {
2246 hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
2247 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
2248 }
2249 /*Call error callback*/
2250 HAL_CRYP_ErrorCallback(hcryp);
2251 }
2252 /* Check if Key error occurred */
2253 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_KEIE) != RESET)
2254 {
2255 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEIF) != RESET)
2256 {
2257 hcryp->ErrorCode |= HAL_CRYP_ERROR_KEY;
2258 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_KEIF);
2259 /*Call error callback*/
2260 HAL_CRYP_ErrorCallback(hcryp);
2261 }
2262 }
2263 /* Check if RNG error occurred */
2264 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RNGEIE) != RESET)
2265 {
2266 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RNGEIF) != RESET)
2267 {
2268 hcryp->ErrorCode |= HAL_CRYP_ERROR_RNG;
2269 /*Call error callback*/
2270 HAL_CRYP_ErrorCallback(hcryp);
2271 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RNGEIF);
2272 }
2273 }
2274 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET)
2275 {
2276 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
2277 {
2278 /* Clear computation complete flag */
2279 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
2280
2281 if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
2282 {
2283 /* if header phase */
2284 if ((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_PHASE_HEADER) == SAES_PHASE_HEADER)
2285 {
2286 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2287 }
2288 else /* if payload phase */
2289 {
2290 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2291 }
2292 }
2293 else /* AES Algorithm ECB,CBC or CTR*/
2294 {
2295 CRYP_AES_IT(hcryp);
2296 }
2297 }
2298 }
2299 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
2300 #endif /* USE_HAL_SAES_ONLY */
2301 }
2302
2303 /**
2304 * @brief Return the CRYP error code.
2305 * @param hcryp : pointer to a CRYP_HandleTypeDef structure that contains
2306 * the configuration information for the CRYP IP
2307 * @retval CRYP error code
2308 */
HAL_CRYP_GetError(const CRYP_HandleTypeDef * hcryp)2309 uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp)
2310 {
2311 return hcryp->ErrorCode;
2312 }
2313
2314 /**
2315 * @brief Returns the CRYP state.
2316 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2317 * the configuration information for CRYP module.
2318 * @retval HAL state
2319 */
HAL_CRYP_GetState(const CRYP_HandleTypeDef * hcryp)2320 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp)
2321 {
2322 return hcryp->State;
2323 }
2324
2325 /**
2326 * @brief Input FIFO transfer completed callback.
2327 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2328 * the configuration information for CRYP module.
2329 * @retval None
2330 */
HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef * hcryp)2331 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
2332 {
2333 /* Prevent unused argument(s) compilation warning */
2334 UNUSED(hcryp);
2335
2336 /* NOTE : This function Should not be modified, when the callback is needed,
2337 the HAL_CRYP_InCpltCallback could be implemented in the user file
2338 */
2339 }
2340
2341 /**
2342 * @brief Output FIFO transfer completed callback.
2343 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2344 * the configuration information for CRYP module.
2345 * @retval None
2346 */
HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef * hcryp)2347 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
2348 {
2349 /* Prevent unused argument(s) compilation warning */
2350 UNUSED(hcryp);
2351
2352 /* NOTE : This function Should not be modified, when the callback is needed,
2353 the HAL_CRYP_OutCpltCallback could be implemented in the user file
2354 */
2355 }
2356
2357 /**
2358 * @brief CRYP error callback.
2359 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2360 * the configuration information for CRYP module.
2361 * @retval None
2362 */
HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef * hcryp)2363 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
2364 {
2365 /* Prevent unused argument(s) compilation warning */
2366 UNUSED(hcryp);
2367
2368 /* NOTE : This function Should not be modified, when the callback is needed,
2369 the HAL_CRYP_ErrorCallback could be implemented in the user file
2370 */
2371 }
2372 /**
2373 * @}
2374 */
2375
2376 /* Private functions ---------------------------------------------------------*/
2377 /** @addtogroup CRYP_Private_Functions
2378 * @{
2379 */
2380
2381
2382 /**
2383 * @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
2384 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
2385 * @param Timeout: specify Timeout value
2386 * @retval HAL status
2387 */
CRYP_AES_Encrypt(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2388 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2389 {
2390 uint16_t outcount; /* Temporary CrypOutCount Value */
2391 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2392 uint32_t tickstart;
2393
2394 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2395 {
2396 if (hcryp->KeyIVConfig == 1U)
2397 {
2398 /* If the Key and IV configuration has to be done only once
2399 and if it has already been done, skip it */
2400 DoKeyIVConfig = 0U;
2401 }
2402 else
2403 {
2404 /* If the Key and IV configuration has to be done only once
2405 and if it has not been done already, do it and set KeyIVConfig
2406 to keep track it won't have to be done again next time */
2407 hcryp->KeyIVConfig = 1U;
2408 }
2409 }
2410
2411 if (DoKeyIVConfig == 1U)
2412 {
2413 /* Set the Key */
2414 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
2415 {
2416 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2417 }
2418
2419 /* Get tick */
2420 tickstart = HAL_GetTick();
2421
2422 while (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEYVALID) == 0x0U)
2423 {
2424 /* Check for the Timeout */
2425 if (Timeout != HAL_MAX_DELAY)
2426 {
2427 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
2428 {
2429 /* Disable the CRYP peripheral clock */
2430 __HAL_CRYP_DISABLE(hcryp);
2431
2432 /* Change state */
2433 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2434 hcryp->State = HAL_CRYP_STATE_READY;
2435
2436 /* Process unlocked */
2437 __HAL_UNLOCK(hcryp);
2438 return HAL_ERROR;
2439 }
2440 }
2441 }
2442
2443 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2444 if (IS_CRYP_INSTANCE(hcryp->Instance))
2445 {
2446 if (hcryp->Init.KeyMode == CRYP_KEYMODE_SHARED)
2447 {
2448 /* As KEYVALID is set, the key share target peripheral is initialized with a valid, shared key.
2449 The application can proceed with the processing of data, setting KMOD[1:0]to 00 */
2450 CLEAR_BIT(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_KMOD);
2451 }
2452 }
2453 #endif /* USE_HAL_CRYP_ONLY */
2454
2455 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2456 {
2457 /* Set the Initialization Vector*/
2458 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2459 if (IS_CRYP_INSTANCE(hcryp->Instance))
2460 {
2461 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2462 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2463 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2464 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2465 }
2466 #endif /* USE_HAL_CRYP_ONLY */
2467 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2468 if (IS_SAES_INSTANCE(hcryp->Instance))
2469 {
2470 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2471 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2472 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2473 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2474 }
2475 #endif /* USE_HAL_SAES_ONLY */
2476 }
2477 } /* if (DoKeyIVConfig == 1U) */
2478
2479 /* Set the phase */
2480 hcryp->Phase = CRYP_PHASE_PROCESS;
2481
2482 /* Enable CRYP */
2483 __HAL_CRYP_ENABLE(hcryp);
2484 /*Temporary CrypOutCount Value */
2485 outcount = hcryp->CrypOutCount;
2486
2487 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2488 {
2489 /* Write plain Ddta and get cipher data */
2490 CRYP_AES_ProcessData(hcryp, Timeout);
2491 /*Temporary CrypOutCount Value */
2492 outcount = hcryp->CrypOutCount;
2493 }
2494
2495 /* Disable CRYP */
2496 __HAL_CRYP_DISABLE(hcryp);
2497
2498 /* Change the CRYP state */
2499 hcryp->State = HAL_CRYP_STATE_READY;
2500
2501 /* Return function status */
2502 return HAL_OK;
2503 }
2504
2505 /**
2506 * @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2507 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2508 * the configuration information for CRYP module
2509 * @retval HAL status
2510 */
CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef * hcryp)2511 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
2512 {
2513 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2514 uint32_t tickstart;
2515
2516 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2517 {
2518 if (hcryp->KeyIVConfig == 1U)
2519 {
2520 /* If the Key and IV configuration has to be done only once
2521 and if it has already been done, skip it */
2522 DoKeyIVConfig = 0U;
2523 }
2524 else
2525 {
2526 /* If the Key and IV configuration has to be done only once
2527 and if it has not been done already, do it and set KeyIVConfig
2528 to keep track it won't have to be done again next time */
2529 hcryp->KeyIVConfig = 1U;
2530 }
2531 }
2532
2533 if (DoKeyIVConfig == 1U)
2534 {
2535 /* Set the Key */
2536 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
2537 {
2538 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2539 }
2540
2541 /* Get tick */
2542 tickstart = HAL_GetTick();
2543
2544 while (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEYVALID) == 0x0U)
2545 {
2546 /* Check for the Timeout */
2547 if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT)
2548 {
2549 /* Disable the CRYP peripheral clock */
2550 __HAL_CRYP_DISABLE(hcryp);
2551
2552 /* Change state */
2553 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2554 hcryp->State = HAL_CRYP_STATE_READY;
2555
2556 /* Process unlocked */
2557 __HAL_UNLOCK(hcryp);
2558 return HAL_ERROR;
2559 }
2560 }
2561
2562 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2563 if (IS_CRYP_INSTANCE(hcryp->Instance))
2564 {
2565 if (hcryp->Init.KeyMode == CRYP_KEYMODE_SHARED)
2566 {
2567 /* As KEYVALID is set, the key share target peripheral is initialized with a valid, shared key.
2568 The application can proceed with the processing of data, setting KMOD[1:0]to 00 */
2569 CLEAR_BIT(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_KMOD);
2570 }
2571 }
2572 #endif /* USE_HAL_CRYP_ONLY */
2573
2574 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2575 {
2576 /* Set the Initialization Vector*/
2577 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2578 if (IS_CRYP_INSTANCE(hcryp->Instance))
2579 {
2580 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2581 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2582 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2583 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2584 }
2585 #endif /* USE_HAL_CRYP_ONLY */
2586 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2587 if (IS_SAES_INSTANCE(hcryp->Instance))
2588 {
2589 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2590 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2591 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2592 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2593 }
2594 #endif /* USE_HAL_SAES_ONLY */
2595 }
2596 } /* if (DoKeyIVConfig == 1U) */
2597
2598 /* Set the phase */
2599 hcryp->Phase = CRYP_PHASE_PROCESS;
2600
2601 if (hcryp->Size != 0U)
2602 {
2603 /* Enable CRYP */
2604 __HAL_CRYP_ENABLE(hcryp);
2605
2606 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2607 if (IS_SAES_INSTANCE(hcryp->Instance))
2608 {
2609 /* Write the input block in the IN FIFO */
2610 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2611 hcryp->CrypInCount++;
2612 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2613 hcryp->CrypInCount++;
2614 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2615 hcryp->CrypInCount++;
2616 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2617 hcryp->CrypInCount++;
2618 }
2619 #endif /* USE_HAL_SAES_ONLY */
2620
2621 /* Enable interrupts */
2622 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2623 if (IS_CRYP_INSTANCE(hcryp->Instance))
2624 {
2625 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2626 }
2627 #endif /* USE_HAL_CRYP_ONLY */
2628 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2629 if (IS_SAES_INSTANCE(hcryp->Instance))
2630 {
2631 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE | CRYP_IT_RNGEIE);
2632 }
2633 #endif /* USE_HAL_SAES_ONLY */
2634 }
2635 else
2636 {
2637 /* Change the CRYP state */
2638 hcryp->State = HAL_CRYP_STATE_READY;
2639
2640 /* Process unlocked */
2641 __HAL_UNLOCK(hcryp);
2642 }
2643
2644 /* Return function status */
2645 return HAL_OK;
2646 }
2647
2648 /**
2649 * @brief Decryption in ECB/CBC & CTR mode with AES Standard
2650 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
2651 * @param Timeout: Specify Timeout value
2652 * @retval HAL status
2653 */
CRYP_AES_Decrypt(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2654 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2655 {
2656 uint16_t outcount; /* Temporary CrypOutCount Value */
2657 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2658
2659 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2660 {
2661 if (hcryp->KeyIVConfig == 1U)
2662 {
2663 /* If the Key and IV configuration has to be done only once
2664 and if it has already been done, skip it */
2665 DoKeyIVConfig = 0U;
2666 }
2667 else
2668 {
2669 /* If the Key and IV configuration has to be done only once
2670 and if it has not been done already, do it and set KeyIVConfig
2671 to keep track it won't have to be done again next time */
2672 hcryp->KeyIVConfig = 1U;
2673 }
2674 }
2675
2676 if (DoKeyIVConfig == 1U)
2677 {
2678 /* Key preparation for ECB/CBC */
2679 if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/
2680 {
2681 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2682 if (IS_CRYP_INSTANCE(hcryp->Instance))
2683 {
2684 /* change ALGOMODE to key preparation for decryption*/
2685 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, CRYP_AES_KEY);
2686
2687 /* Set the Key */
2688 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
2689 {
2690 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
2691 {
2692 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2693 }
2694 }
2695
2696 /* Enable CRYP */
2697 __HAL_CRYP_ENABLE(hcryp);
2698
2699 /* Wait for BUSY flag go to 0 */
2700 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
2701 {
2702 /* Disable the CRYP peripheral clock */
2703 __HAL_CRYP_DISABLE(hcryp);
2704
2705 /* Change state */
2706 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2707 hcryp->State = HAL_CRYP_STATE_READY;
2708
2709 /* Process unlocked */
2710 __HAL_UNLOCK(hcryp);
2711 return HAL_ERROR;
2712 }
2713 /* Turn back to ALGOMODE of the configuration */
2714 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2715 }
2716 #endif /* USE_HAL_CRYP_ONLY */
2717 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2718 if (IS_SAES_INSTANCE(hcryp->Instance))
2719 {
2720 /* When KMOD[1:0] = 01 (wrapped key) or KMOD[1:0] = 01 (shared key)
2721 and MODE[1:0] = 10 (decryption), then a read access to
2722 SAES_DOUTR register triggers a read error (RDERR). So, clear KMOD for the upcoming deciphering */
2723 if (((((SAES_TypeDef *)(hcryp->Instance))->CR) & (CRYP_KEYMODE_WRAPPED | CRYP_KEYMODE_SHARED)) != 0U)
2724 {
2725 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_NORMAL);
2726 }
2727 /* key preparation for decryption, operating mode 2*/
2728 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_KEY_DERIVATION);
2729
2730 /* we should re-write Key, in the case where we change key after first operation*/
2731 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
2732 {
2733 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
2734 {
2735 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2736 }
2737 }
2738
2739 /* Enable SAES */
2740 __HAL_CRYP_ENABLE(hcryp);
2741
2742 /* Wait for CCF flag to be raised */
2743 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
2744 {
2745 /* Disable the CRYP peripheral clock */
2746 __HAL_CRYP_DISABLE(hcryp);
2747
2748 /* Change state & update error code */
2749 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2750 hcryp->State = HAL_CRYP_STATE_READY;
2751
2752 /* Process unlocked */
2753 __HAL_UNLOCK(hcryp);
2754 return HAL_ERROR;
2755 }
2756 /* Clear CCF Flag */
2757 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
2758
2759 /* End of Key preparation for ECB/CBC */
2760 /* Return to decryption operating mode(Mode 3)*/
2761 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
2762 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
2763 #endif /* USE_HAL_SAES_ONLY */
2764 }
2765 else /*Algorithm CTR */
2766 {
2767 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2768 if (IS_CRYP_INSTANCE(hcryp->Instance))
2769 {
2770 /* Set the Key */
2771 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
2772 {
2773 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
2774 {
2775 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2776 }
2777 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
2778 {
2779 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
2780 }
2781 }
2782 }
2783 #endif /* USE_HAL_CRYP_ONLY */
2784 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2785 if (IS_SAES_INSTANCE(hcryp->Instance))
2786 {
2787 /* Set the Key */
2788 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2789 }
2790 #endif /* USE_HAL_SAES_ONLY */
2791 }
2792
2793 /* Set IV */
2794 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2795 {
2796 /* Set the Initialization Vector*/
2797 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2798 if (IS_CRYP_INSTANCE(hcryp->Instance))
2799 {
2800 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2801 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2802 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2803 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2804 }
2805 #endif /* USE_HAL_CRYP_ONLY */
2806 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2807 if (IS_SAES_INSTANCE(hcryp->Instance))
2808 {
2809 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2810 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2811 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2812 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2813 }
2814 #endif /* USE_HAL_SAES_ONLY */
2815 }
2816 } /* if (DoKeyIVConfig == 1U) */
2817
2818 /* Set the phase */
2819 hcryp->Phase = CRYP_PHASE_PROCESS;
2820
2821 /* Enable CRYP */
2822 __HAL_CRYP_ENABLE(hcryp);
2823
2824 /*Temporary CrypOutCount Value */
2825 outcount = hcryp->CrypOutCount;
2826
2827 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2828 {
2829 /* Write plain data and get cipher data */
2830 CRYP_AES_ProcessData(hcryp, Timeout);
2831 /*Temporary CrypOutCount Value */
2832 outcount = hcryp->CrypOutCount;
2833 }
2834
2835 /* Disable CRYP */
2836 __HAL_CRYP_DISABLE(hcryp);
2837
2838 /* Change the CRYP state */
2839 hcryp->State = HAL_CRYP_STATE_READY;
2840
2841 /* Return function status */
2842 return HAL_OK;
2843 }
2844 /**
2845 * @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2846 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2847 * the configuration information for CRYP module
2848 * @retval HAL status
2849 */
CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef * hcryp)2850 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
2851 {
2852 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2853 uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
2854
2855 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2856 {
2857 if (hcryp->KeyIVConfig == 1U)
2858 {
2859 /* If the Key and IV configuration has to be done only once
2860 and if it has already been done, skip it */
2861 DoKeyIVConfig = 0U;
2862 }
2863 else
2864 {
2865 /* If the Key and IV configuration has to be done only once
2866 and if it has not been done already, do it and set KeyIVConfig
2867 to keep track it won't have to be done again next time */
2868 hcryp->KeyIVConfig = 1U;
2869 }
2870 }
2871
2872 if (DoKeyIVConfig == 1U)
2873 {
2874 /* Key preparation for ECB/CBC */
2875 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2876 {
2877 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2878 if (IS_CRYP_INSTANCE(hcryp->Instance))
2879 {
2880 /* change ALGOMODE to key preparation for decryption*/
2881 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, CRYP_AES_KEY);
2882
2883 /* Set the Key */
2884 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
2885 {
2886 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
2887 {
2888 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2889 }
2890 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
2891 {
2892 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
2893 }
2894 }
2895
2896 /* Enable CRYP */
2897 __HAL_CRYP_ENABLE(hcryp);
2898
2899 /* Wait for BUSY flag go to 0 */
2900 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
2901 {
2902 /* Disable the CRYP peripheral clock */
2903 __HAL_CRYP_DISABLE(hcryp);
2904
2905 /* Change state */
2906 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2907 hcryp->State = HAL_CRYP_STATE_READY;
2908
2909 /* Process unlocked */
2910 __HAL_UNLOCK(hcryp);
2911 return HAL_ERROR;
2912 }
2913
2914 /* Turn back to ALGOMODE of the configuration */
2915 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2916 }
2917 #endif /* USE_HAL_CRYP_ONLY */
2918 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2919 if (IS_SAES_INSTANCE(hcryp->Instance))
2920 {
2921 /* When KMOD[1:0] = 01 (wrapped key) or KMOD[1:0] = 01 (shared key)
2922 and MODE[1:0] = 10 (decryption), then a read access to
2923 SAES_DOUTR register triggers a read error (RDERR). So, clear KMOD for the upcoming deciphering */
2924 if (((((SAES_TypeDef *)(hcryp->Instance))->CR) & (CRYP_KEYMODE_WRAPPED | CRYP_KEYMODE_SHARED)) != 0U)
2925 {
2926 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_NORMAL);
2927 }
2928 /* key preparation for decryption, operating mode 2*/
2929 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_KEY_DERIVATION);
2930
2931 /* we should re-write Key, in the case where we change key after first operation*/
2932 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
2933 {
2934 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
2935 {
2936 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2937 }
2938 }
2939
2940 /* Enable SAES */
2941 __HAL_CRYP_ENABLE(hcryp);
2942
2943 /* Wait for CCF flag to be raised */
2944 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
2945 {
2946 /* Disable the CRYP peripheral clock */
2947 __HAL_CRYP_DISABLE(hcryp);
2948
2949 /* Change state & update error code */
2950 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2951 hcryp->State = HAL_CRYP_STATE_READY;
2952
2953 /* Process unlocked */
2954 __HAL_UNLOCK(hcryp);
2955 return HAL_ERROR;
2956 }
2957 /* Clear CCF Flag */
2958 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
2959
2960 /* End of Key preparation for ECB/CBC */
2961 /* Return to decryption operating mode(Mode 3)*/
2962 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
2963 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
2964 #endif /* USE_HAL_SAES_ONLY */
2965 }
2966 else /*Algorithm CTR */
2967 {
2968 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2969 if (IS_CRYP_INSTANCE(hcryp->Instance))
2970 {
2971 /* Set the Key */
2972 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
2973 {
2974 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
2975 {
2976 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2977 }
2978 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
2979 {
2980 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
2981 }
2982 }
2983 }
2984 #endif /* USE_HAL_CRYP_ONLY */
2985 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2986 if (IS_SAES_INSTANCE(hcryp->Instance))
2987 {
2988 /* Set the Key */
2989 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2990 }
2991 #endif /* USE_HAL_SAES_ONLY */
2992 } /* if (hcryp->Init.Algorithm != CRYP_AES_CTR) */
2993
2994 /* Set IV */
2995 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2996 {
2997 /* Set the Initialization Vector*/
2998 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2999 if (IS_CRYP_INSTANCE(hcryp->Instance))
3000 {
3001 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3002 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
3003 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
3004 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
3005 }
3006 #endif /* USE_HAL_CRYP_ONLY */
3007 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3008 if (IS_SAES_INSTANCE(hcryp->Instance))
3009 {
3010 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3011 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
3012 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
3013 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
3014 }
3015 #endif /* USE_HAL_SAES_ONLY */
3016 }
3017 } /* if (DoKeyIVConfig == 1U) */
3018
3019 /* Set the phase */
3020 hcryp->Phase = CRYP_PHASE_PROCESS;
3021 if (hcryp->Size != 0U)
3022 {
3023 /* Enable CRYP */
3024 __HAL_CRYP_ENABLE(hcryp);
3025
3026 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3027 if (IS_SAES_INSTANCE(hcryp->Instance))
3028 {
3029 /* Write the input block in the IN FIFO */
3030 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3031 hcryp->CrypInCount++;
3032 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3033 hcryp->CrypInCount++;
3034 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3035 hcryp->CrypInCount++;
3036 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3037 hcryp->CrypInCount++;
3038 }
3039 #endif /* USE_HAL_SAES_ONLY */
3040
3041 /* Enable interrupts */
3042 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3043 if (IS_CRYP_INSTANCE(hcryp->Instance))
3044 {
3045 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
3046 }
3047 #endif /* USE_HAL_CRYP_ONLY */
3048 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3049 if (IS_SAES_INSTANCE(hcryp->Instance))
3050 {
3051 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE | CRYP_IT_RNGEIE);
3052 }
3053 #endif /* USE_HAL_SAES_ONLY */
3054 }
3055 else
3056 {
3057 /* Process locked */
3058 __HAL_UNLOCK(hcryp);
3059
3060 /* Change the CRYP state */
3061 hcryp->State = HAL_CRYP_STATE_READY;
3062 }
3063 /* Return function status */
3064 return HAL_OK;
3065 }
3066
3067 /**
3068 * @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
3069 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3070 * the configuration information for CRYP module
3071 * @retval HAL status
3072 */
CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef * hcryp)3073 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
3074 {
3075 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3076 uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
3077
3078 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3079 {
3080 if (hcryp->KeyIVConfig == 1U)
3081 {
3082 /* If the Key and IV configuration has to be done only once
3083 and if it has already been done, skip it */
3084 DoKeyIVConfig = 0U;
3085 }
3086 else
3087 {
3088 /* If the Key and IV configuration has to be done only once
3089 and if it has not been done already, do it and set KeyIVConfig
3090 to keep track it won't have to be done again next time */
3091 hcryp->KeyIVConfig = 1U;
3092 }
3093 }
3094
3095 if (DoKeyIVConfig == 1U)
3096 {
3097 if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/
3098 {
3099 /* Key preparation for ECB/CBC */
3100 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3101 if (IS_CRYP_INSTANCE(hcryp->Instance))
3102 {
3103 /* change ALGOMODE to key preparation for decryption*/
3104 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, CRYP_AES_KEY);
3105
3106 /* Set the Key */
3107 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
3108 {
3109 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
3110 {
3111 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3112 }
3113 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
3114 {
3115 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
3116 }
3117 }
3118
3119 /* Enable CRYP */
3120 __HAL_CRYP_ENABLE(hcryp);
3121
3122 /* Wait for BUSY flag go to 0 */
3123 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
3124 {
3125 /* Disable the CRYP peripheral clock */
3126 __HAL_CRYP_DISABLE(hcryp);
3127
3128 /* Change state */
3129 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3130 hcryp->State = HAL_CRYP_STATE_READY;
3131
3132 /* Process unlocked */
3133 __HAL_UNLOCK(hcryp);
3134 return HAL_ERROR;
3135 }
3136 /* Turn back to ALGOMODE of the configuration */
3137 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
3138 }
3139 #endif /* USE_HAL_CRYP_ONLY */
3140 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3141 if (IS_SAES_INSTANCE(hcryp->Instance))
3142 {
3143 /* When KMOD[1:0] = 01 (wrapped key) or KMOD[1:0] = 01 (shared key)
3144 and MODE[1:0] = 10 (decryption), then a read access to
3145 SAES_DOUTR register triggers a read error (RDERR). So, clear KMOD for the upcoming deciphering */
3146 if (((((SAES_TypeDef *)(hcryp->Instance))->CR) & (CRYP_KEYMODE_WRAPPED | CRYP_KEYMODE_SHARED)) != 0U)
3147 {
3148 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_NORMAL);
3149 }
3150 /* key preparation for decryption, operating mode 2*/
3151 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_KEY_DERIVATION);
3152
3153 /* we should re-write Key, in the case where we change key after first operation*/
3154 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
3155 {
3156 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
3157 {
3158 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3159 }
3160 }
3161
3162 /* Enable SAES */
3163 __HAL_CRYP_ENABLE(hcryp);
3164
3165 /* Wait for CCF flag to be raised */
3166 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3167 {
3168 /* Disable the CRYP peripheral clock */
3169 __HAL_CRYP_DISABLE(hcryp);
3170
3171 /* Change state & update error code */
3172 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3173 hcryp->State = HAL_CRYP_STATE_READY;
3174
3175 /* Process unlocked */
3176 __HAL_UNLOCK(hcryp);
3177 return HAL_ERROR;
3178 }
3179 /* Clear CCF Flag */
3180 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
3181
3182 /* End of Key preparation for ECB/CBC */
3183 /* Return to decryption operating mode(Mode 3) */
3184 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
3185
3186 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
3187 #endif /* USE_HAL_SAES_ONLY */
3188 }
3189 else /*Algorithm CTR */
3190 {
3191 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3192 if (IS_CRYP_INSTANCE(hcryp->Instance))
3193 {
3194 /* Set the Key */
3195 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
3196 {
3197 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
3198 {
3199 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3200 }
3201 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
3202 {
3203 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
3204 }
3205 }
3206 }
3207 #endif /* USE_HAL_CRYP_ONLY */
3208 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3209 if (IS_SAES_INSTANCE(hcryp->Instance))
3210 {
3211 /* Set the Key */
3212 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3213 }
3214 #endif /* USE_HAL_SAES_ONLY */
3215 }
3216
3217 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
3218 {
3219 /* Set the Initialization Vector*/
3220 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3221 if (IS_CRYP_INSTANCE(hcryp->Instance))
3222 {
3223 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3224 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
3225 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
3226 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
3227 }
3228 #endif /* USE_HAL_CRYP_ONLY */
3229 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3230 if (IS_SAES_INSTANCE(hcryp->Instance))
3231 {
3232 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3233 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
3234 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
3235 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
3236 }
3237 #endif /* IS_SAES_INSTANCE */
3238 }
3239 } /* if (DoKeyIVConfig == 1U) */
3240
3241 /* Set the phase */
3242 hcryp->Phase = CRYP_PHASE_PROCESS;
3243
3244 if (hcryp->Size != 0U)
3245 {
3246 /* Start DMA process transfer for AES */
3247 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size, (uint32_t)(hcryp->pCrypOutBuffPtr));
3248 }
3249 else
3250 {
3251 /* Process unlocked */
3252 __HAL_UNLOCK(hcryp);
3253
3254 /* Change the CRYP state */
3255 hcryp->State = HAL_CRYP_STATE_READY;
3256 }
3257
3258 /* Return function status */
3259 return HAL_OK;
3260 }
3261
3262 /**
3263 * @brief DMA CRYP input data process complete callback.
3264 * @param hdma: DMA handle
3265 * @retval None
3266 */
CRYP_DMAInCplt(DMA_HandleTypeDef * hdma)3267 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
3268 {
3269 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3270
3271 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3272 if (IS_CRYP_INSTANCE(hcryp->Instance))
3273 {
3274 /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
3275 in the DMACR register */
3276 ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
3277 }
3278 #endif /* USE_HAL_CRYP_ONLY */
3279 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3280 if (IS_SAES_INSTANCE(hcryp->Instance))
3281 {
3282 /* Disable the DMA transfer for input FIFO request by resetting the DMAINEN bit
3283 in the CR register */
3284 ((SAES_TypeDef *)(hcryp->Instance))->CR &= (uint32_t)(~SAES_CR_DMAINEN);
3285 }
3286 #endif /* USE_HAL_SAES_ONLY */
3287
3288 /* Call input data transfer complete callback */
3289 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3290 /*Call registered Input complete callback*/
3291 hcryp->InCpltCallback(hcryp);
3292 #else
3293 /*Call legacy Input complete callback*/
3294 HAL_CRYP_InCpltCallback(hcryp);
3295 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3296 }
3297
3298
3299 /**
3300 * @brief DMA CRYP output data process complete callback.
3301 * @param hdma: DMA handle
3302 * @retval None
3303 */
CRYP_DMAOutCplt(DMA_HandleTypeDef * hdma)3304 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
3305 {
3306 uint32_t count;
3307 uint32_t npblb;
3308 uint32_t lastwordsize;
3309 uint32_t temp; /* Temporary CrypOutBuff */
3310 uint32_t mode;
3311
3312 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3313
3314
3315 /* Disable the DMA transfer for output FIFO */
3316 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3317 if (IS_CRYP_INSTANCE(hcryp->Instance))
3318 {
3319 ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
3320 }
3321 #endif /* USE_HAL_CRYP_ONLY */
3322 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3323 if (IS_SAES_INSTANCE(hcryp->Instance))
3324 {
3325 ((SAES_TypeDef *)(hcryp->Instance))->CR &= (uint32_t)(~SAES_CR_DMAOUTEN);
3326
3327 /* Disable the DMA transfer for output FIFO request by resetting
3328 the DOEN bit in the DMACR register */
3329 CLEAR_BIT(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_DMAOUTEN);
3330 }
3331 #endif /* USE_HAL_SAES_ONLY */
3332
3333 /* Last block transfer in case of GCM or CCM with Size not %16 */
3334 /* Applicable to CRYP peripheral only */
3335 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3336 if (IS_CRYP_INSTANCE(hcryp->Instance))
3337 {
3338 if (((hcryp->Size) % 16U) != 0U)
3339 {
3340 /* set CrypInCount and CrypOutCount to exact number of word already computed via DMA */
3341 hcryp->CrypInCount = (hcryp->Size / 16U) * 4U;
3342 hcryp->CrypOutCount = hcryp->CrypInCount;
3343
3344 /* Compute the number of padding bytes in last block of payload */
3345 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
3346
3347 /* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */
3348 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
3349 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
3350 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
3351 {
3352 /* Disable the CRYP */
3353 __HAL_CRYP_DISABLE(hcryp);
3354
3355 /* Specify the number of non-valid bytes using NPBLB register*/
3356 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
3357
3358 /* Enable CRYP to start the final phase */
3359 __HAL_CRYP_ENABLE(hcryp);
3360 }
3361
3362 /* Number of valid words (lastwordsize) in last block */
3363 if ((npblb % 4U) == 0U)
3364 {
3365 lastwordsize = (16U - npblb) / 4U;
3366 }
3367 else
3368 {
3369 lastwordsize = ((16U - npblb) / 4U) + 1U;
3370 }
3371 /* Write the last input block in the IN FIFO */
3372 for (count = 0U; count < lastwordsize; count ++)
3373 {
3374 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3375 hcryp->CrypInCount++;
3376 }
3377 /* Pad the data with zeros to have a complete block */
3378 while (count < 4U)
3379 {
3380 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
3381 count++;
3382 }
3383 /* Wait for OFNE flag to be raised */
3384 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
3385 do
3386 {
3387 count-- ;
3388 if (count == 0U)
3389 {
3390 /* Disable the CRYP peripheral clock */
3391 __HAL_CRYP_DISABLE(hcryp);
3392
3393 /* Change state */
3394 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3395 hcryp->State = HAL_CRYP_STATE_READY;
3396
3397 /* Process unlocked */
3398 __HAL_UNLOCK(hcryp);
3399 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3400 /*Call registered error callback*/
3401 hcryp->ErrorCallback(hcryp);
3402 #else
3403 /*Call legacy error callback*/
3404 HAL_CRYP_ErrorCallback(hcryp);
3405 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3406 }
3407 } while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_OFNE));
3408
3409 /*Read the output block from the output FIFO */
3410 for (count = 0U; count < 4U; count++)
3411 {
3412 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
3413 temporary buffer */
3414 temp = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
3415
3416 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
3417 hcryp->CrypOutCount++;
3418 }
3419 } /*End of last block transfer in case of GCM or CCM */
3420 }
3421 #endif /* USE_HAL_CRYP_ONLY */
3422 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3423 if (IS_SAES_INSTANCE(hcryp->Instance))
3424 {
3425 temp = 0;
3426 /* Last block transfer in case of GCM or CCM with Size not %16*/
3427 if (((hcryp->Size) % 16U) != 0U)
3428 {
3429 /* set CrypInCount and CrypOutCount to exact number of words already computed via DMA */
3430 hcryp->CrypInCount = (hcryp->Size / 16U) * 4U;
3431 hcryp->CrypOutCount = hcryp->CrypInCount;
3432
3433 /* Compute the number of padding bytes in last block of payload */
3434 npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
3435
3436 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
3437 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
3438 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
3439 {
3440 /* Specify the number of non-valid bytes using NPBLB register*/
3441 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
3442 }
3443
3444 /* Number of valid words (lastwordsize) in last block */
3445 if ((npblb % 4U) == 0U)
3446 {
3447 lastwordsize = (16U - npblb) / 4U;
3448 }
3449 else
3450 {
3451 lastwordsize = ((16U - npblb) / 4U) + 1U;
3452 }
3453
3454 /* Last block optionally pad the data with zeros*/
3455 for (count = 0U; count < lastwordsize; count++)
3456 {
3457 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3458 hcryp->CrypInCount++;
3459 }
3460 while (count < 4U)
3461 {
3462 /* Pad the data with zeros to have a complete block */
3463 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
3464 count++;
3465 }
3466
3467 /* Clear CCF flag */
3468 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
3469
3470 /*Read the output block from the output FIFO */
3471 for (count = 0U; count < 4U; count++)
3472 {
3473 /* Read the output block from the output FIFO and put them in temporary buffer
3474 then get CrypOutBuff from temporary buffer */
3475 temp = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
3476 }
3477
3478 count = 0U;
3479 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U))
3480 {
3481 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
3482 hcryp->CrypOutCount++;
3483 count++;
3484 }
3485 }
3486 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
3487 #endif /* USE_HAL_SAES_ONLY */
3488
3489 if (((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
3490 && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
3491 {
3492 /* Disable CRYP (not allowed in GCM) */
3493 __HAL_CRYP_DISABLE(hcryp);
3494 }
3495
3496 /* Change the CRYP state to ready */
3497 hcryp->State = HAL_CRYP_STATE_READY;
3498
3499 /* Process unlocked */
3500 __HAL_UNLOCK(hcryp);
3501
3502 /* Call output data transfer complete callback */
3503 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3504 /*Call registered Output complete callback*/
3505 hcryp->OutCpltCallback(hcryp);
3506 #else
3507 /*Call legacy Output complete callback*/
3508 HAL_CRYP_OutCpltCallback(hcryp);
3509 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3510 }
3511
3512 /**
3513 * @brief DMA CRYP communication error callback.
3514 * @param hdma: DMA handle
3515 * @retval None
3516 */
CRYP_DMAError(DMA_HandleTypeDef * hdma)3517 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
3518 {
3519 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3520
3521 /* Change the CRYP peripheral state */
3522 hcryp->State = HAL_CRYP_STATE_READY;
3523
3524 /* DMA error code field */
3525 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3526
3527 /* Call error callback */
3528 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3529 /*Call registered error callback*/
3530 hcryp->ErrorCallback(hcryp);
3531 #else
3532 /*Call legacy error callback*/
3533 HAL_CRYP_ErrorCallback(hcryp);
3534 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3535 }
3536
3537 /**
3538 * @brief Set the DMA configuration and start the DMA transfer
3539 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3540 * the configuration information for CRYP module
3541 * @param inputaddr: address of the input buffer
3542 * @param Size: size of the input buffer, must be a multiple of 16.
3543 * @param outputaddr: address of the output buffer
3544 * @retval None
3545 */
CRYP_SetDMAConfig(CRYP_HandleTypeDef * hcryp,uint32_t inputaddr,uint16_t Size,uint32_t outputaddr)3546 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
3547 {
3548 HAL_StatusTypeDef status;
3549 uint32_t peripheral_in_address = 0U;
3550 uint32_t peripheral_out_address = 0U;
3551
3552 /* Set the CRYP DMA transfer complete callback */
3553 hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
3554
3555 /* Set the DMA input error callback */
3556 hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
3557
3558 /* Set the CRYP DMA transfer complete callback */
3559 hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
3560
3561 /* Set the DMA output error callback */
3562 hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
3563
3564 /* Enable CRYP */
3565 __HAL_CRYP_ENABLE(hcryp);
3566
3567 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3568 if (IS_CRYP_INSTANCE(hcryp->Instance))
3569 {
3570 peripheral_in_address = (uint32_t) &((CRYP_TypeDef *)(hcryp->Instance))->DIN;
3571 peripheral_out_address = (uint32_t) &((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
3572 }
3573 #endif /* USE_HAL_CRYP_ONLY */
3574 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3575 if (IS_SAES_INSTANCE(hcryp->Instance))
3576 {
3577 peripheral_in_address = (uint32_t) &((SAES_TypeDef *)(hcryp->Instance))->DINR;
3578 peripheral_out_address = (uint32_t) &((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
3579 }
3580 #endif /* USE_HAL_SAES_ONLY */
3581
3582 /* Enable the DMA input channel */
3583 if ((hcryp->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3584 {
3585 if ((hcryp->hdmain->LinkedListQueue != NULL) && (hcryp->hdmain->LinkedListQueue->Head != NULL))
3586 {
3587 /* Enable the DMA channel */
3588 hcryp->hdmain->LinkedListQueue->Head->\
3589 LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size; /* Set DMA data size */
3590 hcryp->hdmain->LinkedListQueue->Head->\
3591 LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = inputaddr; /* Set DMA source address */
3592 hcryp->hdmain->LinkedListQueue->Head->\
3593 LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = peripheral_in_address; /* Set DMA destination address */
3594
3595 status = HAL_DMAEx_List_Start_IT(hcryp->hdmain);
3596 }
3597 else
3598 {
3599 /* Return error status */
3600 status = HAL_ERROR;
3601 }
3602 }
3603 else
3604 {
3605 status = HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, peripheral_in_address, Size);
3606 }
3607
3608 if (status != HAL_OK)
3609 {
3610 /* DMA error code field */
3611 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3612
3613 /* Call error callback */
3614 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3615 /*Call registered error callback*/
3616 hcryp->ErrorCallback(hcryp);
3617 #else
3618 /*Call legacy error callback*/
3619 HAL_CRYP_ErrorCallback(hcryp);
3620 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3621 }
3622
3623 /* Enable the DMA output channel */
3624 if ((hcryp->hdmaout->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3625 {
3626 if ((hcryp->hdmaout->LinkedListQueue != NULL) && (hcryp->hdmaout->LinkedListQueue->Head != NULL))
3627 {
3628 /* Enable the DMA channel */
3629 hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = \
3630 Size; /* Set DMA data size */
3631 hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
3632 peripheral_out_address; /* Set DMA source address */
3633 hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = \
3634 outputaddr; /* Set DMA destination address */
3635
3636 status = HAL_DMAEx_List_Start_IT(hcryp->hdmaout);
3637 }
3638 else
3639 {
3640 /* Return error status */
3641 status = HAL_ERROR;
3642 }
3643 }
3644 else
3645 {
3646 status = HAL_DMA_Start_IT(hcryp->hdmaout, peripheral_out_address, outputaddr, Size);
3647 }
3648
3649 if (status != HAL_OK)
3650 {
3651 /* DMA error code field */
3652 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3653
3654 /* Call error callback */
3655 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3656 /*Call registered error callback*/
3657 hcryp->ErrorCallback(hcryp);
3658 #else
3659 /*Call legacy error callback*/
3660 HAL_CRYP_ErrorCallback(hcryp);
3661 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3662 }
3663
3664 /* Enable In/Out DMA request */
3665 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3666 if (IS_CRYP_INSTANCE(hcryp->Instance))
3667 {
3668 ((CRYP_TypeDef *)(hcryp->Instance))->DMACR = (CRYP_DMACR_DOEN | CRYP_DMACR_DIEN);
3669 }
3670 #endif /* USE_HAL_CRYP_ONLY */
3671 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3672 if (IS_SAES_INSTANCE(hcryp->Instance))
3673 {
3674 ((SAES_TypeDef *)(hcryp->Instance))->CR |= (SAES_CR_DMAINEN | SAES_CR_DMAOUTEN);
3675 }
3676 #endif /* USE_HAL_SAES_ONLY */
3677 }
3678
3679 /**
3680 * @brief Process Data: Write Input data in polling mode and used in AES functions.
3681 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3682 * the configuration information for CRYP module
3683 * @param Timeout: Specify Timeout value
3684 * @retval None
3685 */
CRYP_AES_ProcessData(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)3686 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3687 {
3688
3689 uint32_t temp[4]; /* Temporary CrypOutBuff */
3690 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3691 uint16_t incount; /* Temporary CrypInCount Value */
3692 uint16_t outcount; /* Temporary CrypOutCount Value */
3693 #endif /* USE_HAL_CRYP_ONLY */
3694 uint32_t i;
3695
3696 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3697 if (IS_CRYP_INSTANCE(hcryp->Instance))
3698 {
3699 /*Temporary CrypOutCount Value */
3700 incount = hcryp->CrypInCount;
3701
3702 if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < ((hcryp->Size) / 4U)))
3703 {
3704 /* Write the input block in the IN FIFO */
3705 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3706 hcryp->CrypInCount++;
3707 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3708 hcryp->CrypInCount++;
3709 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3710 hcryp->CrypInCount++;
3711 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3712 hcryp->CrypInCount++;
3713 }
3714
3715 /* Wait for OFNE flag to be raised */
3716 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
3717 {
3718 /* Disable the CRYP peripheral clock */
3719 __HAL_CRYP_DISABLE(hcryp);
3720
3721 /* Change state & update error code */
3722 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3723 hcryp->State = HAL_CRYP_STATE_READY;
3724
3725 /* Process unlocked */
3726 __HAL_UNLOCK(hcryp);
3727 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3728 /*Call registered error callback*/
3729 hcryp->ErrorCallback(hcryp);
3730 #else
3731 /*Call legacy error callback*/
3732 HAL_CRYP_ErrorCallback(hcryp);
3733 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3734 }
3735 /*Temporary CrypOutCount Value */
3736 outcount = hcryp->CrypOutCount;
3737
3738 if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < ((hcryp->Size) / 4U)))
3739 {
3740 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from
3741 temporary buffer */
3742 for (i = 0U; i < 4U; i++)
3743 {
3744 temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
3745 }
3746 i = 0U;
3747 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3748 {
3749 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3750 hcryp->CrypOutCount++;
3751 i++;
3752 }
3753 }
3754 }
3755 #endif /* USE_HAL_CRYP_ONLY */
3756 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3757 if (IS_SAES_INSTANCE(hcryp->Instance))
3758 {
3759 /* Write the input block in the IN FIFO */
3760 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3761 hcryp->CrypInCount++;
3762 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3763 hcryp->CrypInCount++;
3764 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3765 hcryp->CrypInCount++;
3766 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3767 hcryp->CrypInCount++;
3768
3769 /* Wait for CCF flag to be raised */
3770 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3771 {
3772 /* Disable the CRYP peripheral clock */
3773 __HAL_CRYP_DISABLE(hcryp);
3774
3775 /* Change state */
3776 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3777 hcryp->State = HAL_CRYP_STATE_READY;
3778
3779 /* Process unlocked */
3780 __HAL_UNLOCK(hcryp);
3781 /*Call registered error callback*/
3782 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3783 hcryp->ErrorCallback(hcryp);
3784 #else
3785 /*Call legacy error callback*/
3786 HAL_CRYP_ErrorCallback(hcryp);
3787 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3788 }
3789
3790 /* Clear CCF Flag */
3791 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
3792
3793 /* Read the output block from the output FIFO and put them in temporary buffer then
3794 get CrypOutBuff from temporary buffer*/
3795 for (i = 0U; i < 4U; i++)
3796 {
3797 temp[i] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
3798 }
3799 i = 0U;
3800 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3801 {
3802 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3803 hcryp->CrypOutCount++;
3804 i++;
3805 }
3806 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
3807 #endif /* USE_HAL_SAES_ONLY */
3808 }
3809
3810 /**
3811 * @brief Handle CRYP block input/output data handling under interruption.
3812 * @note The function is called under interruption only, once
3813 * interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
3814 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3815 * the configuration information for CRYP module.
3816 * @retval HAL status
3817 */
CRYP_AES_IT(CRYP_HandleTypeDef * hcryp)3818 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
3819 {
3820 uint32_t temp[4]; /* Temporary CrypOutBuff */
3821 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3822 uint16_t incount; /* Temporary CrypInCount Value */
3823 uint16_t outcount; /* Temporary CrypOutCount Value */
3824 #endif /* USE_HAL_CRYP_ONLY */
3825 uint32_t i;
3826
3827 if (hcryp->State == HAL_CRYP_STATE_BUSY)
3828 {
3829 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3830 if (IS_CRYP_INSTANCE(hcryp->Instance))
3831 {
3832 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
3833 /* If suspension flag has been raised, suspend processing
3834 only if not already at the end of the payload */
3835 if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
3836 {
3837 /* Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the
3838 CRYP_SR) and the BUSY bit is cleared */
3839 while (((((CRYP_TypeDef *)(hcryp->Instance))->SR) & (CRYP_SR_IFEM | CRYP_SR_OFNE | \
3840 CRYP_SR_BUSY)) != CRYP_SR_IFEM)
3841 {
3842 /* Nothing to do */
3843 }
3844
3845 /* Disable interrupts */
3846 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
3847
3848 /* Disable CRYP */
3849 __HAL_CRYP_DISABLE(hcryp);
3850
3851 /* reset SuspendRequest */
3852 hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
3853
3854 /* Change the CRYP state */
3855 hcryp->State = HAL_CRYP_STATE_SUSPENDED;
3856
3857 /* Process Unlocked */
3858 __HAL_UNLOCK(hcryp);
3859 }
3860 else
3861 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
3862 {
3863 /*Temporary CrypOutCount Value */
3864 incount = hcryp->CrypInCount;
3865
3866 if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3867 {
3868 /* Write the input block in the IN FIFO */
3869 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3870 hcryp->CrypInCount++;
3871 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3872 hcryp->CrypInCount++;
3873 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3874 hcryp->CrypInCount++;
3875 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3876 hcryp->CrypInCount++;
3877 if (hcryp->CrypInCount == (hcryp->Size / 4U))
3878 {
3879 /* Disable interrupts */
3880 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
3881
3882 /* Call the input data transfer complete callback */
3883 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3884 /*Call registered Input complete callback*/
3885 hcryp->InCpltCallback(hcryp);
3886 #else
3887 /*Call legacy Input complete callback*/
3888 HAL_CRYP_InCpltCallback(hcryp);
3889 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3890 }
3891 }
3892
3893 /*Temporary CrypOutCount Value */
3894 outcount = hcryp->CrypOutCount;
3895
3896 if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3897 {
3898 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
3899 temporary buffer */
3900 for (i = 0U; i < 4U; i++)
3901 {
3902 temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
3903 }
3904 i = 0U;
3905 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3906 {
3907 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3908 hcryp->CrypOutCount++;
3909 i++;
3910 }
3911 if (hcryp->CrypOutCount == (hcryp->Size / 4U))
3912 {
3913 /* Disable interrupts */
3914 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
3915
3916 /* Change the CRYP state */
3917 hcryp->State = HAL_CRYP_STATE_READY;
3918
3919 /* Disable CRYP */
3920 __HAL_CRYP_DISABLE(hcryp);
3921
3922 /* Process unlocked */
3923 __HAL_UNLOCK(hcryp);
3924
3925 /* Call output transfer complete callback */
3926 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3927 /*Call registered Output complete callback*/
3928 hcryp->OutCpltCallback(hcryp);
3929 #else
3930 /*Call legacy Output complete callback*/
3931 HAL_CRYP_OutCpltCallback(hcryp);
3932 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3933 }
3934 }
3935 } /* if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) */
3936 }
3937 #endif /* USE_HAL_CRYP_ONLY */
3938 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3939 if (IS_SAES_INSTANCE(hcryp->Instance))
3940 {
3941 /* Read the output block from the output FIFO and put them in temporary buffer then
3942 get CrypOutBuff from temporary buffer*/
3943 for (i = 0U; i < 4U; i++)
3944 {
3945 temp[i] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
3946 }
3947 i = 0U;
3948 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3949 {
3950 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3951 hcryp->CrypOutCount++;
3952 i++;
3953 }
3954 if (hcryp->CrypOutCount == (hcryp->Size / 4U))
3955 {
3956 /* Disable Computation Complete flag and errors interrupts */
3957 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
3958
3959 /* Change the CRYP state */
3960 hcryp->State = HAL_CRYP_STATE_READY;
3961
3962 /* Disable CRYP */
3963 __HAL_CRYP_DISABLE(hcryp);
3964 __HAL_UNLOCK(hcryp);
3965
3966 /* Call Output transfer complete callback */
3967 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3968 /*Call registered Output complete callback*/
3969 hcryp->OutCpltCallback(hcryp);
3970 #else
3971 /*Call legacy Output complete callback*/
3972 HAL_CRYP_OutCpltCallback(hcryp);
3973 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3974 }
3975 else
3976 {
3977 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
3978 /* If suspension flag has been raised, suspend processing
3979 only if not already at the end of the payload */
3980 if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
3981 {
3982 /* Clear CCF Flag */
3983 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
3984
3985 /* reset SuspendRequest */
3986 hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
3987
3988 /* Disable Computation Complete Flag and Errors Interrupts */
3989 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
3990
3991 /* Change the CRYP state */
3992 hcryp->State = HAL_CRYP_STATE_SUSPENDED;
3993
3994 /* Mark that the payload phase is suspended */
3995 hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
3996
3997 __HAL_UNLOCK(hcryp);
3998 }
3999 else
4000 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
4001 {
4002 /* Write the input block in the IN FIFO */
4003 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4004 hcryp->CrypInCount++;
4005 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4006 hcryp->CrypInCount++;
4007 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4008 hcryp->CrypInCount++;
4009 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4010 hcryp->CrypInCount++;
4011
4012 if (hcryp->CrypInCount == (hcryp->Size / 4U))
4013 {
4014 /* Call Input transfer complete callback */
4015 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4016 /*Call registered Input complete callback*/
4017 hcryp->InCpltCallback(hcryp);
4018 #else
4019 /*Call legacy Input complete callback*/
4020 HAL_CRYP_InCpltCallback(hcryp);
4021 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4022 }
4023 }
4024 } /* if (hcryp->CrypOutCount == (hcryp->Size / 4U)) */
4025 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
4026 #endif /* USE_HAL_SAES_ONLY */
4027 }
4028 else
4029 {
4030 /* Process unlocked */
4031 __HAL_UNLOCK(hcryp);
4032 /* Busy error code field */
4033 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
4034 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4035 /*Call registered error callback*/
4036 hcryp->ErrorCallback(hcryp);
4037 #else
4038 /*Call legacy error callback*/
4039 HAL_CRYP_ErrorCallback(hcryp);
4040 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4041 }
4042 }
4043
4044 /**
4045 * @brief Writes Key in Key registers.
4046 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4047 * the configuration information for CRYP module
4048 * @param KeySize: Size of Key
4049 * @retval None
4050 */
CRYP_SetKey(CRYP_HandleTypeDef * hcryp,uint32_t KeySize)4051 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
4052 {
4053 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4054 if (IS_CRYP_INSTANCE(hcryp->Instance))
4055 {
4056 switch (KeySize)
4057 {
4058 case CRYP_KEYSIZE_256B:
4059 ((CRYP_TypeDef *)(hcryp->Instance))->K0LR = *(uint32_t *)(hcryp->Init.pKey);
4060 ((CRYP_TypeDef *)(hcryp->Instance))->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1);
4061 ((CRYP_TypeDef *)(hcryp->Instance))->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2);
4062 ((CRYP_TypeDef *)(hcryp->Instance))->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3);
4063 ((CRYP_TypeDef *)(hcryp->Instance))->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4);
4064 ((CRYP_TypeDef *)(hcryp->Instance))->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5);
4065 ((CRYP_TypeDef *)(hcryp->Instance))->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6);
4066 ((CRYP_TypeDef *)(hcryp->Instance))->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7);
4067 break;
4068
4069 case CRYP_KEYSIZE_192B:
4070 ((CRYP_TypeDef *)(hcryp->Instance))->K1LR = *(uint32_t *)(hcryp->Init.pKey);
4071 ((CRYP_TypeDef *)(hcryp->Instance))->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
4072 ((CRYP_TypeDef *)(hcryp->Instance))->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
4073 ((CRYP_TypeDef *)(hcryp->Instance))->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
4074 ((CRYP_TypeDef *)(hcryp->Instance))->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
4075 ((CRYP_TypeDef *)(hcryp->Instance))->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
4076 break;
4077
4078 case CRYP_KEYSIZE_128B:
4079 ((CRYP_TypeDef *)(hcryp->Instance))->K2LR = *(uint32_t *)(hcryp->Init.pKey);
4080 ((CRYP_TypeDef *)(hcryp->Instance))->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1);
4081 ((CRYP_TypeDef *)(hcryp->Instance))->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2);
4082 ((CRYP_TypeDef *)(hcryp->Instance))->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3);
4083 break;
4084
4085 default:
4086 break;
4087 }
4088 }
4089 #endif /* USE_HAL_CRYP_ONLY */
4090 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4091 if (IS_SAES_INSTANCE(hcryp->Instance))
4092 {
4093 if (hcryp->Init.pKey != NULL)
4094 {
4095 switch (KeySize)
4096 {
4097 case CRYP_KEYSIZE_256B:
4098 ((SAES_TypeDef *)(hcryp->Instance))->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
4099 ((SAES_TypeDef *)(hcryp->Instance))->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U);
4100 ((SAES_TypeDef *)(hcryp->Instance))->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U);
4101 ((SAES_TypeDef *)(hcryp->Instance))->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U);
4102 ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U);
4103 ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U);
4104 ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U);
4105 ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U);
4106 break;
4107 case CRYP_KEYSIZE_128B:
4108 ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
4109 ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U);
4110 ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U);
4111 ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U);
4112
4113 break;
4114 default:
4115 break;
4116 }
4117 } /* if (hcryp->Init.pKey != NULL) */
4118 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
4119 #endif /* USE_HAL_SAES_ONLY */
4120 }
4121
4122 /**
4123 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
4124 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4125 * the configuration information for CRYP module
4126 * @param Timeout: Timeout duration
4127 * @retval HAL status
4128 */
CRYP_AESGCM_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)4129 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
4130 {
4131 uint32_t tickstart;
4132 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
4133 uint32_t npblb ;
4134 uint32_t temp[4]; /* Temporary CrypOutBuff */
4135 uint32_t index ;
4136 uint32_t lastwordsize ;
4137 uint32_t outcount; /* Temporary CrypOutCount Value */
4138 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4139 uint32_t mode;
4140
4141 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4142 {
4143 if (hcryp->KeyIVConfig == 1U)
4144 {
4145 /* If the Key and IV configuration has to be done only once
4146 and if it has already been done, skip it */
4147 DoKeyIVConfig = 0U;
4148 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4149 }
4150 else
4151 {
4152 /* If the Key and IV configuration has to be done only once
4153 and if it has not been done already, do it and set KeyIVConfig
4154 to keep track it won't have to be done again next time */
4155 hcryp->KeyIVConfig = 1U;
4156 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4157 }
4158 }
4159 else
4160 {
4161 hcryp->SizesSum = hcryp->Size;
4162 }
4163
4164 if (DoKeyIVConfig == 1U)
4165 {
4166 /* Reset CrypHeaderCount */
4167 hcryp->CrypHeaderCount = 0U;
4168
4169 /****************************** Init phase **********************************/
4170 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4171 if (IS_CRYP_INSTANCE(hcryp->Instance))
4172 {
4173 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4174
4175 /* Set the Key */
4176 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
4177 {
4178 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
4179 {
4180 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4181 }
4182 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
4183 {
4184 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
4185 }
4186 }
4187
4188 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4189 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
4190 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4191 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4192 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4193
4194 /* Enable the CRYP peripheral */
4195 __HAL_CRYP_ENABLE(hcryp);
4196
4197 /* Get tick */
4198 tickstart = HAL_GetTick();
4199
4200 /*Wait for the CRYPEN bit to be cleared*/
4201 while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
4202 {
4203 /* Check for the Timeout */
4204 if (Timeout != HAL_MAX_DELAY)
4205 {
4206 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4207 {
4208 /* Disable the CRYP peripheral clock */
4209 __HAL_CRYP_DISABLE(hcryp);
4210
4211 /* Change state */
4212 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4213 hcryp->State = HAL_CRYP_STATE_READY;
4214
4215 /* Process unlocked */
4216 __HAL_UNLOCK(hcryp);
4217 return HAL_ERROR;
4218 }
4219 }
4220 }
4221 }
4222 #endif /* USE_HAL_CRYP_ONLY */
4223 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4224 if (IS_SAES_INSTANCE(hcryp->Instance))
4225 {
4226 SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
4227
4228 /* We should re-write Key, in the case where we change key after first operation */
4229 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
4230 {
4231 /* Set the Key */
4232 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4233 }
4234
4235 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4236 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
4237 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4238 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4239 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4240
4241 /* Enable the CRYP peripheral */
4242 __HAL_CRYP_ENABLE(hcryp);
4243
4244 /* just wait for hash computation */
4245 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4246 {
4247 /* Disable the CRYP peripheral clock */
4248 __HAL_CRYP_DISABLE(hcryp);
4249
4250 /* Change state */
4251 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4252 hcryp->State = HAL_CRYP_STATE_READY;
4253
4254 /* Process unlocked */
4255 __HAL_UNLOCK(hcryp);
4256 return HAL_ERROR;
4257 }
4258 /* Clear CCF flag */
4259 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
4260 }
4261 #endif /* USE_HAL_SAES_ONLY */
4262
4263 /************************ Header phase *************************************/
4264
4265 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
4266 {
4267 return HAL_ERROR;
4268 }
4269
4270 /*************************Payload phase ************************************/
4271
4272 /* Set the phase */
4273 hcryp->Phase = CRYP_PHASE_PROCESS;
4274
4275 /* Select payload phase once the header phase is performed */
4276 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4277 if (IS_CRYP_INSTANCE(hcryp->Instance))
4278 {
4279 /* Disable the CRYP peripheral */
4280 __HAL_CRYP_DISABLE(hcryp);
4281
4282 /* Select payload phase once the header phase is performed */
4283 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4284
4285 /* Set to 0 the number of non-valid bytes using NPBLB register*/
4286 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
4287
4288 /* Enable the CRYP peripheral */
4289 __HAL_CRYP_ENABLE(hcryp);
4290 }
4291 #endif /* USE_HAL_CRYP_ONLY */
4292 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4293 if (IS_SAES_INSTANCE(hcryp->Instance))
4294 {
4295 /* Select payload phase once the header phase is performed */
4296 SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
4297
4298 /* Set to 0 the number of non-valid bytes using NPBLB register*/
4299 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
4300 }
4301 #endif /* USE_HAL_SAES_ONLY */
4302
4303 } /* if (DoKeyIVConfig == 1U) */
4304
4305 if ((hcryp->Size % 16U) != 0U)
4306 {
4307 /* recalculate wordsize */
4308 wordsize = ((wordsize / 4U) * 4U) ;
4309 }
4310
4311 /* Get tick */
4312 tickstart = HAL_GetTick();
4313
4314 /*Temporary CrypOutCount Value */
4315 outcount = hcryp->CrypOutCount;
4316 /* Write input data and get output data */
4317 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4318 {
4319 /* Write plain data and get cipher data */
4320 CRYP_AES_ProcessData(hcryp, Timeout);
4321
4322 /*Temporary CrypOutCount Value */
4323 outcount = hcryp->CrypOutCount;
4324
4325 /* Check for the Timeout */
4326 if (Timeout != HAL_MAX_DELAY)
4327 {
4328 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4329 {
4330 /* Disable the CRYP peripheral clock */
4331 __HAL_CRYP_DISABLE(hcryp);
4332
4333 /* Change state */
4334 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4335 hcryp->State = HAL_CRYP_STATE_READY;
4336
4337 /* Process unlocked */
4338 __HAL_UNLOCK(hcryp);
4339 return HAL_ERROR;
4340 }
4341 }
4342 }
4343
4344 if ((hcryp->Size % 16U) != 0U)
4345 {
4346 /* Compute the number of padding bytes in last block of payload */
4347 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
4348
4349 /* Set Npblb in case of AES GCM payload encryption to get right tag */
4350 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4351 if (IS_CRYP_INSTANCE(hcryp->Instance))
4352 {
4353 mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
4354 if (mode == CRYP_OPERATINGMODE_ENCRYPT)
4355 {
4356 /* Disable the CRYP */
4357 __HAL_CRYP_DISABLE(hcryp);
4358
4359 /* Specify the number of non-valid bytes using NPBLB register */
4360 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20U);
4361
4362 /* Enable CRYP to start the final phase */
4363 __HAL_CRYP_ENABLE(hcryp);
4364 }
4365 }
4366 #endif /* USE_HAL_CRYP_ONLY */
4367 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4368 if (IS_SAES_INSTANCE(hcryp->Instance))
4369 {
4370 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
4371 if (mode == CRYP_OPERATINGMODE_ENCRYPT)
4372 {
4373 /* Specify the number of non-valid bytes using NPBLB register */
4374 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20U);
4375 }
4376 }
4377 #endif /* USE_HAL_SAES_ONLY */
4378
4379 /* Number of valid words (lastwordsize) in last block */
4380 if ((npblb % 4U) == 0U)
4381 {
4382 lastwordsize = (16U - npblb) / 4U;
4383 }
4384 else
4385 {
4386 lastwordsize = ((16U - npblb) / 4U) + 1U;
4387 }
4388 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4389 if (IS_CRYP_INSTANCE(hcryp->Instance))
4390 {
4391 /* Write the last input block in the IN FIFO */
4392 for (index = 0U; index < lastwordsize; index ++)
4393 {
4394 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4395 hcryp->CrypInCount++;
4396 }
4397
4398 /* Pad the data with zeros to have a complete block */
4399 while (index < 4U)
4400 {
4401 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
4402 index++;
4403 }
4404
4405 /* Wait for OFNE flag to be raised */
4406 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
4407 {
4408 /* Disable the CRYP peripheral clock */
4409 __HAL_CRYP_DISABLE(hcryp);
4410
4411 /* Change state */
4412 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4413 hcryp->State = HAL_CRYP_STATE_READY;
4414
4415 /* Process Unlocked */
4416 __HAL_UNLOCK(hcryp);
4417 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4418 /*Call registered error callback*/
4419 hcryp->ErrorCallback(hcryp);
4420 #else
4421 /*Call legacy error callback*/
4422 HAL_CRYP_ErrorCallback(hcryp);
4423 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4424 }
4425
4426 /*Read the output block from the output FIFO */
4427 if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U)
4428 {
4429 for (index = 0U; index < 4U; index++)
4430 {
4431 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
4432 temporary buffer */
4433 temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
4434 }
4435 }
4436 else
4437 {
4438 /* Disable the CRYP peripheral clock */
4439 __HAL_CRYP_DISABLE(hcryp);
4440
4441 /* Change state */
4442 hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
4443 hcryp->State = HAL_CRYP_STATE_READY;
4444
4445 /* Process unlocked */
4446 __HAL_UNLOCK(hcryp);
4447 return HAL_ERROR;
4448 }
4449 }
4450 #endif /* USE_HAL_CRYP_ONLY */
4451 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4452 if (IS_SAES_INSTANCE(hcryp->Instance))
4453 {
4454 /* Write the last input block in the IN FIFO */
4455 for (index = 0U; index < lastwordsize; index ++)
4456 {
4457 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4458 hcryp->CrypInCount++;
4459 }
4460 while (index < 4U)
4461 {
4462 /* pad the data with zeros to have a complete block */
4463 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U;
4464 index++;
4465 }
4466 /* Wait for CCF flag to be raised */
4467 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4468 {
4469 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4470 /*Call registered error callback*/
4471 hcryp->ErrorCallback(hcryp);
4472 #else
4473 /*Call legacy error callback*/
4474 HAL_CRYP_ErrorCallback(hcryp);
4475 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4476 }
4477
4478 /* Clear CCF Flag */
4479 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
4480
4481 /*Read the output block from the output FIFO */
4482 for (index = 0U; index < 4U; index++)
4483 {
4484 /* Read the output block from the output FIFO and put them in temporary buffer then
4485 get CrypOutBuff from temporary buffer */
4486 temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
4487 }
4488 }
4489 #endif /* USE_HAL_SAES_ONLY */
4490 for (index = 0U; index < lastwordsize; index++)
4491 {
4492 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
4493 hcryp->CrypOutCount++;
4494 }
4495 }
4496
4497 /* Return function status */
4498 return HAL_OK;
4499 }
4500
4501 /**
4502 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
4503 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4504 * the configuration information for CRYP module
4505 * @retval HAL status
4506 */
CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef * hcryp)4507 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
4508 {
4509 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4510 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4511 uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
4512 uint32_t tickstart;
4513 #endif /* USE_HAL_CRYP_ONLY */
4514 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4515 uint32_t count;
4516 uint32_t loopcounter;
4517 uint32_t lastwordsize;
4518 uint32_t headersize_in_bytes;
4519 uint32_t tmp;
4520 uint32_t npblb;
4521 const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
4522 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
4523 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
4524 }; /* 8-bit data type */
4525 #endif /* USE_HAL_SAES_ONLY */
4526
4527 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
4528 if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
4529 {
4530 CRYP_PhaseProcessingResume(hcryp);
4531 return HAL_OK;
4532 }
4533 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
4534
4535 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4536 /* Manage header size given in bytes to handle cases where
4537 header size is not a multiple of 4 bytes */
4538 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
4539 {
4540 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
4541 }
4542 else
4543 {
4544 headersize_in_bytes = hcryp->Init.HeaderSize;
4545 }
4546 #endif /* USE_HAL_SAES_ONLY */
4547
4548 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4549 {
4550 if (hcryp->KeyIVConfig == 1U)
4551 {
4552 /* If the Key and IV configuration has to be done only once
4553 and if it has already been done, skip it */
4554 DoKeyIVConfig = 0U;
4555 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4556 }
4557 else
4558 {
4559 /* If the Key and IV configuration has to be done only once
4560 and if it has not been done already, do it and set KeyIVConfig
4561 to keep track it won't have to be done again next time */
4562 hcryp->KeyIVConfig = 1U;
4563 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4564 }
4565 }
4566 else
4567 {
4568 hcryp->SizesSum = hcryp->Size;
4569 }
4570
4571 /* Configure Key, IV and process message (header and payload) */
4572 if (DoKeyIVConfig == 1U)
4573 {
4574 /* Reset CrypHeaderCount */
4575 hcryp->CrypHeaderCount = 0U;
4576
4577 /******************************* Init phase *********************************/
4578 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4579 if (IS_CRYP_INSTANCE(hcryp->Instance))
4580 {
4581 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4582
4583 /* Set the Key */
4584 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
4585 {
4586 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
4587 {
4588 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4589 }
4590 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
4591 {
4592 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
4593 }
4594 }
4595 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4596 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
4597 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4598 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4599 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4600
4601 /* Enable the CRYP peripheral */
4602 __HAL_CRYP_ENABLE(hcryp);
4603
4604 /* Get tick */
4605 tickstart = HAL_GetTick();
4606 /*Wait for the CRYPEN bit to be cleared */
4607 while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
4608 {
4609 /* Check for the Timeout */
4610 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4611 {
4612 /* Disable the CRYP peripheral clock */
4613 __HAL_CRYP_DISABLE(hcryp);
4614
4615 /* Change state */
4616 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4617 hcryp->State = HAL_CRYP_STATE_READY;
4618
4619 /* Process unlocked */
4620 __HAL_UNLOCK(hcryp);
4621 return HAL_ERROR;
4622 }
4623 }
4624 }
4625 #endif /* USE_HAL_CRYP_ONLY */
4626 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4627 if (IS_SAES_INSTANCE(hcryp->Instance))
4628 {
4629 SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
4630
4631 /* We should re-write Key, in the case where we change key after first operation */
4632 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
4633 {
4634 /* Set the Key */
4635 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4636 }
4637 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
4638 {
4639 ((SAES_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
4640 }
4641
4642 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4643 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
4644 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4645 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4646 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4647
4648 /* Enable the CRYP peripheral */
4649 __HAL_CRYP_ENABLE(hcryp);
4650
4651 /* Wait for KEYVALID flag to be set */
4652 count = CRYP_TIMEOUT_KEYPREPARATION;
4653 do
4654 {
4655 count--;
4656 if (count == 0U)
4657 {
4658 /* Disable the SAES peripheral clock */
4659 __HAL_CRYP_DISABLE(hcryp);
4660
4661 /* Change state */
4662 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4663 hcryp->State = HAL_CRYP_STATE_READY;
4664 __HAL_UNLOCK(hcryp);
4665 return HAL_ERROR;
4666 }
4667 } while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_KEYVALID));
4668
4669 /* just wait for hash computation */
4670 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4671 do
4672 {
4673 count--;
4674 if (count == 0U)
4675 {
4676 /* Disable the CRYP peripheral clock */
4677 __HAL_CRYP_DISABLE(hcryp);
4678
4679 /* Change state */
4680 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4681 hcryp->State = HAL_CRYP_STATE_READY;
4682 __HAL_UNLOCK(hcryp);
4683 return HAL_ERROR;
4684 }
4685 } while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF));
4686
4687 /* Clear CCF flag */
4688 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
4689 }
4690 #endif /* USE_HAL_SAES_ONLY */
4691
4692 /***************************** Header phase *********************************/
4693
4694 /* Select header phase */
4695 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4696 if (IS_CRYP_INSTANCE(hcryp->Instance))
4697 {
4698 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4699 }
4700 #endif /* USE_HAL_CRYP_ONLY */
4701 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4702 if (IS_SAES_INSTANCE(hcryp->Instance))
4703 {
4704 SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
4705
4706 /* Enable the CRYP peripheral */
4707 __HAL_CRYP_ENABLE(hcryp);
4708
4709 if (headersize_in_bytes == 0U) /*header phase is skipped*/
4710 {
4711 /* Set the phase */
4712 hcryp->Phase = CRYP_PHASE_PROCESS;
4713
4714 /* Select payload phase once the header phase is performed */
4715 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_GCMPH, SAES_PHASE_PAYLOAD);
4716
4717 /* Set to 0 the number of non-valid bytes using NPBLB register*/
4718 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
4719
4720 /* Write the payload Input block in the IN FIFO */
4721 if (hcryp->Size == 0U)
4722 {
4723 /* Disable interrupts */
4724 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
4725
4726 /* Change the CRYP state */
4727 hcryp->State = HAL_CRYP_STATE_READY;
4728 __HAL_UNLOCK(hcryp);
4729 }
4730 else if (hcryp->Size >= 16U)
4731 {
4732 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4733 hcryp->CrypInCount++;
4734 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4735 hcryp->CrypInCount++;
4736 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4737 hcryp->CrypInCount++;
4738 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4739 hcryp->CrypInCount++;
4740 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
4741 {
4742 /* Call Input transfer complete callback */
4743 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4744 /*Call registered Input complete callback*/
4745 hcryp->InCpltCallback(hcryp);
4746 #else
4747 /*Call legacy Input complete callback*/
4748 HAL_CRYP_InCpltCallback(hcryp);
4749 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4750 }
4751
4752 /* Enable computation complete flag and error interrupts */
4753 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
4754 }
4755 else /* Size < 16Bytes : first block is the last block*/
4756 {
4757 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4758 Workaround is implemented in polling mode, so if last block of
4759 payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
4760
4761
4762 /* Compute the number of padding bytes in last block of payload */
4763 npblb = 16U - ((uint32_t)hcryp->Size);
4764
4765 if ((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
4766 {
4767 /* Set to 0 the number of non-valid bytes using NPBLB register*/
4768 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
4769 }
4770
4771 /* Number of valid words (lastwordsize) in last block */
4772 if ((npblb % 4U) == 0U)
4773 {
4774 lastwordsize = (16U - npblb) / 4U;
4775 }
4776 else
4777 {
4778 lastwordsize = ((16U - npblb) / 4U) + 1U;
4779 }
4780
4781 /* last block optionally pad the data with zeros*/
4782 for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
4783 {
4784 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4785 hcryp->CrypInCount++;
4786 }
4787 while (loopcounter < 4U)
4788 {
4789 /* pad the data with zeros to have a complete block */
4790 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
4791 loopcounter++;
4792 }
4793 /* Call Input transfer complete callback */
4794 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4795 /*Call registered Input complete callback*/
4796 hcryp->InCpltCallback(hcryp);
4797 #else
4798 /*Call legacy Input complete callback*/
4799 HAL_CRYP_InCpltCallback(hcryp);
4800 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4801
4802 /* Enable computation complete flag and error interrupts */
4803 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
4804 }
4805 }
4806 /* Enter header data */
4807 /* Cher first whether header length is small enough to enter the full header in one shot */
4808 else if (headersize_in_bytes <= 16U)
4809 {
4810 /* Write header data, padded with zeros if need be */
4811 for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
4812 {
4813 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4814 hcryp->CrypHeaderCount++ ;
4815 }
4816 /* If the header size is a multiple of words */
4817 if ((headersize_in_bytes % 4U) == 0U)
4818 {
4819 /* Pad the data with zeros to have a complete block */
4820 while (loopcounter < 4U)
4821 {
4822 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
4823 loopcounter++;
4824 hcryp->CrypHeaderCount++;
4825 }
4826 }
4827 else
4828 {
4829 /* Enter last bytes, padded with zeros */
4830 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4831 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
4832 ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
4833 loopcounter++;
4834 hcryp->CrypHeaderCount++ ;
4835 /* Pad the data with zeros to have a complete block */
4836 while (loopcounter < 4U)
4837 {
4838 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
4839 loopcounter++;
4840 hcryp->CrypHeaderCount++;
4841 }
4842 }
4843 /* Call Input transfer complete callback */
4844 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4845 /*Call registered Input complete callback*/
4846 hcryp->InCpltCallback(hcryp);
4847 #else
4848 /*Call legacy Input complete callback*/
4849 HAL_CRYP_InCpltCallback(hcryp);
4850 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4851 }
4852 else
4853 {
4854 /* Write the first input header block in the Input FIFO,
4855 the following header data will be fed after interrupt occurrence */
4856 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4857 hcryp->CrypHeaderCount++;
4858 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4859 hcryp->CrypHeaderCount++;
4860 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4861 hcryp->CrypHeaderCount++;
4862 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4863 hcryp->CrypHeaderCount++;
4864 }
4865 }
4866 #endif /* USE_HAL_SAES_ONLY */
4867 } /* end of if (DoKeyIVConfig == 1U) */
4868 else /* Key and IV have already been configured,
4869 header has already been processed;
4870 only process here message payload */
4871 {
4872 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4873 if (IS_SAES_INSTANCE(hcryp->Instance))
4874 {
4875 /* Enable computation complete flag and error interrupts */
4876 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
4877
4878 /* Set to 0 the number of non-valid bytes using NPBLB register*/
4879 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
4880
4881 /* Write the payload Input block in the IN FIFO */
4882 if (hcryp->Size == 0U)
4883 {
4884 /* Disable interrupts */
4885 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
4886
4887 /* Change the CRYP state */
4888 hcryp->State = HAL_CRYP_STATE_READY;
4889 __HAL_UNLOCK(hcryp);
4890 }
4891 else if (hcryp->Size >= 16U)
4892 {
4893 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4894 hcryp->CrypInCount++;
4895 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4896 hcryp->CrypInCount++;
4897 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4898 hcryp->CrypInCount++;
4899 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4900 hcryp->CrypInCount++;
4901 if (hcryp->CrypInCount == (hcryp->Size / 4U))
4902 {
4903 /* Call Input transfer complete callback */
4904 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4905 /*Call registered Input complete callback*/
4906 hcryp->InCpltCallback(hcryp);
4907 #else
4908 /*Call legacy Input complete callback*/
4909 HAL_CRYP_InCpltCallback(hcryp);
4910 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4911 }
4912 }
4913 else /* Size < 16Bytes : first block is the last block*/
4914 {
4915 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4916 Workaround is implemented in polling mode, so if last block of
4917 payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
4918
4919 /* Compute the number of padding bytes in last block of payload */
4920 npblb = 16U - ((uint32_t)hcryp->Size);
4921
4922 if ((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
4923 {
4924 /* Set to 0 the number of non-valid bytes using NPBLB register*/
4925 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
4926 }
4927
4928 /* Number of valid words (lastwordsize) in last block */
4929 if ((npblb % 4U) == 0U)
4930 {
4931 lastwordsize = (16U - npblb) / 4U;
4932 }
4933 else
4934 {
4935 lastwordsize = ((16U - npblb) / 4U) + 1U;
4936 }
4937
4938 /* last block optionally pad the data with zeros*/
4939 for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
4940 {
4941 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4942 hcryp->CrypInCount++;
4943 }
4944 while (loopcounter < 4U)
4945 {
4946 /* pad the data with zeros to have a complete block */
4947 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
4948 loopcounter++;
4949 }
4950 }
4951 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
4952 #endif /* USE_HAL_SAES_ONLY */
4953 } /* if (DoKeyIVConfig != 1U) */
4954
4955 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4956 if (IS_CRYP_INSTANCE(hcryp->Instance))
4957 {
4958 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4959
4960 /* Enable interrupts */
4961 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
4962
4963 /* Enable CRYP */
4964 __HAL_CRYP_ENABLE(hcryp);
4965 }
4966 #endif /* USE_HAL_CRYP_ONLY */
4967
4968 /* Return function status */
4969 return HAL_OK;
4970 }
4971
4972 /**
4973 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
4974 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4975 * the configuration information for CRYP module
4976 * @retval HAL status
4977 */
CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef * hcryp)4978 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4979 {
4980 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4981 __IO uint32_t count = 0U;
4982 #endif /* USE_HAL_CRYP_ONLY */
4983 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
4984 uint32_t index;
4985 uint32_t npblb;
4986 uint32_t lastwordsize = 0U;
4987 uint32_t temp[4]; /* Temporary CrypOutBuff */
4988 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4989 uint32_t mode;
4990 uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
4991 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4992 uint32_t tickstart;
4993 #endif /* USE_HAL_CRYP_ONLY */
4994
4995 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4996 {
4997 if (hcryp->KeyIVConfig == 1U)
4998 {
4999 /* If the Key and IV configuration has to be done only once
5000 and if it has already been done, skip it */
5001 DoKeyIVConfig = 0U;
5002 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
5003 }
5004 else
5005 {
5006 /* If the Key and IV configuration has to be done only once
5007 and if it has not been done already, do it and set KeyIVConfig
5008 to keep track it won't have to be done again next time */
5009 hcryp->KeyIVConfig = 1U;
5010 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
5011 }
5012 }
5013 else
5014 {
5015 hcryp->SizesSum = hcryp->Size;
5016 }
5017
5018 if (DoKeyIVConfig == 1U)
5019 {
5020 /* Reset CrypHeaderCount */
5021 hcryp->CrypHeaderCount = 0U;
5022
5023 /*************************** Init phase ************************************/
5024 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5025 if (IS_CRYP_INSTANCE(hcryp->Instance))
5026 {
5027 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
5028
5029 /* Set the Key */
5030 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
5031 {
5032 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
5033 {
5034 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5035 }
5036 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
5037 {
5038 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
5039 }
5040 }
5041
5042 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
5043 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
5044 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
5045 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
5046 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
5047
5048 /* Enable the CRYP peripheral */
5049 __HAL_CRYP_ENABLE(hcryp);
5050
5051 /* Get tick */
5052 tickstart = HAL_GetTick();
5053 /*Wait for the CRYPEN bit to be cleared */
5054 while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
5055 {
5056 /* Check for the Timeout */
5057 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
5058 {
5059 /* Disable the CRYP peripheral clock */
5060 __HAL_CRYP_DISABLE(hcryp);
5061
5062 /* Change state */
5063 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5064 hcryp->State = HAL_CRYP_STATE_READY;
5065
5066 /* Process unlocked */
5067 __HAL_UNLOCK(hcryp);
5068 }
5069 }
5070 }
5071 #endif /* USE_HAL_CRYP_ONLY */
5072 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5073 if (IS_SAES_INSTANCE(hcryp->Instance))
5074 {
5075 SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
5076
5077 /* Set the Key */
5078 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5079
5080 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
5081 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
5082 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
5083 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
5084 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
5085
5086 /* Enable the CRYP peripheral */
5087 __HAL_CRYP_ENABLE(hcryp);
5088
5089 /* Wait for CCF to be raised */
5090 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5091 {
5092 /* Disable the CRYP peripheral clock */
5093 __HAL_CRYP_DISABLE(hcryp);
5094
5095 /* Change state */
5096 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5097 hcryp->State = HAL_CRYP_STATE_READY;
5098
5099 /* Process unlocked */
5100 __HAL_UNLOCK(hcryp);
5101 return HAL_ERROR;
5102 }
5103 /* Clear CCF flag */
5104 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
5105 }
5106 #endif /* USE_HAL_SAES_ONLY */
5107 /************************ Header phase *************************************/
5108
5109 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
5110 {
5111 return HAL_ERROR;
5112 }
5113
5114 /************************ Payload phase ************************************/
5115
5116 /* Set the phase */
5117 hcryp->Phase = CRYP_PHASE_PROCESS;
5118
5119 /* Select payload phase once the header phase is performed */
5120 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5121 if (IS_CRYP_INSTANCE(hcryp->Instance))
5122 {
5123 /* Disable the CRYP peripheral */
5124 __HAL_CRYP_DISABLE(hcryp);
5125
5126 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
5127
5128 /* Set to 0 the number of non-valid bytes using NPBLB register*/
5129 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
5130
5131 /* Enable the CRYP peripheral */
5132 __HAL_CRYP_ENABLE(hcryp);
5133 }
5134 #endif /* USE_HAL_CRYP_ONLY */
5135 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5136 if (IS_SAES_INSTANCE(hcryp->Instance))
5137 {
5138 SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
5139
5140 /* Set to 0 the number of non-valid bytes using NPBLB register*/
5141 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
5142 }
5143 #endif /* USE_HAL_SAES_ONLY */
5144
5145 } /* if (DoKeyIVConfig == 1U) */
5146
5147 if (hcryp->Size == 0U)
5148 {
5149 /* Process unLocked */
5150 __HAL_UNLOCK(hcryp);
5151
5152 /* Change the CRYP state and phase */
5153 hcryp->State = HAL_CRYP_STATE_READY;
5154 }
5155 else if (hcryp->Size >= 16U)
5156 {
5157 /* DMA transfer must not include the last block in case of Size is not %16 */
5158 wordsize = wordsize - (wordsize % 4U);
5159
5160 /* DMA transfer */
5161 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize * 4U,
5162 (uint32_t)(hcryp->pCrypOutBuffPtr));
5163 }
5164 else /* length of input data is < 16 */
5165 {
5166 /* Compute the number of padding bytes in last block of payload */
5167 npblb = 16U - (uint32_t)hcryp->Size;
5168
5169 /* Set Npblb in case of AES GCM payload encryption to get right tag*/
5170 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5171 if (IS_CRYP_INSTANCE(hcryp->Instance))
5172 {
5173 mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
5174
5175 if (mode == CRYP_OPERATINGMODE_ENCRYPT)
5176 {
5177 /* Specify the number of non-valid bytes using NPBLB register*/
5178 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
5179 }
5180
5181 /* Enable CRYP to start the final phase */
5182 __HAL_CRYP_ENABLE(hcryp);
5183
5184 /* Number of valid words (lastwordsize) in last block */
5185 if ((npblb % 4U) == 0U)
5186 {
5187 lastwordsize = (16U - npblb) / 4U;
5188 }
5189 else
5190 {
5191 lastwordsize = ((16U - npblb) / 4U) + 1U;
5192 }
5193
5194 /* Write the last input block in the IN FIFO */
5195 for (index = 0; index < lastwordsize; index ++)
5196 {
5197 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5198 hcryp->CrypInCount++;
5199 }
5200
5201 /* Pad the data with zeros to have a complete block */
5202 while (index < 4U)
5203 {
5204 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
5205 index++;
5206 }
5207
5208 /* Wait for OFNE flag to be raised */
5209 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5210 do
5211 {
5212 count-- ;
5213 if (count == 0U)
5214 {
5215 /* Disable the CRYP peripheral clock */
5216 __HAL_CRYP_DISABLE(hcryp);
5217
5218 /* Change state */
5219 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5220 hcryp->State = HAL_CRYP_STATE_READY;
5221
5222 /* Process unlocked */
5223 __HAL_UNLOCK(hcryp);
5224 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5225 /*Call registered error callback*/
5226 hcryp->ErrorCallback(hcryp);
5227 #else
5228 /*Call legacy error callback*/
5229 HAL_CRYP_ErrorCallback(hcryp);
5230 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5231 }
5232 } while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_OFNE));
5233
5234 /*Read the output block from the output FIFO */
5235 for (index = 0U; index < 4U; index++)
5236 {
5237 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
5238 temporary buffer */
5239 temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
5240 }
5241 }
5242 #endif /* USE_HAL_CRYP_ONLY */
5243 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5244 if (IS_SAES_INSTANCE(hcryp->Instance))
5245 {
5246
5247 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
5248 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
5249 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
5250 {
5251 /* Specify the number of non-valid bytes using NPBLB register*/
5252 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20);
5253 }
5254
5255 /* Number of valid words (lastwordsize) in last block */
5256 if ((npblb % 4U) == 0U)
5257 {
5258 lastwordsize = (16U - npblb) / 4U;
5259 }
5260 else
5261 {
5262 lastwordsize = ((16U - npblb) / 4U) + 1U;
5263 }
5264
5265 /* Write the last input block in the IN FIFO */
5266 for (index = 0; index < lastwordsize; index ++)
5267 {
5268 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5269 hcryp->CrypInCount++;
5270 }
5271
5272 /* Pad the data with zeros to have a complete block */
5273 while (index < 4U)
5274 {
5275 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U;
5276 index++;
5277 }
5278
5279 /* Wait for CCF flag to be raised */
5280 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5281 {
5282 /* Disable the CRYP peripheral clock */
5283 __HAL_CRYP_DISABLE(hcryp);
5284
5285 /* Change state */
5286 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5287 hcryp->State = HAL_CRYP_STATE_READY;
5288
5289 /* Process unlocked */
5290 __HAL_UNLOCK(hcryp);
5291 /*Call registered error callback*/
5292 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5293 hcryp->ErrorCallback(hcryp);
5294 #else
5295 /*Call legacy error callback*/
5296 HAL_CRYP_ErrorCallback(hcryp);
5297 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5298 }
5299 /* Clear the CCF flag by setting the CCF bit of the SAES_ICR register */
5300 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
5301
5302 /*Read the output block from the output FIFO */
5303 for (index = 0U; index < 4U; index++)
5304 {
5305 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
5306 temporary buffer */
5307 temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
5308 }
5309 }
5310 #endif /* USE_HAL_SAES_ONLY */
5311
5312 for (index = 0; index < lastwordsize; index++)
5313 {
5314 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
5315 hcryp->CrypOutCount++;
5316 }
5317
5318 /* Change the CRYP state to ready */
5319 hcryp->State = HAL_CRYP_STATE_READY;
5320
5321 /* Process unlocked */
5322 __HAL_UNLOCK(hcryp);
5323 }
5324
5325 /* Return function status */
5326 return HAL_OK;
5327 }
5328
5329
5330 /**
5331 * @brief AES CCM encryption/decryption processing in polling mode
5332 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5333 * the configuration information for CRYP module
5334 * @param Timeout: Timeout duration
5335 * @retval HAL status
5336 */
CRYP_AESCCM_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)5337 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
5338 {
5339 uint32_t tickstart;
5340 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
5341 uint32_t npblb ;
5342 uint32_t lastwordsize ;
5343 uint32_t temp[4] ; /* Temporary CrypOutBuff */
5344 uint32_t index ;
5345 uint32_t outcount; /* Temporary CrypOutCount Value */
5346 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
5347 uint32_t mode;
5348
5349 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
5350 {
5351 if (hcryp->KeyIVConfig == 1U)
5352 {
5353 /* If the Key and IV configuration has to be done only once
5354 and if it has already been done, skip it */
5355 DoKeyIVConfig = 0U;
5356 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
5357 }
5358 else
5359 {
5360 /* If the Key and IV configuration has to be done only once
5361 and if it has not been done already, do it and set KeyIVConfig
5362 to keep track it won't have to be done again next time */
5363 hcryp->KeyIVConfig = 1U;
5364 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
5365 }
5366 }
5367 else
5368 {
5369 hcryp->SizesSum = hcryp->Size;
5370 }
5371
5372 if (DoKeyIVConfig == 1U)
5373 {
5374 /* Reset CrypHeaderCount */
5375 hcryp->CrypHeaderCount = 0U;
5376
5377 /********************** Init phase ******************************************/
5378 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5379 if (IS_CRYP_INSTANCE(hcryp->Instance))
5380 {
5381 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
5382
5383 /* Set the Key */
5384 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
5385 {
5386 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
5387 {
5388 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5389 }
5390 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
5391 {
5392 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
5393 }
5394 }
5395 /* Set the initialization vector (IV) with CTR1 information */
5396 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
5397 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = hcryp->Init.B0[1];
5398 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = hcryp->Init.B0[2];
5399 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
5400
5401 /* Enable the CRYP peripheral */
5402 __HAL_CRYP_ENABLE(hcryp);
5403
5404 /* Set the initialization vector (IV) with B0 */
5405 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0);
5406 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
5407 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
5408 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
5409
5410 /* Get tick */
5411 tickstart = HAL_GetTick();
5412
5413 /*Wait for the CRYPEN bit to be cleared*/
5414 while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
5415 {
5416 /* Check for the Timeout */
5417 if (Timeout != HAL_MAX_DELAY)
5418 {
5419 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
5420 {
5421 /* Disable the CRYP peripheral clock */
5422 __HAL_CRYP_DISABLE(hcryp);
5423
5424 /* Change state */
5425 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5426 hcryp->State = HAL_CRYP_STATE_READY;
5427
5428 /* Process unlocked */
5429 __HAL_UNLOCK(hcryp);
5430 return HAL_ERROR;
5431 }
5432 }
5433 }
5434 }
5435 #endif /* USE_HAL_CRYP_ONLY */
5436 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5437 if (IS_SAES_INSTANCE(hcryp->Instance))
5438 {
5439 SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
5440
5441 /* We should re-write Key, in the case where we change key after first operation */
5442 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
5443 {
5444 /* Set the Key */
5445 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5446 }
5447
5448 /* Set the initialization vector (IV) with B0 */
5449 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.B0);
5450 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
5451 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
5452 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
5453
5454 /* Enable the CRYP peripheral */
5455 __HAL_CRYP_ENABLE(hcryp);
5456
5457 /* just wait for hash computation */
5458 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5459 {
5460 /* Disable the CRYP peripheral clock */
5461 __HAL_CRYP_DISABLE(hcryp);
5462
5463 /* Change state */
5464 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5465 hcryp->State = HAL_CRYP_STATE_READY;
5466
5467 /* Process unlocked */
5468 __HAL_UNLOCK(hcryp);
5469 return HAL_ERROR;
5470 }
5471 /* Clear CCF flag */
5472 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
5473 }
5474 #endif /* USE_HAL_SAES_ONLY */
5475
5476 /************************* Header phase *************************************/
5477 /* Header block(B1) : associated data length expressed in bytes concatenated
5478 with Associated Data (A)*/
5479
5480 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
5481 {
5482 return HAL_ERROR;
5483 }
5484 /********************** Payload phase ***************************************/
5485
5486 /* Set the phase */
5487 hcryp->Phase = CRYP_PHASE_PROCESS;
5488
5489 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5490 /* Select payload phase once the header phase is performed */
5491 if (IS_CRYP_INSTANCE(hcryp->Instance))
5492 {
5493 /* Disable the CRYP peripheral */
5494 __HAL_CRYP_DISABLE(hcryp);
5495
5496 /* Set to 0 the number of non-valid bytes using NPBLB register*/
5497 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
5498
5499 /* Select payload phase once the header phase is performed */
5500 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
5501
5502 /* Enable the CRYP peripheral */
5503 __HAL_CRYP_ENABLE(hcryp);
5504 }
5505 #endif /* USE_HAL_CRYP_ONLY */
5506 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5507 if (IS_SAES_INSTANCE(hcryp->Instance))
5508 {
5509 /* Set to 0 the number of non-valid bytes using NPBLB register*/
5510 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
5511
5512 /* Select payload phase once the header phase is performed */
5513 SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
5514 }
5515 #endif /* USE_HAL_SAES_ONLY */
5516
5517 } /* if (DoKeyIVConfig == 1U) */
5518
5519 if ((hcryp->Size % 16U) != 0U)
5520 {
5521 /* recalculate wordsize */
5522 wordsize = ((wordsize / 4U) * 4U) ;
5523 }
5524 /* Get tick */
5525 tickstart = HAL_GetTick();
5526
5527 /*Temporary CrypOutCount Value */
5528 outcount = hcryp->CrypOutCount;
5529 /* Write input data and get output data */
5530 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
5531 {
5532 /* Write plain data and get cipher data */
5533 CRYP_AES_ProcessData(hcryp, Timeout);
5534
5535 /*Temporary CrypOutCount Value */
5536 outcount = hcryp->CrypOutCount;
5537
5538 /* Check for the Timeout */
5539 if (Timeout != HAL_MAX_DELAY)
5540 {
5541 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
5542 {
5543 /* Disable the CRYP peripheral clock */
5544 __HAL_CRYP_DISABLE(hcryp);
5545
5546 /* Change state */
5547 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5548 hcryp->State = HAL_CRYP_STATE_READY;
5549
5550 /* Process unlocked */
5551 __HAL_UNLOCK(hcryp);
5552 return HAL_ERROR;
5553 }
5554 }
5555 }
5556
5557 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5558 if (IS_CRYP_INSTANCE(hcryp->Instance))
5559 {
5560 if ((hcryp->Size % 16U) != 0U)
5561 {
5562 /* Compute the number of padding bytes in last block of payload */
5563 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5564
5565 mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
5566 if (mode == CRYP_OPERATINGMODE_DECRYPT)
5567 {
5568 /* Disable the CRYP */
5569 __HAL_CRYP_DISABLE(hcryp);
5570
5571 /* Set Npblb in case of AES CCM payload decryption to get right tag */
5572 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
5573
5574 /* Enable CRYP to start the final phase */
5575 __HAL_CRYP_ENABLE(hcryp);
5576 }
5577
5578 /* Number of valid words (lastwordsize) in last block */
5579 if ((npblb % 4U) == 0U)
5580 {
5581 lastwordsize = (16U - npblb) / 4U;
5582 }
5583 else
5584 {
5585 lastwordsize = ((16U - npblb) / 4U) + 1U;
5586 }
5587
5588 /* Write the last input block in the IN FIFO */
5589 for (index = 0U; index < lastwordsize; index ++)
5590 {
5591 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5592 hcryp->CrypInCount++;
5593 }
5594
5595 /* Pad the data with zeros to have a complete block */
5596 while (index < 4U)
5597 {
5598 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
5599 index++;
5600 }
5601
5602 /* Wait for OFNE flag to be raised */
5603 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
5604 {
5605 /* Disable the CRYP peripheral clock */
5606 __HAL_CRYP_DISABLE(hcryp);
5607
5608 /* Change state */
5609 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5610 hcryp->State = HAL_CRYP_STATE_READY;
5611
5612 /* Process Unlocked */
5613 __HAL_UNLOCK(hcryp);
5614 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5615 /*Call registered error callback*/
5616 hcryp->ErrorCallback(hcryp);
5617 #else
5618 /*Call legacy error callback*/
5619 HAL_CRYP_ErrorCallback(hcryp);
5620 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5621 }
5622
5623 /*Read the output block from the output FIFO */
5624 if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U)
5625 {
5626 for (index = 0U; index < 4U; index++)
5627 {
5628 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
5629 temporary buffer */
5630 temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
5631 }
5632 for (index = 0; index < lastwordsize; index++)
5633 {
5634 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
5635 hcryp->CrypOutCount++;
5636 }
5637 }
5638 }
5639 }
5640 #endif /* USE_HAL_CRYP_ONLY */
5641 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5642 if (IS_SAES_INSTANCE(hcryp->Instance))
5643 {
5644
5645 if ((hcryp->Size % 16U) != 0U)
5646 {
5647 /* Compute the number of padding bytes in last block of payload */
5648 npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
5649
5650 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
5651 if (mode == CRYP_OPERATINGMODE_DECRYPT)
5652 {
5653 /* Set Npblb in case of AES CCM payload decryption to get right tag */
5654 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20);
5655 }
5656 /* Number of valid words (lastwordsize) in last block */
5657 if ((npblb % 4U) == 0U)
5658 {
5659 lastwordsize = (16U - npblb) / 4U;
5660 }
5661 else
5662 {
5663 lastwordsize = ((16U - npblb) / 4U) + 1U;
5664 }
5665
5666 /* Write the last input block in the IN FIFO */
5667 for (index = 0U; index < lastwordsize; index ++)
5668 {
5669 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5670 hcryp->CrypInCount++;
5671 }
5672
5673 /* Pad the data with zeros to have a complete block */
5674 while (index < 4U)
5675 {
5676 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U;
5677 index++;
5678 }
5679 /* just wait for hash computation */
5680 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5681 {
5682 /* Disable the CRYP peripheral clock */
5683 __HAL_CRYP_DISABLE(hcryp);
5684
5685 /* Change state */
5686 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5687 hcryp->State = HAL_CRYP_STATE_READY;
5688
5689 /* Process Unlocked */
5690 __HAL_UNLOCK(hcryp);
5691 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5692 /*Call registered error callback*/
5693 hcryp->ErrorCallback(hcryp);
5694 #else
5695 /*Call legacy error callback*/
5696 HAL_CRYP_ErrorCallback(hcryp);
5697 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5698 }
5699 /* Clear CCF flag */
5700 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
5701
5702 for (index = 0U; index < 4U; index++)
5703 {
5704 /* Read the output block from the output FIFO and put them in temporary buffer then
5705 get CrypOutBuff from temporary buffer */
5706 temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
5707 }
5708 for (index = 0U; index < lastwordsize; index++)
5709 {
5710 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
5711 hcryp->CrypOutCount++;
5712 }
5713 }
5714 }
5715 #endif /* USE_HAL_SAES_ONLY */
5716 /* Wait until the complete message has been processed */
5717 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
5718 {
5719 /* Disable the CRYP peripheral clock */
5720 __HAL_CRYP_DISABLE(hcryp);
5721
5722 /* Change state */
5723 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5724 hcryp->State = HAL_CRYP_STATE_READY;
5725
5726 /* Process unlocked & return error */
5727 __HAL_UNLOCK(hcryp);
5728 return HAL_ERROR;
5729 }
5730
5731 /* Return function status */
5732 return HAL_OK;
5733 }
5734
5735 /**
5736 * @brief AES CCM encryption/decryption process in interrupt mode
5737 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5738 * the configuration information for CRYP module
5739 * @retval HAL status
5740 */
CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef * hcryp)5741 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
5742 {
5743 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
5744 uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
5745 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5746 uint32_t tickstart;
5747 #endif /* USE_HAL_CRYP_ONLY */
5748 uint32_t loopcounter;
5749 uint32_t lastwordsize;
5750 uint32_t npblb;
5751 uint32_t mode;
5752 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5753 uint32_t headersize_in_bytes;
5754 uint32_t tmp;
5755 const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
5756 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
5757 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
5758 }; /* 8-bit data type */
5759 #endif /* USE_HAL_SAES_ONLY */
5760
5761 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
5762 if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
5763 {
5764 CRYP_PhaseProcessingResume(hcryp);
5765 return HAL_OK;
5766 }
5767 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
5768
5769 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
5770 {
5771 if (hcryp->KeyIVConfig == 1U)
5772 {
5773 /* If the Key and IV configuration has to be done only once
5774 and if it has already been done, skip it */
5775 DoKeyIVConfig = 0U;
5776 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
5777 }
5778 else
5779 {
5780 /* If the Key and IV configuration has to be done only once
5781 and if it has not been done already, do it and set KeyIVConfig
5782 to keep track it won't have to be done again next time */
5783 hcryp->KeyIVConfig = 1U;
5784 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
5785 }
5786 }
5787 else
5788 {
5789 hcryp->SizesSum = hcryp->Size;
5790 }
5791
5792 /* Configure Key, IV and process message (header and payload) */
5793 if (DoKeyIVConfig == 1U)
5794 {
5795 /* Reset CrypHeaderCount */
5796 hcryp->CrypHeaderCount = 0U;
5797
5798 /************ Init phase ************/
5799 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5800 if (IS_CRYP_INSTANCE(hcryp->Instance))
5801 {
5802 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
5803
5804 /* Set the Key */
5805 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
5806 {
5807 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
5808 {
5809 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5810 }
5811 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
5812 {
5813 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
5814 }
5815 }
5816
5817 /* Set the initialization vector (IV) with CTR1 information */
5818 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
5819 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = hcryp->Init.B0[1];
5820 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = hcryp->Init.B0[2];
5821 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
5822
5823 /* Enable the CRYP peripheral */
5824 __HAL_CRYP_ENABLE(hcryp);
5825
5826 /*Write the B0 packet into CRYP_DR*/
5827 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0);
5828 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
5829 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
5830 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
5831
5832 /* Get tick */
5833 tickstart = HAL_GetTick();
5834
5835 /*Wait for the CRYPEN bit to be cleared */
5836 while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
5837 {
5838 /* Check for the Timeout */
5839 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
5840 {
5841 /* Disable the CRYP peripheral clock */
5842 __HAL_CRYP_DISABLE(hcryp);
5843
5844 /* Change state */
5845 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5846 hcryp->State = HAL_CRYP_STATE_READY;
5847
5848 /* Process unlocked */
5849 __HAL_UNLOCK(hcryp);
5850 return HAL_ERROR;
5851 }
5852 }
5853 }
5854 #endif /* USE_HAL_CRYP_ONLY */
5855 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5856 if (IS_SAES_INSTANCE(hcryp->Instance))
5857 {
5858 SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
5859
5860 /* We should re-write Key, in the case where we change key after first operation */
5861 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
5862 {
5863 /* Set the Key */
5864 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5865 }
5866
5867 /* Set the initialization vector (IV) with B0 */
5868 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.B0);
5869 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
5870 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
5871 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
5872
5873 /* Enable the CRYP peripheral */
5874 __HAL_CRYP_ENABLE(hcryp);
5875
5876 /* just wait for hash computation */
5877 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5878 {
5879 /* Disable the CRYP peripheral clock */
5880 __HAL_CRYP_DISABLE(hcryp);
5881
5882 /* Change state */
5883 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5884 hcryp->State = HAL_CRYP_STATE_READY;
5885
5886 /* Process unlocked */
5887 __HAL_UNLOCK(hcryp);
5888 return HAL_ERROR;
5889 }
5890 /* Clear CCF flag */
5891 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
5892 }
5893 #endif /* USE_HAL_SAES_ONLY */
5894
5895 /***************************** Header phase *********************************/
5896
5897 /* Select header phase */
5898 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5899 if (IS_CRYP_INSTANCE(hcryp->Instance))
5900 {
5901 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5902
5903 /* Enable interrupts */
5904 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
5905
5906 /* Enable CRYP */
5907 __HAL_CRYP_ENABLE(hcryp);
5908 }
5909 #endif /* USE_HAL_CRYP_ONLY */
5910 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5911 if (IS_SAES_INSTANCE(hcryp->Instance))
5912 {
5913 /* Select header phase */
5914 SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
5915
5916 /* Enable computation complete flag and error interrupts */
5917 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
5918
5919 /* Enable the CRYP peripheral */
5920 __HAL_CRYP_ENABLE(hcryp);
5921
5922 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
5923 if (headersize_in_bytes == 0U) /* Header phase is skipped */
5924 {
5925 /* Set the phase */
5926 hcryp->Phase = CRYP_PHASE_PROCESS;
5927
5928 /* Select payload phase once the header phase is performed */
5929 SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
5930
5931 /* Set to 0 the number of non-valid bytes using NPBLB register*/
5932 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
5933
5934 if (hcryp->Init.Algorithm == CRYP_AES_CCM)
5935 {
5936 /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
5937 hcryp->CrypHeaderCount++;
5938 }
5939 /* Write the payload Input block in the IN FIFO */
5940 if (hcryp->Size == 0U)
5941 {
5942 /* Disable interrupts */
5943 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
5944
5945 /* Change the CRYP state */
5946 hcryp->State = HAL_CRYP_STATE_READY;
5947 __HAL_UNLOCK(hcryp);
5948 }
5949 else if (hcryp->Size >= 16U)
5950 {
5951 hcryp->CrypInCount++;
5952 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
5953 hcryp->CrypInCount++;
5954 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
5955 hcryp->CrypInCount++;
5956 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
5957 hcryp->CrypInCount++;
5958 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
5959
5960 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
5961 {
5962 /* Call Input transfer complete callback */
5963 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5964 /*Call registered Input complete callback*/
5965 hcryp->InCpltCallback(hcryp);
5966 #else
5967 /*Call legacy Input complete callback*/
5968 HAL_CRYP_InCpltCallback(hcryp);
5969 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5970 }
5971 }
5972 else /* Size < 4 words : first block is the last block*/
5973 {
5974 /* Compute the number of padding bytes in last block of payload */
5975 npblb = 16U - (uint32_t)hcryp->Size;
5976
5977 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
5978 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
5979 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
5980 {
5981 /* Specify the number of non-valid bytes using NPBLB register*/
5982 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
5983 }
5984
5985 /* Number of valid words (lastwordsize) in last block */
5986 if ((npblb % 4U) == 0U)
5987 {
5988 lastwordsize = (16U - npblb) / 4U;
5989 }
5990 else
5991 {
5992 lastwordsize = ((16U - npblb) / 4U) + 1U;
5993 }
5994
5995 /* Last block optionally pad the data with zeros*/
5996 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5997 {
5998 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5999 hcryp->CrypInCount++;
6000 }
6001 while (loopcounter < 4U)
6002 {
6003 /* Pad the data with zeros to have a complete block */
6004 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
6005 loopcounter++;
6006 }
6007 /* Call Input transfer complete callback */
6008 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6009 /*Call registered Input complete callback*/
6010 hcryp->InCpltCallback(hcryp);
6011 #else
6012 /*Call legacy Input complete callback*/
6013 HAL_CRYP_InCpltCallback(hcryp);
6014 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6015 }
6016 }
6017 /* Enter header data */
6018 /* Check first whether header length is small enough to enter the full header in one shot */
6019 else if (headersize_in_bytes <= 16U)
6020 {
6021 for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
6022 {
6023 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6024 hcryp->CrypHeaderCount++;
6025 }
6026 /* If the header size is a multiple of words */
6027 if ((headersize_in_bytes % 4U) == 0U)
6028 {
6029 /* Pad the data with zeros to have a complete block */
6030 while (loopcounter < 4U)
6031 {
6032 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
6033 loopcounter++;
6034 }
6035 }
6036 else
6037 {
6038 /* Enter last bytes, padded with zeros */
6039 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6040 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6041 ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
6042 hcryp->CrypHeaderCount++;
6043 loopcounter++;
6044 /* Pad the data with zeros to have a complete block */
6045 while (loopcounter < 4U)
6046 {
6047 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
6048 loopcounter++;
6049 }
6050 }
6051 /* Call Input transfer complete callback */
6052 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6053 /*Call registered Input complete callback*/
6054 hcryp->InCpltCallback(hcryp);
6055 #else
6056 /*Call legacy Input complete callback*/
6057 HAL_CRYP_InCpltCallback(hcryp);
6058 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6059 }
6060 else
6061 {
6062 /* Write the first input header block in the Input FIFO,
6063 the following header data will be fed after interrupt occurrence */
6064 hcryp->CrypHeaderCount++;
6065 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
6066 hcryp->CrypHeaderCount++;
6067 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
6068 hcryp->CrypHeaderCount++;
6069 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
6070 hcryp->CrypHeaderCount++;
6071 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount - 1U);
6072 } /* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/
6073 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
6074 #endif /* USE_HAL_SAES_ONLY */
6075 } /* end of if (dokeyivconfig == 1U) */
6076 else /* Key and IV have already been configured,
6077 header has already been processed;
6078 only process here message payload */
6079 {
6080 /* Write the payload Input block in the IN FIFO */
6081 if (hcryp->Size == 0U)
6082 {
6083 /* Disable interrupts */
6084 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
6085
6086 /* Change the CRYP state */
6087 hcryp->State = HAL_CRYP_STATE_READY;
6088 __HAL_UNLOCK(hcryp);
6089 }
6090 else if (hcryp->Size >= 16U)
6091 {
6092 hcryp->CrypInCount++;
6093 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
6094 hcryp->CrypInCount++;
6095 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
6096 hcryp->CrypInCount++;
6097 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
6098 hcryp->CrypInCount++;
6099 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount - 1U);
6100
6101 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
6102 {
6103 /* Call Input transfer complete callback */
6104 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6105 /*Call registered Input complete callback*/
6106 hcryp->InCpltCallback(hcryp);
6107 #else
6108 /*Call legacy Input complete callback*/
6109 HAL_CRYP_InCpltCallback(hcryp);
6110 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6111 }
6112 }
6113 else /* Size < 4 words : first block is the last block*/
6114 {
6115 /* Compute the number of padding bytes in last block of payload */
6116 npblb = 16U - (uint32_t)hcryp->Size;
6117
6118 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
6119 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
6120 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
6121 {
6122 /* Specify the number of non-valid bytes using NPBLB register*/
6123 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
6124 }
6125
6126 /* Number of valid words (lastwordsize) in last block */
6127 if ((npblb % 4U) == 0U)
6128 {
6129 lastwordsize = (16U - npblb) / 4U;
6130 }
6131 else
6132 {
6133 lastwordsize = ((16U - npblb) / 4U) + 1U;
6134 }
6135
6136 /* Last block optionally pad the data with zeros*/
6137 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
6138 {
6139 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6140 hcryp->CrypInCount++;
6141 }
6142 while (loopcounter < 4U)
6143 {
6144 /* Pad the data with zeros to have a complete block */
6145 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
6146 loopcounter++;
6147 }
6148 /* Call Input transfer complete callback */
6149 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6150 /*Call registered Input complete callback*/
6151 hcryp->InCpltCallback(hcryp);
6152 #else
6153 /*Call legacy Input complete callback*/
6154 HAL_CRYP_InCpltCallback(hcryp);
6155 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6156 }
6157 } /* end of if (DoKeyIVConfig == 1U) */
6158
6159 /* Return function status */
6160 return HAL_OK;
6161 }
6162
6163
6164 /**
6165 * @brief AES CCM encryption/decryption process in DMA mode
6166 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6167 * the configuration information for CRYP module
6168 * @retval HAL status
6169 */
CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef * hcryp)6170 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
6171 {
6172 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
6173 uint32_t index;
6174 uint32_t npblb;
6175 uint32_t lastwordsize = 0U;
6176 uint32_t temp[4]; /* Temporary CrypOutBuff */
6177 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
6178 uint32_t mode;
6179 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
6180 uint32_t tickstart;
6181 #endif /* USE_HAL_CRYP_ONLY */
6182
6183 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
6184 {
6185 if (hcryp->KeyIVConfig == 1U)
6186 {
6187 /* If the Key and IV configuration has to be done only once
6188 and if it has already been done, skip it */
6189 DoKeyIVConfig = 0U;
6190 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
6191 }
6192 else
6193 {
6194 /* If the Key and IV configuration has to be done only once
6195 and if it has not been done already, do it and set KeyIVConfig
6196 to keep track it won't have to be done again next time */
6197 hcryp->KeyIVConfig = 1U;
6198 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
6199 }
6200 }
6201 else
6202 {
6203 hcryp->SizesSum = hcryp->Size;
6204 }
6205
6206 if (DoKeyIVConfig == 1U)
6207 {
6208 /* Reset CrypHeaderCount */
6209 hcryp->CrypHeaderCount = 0U;
6210
6211 /************************** Init phase **************************************/
6212 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
6213 if (IS_CRYP_INSTANCE(hcryp->Instance))
6214 {
6215 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
6216
6217 /* Set the Key */
6218 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
6219 {
6220 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
6221 {
6222 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
6223 }
6224 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
6225 {
6226 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
6227 }
6228 }
6229 /* Set the initialization vector (IV) with CTR1 information */
6230 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
6231 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = hcryp->Init.B0[1];
6232 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = hcryp->Init.B0[2];
6233 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
6234
6235 /* Enable the CRYP peripheral */
6236 __HAL_CRYP_ENABLE(hcryp);
6237
6238 /*Write the B0 packet into CRYP_DR*/
6239 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0);
6240 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
6241 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
6242 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
6243
6244 /* Get tick */
6245 tickstart = HAL_GetTick();
6246
6247 /*Wait for the CRYPEN bit to be cleared*/
6248 while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
6249 {
6250 /* Check for the Timeout */
6251 if ((HAL_GetTick() - tickstart) > CRYP_TIMEOUT_GCMCCMINITPHASE)
6252 {
6253 /* Disable the CRYP peripheral clock */
6254 __HAL_CRYP_DISABLE(hcryp);
6255
6256 /* Change state */
6257 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6258 hcryp->State = HAL_CRYP_STATE_READY;
6259
6260 /* Process unlocked */
6261 __HAL_UNLOCK(hcryp);
6262 return HAL_ERROR;
6263 }
6264 }
6265 }
6266 #endif /* USE_HAL_CRYP_ONLY */
6267 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
6268 if (IS_SAES_INSTANCE(hcryp->Instance))
6269 {
6270 SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
6271
6272 /* We should re-write Key, in the case where we change key after first operation */
6273 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
6274 {
6275 /* Set the Key */
6276 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
6277 };
6278
6279 /* Set the initialization vector (IV) with B0 */
6280 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.B0);
6281 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
6282 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
6283 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
6284
6285 /* Enable the CRYP peripheral */
6286 __HAL_CRYP_ENABLE(hcryp);
6287
6288 /* just wait for hash computation */
6289 if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMINITPHASE) != HAL_OK)
6290 {
6291 /* Disable the CRYP peripheral clock */
6292 __HAL_CRYP_DISABLE(hcryp);
6293
6294 /* Change state */
6295 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6296 hcryp->State = HAL_CRYP_STATE_READY;
6297
6298 /* Process unlocked */
6299 __HAL_UNLOCK(hcryp);
6300 return HAL_ERROR;
6301 }
6302 /* Clear CCF flag */
6303 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
6304 }
6305 #endif /* USE_HAL_SAES_ONLY */
6306
6307 /********************* Header phase *****************************************/
6308
6309 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
6310 {
6311 return HAL_ERROR;
6312 }
6313
6314 /******************** Payload phase *****************************************/
6315
6316 /* Set the phase */
6317 hcryp->Phase = CRYP_PHASE_PROCESS;
6318
6319 /* Select payload phase once the header phase is performed */
6320 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
6321 if (IS_CRYP_INSTANCE(hcryp->Instance))
6322 {
6323 /* Disable the CRYP peripheral */
6324 __HAL_CRYP_DISABLE(hcryp);
6325
6326 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
6327
6328 /* Set to 0 the number of non-valid bytes using NPBLB register*/
6329 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
6330
6331 /* Enable the CRYP peripheral */
6332 __HAL_CRYP_ENABLE(hcryp);
6333 }
6334 #endif /* USE_HAL_CRYP_ONLY */
6335 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
6336 if (IS_SAES_INSTANCE(hcryp->Instance))
6337 {
6338 SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
6339
6340 /* Set to 0 the number of non-valid bytes using NPBLB register*/
6341 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
6342 }
6343 #endif /* USE_CRYP_INSTANCE */
6344 } /* if (DoKeyIVConfig == 1U) */
6345
6346 if (hcryp->Size == 0U)
6347 {
6348 /* Process unLocked */
6349 __HAL_UNLOCK(hcryp);
6350
6351 /* Change the CRYP state and phase */
6352 hcryp->State = HAL_CRYP_STATE_READY;
6353 }
6354 else if (hcryp->Size >= 16U)
6355 {
6356 wordsize = wordsize - (wordsize % 4U);
6357 /* DMA transfer */
6358 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t) wordsize * 4U,
6359 (uint32_t)(hcryp->pCrypOutBuffPtr));
6360 }
6361 else /* length of input data is < 16U */
6362 {
6363 /* Compute the number of padding bytes in last block of payload */
6364 npblb = 16U - (uint32_t)(hcryp->Size);
6365
6366 /* Set Npblb in case of AES CCM payload decryption to get right tag*/
6367 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
6368 if (IS_CRYP_INSTANCE(hcryp->Instance))
6369 {
6370 mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
6371
6372 if (mode == CRYP_OPERATINGMODE_DECRYPT)
6373 {
6374 /* Specify the number of non-valid bytes using NPBLB register*/
6375 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
6376 }
6377
6378 /* Enable CRYP to start the final phase */
6379 __HAL_CRYP_ENABLE(hcryp);
6380
6381 /* Number of valid words (lastwordsize) in last block */
6382 if ((npblb % 4U) == 0U)
6383 {
6384 lastwordsize = (16U - npblb) / 4U;
6385 }
6386 else
6387 {
6388 lastwordsize = ((16U - npblb) / 4U) + 1U;
6389 }
6390
6391 /* Write the last input block in the IN FIFO */
6392 for (index = 0U; index < lastwordsize; index ++)
6393 {
6394 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6395 hcryp->CrypInCount++;
6396 }
6397
6398 /* Pad the data with zeros to have a complete block */
6399 while (index < 4U)
6400 {
6401 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
6402 index++;
6403 }
6404
6405 /* Wait for OFNE flag to be raised */
6406 if (CRYP_WaitOnOFNEFlag(hcryp, CRYP_TIMEOUT_GCMCCMINITPHASE) != HAL_OK)
6407 {
6408 /* Disable the CRYP peripheral clock */
6409 __HAL_CRYP_DISABLE(hcryp);
6410
6411 /* Change state & update error code */
6412 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6413 hcryp->State = HAL_CRYP_STATE_READY;
6414
6415 /* Process unlocked */
6416 __HAL_UNLOCK(hcryp);
6417 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6418 /*Call registered error callback*/
6419 hcryp->ErrorCallback(hcryp);
6420 #else
6421 /*Call legacy error callback*/
6422 HAL_CRYP_ErrorCallback(hcryp);
6423 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6424 }
6425
6426 /*Read the output block from the output FIFO */
6427 for (index = 0U; index < 4U; index++)
6428 {
6429 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
6430 temporary buffer */
6431 temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
6432 }
6433 } /* SAES peripheral */
6434 #endif /* USE_HAL_CRYP_ONLY */
6435 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
6436 if (IS_SAES_INSTANCE(hcryp->Instance))
6437 {
6438 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
6439
6440 if (mode == CRYP_OPERATINGMODE_DECRYPT)
6441 {
6442 /* Specify the number of non-valid bytes using NPBLB register*/
6443 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20);
6444 }
6445
6446 /* Number of valid words (lastwordsize) in last block */
6447 if ((npblb % 4U) == 0U)
6448 {
6449 lastwordsize = (16U - npblb) / 4U;
6450 }
6451 else
6452 {
6453 lastwordsize = ((16U - npblb) / 4U) + 1U;
6454 }
6455
6456 /* Write the last input block in the IN FIFO */
6457 for (index = 0U; index < lastwordsize; index ++)
6458 {
6459 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6460 hcryp->CrypInCount++;
6461 }
6462
6463 /* Pad the data with zeros to have a complete block */
6464 while (index < 4U)
6465 {
6466 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U;
6467 index++;
6468 }
6469 /* just wait for hash computation */
6470 if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMINITPHASE) != HAL_OK)
6471 {
6472 /* Disable the CRYP peripheral clock */
6473 __HAL_CRYP_DISABLE(hcryp);
6474
6475 /* Change state & update error code */
6476 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6477 hcryp->State = HAL_CRYP_STATE_READY;
6478
6479 /* Process unlocked */
6480 __HAL_UNLOCK(hcryp);
6481 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6482 /*Call registered error callback*/
6483 hcryp->ErrorCallback(hcryp);
6484 #else
6485 /*Call legacy error callback*/
6486 HAL_CRYP_ErrorCallback(hcryp);
6487 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6488 }
6489 /* Clear CCF flag */
6490 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
6491
6492 /*Read the output block from the output FIFO */
6493 for (index = 0U; index < 4U; index++)
6494 {
6495 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
6496 temporary buffer */
6497 temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
6498 }
6499 }
6500 #endif /* USE_HAL_SAES_ONLY */
6501
6502 for (index = 0; index < lastwordsize; index++)
6503 {
6504 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
6505 hcryp->CrypOutCount++;
6506 }
6507
6508 /* Change the CRYP state to ready */
6509 hcryp->State = HAL_CRYP_STATE_READY;
6510
6511 /* Process unlocked */
6512 __HAL_UNLOCK(hcryp);
6513 }
6514
6515 /* Return function status */
6516 return HAL_OK;
6517 }
6518
6519 /**
6520 * @brief Sets the payload phase in interrupt mode
6521 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6522 * the configuration information for CRYP module
6523 * @retval state
6524 */
CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef * hcryp)6525 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
6526 {
6527 uint32_t loopcounter;
6528 uint32_t temp[4]; /* Temporary CrypOutBuff */
6529 uint32_t lastwordsize;
6530 uint32_t npblb;
6531 uint32_t mode;
6532 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
6533 uint8_t negative = 0U;
6534 #endif /* USE_HAL_CRYP_ONLY */
6535 uint32_t i;
6536
6537 /***************************** Payload phase *******************************/
6538 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
6539 if (IS_CRYP_INSTANCE(hcryp->Instance))
6540 {
6541 if ((hcryp->Size / 4U) < hcryp->CrypInCount)
6542 {
6543 negative = 1U;
6544 }
6545
6546 if (hcryp->Size == 0U)
6547 {
6548 /* Disable interrupts */
6549 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
6550
6551 /* Process unlocked */
6552 __HAL_UNLOCK(hcryp);
6553
6554 /* Change the CRYP state */
6555 hcryp->State = HAL_CRYP_STATE_READY;
6556 }
6557
6558 else if ((((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) &&
6559 (negative == 0U))
6560 {
6561 if ((((CRYP_TypeDef *)(hcryp->Instance))->IMSCR & CRYP_IMSCR_INIM) != 0x0U)
6562 {
6563
6564 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
6565 /* If suspension flag has been raised, suspend processing
6566 only if not already at the end of the payload */
6567 if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
6568 {
6569 /* Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the
6570 CRYP_SR) and the BUSY bit is cleared */
6571 while (((((CRYP_TypeDef *)(hcryp->Instance))->SR) & (CRYP_SR_IFEM | CRYP_SR_OFNE | \
6572 CRYP_SR_BUSY)) != CRYP_SR_IFEM)
6573 {
6574 /* Nothing to do */
6575 }
6576
6577 /* Disable interrupts */
6578 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
6579
6580 /* Disable CRYP */
6581 __HAL_CRYP_DISABLE(hcryp);
6582
6583 /* reset SuspendRequest */
6584 hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
6585
6586 /* Change the CRYP state */
6587 hcryp->State = HAL_CRYP_STATE_SUSPENDED;
6588
6589 /* Mark that the payload phase is suspended */
6590 hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
6591
6592 /* Process Unlocked */
6593 __HAL_UNLOCK(hcryp);
6594 }
6595 else
6596 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
6597 {
6598 /* Write the input block in the IN FIFO */
6599 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6600 hcryp->CrypInCount++;
6601 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6602 hcryp->CrypInCount++;
6603 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6604 hcryp->CrypInCount++;
6605 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6606 hcryp->CrypInCount++;
6607 if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U))
6608 {
6609 /* Disable interrupts */
6610 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
6611 /* Call the input data transfer complete callback */
6612 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6613 /*Call registered Input complete callback*/
6614 hcryp->InCpltCallback(hcryp);
6615 #else
6616 /*Call legacy Input complete callback*/
6617 HAL_CRYP_InCpltCallback(hcryp);
6618 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6619 }
6620
6621 if (hcryp->CrypOutCount < (hcryp->Size / 4U))
6622 {
6623 if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U)
6624 {
6625 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from
6626 temporary buffer */
6627 for (i = 0U; i < 4U; i++)
6628 {
6629 temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
6630 }
6631 i = 0U;
6632 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
6633 {
6634 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
6635 hcryp->CrypOutCount++;
6636 i++;
6637 }
6638 if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
6639 {
6640 /* Disable interrupts */
6641 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
6642
6643 /* Change the CRYP state */
6644 hcryp->State = HAL_CRYP_STATE_READY;
6645
6646 /* Disable CRYP */
6647 __HAL_CRYP_DISABLE(hcryp);
6648
6649 /* Process unlocked */
6650 __HAL_UNLOCK(hcryp);
6651
6652 /* Call output transfer complete callback */
6653 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6654 /*Call registered Output complete callback*/
6655 hcryp->OutCpltCallback(hcryp);
6656 #else
6657 /*Call legacy Output complete callback*/
6658 HAL_CRYP_OutCpltCallback(hcryp);
6659 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6660 }
6661 }
6662 }
6663 } /* if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) */
6664 }
6665 }
6666 else if ((hcryp->Size % 16U) != 0U)
6667 {
6668 /* Set padding only in case of input fifo interrupt */
6669 if ((((CRYP_TypeDef *)(hcryp->Instance))->IMSCR & CRYP_IMSCR_INIM) != 0x0U)
6670 {
6671 /* Compute the number of padding bytes in last block of payload */
6672 npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
6673
6674 mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
6675 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
6676 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
6677 {
6678 /* Disable the CRYP */
6679 __HAL_CRYP_DISABLE(hcryp);
6680
6681 /* Specify the number of non-valid bytes using NPBLB register*/
6682 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
6683
6684 /* Enable CRYP to start the final phase */
6685 __HAL_CRYP_ENABLE(hcryp);
6686 }
6687
6688
6689 /* Number of valid words (lastwordsize) in last block */
6690 if ((npblb % 4U) == 0U)
6691 {
6692 lastwordsize = (16U - npblb) / 4U;
6693 }
6694 else
6695 {
6696 lastwordsize = ((16U - npblb) / 4U) + 1U;
6697 }
6698
6699 /* Write the last input block in the IN FIFO */
6700 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
6701 {
6702 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6703 hcryp->CrypInCount++;
6704 }
6705 /* Pad the data with zeros to have a complete block */
6706 while (loopcounter < 4U)
6707 {
6708 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
6709 loopcounter++;
6710 }
6711
6712 /* Disable the input FIFO Interrupt */
6713 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
6714 }
6715
6716 /*Read the output block from the output FIFO */
6717 if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U)
6718 {
6719 for (i = 0U; i < 4U; i++)
6720 {
6721 temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
6722 }
6723 if (((hcryp->Size) / 4U) == 0U)
6724 {
6725 for (i = 0U; (uint16_t)i < ((hcryp->Size) % 4U); i++)
6726 {
6727 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
6728 hcryp->CrypOutCount++;
6729 }
6730 }
6731 i = 0U;
6732 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
6733 {
6734 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
6735 hcryp->CrypOutCount++;
6736 i++;
6737 }
6738 }
6739
6740 /* Disable the output FIFO Interrupt */
6741 if (hcryp->CrypOutCount >= ((hcryp->Size) / 4U))
6742 {
6743 /* Disable interrupts */
6744 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);
6745
6746 /* Change the CRYP peripheral state */
6747 hcryp->State = HAL_CRYP_STATE_READY;
6748
6749 /* Process unlocked */
6750 __HAL_UNLOCK(hcryp);
6751
6752 /* Call output transfer complete callback */
6753 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6754 /*Call registered Output complete callback*/
6755 hcryp->OutCpltCallback(hcryp);
6756 #else
6757 /*Call legacy Output complete callback*/
6758 HAL_CRYP_OutCpltCallback(hcryp);
6759 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6760 }
6761 }
6762 else
6763 {
6764 /* Nothing to do */
6765 }
6766 }
6767 #endif /* USE_HAL_CRYP_ONLY */
6768 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
6769 if (IS_SAES_INSTANCE(hcryp->Instance))
6770 {
6771 uint32_t incount;
6772 uint32_t outcount;
6773
6774 /* Read the output block from the output FIFO and put them in temporary buffer then
6775 get CrypOutBuff from temporary buffer*/
6776 for (i = 0U; i < 4U; i++)
6777 {
6778 temp[i] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
6779 }
6780 i = 0U;
6781 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
6782 {
6783 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
6784 hcryp->CrypOutCount++;
6785 i++;
6786 }
6787 incount = hcryp->CrypInCount;
6788 outcount = hcryp->CrypOutCount;
6789 if ((outcount >= ((uint32_t)(hcryp->Size) / 4U)) && ((incount * 4U) >= (uint32_t)(hcryp->Size)))
6790 {
6791
6792 /* When in CCM with Key and IV configuration skipped, don't disable interruptions */
6793 if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U)))
6794 {
6795 /* Disable computation complete flag and errors interrupts */
6796 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
6797 }
6798
6799 /* Change the CRYP state */
6800 hcryp->State = HAL_CRYP_STATE_READY;
6801 __HAL_UNLOCK(hcryp);
6802
6803 /* Call output transfer complete callback */
6804 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6805 /*Call registered Output complete callback*/
6806 hcryp->OutCpltCallback(hcryp);
6807 #else
6808 /*Call legacy Output complete callback*/
6809 HAL_CRYP_OutCpltCallback(hcryp);
6810 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6811 }
6812
6813 else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
6814 {
6815
6816 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
6817 /* If suspension flag has been raised, suspend processing
6818 only if not already at the end of the payload */
6819 if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
6820 {
6821 /* Clear CCF Flag */
6822 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
6823
6824 /* reset SuspendRequest */
6825 hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
6826 /* Disable Computation Complete Flag and Errors Interrupts */
6827 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
6828 /* Change the CRYP state */
6829 hcryp->State = HAL_CRYP_STATE_SUSPENDED;
6830 /* Mark that the payload phase is suspended */
6831 hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
6832 __HAL_UNLOCK(hcryp);
6833 }
6834 else
6835 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
6836 {
6837 /* Write the input block in the IN FIFO */
6838 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6839 hcryp->CrypInCount++;
6840 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6841 hcryp->CrypInCount++;
6842 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6843 hcryp->CrypInCount++;
6844 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6845 hcryp->CrypInCount++;
6846 if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM))
6847 {
6848 /* Call output transfer complete callback */
6849 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6850 /*Call registered Input complete callback*/
6851 hcryp->InCpltCallback(hcryp);
6852 #else
6853 /*Call legacy Input complete callback*/
6854 HAL_CRYP_InCpltCallback(hcryp);
6855 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6856 }
6857 }
6858 }
6859 else /* Last block of payload < 128bit*/
6860 {
6861 /* Compute the number of padding bytes in last block of payload */
6862 npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
6863
6864 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
6865 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
6866 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
6867 {
6868 /* Specify the number of non-valid bytes using NPBLB register*/
6869 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20);
6870 }
6871
6872 /* Number of valid words (lastwordsize) in last block */
6873 if ((npblb % 4U) == 0U)
6874 {
6875 lastwordsize = (16U - npblb) / 4U;
6876 }
6877 else
6878 {
6879 lastwordsize = ((16U - npblb) / 4U) + 1U;
6880 }
6881
6882 /* Last block optionally pad the data with zeros*/
6883 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
6884 {
6885 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6886 hcryp->CrypInCount++;
6887 }
6888 while (loopcounter < 4U)
6889 {
6890 /* pad the data with zeros to have a complete block */
6891 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
6892 loopcounter++;
6893 }
6894 }
6895 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
6896 #endif /* USE_HAL_SAES_ONLY */
6897 }
6898
6899
6900 /**
6901 * @brief Sets the header phase in polling mode
6902 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6903 * the configuration information for CRYP module(Header & HeaderSize)
6904 * @param Timeout: Timeout value
6905 * @retval state
6906 */
CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)6907 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6908 {
6909 uint32_t loopcounter;
6910 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
6911 uint32_t headersize_in_bytes;
6912 uint32_t tmp;
6913 const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
6914 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
6915 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
6916 }; /* 8-bit data type */
6917 #endif /* USE_HAL_SAES_ONLY */
6918
6919 /***************************** Header phase for GCM/GMAC or CCM *********************************/
6920
6921 /* Select header phase */
6922 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
6923 if (IS_CRYP_INSTANCE(hcryp->Instance))
6924 {
6925 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
6926 /* Enable the CRYP peripheral */
6927 __HAL_CRYP_ENABLE(hcryp);
6928
6929 if ((hcryp->Init.HeaderSize % 4U) == 0U)
6930 {
6931 /* HeaderSize %4, no padding */
6932 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
6933 {
6934 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6935 hcryp->CrypHeaderCount++ ;
6936 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6937 hcryp->CrypHeaderCount++ ;
6938 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6939 hcryp->CrypHeaderCount++ ;
6940 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6941 hcryp->CrypHeaderCount++ ;
6942
6943 /* Wait for IFEM to be raised */
6944 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
6945 {
6946 /* Disable the CRYP peripheral clock */
6947 __HAL_CRYP_DISABLE(hcryp);
6948
6949 /* Change state */
6950 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6951 hcryp->State = HAL_CRYP_STATE_READY;
6952
6953 /* Process unlocked */
6954 __HAL_UNLOCK(hcryp);
6955 return HAL_ERROR;
6956 }
6957 }
6958 }
6959 else
6960 {
6961 /*Write header block in the IN FIFO without last block */
6962 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U)));
6963 loopcounter += 4U)
6964 {
6965 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6966 hcryp->CrypHeaderCount++ ;
6967 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6968 hcryp->CrypHeaderCount++ ;
6969 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6970 hcryp->CrypHeaderCount++ ;
6971 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6972 hcryp->CrypHeaderCount++ ;
6973
6974 /* Wait for IFEM to be raised */
6975 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
6976 {
6977 /* Disable the CRYP peripheral clock */
6978 __HAL_CRYP_DISABLE(hcryp);
6979
6980 /* Change state */
6981 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6982 hcryp->State = HAL_CRYP_STATE_READY;
6983
6984 /* Process unlocked */
6985 __HAL_UNLOCK(hcryp);
6986 return HAL_ERROR;
6987 }
6988 }
6989 /* Last block optionally pad the data with zeros*/
6990 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
6991 {
6992 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6993 hcryp->CrypHeaderCount++ ;
6994 }
6995 while (loopcounter < 4U)
6996 {
6997 /* pad the data with zeros to have a complete block */
6998 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0x0U;
6999 loopcounter++;
7000 }
7001 /* Wait for IFEM to be raised */
7002 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
7003 {
7004 /* Disable the CRYP peripheral clock */
7005 __HAL_CRYP_DISABLE(hcryp);
7006
7007 /* Change state */
7008 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7009 hcryp->State = HAL_CRYP_STATE_READY;
7010
7011 /* Process unlocked */
7012 __HAL_UNLOCK(hcryp);
7013 return HAL_ERROR;
7014 }
7015 }
7016 }
7017 #endif /* USE_HAL_CRYP_ONLY */
7018 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7019 if (IS_SAES_INSTANCE(hcryp->Instance))
7020 {
7021 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
7022 {
7023 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
7024 }
7025 else
7026 {
7027 headersize_in_bytes = hcryp->Init.HeaderSize;
7028 }
7029
7030 /* Set Header phase */
7031 SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
7032
7033 /* Enable the CRYP peripheral */
7034 __HAL_CRYP_ENABLE(hcryp);
7035
7036 if ((headersize_in_bytes % 16U) == 0U)
7037 {
7038 /* HeaderSize %4, no padding */
7039 for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
7040 {
7041 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7042 hcryp->CrypHeaderCount++ ;
7043 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7044 hcryp->CrypHeaderCount++ ;
7045 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7046 hcryp->CrypHeaderCount++ ;
7047 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7048 hcryp->CrypHeaderCount++ ;
7049
7050 /* Wait for CCF to be raised */
7051 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
7052 {
7053 /* Disable the CRYP peripheral clock */
7054 __HAL_CRYP_DISABLE(hcryp);
7055
7056 /* Change state */
7057 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7058 hcryp->State = HAL_CRYP_STATE_READY;
7059
7060 /* Process unlocked */
7061 __HAL_UNLOCK(hcryp);
7062 return HAL_ERROR;
7063 }
7064 /* Clear CCF flag */
7065 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
7066 }
7067 }
7068 else
7069 {
7070 /*Write header block in the IN FIFO without last block */
7071 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
7072 {
7073 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7074 hcryp->CrypHeaderCount++ ;
7075 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7076 hcryp->CrypHeaderCount++ ;
7077 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7078 hcryp->CrypHeaderCount++ ;
7079 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7080 hcryp->CrypHeaderCount++ ;
7081
7082 /* Wait for CCF to be raised */
7083 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
7084 {
7085 /* Disable the CRYP peripheral clock */
7086 __HAL_CRYP_DISABLE(hcryp);
7087
7088 /* Change state */
7089 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7090 hcryp->State = HAL_CRYP_STATE_READY;
7091
7092 /* Process unlocked */
7093 __HAL_UNLOCK(hcryp);
7094 return HAL_ERROR;
7095 }
7096 /* Clear CCF flag */
7097 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
7098 }
7099 /* Write last complete words */
7100 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
7101 {
7102 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7103 hcryp->CrypHeaderCount++ ;
7104 }
7105 /* If the header size is a multiple of words */
7106 if ((headersize_in_bytes % 4U) == 0U)
7107 {
7108 /* Pad the data with zeros to have a complete block */
7109 while (loopcounter < 4U)
7110 {
7111 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
7112 loopcounter++;
7113 }
7114 }
7115 else
7116 {
7117 /* Enter last bytes, padded with zeros */
7118 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7119 tmp &= mask[(SAES_CONV_DATATYPE(hcryp->Init.DataType) * 2U) + (headersize_in_bytes % 4U)];
7120 ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
7121 loopcounter++;
7122 /* Pad the data with zeros to have a complete block */
7123 while (loopcounter < 4U)
7124 {
7125 /* pad the data with zeros to have a complete block */
7126 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
7127 loopcounter++;
7128 }
7129 }
7130
7131 /* Wait for CCF to be raised */
7132 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
7133 {
7134 /* Disable the CRYP peripheral clock */
7135 __HAL_CRYP_DISABLE(hcryp);
7136
7137 /* Change state */
7138 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7139 hcryp->State = HAL_CRYP_STATE_READY;
7140
7141 /* Process unlocked */
7142 __HAL_UNLOCK(hcryp);
7143 return HAL_ERROR;
7144 }
7145 /* Clear CCF flag */
7146 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
7147 }
7148 }
7149 #endif /* USE_HAL_SAES_ONLY */
7150 /* Wait until the complete message has been processed */
7151 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
7152 {
7153 /* Disable the CRYP peripheral clock */
7154 __HAL_CRYP_DISABLE(hcryp);
7155
7156 /* Change state */
7157 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7158 hcryp->State = HAL_CRYP_STATE_READY;
7159
7160 /* Process unlocked & return error */
7161 __HAL_UNLOCK(hcryp);
7162 return HAL_ERROR;
7163 }
7164 /* Return function status */
7165 return HAL_OK;
7166 }
7167
7168
7169 /**
7170 * @brief Sets the header phase when using DMA in process
7171 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7172 * the configuration information for CRYP module(Header & HeaderSize)
7173 * @retval None
7174 */
CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef * hcryp)7175 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
7176 {
7177 uint32_t loopcounter;
7178 uint32_t Timeout = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
7179 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7180 uint32_t headersize_in_bytes;
7181 uint32_t tmp;
7182 const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
7183 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
7184 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
7185 }; /* 8-bit data type */
7186 #endif /* USE_HAL_SAES_ONLY */
7187
7188 /***************************** Header phase for GCM/GMAC or CCM *********************************/
7189 if ((hcryp->Init.HeaderSize != 0U))
7190 {
7191 /* Select header phase */
7192 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7193 if (IS_CRYP_INSTANCE(hcryp->Instance))
7194 {
7195 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
7196 /* Enable the CRYP peripheral */
7197 __HAL_CRYP_ENABLE(hcryp);
7198
7199 if ((hcryp->Init.HeaderSize % 4U) == 0U)
7200 {
7201 /* HeaderSize %4, no padding */
7202 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
7203 {
7204 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7205 hcryp->CrypHeaderCount++ ;
7206 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7207 hcryp->CrypHeaderCount++ ;
7208 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7209 hcryp->CrypHeaderCount++ ;
7210 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7211 hcryp->CrypHeaderCount++ ;
7212
7213 /* Wait for IFEM to be raised */
7214 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
7215 {
7216 /* Disable the CRYP peripheral clock */
7217 __HAL_CRYP_DISABLE(hcryp);
7218
7219 /* Change state */
7220 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7221 hcryp->State = HAL_CRYP_STATE_READY;
7222
7223 /* Process unlocked */
7224 __HAL_UNLOCK(hcryp);
7225 return HAL_ERROR;
7226 }
7227 }
7228 }
7229 else
7230 {
7231 /*Write header block in the IN FIFO without last block */
7232 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U)));
7233 loopcounter += 4U)
7234 {
7235 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7236 hcryp->CrypHeaderCount++ ;
7237 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7238 hcryp->CrypHeaderCount++ ;
7239 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7240 hcryp->CrypHeaderCount++ ;
7241 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7242 hcryp->CrypHeaderCount++ ;
7243
7244 /* Wait for IFEM to be raised */
7245 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
7246 {
7247 /* Disable the CRYP peripheral clock */
7248 __HAL_CRYP_DISABLE(hcryp);
7249
7250 /* Change state */
7251 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7252 hcryp->State = HAL_CRYP_STATE_READY;
7253
7254 /* Process unlocked */
7255 __HAL_UNLOCK(hcryp);
7256 return HAL_ERROR;
7257 }
7258 }
7259 /* Last block optionally pad the data with zeros*/
7260 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
7261 {
7262 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7263 hcryp->CrypHeaderCount++ ;
7264 }
7265 while (loopcounter < 4U)
7266 {
7267 /* Pad the data with zeros to have a complete block */
7268 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0x0U;
7269 loopcounter++;
7270 }
7271
7272 /* Wait for IFEM to be raised */
7273 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
7274 {
7275 /* Disable the CRYP peripheral clock */
7276 __HAL_CRYP_DISABLE(hcryp);
7277
7278 /* Change state */
7279 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7280 hcryp->State = HAL_CRYP_STATE_READY;
7281
7282 /* Process unlocked */
7283 __HAL_UNLOCK(hcryp);
7284 return HAL_ERROR;
7285 }
7286 }
7287 }
7288 #endif /* USE_HAL_CRYP_ONLY */
7289 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7290 if (IS_SAES_INSTANCE(hcryp->Instance))
7291 {
7292 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
7293 {
7294 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
7295 }
7296 else
7297 {
7298 headersize_in_bytes = hcryp->Init.HeaderSize;
7299 }
7300 /* Set header phase*/
7301 SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
7302
7303 /* Enable the CRYP peripheral */
7304 __HAL_CRYP_ENABLE(hcryp);
7305
7306 if ((headersize_in_bytes % 16U) == 0U)
7307 {
7308 /* HeaderSize %4, no padding */
7309 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
7310 {
7311 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7312 hcryp->CrypHeaderCount++ ;
7313 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7314 hcryp->CrypHeaderCount++ ;
7315 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7316 hcryp->CrypHeaderCount++ ;
7317 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7318 hcryp->CrypHeaderCount++ ;
7319
7320 /* Wait for CCF to be raised */
7321 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
7322 {
7323 /* Disable the CRYP peripheral clock */
7324 __HAL_CRYP_DISABLE(hcryp);
7325
7326 /* Change state */
7327 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7328 hcryp->State = HAL_CRYP_STATE_READY;
7329
7330 /* Process unlocked */
7331 __HAL_UNLOCK(hcryp);
7332 return HAL_ERROR;
7333 }
7334 }
7335 }
7336 else
7337 {
7338 /*Write header block in the IN FIFO without last block */
7339 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
7340 {
7341 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7342 hcryp->CrypHeaderCount++ ;
7343 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7344 hcryp->CrypHeaderCount++ ;
7345 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7346 hcryp->CrypHeaderCount++ ;
7347 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7348 hcryp->CrypHeaderCount++ ;
7349
7350 /* Wait for CCF to be raised */
7351 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
7352 {
7353 /* Disable the CRYP peripheral clock */
7354 __HAL_CRYP_DISABLE(hcryp);
7355
7356 /* Change state */
7357 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7358 hcryp->State = HAL_CRYP_STATE_READY;
7359
7360 /* Process unlocked */
7361 __HAL_UNLOCK(hcryp);
7362 return HAL_ERROR;
7363 }
7364 }
7365 /* Write last complete words */
7366 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
7367 {
7368 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7369 hcryp->CrypHeaderCount++;
7370 }
7371 /* If the header size is a multiple of words */
7372 if ((headersize_in_bytes % 4U) == 0U)
7373 {
7374 /* Pad the data with zeros to have a complete block */
7375 while (loopcounter < 4U)
7376 {
7377 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
7378 loopcounter++;
7379 }
7380 }
7381 else
7382 {
7383 /* Enter last bytes, padded with zeros */
7384 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7385 tmp &= mask[(SAES_CONV_DATATYPE(hcryp->Init.DataType) * 2U) + (headersize_in_bytes % 4U)];
7386 ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
7387 loopcounter++;
7388 /* Pad the data with zeros to have a complete block */
7389 while (loopcounter < 4U)
7390 {
7391 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
7392 loopcounter++;
7393 }
7394 }
7395
7396 /* Wait for CCF to be raised */
7397 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
7398 {
7399 /* Disable the CRYP peripheral clock */
7400 __HAL_CRYP_DISABLE(hcryp);
7401
7402 /* Change state */
7403 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7404 hcryp->State = HAL_CRYP_STATE_READY;
7405
7406 /* Process unlocked */
7407 __HAL_UNLOCK(hcryp);
7408 return HAL_ERROR;
7409 }
7410 }
7411 }
7412 #endif /* USE_HAL_SAES_ONLY */
7413 /* Wait until the complete message has been processed */
7414 Timeout = CRYP_GENERAL_TIMEOUT;
7415 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
7416 {
7417 /* Disable the CRYP peripheral clock */
7418 __HAL_CRYP_DISABLE(hcryp);
7419
7420 /* Change state */
7421 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7422 hcryp->State = HAL_CRYP_STATE_READY;
7423
7424 /* Process unlocked */
7425 __HAL_UNLOCK(hcryp);
7426 return HAL_ERROR;
7427 }
7428 }
7429
7430 /* Return function status */
7431 return HAL_OK;
7432 }
7433
7434 /**
7435 * @brief Sets the header phase in interrupt mode
7436 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7437 * the configuration information for CRYP module(Header & HeaderSize)
7438 * @retval None
7439 */
CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef * hcryp)7440 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
7441 {
7442 uint32_t loopcounter;
7443 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7444 uint32_t lastwordsize;
7445 uint32_t npblb;
7446 uint32_t mode;
7447 uint32_t headersize_in_bytes;
7448 uint32_t tmp;
7449 const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
7450 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
7451 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
7452 }; /* 8-bit data type */
7453 #endif /* USE_HAL_SAES_ONLY */
7454
7455 /***************************** Header phase *********************************/
7456 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7457 if (IS_CRYP_INSTANCE(hcryp->Instance))
7458 {
7459 if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
7460 {
7461 /* Disable interrupts */
7462 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
7463
7464 /* Disable the CRYP peripheral */
7465 __HAL_CRYP_DISABLE(hcryp);
7466
7467 /* Set to 0 the number of non-valid bytes using NPBLB register*/
7468 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
7469
7470 /* Set the phase */
7471 hcryp->Phase = CRYP_PHASE_PROCESS;
7472
7473 /* Select payload phase once the header phase is performed */
7474 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
7475
7476 /* Enable Interrupts */
7477 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
7478
7479 /* Enable the CRYP peripheral */
7480 __HAL_CRYP_ENABLE(hcryp);
7481 }
7482 else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
7483
7484 {
7485 /* HeaderSize %4, no padding */
7486 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7487 hcryp->CrypHeaderCount++ ;
7488 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7489 hcryp->CrypHeaderCount++ ;
7490 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7491 hcryp->CrypHeaderCount++ ;
7492 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7493 hcryp->CrypHeaderCount++ ;
7494 }
7495 else
7496 {
7497 /* Last block optionally pad the data with zeros*/
7498 for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
7499 {
7500 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7501 hcryp->CrypHeaderCount++ ;
7502 }
7503 while (loopcounter < 4U)
7504 {
7505 /* Pad the data with zeros to have a complete block */
7506 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0x0U;
7507 loopcounter++ ;
7508 }
7509 }
7510 }
7511 #endif /* USE_HAL_CRYP_ONLY */
7512 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7513 if (IS_SAES_INSTANCE(hcryp->Instance))
7514 {
7515 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
7516 {
7517 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
7518 }
7519 else
7520 {
7521 headersize_in_bytes = hcryp->Init.HeaderSize;
7522 }
7523 /***************************** Header phase *********************************/
7524 /* Test whether or not the header phase is over.
7525 If the test below is true, move to payload phase */
7526 if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
7527 {
7528 /* Set the phase */
7529 hcryp->Phase = CRYP_PHASE_PROCESS;
7530 /* Select payload phase */
7531 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_GCMPH, SAES_PHASE_PAYLOAD);
7532 /* Set to 0 the number of non-valid bytes using NPBLB register*/
7533 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
7534
7535 if (hcryp->Init.Algorithm == CRYP_AES_CCM)
7536 {
7537 /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
7538 hcryp->CrypHeaderCount++;
7539 }
7540 /* Write the payload Input block in the IN FIFO */
7541 if (hcryp->Size == 0U)
7542 {
7543 /* Disable interrupts */
7544 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
7545
7546 /* Change the CRYP state */
7547 hcryp->State = HAL_CRYP_STATE_READY;
7548 __HAL_UNLOCK(hcryp);
7549 }
7550 else if (hcryp->Size >= 16U)
7551 {
7552 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
7553 hcryp->CrypInCount++;
7554 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
7555 hcryp->CrypInCount++;
7556 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
7557 hcryp->CrypInCount++;
7558 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
7559 hcryp->CrypInCount++;
7560
7561 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
7562 {
7563 /* Call the input data transfer complete callback */
7564 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
7565 /*Call registered Input complete callback*/
7566 hcryp->InCpltCallback(hcryp);
7567 #else
7568 /*Call legacy Input complete callback*/
7569 HAL_CRYP_InCpltCallback(hcryp);
7570 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
7571 }
7572 }
7573 else /* Size < 4 words : first block is the last block*/
7574 {
7575 /* Compute the number of padding bytes in last block of payload */
7576 npblb = 16U - ((uint32_t)hcryp->Size);
7577 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
7578 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
7579 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
7580 {
7581 /* Specify the number of non-valid bytes using NPBLB register*/
7582 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
7583 }
7584
7585 /* Number of valid words (lastwordsize) in last block */
7586 if ((npblb % 4U) == 0U)
7587 {
7588 lastwordsize = (16U - npblb) / 4U;
7589 }
7590 else
7591 {
7592 lastwordsize = ((16U - npblb) / 4U) + 1U;
7593 }
7594
7595 /* Last block optionally pad the data with zeros*/
7596 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
7597 {
7598 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
7599 hcryp->CrypInCount++;
7600 }
7601 while (loopcounter < 4U)
7602 {
7603 /* Pad the data with zeros to have a complete block */
7604 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
7605 loopcounter++;
7606 }
7607 /* Call the input data transfer complete callback */
7608 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
7609 /*Call registered Input complete callback*/
7610 hcryp->InCpltCallback(hcryp);
7611 #else
7612 /*Call legacy Input complete callback*/
7613 HAL_CRYP_InCpltCallback(hcryp);
7614 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
7615 }
7616 }
7617 else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
7618 {
7619 /* Can enter full 4 header words */
7620 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
7621 /* If suspension flag has been raised, suspend processing
7622 only if not already at the end of the header */
7623 if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
7624 {
7625 /* Clear CCF Flag */
7626 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
7627
7628 /* reset SuspendRequest */
7629 hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
7630 /* Disable Computation Complete Flag and Errors Interrupts */
7631 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
7632 /* Change the CRYP state */
7633 hcryp->State = HAL_CRYP_STATE_SUSPENDED;
7634 /* Mark that the payload phase is suspended */
7635 hcryp->Phase = CRYP_PHASE_HEADER_SUSPENDED;
7636 __HAL_UNLOCK(hcryp);
7637 }
7638 else
7639 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
7640 {
7641 /* Write the input block in the IN FIFO */
7642 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7643 hcryp->CrypHeaderCount++;
7644 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7645 hcryp->CrypHeaderCount++;
7646 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7647 hcryp->CrypHeaderCount++;
7648 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7649 hcryp->CrypHeaderCount++;
7650 }
7651 }
7652 else /* Write last header block (4 words), padded with zeros if needed */
7653 {
7654 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
7655 {
7656 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7657 hcryp->CrypHeaderCount++ ;
7658 }
7659 /* If the header size is a multiple of words */
7660 if ((headersize_in_bytes % 4U) == 0U)
7661 {
7662 /* Pad the data with zeros to have a complete block */
7663 while (loopcounter < 4U)
7664 {
7665 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
7666 loopcounter++;
7667 hcryp->CrypHeaderCount++;
7668 }
7669 }
7670 else
7671 {
7672 /* Enter last bytes, padded with zeros */
7673 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7674 tmp &= mask[(SAES_CONV_DATATYPE(hcryp->Init.DataType) * 2U) + (headersize_in_bytes % 4U)];
7675 ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
7676 loopcounter++;
7677 hcryp->CrypHeaderCount++;
7678 /* Pad the data with zeros to have a complete block */
7679 while (loopcounter < 4U)
7680 {
7681 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
7682 loopcounter++;
7683 hcryp->CrypHeaderCount++;
7684 }
7685 }
7686 }
7687 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
7688 #endif /* USE_HAL_SAES_ONLY */
7689 }
7690
7691 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7692 /**
7693 * @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
7694 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7695 * the configuration information for CRYP module.
7696 * @param Timeout: Timeout duration.
7697 * @retval HAL status
7698 */
CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef * hcryp,uint32_t Timeout)7699 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7700 {
7701 uint32_t tickstart;
7702
7703 /* Get timeout */
7704 tickstart = HAL_GetTick();
7705
7706 while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_IFEM))
7707 {
7708 /* Check for the Timeout */
7709 if (Timeout != HAL_MAX_DELAY)
7710 {
7711 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7712 {
7713 return HAL_ERROR;
7714 }
7715 }
7716 }
7717 return HAL_OK;
7718 }
7719 #endif /* USE_HAL_CRYP_ONLY */
7720
7721 /**
7722 * @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
7723 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7724 * the configuration information for CRYP module.
7725 * @param Timeout: Timeout duration.
7726 * @retval HAL status
7727 */
CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef * hcryp,uint32_t Timeout)7728 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7729 {
7730 uint32_t tickstart;
7731 uint32_t flag_busy = 0U;
7732
7733 /* Get timeout */
7734 tickstart = HAL_GetTick();
7735
7736 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7737 if (IS_CRYP_INSTANCE(hcryp->Instance))
7738 {
7739 flag_busy = CRYP_FLAG_BUSY;
7740 }
7741 #endif /* USE_HAL_CRYP_ONLY */
7742 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7743 if (IS_SAES_INSTANCE(hcryp->Instance))
7744 {
7745 flag_busy = SAES_FLAG_BUSY;
7746 }
7747 #endif /* USE_HAL_SAES_ONLY */
7748 while (HAL_IS_BIT_SET(((CRYP_TypeDef *)(hcryp->Instance))->SR, flag_busy))
7749 {
7750 /* Check for the Timeout */
7751 if (Timeout != HAL_MAX_DELAY)
7752 {
7753 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7754 {
7755 return HAL_ERROR;
7756 }
7757 }
7758 }
7759 return HAL_OK;
7760 }
7761
7762 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7763 /**
7764 * @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
7765 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7766 * the configuration information for CRYP module.
7767 * @param Timeout: Timeout duration.
7768 * @retval HAL status
7769 */
CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef * hcryp,uint32_t Timeout)7770 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7771 {
7772 uint32_t tickstart;
7773
7774 /* Get timeout */
7775 tickstart = HAL_GetTick();
7776
7777 while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_OFNE))
7778 {
7779 /* Check for the Timeout */
7780 if (Timeout != HAL_MAX_DELAY)
7781 {
7782 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7783 {
7784 return HAL_ERROR;
7785 }
7786 }
7787 }
7788 return HAL_OK;
7789 }
7790 #endif /* USE_HAL_CRYP_ONLY */
7791
7792 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7793 /**
7794 * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
7795 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
7796 * the configuration information for CRYP module.
7797 * @param Timeout Timeout duration.
7798 * @retval HAL status
7799 */
CRYP_WaitOnCCFlag(const CRYP_HandleTypeDef * hcryp,uint32_t Timeout)7800 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7801 {
7802 uint32_t tickstart;
7803
7804 /* Get timeout */
7805 tickstart = HAL_GetTick();
7806
7807 while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF))
7808 {
7809 /* Check for the Timeout */
7810 if (Timeout != HAL_MAX_DELAY)
7811 {
7812 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7813 {
7814 return HAL_ERROR;
7815 }
7816 }
7817 }
7818 return HAL_OK;
7819 }
7820 #endif /* USE_HAL_SAES_ONLY */
7821
7822 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
7823 /**
7824 * @brief In case of message processing suspension, read the Initialization Vector.
7825 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
7826 * the configuration information for CRYP module.
7827 * @param Output Pointer to the buffer containing the saved Initialization Vector.
7828 * @note This value has to be stored for reuse by writing the AES_IVRx registers
7829 * as soon as the suspended processing has to be resumed.
7830 * @retval None
7831 */
CRYP_Read_IVRegisters(CRYP_HandleTypeDef * hcryp,uint32_t * Output)7832 static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output)
7833 {
7834 uint32_t outputaddr = (uint32_t)Output;
7835
7836 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7837 if (IS_CRYP_INSTANCE(hcryp->Instance))
7838 {
7839 *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR;
7840 outputaddr += 4U;
7841 *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR;
7842 outputaddr += 4U;
7843 *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR;
7844 outputaddr += 4U;
7845 *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR;
7846 }
7847 #endif /* USE_HAL_CRYP_ONLY */
7848 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7849 if (IS_SAES_INSTANCE(hcryp->Instance))
7850 {
7851 *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR3;
7852 outputaddr += 4U;
7853 *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR2;
7854 outputaddr += 4U;
7855 *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR1;
7856 outputaddr += 4U;
7857 *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR0;
7858 }
7859 #endif /* USE_HAL_SAES_ONLY */
7860 }
7861
7862 /**
7863 * @brief In case of GCM/GMAC/CCM processing resumption, rewrite the Initialization
7864 * Vector in the SAES_IVx registers.
7865 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
7866 * the configuration information for CRYP module.
7867 * @param Input Pointer to the buffer containing the saved Initialization Vector to
7868 * write back in the CRYP hardware block.
7869 * @note Applicable only to CRYP peripheral
7870 * @note CRYP must be disabled when reconfiguring the IV values.
7871 * @retval None
7872 */
CRYP_Write_IVRegisters(CRYP_HandleTypeDef * hcryp,uint32_t * Input)7873 static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input)
7874 {
7875 uint32_t ivaddr = (uint32_t)Input;
7876 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7877 if (IS_CRYP_INSTANCE(hcryp->Instance))
7878 {
7879 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(ivaddr);
7880 ivaddr += 4U;
7881 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(ivaddr);
7882 ivaddr += 4U;
7883 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(ivaddr);
7884 ivaddr += 4U;
7885 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(ivaddr);
7886 }
7887 #endif /* USE_HAL_CRYP_ONLY */
7888 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7889 if (IS_SAES_INSTANCE(hcryp->Instance))
7890 {
7891 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(ivaddr);
7892 ivaddr += 4U;
7893 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(ivaddr);
7894 ivaddr += 4U;
7895 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(ivaddr);
7896 ivaddr += 4U;
7897 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(ivaddr);
7898 }
7899 #endif /* USE_HAL_SAES_ONLY */
7900 }
7901
7902 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7903 /**
7904 * @brief In case of message GCM/GMAC/CCM processing suspension,
7905 * read the context swap Registers.
7906 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
7907 * the configuration information for CRYP module.
7908 * @param Output Pointer to the buffer containing the saved Suspend Registers.
7909 * @param Algorithm specifies whether CCM or GCM/GMAC is suspended.
7910 * @note These values have to be stored for reuse by writing back the CRYP_CSGCMCCMxR CRYP_CSGCMxR registers
7911 * as soon as the suspended processing has to be resumed.
7912 * @retval None
7913 */
CRYP_Read_ContextSwapRegisters(CRYP_HandleTypeDef * hcryp,uint32_t * Output,uint32_t Algorithm)7914 static void CRYP_Read_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t Algorithm)
7915 {
7916 uint32_t outputaddr = (uint32_t)Output;
7917 uint32_t inputaddr = (uint32_t)(&((CRYP_TypeDef *)(hcryp->Instance))->CSGCMCCM0R);
7918 uint32_t i;
7919
7920 for (i = 0; i < 8U; i++)
7921 {
7922 *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr);
7923 outputaddr += 4U;
7924 inputaddr += 4U;
7925 }
7926 if (Algorithm == CRYP_AES_GCM)
7927 {
7928 for (i = 0; i < 8U; i++)
7929 {
7930 *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr);
7931 outputaddr += 4U;
7932 inputaddr += 4U;
7933 }
7934 }
7935 }
7936 #endif /* USE_HAL_CRYP_ONLY */
7937
7938 /**
7939 * @brief In case of message GCM/GMAC/CCM processing resumption, rewrite the context swap registers.
7940 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
7941 * the configuration information for CRYP module.
7942 * @param Input Pointer to the buffer containing the saved suspend registers to
7943 * write back in the CRYP hardware block.
7944 * @param Algorithm specifies whether CCM or GCM/GMAC is suspended.
7945 * @note AES must be disabled when reconfiguring the suspend registers.
7946 * @retval None
7947 */
CRYP_Write_ContextSwapRegisters(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint32_t Algorithm)7948 static void CRYP_Write_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t Algorithm)
7949 {
7950 uint32_t inputaddr = (uint32_t)Input;
7951 uint32_t outputaddr = (uint32_t)(&((CRYP_TypeDef *)(hcryp->Instance))->CSGCMCCM0R);
7952 uint32_t i;
7953
7954 for (i = 0; i < 8U; i++)
7955 {
7956 *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr);
7957 outputaddr += 4U;
7958 inputaddr += 4U;
7959 }
7960 if (Algorithm == CRYP_AES_GCM)
7961 {
7962 for (i = 0; i < 8U; i++)
7963 {
7964 *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr);
7965 outputaddr += 4U;
7966 inputaddr += 4U;
7967 }
7968 }
7969 }
7970
7971 /**
7972 * @brief Authentication phase resumption in case of GCM/GMAC/CCM process in interrupt mode
7973 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
7974 * the configuration information for CRYP module(Header & HeaderSize)
7975 * @retval None
7976 */
CRYP_PhaseProcessingResume(CRYP_HandleTypeDef * hcryp)7977 static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
7978 {
7979 /* Case of header phase resumption =================================================*/
7980 if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED)
7981 {
7982 /* Set the phase */
7983 hcryp->Phase = CRYP_PHASE_PROCESS;
7984
7985 /* Select header phase */
7986 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7987 if (IS_CRYP_INSTANCE(hcryp->Instance))
7988 {
7989 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
7990 }
7991 #endif /* USE_HAL_CRYP_ONLY */
7992 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7993 if (IS_SAES_INSTANCE(hcryp->Instance))
7994 {
7995 SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
7996 }
7997 #endif /* USE_HAL_SAES_ONLY */
7998
7999 /* Enable interrupts */
8000 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
8001
8002 /* Enable CRYP */
8003 __HAL_CRYP_ENABLE(hcryp);
8004
8005 }
8006 /* Case of payload phase resumption =================================================*/
8007 else
8008 {
8009 /* Set the phase */
8010 hcryp->Phase = CRYP_PHASE_PROCESS;
8011
8012 /* Select payload phase once the header phase is performed */
8013 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
8014 if (IS_CRYP_INSTANCE(hcryp->Instance))
8015 {
8016 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
8017 }
8018 #endif /* USE_HAL_CRYP_ONLY */
8019 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
8020 if (IS_SAES_INSTANCE(hcryp->Instance))
8021 {
8022 SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
8023 }
8024 #endif /* USE_HAL_SAES_ONLY */
8025
8026 /* Enable Interrupts */
8027 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
8028
8029 /* Enable the CRYP peripheral */
8030 __HAL_CRYP_ENABLE(hcryp);
8031
8032 }
8033 }
8034
8035 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
8036
8037 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
8038 /*
8039 * @brief Adaptation needed do differentiate between CRYP and SAES CR_CHMOD fields
8040 * @param algo: corresponds to the algorithm to set
8041 * order: determines if conversion is done from CRYP to SAES and vice versa
8042 order = ALGOMODE_CRYP_TO_CHMOD_SAES means from algomode CRYP to chmod SAES
8043 order = ALGOMODE_SAES_TO_CHMOD_CRYP means from algomode SAES to chmod CRYP
8044 * @retval new_algo: correspond to the CR_CHMOD setting applied
8045 */
CRYP_SAES_AlgoConversion(uint32_t algo,uint32_t order)8046 static uint32_t CRYP_SAES_AlgoConversion(uint32_t algo, uint32_t order)
8047 {
8048 uint32_t new_algo = 0x0;
8049
8050 if (order == 0U) /* from algomode CRYP to chmod SAES */
8051 {
8052 switch (algo)
8053 {
8054 case CRYP_AES_ECB :
8055 new_algo = SAES_CR_CHMOD_AES_ECB;
8056 break;
8057 case CRYP_AES_CBC :
8058 new_algo = SAES_CR_CHMOD_AES_CBC;
8059 break;
8060 case CRYP_AES_CTR :
8061 new_algo = SAES_CR_CHMOD_AES_CTR;
8062 break;
8063 case CRYP_AES_GCM :
8064 new_algo = SAES_CR_CHMOD_AES_GCM;
8065 break;
8066 case CRYP_AES_CCM :
8067 new_algo = SAES_CR_CHMOD_AES_CCM;
8068 break;
8069 default :
8070 break;
8071 }
8072
8073 }
8074 else /* order == 1 , from chmod SAES to algomode CRYP */
8075 {
8076 switch (algo)
8077 {
8078 case SAES_CR_CHMOD_AES_ECB :
8079 new_algo = CRYP_AES_ECB;
8080 break;
8081 case SAES_CR_CHMOD_AES_CBC :
8082 new_algo = CRYP_AES_CBC;
8083 break;
8084 case SAES_CR_CHMOD_AES_CTR :
8085 new_algo = CRYP_AES_CTR;
8086 break;
8087 case SAES_CR_CHMOD_AES_GCM :
8088 new_algo = CRYP_AES_GCM;
8089 break;
8090 case SAES_CR_CHMOD_AES_CCM :
8091 new_algo = CRYP_AES_CCM;
8092 break;
8093 default :
8094 break;
8095 }
8096 }
8097
8098 return new_algo;
8099 }
8100 #endif /* USE_HAL_SAES_ONLY */
8101
8102 /**
8103 * @}
8104 */
8105
8106 /**
8107 * @}
8108 */
8109
8110 #endif /* HAL_CRYP_MODULE_ENABLED */
8111
8112
8113 /**
8114 * @}
8115 */
8116 #endif /* CRYP */
8117 /**
8118 * @}
8119 */
8120
