1 /**
2 ******************************************************************************
3 * @file stm32n6xx_hal.c
4 * @author MCD Application Team
5 * @brief HAL module driver.
6 * This is the common part of the HAL initialization
7 *
8 ******************************************************************************
9 * @attention
10 *
11 * Copyright (c) 2023 STMicroelectronics.
12 * All rights reserved.
13 *
14 * This software is licensed under terms that can be found in the LICENSE file
15 * in the root directory of this software component.
16 * If no LICENSE file comes with this software, it is provided AS-IS.
17 *
18 ******************************************************************************
19 @verbatim
20 ==============================================================================
21 ##### How to use this driver #####
22 ==============================================================================
23 [..]
24 The common HAL driver contains a set of generic and common APIs that can be
25 used by the PPP peripheral drivers and the user to start using the HAL.
26 [..]
27 The HAL contains two APIs' categories:
28 (+) Common HAL APIs
29 (+) Services HAL APIs
30 [..]
31 All the SYSCFG functions have the same privilege and security attributes.
32 (+) Functions can operate in non-privileged code should
33 privileged and unprivileged data access are granted to the
34 peripheral (see HAL_RIF_RISC_SetSlaveSecureAttributes)
35
36 (+) Functions can operate in non-secure code should
37 secure and non-secure data access are granted to the peripheral
38 (see HAL_RIF_RISC_SetSlaveSecureAttributes).
39
40 @endverbatim
41 ******************************************************************************
42 */
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32n6xx_hal.h"
46
47 /** @addtogroup STM32N6xx_HAL_Driver
48 * @{
49 */
50
51 /** @defgroup HAL HAL
52 * @brief HAL module driver
53 * @{
54 */
55
56 #ifdef HAL_MODULE_ENABLED
57
58 /* Private typedef -----------------------------------------------------------*/
59 /* Private define ------------------------------------------------------------*/
60 #define HAL_TIMEOUT_SYSCFG_ABORT 5U /* 5 ms */
61
62 /* Private macros ------------------------------------------------------------*/
63 /* Private variables ---------------------------------------------------------*/
64 /* Exported variables --------------------------------------------------------*/
65
66 /** @defgroup HAL_Exported_Variables HAL Exported Variables
67 * @{
68 */
69 __IO uint32_t uwTick;
70 uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
71 HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
72 /**
73 * @}
74 */
75
76 /* Private function prototypes -----------------------------------------------*/
77 /* Exported functions --------------------------------------------------------*/
78
79 /** @defgroup HAL_Exported_Functions HAL Exported Functions
80 * @{
81 */
82
83 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
84 * @brief Initialization and de-initialization functions
85 *
86 @verbatim
87 ===============================================================================
88 ##### Initialization and de-initialization functions #####
89 ===============================================================================
90 [..] This section provides functions allowing to:
91 (+) Initializes the NVIC allocation and initial clock configuration.
92 It initializes the systick also when timeout is needed
93 and the backup domain when enabled.
94 (+) De-Initializes common part of the HAL.
95 (+) Configure The time base source to have 1ms time base with a dedicated
96 Tick interrupt priority.
97 (++) SysTick timer is used by default as source of time base, but user
98 can eventually implement his proper time base source (a general purpose
99 timer for example or other time source), keeping in mind that Time base
100 duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
101 handled in milliseconds basis.
102 (++) Time base configuration function (HAL_InitTick ()) is called automatically
103 at the beginning of the program after reset by HAL_Init() or at any time
104 when clock is configured, by HAL_RCC_ClockConfig().
105 (++) Source of time base is configured to generate interrupts at regular
106 time intervals. Care must be taken if HAL_Delay() is called from a
107 peripheral ISR process, the Tick interrupt line must have higher priority
108 (numerically lower) than the peripheral interrupt. Otherwise the caller
109 ISR process will be blocked.
110 (++) functions affecting time base configurations are declared as __weak
111 to make override possible in case of other implementations in user file.
112 @endverbatim
113 * @{
114 */
115
116 /**
117 * @brief Configure the time base source, NVIC and any required global low
118 * level hardware by calling the HAL_MspInit() callback function to be optionally defined
119 * in user file stm32n6xx_hal_msp.c.
120 *
121 * @note HAL_Init() function is called at the beginning of program after reset and before
122 * the clock configuration.
123 *
124 * @note In the default implementation the System Timer (Systick) is used as source of time base.
125 * The Systick configuration is based on HSI clock, as HSI is the clock
126 * used after a system Reset and the NVIC configuration is set to Priority group 4.
127 * Once done, time base tick starts incrementing: the tick variable counter is incremented
128 * each 1ms in the SysTick_Handler() interrupt handler.
129 *
130 * @retval HAL status
131 */
HAL_Init(void)132 HAL_StatusTypeDef HAL_Init(void)
133 {
134 /* Set Interrupt Group Priority */
135 HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
136
137 /* Ensure time base clock coherency in SystemCoreClock global variable */
138 SystemCoreClockUpdate();
139
140 /* Initialize 1ms tick time base (default SysTick based on HSI clock after Reset) */
141 if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
142 {
143 return HAL_ERROR;
144 }
145
146 /* Init the low level hardware */
147 HAL_MspInit();
148
149 /* Return function status */
150 return HAL_OK;
151 }
152
153 /**
154 * @brief This function de-initializes all peripherals and low level hardware resources.
155 * @note This function should only be called from code running in internal RAM
156 * since it resets the external peripheral memory interfaces.
157 * @note This function is optional.
158 * @retval HAL status
159 */
HAL_DeInit(void)160 HAL_StatusTypeDef HAL_DeInit(void)
161 {
162 /* Reset of all peripherals */
163 __HAL_RCC_APB1_FORCE_RESET();
164 __HAL_RCC_APB1_RELEASE_RESET();
165
166 __HAL_RCC_APB2_FORCE_RESET();
167 __HAL_RCC_APB2_RELEASE_RESET();
168
169 __HAL_RCC_APB4_FORCE_RESET();
170 __HAL_RCC_APB4_RELEASE_RESET();
171
172 __HAL_RCC_APB5_FORCE_RESET();
173 __HAL_RCC_APB5_RELEASE_RESET();
174
175 __HAL_RCC_AHB1_FORCE_RESET();
176 __HAL_RCC_AHB1_RELEASE_RESET();
177
178 __HAL_RCC_AHB2_FORCE_RESET();
179 __HAL_RCC_AHB2_RELEASE_RESET();
180
181 __HAL_RCC_AHB3_FORCE_RESET();
182 __HAL_RCC_AHB3_RELEASE_RESET();
183
184 __HAL_RCC_AHB4_FORCE_RESET();
185 __HAL_RCC_AHB4_RELEASE_RESET();
186
187 __HAL_RCC_AHB5_FORCE_RESET();
188 __HAL_RCC_AHB5_RELEASE_RESET();
189
190 /* De-Init the low level hardware */
191 HAL_MspDeInit();
192
193 /* Return function status */
194 return HAL_OK;
195 }
196
197 /**
198 * @brief Initializes the MSP.
199 * @retval None
200 */
HAL_MspInit(void)201 __weak void HAL_MspInit(void)
202 {
203 /* NOTE : This function Should not be modified, when the callback is needed,
204 the HAL_MspInit could be implemented in the user file
205 */
206 }
207
208 /**
209 * @brief DeInitializes the MSP.
210 * @retval None
211 */
HAL_MspDeInit(void)212 __weak void HAL_MspDeInit(void)
213 {
214 /* NOTE : This function Should not be modified, when the callback is needed,
215 the HAL_MspDeInit could be implemented in the user file
216 */
217 }
218
219 /**
220 * @brief This function configures the source of the time base.
221 * The time source is configured to have 1ms time base with a dedicated
222 * Tick interrupt priority.
223 * @note This function is called automatically at the beginning of program after
224 * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
225 * @note In the default implementation, SysTick timer is the source of time base.
226 * It is used to generate interrupts at regular time intervals.
227 * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
228 * The SysTick interrupt must have higher priority (numerically lower)
229 * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
230 * The function is declared as __weak to be overwritten in case of other
231 * implementation in user file.
232 * @param TickPriority: Tick interrupt priority.
233 * @retval HAL status
234 */
HAL_InitTick(uint32_t TickPriority)235 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
236 {
237 /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
238 if ((uint32_t)uwTickFreq == 0UL)
239 {
240 return HAL_ERROR;
241 }
242
243 /* Configure the SysTick to have interrupt in 1ms time basis*/
244 if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
245 {
246 return HAL_ERROR;
247 }
248
249 /* Configure the SysTick IRQ priority */
250 if (TickPriority < (1UL << __NVIC_PRIO_BITS))
251 {
252 HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
253 uwTickPrio = TickPriority;
254 }
255 else
256 {
257 return HAL_ERROR;
258 }
259
260 /* Return function status */
261 return HAL_OK;
262 }
263
264 /**
265 * @}
266 */
267
268 /** @defgroup HAL_Group2 HAL Control functions
269 * @brief HAL Control functions
270 *
271 @verbatim
272 ===============================================================================
273 ##### HAL Control functions #####
274 ===============================================================================
275 [..] This section provides functions allowing to:
276 (+) Provide a tick value in millisecond
277 (+) Provide a blocking delay in millisecond
278 (+) Suspend the time base source interrupt
279 (+) Resume the time base source interrupt
280 (+) Get the HAL API driver version
281 (+) Get the device identifier
282 (+) Get the device revision identifier
283 (+) Enable/Disable Debug module during SLEEP mode
284 (+) Enable/Disable Debug module during STOP mode
285 (+) Enable/Disable Debug module during STANDBY mode
286
287 @endverbatim
288 * @{
289 */
290
291 /**
292 * @brief This function is called to increment a global variable "uwTick"
293 * used as application time base.
294 * @note In the default implementation, this variable is incremented each 1ms
295 * in Systick ISR.
296 * @note This function is declared as __weak to be overwritten in case of other
297 * implementations in user file.
298 * @retval None
299 */
HAL_IncTick(void)300 __weak void HAL_IncTick(void)
301 {
302 uwTick += (uint32_t)uwTickFreq;
303 }
304
305 /**
306 * @brief Provides a tick value in millisecond.
307 * @note This function is declared as __weak to be overwritten in case of other
308 * implementations in user file.
309 * @retval tick value
310 */
HAL_GetTick(void)311 __weak uint32_t HAL_GetTick(void)
312 {
313 return uwTick;
314 }
315
316 /**
317 * @brief This function returns a tick priority.
318 * @retval tick priority
319 */
HAL_GetTickPrio(void)320 uint32_t HAL_GetTickPrio(void)
321 {
322 return uwTickPrio;
323 }
324
325 /**
326 * @brief Set new tick Freq.
327 * @param Freq Tick frequency, value of @ref HAL_TickFreqTypeDef.
328 * @retval HAL status
329 */
HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)330 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
331 {
332 HAL_StatusTypeDef status = HAL_OK;
333 HAL_TickFreqTypeDef prevTickFreq;
334
335 assert_param(IS_TICKFREQ(Freq));
336
337 if (uwTickFreq != Freq)
338 {
339 /* Back up uwTickFreq frequency */
340 prevTickFreq = uwTickFreq;
341
342 /* Update uwTickFreq global variable used by HAL_InitTick() */
343 uwTickFreq = Freq;
344
345 /* Apply the new tick Freq */
346 status = HAL_InitTick(uwTickPrio);
347 if (status != HAL_OK)
348 {
349 /* Restore previous tick frequency */
350 uwTickFreq = prevTickFreq;
351 }
352 }
353
354 return status;
355 }
356
357 /**
358 * @brief Return tick frequency.
359 * @retval Tick frequency.
360 * Value of @ref HAL_TickFreqTypeDef.
361 */
HAL_GetTickFreq(void)362 HAL_TickFreqTypeDef HAL_GetTickFreq(void)
363 {
364 return uwTickFreq;
365 }
366
367 /**
368 * @brief This function provides minimum delay (in milliseconds) based
369 * on variable incremented.
370 * @note In the default implementation , SysTick timer is the source of time base.
371 * It is used to generate interrupts at regular time intervals where uwTick
372 * is incremented.
373 * @note This function is declared as __weak to be overwritten in case of other
374 * implementations in user file.
375 * @param Delay Specifies the delay time length, in milliseconds.
376 * @retval None
377 */
HAL_Delay(uint32_t Delay)378 __weak void HAL_Delay(uint32_t Delay)
379 {
380 uint32_t tickstart = HAL_GetTick();
381 uint32_t wait = Delay;
382
383 /* Add a freq to guarantee minimum wait */
384 if (wait < HAL_MAX_DELAY)
385 {
386 wait += (uint32_t)(uwTickFreq);
387 }
388
389 while ((HAL_GetTick() - tickstart) < wait)
390 {
391 }
392 }
393
394 /**
395 * @brief Suspend Tick increment.
396 * @note In the default implementation , SysTick timer is the source of time base. It is
397 * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
398 * is called, the SysTick interrupt will be disabled and so Tick increment
399 * is suspended.
400 * @note This function is declared as __weak to be overwritten in case of other
401 * implementations in user file.
402 * @retval None
403 */
HAL_SuspendTick(void)404 __weak void HAL_SuspendTick(void)
405 {
406 /* Disable SysTick Interrupt */
407 SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
408 }
409
410 /**
411 * @brief Resume Tick increment.
412 * @note In the default implementation , SysTick timer is the source of time base. It is
413 * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
414 * is called, the SysTick interrupt will be enabled and so Tick increment
415 * is resumed.
416 * @note This function is declared as __weak to be overwritten in case of other
417 * implementations in user file.
418 * @retval None
419 */
HAL_ResumeTick(void)420 __weak void HAL_ResumeTick(void)
421 {
422 /* Enable SysTick Interrupt */
423 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
424 }
425
426 /**
427 * @brief Returns the HAL revision
428 * @retval version : 0xXYZR (8bits for each decimal, R for RC)
429 */
HAL_GetHalVersion(void)430 uint32_t HAL_GetHalVersion(void)
431 {
432 return __STM32N6xx_HAL_VERSION;
433 }
434
435 #if defined(CPU_IN_SECURE_STATE)
436 /**
437 * @brief Returns the device revision identifier
438 * @note Returned Revision ID can be
439 * 0x00000100 for Cut1.0
440 * 0x00000101 for Cut1.1
441 * 0x00000200 for Cut2.0
442 * @retval Device revision identifier
443 */
HAL_GetREVID(void)444 uint32_t HAL_GetREVID(void)
445 {
446 return *(uint32_t *)(REVID_BASE);
447 }
448
449 /**
450 * @brief Returns the device identifier
451 * @note This function can only be used if the HAL BSEC module is enabled in the hal configuration file.
452 * The BSEC clock must be enabled before calling this function
453 * Returned Device ID can be
454 * 0x00006200 for STM32N645xx
455 * 0x00006000 for STM32N655xx
456 * 0x00002200 for STM32N647xx
457 * 0x00002000 for STM32N657xx
458 * 0xFFFFFFFF if an error occurs
459 * @retval Device identifier
460 */
HAL_GetDEVID(void)461 uint32_t HAL_GetDEVID(void)
462 {
463 #if defined(HAL_BSEC_MODULE_ENABLED)
464 #define BSEC_FUSE_ADDRESS 9U
465 uint32_t data;
466 if(__HAL_RCC_BSEC_IS_CLK_ENABLED() == 0UL){
467 data = 0xFFFFFFFFU;
468 }
469 else
470 {
471 BSEC_HandleTypeDef sBsecHandler = {0};
472 sBsecHandler.Instance = BSEC;
473
474 if(HAL_BSEC_OTP_Read(&sBsecHandler, BSEC_FUSE_ADDRESS, &data) != HAL_OK){
475 data = 0xFFFFFFFFU;
476 }
477 }
478 return data;
479 #else
480 return 0xFFFFFFFFU;
481 #endif /* HAL_BSEC_MODULE_ENABLED */
482 }
483 #endif /* CPU_IN_SECURE_STATE */
484
485 /**
486 * @brief Return the first word of the unique device identifier (UID based on 96 bits)
487 * @note The application must ensures that SYSCFG clock is enabled.
488 * @retval Device identifier
489 */
HAL_GetUIDw0(void)490 uint32_t HAL_GetUIDw0(void)
491 {
492 return (READ_REG(*((uint32_t *)UID_BASE)));
493 }
494
495 /**
496 * @brief Return the second word of the unique device identifier (UID based on 96 bits)
497 * @note The application must ensures that SYSCFG clock is enabled.
498 * @retval Device identifier
499 */
HAL_GetUIDw1(void)500 uint32_t HAL_GetUIDw1(void)
501 {
502 return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
503 }
504
505 /**
506 * @brief Return the third word of the unique device identifier (UID based on 96 bits)
507 * @note The application must ensures that SYSCFG clock is enabled.
508 * @retval Device identifier
509 */
HAL_GetUIDw2(void)510 uint32_t HAL_GetUIDw2(void)
511 {
512 return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
513 }
514
515 /**
516 * @}
517 */
518
519 /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
520 * @brief HAL Debug functions
521 *
522 @verbatim
523 ===============================================================================
524 ##### HAL Debug functions #####
525 ===============================================================================
526 [..] This section provides functions allowing to:
527 (+) Enable/Disable Debug module during Sleep mode
528 (+) Enable/Disable Debug module during Stop modes
529 (+) Enable/Disable Debug module during Stanby mode
530
531 @endverbatim
532 * @{
533 */
534
535 /**
536 * @brief Enable the Debug Module during Sleep mode.
537 * @retval None
538 */
HAL_DBGMCU_EnableDBGSleepMode(void)539 void HAL_DBGMCU_EnableDBGSleepMode(void)
540 {
541 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
542 }
543
544 /**
545 * @brief Disable the Debug Module during Sleep mode.
546 * @retval None
547 */
HAL_DBGMCU_DisableDBGSleepMode(void)548 void HAL_DBGMCU_DisableDBGSleepMode(void)
549 {
550 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
551 }
552
553 /**
554 * @brief Enable the Debug Module during Stop mode.
555 * @retval None
556 */
HAL_DBGMCU_EnableDBGStopMode(void)557 void HAL_DBGMCU_EnableDBGStopMode(void)
558 {
559 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
560 }
561
562 /**
563 * @brief Disable the Debug Module during Stop mode.
564 * @retval None
565 */
HAL_DBGMCU_DisableDBGStopMode(void)566 void HAL_DBGMCU_DisableDBGStopMode(void)
567 {
568 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
569 }
570
571 /**
572 * @brief Enable the Debug Module during Stanby mode.
573 * @retval None
574 */
HAL_DBGMCU_EnableDBGStandbyMode(void)575 void HAL_DBGMCU_EnableDBGStandbyMode(void)
576 {
577 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
578 }
579
580 /**
581 * @brief Disable the Debug Module during Stanby mode.
582 * @retval None
583 */
HAL_DBGMCU_DisableDBGStandbyMode(void)584 void HAL_DBGMCU_DisableDBGStandbyMode(void)
585 {
586 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
587 }
588
589 /**
590 * @}
591 */
592
593 /** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
594 * @brief HAL SYSCFG configuration functions
595 *
596 @verbatim
597 ===============================================================================
598 ##### HAL SYSCFG configuration functions #####
599 ===============================================================================
600 [..] This section provides functions allowing to:
601 (+) Enable or disable BOOT pins pull-down.
602 (+) Lock and get locks status of system items.
603 (+) Set (and get) TCM size and DTCM size.
604 (+) Lock (and get) write accesses.
605 (+) Enable or disable wait state on extended ITCM and DTCM.
606 (+) Enable or disable external RW margin input for TCM memories.
607 (+) Set and get the TCM biasing level.
608 (+) Enable or disable the external RW for caches memories.
609 (+) Set and get the cache biasing level.
610 (+) Enable or disable the Power-on reset upon SW system request.
611 (+) Enable or disable that Lockup requests a warm reset to the RCC
612 (+) Enable or disable that Lockup generates a NMI on the core
613 (+) Clear Error capture in write posting buffer
614 (+) Reserve VENCRAM for VENC or release it (any use allowed)
615 (+) Enable or disable PKA, SAES, CRYP1/2 and HASH reset in case of potential tamper
616 (+) Set/Get write/read Qos for NP1, NP2 or CPU.
617 (+) Enable or disable SDMMC early-write response.
618 (+) Enable or disable USB early-write response.
619 (+) Enable or disable the NPU NIC, NPU NOC or CPU NOC clock gating.
620 (+) Enable or disable the VDDIOx compensation cell.
621 (+) Configure or get VDDIOx compensation cells.
622 (+) Get VDDIOx compensation ready status.
623 (+) Enable or disable the VDD compensation cell.
624 (+) Configure or get VDD compensation cells.
625 (+) Configure or get the Timer Break input for error flag
626 (+) Set and get secure OS allocation of specific CID to the DMA channel
627 (+) Set and get non-secure OS allocation of specific CID to the DMA channel
628 (+) Enable or disable Retiming on RX path.
629 (+) Enable or disable Retiming on TX path.
630 (+) Set and get Delay on feedback clock.
631 (+) Enable or disable the interleaving on NPU RAM.
632 (+) Get BOOT pin connection status
633 (+) Get the address of first error in P-AHB write-posting buffer
634
635 @endverbatim
636 * @{
637 */
638
639 /**
640 * @brief Enable the Pull Down on BOOT pin.
641 * @param BootId Specifies the boot pins.
642 * This parameter can one of the following values:
643 * @arg SYSCFG_BOOT_0 boot 0 pin
644 * @arg SYSCFG_BOOT_1 boot 1 pin
645 * @retval None
646 */
HAL_SYSCFG_EnablePullDown(uint32_t BootId)647 void HAL_SYSCFG_EnablePullDown(uint32_t BootId)
648 {
649 /* Check the parameters */
650 assert_param(IS_SYSCFG_BOOT_ID(BootId));
651
652 SET_BIT(SYSCFG->BOOTCR, BootId);
653 }
654
655 /**
656 * @brief Disable the Pull Down on BOOT pin.
657 * @param BootId Specifies the boot pins.
658 * This parameter can one of the following values:
659 * @arg SYSCFG_BOOT_0 boot 0 pin
660 * @arg SYSCFG_BOOT_1 boot 1 pin
661 * @retval None
662 */
HAL_SYSCFG_DisablePullDown(uint32_t BootId)663 void HAL_SYSCFG_DisablePullDown(uint32_t BootId)
664 {
665 /* Check the parameters */
666 assert_param(IS_SYSCFG_BOOT_ID(BootId));
667
668 CLEAR_BIT(SYSCFG->BOOTCR, BootId);
669 }
670
671 /**
672 * @brief Lock the SYSCFG item(s).
673 * @note Lock(s) cleared only at system reset
674 * @param Item Item(s) to set lock on.
675 * This parameter can be a combination of @ref SYSCFG_Lock_items
676 * @retval None
677 */
HAL_SYSCFG_Lock(uint32_t Item)678 void HAL_SYSCFG_Lock(uint32_t Item)
679 {
680 /* Check the parameters */
681 assert_param(IS_SYSCFG_LOCK_ITEMS(Item));
682
683 MODIFY_REG(SYSCFG->CM55CR, SYSCFG_LOCK_ALL, Item);
684 }
685
686 /**
687 * @brief Get the lock state of SYSCFG item.
688 * @param pItem Pointer to return locked items
689 * the return value can be a combination of @ref SYSCFG_Lock_items
690 * @retval HAL status
691 */
HAL_SYSCFG_GetLock(uint32_t * pItem)692 HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem)
693 {
694 /* Check null pointer */
695 if (pItem == NULL)
696 {
697 return HAL_ERROR;
698 }
699
700 /* Get the non-secure lock state */
701 *pItem = READ_BIT(SYSCFG->CM55CR, SYSCFG_LOCK_ALL);
702
703 return HAL_OK;
704 }
705
706 /**
707 * @brief Set the DTCM and ITCM memory sizes.
708 * @note Write-once TCM configuration change.
709 * @note Effective change applied upon new power-on reset by calling
710 * HAL_SYSCFG_EnablePowerOnReset() and NVIC_SystemReset()
711 * @param DtcmSize DTCM memory size
712 * This parameter can one of the following values:
713 * @arg SYSCFG_DTCM_128K 128K
714 * @arg SYSCFG_DTCM_256K 256K
715 * @param ItcmSize ITCM memory size
716 * This parameter can one of the following values:
717 * @arg SYSCFG_ITCM_64K 64K
718 * @arg SYSCFG_ITCM_128K 128K
719 * @arg SYSCFG_ITCM_256K 256K
720 * @retval None
721 */
HAL_SYSCFG_SetTCMSize(uint32_t DtcmSize,uint32_t ItcmSize)722 void HAL_SYSCFG_SetTCMSize(uint32_t DtcmSize, uint32_t ItcmSize)
723 {
724 /* Check the parameters */
725 assert_param(IS_SYSCFG_DTCM_SIZE(DtcmSize));
726 assert_param(IS_SYSCFG_ITCM_SIZE(ItcmSize));
727
728 MODIFY_REG(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_CFGDTCMSZ | SYSCFG_CM55TCMCR_CFGITCMSZ, DtcmSize | ItcmSize);
729 }
730
731 /**
732 * @brief Get the DTCM and ITCM memory sizes.
733 * @param pDtcmSize Pointer to return DTCM memory size
734 * This return value can be one of
735 * @arg SYSCFG_DTCM_128K 128K
736 * @arg SYSCFG_DTCM_256K 256K
737 * @param pItcmSize Pointer to return ITCM memory size
738 * This return value can be one of
739 * @arg SYSCFG_ITCM_64K 64K
740 * @arg SYSCFG_ITCM_128K 128K
741 * @arg SYSCFG_ITCM_256K 256K
742 * @retval HAL status
743 */
HAL_SYSCFG_GetTCMSize(uint32_t * pDtcmSize,uint32_t * pItcmSize)744 HAL_StatusTypeDef HAL_SYSCFG_GetTCMSize(uint32_t *pDtcmSize, uint32_t *pItcmSize)
745 {
746 uint32_t values;
747
748 /* Check null pointer */
749 if ((pDtcmSize == NULL) || (pItcmSize == NULL))
750 {
751 return HAL_ERROR;
752 }
753
754 values = READ_REG(SYSCFG->CM55TCMCR);
755 *pDtcmSize = (values & 0xF0U);
756 *pItcmSize = (values & 0xFU);
757
758 return HAL_OK;
759 }
760
761 /**
762 * @brief Lock the SYSCFG write access item(s).
763 * @note Lock(s) cleared only at system reset
764 * @param Item Item(s) to set lock on.
765 * This parameter can be a combination of @ref SYSCFG_WRITE_access
766 * @retval None
767 */
HAL_SYSCFG_LockWriteAccess(uint32_t Item)768 void HAL_SYSCFG_LockWriteAccess(uint32_t Item)
769 {
770 /* Check the parameters */
771 assert_param(IS_SYSCFG_LOCK_WRACCESS(Item));
772
773 MODIFY_REG(SYSCFG->CM55TCMCR, SYSCFG_LOCK_WR_ALL, Item);
774 }
775
776 /**
777 * @brief Get the lock state of SYSCFG write access item.
778 * @param pItem pointer to return locked items
779 * the return value can be a combination of @ref SYSCFG_WRITE_access
780 * @retval HAL status
781 */
HAL_SYSCFG_GetLockWriteAccess(uint32_t * pItem)782 HAL_StatusTypeDef HAL_SYSCFG_GetLockWriteAccess(uint32_t *pItem)
783 {
784 /* Check null pointer */
785 if (pItem == NULL)
786 {
787 return HAL_ERROR;
788 }
789
790 /* Get the non-secure lock state */
791 *pItem = READ_BIT(SYSCFG->CM55TCMCR, SYSCFG_LOCK_WR_ALL);
792
793 return HAL_OK;
794 }
795
796 /**
797 * @brief Enable the ITCM Wait State.
798 * @retval None
799 */
HAL_SYSCFG_EnableITCMWaiteState(void)800 void HAL_SYSCFG_EnableITCMWaiteState(void)
801 {
802 SET_BIT(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_ITCMWSDISABLE);
803 }
804
805 /**
806 * @brief Disable the ITCM Wait State.
807 * @retval None
808 */
HAL_SYSCFG_DisableITCMWaiteState(void)809 void HAL_SYSCFG_DisableITCMWaiteState(void)
810 {
811 CLEAR_BIT(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_ITCMWSDISABLE);
812 }
813
814 /**
815 * @brief Enable the DTCM Wait State.
816 * @retval None
817 */
HAL_SYSCFG_EnableDTCMWaiteState(void)818 void HAL_SYSCFG_EnableDTCMWaiteState(void)
819 {
820 SET_BIT(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_DTCMWSDISABLE);
821 }
822
823 /**
824 * @brief Disable the DTCM Wait State.
825 * @retval None
826 */
HAL_SYSCFG_DisableDTCMWaiteState(void)827 void HAL_SYSCFG_DisableDTCMWaiteState(void)
828 {
829 CLEAR_BIT(SYSCFG->CM55TCMCR, SYSCFG_CM55TCMCR_DTCMWSDISABLE);
830 }
831
832 /**
833 * @brief Enable external RW margin inputs for TCM memories
834 * @retval None
835 */
HAL_SYSCFG_EnableTCMExternalMargin(void)836 void HAL_SYSCFG_EnableTCMExternalMargin(void)
837 {
838 SET_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RME_TCM);
839 }
840
841 /**
842 * @brief Disable external RW margin inputs for TCM memories
843 * @retval None
844 */
HAL_SYSCFG_DisableTCMExternalMargin(void)845 void HAL_SYSCFG_DisableTCMExternalMargin(void)
846 {
847 CLEAR_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RME_TCM);
848 }
849
850 /**
851 * @brief Set external RW margin inputs for TCM memories.
852 * @param TcmRwMarginInput Input Margin.
853 * @retval None
854 */
HAL_SYSCFG_SetTCMRWMarginInput(uint32_t TcmRwMarginInput)855 void HAL_SYSCFG_SetTCMRWMarginInput(uint32_t TcmRwMarginInput)
856 {
857 assert_param(IS_TCM_MARGIN_INPUT(TcmRwMarginInput));
858
859 MODIFY_REG(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RM_TCM, (TcmRwMarginInput << 1U));
860 }
861
862 /**
863 * @brief Get the External RW margin inputs for TCM memories.
864 * @param pTcmRwMarginInput pointer to return Input Margin.
865 * @retval HAL status.
866 */
HAL_SYSCFG_GetTCMRWMarginInput(uint32_t * pTcmRwMarginInput)867 HAL_StatusTypeDef HAL_SYSCFG_GetTCMRWMarginInput(uint32_t *pTcmRwMarginInput)
868 {
869 /* Check null pointer */
870 if (pTcmRwMarginInput == NULL)
871 {
872 return HAL_ERROR;
873 }
874
875 /* Get the non-secure lock state */
876 *pTcmRwMarginInput = (READ_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RM_TCM) >> 1U);
877
878 return HAL_OK;
879 }
880
881 /**
882 * @brief Set the TCM biasing level adjust input.
883 * @param Level Biaising level adjust input
884 * This parameter can one of the following values:
885 * @arg SYSCFG_TCM_BIAS_VNOM : Biasing level adjust input recommended for Vnom
886 * @arg SYSCFG_TCM_BIAS_VNOM_10_PERCENT : Biasing level adjust input recommended for Vnom + 10%
887 * @retval None
888 */
HAL_SYSCFG_SetTCMBiasingLevel(uint32_t Level)889 void HAL_SYSCFG_SetTCMBiasingLevel(uint32_t Level)
890 {
891 /* Check the parameters */
892 assert_param(IS_SYSCFG_TCM_BIASING_LEVEL(Level));
893
894 MODIFY_REG(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_BC2_TCM | SYSCFG_CM55RWMCR_BC1_TCM, Level);
895 }
896
897 /**
898 * @brief Get the TCM biasing level adjust input.
899 * @param pLevel Pointer to return biasing level adjust input.
900 * The return value can be one of the following values:
901 * @arg SYSCFG_CACHE_BIAS_VNOM boot 0 pin: Biasing level adjust input recommended for Vnom
902 * @arg SYSCFG_CACHE_BIAS_VNOM_10_PERCENT: Biasing level adjust input recommended for Vnom + 10%
903 * @retval HAL status
904 */
HAL_SYSCFG_GetTCMBiasingLevel(uint32_t * pLevel)905 HAL_StatusTypeDef HAL_SYSCFG_GetTCMBiasingLevel(uint32_t *pLevel)
906 {
907 /* Check null pointer */
908 if (pLevel == NULL)
909 {
910 return HAL_ERROR;
911 }
912
913 /* Get the non-secure lock state */
914 *pLevel = READ_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_BC2_TCM | SYSCFG_CM55RWMCR_BC1_TCM);
915
916 return HAL_OK;
917 }
918
919 /**
920 * @brief Enable external RW margin inputs for Cache memories
921 * @retval None
922 */
HAL_SYSCFG_EnableCacheExternalMargin(void)923 void HAL_SYSCFG_EnableCacheExternalMargin(void)
924 {
925 SET_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RME_CACHE);
926 }
927
928 /**
929 * @brief Disable external RW margin inputs for Cache memories
930 * @retval None
931 */
HAL_SYSCFG_DisableCacheExternalMargin(void)932 void HAL_SYSCFG_DisableCacheExternalMargin(void)
933 {
934 CLEAR_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RME_CACHE);
935 }
936
937 /**
938 * @brief Set External RW margin inputs for Cache memories.
939 * @param CacheRWMarginInput Input Margin.
940 * @retval None
941 */
HAL_SYSCFG_SetCacheRWMarginInput(uint32_t CacheRWMarginInput)942 void HAL_SYSCFG_SetCacheRWMarginInput(uint32_t CacheRWMarginInput)
943 {
944 assert_param(IS_TCM_MARGIN_INPUT(CacheRWMarginInput));
945
946 MODIFY_REG(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RM_CACHE, (CacheRWMarginInput << 8U));
947 }
948
949 /**
950 * @brief Get the External RW margin inputs for Cache memories.
951 * @param pCacheRWMarginInput Pointer to return Input Margin.
952 * @retval HAL status
953 */
HAL_SYSCFG_GetCacheRWMarginInput(uint32_t * pCacheRWMarginInput)954 HAL_StatusTypeDef HAL_SYSCFG_GetCacheRWMarginInput(uint32_t *pCacheRWMarginInput)
955 {
956 /* Check null pointer */
957 if (pCacheRWMarginInput == NULL)
958 {
959 return HAL_ERROR;
960 }
961
962 /* Get the non-secure lock state */
963 *pCacheRWMarginInput = (READ_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_RM_CACHE) >> 8U);
964
965 return HAL_OK;
966 }
967
968 /**
969 * @brief Set the Cache biasing level adjust input.
970 * @param Level the biaising level adjust input
971 * This parameter can one of the following values:
972 * @arg SYSCFG_CACHE_BIAS_VNOM: Biasing level adjust input recommended for Vnom
973 * @arg SYSCFG_CACHE_BIAS_VNOM_10_PERCENT: Biasing level adjust input recommended for Vnom + 10%
974 * @retval None
975 */
HAL_SYSCFG_SetCacheBiasingLevel(uint32_t Level)976 void HAL_SYSCFG_SetCacheBiasingLevel(uint32_t Level)
977 {
978 /* Check the parameters */
979 assert_param(IS_SYSCFG_CACHE_BIASING_LEVEL(Level));
980
981 MODIFY_REG(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_BC2_CACHE | SYSCFG_CM55RWMCR_BC1_CACHE, Level);
982 }
983
984 /**
985 * @brief Get the Cache biasing level adjust input.
986 * @param pLevel Pointer to return Cache biasing level adjust input.
987 * The return value can be onr of the following values:
988 * @arg SYSCFG_CACHE_BIAS_VNOM boot: Biasing level adjust input recommended for Vnom
989 * @arg SYSCFG_CACHE_BIAS_VNOM_10_PERCENT: Biasing level adjust input recommended for Vnom + 10%
990 * @retval HAL status
991 */
HAL_SYSCFG_GetCacheBiasingLevel(uint32_t * pLevel)992 HAL_StatusTypeDef HAL_SYSCFG_GetCacheBiasingLevel(uint32_t *pLevel)
993 {
994 /* Check null pointer */
995 if (pLevel == NULL)
996 {
997 return HAL_ERROR;
998 }
999
1000 /* Get the cache biaising */
1001 *pLevel = READ_BIT(SYSCFG->CM55RWMCR, SYSCFG_CM55RWMCR_BC2_CACHE | SYSCFG_CM55RWMCR_BC1_CACHE);
1002
1003 return HAL_OK;
1004 }
1005
1006 /**
1007 * @brief Set the secure vector table (VTOR) address.
1008 * @note Secure vector table address must be set to ensure return from STANDBY state.
1009 * @param Address Secure VTOR address
1010 * @retval None
1011 */
HAL_SYSCFG_SetSVTORAddress(uint32_t Address)1012 void HAL_SYSCFG_SetSVTORAddress(uint32_t Address)
1013 {
1014 /* Check the parameters */
1015 assert_param(IS_VTOR_ADDRESS(Address));
1016
1017 WRITE_REG(SYSCFG->INITSVTORCR, Address);
1018 }
1019
1020 /**
1021 * @brief Get the secure vector table (VTOR) address.
1022 * @param pAddress Pointer to return the secure vector table address
1023 * @retval HAL status
1024 */
HAL_SYSCFG_GetSVTORAddress(uint32_t * pAddress)1025 HAL_StatusTypeDef HAL_SYSCFG_GetSVTORAddress(uint32_t *pAddress)
1026 {
1027 /* Check null pointer */
1028 if (pAddress == NULL)
1029 {
1030 return HAL_ERROR;
1031 }
1032
1033 /* Get the secure VTOR address */
1034 *pAddress = READ_REG(SYSCFG->INITSVTORCR);
1035
1036 return HAL_OK;
1037 }
1038
1039 /**
1040 * @brief Set the non secure vector table (VTOR) address.
1041 * @param Address Non-secure VTOR address
1042 * @retval None
1043 */
HAL_SYSCFG_SetNSVTORAddress(uint32_t Address)1044 void HAL_SYSCFG_SetNSVTORAddress(uint32_t Address)
1045 {
1046 /* Check the parameters */
1047 assert_param(IS_VTOR_ADDRESS(Address));
1048
1049 WRITE_REG(SYSCFG->INITNSVTORCR, Address);
1050 }
1051
1052 /**
1053 * @brief Get the non secure VTOR address.
1054 * @param pAddress Pointer to return the non-secure vector table address
1055 * @retval HAL status
1056 */
HAL_SYSCFG_GetNSVTORAddress(uint32_t * pAddress)1057 HAL_StatusTypeDef HAL_SYSCFG_GetNSVTORAddress(uint32_t *pAddress)
1058 {
1059 /* Check null pointer */
1060 if (pAddress == NULL)
1061 {
1062 return HAL_ERROR;
1063 }
1064
1065 /* Get the non-secure VTOR address */
1066 *pAddress = READ_REG(SYSCFG->INITNSVTORCR);
1067
1068 return HAL_OK;
1069 }
1070
1071 /**
1072 * @brief Enable the Power-on reset.
1073 * @note Select power-on reset to apply on core upon SYSRESETREQ (NVIC_SystemReset())
1074 * @retval None
1075 */
HAL_SYSCFG_EnablePowerOnReset(void)1076 void HAL_SYSCFG_EnablePowerOnReset(void)
1077 {
1078 SET_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_CORE_RESET_TYPE);
1079 }
1080
1081 /**
1082 * @brief Disable the Power-on reset.
1083 * @note Select warm reset to apply on core upon SYSRESETREQ (NVIC_SystemReset())
1084 * @retval None
1085 */
HAL_SYSCFG_DisablePowerOnReset(void)1086 void HAL_SYSCFG_DisablePowerOnReset(void)
1087 {
1088 CLEAR_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_CORE_RESET_TYPE);
1089 }
1090
1091 /**
1092 * @brief Enable Lockup requests a warm reset to the RCC.
1093 * @note Select action to perform on a lockup state on the core
1094 * @retval None
1095 */
HAL_SYSCFG_EnableLockupWarmResetonRCC(void)1096 void HAL_SYSCFG_EnableLockupWarmResetonRCC(void)
1097 {
1098 SET_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_LOCKUP_RST_EN);
1099 }
1100
1101 /**
1102 * @brief Disable Lockup requests a warm reset to the RCC.
1103 * @note Select action to perform on a lockup state on the core
1104 * @retval None
1105 */
HAL_SYSCFG_DisableLockupWarmResetonRCC(void)1106 void HAL_SYSCFG_DisableLockupWarmResetonRCC(void)
1107 {
1108 CLEAR_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_LOCKUP_RST_EN);
1109 }
1110
1111 /**
1112 * @brief Enable Lockup generates a NMI on the core.
1113 * @note Select action to perform on a lockup state on the core
1114 * @retval None
1115 */
HAL_SYSCFG_EnableLockupGenerateNMI(void)1116 void HAL_SYSCFG_EnableLockupGenerateNMI(void)
1117 {
1118 SET_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_LOCKUP_NMI_EN);
1119 }
1120
1121 /**
1122 * @brief Disable Lockup generates a NMI on the core.
1123 * @note Select action to perform on a lockup state on the core
1124 * @retval None
1125 */
HAL_SYSCFG_DisableLockupGenerateNMI(void)1126 void HAL_SYSCFG_DisableLockupGenerateNMI(void)
1127 {
1128 CLEAR_BIT(SYSCFG->CM55RSTCR, SYSCFG_CM55RSTCR_LOCKUP_NMI_EN);
1129 }
1130
1131 /**
1132 * @brief Enable the capture mechanism upon write posting buffer error.
1133 * @note Upon error detection, the erroneous address is logged on and
1134 * the capture mechanism is on hold.
1135 * The address error can be read thanks to
1136 * HAL_SYSCFG_GetAddressWritePostingBuffer.
1137 * @note This function enables the error capture mechanism again.
1138 * @retval HAL status.
1139 */
HAL_SYSCFG_ReEnableWritePostingErrorCapture(void)1140 HAL_StatusTypeDef HAL_SYSCFG_ReEnableWritePostingErrorCapture(void)
1141 {
1142 /* Re-enable HW write posting detection mechanism */
1143 SET_BIT(SYSCFG->CM55PAHBWPR, SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK);
1144
1145 CLEAR_BIT(SYSCFG->CM55PAHBWPR, SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK);
1146
1147 return HAL_OK;
1148 }
1149
1150 #if defined(VENC)
1151 /**
1152 * @brief Reserve the VENCRAM allocation to VENC.
1153 * @retval None
1154 */
HAL_SYSCFG_EnableVENCRAMReserved(void)1155 void HAL_SYSCFG_EnableVENCRAMReserved(void)
1156 {
1157 CLEAR_BIT(SYSCFG->VENCRAMCR, SYSCFG_VENCRAMCR_VENCRAM_EN);
1158 }
1159
1160 /**
1161 * @brief Release the VENCRAM allocation to VENC (any use allowed).
1162 * @retval None
1163 */
HAL_SYSCFG_DisableVENCRAMReserved(void)1164 void HAL_SYSCFG_DisableVENCRAMReserved(void)
1165 {
1166 SET_BIT(SYSCFG->VENCRAMCR, SYSCFG_VENCRAMCR_VENCRAM_EN);
1167 }
1168
1169 #endif /* VENC */
1170
1171 /**
1172 * @brief Enable PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper
1173 * @retval None
1174 */
HAL_SYSCFG_EnableCRYPPotentialTamper(void)1175 void HAL_SYSCFG_EnableCRYPPotentialTamper(void)
1176 {
1177 CLEAR_BIT(SYSCFG->POTTAMPRSTCR, SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK);
1178 }
1179
1180 /**
1181 * @brief Disable PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper
1182 * @retval None
1183 */
HAL_SYSCFG_DisableCRYPPotentialTamper(void)1184 void HAL_SYSCFG_DisableCRYPPotentialTamper(void)
1185 {
1186 SET_BIT(SYSCFG->POTTAMPRSTCR, SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK);
1187 }
1188
1189 #if defined(SYSCFG_NPUNICQOSCR_NPU1_ARQOSR)
1190 /**
1191 * @brief Set write QoS information for master port from NP1 NPUNIC
1192 * @param QosValue Write QoS value (0 to 15).
1193 * @retval None
1194 */
HAL_SYSCFG_SetWriteQosNP1(uint32_t QosValue)1195 void HAL_SYSCFG_SetWriteQosNP1(uint32_t QosValue)
1196 {
1197 /* Check the parameters */
1198 assert_param(IS_SYSCFG_QOS_CPU(QosValue));
1199
1200 MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU1_ARQOSW, QosValue << 4U);
1201 }
1202
1203 /**
1204 * @brief Get write QoS information for master port from NP1 NPUNIC
1205 * @param pQosValue Pointer to return write QOS value (0 to 15)
1206 * @retval HAL status
1207 */
1208
HAL_SYSCFG_GetWriteQosNP1(uint32_t * pQosValue)1209 HAL_StatusTypeDef HAL_SYSCFG_GetWriteQosNP1(uint32_t *pQosValue)
1210 {
1211 /* Check null pointer */
1212 if (pQosValue == NULL)
1213 {
1214 return HAL_ERROR;
1215 }
1216
1217 /* Get the QOS */
1218 *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU1_ARQOSW) >> 4U);
1219
1220 return HAL_OK;
1221 }
1222
1223 /**
1224 * @brief Set read QoS information for master port from NP1 NPUNIC
1225 * @param QosValue Read QoS value (0 to 15)
1226 * @retval None
1227 */
HAL_SYSCFG_SetReadQosNP1(uint32_t QosValue)1228 void HAL_SYSCFG_SetReadQosNP1(uint32_t QosValue)
1229 {
1230 /* Check the parameters */
1231 assert_param(IS_SYSCFG_QOS_CPU(QosValue));
1232
1233 MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU1_ARQOSR, QosValue);
1234 }
1235
1236 /**
1237 * @brief Get read QoS information for master port from NP1 NPUNIC
1238 * @param pQosValue Pointer to return read QOS value (0 to 15)
1239 * @retval HAL status
1240 */
HAL_SYSCFG_GetReadQosNP1(uint32_t * pQosValue)1241 HAL_StatusTypeDef HAL_SYSCFG_GetReadQosNP1(uint32_t *pQosValue)
1242 {
1243 /* Check null pointer */
1244 if (pQosValue == NULL)
1245 {
1246 return HAL_ERROR;
1247 }
1248
1249 /* Get the QOS */
1250 *pQosValue = READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU1_ARQOSR);
1251
1252 return HAL_OK;
1253 }
1254
1255 /**
1256 * @brief Set write QoS information for master port from NP2 NPUNIC
1257 * @param QosValue Write Qos value (0 to 15)
1258 * @retval None
1259 */
HAL_SYSCFG_SetWriteQosNP2(uint32_t QosValue)1260 void HAL_SYSCFG_SetWriteQosNP2(uint32_t QosValue)
1261 {
1262 /* Check the parameters */
1263 assert_param(IS_SYSCFG_QOS_CPU(QosValue));
1264
1265 MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU2_ARQOSW, QosValue << 12U);
1266 }
1267
1268 /**
1269 * @brief Get write QoS information for master port from NP2 NPUNIC
1270 * @param pQosValue Pointer to return write QOS value (0 to 15)
1271 * @retval HAL status
1272 */
HAL_SYSCFG_GetWriteQosNP2(uint32_t * pQosValue)1273 HAL_StatusTypeDef HAL_SYSCFG_GetWriteQosNP2(uint32_t *pQosValue)
1274 {
1275 /* Check null pointer */
1276 if (pQosValue == NULL)
1277 {
1278 return HAL_ERROR;
1279 }
1280
1281 /* Get the QOS */
1282 *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU2_ARQOSW) >> 12U);
1283
1284 return HAL_OK;
1285 }
1286
1287 /**
1288 * @brief Set read QoS information for master port from NP2 NPUNIC
1289 * @param QosValue Read Qos value (0 to 15)
1290 * @retval None
1291 */
HAL_SYSCFG_SetReadQosNP2(uint32_t QosValue)1292 void HAL_SYSCFG_SetReadQosNP2(uint32_t QosValue)
1293 {
1294 /* Check the parameters */
1295 assert_param(IS_SYSCFG_QOS_CPU(QosValue));
1296
1297 MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU2_ARQOSR, QosValue << 8U);
1298 }
1299
1300 /**
1301 * @brief Get read QoS information for master port from NP2 NPUNIC
1302 * @param pQosValue Pointer to return read QOS value (0 to 15)
1303 * @retval HAL status
1304 */
HAL_SYSCFG_GetReadQosNP2(uint32_t * pQosValue)1305 HAL_StatusTypeDef HAL_SYSCFG_GetReadQosNP2(uint32_t *pQosValue)
1306 {
1307 /* Check null pointer */
1308 if (pQosValue == NULL)
1309 {
1310 return HAL_ERROR;
1311 }
1312
1313 /* Get the QOS */
1314 *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_NPU2_ARQOSR) >> 8U);
1315
1316 return HAL_OK;
1317 }
1318
1319 /**
1320 * @brief Set write QoS information for master port from CPUSS NPUNIC
1321 * @param QosValue Write QoS value (0 to 15)
1322 * @retval None
1323 */
HAL_SYSCFG_SetWriteQosCPUSS(uint32_t QosValue)1324 void HAL_SYSCFG_SetWriteQosCPUSS(uint32_t QosValue)
1325 {
1326 /* Check the parameters */
1327 assert_param(IS_SYSCFG_QOS_CPU(QosValue));
1328
1329 MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW, QosValue << 20U);
1330 }
1331
1332 /**
1333 * @brief Get write QoS information for master port from CPUSS NPUNIC
1334 * @param pQosValue Pointer to return write QOS value (0 to 15)
1335 * @retval HAL status
1336 */
HAL_SYSCFG_GetwriteQosCPUSS(uint32_t * pQosValue)1337 HAL_StatusTypeDef HAL_SYSCFG_GetwriteQosCPUSS(uint32_t *pQosValue)
1338 {
1339 /* Check null pointer */
1340 if (pQosValue == NULL)
1341 {
1342 return HAL_ERROR;
1343 }
1344
1345 /* Get the QOS */
1346 *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW) >> 20U);
1347
1348 return HAL_OK;
1349 }
1350
1351 /**
1352 * @brief Set read QoS information for master port from CPUSS NPUNIC
1353 * @param QosValue Read QoS value (0 to 15)
1354 * @retval None
1355 */
HAL_SYSCFG_SetReadQosCPUSS(uint32_t QosValue)1356 void HAL_SYSCFG_SetReadQosCPUSS(uint32_t QosValue)
1357 {
1358 /* Check the parameters */
1359 assert_param(IS_SYSCFG_QOS_CPU(QosValue));
1360
1361 MODIFY_REG(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR, QosValue << 16U);
1362 }
1363
1364 /**
1365 * @brief Get read QoS information for master port from CPUSS NPUNIC
1366 * @param pQosValue Pointer to return read QOS value (0 to 15)
1367 * @retval HAL status
1368 */
HAL_SYSCFG_GetReadQosCPUSS(uint32_t * pQosValue)1369 HAL_StatusTypeDef HAL_SYSCFG_GetReadQosCPUSS(uint32_t *pQosValue)
1370 {
1371 /* Check null pointer */
1372 if (pQosValue == NULL)
1373 {
1374 return HAL_ERROR;
1375 }
1376
1377 /* Get the QOS */
1378 *pQosValue = (READ_BIT(SYSCFG->NPUNICQOSCR, SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR) >> 16U);
1379
1380 return HAL_OK;
1381 }
1382 #endif /* defined(SYSCFG_NPUNICQOSCR_NPU1_ARQOSR) */
1383
1384 /**
1385 * @brief Enable SDMMC early-write response.
1386 * @param Sdmmc Selected SDMMC instance(s).
1387 * This parameter can be a one of @ref SYSCFG_SDMMCId
1388 * @retval None
1389 */
HAL_SYSCFG_EnableSDMMCEarlyWRRESP(uint32_t Sdmmc)1390 void HAL_SYSCFG_EnableSDMMCEarlyWRRESP(uint32_t Sdmmc)
1391 {
1392 /* Check the parameters */
1393 assert_param(IS_SYSCFG_SDMMC(Sdmmc));
1394
1395 SET_BIT(SYSCFG->ICNEWRCR, Sdmmc);
1396 }
1397
1398 /**
1399 * @brief Disable SDMMC early-write response.
1400 * @param Sdmmc Selected SDMMC instance(s).
1401 * This parameter can be a one of @ref SYSCFG_SDMMCId
1402 * @retval None
1403 */
HAL_SYSCFG_DisableSDMMCEarlyWRRSP(uint32_t Sdmmc)1404 void HAL_SYSCFG_DisableSDMMCEarlyWRRSP(uint32_t Sdmmc)
1405 {
1406 /* Check the parameters */
1407 assert_param(IS_SYSCFG_SDMMC(Sdmmc));
1408
1409 CLEAR_BIT(SYSCFG->ICNEWRCR, Sdmmc);
1410 }
1411
1412 /**
1413 * @brief Enable USB early-write response.
1414 * @param Usb Selected USB instance(s).
1415 * This parameter can be a one of @ref SYSCFG_USBId
1416 * @retval None
1417 */
HAL_SYSCFG_EnableUSBEarlyEarlyWRRESP(uint32_t Usb)1418 void HAL_SYSCFG_EnableUSBEarlyEarlyWRRESP(uint32_t Usb)
1419 {
1420 /* Check the parameters */
1421 assert_param(IS_SYSCFG_USB(Usb));
1422
1423 SET_BIT(SYSCFG->ICNEWRCR, Usb);
1424 }
1425
1426 /**
1427 * @brief Disable USB early-write response.
1428 * @param Usb Selected USB instance(s).
1429 * This parameter can be a one of @ref SYSCFG_USBId
1430 * @retval None
1431 */
HAL_SYSCFG_DisableUSBEarlyEarlyWRRESP(uint32_t Usb)1432 void HAL_SYSCFG_DisableUSBEarlyEarlyWRRESP(uint32_t Usb)
1433 {
1434 /* Check the parameters */
1435 assert_param(IS_SYSCFG_USB(Usb));
1436
1437 CLEAR_BIT(SYSCFG->ICNEWRCR, Usb);
1438 }
1439
1440 /**
1441 * @brief Enable xPU clock gating.
1442 * @param Xpu Selected CPU(s).
1443 * This parameter can be a one of @ref SYSCFG_XPUId
1444 * @retval None
1445 */
HAL_SYSCFG_EnablexPUClockGating(uint32_t Xpu)1446 void HAL_SYSCFG_EnablexPUClockGating(uint32_t Xpu)
1447 {
1448 /* Check the parameters */
1449 assert_param(IS_SYSCFG_CPU_CLK_GATING(Xpu));
1450
1451 SET_BIT(SYSCFG->ICNCGCR, Xpu);
1452 }
1453
1454 /**
1455 * @brief Disable xPU clock gating.
1456 * @param Xpu Selected CPU(s).
1457 * This parameter can be a one of @ref SYSCFG_XPUId
1458 * @retval None
1459 */
HAL_SYSCFG_DisablexPUClockGating(uint32_t Xpu)1460 void HAL_SYSCFG_DisablexPUClockGating(uint32_t Xpu)
1461 {
1462 /* Check the parameters */
1463 assert_param(IS_SYSCFG_CPU_CLK_GATING(Xpu));
1464
1465 CLEAR_BIT(SYSCFG->ICNCGCR, Xpu);
1466 }
1467
1468 /**
1469 * @brief Enable the VDDIO2 compensation cell.
1470 * @retval None
1471 */
HAL_SYSCFG_EnableVDDIO2CompensationCell(void)1472 void HAL_SYSCFG_EnableVDDIO2CompensationCell(void)
1473 {
1474 SET_BIT(SYSCFG->VDDIO2CCCR, SYSCFG_VDDIO2CCCR_EN);
1475 }
1476
1477 /**
1478 * @brief Disable the VDDIO2 compensation cell.
1479 * @retval None
1480 */
HAL_SYSCFG_DisableVDDIO2CompensationCell(void)1481 void HAL_SYSCFG_DisableVDDIO2CompensationCell(void)
1482 {
1483 CLEAR_BIT(SYSCFG->VDDIO2CCCR, SYSCFG_VDDIO2CCCR_EN);
1484 }
1485
1486 /**
1487 * @brief Enable the VDDIO3 compensation cell.
1488 * @retval None
1489 */
HAL_SYSCFG_EnableVDDIO3CompensationCell(void)1490 void HAL_SYSCFG_EnableVDDIO3CompensationCell(void)
1491 {
1492 SET_BIT(SYSCFG->VDDIO3CCCR, SYSCFG_VDDIO3CCCR_EN);
1493 }
1494
1495 /**
1496 * @brief Disable the VDDIO3 compensation cell.
1497 * @retval None
1498 */
HAL_SYSCFG_DisableVDDIO3CompensationCell(void)1499 void HAL_SYSCFG_DisableVDDIO3CompensationCell(void)
1500 {
1501 CLEAR_BIT(SYSCFG->VDDIO3CCCR, SYSCFG_VDDIO3CCCR_EN);
1502 }
1503
1504 /**
1505 * @brief Enable the VDDIO4 compensation cell.
1506 * @retval None
1507 */
HAL_SYSCFG_EnableVDDIO4CompensationCell(void)1508 void HAL_SYSCFG_EnableVDDIO4CompensationCell(void)
1509 {
1510 SET_BIT(SYSCFG->VDDIO4CCCR, SYSCFG_VDDIO4CCCR_EN);
1511 }
1512
1513 /**
1514 * @brief Disable the VDDIO4 compensation cell.
1515 * @retval None
1516 */
HAL_SYSCFG_DisableVDDIO4CompensationCell(void)1517 void HAL_SYSCFG_DisableVDDIO4CompensationCell(void)
1518 {
1519 CLEAR_BIT(SYSCFG->VDDIO4CCCR, SYSCFG_VDDIO4CCCR_EN);
1520 }
1521
1522 /**
1523 * @brief Enable the VDDIO5 compensation cell.
1524 * @retval None
1525 */
HAL_SYSCFG_EnableVDDIO5CompensationCell(void)1526 void HAL_SYSCFG_EnableVDDIO5CompensationCell(void)
1527 {
1528 SET_BIT(SYSCFG->VDDIO5CCCR, SYSCFG_VDDIO5CCCR_EN);
1529 }
1530
1531 /**
1532 * @brief Disable the VDDIO5 compensation cell.
1533 * @retval None
1534 */
HAL_SYSCFG_DisableVDDIO5CompensationCell(void)1535 void HAL_SYSCFG_DisableVDDIO5CompensationCell(void)
1536 {
1537 CLEAR_BIT(SYSCFG->VDDIO5CCCR, SYSCFG_VDDIO5CCCR_EN);
1538 }
1539
1540 /**
1541 * @brief Configure the code selection for the compensation cell
1542 * @param Selection specifies the concerned compensation cell
1543 * This parameter can one of the following values:
1544 * @arg SYSCFG_IO_VDDIO2_CELL Compensation cell for the VDDIO2
1545 * @arg SYSCFG_IO_VDDIO3_CELL Compensation cell for the VDDIO3
1546 * @arg SYSCFG_IO_VDDIO4_CELL Compensation cell for the VDDIO4
1547 * @arg SYSCFG_IO_VDDIO5_CELL Compensation cell for the VDDIO5
1548 * @param Code code selection to be applied for the I/O compensation cell
1549 * This parameter can be one of the following values:
1550 * @arg SYSCFG_IO_CELL_CODE Code from the cell (available in the SYSCFG_VDDIOxCCSR)
1551 * @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register ((SYSCFG_VDDIOxCCCR)
1552 * @param NmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it provides the Nmos value
1553 * to apply in range 0 to 15 else this parameter is not used
1554 * @param PmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it provides the Pmos value
1555 * to apply in range 0 to 15 else this parameter is not used
1556 * @retval HAL status
1557 */
HAL_SYSCFG_ConfigVDDIOCompensationCell(uint32_t Selection,uint32_t Code,uint32_t NmosValue,uint32_t PmosValue)1558 HAL_StatusTypeDef HAL_SYSCFG_ConfigVDDIOCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue,
1559 uint32_t PmosValue)
1560 {
1561 HAL_StatusTypeDef status = HAL_OK;
1562
1563 /* Check the parameters */
1564 assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection));
1565 assert_param(IS_SYSCFG_IO_COMPENSATION_CODE(Code));
1566
1567 if (Code == SYSCFG_IO_REGISTER_CODE)
1568 {
1569 /* Check the parameters */
1570 assert_param(IS_SYSCFG_IO_COMPENSATION_CELL_NMOS_VALUE(NmosValue));
1571 assert_param(IS_SYSCFG_IO_COMPENSATION_CELL_PMOS_VALUE(PmosValue));
1572
1573 /* Reject forbidden Nmos = 0 and Pmos = 15 */
1574 if ((NmosValue == 0U) || (PmosValue == 0xFU))
1575 {
1576 status = HAL_ERROR;
1577 }
1578 else
1579 {
1580 switch (Selection)
1581 {
1582 case SYSCFG_IO_VDDIO2_CELL:
1583 {
1584 MODIFY_REG(SYSCFG->VDDIO2CCCR, 0x2FFU, ((NmosValue | (PmosValue << (4U))) | SYSCFG_VDDIO2CCCR_CS));
1585 break;
1586 }
1587 case SYSCFG_IO_VDDIO3_CELL:
1588 {
1589 MODIFY_REG(SYSCFG->VDDIO3CCCR, 0x2FFU, ((NmosValue | (PmosValue << (4U))) | SYSCFG_VDDIO3CCCR_CS));
1590 break;
1591 }
1592 case SYSCFG_IO_VDDIO4_CELL:
1593 {
1594 MODIFY_REG(SYSCFG->VDDIO4CCCR, 0x2FFU, ((NmosValue) | (PmosValue << (4U)) | SYSCFG_VDDIO4CCCR_CS));
1595 break;
1596 }
1597 case SYSCFG_IO_VDDIO5_CELL:
1598 {
1599 MODIFY_REG(SYSCFG->VDDIO5CCCR, 0x2FFU, ((NmosValue | (PmosValue << (4U))) | SYSCFG_VDDIO5CCCR_CS));
1600 break;
1601 }
1602 default:
1603 {
1604 /* Update error status */
1605 status = HAL_ERROR;
1606 break;
1607 }
1608 }
1609 }
1610 }
1611 else
1612 {
1613 switch (Selection)
1614 {
1615
1616 case SYSCFG_IO_VDDIO2_CELL:
1617 {
1618 MODIFY_REG(SYSCFG->VDDIO2CCCR, SYSCFG_VDDIO2CCCR_CS, 0U);
1619 break;
1620 }
1621 case SYSCFG_IO_VDDIO3_CELL:
1622 {
1623 MODIFY_REG(SYSCFG->VDDIO3CCCR, SYSCFG_VDDIO3CCCR_CS, 0U);
1624 break;
1625 }
1626 case SYSCFG_IO_VDDIO4_CELL:
1627 {
1628 MODIFY_REG(SYSCFG->VDDIO4CCCR, SYSCFG_VDDIO4CCCR_CS, 0U);
1629 break;
1630 }
1631 case SYSCFG_IO_VDDIO5_CELL:
1632 {
1633 MODIFY_REG(SYSCFG->VDDIO5CCCR, SYSCFG_VDDIO5CCCR_CS, 0U);
1634 break;
1635 }
1636 default:
1637 {
1638 /* Update error status */
1639 status = HAL_ERROR;
1640 break;
1641 }
1642 }
1643 }
1644 return status;
1645 }
1646
1647 /**
1648 * @brief Get the code selection for the compensation cell
1649 * @param Selection specifies the concerned compensation cell
1650 * This parameter can one of the following values:
1651 * @arg SYSCFG_IO_VDDIO2_CELL Compensation cell for the VDDIO2
1652 * @arg SYSCFG_IO_VDDIO3_CELL Compensation cell for the VDDIO3
1653 * @arg SYSCFG_IO_VDDIO4_CELL Compensation cell for the VDDIO4
1654 * @arg SYSCFG_IO_VDDIO5_CELL Compensation cell for the VDDIO5
1655 * @param pCode pointer to code selection
1656 * This parameter can be one of the following values:
1657 * @arg SYSCFG_IO_CELL_CODE Code from the cell (available in the SYSCFG_VDDIOxCCSR)
1658 * @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register ((SYSCFG_VDDIOxCCCR)
1659 * @param pNmosValue pointer to the Nmos value in range 0 to 15
1660 * @param pPmosValue pointer to the Pmos value in range 0 to 15
1661 * @retval HAL_OK (all values available) or HAL_ERROR (check parameters)
1662 */
HAL_SYSCFG_GetVDDIOCompensationCell(uint32_t Selection,const uint32_t * pCode,uint32_t * pNmosValue,uint32_t * pPmosValue)1663 HAL_StatusTypeDef HAL_SYSCFG_GetVDDIOCompensationCell(uint32_t Selection, const uint32_t *pCode, uint32_t *pNmosValue,
1664 uint32_t *pPmosValue)
1665 {
1666 HAL_StatusTypeDef status = HAL_ERROR;
1667 uint32_t values = 0;
1668
1669 /* Check the parameters */
1670 assert_param(IS_SYSCFG_COMPENSATION_CELL(Selection));
1671 assert_param(IS_SYSCFG_IO_COMPENSATION_CODE(*pCode));
1672
1673 if ((pCode != NULL) && (pNmosValue != NULL) && (pPmosValue != NULL))
1674 {
1675 status = HAL_OK;
1676
1677 if (*pCode == SYSCFG_IO_REGISTER_CODE)
1678 {
1679 switch (Selection)
1680 {
1681 case SYSCFG_IO_VDDIO2_CELL:
1682 {
1683 values = READ_REG(SYSCFG->VDDIO2CCCR) & 0xFFU;
1684 break;
1685 }
1686 case SYSCFG_IO_VDDIO3_CELL:
1687 {
1688 values = READ_REG(SYSCFG->VDDIO3CCCR) & 0xFFU;
1689 break;
1690 }
1691 case SYSCFG_IO_VDDIO4_CELL:
1692 {
1693 values = READ_REG(SYSCFG->VDDIO4CCCR) & 0xFFU;
1694 break;
1695 }
1696 case SYSCFG_IO_VDDIO5_CELL:
1697 {
1698 values = READ_REG(SYSCFG->VDDIO5CCCR) & 0xFFU;
1699 break;
1700 }
1701 default:
1702 {
1703 /* Update error status */
1704 status = HAL_ERROR;
1705 break;
1706 }
1707 }
1708 }
1709 else
1710 {
1711 switch (Selection)
1712 {
1713 case SYSCFG_IO_VDDIO2_CELL:
1714 {
1715 values = READ_REG(SYSCFG->VDDIO2CCSR) & 0xFFU;
1716 break;
1717 }
1718 case SYSCFG_IO_VDDIO3_CELL:
1719 {
1720 values = READ_REG(SYSCFG->VDDIO3CCSR) & 0xFFU;
1721 break;
1722 }
1723 case SYSCFG_IO_VDDIO4_CELL:
1724 {
1725 values = READ_REG(SYSCFG->VDDIO4CCSR) & 0xFFU;
1726 break;
1727 }
1728 case SYSCFG_IO_VDDIO5_CELL:
1729 {
1730 values = READ_REG(SYSCFG->VDDIO5CCSR) & 0xFFU;
1731 break;
1732 }
1733 default:
1734 {
1735 /* Update error status */
1736 status = HAL_ERROR;
1737 break;
1738 }
1739 }
1740 }
1741 *pNmosValue = (values & 0xFU);
1742 *pPmosValue = ((values & 0xF0U) >> 4U);
1743 }
1744 return status;
1745 }
1746
1747 /**
1748 * @brief Get the compensation cell ready status of VDDIO2.
1749 * @retval Ready status (0 (not ready) or !=0 (ready))
1750 */
HAL_SYSCFG_GetCompVDDIO2CellReadyStatus(void)1751 uint32_t HAL_SYSCFG_GetCompVDDIO2CellReadyStatus(void)
1752 {
1753 return READ_BIT(SYSCFG->VDDIO2CCSR, SYSCFG_VDDIO2CCSR_READY);
1754 }
1755
1756 /**
1757 * @brief Get the compensation cell ready status of VDDIO3.
1758 * @retval Ready status (0 (not ready) or !=0 (ready))
1759 */
HAL_SYSCFG_GetCompVDDIO3CellReadyStatus(void)1760 uint32_t HAL_SYSCFG_GetCompVDDIO3CellReadyStatus(void)
1761 {
1762 return READ_BIT(SYSCFG->VDDIO3CCSR, SYSCFG_VDDIO3CCSR_READY);
1763 }
1764
1765 /**
1766 * @brief Get the compensation cell ready status of VDDIO4.
1767 * @retval Ready status (0 (not ready) or !=0 (ready))
1768 */
HAL_SYSCFG_GetCompVDDIO4CellReadyStatus(void)1769 uint32_t HAL_SYSCFG_GetCompVDDIO4CellReadyStatus(void)
1770 {
1771 return READ_BIT(SYSCFG->VDDIO4CCSR, SYSCFG_VDDIO4CCSR_READY);
1772 }
1773
1774 /**
1775 * @brief Get the compensation cell ready status of VDDIO5.
1776 * @retval Ready status (0 (not ready) or !=0 (ready))
1777 */
HAL_SYSCFG_GetCompVDDIO5CellReadyStatus(void)1778 uint32_t HAL_SYSCFG_GetCompVDDIO5CellReadyStatus(void)
1779 {
1780 return READ_BIT(SYSCFG->VDDIO5CCSR, SYSCFG_VDDIO5CCSR_READY);
1781 }
1782
1783 /**
1784 * @brief Configure the code selection for the compensation cell of VDD
1785 * @param Code code selection to be applied for the I/O compensation cell
1786 * This parameter can be one of the following values:
1787 * @arg SYSCFG_IO_CELL_CODE Code from the cell (available in the SYSCFG_VDDIOxCCSR)
1788 * @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register ((SYSCFG_VDDIOxCCCR)
1789 * @param NmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it provides the Nmos value
1790 * to apply in range 0 to 15 else this parameter is not used
1791 * @param PmosValue In case SYSCFG_IO_REGISTER_CODE is selected, it provides the Pmos value
1792 * to apply in range 0 to 15 else this parameter is not used
1793 * @retval HAL status
1794 */
1795
HAL_SYSCFG_ConfigVDDCompensationCell(uint32_t Code,uint32_t NmosValue,uint32_t PmosValue)1796 HAL_StatusTypeDef HAL_SYSCFG_ConfigVDDCompensationCell(uint32_t Code, uint32_t NmosValue, uint32_t PmosValue)
1797 {
1798 HAL_StatusTypeDef status;
1799
1800 /* Check the parameters */
1801 assert_param(IS_SYSCFG_IO_COMPENSATION_CODE(Code));
1802
1803 if (Code == SYSCFG_IO_REGISTER_CODE)
1804 {
1805 /* Check the parameters */
1806 assert_param(IS_SYSCFG_IO_COMPENSATION_CELL_NMOS_VALUE(NmosValue));
1807 assert_param(IS_SYSCFG_IO_COMPENSATION_CELL_PMOS_VALUE(PmosValue));
1808
1809 MODIFY_REG(SYSCFG->VDDCCCR, 0xFFU, ((NmosValue | (PmosValue << (4U))) | SYSCFG_VDDCCCR_CS));
1810
1811 status = HAL_OK;
1812 }
1813 else
1814 {
1815 MODIFY_REG(SYSCFG->VDDCCCR, 0x200U, 0U);
1816 status = HAL_OK;
1817 }
1818 return status;
1819 }
1820
1821 /**
1822 * @brief Enable the VDD compensation cell.
1823 * @retval None
1824 */
HAL_SYSCFG_EnableVDDCompensationCell(void)1825 void HAL_SYSCFG_EnableVDDCompensationCell(void)
1826 {
1827 SET_BIT(SYSCFG->VDDCCCR, SYSCFG_VDDCCCR_EN);
1828 }
1829
1830 /**
1831 * @brief Disable the VDD compensation cell.
1832 * @retval None
1833 */
HAL_SYSCFG_DisableVDDCompensationCell(void)1834 void HAL_SYSCFG_DisableVDDCompensationCell(void)
1835 {
1836 CLEAR_BIT(SYSCFG->VDDCCCR, SYSCFG_VDDCCCR_EN);
1837 }
1838
1839 /**
1840 * @brief Get the code selection for the compensation cell of VDD
1841 * @param Code code selection
1842 * This parameter can be one of the following values:
1843 * @arg SYSCFG_IO_CELL_CODE Code from the cell (available in the SYSCFG_VDDIOxCCSR)
1844 * @arg SYSCFG_IO_REGISTER_CODE Code from the compensation cell code register ((SYSCFG_VDDIOxCCCR)
1845 * @param pNmosValue pointer to the Nmos value in range 0 to 15
1846 * @param pPmosValue pointer to the Pmos value in range 0 to 15
1847 * @retval HAL_OK (all values available) or HAL_ERROR (check parameters)
1848 */
HAL_SYSCFG_GetVDDCompensationCell(uint32_t Code,uint32_t * pNmosValue,uint32_t * pPmosValue)1849 HAL_StatusTypeDef HAL_SYSCFG_GetVDDCompensationCell(uint32_t Code, uint32_t *pNmosValue,
1850 uint32_t *pPmosValue)
1851 {
1852 uint32_t values;
1853 HAL_StatusTypeDef status = HAL_ERROR;
1854
1855 /* Check the parameters */
1856 assert_param(IS_SYSCFG_IO_COMPENSATION_CODE(Code));
1857
1858 if ((pNmosValue != NULL) && (pPmosValue != NULL))
1859 {
1860 if (Code == SYSCFG_IO_REGISTER_CODE)
1861 {
1862 values = READ_REG(SYSCFG->VDDCCCR) & 0xFFU;
1863 }
1864 else
1865 {
1866 values = READ_REG(SYSCFG->VDDCCSR) & 0xFFU;
1867 }
1868
1869 *pNmosValue = (values & 0xFU);
1870 *pPmosValue = ((values >> 4U) & 0xFU);
1871
1872 status = HAL_OK;
1873 }
1874 return status;
1875 }
1876
1877 /**
1878 * @brief Get the compensation cell ready status of VDD.
1879 * @retval Ready status (0 (not ready) or !=0 (ready))
1880 */
HAL_SYSCFG_GetCompensationVDDCellReadyStatus(void)1881 uint32_t HAL_SYSCFG_GetCompensationVDDCellReadyStatus(void)
1882 {
1883 return READ_BIT(SYSCFG->VDDCCSR, SYSCFG_VDDCCSR_READY);
1884 }
1885
1886 /**
1887 * @brief Configure the Timer Break input for error flag(s).
1888 * @note When a configuration is set, only a system reset can reset it.
1889 * @param Input Input configuration
1890 * This parameter can be one or a combination of the following values:
1891 * @arg SYSCFG_CBR_BREAK_LOCK_CORE Cortex-CM55 lockup
1892 * @arg SYSCFG_CBR_BREAK_LOCK_PVD PVD lock
1893 * @arg SYSCFG_CBR_BREAK_LOCK_BKPRAM Backup SRAM ECC error
1894 * @arg SYSCFG_CBR_BREAK_LOCK_CM55_CACHE CM55 cache double ECC error
1895 * @arg SYSCFG_CBR_BREAK_LOCK_CM55_TCM DTCM double ECC error
1896 * @retval None
1897 */
HAL_SYSCFG_ConfigTimerBreakInput(uint32_t Input)1898 void HAL_SYSCFG_ConfigTimerBreakInput(uint32_t Input)
1899 {
1900 /* Check the parameter */
1901 assert_param(IS_SYSCFG_CBR_BREAK_INPUT(Input));
1902
1903 MODIFY_REG(SYSCFG->CBR, Input, Input);
1904 }
1905
1906 /**
1907 * @brief Get the Timer Break input configuration.
1908 * @note When a configuration is set, only a system reset can reset it.
1909 * @retval Timer break input configuration
1910 * This return value can be one or a combination of the following values:
1911 * @arg SYSCFG_CBR_BREAK_LOCK_CORE Cortex-CM55 lockup
1912 * @arg SYSCFG_CBR_BREAK_LOCK_PVD PVD lock
1913 * @arg SYSCFG_CBR_BREAK_LOCK_BKPRAM Backup SRAM ECC error
1914 * @arg SYSCFG_CBR_BREAK_LOCK_CM55_CACHE CM55 cache double ECC error
1915 * @arg SYSCFG_CBR_BREAK_LOCK_CM55_TCM DTCM double ECC error
1916 */
HAL_SYSCFG_GetTimerBreakInputConfig(void)1917 uint32_t HAL_SYSCFG_GetTimerBreakInputConfig(void)
1918 {
1919 return (SYSCFG->CBR & SYSCFG_CBR_BREAK_LOCK_ALL);
1920 }
1921
1922 /**
1923 * @brief Set the perceived CID of the peripheral.
1924 * @note Set the perceived CID so that all accesses which arrive at the peripheral
1925 * (here HPDMA) appear to carry that CID.
1926 * See Multi-tenancy section of the reference manual for further information.
1927 * @param Cid CID in range 0 to 7
1928 * @retval None
1929 */
HAL_SYSCFG_SetPerceivedCID(uint32_t Cid)1930 void HAL_SYSCFG_SetPerceivedCID(uint32_t Cid)
1931 {
1932 /* Check the parameter */
1933 assert_param(IS_SYSCFG_DMA_CID_SEC(Cid));
1934
1935 MODIFY_REG(SYSCFG->SEC_AIDCR, SYSCFG_SEC_AIDCR_DMACID_SEC, Cid);
1936 }
1937
1938 /**
1939 * @brief Get the perceived CID of the peripheral.
1940 * @retval CID in range 0 to 7
1941 */
HAL_SYSCFG_GetPerceivedCID(void)1942 uint32_t HAL_SYSCFG_GetPerceivedCID(void)
1943 {
1944 return (SYSCFG->SEC_AIDCR & SYSCFG_SEC_AIDCR_DMACID_SEC);
1945 }
1946
1947 /**
1948 * @brief Set the perceived CID of the peripheral as privileged.
1949 * @note Set the perceived CID so that all accesses which arrive at the peripheral
1950 * (here HPDMA) appear to carry that CID.
1951 * This function shall be called in case of DMA channel interrupt (privileged) code
1952 * to read the registers and clear the interrupt of this DMA channel.
1953 * See Multi-tenancy section of the reference manual for forther information.
1954 * @param Cid in range 0 to 7
1955 * @retval None
1956 */
HAL_SYSCFG_SetPerceivedPrivCID(uint32_t Cid)1957 void HAL_SYSCFG_SetPerceivedPrivCID(uint32_t Cid)
1958 {
1959 MODIFY_REG(SYSCFG->SECPRIV_AIDCR, SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC, Cid);
1960 }
1961
1962 /**
1963 * @brief Get the perceived CID of the peripheral as privileged.
1964 * @retval CID in range 0 to 7
1965 */
HAL_SYSCFG_GetPerceivedPrivCID(void)1966 uint32_t HAL_SYSCFG_GetPerceivedPrivCID(void)
1967 {
1968 return (SYSCFG->SECPRIV_AIDCR & SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC);
1969 }
1970
1971 /**
1972 * @brief Enable Retiming on RX path.
1973 * @retval None
1974 */
HAL_SYSCFG_EnableReTimingRXpath(void)1975 void HAL_SYSCFG_EnableReTimingRXpath(void)
1976 {
1977 SET_BIT(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_CFG_RETIME_RX);
1978 }
1979
1980 /**
1981 * @brief Disable Retiming on RX path.
1982 * @retval None
1983 */
HAL_SYSCFG_DisableReTimingRXpath(void)1984 void HAL_SYSCFG_DisableReTimingRXpath(void)
1985 {
1986 CLEAR_BIT(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_CFG_RETIME_RX);
1987 }
1988
1989 /**
1990 * @brief Enable Retiming on TX path.
1991 * @retval None
1992 */
HAL_SYSCFG_EnableReTimingTXpath(void)1993 void HAL_SYSCFG_EnableReTimingTXpath(void)
1994 {
1995 SET_BIT(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_CFG_RETIME_TX);
1996 }
1997
1998 /**
1999 * @brief Disable Retiming on TX path.
2000 * @retval None
2001 */
HAL_SYSCFG_DisableReTimingTXpath(void)2002 void HAL_SYSCFG_DisableReTimingTXpath(void)
2003 {
2004 CLEAR_BIT(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_CFG_RETIME_TX);
2005 }
2006
2007 /**
2008 * @brief Set delay on feedback clock.
2009 * @param Delay Delay on feedback clock
2010 * @arg SYSCFG_DELAY_FEEDBACK_NONE None
2011 * @arg SYSCFG_DELAY_FEEDBACK_HALF_CYCLE Half a cycle delay
2012 * @retval None
2013 */
HAL_SYSCFG_SetDelayOnFeedbackClock(uint32_t Delay)2014 void HAL_SYSCFG_SetDelayOnFeedbackClock(uint32_t Delay)
2015 {
2016 /* Check the parameter */
2017 assert_param(IS_SYSCFG_DMA_DELAY_FEEDBACK_CLOCK(Delay));
2018
2019 MODIFY_REG(SYSCFG->FMC_RETIMECR, SYSCFG_FMC_RETIMECR_SDFBCLK_180, Delay);
2020 }
2021
2022 /**
2023 * @brief Get delay on feedback clock.
2024 * @retval Delay on feedback clock
2025 * @arg SYSCFG_DELAY_FEEDBACK_NONE None
2026 * @arg SYSCFG_DELAY_FEEDBACK_HALF_CYCLE Half a cycle delay
2027 */
HAL_SYSCFG_GetDelayOnFeedbackClock(void)2028 uint32_t HAL_SYSCFG_GetDelayOnFeedbackClock(void)
2029 {
2030 return (SYSCFG->FMC_RETIMECR & SYSCFG_FMC_RETIMECR_SDFBCLK_180);
2031 }
2032
2033 #if defined(SYSCFG_NPUNICQOSCR_NPU1_ARQOSR)
2034 /**
2035 * @brief Enable the interleaving on NPU RAM.
2036 * @retval None
2037 */
HAL_SYSCFG_EnableInterleavingCpuRam(void)2038 void HAL_SYSCFG_EnableInterleavingCpuRam(void)
2039 {
2040 SET_BIT(SYSCFG->NPU_ICNCR, SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE);
2041 }
2042
2043 /**
2044 * @brief Disable the interleaving on NPU RAM.
2045 * @retval None
2046 */
HAL_SYSCFG_DisableInterleavingCpuRam(void)2047 void HAL_SYSCFG_DisableInterleavingCpuRam(void)
2048 {
2049 CLEAR_BIT(SYSCFG->NPU_ICNCR, SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE);
2050 }
2051 #endif /* SYSCFG_NPUNICQOSCR_NPU1_ARQOSR */
2052
2053 /**
2054 * @brief Get BOOT pin connection status
2055 * @param BootId specifies the boot pins.
2056 * @retval BOOT pin connection configuration
2057 * This return value can be one of the following values:
2058 * @arg SYSCFG_BOOT_CONNECTION_VSS pin connected to VSS
2059 * @arg SYSCFG_BOOT_CONNECTION_VDD pin connected to VDD
2060 */
HAL_SYSCFG_GetBootPinConnection(uint32_t BootId)2061 uint32_t HAL_SYSCFG_GetBootPinConnection(uint32_t BootId)
2062 {
2063 uint32_t Connection;
2064
2065 /* Check the parameters */
2066 assert_param(IS_SYSCFG_BOOT_ID(BootId));
2067
2068 Connection = READ_BIT(SYSCFG->BOOTSR, BootId);
2069
2070 if (BootId == SYSCFG_BOOTCR_BOOT0_PD)
2071 {
2072 return Connection;
2073 }
2074 else
2075 {
2076 return (Connection >> 1U);
2077 }
2078 }
2079
2080 /**
2081 * @brief Get address of first error in P-AHB write-posting buffer
2082 * @retval Address of the first error in P-AHB write-posting buffer
2083 */
HAL_SYSCFG_GetAddressWritePostingBuffer(void)2084 uint32_t HAL_SYSCFG_GetAddressWritePostingBuffer(void)
2085 {
2086 return READ_BIT(SYSCFG->AHBWP_ERROR_SR, SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR);
2087 }
2088
2089 /**
2090 * @}
2091 */
2092
2093 /**
2094 * @}
2095 */
2096
2097 #endif /* HAL_MODULE_ENABLED */
2098
2099 /**
2100 * @}
2101 */
2102
2103 /**
2104 * @}
2105 */
2106
