1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_hal_sram.c
4 * @author MCD Application Team
5 * @brief SRAM HAL module driver.
6 * This file provides a generic firmware to drive SRAM memories
7 * mounted as external device.
8 *
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2019 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 This driver is a generic layered driver which contains a set of APIs used to
26 control SRAM memories. It uses the FMC layer functions to interface
27 with SRAM devices.
28 The following sequence should be followed to configure the FMC to interface
29 with SRAM/PSRAM memories:
30
31 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
32 SRAM_HandleTypeDef hsram; and:
33
34 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
35 values of the structure member.
36
37 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
38 base register instance for NOR or SRAM device
39
40 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
41 base register instance for NOR or SRAM extended mode
42
43 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
44 mode timings; for example:
45 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
46 and fill its fields with the allowed values of the structure member.
47
48 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
49 performs the following sequence:
50
51 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
52 (##) Control register configuration using the FMC NORSRAM interface function
53 FMC_NORSRAM_Init()
54 (##) Timing register configuration using the FMC NORSRAM interface function
55 FMC_NORSRAM_Timing_Init()
56 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
57 FMC_NORSRAM_Extended_Timing_Init()
58 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
59
60 (#) At this stage you can perform read/write accesses from/to the memory connected
61 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
62 following APIs:
63 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
64 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
65
66 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
67 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
68
69 (#) You can continuously monitor the SRAM device HAL state by calling the function
70 HAL_SRAM_GetState()
71
72 *** Callback registration ***
73 =============================================
74 [..]
75 The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
76 allows the user to configure dynamically the driver callbacks.
77
78 Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
79 it allows to register following callbacks:
80 (+) MspInitCallback : SRAM MspInit.
81 (+) MspDeInitCallback : SRAM MspDeInit.
82 This function takes as parameters the HAL peripheral handle, the Callback ID
83 and a pointer to the user callback function.
84
85 Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
86 weak (surcharged) function. It allows to reset following callbacks:
87 (+) MspInitCallback : SRAM MspInit.
88 (+) MspDeInitCallback : SRAM MspDeInit.
89 This function) takes as parameters the HAL peripheral handle and the Callback ID.
90
91 By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
92 all callbacks are reset to the corresponding legacy weak (surcharged) functions.
93 Exception done for MspInit and MspDeInit callbacks that are respectively
94 reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
95 and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
96 If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
97 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
98
99 Callbacks can be registered/unregistered in READY state only.
100 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
101 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
102 during the Init/DeInit.
103 In that case first register the MspInit/MspDeInit user callbacks
104 using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
105 or @ref HAL_SRAM_Init function.
106
107 When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
108 not defined, the callback registering feature is not available
109 and weak (surcharged) callbacks are used.
110
111 @endverbatim
112 ******************************************************************************
113 */
114
115 /* Includes ------------------------------------------------------------------*/
116 #include "stm32mp1xx_hal.h"
117
118
119 /** @addtogroup STM32MP1xx_HAL_Driver
120 * @{
121 */
122
123 #ifdef HAL_SRAM_MODULE_ENABLED
124
125 /** @defgroup SRAM SRAM
126 * @brief SRAM driver modules
127 * @{
128 */
129
130 /**
131 @cond 0
132 */
133 /* Private typedef -----------------------------------------------------------*/
134 /* Private define ------------------------------------------------------------*/
135 /* Private macro -------------------------------------------------------------*/
136 /* Private variables ---------------------------------------------------------*/
137 /* Private function prototypes -----------------------------------------------*/
138 static void SRAM_DMACplt (DMA_HandleTypeDef *hdma);
139 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
140 static void SRAM_DMAError (DMA_HandleTypeDef *hdma);
141 /**
142 @endcond
143 */
144
145 /* Exported functions --------------------------------------------------------*/
146
147 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
148 * @{
149 */
150
151 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
152 * @brief Initialization and Configuration functions.
153 *
154 @verbatim
155 ==============================================================================
156 ##### SRAM Initialization and de_initialization functions #####
157 ==============================================================================
158 [..] This section provides functions allowing to initialize/de-initialize
159 the SRAM memory
160
161 @endverbatim
162 * @{
163 */
164
165 /**
166 * @brief Performs the SRAM device initialization sequence
167 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
168 * the configuration information for SRAM module.
169 * @param Timing Pointer to SRAM control timing structure
170 * @param ExtTiming Pointer to SRAM extended mode timing structure
171 * @retval HAL status
172 */
HAL_SRAM_Init(SRAM_HandleTypeDef * hsram,FMC_NORSRAM_TimingTypeDef * Timing,FMC_NORSRAM_TimingTypeDef * ExtTiming)173 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
174 {
175 /* Check the SRAM handle parameter */
176 if (hsram == NULL)
177 {
178 return HAL_ERROR;
179 }
180
181 if (hsram->State == HAL_SRAM_STATE_RESET)
182 {
183 /* Allocate lock resource and initialize it */
184 hsram->Lock = HAL_UNLOCKED;
185
186 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
187 if(hsram->MspInitCallback == NULL)
188 {
189 hsram->MspInitCallback = HAL_SRAM_MspInit;
190 }
191 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
192 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
193
194 /* Init the low level hardware */
195 hsram->MspInitCallback(hsram);
196 #else
197 /* Initialize the low level hardware (MSP) */
198 HAL_SRAM_MspInit(hsram);
199 #endif
200 }
201
202 /* Initialize SRAM control Interface */
203 (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
204
205 /* Initialize SRAM timing Interface */
206 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
207
208 /* Initialize SRAM extended mode timing Interface */
209 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
210
211 /* Enable the NORSRAM device */
212 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
213
214 /* Enable FMC Peripheral */
215 __FMC_ENABLE();
216
217 /* Initialize the SRAM controller state */
218 hsram->State = HAL_SRAM_STATE_READY;
219
220 return HAL_OK;
221 }
222
223 /**
224 * @brief Performs the SRAM device De-initialization sequence.
225 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
226 * the configuration information for SRAM module.
227 * @retval HAL status
228 */
HAL_SRAM_DeInit(SRAM_HandleTypeDef * hsram)229 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
230 {
231 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
232 if(hsram->MspDeInitCallback == NULL)
233 {
234 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
235 }
236
237 /* DeInit the low level hardware */
238 hsram->MspDeInitCallback(hsram);
239 #else
240 /* De-Initialize the low level hardware (MSP) */
241 HAL_SRAM_MspDeInit(hsram);
242 #endif
243
244 /* Configure the SRAM registers with their reset values */
245 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
246
247 /* Reset the SRAM controller state */
248 hsram->State = HAL_SRAM_STATE_RESET;
249
250 /* Release Lock */
251 __HAL_UNLOCK(hsram);
252
253 return HAL_OK;
254 }
255
256 /**
257 * @brief SRAM MSP Init.
258 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
259 * the configuration information for SRAM module.
260 * @retval None
261 */
HAL_SRAM_MspInit(SRAM_HandleTypeDef * hsram)262 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
263 {
264 /* Prevent unused argument(s) compilation warning */
265 UNUSED(hsram);
266
267 /* NOTE : This function Should not be modified, when the callback is needed,
268 the HAL_SRAM_MspInit could be implemented in the user file
269 */
270 }
271
272 /**
273 * @brief SRAM MSP DeInit.
274 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
275 * the configuration information for SRAM module.
276 * @retval None
277 */
HAL_SRAM_MspDeInit(SRAM_HandleTypeDef * hsram)278 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
279 {
280 /* Prevent unused argument(s) compilation warning */
281 UNUSED(hsram);
282
283 /* NOTE : This function Should not be modified, when the callback is needed,
284 the HAL_SRAM_MspDeInit could be implemented in the user file
285 */
286 }
287
288 /**
289 * @brief DMA transfer complete callback.
290 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
291 * the configuration information for SRAM module.
292 * @retval None
293 */
HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef * hdma)294 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
295 {
296 /* Prevent unused argument(s) compilation warning */
297 UNUSED(hdma);
298
299 /* NOTE : This function Should not be modified, when the callback is needed,
300 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
301 */
302 }
303
304 /**
305 * @brief DMA transfer complete error callback.
306 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
307 * the configuration information for SRAM module.
308 * @retval None
309 */
HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef * hdma)310 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
311 {
312 /* Prevent unused argument(s) compilation warning */
313 UNUSED(hdma);
314
315 /* NOTE : This function Should not be modified, when the callback is needed,
316 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
317 */
318 }
319
320 /**
321 * @}
322 */
323
324 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
325 * @brief Input Output and memory control functions
326 *
327 @verbatim
328 ==============================================================================
329 ##### SRAM Input and Output functions #####
330 ==============================================================================
331 [..]
332 This section provides functions allowing to use and control the SRAM memory
333
334 @endverbatim
335 * @{
336 */
337
338 /**
339 * @brief Reads 8-bit buffer from SRAM memory.
340 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
341 * the configuration information for SRAM module.
342 * @param pAddress Pointer to read start address
343 * @param pDstBuffer Pointer to destination buffer
344 * @param BufferSize Size of the buffer to read from memory
345 * @retval HAL status
346 */
HAL_SRAM_Read_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)347 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
348 {
349 uint32_t size;
350 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
351 uint8_t * pdestbuff = pDstBuffer;
352 HAL_SRAM_StateTypeDef state = hsram->State;
353
354 /* Check the SRAM controller state */
355 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
356 {
357 /* Process Locked */
358 __HAL_LOCK(hsram);
359
360 /* Update the SRAM controller state */
361 hsram->State = HAL_SRAM_STATE_BUSY;
362
363 /* Read data from memory */
364 for (size = BufferSize; size != 0U; size--)
365 {
366 *pdestbuff = *psramaddress;
367 pdestbuff++;
368 psramaddress++;
369 }
370
371 /* Update the SRAM controller state */
372 hsram->State = state;
373
374 /* Process unlocked */
375 __HAL_UNLOCK(hsram);
376 }
377 else
378 {
379 return HAL_ERROR;
380 }
381
382 return HAL_OK;
383 }
384
385 /**
386 * @brief Writes 8-bit buffer to SRAM memory.
387 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
388 * the configuration information for SRAM module.
389 * @param pAddress Pointer to write start address
390 * @param pSrcBuffer Pointer to source buffer to write
391 * @param BufferSize Size of the buffer to write to memory
392 * @retval HAL status
393 */
HAL_SRAM_Write_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)394 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
395 {
396 uint32_t size;
397 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
398 uint8_t * psrcbuff = pSrcBuffer;
399
400 /* Check the SRAM controller state */
401 if (hsram->State == HAL_SRAM_STATE_READY)
402 {
403 /* Process Locked */
404 __HAL_LOCK(hsram);
405
406 /* Update the SRAM controller state */
407 hsram->State = HAL_SRAM_STATE_BUSY;
408
409 /* Write data to memory */
410 for (size = BufferSize; size != 0U; size--)
411 {
412 *psramaddress = *psrcbuff;
413 psrcbuff++;
414 psramaddress++;
415 }
416
417 /* Update the SRAM controller state */
418 hsram->State = HAL_SRAM_STATE_READY;
419
420 /* Process unlocked */
421 __HAL_UNLOCK(hsram);
422 }
423 else
424 {
425 return HAL_ERROR;
426 }
427
428 return HAL_OK;
429 }
430
431 /**
432 * @brief Reads 16-bit buffer from SRAM memory.
433 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
434 * the configuration information for SRAM module.
435 * @param pAddress Pointer to read start address
436 * @param pDstBuffer Pointer to destination buffer
437 * @param BufferSize Size of the buffer to read from memory
438 * @retval HAL status
439 */
HAL_SRAM_Read_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)440 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
441 {
442 uint32_t size;
443 __IO uint32_t *psramaddress = pAddress;
444 uint16_t *pdestbuff = pDstBuffer;
445 uint8_t limit;
446 HAL_SRAM_StateTypeDef state = hsram->State;
447
448 /* Check the SRAM controller state */
449 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
450 {
451 /* Process Locked */
452 __HAL_LOCK(hsram);
453
454 /* Update the SRAM controller state */
455 hsram->State = HAL_SRAM_STATE_BUSY;
456
457 /* Check if the size is a 32-bits mulitple */
458 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
459
460 /* Read data from memory */
461 for (size = BufferSize; size != limit; size-=2U)
462 {
463 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
464 pdestbuff++;
465 *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
466 pdestbuff++;
467 psramaddress++;
468 }
469
470 /* Read last 16-bits if size is not 32-bits multiple */
471 if (limit != 0U)
472 {
473 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
474 }
475
476 /* Update the SRAM controller state */
477 hsram->State = state;
478
479 /* Process unlocked */
480 __HAL_UNLOCK(hsram);
481 }
482 else
483 {
484 return HAL_ERROR;
485 }
486
487 return HAL_OK;
488 }
489
490 /**
491 * @brief Writes 16-bit buffer to SRAM memory.
492 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
493 * the configuration information for SRAM module.
494 * @param pAddress Pointer to write start address
495 * @param pSrcBuffer Pointer to source buffer to write
496 * @param BufferSize Size of the buffer to write to memory
497 * @retval HAL status
498 */
HAL_SRAM_Write_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)499 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
500 {
501 uint32_t size;
502 __IO uint32_t *psramaddress = pAddress;
503 uint16_t * psrcbuff = pSrcBuffer;
504 uint8_t limit;
505
506 /* Check the SRAM controller state */
507 if (hsram->State == HAL_SRAM_STATE_READY)
508 {
509 /* Process Locked */
510 __HAL_LOCK(hsram);
511
512 /* Update the SRAM controller state */
513 hsram->State = HAL_SRAM_STATE_BUSY;
514
515 /* Check if the size is a 32-bits mulitple */
516 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
517
518 /* Write data to memory */
519 for (size = BufferSize; size != limit; size-=2U)
520 {
521 *psramaddress = (uint32_t)(*psrcbuff);
522 psrcbuff++;
523 *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
524 psrcbuff++;
525 psramaddress++;
526 }
527
528 /* Write last 16-bits if size is not 32-bits multiple */
529 if (limit != 0U)
530 {
531 *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
532 }
533
534 /* Update the SRAM controller state */
535 hsram->State = HAL_SRAM_STATE_READY;
536
537 /* Process unlocked */
538 __HAL_UNLOCK(hsram);
539 }
540 else
541 {
542 return HAL_ERROR;
543 }
544
545 return HAL_OK;
546 }
547
548 /**
549 * @brief Reads 32-bit buffer from SRAM memory.
550 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
551 * the configuration information for SRAM module.
552 * @param pAddress Pointer to read start address
553 * @param pDstBuffer Pointer to destination buffer
554 * @param BufferSize Size of the buffer to read from memory
555 * @retval HAL status
556 */
HAL_SRAM_Read_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)557 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
558 {
559 uint32_t size;
560 __IO uint32_t * psramaddress = pAddress;
561 uint32_t * pdestbuff = pDstBuffer;
562 HAL_SRAM_StateTypeDef state = hsram->State;
563
564 /* Check the SRAM controller state */
565 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
566 {
567 /* Process Locked */
568 __HAL_LOCK(hsram);
569
570 /* Update the SRAM controller state */
571 hsram->State = HAL_SRAM_STATE_BUSY;
572
573 /* Read data from memory */
574 for (size = BufferSize; size != 0U; size--)
575 {
576 *pdestbuff = *psramaddress;
577 pdestbuff++;
578 psramaddress++;
579 }
580
581 /* Update the SRAM controller state */
582 hsram->State = state;
583
584 /* Process unlocked */
585 __HAL_UNLOCK(hsram);
586 }
587 else
588 {
589 return HAL_ERROR;
590 }
591
592 return HAL_OK;
593 }
594
595 /**
596 * @brief Writes 32-bit buffer to SRAM memory.
597 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
598 * the configuration information for SRAM module.
599 * @param pAddress Pointer to write start address
600 * @param pSrcBuffer Pointer to source buffer to write
601 * @param BufferSize Size of the buffer to write to memory
602 * @retval HAL status
603 */
HAL_SRAM_Write_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)604 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
605 {
606 uint32_t size;
607 __IO uint32_t * psramaddress = pAddress;
608 uint32_t * psrcbuff = pSrcBuffer;
609
610 /* Check the SRAM controller state */
611 if (hsram->State == HAL_SRAM_STATE_READY)
612 {
613 /* Process Locked */
614 __HAL_LOCK(hsram);
615
616 /* Update the SRAM controller state */
617 hsram->State = HAL_SRAM_STATE_BUSY;
618
619 /* Write data to memory */
620 for (size = BufferSize; size != 0U; size--)
621 {
622 *psramaddress = *psrcbuff;
623 psrcbuff++;
624 psramaddress++;
625 }
626
627 /* Update the SRAM controller state */
628 hsram->State = HAL_SRAM_STATE_READY;
629
630 /* Process unlocked */
631 __HAL_UNLOCK(hsram);
632 }
633 else
634 {
635 return HAL_ERROR;
636 }
637
638 return HAL_OK;
639 }
640
641 /**
642 * @brief Reads a Words data from the SRAM memory using DMA transfer.
643 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
644 * the configuration information for SRAM module.
645 * @param pAddress Pointer to read start address
646 * @param pDstBuffer Pointer to destination buffer
647 * @param BufferSize Size of the buffer to read from memory
648 * @retval HAL status
649 */
HAL_SRAM_Read_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)650 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
651 {
652 HAL_StatusTypeDef status;
653 HAL_SRAM_StateTypeDef state = hsram->State;
654
655 /* Check the SRAM controller state */
656 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
657 {
658 /* Process Locked */
659 __HAL_LOCK(hsram);
660
661 /* Update the SRAM controller state */
662 hsram->State = HAL_SRAM_STATE_BUSY;
663
664 /* Configure DMA user callbacks */
665 if (state == HAL_SRAM_STATE_READY)
666 {
667 hsram->hdma->XferCpltCallback = SRAM_DMACplt;
668 }
669 else
670 {
671 hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
672 }
673 hsram->hdma->XferErrorCallback = SRAM_DMAError;
674
675 /* Enable the DMA Stream */
676 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
677
678 /* Process unlocked */
679 __HAL_UNLOCK(hsram);
680 }
681 else
682 {
683 return HAL_ERROR;
684 }
685
686 return status;
687 }
688
689 /**
690 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
691 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
692 * the configuration information for SRAM module.
693 * @param pAddress Pointer to write start address
694 * @param pSrcBuffer Pointer to source buffer to write
695 * @param BufferSize Size of the buffer to write to memory
696 * @retval HAL status
697 */
HAL_SRAM_Write_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)698 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
699 {
700 HAL_StatusTypeDef status;
701
702 /* Check the SRAM controller state */
703 if (hsram->State == HAL_SRAM_STATE_READY)
704 {
705 /* Process Locked */
706 __HAL_LOCK(hsram);
707
708 /* Update the SRAM controller state */
709 hsram->State = HAL_SRAM_STATE_BUSY;
710
711 /* Configure DMA user callbacks */
712 hsram->hdma->XferCpltCallback = SRAM_DMACplt;
713 hsram->hdma->XferErrorCallback = SRAM_DMAError;
714
715 /* Enable the DMA Stream */
716 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
717
718 /* Process unlocked */
719 __HAL_UNLOCK(hsram);
720 }
721 else
722 {
723 return HAL_ERROR;
724 }
725
726 return status;
727 }
728
729 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
730 /**
731 * @brief Register a User SRAM Callback
732 * To be used instead of the weak (surcharged) predefined callback
733 * @param hsram : SRAM handle
734 * @param CallbackId : ID of the callback to be registered
735 * This parameter can be one of the following values:
736 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
737 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
738 * @param pCallback : pointer to the Callback function
739 * @retval status
740 */
HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_CallbackTypeDef pCallback)741 HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
742 {
743 HAL_StatusTypeDef status = HAL_OK;
744 HAL_SRAM_StateTypeDef state;
745
746 if(pCallback == NULL)
747 {
748 return HAL_ERROR;
749 }
750
751 /* Process locked */
752 __HAL_LOCK(hsram);
753
754 state = hsram->State;
755 if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
756 {
757 switch (CallbackId)
758 {
759 case HAL_SRAM_MSP_INIT_CB_ID :
760 hsram->MspInitCallback = pCallback;
761 break;
762 case HAL_SRAM_MSP_DEINIT_CB_ID :
763 hsram->MspDeInitCallback = pCallback;
764 break;
765 default :
766 /* update return status */
767 status = HAL_ERROR;
768 break;
769 }
770 }
771 else
772 {
773 /* update return status */
774 status = HAL_ERROR;
775 }
776
777 /* Release Lock */
778 __HAL_UNLOCK(hsram);
779 return status;
780 }
781
782 /**
783 * @brief Unregister a User SRAM Callback
784 * SRAM Callback is redirected to the weak (surcharged) predefined callback
785 * @param hsram : SRAM handle
786 * @param CallbackId : ID of the callback to be unregistered
787 * This parameter can be one of the following values:
788 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
789 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
790 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
791 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
792 * @retval status
793 */
HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId)794 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
795 {
796 HAL_StatusTypeDef status = HAL_OK;
797 HAL_SRAM_StateTypeDef state;
798
799 /* Process locked */
800 __HAL_LOCK(hsram);
801
802 state = hsram->State;
803 if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
804 {
805 switch (CallbackId)
806 {
807 case HAL_SRAM_MSP_INIT_CB_ID :
808 hsram->MspInitCallback = HAL_SRAM_MspInit;
809 break;
810 case HAL_SRAM_MSP_DEINIT_CB_ID :
811 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
812 break;
813 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
814 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
815 break;
816 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
817 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
818 break;
819 default :
820 /* update return status */
821 status = HAL_ERROR;
822 break;
823 }
824 }
825 else if(state == HAL_SRAM_STATE_RESET)
826 {
827 switch (CallbackId)
828 {
829 case HAL_SRAM_MSP_INIT_CB_ID :
830 hsram->MspInitCallback = HAL_SRAM_MspInit;
831 break;
832 case HAL_SRAM_MSP_DEINIT_CB_ID :
833 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
834 break;
835 default :
836 /* update return status */
837 status = HAL_ERROR;
838 break;
839 }
840 }
841 else
842 {
843 /* update return status */
844 status = HAL_ERROR;
845 }
846
847 /* Release Lock */
848 __HAL_UNLOCK(hsram);
849 return status;
850 }
851
852 /**
853 * @brief Register a User SRAM Callback for DMA transfers
854 * To be used instead of the weak (surcharged) predefined callback
855 * @param hsram : SRAM handle
856 * @param CallbackId : ID of the callback to be registered
857 * This parameter can be one of the following values:
858 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
859 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
860 * @param pCallback : pointer to the Callback function
861 * @retval status
862 */
HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_DmaCallbackTypeDef pCallback)863 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
864 {
865 HAL_StatusTypeDef status = HAL_OK;
866 HAL_SRAM_StateTypeDef state;
867
868 if(pCallback == NULL)
869 {
870 return HAL_ERROR;
871 }
872
873 /* Process locked */
874 __HAL_LOCK(hsram);
875
876 state = hsram->State;
877 if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
878 {
879 switch (CallbackId)
880 {
881 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
882 hsram->DmaXferCpltCallback = pCallback;
883 break;
884 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
885 hsram->DmaXferErrorCallback = pCallback;
886 break;
887 default :
888 /* update return status */
889 status = HAL_ERROR;
890 break;
891 }
892 }
893 else
894 {
895 /* update return status */
896 status = HAL_ERROR;
897 }
898
899 /* Release Lock */
900 __HAL_UNLOCK(hsram);
901 return status;
902 }
903 #endif
904
905 /**
906 * @}
907 */
908
909 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
910 * @brief Control functions
911 *
912 @verbatim
913 ==============================================================================
914 ##### SRAM Control functions #####
915 ==============================================================================
916 [..]
917 This subsection provides a set of functions allowing to control dynamically
918 the SRAM interface.
919
920 @endverbatim
921 * @{
922 */
923
924 /**
925 * @brief Enables dynamically SRAM write operation.
926 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
927 * the configuration information for SRAM module.
928 * @retval HAL status
929 */
HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef * hsram)930 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
931 {
932 /* Check the SRAM controller state */
933 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
934 {
935 /* Process Locked */
936 __HAL_LOCK(hsram);
937
938 /* Update the SRAM controller state */
939 hsram->State = HAL_SRAM_STATE_BUSY;
940
941 /* Enable write operation */
942 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
943
944 /* Update the SRAM controller state */
945 hsram->State = HAL_SRAM_STATE_READY;
946
947 /* Process unlocked */
948 __HAL_UNLOCK(hsram);
949 }
950 else
951 {
952 return HAL_ERROR;
953 }
954
955 return HAL_OK;
956 }
957
958 /**
959 * @brief Disables dynamically SRAM write operation.
960 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
961 * the configuration information for SRAM module.
962 * @retval HAL status
963 */
HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef * hsram)964 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
965 {
966 /* Check the SRAM controller state */
967 if(hsram->State == HAL_SRAM_STATE_READY)
968 {
969 /* Process Locked */
970 __HAL_LOCK(hsram);
971
972 /* Update the SRAM controller state */
973 hsram->State = HAL_SRAM_STATE_BUSY;
974
975 /* Disable write operation */
976 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
977
978 /* Update the SRAM controller state */
979 hsram->State = HAL_SRAM_STATE_PROTECTED;
980
981 /* Process unlocked */
982 __HAL_UNLOCK(hsram);
983 }
984 else
985 {
986 return HAL_ERROR;
987 }
988
989 return HAL_OK;
990 }
991
992 /**
993 * @}
994 */
995
996 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
997 * @brief Peripheral State functions
998 *
999 @verbatim
1000 ==============================================================================
1001 ##### SRAM State functions #####
1002 ==============================================================================
1003 [..]
1004 This subsection permits to get in run-time the status of the SRAM controller
1005 and the data flow.
1006
1007 @endverbatim
1008 * @{
1009 */
1010
1011 /**
1012 * @brief Returns the SRAM controller state
1013 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
1014 * the configuration information for SRAM module.
1015 * @retval HAL state
1016 */
HAL_SRAM_GetState(SRAM_HandleTypeDef * hsram)1017 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
1018 {
1019 return hsram->State;
1020 }
1021
1022 /**
1023 * @}
1024 */
1025
1026 /**
1027 * @}
1028 */
1029
1030 /**
1031 @cond 0
1032 */
1033 /**
1034 * @brief DMA SRAM process complete callback.
1035 * @param hdma : DMA handle
1036 * @retval None
1037 */
SRAM_DMACplt(DMA_HandleTypeDef * hdma)1038 static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
1039 {
1040 SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
1041
1042 /* Disable the DMA channel */
1043 __HAL_DMA_DISABLE(hdma);
1044
1045 /* Update the SRAM controller state */
1046 hsram->State = HAL_SRAM_STATE_READY;
1047
1048 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1049 hsram->DmaXferCpltCallback(hdma);
1050 #else
1051 HAL_SRAM_DMA_XferCpltCallback(hdma);
1052 #endif
1053 }
1054
1055 /**
1056 * @brief DMA SRAM process complete callback.
1057 * @param hdma : DMA handle
1058 * @retval None
1059 */
SRAM_DMACpltProt(DMA_HandleTypeDef * hdma)1060 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
1061 {
1062 SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
1063
1064 /* Disable the DMA channel */
1065 __HAL_DMA_DISABLE(hdma);
1066
1067 /* Update the SRAM controller state */
1068 hsram->State = HAL_SRAM_STATE_PROTECTED;
1069
1070 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1071 hsram->DmaXferCpltCallback(hdma);
1072 #else
1073 HAL_SRAM_DMA_XferCpltCallback(hdma);
1074 #endif
1075 }
1076
1077 /**
1078 * @brief DMA SRAM error callback.
1079 * @param hdma : DMA handle
1080 * @retval None
1081 */
SRAM_DMAError(DMA_HandleTypeDef * hdma)1082 static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
1083 {
1084 SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
1085
1086 /* Disable the DMA channel */
1087 __HAL_DMA_DISABLE(hdma);
1088
1089 /* Update the SRAM controller state */
1090 hsram->State = HAL_SRAM_STATE_ERROR;
1091
1092 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1093 hsram->DmaXferErrorCallback(hdma);
1094 #else
1095 HAL_SRAM_DMA_XferErrorCallback(hdma);
1096 #endif
1097 }
1098 /**
1099 @endcond
1100 */
1101
1102 /**
1103 * @}
1104 */
1105
1106 #endif /* HAL_SRAM_MODULE_ENABLED */
1107
1108 /**
1109 * @}
1110 */
1111
1112
