1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32l5xx_ll_adc.h"
22 #include "stm32l5xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32L5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* APB prescaler 16, ADC prescaler 4. */
62 /* - ADC clock from asynchronous clock (PLLSAI) with prescaler 1, */
63 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
64 /* CPU clock frequency max 72MHz, PLLSAI freq min 26MHz: ratio 4. */
65 /* Unit: CPU cycles. */
66 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
67 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
69
70 /**
71 * @}
72 */
73
74 /* Private macros ------------------------------------------------------------*/
75
76 /** @addtogroup ADC_LL_Private_Macros
77 * @{
78 */
79
80 /* Check of parameters for configuration of ADC hierarchical scope: */
81 /* common to several ADC instances. */
82 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
83 (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
84 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
85 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
86 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
98 )
99
100 /* Check of parameters for configuration of ADC hierarchical scope: */
101 /* ADC instance. */
102 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
103 (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
104 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
105 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
106 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
107 )
108
109 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
110 (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
111 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
112 )
113
114 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
115 (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
116 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
117 )
118
119 /* Check of parameters for configuration of ADC hierarchical scope: */
120 /* ADC group regular */
121 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
122 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
123 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
124 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
125 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
126 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
127 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
128 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
129 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
130 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
131 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
132 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
133 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
134 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
135 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
136 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
139 )
140
141 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
142 (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
143 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
144 )
145
146 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
147 (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
148 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
149 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
150 )
151
152 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
153 (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
154 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
155 )
156
157 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
158 (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
159 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
160 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
161 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
162 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
163 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
164 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
165 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
166 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
167 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
168 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
169 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
170 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
171 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
172 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
173 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
174 )
175
176 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
177 (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
178 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
179 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
180 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
181 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
182 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
183 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
184 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
185 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
186 )
187
188 /* Check of parameters for configuration of ADC hierarchical scope: */
189 /* ADC group injected */
190 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
191 (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
192 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
193 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
194 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
195 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
196 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
197 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
198 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
199 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
200 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
201 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
202 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
203 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
204 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
205 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
206 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
207 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
208 )
209
210 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
211 (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
212 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
213 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
214 )
215
216 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
217 (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
218 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
219 )
220
221 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
222 (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
223 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
224 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
225 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
226 )
227
228 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
229 (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
230 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
231 )
232
233 #if defined(ADC_MULTIMODE_SUPPORT)
234 /* Check of parameters for configuration of ADC hierarchical scope: */
235 /* multimode. */
236 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
237 (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
238 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
239 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
240 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
241 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
242 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
243 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
244 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
245 )
246
247 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
248 (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
249 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
250 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
251 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
252 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \
253 )
254
255 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
256 (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
257 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
258 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
259 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
260 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
261 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
262 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
263 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
264 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
265 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
266 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
267 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
268 )
269
270 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
271 (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
272 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
273 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
274 )
275
276 #endif /* ADC_MULTIMODE_SUPPORT */
277 /**
278 * @}
279 */
280
281
282 /* Private function prototypes -----------------------------------------------*/
283
284 /* Exported functions --------------------------------------------------------*/
285 /** @addtogroup ADC_LL_Exported_Functions
286 * @{
287 */
288
289 /** @addtogroup ADC_LL_EF_Init
290 * @{
291 */
292
293 /**
294 * @brief De-initialize registers of all ADC instances belonging to
295 * the same ADC common instance to their default reset values.
296 * @note This function is performing a hard reset, using high level
297 * clock source RCC ADC reset.
298 * Caution: On this STM32 series, if several ADC instances are available
299 * on the selected device, RCC ADC reset will reset
300 * all ADC instances belonging to the common ADC instance.
301 * To de-initialize only 1 ADC instance, use
302 * function @ref LL_ADC_DeInit().
303 * @param ADCxy_COMMON ADC common instance
304 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
305 * @retval An ErrorStatus enumeration value:
306 * - SUCCESS: ADC common registers are de-initialized
307 * - ERROR: not applicable
308 */
LL_ADC_CommonDeInit(const ADC_Common_TypeDef * ADCxy_COMMON)309 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON)
310 {
311 /* Check the parameters */
312 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
313
314 /* Prevent unused argument compilation warning */
315 (void)(ADCxy_COMMON);
316
317 /* Force reset of ADC clock (core clock) */
318 LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
319
320 /* Release reset of ADC clock (core clock) */
321 LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);
322
323 return SUCCESS;
324 }
325
326 /**
327 * @brief Initialize some features of ADC common parameters
328 * (all ADC instances belonging to the same ADC common instance)
329 * and multimode (for devices with several ADC instances available).
330 * @note The setting of ADC common parameters is conditioned to
331 * ADC instances state:
332 * All ADC instances belonging to the same ADC common instance
333 * must be disabled.
334 * @param ADCxy_COMMON ADC common instance
335 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
336 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
337 * @retval An ErrorStatus enumeration value:
338 * - SUCCESS: ADC common registers are initialized
339 * - ERROR: ADC common registers are not initialized
340 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,const LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)341 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
342 {
343 ErrorStatus status = SUCCESS;
344
345 /* Check the parameters */
346 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
347 assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
348
349 #if defined(ADC_MULTIMODE_SUPPORT)
350 assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode));
351 if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
352 {
353 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(pADC_CommonInitStruct->MultiDMATransfer));
354 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay));
355 }
356 #endif /* ADC_MULTIMODE_SUPPORT */
357
358 /* Note: Hardware constraint (refer to description of functions */
359 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
360 /* On this STM32 series, setting of these features is conditioned to */
361 /* ADC state: */
362 /* All ADC instances of the ADC common group must be disabled. */
363 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
364 {
365 /* Configuration of ADC hierarchical scope: */
366 /* - common to several ADC */
367 /* (all ADC instances belonging to the same ADC common instance) */
368 /* - Set ADC clock (conversion clock) */
369 /* - multimode (if several ADC instances available on the */
370 /* selected device) */
371 /* - Set ADC multimode configuration */
372 /* - Set ADC multimode DMA transfer */
373 /* - Set ADC multimode: delay between 2 sampling phases */
374 #if defined(ADC_MULTIMODE_SUPPORT)
375 if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
376 {
377 MODIFY_REG(ADCxy_COMMON->CCR,
378 ADC_CCR_CKMODE
379 | ADC_CCR_PRESC
380 | ADC_CCR_DUAL
381 | ADC_CCR_MDMA
382 | ADC_CCR_DELAY
383 ,
384 pADC_CommonInitStruct->CommonClock
385 | pADC_CommonInitStruct->Multimode
386 | pADC_CommonInitStruct->MultiDMATransfer
387 | pADC_CommonInitStruct->MultiTwoSamplingDelay
388 );
389 }
390 else
391 {
392 MODIFY_REG(ADCxy_COMMON->CCR,
393 ADC_CCR_CKMODE
394 | ADC_CCR_PRESC
395 | ADC_CCR_DUAL
396 | ADC_CCR_MDMA
397 | ADC_CCR_DELAY
398 ,
399 pADC_CommonInitStruct->CommonClock
400 | LL_ADC_MULTI_INDEPENDENT
401 );
402 }
403 #else
404 LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
405 #endif /* ADC_MULTIMODE_SUPPORT */
406 }
407 else
408 {
409 /* Initialization error: One or several ADC instances belonging to */
410 /* the same ADC common instance are not disabled. */
411 status = ERROR;
412 }
413
414 return status;
415 }
416
417 /**
418 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
419 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
420 * whose fields will be set to default values.
421 * @retval None
422 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)423 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
424 {
425 /* Set pADC_CommonInitStruct fields to default values */
426 /* Set fields of ADC common */
427 /* (all ADC instances belonging to the same ADC common instance) */
428 pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
429
430 #if defined(ADC_MULTIMODE_SUPPORT)
431 /* Set fields of ADC multimode */
432 pADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
433 pADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
434 pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
435 #endif /* ADC_MULTIMODE_SUPPORT */
436 }
437
438 /**
439 * @brief De-initialize registers of the selected ADC instance
440 * to their default reset values.
441 * @note To reset all ADC instances quickly (perform a hard reset),
442 * use function @ref LL_ADC_CommonDeInit().
443 * @note If this functions returns error status, it means that ADC instance
444 * is in an unknown state.
445 * In this case, perform a hard reset using high level
446 * clock source RCC ADC reset.
447 * Caution: On this STM32 series, if several ADC instances are available
448 * on the selected device, RCC ADC reset will reset
449 * all ADC instances belonging to the common ADC instance.
450 * Refer to function @ref LL_ADC_CommonDeInit().
451 * @param ADCx ADC instance
452 * @retval An ErrorStatus enumeration value:
453 * - SUCCESS: ADC registers are de-initialized
454 * - ERROR: ADC registers are not de-initialized
455 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)456 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
457 {
458 ErrorStatus status = SUCCESS;
459
460 __IO uint32_t timeout_cpu_cycles = 0UL;
461
462 /* Check the parameters */
463 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
464
465 /* Disable ADC instance if not already disabled. */
466 if (LL_ADC_IsEnabled(ADCx) == 1UL)
467 {
468 /* Stop potential ADC conversion on going on ADC group regular. */
469 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
470 {
471 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
472 {
473 LL_ADC_REG_StopConversion(ADCx);
474 }
475 }
476
477 /* Stop potential ADC conversion on going on ADC group injected. */
478 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
479 {
480 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
481 {
482 LL_ADC_INJ_StopConversion(ADCx);
483 }
484 }
485
486 /* Wait for ADC conversions are effectively stopped */
487 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
488 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
489 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
490 {
491 timeout_cpu_cycles--;
492 if (timeout_cpu_cycles == 0UL)
493 {
494 /* Time-out error */
495 status = ERROR;
496 break;
497 }
498 }
499
500 /* Flush group injected contexts queue (register JSQR): */
501 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
502 /* contexts queue is maintained with the last active context). */
503 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
504
505 /* Disable the ADC instance */
506 LL_ADC_Disable(ADCx);
507
508 /* Wait for ADC instance is effectively disabled */
509 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
510 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
511 {
512 timeout_cpu_cycles--;
513 if (timeout_cpu_cycles == 0UL)
514 {
515 /* Time-out error */
516 status = ERROR;
517 break;
518 }
519 }
520 }
521
522 /* Check whether ADC state is compliant with expected state */
523 if (READ_BIT(ADCx->CR,
524 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
525 | ADC_CR_ADDIS | ADC_CR_ADEN)
526 )
527 == 0UL)
528 {
529 /* ========== Reset ADC registers ========== */
530 /* Reset register IER */
531 CLEAR_BIT(ADCx->IER,
532 (LL_ADC_IT_ADRDY
533 | LL_ADC_IT_EOC
534 | LL_ADC_IT_EOS
535 | LL_ADC_IT_OVR
536 | LL_ADC_IT_EOSMP
537 | LL_ADC_IT_JEOC
538 | LL_ADC_IT_JEOS
539 | LL_ADC_IT_JQOVF
540 | LL_ADC_IT_AWD1
541 | LL_ADC_IT_AWD2
542 | LL_ADC_IT_AWD3
543 )
544 );
545
546 /* Reset register ISR */
547 SET_BIT(ADCx->ISR,
548 (LL_ADC_FLAG_ADRDY
549 | LL_ADC_FLAG_EOC
550 | LL_ADC_FLAG_EOS
551 | LL_ADC_FLAG_OVR
552 | LL_ADC_FLAG_EOSMP
553 | LL_ADC_FLAG_JEOC
554 | LL_ADC_FLAG_JEOS
555 | LL_ADC_FLAG_JQOVF
556 | LL_ADC_FLAG_AWD1
557 | LL_ADC_FLAG_AWD2
558 | LL_ADC_FLAG_AWD3
559 )
560 );
561
562 /* Reset register CR */
563 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
564 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
565 /* access mode "read-set": no direct reset applicable. */
566 /* - Reset Calibration mode to default setting (single ended). */
567 /* - Disable ADC internal voltage regulator. */
568 /* - Enable ADC deep power down. */
569 /* Note: ADC internal voltage regulator disable and ADC deep power */
570 /* down enable are conditioned to ADC state disabled: */
571 /* already done above. */
572 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
573 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
574
575 /* Reset register CFGR */
576 MODIFY_REG(ADCx->CFGR,
577 (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
578 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
579 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
580 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
581 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
582 | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN),
583 ADC_CFGR_JQDIS
584 );
585
586 /* Reset register CFGR2 */
587 CLEAR_BIT(ADCx->CFGR2,
588 (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
589 | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
590 );
591
592 /* Reset register SMPR1 */
593 CLEAR_BIT(ADCx->SMPR1,
594 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
595 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
596 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
597 );
598
599 /* Reset register SMPR2 */
600 CLEAR_BIT(ADCx->SMPR2,
601 (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
602 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
603 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
604 );
605
606 /* Reset register TR1 */
607 MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
608
609 /* Reset register TR2 */
610 MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
611
612 /* Reset register TR3 */
613 MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
614
615 /* Reset register SQR1 */
616 CLEAR_BIT(ADCx->SQR1,
617 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
618 | ADC_SQR1_SQ1 | ADC_SQR1_L)
619 );
620
621 /* Reset register SQR2 */
622 CLEAR_BIT(ADCx->SQR2,
623 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
624 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
625 );
626
627 /* Reset register SQR3 */
628 CLEAR_BIT(ADCx->SQR3,
629 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
630 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
631 );
632
633 /* Reset register SQR4 */
634 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
635
636 /* Reset register JSQR */
637 CLEAR_BIT(ADCx->JSQR,
638 (ADC_JSQR_JL
639 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
640 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
641 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
642 );
643
644 /* Reset register DR */
645 /* Note: bits in access mode read only, no direct reset applicable */
646
647 /* Reset register OFR1 */
648 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
649 /* Reset register OFR2 */
650 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
651 /* Reset register OFR3 */
652 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
653 /* Reset register OFR4 */
654 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
655
656 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
657 /* Note: bits in access mode read only, no direct reset applicable */
658
659 /* Reset register AWD2CR */
660 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
661
662 /* Reset register AWD3CR */
663 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
664
665 /* Reset register DIFSEL */
666 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
667
668 /* Reset register CALFACT */
669 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
670 }
671 else
672 {
673 /* ADC instance is in an unknown state */
674 /* Need to performing a hard reset of ADC instance, using high level */
675 /* clock source RCC ADC reset. */
676 /* Caution: On this STM32 series, if several ADC instances are available */
677 /* on the selected device, RCC ADC reset will reset */
678 /* all ADC instances belonging to the common ADC instance. */
679 /* Caution: On this STM32 series, if several ADC instances are available */
680 /* on the selected device, RCC ADC reset will reset */
681 /* all ADC instances belonging to the common ADC instance. */
682 status = ERROR;
683 }
684
685 return status;
686 }
687
688 /**
689 * @brief Initialize some features of ADC instance.
690 * @note These parameters have an impact on ADC scope: ADC instance.
691 * Affects both group regular and group injected (availability
692 * of ADC group injected depends on STM32 series).
693 * Refer to corresponding unitary functions into
694 * @ref ADC_LL_EF_Configuration_ADC_Instance .
695 * @note The setting of these parameters by function @ref LL_ADC_Init()
696 * is conditioned to ADC state:
697 * ADC instance must be disabled.
698 * This condition is applied to all ADC features, for efficiency
699 * and compatibility over all STM32 series. However, the different
700 * features can be set under different ADC state conditions
701 * (setting possible with ADC enabled without conversion on going,
702 * ADC enabled with conversion on going, ...)
703 * Each feature can be updated afterwards with a unitary function
704 * and potentially with ADC in a different state than disabled,
705 * refer to description of each function for setting
706 * conditioned to ADC state.
707 * @note After using this function, some other features must be configured
708 * using LL unitary functions.
709 * The minimum configuration remaining to be done is:
710 * - Set ADC group regular or group injected sequencer:
711 * map channel on the selected sequencer rank.
712 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
713 * - Set ADC channel sampling time
714 * Refer to function LL_ADC_SetChannelSamplingTime();
715 * @param ADCx ADC instance
716 * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
717 * @retval An ErrorStatus enumeration value:
718 * - SUCCESS: ADC registers are initialized
719 * - ERROR: ADC registers are not initialized
720 */
LL_ADC_Init(ADC_TypeDef * ADCx,const LL_ADC_InitTypeDef * pADC_InitStruct)721 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct)
722 {
723 ErrorStatus status = SUCCESS;
724
725 /* Check the parameters */
726 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
727
728 assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
729 assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
730 assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
731
732 /* Note: Hardware constraint (refer to description of this function): */
733 /* ADC instance must be disabled. */
734 if (LL_ADC_IsEnabled(ADCx) == 0UL)
735 {
736 /* Configuration of ADC hierarchical scope: */
737 /* - ADC instance */
738 /* - Set ADC data resolution */
739 /* - Set ADC conversion data alignment */
740 /* - Set ADC low power mode */
741 MODIFY_REG(ADCx->CFGR,
742 ADC_CFGR_RES
743 | ADC_CFGR_ALIGN
744 | ADC_CFGR_AUTDLY
745 ,
746 pADC_InitStruct->Resolution
747 | pADC_InitStruct->DataAlignment
748 | pADC_InitStruct->LowPowerMode
749 );
750
751 }
752 else
753 {
754 /* Initialization error: ADC instance is not disabled. */
755 status = ERROR;
756 }
757
758 return status;
759 }
760
761 /**
762 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
763 * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
764 * whose fields will be set to default values.
765 * @retval None
766 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * pADC_InitStruct)767 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
768 {
769 /* Set pADC_InitStruct fields to default values */
770 /* Set fields of ADC instance */
771 pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
772 pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
773 pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
774
775 }
776
777 /**
778 * @brief Initialize some features of ADC group regular.
779 * @note These parameters have an impact on ADC scope: ADC group regular.
780 * Refer to corresponding unitary functions into
781 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
782 * (functions with prefix "REG").
783 * @note The setting of these parameters by function @ref LL_ADC_Init()
784 * is conditioned to ADC state:
785 * ADC instance must be disabled.
786 * This condition is applied to all ADC features, for efficiency
787 * and compatibility over all STM32 series. However, the different
788 * features can be set under different ADC state conditions
789 * (setting possible with ADC enabled without conversion on going,
790 * ADC enabled with conversion on going, ...)
791 * Each feature can be updated afterwards with a unitary function
792 * and potentially with ADC in a different state than disabled,
793 * refer to description of each function for setting
794 * conditioned to ADC state.
795 * @note After using this function, other features must be configured
796 * using LL unitary functions.
797 * The minimum configuration remaining to be done is:
798 * - Set ADC group regular or group injected sequencer:
799 * map channel on the selected sequencer rank.
800 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
801 * - Set ADC channel sampling time
802 * Refer to function LL_ADC_SetChannelSamplingTime();
803 * @param ADCx ADC instance
804 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
805 * @retval An ErrorStatus enumeration value:
806 * - SUCCESS: ADC registers are initialized
807 * - ERROR: ADC registers are not initialized
808 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,const LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)809 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
810 {
811 ErrorStatus status = SUCCESS;
812
813 /* Check the parameters */
814 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
815 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
816 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
817 if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
818 {
819 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
820
821 /* ADC group regular continuous mode and discontinuous mode */
822 /* can not be enabled simultenaeously */
823 assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
824 || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
825 }
826 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
827 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
828 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
829
830 /* Note: Hardware constraint (refer to description of this function): */
831 /* ADC instance must be disabled. */
832 if (LL_ADC_IsEnabled(ADCx) == 0UL)
833 {
834 /* Configuration of ADC hierarchical scope: */
835 /* - ADC group regular */
836 /* - Set ADC group regular trigger source */
837 /* - Set ADC group regular sequencer length */
838 /* - Set ADC group regular sequencer discontinuous mode */
839 /* - Set ADC group regular continuous mode */
840 /* - Set ADC group regular conversion data transfer: no transfer or */
841 /* transfer by DMA, and DMA requests mode */
842 /* - Set ADC group regular overrun behavior */
843 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
844 /* setting of trigger source to SW start. */
845 if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
846 {
847 MODIFY_REG(ADCx->CFGR,
848 ADC_CFGR_EXTSEL
849 | ADC_CFGR_EXTEN
850 | ADC_CFGR_DISCEN
851 | ADC_CFGR_DISCNUM
852 | ADC_CFGR_CONT
853 | ADC_CFGR_DMAEN
854 | ADC_CFGR_DMACFG
855 | ADC_CFGR_OVRMOD
856 ,
857 pADC_RegInitStruct->TriggerSource
858 | pADC_RegInitStruct->SequencerDiscont
859 | pADC_RegInitStruct->ContinuousMode
860 | pADC_RegInitStruct->DMATransfer
861 | pADC_RegInitStruct->Overrun
862 );
863 }
864 else
865 {
866 MODIFY_REG(ADCx->CFGR,
867 ADC_CFGR_EXTSEL
868 | ADC_CFGR_EXTEN
869 | ADC_CFGR_DISCEN
870 | ADC_CFGR_DISCNUM
871 | ADC_CFGR_CONT
872 | ADC_CFGR_DMAEN
873 | ADC_CFGR_DMACFG
874 | ADC_CFGR_OVRMOD
875 ,
876 pADC_RegInitStruct->TriggerSource
877 | LL_ADC_REG_SEQ_DISCONT_DISABLE
878 | pADC_RegInitStruct->ContinuousMode
879 | pADC_RegInitStruct->DMATransfer
880 | pADC_RegInitStruct->Overrun
881 );
882 }
883
884 /* Set ADC group regular sequencer length and scan direction */
885 LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
886 }
887 else
888 {
889 /* Initialization error: ADC instance is not disabled. */
890 status = ERROR;
891 }
892 return status;
893 }
894
895 /**
896 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
897 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
898 * whose fields will be set to default values.
899 * @retval None
900 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)901 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
902 {
903 /* Set pADC_RegInitStruct fields to default values */
904 /* Set fields of ADC group regular */
905 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
906 /* setting of trigger source to SW start. */
907 pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
908 pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
909 pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
910 pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
911 pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
912 pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
913 }
914
915 /**
916 * @brief Initialize some features of ADC group injected.
917 * @note These parameters have an impact on ADC scope: ADC group injected.
918 * Refer to corresponding unitary functions into
919 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
920 * (functions with prefix "INJ").
921 * @note The setting of these parameters by function @ref LL_ADC_Init()
922 * is conditioned to ADC state:
923 * ADC instance must be disabled.
924 * This condition is applied to all ADC features, for efficiency
925 * and compatibility over all STM32 series. However, the different
926 * features can be set under different ADC state conditions
927 * (setting possible with ADC enabled without conversion on going,
928 * ADC enabled with conversion on going, ...)
929 * Each feature can be updated afterwards with a unitary function
930 * and potentially with ADC in a different state than disabled,
931 * refer to description of each function for setting
932 * conditioned to ADC state.
933 * @note After using this function, other features must be configured
934 * using LL unitary functions.
935 * The minimum configuration remaining to be done is:
936 * - Set ADC group injected sequencer:
937 * map channel on the selected sequencer rank.
938 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
939 * - Set ADC channel sampling time
940 * Refer to function LL_ADC_SetChannelSamplingTime();
941 * @note Caution if feature ADC group injected contexts queue is enabled
942 * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
943 * using successively several times this function will appear as
944 * having no effect.
945 * To set several features of ADC group injected, use
946 * function @ref LL_ADC_INJ_ConfigQueueContext().
947 * @param ADCx ADC instance
948 * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
949 * @retval An ErrorStatus enumeration value:
950 * - SUCCESS: ADC registers are initialized
951 * - ERROR: ADC registers are not initialized
952 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,const LL_ADC_INJ_InitTypeDef * pADC_InjInitStruct)953 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
954 {
955 ErrorStatus status = SUCCESS;
956
957 /* Check the parameters */
958 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
959 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(pADC_InjInitStruct->TriggerSource));
960 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_InjInitStruct->SequencerLength));
961 if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
962 {
963 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_InjInitStruct->SequencerDiscont));
964 }
965 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_InjInitStruct->TrigAuto));
966
967 /* Note: Hardware constraint (refer to description of this function): */
968 /* ADC instance must be disabled. */
969 if (LL_ADC_IsEnabled(ADCx) == 0UL)
970 {
971 /* Configuration of ADC hierarchical scope: */
972 /* - ADC group injected */
973 /* - Set ADC group injected trigger source */
974 /* - Set ADC group injected sequencer length */
975 /* - Set ADC group injected sequencer discontinuous mode */
976 /* - Set ADC group injected conversion trigger: independent or */
977 /* from ADC group regular */
978 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
979 /* setting of trigger source to SW start. */
980 if (pADC_InjInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
981 {
982 MODIFY_REG(ADCx->CFGR,
983 ADC_CFGR_JDISCEN
984 | ADC_CFGR_JAUTO
985 ,
986 pADC_InjInitStruct->SequencerDiscont
987 | pADC_InjInitStruct->TrigAuto
988 );
989 }
990 else
991 {
992 MODIFY_REG(ADCx->CFGR,
993 ADC_CFGR_JDISCEN
994 | ADC_CFGR_JAUTO
995 ,
996 LL_ADC_REG_SEQ_DISCONT_DISABLE
997 | pADC_InjInitStruct->TrigAuto
998 );
999 }
1000
1001 MODIFY_REG(ADCx->JSQR,
1002 ADC_JSQR_JEXTSEL
1003 | ADC_JSQR_JEXTEN
1004 | ADC_JSQR_JL
1005 ,
1006 pADC_InjInitStruct->TriggerSource
1007 | pADC_InjInitStruct->SequencerLength
1008 );
1009 }
1010 else
1011 {
1012 /* Initialization error: ADC instance is not disabled. */
1013 status = ERROR;
1014 }
1015 return status;
1016 }
1017
1018 /**
1019 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1020 * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1021 * whose fields will be set to default values.
1022 * @retval None
1023 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * pADC_InjInitStruct)1024 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
1025 {
1026 /* Set pADC_InjInitStruct fields to default values */
1027 /* Set fields of ADC group injected */
1028 pADC_InjInitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1029 pADC_InjInitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1030 pADC_InjInitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1031 pADC_InjInitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1032 }
1033
1034 /**
1035 * @}
1036 */
1037
1038 /**
1039 * @}
1040 */
1041
1042 /**
1043 * @}
1044 */
1045
1046 #endif /* ADC1 || ADC2 */
1047
1048 /**
1049 * @}
1050 */
1051
1052 #endif /* USE_FULL_LL_DRIVER */
1053
