1 /**
2 ******************************************************************************
3 * @file stm32l5xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 The SPI HAL driver can be used as follows:
19
20 (#) Declare a SPI_HandleTypeDef handle structure, for example:
21 SPI_HandleTypeDef hspi;
22
23 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
24 (##) Enable the SPIx interface clock
25 (##) SPI pins configuration
26 (+++) Enable the clock for the SPI GPIOs
27 (+++) Configure these SPI pins as alternate function push-pull
28 (##) NVIC configuration if you need to use interrupt process
29 (+++) Configure the SPIx interrupt priority
30 (+++) Enable the NVIC SPI IRQ handle
31 (##) DMA Configuration if you need to use DMA process
32 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
33 (+++) Enable the DMAx clock
34 (+++) Configure the DMA handle parameters
35 (+++) Configure the DMA Tx or Rx Stream/Channel
36 (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
38
39 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
40 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
41
42 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
43 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
44 by calling the customized HAL_SPI_MspInit() API.
45 [..]
46 Circular mode restriction:
47 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
48 (##) Master 2Lines RxOnly
49 (##) Master 1Line Rx
50 (#) The CRC feature is not managed when the DMA circular mode is enabled
51 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
52 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
53 [..]
54 Master Receive mode restriction:
55 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
56 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
57 does not initiate a new transfer the following procedure has to be respected:
58 (##) HAL_SPI_DeInit()
59 (##) HAL_SPI_Init()
60 [..]
61 Callback registration:
62
63 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
64 allows the user to configure dynamically the driver callbacks.
65 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
66
67 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
68 (++) TxCpltCallback : SPI Tx Completed callback
69 (++) RxCpltCallback : SPI Rx Completed callback
70 (++) TxRxCpltCallback : SPI TxRx Completed callback
71 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
72 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
73 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
74 (++) ErrorCallback : SPI Error callback
75 (++) AbortCpltCallback : SPI Abort callback
76 (++) MspInitCallback : SPI Msp Init callback
77 (++) MspDeInitCallback : SPI Msp DeInit callback
78 This function takes as parameters the HAL peripheral handle, the Callback ID
79 and a pointer to the user callback function.
80
81
82 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
83 weak function.
84 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
85 and the Callback ID.
86 This function allows to reset following callbacks:
87 (++) TxCpltCallback : SPI Tx Completed callback
88 (++) RxCpltCallback : SPI Rx Completed callback
89 (++) TxRxCpltCallback : SPI TxRx Completed callback
90 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
91 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
92 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
93 (++) ErrorCallback : SPI Error callback
94 (++) AbortCpltCallback : SPI Abort callback
95 (++) MspInitCallback : SPI Msp Init callback
96 (++) MspDeInitCallback : SPI Msp DeInit callback
97
98 [..]
99 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
100 all callbacks are set to the corresponding weak functions:
101 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
102 Exception done for MspInit and MspDeInit functions that are
103 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
104 these callbacks are null (not registered beforehand).
105 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
106 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
107
108 [..]
109 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
110 Exception done MspInit/MspDeInit functions that can be registered/unregistered
111 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
112 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
113 Then, the user first registers the MspInit/MspDeInit user callbacks
114 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
115 or HAL_SPI_Init() function.
116
117 [..]
118 When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
119 not defined, the callback registering feature is not available
120 and weak (surcharged) callbacks are used.
121
122 [..]
123 Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
124 the following table resume the max SPI frequency reached with data size 8bits/16bits,
125 according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
126
127 @endverbatim
128
129 Additional table :
130
131 DataSize = SPI_DATASIZE_8BIT:
132 +----------------------------------------------------------------------------------------------+
133 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
134 | Process | Transfer mode |---------------------|----------------------|----------------------|
135 | | | Master | Slave | Master | Slave | Master | Slave |
136 |==============================================================================================|
137 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
138 | X |----------------|----------|----------|-----------|----------|-----------|----------|
139 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
140 | R |----------------|----------|----------|-----------|----------|-----------|----------|
141 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
142 |=========|================|==========|==========|===========|==========|===========|==========|
143 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
144 | |----------------|----------|----------|-----------|----------|-----------|----------|
145 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
146 | X |----------------|----------|----------|-----------|----------|-----------|----------|
147 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
148 |=========|================|==========|==========|===========|==========|===========|==========|
149 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
150 | |----------------|----------|----------|-----------|----------|-----------|----------|
151 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
152 | X |----------------|----------|----------|-----------|----------|-----------|----------|
153 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
154 +----------------------------------------------------------------------------------------------+
155
156 DataSize = SPI_DATASIZE_16BIT:
157 +----------------------------------------------------------------------------------------------+
158 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
159 | Process | Transfer mode |---------------------|----------------------|----------------------|
160 | | | Master | Slave | Master | Slave | Master | Slave |
161 |==============================================================================================|
162 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
163 | X |----------------|----------|----------|-----------|----------|-----------|----------|
164 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
165 | R |----------------|----------|----------|-----------|----------|-----------|----------|
166 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
167 |=========|================|==========|==========|===========|==========|===========|==========|
168 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
169 | |----------------|----------|----------|-----------|----------|-----------|----------|
170 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
171 | X |----------------|----------|----------|-----------|----------|-----------|----------|
172 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
173 |=========|================|==========|==========|===========|==========|===========|==========|
174 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
175 | |----------------|----------|----------|-----------|----------|-----------|----------|
176 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
177 | X |----------------|----------|----------|-----------|----------|-----------|----------|
178 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
179 +----------------------------------------------------------------------------------------------+
180 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
181 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
182 @note
183 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
184 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
185 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
186
187 ******************************************************************************
188 * @attention
189 *
190 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
191 * All rights reserved.</center></h2>
192 *
193 * This software component is licensed by ST under BSD 3-Clause license,
194 * the "License"; You may not use this file except in compliance with the
195 * License. You may obtain a copy of the License at:
196 * opensource.org/licenses/BSD-3-Clause
197 *
198 ******************************************************************************
199 */
200
201 /* Includes ------------------------------------------------------------------*/
202 #include "stm32l5xx_hal.h"
203
204 /** @addtogroup STM32L5xx_HAL_Driver
205 * @{
206 */
207
208 /** @defgroup SPI SPI
209 * @brief SPI HAL module driver
210 * @{
211 */
212 #ifdef HAL_SPI_MODULE_ENABLED
213
214 /* Private typedef -----------------------------------------------------------*/
215 /* Private defines -----------------------------------------------------------*/
216 /** @defgroup SPI_Private_Constants SPI Private Constants
217 * @{
218 */
219 #define SPI_DEFAULT_TIMEOUT 100U
220 /**
221 * @}
222 */
223
224 /* Private macros ------------------------------------------------------------*/
225 /* Private variables ---------------------------------------------------------*/
226 /* Private function prototypes -----------------------------------------------*/
227 /** @defgroup SPI_Private_Functions SPI Private Functions
228 * @{
229 */
230 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
231 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
232 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
233 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
234 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
235 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
236 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
237 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
238 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
239 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
240 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
241 uint32_t Timeout, uint32_t Tickstart);
242 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
243 uint32_t Timeout, uint32_t Tickstart);
244 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
245 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
246 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
247 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
248 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
249 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
250 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
251 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
252 #if (USE_SPI_CRC != 0U)
253 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
254 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
255 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
256 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
257 #endif /* USE_SPI_CRC */
258 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
259 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
260 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
261 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
262 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
263 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
264 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
265 /**
266 * @}
267 */
268
269 /* Exported functions --------------------------------------------------------*/
270 /** @defgroup SPI_Exported_Functions SPI Exported Functions
271 * @{
272 */
273
274 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
275 * @brief Initialization and Configuration functions
276 *
277 @verbatim
278 ===============================================================================
279 ##### Initialization and de-initialization functions #####
280 ===============================================================================
281 [..] This subsection provides a set of functions allowing to initialize and
282 de-initialize the SPIx peripheral:
283
284 (+) User must implement HAL_SPI_MspInit() function in which he configures
285 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
286
287 (+) Call the function HAL_SPI_Init() to configure the selected device with
288 the selected configuration:
289 (++) Mode
290 (++) Direction
291 (++) Data Size
292 (++) Clock Polarity and Phase
293 (++) NSS Management
294 (++) BaudRate Prescaler
295 (++) FirstBit
296 (++) TIMode
297 (++) CRC Calculation
298 (++) CRC Polynomial if CRC enabled
299 (++) CRC Length, used only with Data8 and Data16
300 (++) FIFO reception threshold
301
302 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
303 of the selected SPIx peripheral.
304
305 @endverbatim
306 * @{
307 */
308
309 /**
310 * @brief Initialize the SPI according to the specified parameters
311 * in the SPI_InitTypeDef and initialize the associated handle.
312 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
313 * the configuration information for SPI module.
314 * @retval HAL status
315 */
HAL_SPI_Init(SPI_HandleTypeDef * hspi)316 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
317 {
318 uint32_t frxth;
319
320 /* Check the SPI handle allocation */
321 if (hspi == NULL)
322 {
323 return HAL_ERROR;
324 }
325
326 /* Check the parameters */
327 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
328 assert_param(IS_SPI_MODE(hspi->Init.Mode));
329 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
330 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
331 assert_param(IS_SPI_NSS(hspi->Init.NSS));
332 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
333 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
334 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
335 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
336 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
337 {
338 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
339 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
340
341 if (hspi->Init.Mode == SPI_MODE_MASTER)
342 {
343 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
344 }
345 else
346 {
347 /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
348 hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
349 }
350 }
351 else
352 {
353 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
354
355 /* Force polarity and phase to TI protocaol requirements */
356 hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
357 hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
358 }
359 #if (USE_SPI_CRC != 0U)
360 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
361 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
362 {
363 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
364 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
365 }
366 #else
367 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
368 #endif /* USE_SPI_CRC */
369
370 if (hspi->State == HAL_SPI_STATE_RESET)
371 {
372 /* Allocate lock resource and initialize it */
373 hspi->Lock = HAL_UNLOCKED;
374
375 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
376 /* Init the SPI Callback settings */
377 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
378 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
379 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
380 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
381 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
382 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
383 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
384 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
385
386 if (hspi->MspInitCallback == NULL)
387 {
388 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
389 }
390
391 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
392 hspi->MspInitCallback(hspi);
393 #else
394 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
395 HAL_SPI_MspInit(hspi);
396 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
397 }
398
399 hspi->State = HAL_SPI_STATE_BUSY;
400
401 /* Disable the selected SPI peripheral */
402 __HAL_SPI_DISABLE(hspi);
403
404 /* Align by default the rs fifo threshold on the data size */
405 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
406 {
407 frxth = SPI_RXFIFO_THRESHOLD_HF;
408 }
409 else
410 {
411 frxth = SPI_RXFIFO_THRESHOLD_QF;
412 }
413
414 /* CRC calculation is valid only for 16Bit and 8 Bit */
415 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
416 {
417 /* CRC must be disabled */
418 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
419 }
420
421 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
422 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
423 Communication speed, First bit and CRC calculation state */
424 WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
425 (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
426 (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
427 (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
428 (hspi->Init.NSS & SPI_CR1_SSM) |
429 (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
430 (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
431 (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
432 #if (USE_SPI_CRC != 0U)
433 /*---------------------------- SPIx CRCL Configuration -------------------*/
434 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
435 {
436 /* Align the CRC Length on the data size */
437 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
438 {
439 /* CRC Length aligned on the data size : value set by default */
440 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
441 {
442 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
443 }
444 else
445 {
446 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
447 }
448 }
449
450 /* Configure : CRC Length */
451 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
452 {
453 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
454 }
455 }
456 #endif /* USE_SPI_CRC */
457
458 /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
459 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
460 (hspi->Init.TIMode & SPI_CR2_FRF) |
461 (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
462 (hspi->Init.DataSize & SPI_CR2_DS_Msk) |
463 (frxth & SPI_CR2_FRXTH)));
464
465 #if (USE_SPI_CRC != 0U)
466 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
467 /* Configure : CRC Polynomial */
468 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
469 {
470 WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
471 }
472 #endif /* USE_SPI_CRC */
473
474 #if defined(SPI_I2SCFGR_I2SMOD)
475 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
476 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
477 #endif /* SPI_I2SCFGR_I2SMOD */
478
479 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
480 hspi->State = HAL_SPI_STATE_READY;
481
482 return HAL_OK;
483 }
484
485 /**
486 * @brief De-Initialize the SPI peripheral.
487 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
488 * the configuration information for SPI module.
489 * @retval HAL status
490 */
HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)491 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
492 {
493 /* Check the SPI handle allocation */
494 if (hspi == NULL)
495 {
496 return HAL_ERROR;
497 }
498
499 /* Check SPI Instance parameter */
500 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
501
502 hspi->State = HAL_SPI_STATE_BUSY;
503
504 /* Disable the SPI Peripheral Clock */
505 __HAL_SPI_DISABLE(hspi);
506
507 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
508 if (hspi->MspDeInitCallback == NULL)
509 {
510 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
511 }
512
513 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
514 hspi->MspDeInitCallback(hspi);
515 #else
516 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
517 HAL_SPI_MspDeInit(hspi);
518 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
519
520 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
521 hspi->State = HAL_SPI_STATE_RESET;
522
523 /* Release Lock */
524 __HAL_UNLOCK(hspi);
525
526 return HAL_OK;
527 }
528
529 /**
530 * @brief Initialize the SPI MSP.
531 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
532 * the configuration information for SPI module.
533 * @retval None
534 */
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)535 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
536 {
537 /* Prevent unused argument(s) compilation warning */
538 UNUSED(hspi);
539
540 /* NOTE : This function should not be modified, when the callback is needed,
541 the HAL_SPI_MspInit should be implemented in the user file
542 */
543 }
544
545 /**
546 * @brief De-Initialize the SPI MSP.
547 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
548 * the configuration information for SPI module.
549 * @retval None
550 */
HAL_SPI_MspDeInit(SPI_HandleTypeDef * hspi)551 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
552 {
553 /* Prevent unused argument(s) compilation warning */
554 UNUSED(hspi);
555
556 /* NOTE : This function should not be modified, when the callback is needed,
557 the HAL_SPI_MspDeInit should be implemented in the user file
558 */
559 }
560
561 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
562 /**
563 * @brief Register a User SPI Callback
564 * To be used instead of the weak predefined callback
565 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
566 * the configuration information for the specified SPI.
567 * @param CallbackID ID of the callback to be registered
568 * @param pCallback pointer to the Callback function
569 * @retval HAL status
570 */
HAL_SPI_RegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID,pSPI_CallbackTypeDef pCallback)571 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
572 pSPI_CallbackTypeDef pCallback)
573 {
574 HAL_StatusTypeDef status = HAL_OK;
575
576 if (pCallback == NULL)
577 {
578 /* Update the error code */
579 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
580
581 return HAL_ERROR;
582 }
583 /* Process locked */
584 __HAL_LOCK(hspi);
585
586 if (HAL_SPI_STATE_READY == hspi->State)
587 {
588 switch (CallbackID)
589 {
590 case HAL_SPI_TX_COMPLETE_CB_ID :
591 hspi->TxCpltCallback = pCallback;
592 break;
593
594 case HAL_SPI_RX_COMPLETE_CB_ID :
595 hspi->RxCpltCallback = pCallback;
596 break;
597
598 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
599 hspi->TxRxCpltCallback = pCallback;
600 break;
601
602 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
603 hspi->TxHalfCpltCallback = pCallback;
604 break;
605
606 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
607 hspi->RxHalfCpltCallback = pCallback;
608 break;
609
610 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
611 hspi->TxRxHalfCpltCallback = pCallback;
612 break;
613
614 case HAL_SPI_ERROR_CB_ID :
615 hspi->ErrorCallback = pCallback;
616 break;
617
618 case HAL_SPI_ABORT_CB_ID :
619 hspi->AbortCpltCallback = pCallback;
620 break;
621
622 case HAL_SPI_MSPINIT_CB_ID :
623 hspi->MspInitCallback = pCallback;
624 break;
625
626 case HAL_SPI_MSPDEINIT_CB_ID :
627 hspi->MspDeInitCallback = pCallback;
628 break;
629
630 default :
631 /* Update the error code */
632 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
633
634 /* Return error status */
635 status = HAL_ERROR;
636 break;
637 }
638 }
639 else if (HAL_SPI_STATE_RESET == hspi->State)
640 {
641 switch (CallbackID)
642 {
643 case HAL_SPI_MSPINIT_CB_ID :
644 hspi->MspInitCallback = pCallback;
645 break;
646
647 case HAL_SPI_MSPDEINIT_CB_ID :
648 hspi->MspDeInitCallback = pCallback;
649 break;
650
651 default :
652 /* Update the error code */
653 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
654
655 /* Return error status */
656 status = HAL_ERROR;
657 break;
658 }
659 }
660 else
661 {
662 /* Update the error code */
663 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
664
665 /* Return error status */
666 status = HAL_ERROR;
667 }
668
669 /* Release Lock */
670 __HAL_UNLOCK(hspi);
671 return status;
672 }
673
674 /**
675 * @brief Unregister an SPI Callback
676 * SPI callback is redirected to the weak predefined callback
677 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
678 * the configuration information for the specified SPI.
679 * @param CallbackID ID of the callback to be unregistered
680 * @retval HAL status
681 */
HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID)682 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
683 {
684 HAL_StatusTypeDef status = HAL_OK;
685
686 /* Process locked */
687 __HAL_LOCK(hspi);
688
689 if (HAL_SPI_STATE_READY == hspi->State)
690 {
691 switch (CallbackID)
692 {
693 case HAL_SPI_TX_COMPLETE_CB_ID :
694 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
695 break;
696
697 case HAL_SPI_RX_COMPLETE_CB_ID :
698 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
699 break;
700
701 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
702 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
703 break;
704
705 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
706 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
707 break;
708
709 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
710 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
711 break;
712
713 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
714 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
715 break;
716
717 case HAL_SPI_ERROR_CB_ID :
718 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
719 break;
720
721 case HAL_SPI_ABORT_CB_ID :
722 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
723 break;
724
725 case HAL_SPI_MSPINIT_CB_ID :
726 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
727 break;
728
729 case HAL_SPI_MSPDEINIT_CB_ID :
730 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
731 break;
732
733 default :
734 /* Update the error code */
735 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
736
737 /* Return error status */
738 status = HAL_ERROR;
739 break;
740 }
741 }
742 else if (HAL_SPI_STATE_RESET == hspi->State)
743 {
744 switch (CallbackID)
745 {
746 case HAL_SPI_MSPINIT_CB_ID :
747 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
748 break;
749
750 case HAL_SPI_MSPDEINIT_CB_ID :
751 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
752 break;
753
754 default :
755 /* Update the error code */
756 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
757
758 /* Return error status */
759 status = HAL_ERROR;
760 break;
761 }
762 }
763 else
764 {
765 /* Update the error code */
766 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
767
768 /* Return error status */
769 status = HAL_ERROR;
770 }
771
772 /* Release Lock */
773 __HAL_UNLOCK(hspi);
774 return status;
775 }
776 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
777 /**
778 * @}
779 */
780
781 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
782 * @brief Data transfers functions
783 *
784 @verbatim
785 ==============================================================================
786 ##### IO operation functions #####
787 ===============================================================================
788 [..]
789 This subsection provides a set of functions allowing to manage the SPI
790 data transfers.
791
792 [..] The SPI supports master and slave mode :
793
794 (#) There are two modes of transfer:
795 (++) Blocking mode: The communication is performed in polling mode.
796 The HAL status of all data processing is returned by the same function
797 after finishing transfer.
798 (++) No-Blocking mode: The communication is performed using Interrupts
799 or DMA, These APIs return the HAL status.
800 The end of the data processing will be indicated through the
801 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
802 using DMA mode.
803 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
804 will be executed respectively at the end of the transmit or Receive process
805 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
806
807 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
808 exist for 1Line (simplex) and 2Lines (full duplex) modes.
809
810 @endverbatim
811 * @{
812 */
813
814 /**
815 * @brief Transmit an amount of data in blocking mode.
816 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
817 * the configuration information for SPI module.
818 * @param pData pointer to data buffer
819 * @param Size amount of data to be sent
820 * @param Timeout Timeout duration
821 * @retval HAL status
822 */
HAL_SPI_Transmit(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)823 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
824 {
825 uint32_t tickstart;
826 HAL_StatusTypeDef errorcode = HAL_OK;
827 uint16_t initial_TxXferCount;
828
829 /* Check Direction parameter */
830 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
831
832 /* Process Locked */
833 __HAL_LOCK(hspi);
834
835 /* Init tickstart for timeout management*/
836 tickstart = HAL_GetTick();
837 initial_TxXferCount = Size;
838
839 if (hspi->State != HAL_SPI_STATE_READY)
840 {
841 errorcode = HAL_BUSY;
842 goto error;
843 }
844
845 if ((pData == NULL) || (Size == 0U))
846 {
847 errorcode = HAL_ERROR;
848 goto error;
849 }
850
851 /* Set the transaction information */
852 hspi->State = HAL_SPI_STATE_BUSY_TX;
853 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
854 hspi->pTxBuffPtr = (uint8_t *)pData;
855 hspi->TxXferSize = Size;
856 hspi->TxXferCount = Size;
857
858 /*Init field not used in handle to zero */
859 hspi->pRxBuffPtr = (uint8_t *)NULL;
860 hspi->RxXferSize = 0U;
861 hspi->RxXferCount = 0U;
862 hspi->TxISR = NULL;
863 hspi->RxISR = NULL;
864
865 /* Configure communication direction : 1Line */
866 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
867 {
868 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
869 __HAL_SPI_DISABLE(hspi);
870 SPI_1LINE_TX(hspi);
871 }
872
873 #if (USE_SPI_CRC != 0U)
874 /* Reset CRC Calculation */
875 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
876 {
877 SPI_RESET_CRC(hspi);
878 }
879 #endif /* USE_SPI_CRC */
880
881 /* Check if the SPI is already enabled */
882 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
883 {
884 /* Enable SPI peripheral */
885 __HAL_SPI_ENABLE(hspi);
886 }
887
888 /* Transmit data in 16 Bit mode */
889 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
890 {
891 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
892 {
893 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
894 hspi->pTxBuffPtr += sizeof(uint16_t);
895 hspi->TxXferCount--;
896 }
897 /* Transmit data in 16 Bit mode */
898 while (hspi->TxXferCount > 0U)
899 {
900 /* Wait until TXE flag is set to send data */
901 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
902 {
903 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
904 hspi->pTxBuffPtr += sizeof(uint16_t);
905 hspi->TxXferCount--;
906 }
907 else
908 {
909 /* Timeout management */
910 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
911 {
912 errorcode = HAL_TIMEOUT;
913 goto error;
914 }
915 }
916 }
917 }
918 /* Transmit data in 8 Bit mode */
919 else
920 {
921 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
922 {
923 if (hspi->TxXferCount > 1U)
924 {
925 /* write on the data register in packing mode */
926 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
927 hspi->pTxBuffPtr += sizeof(uint16_t);
928 hspi->TxXferCount -= 2U;
929 }
930 else
931 {
932 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
933 hspi->pTxBuffPtr ++;
934 hspi->TxXferCount--;
935 }
936 }
937 while (hspi->TxXferCount > 0U)
938 {
939 /* Wait until TXE flag is set to send data */
940 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
941 {
942 if (hspi->TxXferCount > 1U)
943 {
944 /* write on the data register in packing mode */
945 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
946 hspi->pTxBuffPtr += sizeof(uint16_t);
947 hspi->TxXferCount -= 2U;
948 }
949 else
950 {
951 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
952 hspi->pTxBuffPtr++;
953 hspi->TxXferCount--;
954 }
955 }
956 else
957 {
958 /* Timeout management */
959 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
960 {
961 errorcode = HAL_TIMEOUT;
962 goto error;
963 }
964 }
965 }
966 }
967 #if (USE_SPI_CRC != 0U)
968 /* Enable CRC Transmission */
969 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
970 {
971 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
972 }
973 #endif /* USE_SPI_CRC */
974
975 /* Check the end of the transaction */
976 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
977 {
978 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
979 }
980
981 /* Clear overrun flag in 2 Lines communication mode because received is not read */
982 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
983 {
984 __HAL_SPI_CLEAR_OVRFLAG(hspi);
985 }
986
987 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
988 {
989 errorcode = HAL_ERROR;
990 }
991
992 error:
993 hspi->State = HAL_SPI_STATE_READY;
994 /* Process Unlocked */
995 __HAL_UNLOCK(hspi);
996 return errorcode;
997 }
998
999 /**
1000 * @brief Receive an amount of data in blocking mode.
1001 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1002 * the configuration information for SPI module.
1003 * @param pData pointer to data buffer
1004 * @param Size amount of data to be received
1005 * @param Timeout Timeout duration
1006 * @retval HAL status
1007 */
HAL_SPI_Receive(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)1008 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1009 {
1010 #if (USE_SPI_CRC != 0U)
1011 __IO uint32_t tmpreg = 0U;
1012 #endif /* USE_SPI_CRC */
1013 uint32_t tickstart;
1014 HAL_StatusTypeDef errorcode = HAL_OK;
1015
1016 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
1017 {
1018 hspi->State = HAL_SPI_STATE_BUSY_RX;
1019 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1020 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
1021 }
1022
1023 /* Process Locked */
1024 __HAL_LOCK(hspi);
1025
1026 /* Init tickstart for timeout management*/
1027 tickstart = HAL_GetTick();
1028
1029 if (hspi->State != HAL_SPI_STATE_READY)
1030 {
1031 errorcode = HAL_BUSY;
1032 goto error;
1033 }
1034
1035 if ((pData == NULL) || (Size == 0U))
1036 {
1037 errorcode = HAL_ERROR;
1038 goto error;
1039 }
1040
1041 /* Set the transaction information */
1042 hspi->State = HAL_SPI_STATE_BUSY_RX;
1043 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1044 hspi->pRxBuffPtr = (uint8_t *)pData;
1045 hspi->RxXferSize = Size;
1046 hspi->RxXferCount = Size;
1047
1048 /*Init field not used in handle to zero */
1049 hspi->pTxBuffPtr = (uint8_t *)NULL;
1050 hspi->TxXferSize = 0U;
1051 hspi->TxXferCount = 0U;
1052 hspi->RxISR = NULL;
1053 hspi->TxISR = NULL;
1054
1055 #if (USE_SPI_CRC != 0U)
1056 /* Reset CRC Calculation */
1057 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1058 {
1059 SPI_RESET_CRC(hspi);
1060 /* this is done to handle the CRCNEXT before the latest data */
1061 hspi->RxXferCount--;
1062 }
1063 #endif /* USE_SPI_CRC */
1064
1065 /* Set the Rx Fifo threshold */
1066 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1067 {
1068 /* Set RX Fifo threshold according the reception data length: 16bit */
1069 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1070 }
1071 else
1072 {
1073 /* Set RX Fifo threshold according the reception data length: 8bit */
1074 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1075 }
1076
1077 /* Configure communication direction: 1Line */
1078 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1079 {
1080 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1081 __HAL_SPI_DISABLE(hspi);
1082 SPI_1LINE_RX(hspi);
1083 }
1084
1085 /* Check if the SPI is already enabled */
1086 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1087 {
1088 /* Enable SPI peripheral */
1089 __HAL_SPI_ENABLE(hspi);
1090 }
1091
1092 /* Receive data in 8 Bit mode */
1093 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
1094 {
1095 /* Transfer loop */
1096 while (hspi->RxXferCount > 0U)
1097 {
1098 /* Check the RXNE flag */
1099 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1100 {
1101 /* read the received data */
1102 (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1103 hspi->pRxBuffPtr += sizeof(uint8_t);
1104 hspi->RxXferCount--;
1105 }
1106 else
1107 {
1108 /* Timeout management */
1109 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1110 {
1111 errorcode = HAL_TIMEOUT;
1112 goto error;
1113 }
1114 }
1115 }
1116 }
1117 else
1118 {
1119 /* Transfer loop */
1120 while (hspi->RxXferCount > 0U)
1121 {
1122 /* Check the RXNE flag */
1123 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1124 {
1125 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1126 hspi->pRxBuffPtr += sizeof(uint16_t);
1127 hspi->RxXferCount--;
1128 }
1129 else
1130 {
1131 /* Timeout management */
1132 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1133 {
1134 errorcode = HAL_TIMEOUT;
1135 goto error;
1136 }
1137 }
1138 }
1139 }
1140
1141 #if (USE_SPI_CRC != 0U)
1142 /* Handle the CRC Transmission */
1143 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1144 {
1145 /* freeze the CRC before the latest data */
1146 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1147
1148 /* Read the latest data */
1149 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1150 {
1151 /* the latest data has not been received */
1152 errorcode = HAL_TIMEOUT;
1153 goto error;
1154 }
1155
1156 /* Receive last data in 16 Bit mode */
1157 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1158 {
1159 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1160 }
1161 /* Receive last data in 8 Bit mode */
1162 else
1163 {
1164 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1165 }
1166
1167 /* Wait the CRC data */
1168 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1169 {
1170 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1171 errorcode = HAL_TIMEOUT;
1172 goto error;
1173 }
1174
1175 /* Read CRC to Flush DR and RXNE flag */
1176 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1177 {
1178 /* Read 16bit CRC */
1179 tmpreg = READ_REG(hspi->Instance->DR);
1180 /* To avoid GCC warning */
1181 UNUSED(tmpreg);
1182 }
1183 else
1184 {
1185 /* Read 8bit CRC */
1186 tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1187 /* To avoid GCC warning */
1188 UNUSED(tmpreg);
1189
1190 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1191 {
1192 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1193 {
1194 /* Error on the CRC reception */
1195 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1196 errorcode = HAL_TIMEOUT;
1197 goto error;
1198 }
1199 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1200 tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1201 /* To avoid GCC warning */
1202 UNUSED(tmpreg);
1203 }
1204 }
1205 }
1206 #endif /* USE_SPI_CRC */
1207
1208 /* Check the end of the transaction */
1209 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1210 {
1211 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1212 }
1213
1214 #if (USE_SPI_CRC != 0U)
1215 /* Check if CRC error occurred */
1216 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1217 {
1218 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1219 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1220 }
1221 #endif /* USE_SPI_CRC */
1222
1223 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1224 {
1225 errorcode = HAL_ERROR;
1226 }
1227
1228 error :
1229 hspi->State = HAL_SPI_STATE_READY;
1230 __HAL_UNLOCK(hspi);
1231 return errorcode;
1232 }
1233
1234 /**
1235 * @brief Transmit and Receive an amount of data in blocking mode.
1236 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1237 * the configuration information for SPI module.
1238 * @param pTxData pointer to transmission data buffer
1239 * @param pRxData pointer to reception data buffer
1240 * @param Size amount of data to be sent and received
1241 * @param Timeout Timeout duration
1242 * @retval HAL status
1243 */
HAL_SPI_TransmitReceive(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size,uint32_t Timeout)1244 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1245 uint32_t Timeout)
1246 {
1247 #if (USE_SPI_CRC != 0U)
1248 __IO uint32_t tmpreg = 0U;
1249 #endif /* USE_SPI_CRC */
1250 uint16_t initial_TxXferCount;
1251 uint16_t initial_RxXferCount;
1252 uint32_t tmp_mode;
1253 HAL_SPI_StateTypeDef tmp_state;
1254 uint32_t tickstart;
1255 #if (USE_SPI_CRC != 0U)
1256 uint32_t spi_cr1;
1257 uint32_t spi_cr2;
1258 #endif /* USE_SPI_CRC */
1259
1260 /* Variable used to alternate Rx and Tx during transfer */
1261 uint32_t txallowed = 1U;
1262 HAL_StatusTypeDef errorcode = HAL_OK;
1263
1264 /* Check Direction parameter */
1265 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1266
1267 /* Process Locked */
1268 __HAL_LOCK(hspi);
1269
1270 /* Init tickstart for timeout management*/
1271 tickstart = HAL_GetTick();
1272
1273 /* Init temporary variables */
1274 tmp_state = hspi->State;
1275 tmp_mode = hspi->Init.Mode;
1276 initial_TxXferCount = Size;
1277 initial_RxXferCount = Size;
1278 #if (USE_SPI_CRC != 0U)
1279 spi_cr1 = READ_REG(hspi->Instance->CR1);
1280 spi_cr2 = READ_REG(hspi->Instance->CR2);
1281 #endif /* USE_SPI_CRC */
1282
1283 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1284 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1285 {
1286 errorcode = HAL_BUSY;
1287 goto error;
1288 }
1289
1290 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1291 {
1292 errorcode = HAL_ERROR;
1293 goto error;
1294 }
1295
1296 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1297 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1298 {
1299 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1300 }
1301
1302 /* Set the transaction information */
1303 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1304 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1305 hspi->RxXferCount = Size;
1306 hspi->RxXferSize = Size;
1307 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1308 hspi->TxXferCount = Size;
1309 hspi->TxXferSize = Size;
1310
1311 /*Init field not used in handle to zero */
1312 hspi->RxISR = NULL;
1313 hspi->TxISR = NULL;
1314
1315 #if (USE_SPI_CRC != 0U)
1316 /* Reset CRC Calculation */
1317 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1318 {
1319 SPI_RESET_CRC(hspi);
1320 }
1321 #endif /* USE_SPI_CRC */
1322
1323 /* Set the Rx Fifo threshold */
1324 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
1325 {
1326 /* Set fiforxthreshold according the reception data length: 16bit */
1327 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1328 }
1329 else
1330 {
1331 /* Set fiforxthreshold according the reception data length: 8bit */
1332 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1333 }
1334
1335 /* Check if the SPI is already enabled */
1336 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1337 {
1338 /* Enable SPI peripheral */
1339 __HAL_SPI_ENABLE(hspi);
1340 }
1341
1342 /* Transmit and Receive data in 16 Bit mode */
1343 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1344 {
1345 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1346 {
1347 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1348 hspi->pTxBuffPtr += sizeof(uint16_t);
1349 hspi->TxXferCount--;
1350 }
1351 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1352 {
1353 /* Check TXE flag */
1354 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1355 {
1356 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1357 hspi->pTxBuffPtr += sizeof(uint16_t);
1358 hspi->TxXferCount--;
1359 /* Next Data is a reception (Rx). Tx not allowed */
1360 txallowed = 0U;
1361
1362 #if (USE_SPI_CRC != 0U)
1363 /* Enable CRC Transmission */
1364 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1365 {
1366 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1367 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1368 {
1369 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1370 }
1371 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1372 }
1373 #endif /* USE_SPI_CRC */
1374 }
1375
1376 /* Check RXNE flag */
1377 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1378 {
1379 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1380 hspi->pRxBuffPtr += sizeof(uint16_t);
1381 hspi->RxXferCount--;
1382 /* Next Data is a Transmission (Tx). Tx is allowed */
1383 txallowed = 1U;
1384 }
1385 if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
1386 {
1387 errorcode = HAL_TIMEOUT;
1388 goto error;
1389 }
1390 }
1391 }
1392 /* Transmit and Receive data in 8 Bit mode */
1393 else
1394 {
1395 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1396 {
1397 if (hspi->TxXferCount > 1U)
1398 {
1399 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1400 hspi->pTxBuffPtr += sizeof(uint16_t);
1401 hspi->TxXferCount -= 2U;
1402 }
1403 else
1404 {
1405 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1406 hspi->pTxBuffPtr++;
1407 hspi->TxXferCount--;
1408 }
1409 }
1410 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1411 {
1412 /* Check TXE flag */
1413 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1414 {
1415 if (hspi->TxXferCount > 1U)
1416 {
1417 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1418 hspi->pTxBuffPtr += sizeof(uint16_t);
1419 hspi->TxXferCount -= 2U;
1420 }
1421 else
1422 {
1423 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1424 hspi->pTxBuffPtr++;
1425 hspi->TxXferCount--;
1426 }
1427 /* Next Data is a reception (Rx). Tx not allowed */
1428 txallowed = 0U;
1429
1430 #if (USE_SPI_CRC != 0U)
1431 /* Enable CRC Transmission */
1432 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1433 {
1434 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1435 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1436 {
1437 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1438 }
1439 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1440 }
1441 #endif /* USE_SPI_CRC */
1442 }
1443
1444 /* Wait until RXNE flag is reset */
1445 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1446 {
1447 if (hspi->RxXferCount > 1U)
1448 {
1449 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1450 hspi->pRxBuffPtr += sizeof(uint16_t);
1451 hspi->RxXferCount -= 2U;
1452 if (hspi->RxXferCount <= 1U)
1453 {
1454 /* Set RX Fifo threshold before to switch on 8 bit data size */
1455 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1456 }
1457 }
1458 else
1459 {
1460 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1461 hspi->pRxBuffPtr++;
1462 hspi->RxXferCount--;
1463 }
1464 /* Next Data is a Transmission (Tx). Tx is allowed */
1465 txallowed = 1U;
1466 }
1467 if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1468 {
1469 errorcode = HAL_TIMEOUT;
1470 goto error;
1471 }
1472 }
1473 }
1474
1475 #if (USE_SPI_CRC != 0U)
1476 /* Read CRC from DR to close CRC calculation process */
1477 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1478 {
1479 /* Wait until TXE flag */
1480 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1481 {
1482 /* Error on the CRC reception */
1483 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1484 errorcode = HAL_TIMEOUT;
1485 goto error;
1486 }
1487 /* Read CRC */
1488 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1489 {
1490 /* Read 16bit CRC */
1491 tmpreg = READ_REG(hspi->Instance->DR);
1492 /* To avoid GCC warning */
1493 UNUSED(tmpreg);
1494 }
1495 else
1496 {
1497 /* Read 8bit CRC */
1498 tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1499 /* To avoid GCC warning */
1500 UNUSED(tmpreg);
1501
1502 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
1503 {
1504 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1505 {
1506 /* Error on the CRC reception */
1507 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1508 errorcode = HAL_TIMEOUT;
1509 goto error;
1510 }
1511 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1512 tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1513 /* To avoid GCC warning */
1514 UNUSED(tmpreg);
1515 }
1516 }
1517 }
1518
1519 /* Check if CRC error occurred */
1520 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1521 {
1522 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1523 /* Clear CRC Flag */
1524 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1525
1526 errorcode = HAL_ERROR;
1527 }
1528 #endif /* USE_SPI_CRC */
1529
1530 /* Check the end of the transaction */
1531 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1532 {
1533 errorcode = HAL_ERROR;
1534 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1535 }
1536
1537 error :
1538 hspi->State = HAL_SPI_STATE_READY;
1539 __HAL_UNLOCK(hspi);
1540 return errorcode;
1541 }
1542
1543 /**
1544 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1545 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1546 * the configuration information for SPI module.
1547 * @param pData pointer to data buffer
1548 * @param Size amount of data to be sent
1549 * @retval HAL status
1550 */
HAL_SPI_Transmit_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1551 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1552 {
1553 HAL_StatusTypeDef errorcode = HAL_OK;
1554
1555 /* Check Direction parameter */
1556 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1557
1558 /* Process Locked */
1559 __HAL_LOCK(hspi);
1560
1561 if ((pData == NULL) || (Size == 0U))
1562 {
1563 errorcode = HAL_ERROR;
1564 goto error;
1565 }
1566
1567 if (hspi->State != HAL_SPI_STATE_READY)
1568 {
1569 errorcode = HAL_BUSY;
1570 goto error;
1571 }
1572
1573 /* Set the transaction information */
1574 hspi->State = HAL_SPI_STATE_BUSY_TX;
1575 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1576 hspi->pTxBuffPtr = (uint8_t *)pData;
1577 hspi->TxXferSize = Size;
1578 hspi->TxXferCount = Size;
1579
1580 /* Init field not used in handle to zero */
1581 hspi->pRxBuffPtr = (uint8_t *)NULL;
1582 hspi->RxXferSize = 0U;
1583 hspi->RxXferCount = 0U;
1584 hspi->RxISR = NULL;
1585
1586 /* Set the function for IT treatment */
1587 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1588 {
1589 hspi->TxISR = SPI_TxISR_16BIT;
1590 }
1591 else
1592 {
1593 hspi->TxISR = SPI_TxISR_8BIT;
1594 }
1595
1596 /* Configure communication direction : 1Line */
1597 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1598 {
1599 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1600 __HAL_SPI_DISABLE(hspi);
1601 SPI_1LINE_TX(hspi);
1602 }
1603
1604 #if (USE_SPI_CRC != 0U)
1605 /* Reset CRC Calculation */
1606 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1607 {
1608 SPI_RESET_CRC(hspi);
1609 }
1610 #endif /* USE_SPI_CRC */
1611
1612 /* Enable TXE and ERR interrupt */
1613 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1614
1615
1616 /* Check if the SPI is already enabled */
1617 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1618 {
1619 /* Enable SPI peripheral */
1620 __HAL_SPI_ENABLE(hspi);
1621 }
1622
1623 error :
1624 __HAL_UNLOCK(hspi);
1625 return errorcode;
1626 }
1627
1628 /**
1629 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1630 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1631 * the configuration information for SPI module.
1632 * @param pData pointer to data buffer
1633 * @param Size amount of data to be sent
1634 * @retval HAL status
1635 */
HAL_SPI_Receive_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1636 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1637 {
1638 HAL_StatusTypeDef errorcode = HAL_OK;
1639
1640 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1641 {
1642 hspi->State = HAL_SPI_STATE_BUSY_RX;
1643 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1644 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1645 }
1646
1647 /* Process Locked */
1648 __HAL_LOCK(hspi);
1649
1650 if (hspi->State != HAL_SPI_STATE_READY)
1651 {
1652 errorcode = HAL_BUSY;
1653 goto error;
1654 }
1655
1656 if ((pData == NULL) || (Size == 0U))
1657 {
1658 errorcode = HAL_ERROR;
1659 goto error;
1660 }
1661
1662 /* Set the transaction information */
1663 hspi->State = HAL_SPI_STATE_BUSY_RX;
1664 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1665 hspi->pRxBuffPtr = (uint8_t *)pData;
1666 hspi->RxXferSize = Size;
1667 hspi->RxXferCount = Size;
1668
1669 /* Init field not used in handle to zero */
1670 hspi->pTxBuffPtr = (uint8_t *)NULL;
1671 hspi->TxXferSize = 0U;
1672 hspi->TxXferCount = 0U;
1673 hspi->TxISR = NULL;
1674
1675 /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
1676 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1677 {
1678 /* Set RX Fifo threshold according the reception data length: 16 bit */
1679 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1680 hspi->RxISR = SPI_RxISR_16BIT;
1681 }
1682 else
1683 {
1684 /* Set RX Fifo threshold according the reception data length: 8 bit */
1685 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1686 hspi->RxISR = SPI_RxISR_8BIT;
1687 }
1688
1689 /* Configure communication direction : 1Line */
1690 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1691 {
1692 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1693 __HAL_SPI_DISABLE(hspi);
1694 SPI_1LINE_RX(hspi);
1695 }
1696
1697 #if (USE_SPI_CRC != 0U)
1698 /* Reset CRC Calculation */
1699 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1700 {
1701 hspi->CRCSize = 1U;
1702 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1703 {
1704 hspi->CRCSize = 2U;
1705 }
1706 SPI_RESET_CRC(hspi);
1707 }
1708 else
1709 {
1710 hspi->CRCSize = 0U;
1711 }
1712 #endif /* USE_SPI_CRC */
1713
1714 /* Enable TXE and ERR interrupt */
1715 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1716
1717 /* Note : The SPI must be enabled after unlocking current process
1718 to avoid the risk of SPI interrupt handle execution before current
1719 process unlock */
1720
1721 /* Check if the SPI is already enabled */
1722 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1723 {
1724 /* Enable SPI peripheral */
1725 __HAL_SPI_ENABLE(hspi);
1726 }
1727
1728 error :
1729 /* Process Unlocked */
1730 __HAL_UNLOCK(hspi);
1731 return errorcode;
1732 }
1733
1734 /**
1735 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1736 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1737 * the configuration information for SPI module.
1738 * @param pTxData pointer to transmission data buffer
1739 * @param pRxData pointer to reception data buffer
1740 * @param Size amount of data to be sent and received
1741 * @retval HAL status
1742 */
HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1743 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1744 {
1745 uint32_t tmp_mode;
1746 HAL_SPI_StateTypeDef tmp_state;
1747 HAL_StatusTypeDef errorcode = HAL_OK;
1748
1749 /* Check Direction parameter */
1750 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1751
1752 /* Process locked */
1753 __HAL_LOCK(hspi);
1754
1755 /* Init temporary variables */
1756 tmp_state = hspi->State;
1757 tmp_mode = hspi->Init.Mode;
1758
1759 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1760 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1761 {
1762 errorcode = HAL_BUSY;
1763 goto error;
1764 }
1765
1766 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1767 {
1768 errorcode = HAL_ERROR;
1769 goto error;
1770 }
1771
1772 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1773 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1774 {
1775 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1776 }
1777
1778 /* Set the transaction information */
1779 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1780 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1781 hspi->TxXferSize = Size;
1782 hspi->TxXferCount = Size;
1783 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1784 hspi->RxXferSize = Size;
1785 hspi->RxXferCount = Size;
1786
1787 /* Set the function for IT treatment */
1788 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1789 {
1790 hspi->RxISR = SPI_2linesRxISR_16BIT;
1791 hspi->TxISR = SPI_2linesTxISR_16BIT;
1792 }
1793 else
1794 {
1795 hspi->RxISR = SPI_2linesRxISR_8BIT;
1796 hspi->TxISR = SPI_2linesTxISR_8BIT;
1797 }
1798
1799 #if (USE_SPI_CRC != 0U)
1800 /* Reset CRC Calculation */
1801 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1802 {
1803 hspi->CRCSize = 1U;
1804 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1805 {
1806 hspi->CRCSize = 2U;
1807 }
1808 SPI_RESET_CRC(hspi);
1809 }
1810 else
1811 {
1812 hspi->CRCSize = 0U;
1813 }
1814 #endif /* USE_SPI_CRC */
1815
1816 /* Check if packing mode is enabled and if there is more than 2 data to receive */
1817 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
1818 {
1819 /* Set RX Fifo threshold according the reception data length: 16 bit */
1820 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1821 }
1822 else
1823 {
1824 /* Set RX Fifo threshold according the reception data length: 8 bit */
1825 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1826 }
1827
1828 /* Enable TXE, RXNE and ERR interrupt */
1829 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1830
1831 /* Check if the SPI is already enabled */
1832 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1833 {
1834 /* Enable SPI peripheral */
1835 __HAL_SPI_ENABLE(hspi);
1836 }
1837
1838 error :
1839 /* Process Unlocked */
1840 __HAL_UNLOCK(hspi);
1841 return errorcode;
1842 }
1843
1844 /**
1845 * @brief Transmit an amount of data in non-blocking mode with DMA.
1846 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1847 * the configuration information for SPI module.
1848 * @param pData pointer to data buffer
1849 * @param Size amount of data to be sent
1850 * @retval HAL status
1851 */
HAL_SPI_Transmit_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1852 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1853 {
1854 HAL_StatusTypeDef errorcode = HAL_OK;
1855
1856 /* Check tx dma handle */
1857 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1858
1859 /* Check Direction parameter */
1860 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1861
1862 /* Process Locked */
1863 __HAL_LOCK(hspi);
1864
1865 if (hspi->State != HAL_SPI_STATE_READY)
1866 {
1867 errorcode = HAL_BUSY;
1868 goto error;
1869 }
1870
1871 if ((pData == NULL) || (Size == 0U))
1872 {
1873 errorcode = HAL_ERROR;
1874 goto error;
1875 }
1876
1877 /* Set the transaction information */
1878 hspi->State = HAL_SPI_STATE_BUSY_TX;
1879 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1880 hspi->pTxBuffPtr = (uint8_t *)pData;
1881 hspi->TxXferSize = Size;
1882 hspi->TxXferCount = Size;
1883
1884 /* Init field not used in handle to zero */
1885 hspi->pRxBuffPtr = (uint8_t *)NULL;
1886 hspi->TxISR = NULL;
1887 hspi->RxISR = NULL;
1888 hspi->RxXferSize = 0U;
1889 hspi->RxXferCount = 0U;
1890
1891 /* Configure communication direction : 1Line */
1892 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1893 {
1894 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1895 __HAL_SPI_DISABLE(hspi);
1896 SPI_1LINE_TX(hspi);
1897 }
1898
1899 #if (USE_SPI_CRC != 0U)
1900 /* Reset CRC Calculation */
1901 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1902 {
1903 SPI_RESET_CRC(hspi);
1904 }
1905 #endif /* USE_SPI_CRC */
1906
1907 /* Set the SPI TxDMA Half transfer complete callback */
1908 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1909
1910 /* Set the SPI TxDMA transfer complete callback */
1911 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1912
1913 /* Set the DMA error callback */
1914 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1915
1916 /* Set the DMA AbortCpltCallback */
1917 hspi->hdmatx->XferAbortCallback = NULL;
1918
1919 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1920 /* Packing mode is enabled only if the DMA setting is HALWORD */
1921 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1922 {
1923 /* Check the even/odd of the data size + crc if enabled */
1924 if ((hspi->TxXferCount & 0x1U) == 0U)
1925 {
1926 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1927 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
1928 }
1929 else
1930 {
1931 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1932 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
1933 }
1934 }
1935
1936 /* Enable the Tx DMA Stream/Channel */
1937 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1938 hspi->TxXferCount))
1939 {
1940 /* Update SPI error code */
1941 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1942 errorcode = HAL_ERROR;
1943
1944 hspi->State = HAL_SPI_STATE_READY;
1945 goto error;
1946 }
1947
1948 /* Check if the SPI is already enabled */
1949 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1950 {
1951 /* Enable SPI peripheral */
1952 __HAL_SPI_ENABLE(hspi);
1953 }
1954
1955 /* Enable the SPI Error Interrupt Bit */
1956 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1957
1958 /* Enable Tx DMA Request */
1959 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1960
1961 error :
1962 /* Process Unlocked */
1963 __HAL_UNLOCK(hspi);
1964 return errorcode;
1965 }
1966
1967 /**
1968 * @brief Receive an amount of data in non-blocking mode with DMA.
1969 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1970 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1971 * the configuration information for SPI module.
1972 * @param pData pointer to data buffer
1973 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1974 * @param Size amount of data to be sent
1975 * @retval HAL status
1976 */
HAL_SPI_Receive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1977 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1978 {
1979 HAL_StatusTypeDef errorcode = HAL_OK;
1980
1981 /* Check rx dma handle */
1982 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1983
1984 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1985 {
1986 hspi->State = HAL_SPI_STATE_BUSY_RX;
1987
1988 /* Check tx dma handle */
1989 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1990
1991 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1992 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1993 }
1994
1995 /* Process Locked */
1996 __HAL_LOCK(hspi);
1997
1998 if (hspi->State != HAL_SPI_STATE_READY)
1999 {
2000 errorcode = HAL_BUSY;
2001 goto error;
2002 }
2003
2004 if ((pData == NULL) || (Size == 0U))
2005 {
2006 errorcode = HAL_ERROR;
2007 goto error;
2008 }
2009
2010 /* Set the transaction information */
2011 hspi->State = HAL_SPI_STATE_BUSY_RX;
2012 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2013 hspi->pRxBuffPtr = (uint8_t *)pData;
2014 hspi->RxXferSize = Size;
2015 hspi->RxXferCount = Size;
2016
2017 /*Init field not used in handle to zero */
2018 hspi->RxISR = NULL;
2019 hspi->TxISR = NULL;
2020 hspi->TxXferSize = 0U;
2021 hspi->TxXferCount = 0U;
2022
2023 /* Configure communication direction : 1Line */
2024 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
2025 {
2026 /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
2027 __HAL_SPI_DISABLE(hspi);
2028 SPI_1LINE_RX(hspi);
2029 }
2030
2031 #if (USE_SPI_CRC != 0U)
2032 /* Reset CRC Calculation */
2033 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2034 {
2035 SPI_RESET_CRC(hspi);
2036 }
2037 #endif /* USE_SPI_CRC */
2038
2039
2040 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2041 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2042 {
2043 /* Set RX Fifo threshold according the reception data length: 16bit */
2044 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2045 }
2046 else
2047 {
2048 /* Set RX Fifo threshold according the reception data length: 8bit */
2049 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2050
2051 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2052 {
2053 /* Set RX Fifo threshold according the reception data length: 16bit */
2054 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2055
2056 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2057 {
2058 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2059 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2060 }
2061 else
2062 {
2063 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2064 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2065 }
2066 }
2067 }
2068
2069 /* Set the SPI RxDMA Half transfer complete callback */
2070 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2071
2072 /* Set the SPI Rx DMA transfer complete callback */
2073 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2074
2075 /* Set the DMA error callback */
2076 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2077
2078 /* Set the DMA AbortCpltCallback */
2079 hspi->hdmarx->XferAbortCallback = NULL;
2080
2081 /* Enable the Rx DMA Stream/Channel */
2082 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2083 hspi->RxXferCount))
2084 {
2085 /* Update SPI error code */
2086 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2087 errorcode = HAL_ERROR;
2088
2089 hspi->State = HAL_SPI_STATE_READY;
2090 goto error;
2091 }
2092
2093 /* Check if the SPI is already enabled */
2094 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2095 {
2096 /* Enable SPI peripheral */
2097 __HAL_SPI_ENABLE(hspi);
2098 }
2099
2100 /* Enable the SPI Error Interrupt Bit */
2101 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2102
2103 /* Enable Rx DMA Request */
2104 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2105
2106 error:
2107 /* Process Unlocked */
2108 __HAL_UNLOCK(hspi);
2109 return errorcode;
2110 }
2111
2112 /**
2113 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
2114 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2115 * the configuration information for SPI module.
2116 * @param pTxData pointer to transmission data buffer
2117 * @param pRxData pointer to reception data buffer
2118 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
2119 * @param Size amount of data to be sent
2120 * @retval HAL status
2121 */
HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)2122 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
2123 uint16_t Size)
2124 {
2125 uint32_t tmp_mode;
2126 HAL_SPI_StateTypeDef tmp_state;
2127 HAL_StatusTypeDef errorcode = HAL_OK;
2128
2129 /* Check rx & tx dma handles */
2130 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
2131 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
2132
2133 /* Check Direction parameter */
2134 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
2135
2136 /* Process locked */
2137 __HAL_LOCK(hspi);
2138
2139 /* Init temporary variables */
2140 tmp_state = hspi->State;
2141 tmp_mode = hspi->Init.Mode;
2142
2143 if (!((tmp_state == HAL_SPI_STATE_READY) ||
2144 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
2145 {
2146 errorcode = HAL_BUSY;
2147 goto error;
2148 }
2149
2150 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
2151 {
2152 errorcode = HAL_ERROR;
2153 goto error;
2154 }
2155
2156 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
2157 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
2158 {
2159 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
2160 }
2161
2162 /* Set the transaction information */
2163 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2164 hspi->pTxBuffPtr = (uint8_t *)pTxData;
2165 hspi->TxXferSize = Size;
2166 hspi->TxXferCount = Size;
2167 hspi->pRxBuffPtr = (uint8_t *)pRxData;
2168 hspi->RxXferSize = Size;
2169 hspi->RxXferCount = Size;
2170
2171 /* Init field not used in handle to zero */
2172 hspi->RxISR = NULL;
2173 hspi->TxISR = NULL;
2174
2175 #if (USE_SPI_CRC != 0U)
2176 /* Reset CRC Calculation */
2177 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2178 {
2179 SPI_RESET_CRC(hspi);
2180 }
2181 #endif /* USE_SPI_CRC */
2182
2183 /* Reset the threshold bit */
2184 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
2185
2186 /* The packing mode management is enabled by the DMA settings according the spi data size */
2187 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2188 {
2189 /* Set fiforxthreshold according the reception data length: 16bit */
2190 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2191 }
2192 else
2193 {
2194 /* Set RX Fifo threshold according the reception data length: 8bit */
2195 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2196
2197 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2198 {
2199 if ((hspi->TxXferSize & 0x1U) == 0x0U)
2200 {
2201 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2202 hspi->TxXferCount = hspi->TxXferCount >> 1U;
2203 }
2204 else
2205 {
2206 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2207 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
2208 }
2209 }
2210
2211 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2212 {
2213 /* Set RX Fifo threshold according the reception data length: 16bit */
2214 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2215
2216 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2217 {
2218 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2219 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2220 }
2221 else
2222 {
2223 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2224 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2225 }
2226 }
2227 }
2228
2229 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
2230 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
2231 {
2232 /* Set the SPI Rx DMA Half transfer complete callback */
2233 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2234 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2235 }
2236 else
2237 {
2238 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
2239 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
2240 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
2241 }
2242
2243 /* Set the DMA error callback */
2244 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2245
2246 /* Set the DMA AbortCpltCallback */
2247 hspi->hdmarx->XferAbortCallback = NULL;
2248
2249 /* Enable the Rx DMA Stream/Channel */
2250 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2251 hspi->RxXferCount))
2252 {
2253 /* Update SPI error code */
2254 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2255 errorcode = HAL_ERROR;
2256
2257 hspi->State = HAL_SPI_STATE_READY;
2258 goto error;
2259 }
2260
2261 /* Enable Rx DMA Request */
2262 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2263
2264 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2265 is performed in DMA reception complete callback */
2266 hspi->hdmatx->XferHalfCpltCallback = NULL;
2267 hspi->hdmatx->XferCpltCallback = NULL;
2268 hspi->hdmatx->XferErrorCallback = NULL;
2269 hspi->hdmatx->XferAbortCallback = NULL;
2270
2271 /* Enable the Tx DMA Stream/Channel */
2272 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
2273 hspi->TxXferCount))
2274 {
2275 /* Update SPI error code */
2276 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2277 errorcode = HAL_ERROR;
2278
2279 hspi->State = HAL_SPI_STATE_READY;
2280 goto error;
2281 }
2282
2283 /* Check if the SPI is already enabled */
2284 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2285 {
2286 /* Enable SPI peripheral */
2287 __HAL_SPI_ENABLE(hspi);
2288 }
2289 /* Enable the SPI Error Interrupt Bit */
2290 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2291
2292 /* Enable Tx DMA Request */
2293 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2294
2295 error :
2296 /* Process Unlocked */
2297 __HAL_UNLOCK(hspi);
2298 return errorcode;
2299 }
2300
2301 /**
2302 * @brief Abort ongoing transfer (blocking mode).
2303 * @param hspi SPI handle.
2304 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2305 * started in Interrupt or DMA mode.
2306 * This procedure performs following operations :
2307 * - Disable SPI Interrupts (depending of transfer direction)
2308 * - Disable the DMA transfer in the peripheral register (if enabled)
2309 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2310 * - Set handle State to READY
2311 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2312 * @retval HAL status
2313 */
HAL_SPI_Abort(SPI_HandleTypeDef * hspi)2314 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2315 {
2316 HAL_StatusTypeDef errorcode;
2317 __IO uint32_t count;
2318 __IO uint32_t resetcount;
2319
2320 /* Initialized local variable */
2321 errorcode = HAL_OK;
2322 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2323 count = resetcount;
2324
2325 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2326 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2327
2328 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
2329 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2330 {
2331 hspi->TxISR = SPI_AbortTx_ISR;
2332 /* Wait HAL_SPI_STATE_ABORT state */
2333 do
2334 {
2335 if (count == 0U)
2336 {
2337 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2338 break;
2339 }
2340 count--;
2341 } while (hspi->State != HAL_SPI_STATE_ABORT);
2342 /* Reset Timeout Counter */
2343 count = resetcount;
2344 }
2345
2346 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2347 {
2348 hspi->RxISR = SPI_AbortRx_ISR;
2349 /* Wait HAL_SPI_STATE_ABORT state */
2350 do
2351 {
2352 if (count == 0U)
2353 {
2354 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2355 break;
2356 }
2357 count--;
2358 } while (hspi->State != HAL_SPI_STATE_ABORT);
2359 /* Reset Timeout Counter */
2360 count = resetcount;
2361 }
2362
2363 /* Disable the SPI DMA Tx request if enabled */
2364 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2365 {
2366 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2367 if (hspi->hdmatx != NULL)
2368 {
2369 /* Set the SPI DMA Abort callback :
2370 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2371 hspi->hdmatx->XferAbortCallback = NULL;
2372
2373 /* Abort DMA Tx Handle linked to SPI Peripheral */
2374 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2375 {
2376 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2377 }
2378
2379 /* Disable Tx DMA Request */
2380 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2381
2382 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2383 {
2384 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2385 }
2386
2387 /* Disable SPI Peripheral */
2388 __HAL_SPI_DISABLE(hspi);
2389
2390 /* Empty the FRLVL fifo */
2391 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2392 {
2393 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2394 }
2395 }
2396 }
2397
2398 /* Disable the SPI DMA Rx request if enabled */
2399 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2400 {
2401 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2402 if (hspi->hdmarx != NULL)
2403 {
2404 /* Set the SPI DMA Abort callback :
2405 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2406 hspi->hdmarx->XferAbortCallback = NULL;
2407
2408 /* Abort DMA Rx Handle linked to SPI Peripheral */
2409 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2410 {
2411 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2412 }
2413
2414 /* Disable peripheral */
2415 __HAL_SPI_DISABLE(hspi);
2416
2417 /* Control the BSY flag */
2418 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2419 {
2420 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2421 }
2422
2423 /* Empty the FRLVL fifo */
2424 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2425 {
2426 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2427 }
2428
2429 /* Disable Rx DMA Request */
2430 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2431 }
2432 }
2433 /* Reset Tx and Rx transfer counters */
2434 hspi->RxXferCount = 0U;
2435 hspi->TxXferCount = 0U;
2436
2437 /* Check error during Abort procedure */
2438 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2439 {
2440 /* return HAL_Error in case of error during Abort procedure */
2441 errorcode = HAL_ERROR;
2442 }
2443 else
2444 {
2445 /* Reset errorCode */
2446 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2447 }
2448
2449 /* Clear the Error flags in the SR register */
2450 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2451 __HAL_SPI_CLEAR_FREFLAG(hspi);
2452
2453 /* Restore hspi->state to ready */
2454 hspi->State = HAL_SPI_STATE_READY;
2455
2456 return errorcode;
2457 }
2458
2459 /**
2460 * @brief Abort ongoing transfer (Interrupt mode).
2461 * @param hspi SPI handle.
2462 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2463 * started in Interrupt or DMA mode.
2464 * This procedure performs following operations :
2465 * - Disable SPI Interrupts (depending of transfer direction)
2466 * - Disable the DMA transfer in the peripheral register (if enabled)
2467 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2468 * - Set handle State to READY
2469 * - At abort completion, call user abort complete callback
2470 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2471 * considered as completed only when user abort complete callback is executed (not when exiting function).
2472 * @retval HAL status
2473 */
HAL_SPI_Abort_IT(SPI_HandleTypeDef * hspi)2474 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2475 {
2476 HAL_StatusTypeDef errorcode;
2477 uint32_t abortcplt ;
2478 __IO uint32_t count;
2479 __IO uint32_t resetcount;
2480
2481 /* Initialized local variable */
2482 errorcode = HAL_OK;
2483 abortcplt = 1U;
2484 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2485 count = resetcount;
2486
2487 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2488 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2489
2490 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2491 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2492 {
2493 hspi->TxISR = SPI_AbortTx_ISR;
2494 /* Wait HAL_SPI_STATE_ABORT state */
2495 do
2496 {
2497 if (count == 0U)
2498 {
2499 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2500 break;
2501 }
2502 count--;
2503 } while (hspi->State != HAL_SPI_STATE_ABORT);
2504 /* Reset Timeout Counter */
2505 count = resetcount;
2506 }
2507
2508 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2509 {
2510 hspi->RxISR = SPI_AbortRx_ISR;
2511 /* Wait HAL_SPI_STATE_ABORT state */
2512 do
2513 {
2514 if (count == 0U)
2515 {
2516 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2517 break;
2518 }
2519 count--;
2520 } while (hspi->State != HAL_SPI_STATE_ABORT);
2521 /* Reset Timeout Counter */
2522 count = resetcount;
2523 }
2524
2525 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2526 before any call to DMA Abort functions */
2527 /* DMA Tx Handle is valid */
2528 if (hspi->hdmatx != NULL)
2529 {
2530 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2531 Otherwise, set it to NULL */
2532 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2533 {
2534 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2535 }
2536 else
2537 {
2538 hspi->hdmatx->XferAbortCallback = NULL;
2539 }
2540 }
2541 /* DMA Rx Handle is valid */
2542 if (hspi->hdmarx != NULL)
2543 {
2544 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2545 Otherwise, set it to NULL */
2546 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2547 {
2548 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2549 }
2550 else
2551 {
2552 hspi->hdmarx->XferAbortCallback = NULL;
2553 }
2554 }
2555
2556 /* Disable the SPI DMA Tx request if enabled */
2557 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2558 {
2559 /* Abort the SPI DMA Tx Stream/Channel */
2560 if (hspi->hdmatx != NULL)
2561 {
2562 /* Abort DMA Tx Handle linked to SPI Peripheral */
2563 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2564 {
2565 hspi->hdmatx->XferAbortCallback = NULL;
2566 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2567 }
2568 else
2569 {
2570 abortcplt = 0U;
2571 }
2572 }
2573 }
2574 /* Disable the SPI DMA Rx request if enabled */
2575 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2576 {
2577 /* Abort the SPI DMA Rx Stream/Channel */
2578 if (hspi->hdmarx != NULL)
2579 {
2580 /* Abort DMA Rx Handle linked to SPI Peripheral */
2581 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2582 {
2583 hspi->hdmarx->XferAbortCallback = NULL;
2584 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2585 }
2586 else
2587 {
2588 abortcplt = 0U;
2589 }
2590 }
2591 }
2592
2593 if (abortcplt == 1U)
2594 {
2595 /* Reset Tx and Rx transfer counters */
2596 hspi->RxXferCount = 0U;
2597 hspi->TxXferCount = 0U;
2598
2599 /* Check error during Abort procedure */
2600 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2601 {
2602 /* return HAL_Error in case of error during Abort procedure */
2603 errorcode = HAL_ERROR;
2604 }
2605 else
2606 {
2607 /* Reset errorCode */
2608 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2609 }
2610
2611 /* Clear the Error flags in the SR register */
2612 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2613 __HAL_SPI_CLEAR_FREFLAG(hspi);
2614
2615 /* Restore hspi->State to Ready */
2616 hspi->State = HAL_SPI_STATE_READY;
2617
2618 /* As no DMA to be aborted, call directly user Abort complete callback */
2619 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2620 hspi->AbortCpltCallback(hspi);
2621 #else
2622 HAL_SPI_AbortCpltCallback(hspi);
2623 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2624 }
2625
2626 return errorcode;
2627 }
2628
2629 /**
2630 * @brief Pause the DMA Transfer.
2631 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2632 * the configuration information for the specified SPI module.
2633 * @retval HAL status
2634 */
HAL_SPI_DMAPause(SPI_HandleTypeDef * hspi)2635 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2636 {
2637 /* Process Locked */
2638 __HAL_LOCK(hspi);
2639
2640 /* Disable the SPI DMA Tx & Rx requests */
2641 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2642
2643 /* Process Unlocked */
2644 __HAL_UNLOCK(hspi);
2645
2646 return HAL_OK;
2647 }
2648
2649 /**
2650 * @brief Resume the DMA Transfer.
2651 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2652 * the configuration information for the specified SPI module.
2653 * @retval HAL status
2654 */
HAL_SPI_DMAResume(SPI_HandleTypeDef * hspi)2655 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2656 {
2657 /* Process Locked */
2658 __HAL_LOCK(hspi);
2659
2660 /* Enable the SPI DMA Tx & Rx requests */
2661 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2662
2663 /* Process Unlocked */
2664 __HAL_UNLOCK(hspi);
2665
2666 return HAL_OK;
2667 }
2668
2669 /**
2670 * @brief Stop the DMA Transfer.
2671 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2672 * the configuration information for the specified SPI module.
2673 * @retval HAL status
2674 */
HAL_SPI_DMAStop(SPI_HandleTypeDef * hspi)2675 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2676 {
2677 HAL_StatusTypeDef errorcode = HAL_OK;
2678 /* The Lock is not implemented on this API to allow the user application
2679 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2680 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2681 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2682 */
2683
2684 /* Abort the SPI DMA tx Stream/Channel */
2685 if (hspi->hdmatx != NULL)
2686 {
2687 if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2688 {
2689 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2690 errorcode = HAL_ERROR;
2691 }
2692 }
2693 /* Abort the SPI DMA rx Stream/Channel */
2694 if (hspi->hdmarx != NULL)
2695 {
2696 if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2697 {
2698 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2699 errorcode = HAL_ERROR;
2700 }
2701 }
2702
2703 /* Disable the SPI DMA Tx & Rx requests */
2704 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2705 hspi->State = HAL_SPI_STATE_READY;
2706 return errorcode;
2707 }
2708
2709 /**
2710 * @brief Handle SPI interrupt request.
2711 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2712 * the configuration information for the specified SPI module.
2713 * @retval None
2714 */
HAL_SPI_IRQHandler(SPI_HandleTypeDef * hspi)2715 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2716 {
2717 uint32_t itsource = hspi->Instance->CR2;
2718 uint32_t itflag = hspi->Instance->SR;
2719
2720 /* SPI in mode Receiver ----------------------------------------------------*/
2721 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2722 (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2723 {
2724 hspi->RxISR(hspi);
2725 return;
2726 }
2727
2728 /* SPI in mode Transmitter -------------------------------------------------*/
2729 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2730 {
2731 hspi->TxISR(hspi);
2732 return;
2733 }
2734
2735 /* SPI in Error Treatment --------------------------------------------------*/
2736 if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2737 || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2738 {
2739 /* SPI Overrun error interrupt occurred ----------------------------------*/
2740 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2741 {
2742 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2743 {
2744 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2745 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2746 }
2747 else
2748 {
2749 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2750 return;
2751 }
2752 }
2753
2754 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2755 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2756 {
2757 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2758 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2759 }
2760
2761 /* SPI Frame error interrupt occurred ------------------------------------*/
2762 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2763 {
2764 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2765 __HAL_SPI_CLEAR_FREFLAG(hspi);
2766 }
2767
2768 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2769 {
2770 /* Disable all interrupts */
2771 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2772
2773 hspi->State = HAL_SPI_STATE_READY;
2774 /* Disable the SPI DMA requests if enabled */
2775 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2776 {
2777 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2778
2779 /* Abort the SPI DMA Rx channel */
2780 if (hspi->hdmarx != NULL)
2781 {
2782 /* Set the SPI DMA Abort callback :
2783 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2784 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2785 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2786 {
2787 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2788 }
2789 }
2790 /* Abort the SPI DMA Tx channel */
2791 if (hspi->hdmatx != NULL)
2792 {
2793 /* Set the SPI DMA Abort callback :
2794 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2795 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2796 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2797 {
2798 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2799 }
2800 }
2801 }
2802 else
2803 {
2804 /* Call user error callback */
2805 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2806 hspi->ErrorCallback(hspi);
2807 #else
2808 HAL_SPI_ErrorCallback(hspi);
2809 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2810 }
2811 }
2812 return;
2813 }
2814 }
2815
2816 /**
2817 * @brief Tx Transfer completed callback.
2818 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2819 * the configuration information for SPI module.
2820 * @retval None
2821 */
HAL_SPI_TxCpltCallback(SPI_HandleTypeDef * hspi)2822 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2823 {
2824 /* Prevent unused argument(s) compilation warning */
2825 UNUSED(hspi);
2826
2827 /* NOTE : This function should not be modified, when the callback is needed,
2828 the HAL_SPI_TxCpltCallback should be implemented in the user file
2829 */
2830 }
2831
2832 /**
2833 * @brief Rx Transfer completed callback.
2834 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2835 * the configuration information for SPI module.
2836 * @retval None
2837 */
HAL_SPI_RxCpltCallback(SPI_HandleTypeDef * hspi)2838 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2839 {
2840 /* Prevent unused argument(s) compilation warning */
2841 UNUSED(hspi);
2842
2843 /* NOTE : This function should not be modified, when the callback is needed,
2844 the HAL_SPI_RxCpltCallback should be implemented in the user file
2845 */
2846 }
2847
2848 /**
2849 * @brief Tx and Rx Transfer completed callback.
2850 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2851 * the configuration information for SPI module.
2852 * @retval None
2853 */
HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef * hspi)2854 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2855 {
2856 /* Prevent unused argument(s) compilation warning */
2857 UNUSED(hspi);
2858
2859 /* NOTE : This function should not be modified, when the callback is needed,
2860 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2861 */
2862 }
2863
2864 /**
2865 * @brief Tx Half Transfer completed callback.
2866 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2867 * the configuration information for SPI module.
2868 * @retval None
2869 */
HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef * hspi)2870 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2871 {
2872 /* Prevent unused argument(s) compilation warning */
2873 UNUSED(hspi);
2874
2875 /* NOTE : This function should not be modified, when the callback is needed,
2876 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2877 */
2878 }
2879
2880 /**
2881 * @brief Rx Half Transfer completed callback.
2882 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2883 * the configuration information for SPI module.
2884 * @retval None
2885 */
HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef * hspi)2886 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2887 {
2888 /* Prevent unused argument(s) compilation warning */
2889 UNUSED(hspi);
2890
2891 /* NOTE : This function should not be modified, when the callback is needed,
2892 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2893 */
2894 }
2895
2896 /**
2897 * @brief Tx and Rx Half Transfer callback.
2898 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2899 * the configuration information for SPI module.
2900 * @retval None
2901 */
HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef * hspi)2902 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2903 {
2904 /* Prevent unused argument(s) compilation warning */
2905 UNUSED(hspi);
2906
2907 /* NOTE : This function should not be modified, when the callback is needed,
2908 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2909 */
2910 }
2911
2912 /**
2913 * @brief SPI error callback.
2914 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2915 * the configuration information for SPI module.
2916 * @retval None
2917 */
HAL_SPI_ErrorCallback(SPI_HandleTypeDef * hspi)2918 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2919 {
2920 /* Prevent unused argument(s) compilation warning */
2921 UNUSED(hspi);
2922
2923 /* NOTE : This function should not be modified, when the callback is needed,
2924 the HAL_SPI_ErrorCallback should be implemented in the user file
2925 */
2926 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2927 and user can use HAL_SPI_GetError() API to check the latest error occurred
2928 */
2929 }
2930
2931 /**
2932 * @brief SPI Abort Complete callback.
2933 * @param hspi SPI handle.
2934 * @retval None
2935 */
HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef * hspi)2936 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2937 {
2938 /* Prevent unused argument(s) compilation warning */
2939 UNUSED(hspi);
2940
2941 /* NOTE : This function should not be modified, when the callback is needed,
2942 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2943 */
2944 }
2945
2946 /**
2947 * @}
2948 */
2949
2950 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2951 * @brief SPI control functions
2952 *
2953 @verbatim
2954 ===============================================================================
2955 ##### Peripheral State and Errors functions #####
2956 ===============================================================================
2957 [..]
2958 This subsection provides a set of functions allowing to control the SPI.
2959 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2960 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2961 @endverbatim
2962 * @{
2963 */
2964
2965 /**
2966 * @brief Return the SPI handle state.
2967 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2968 * the configuration information for SPI module.
2969 * @retval SPI state
2970 */
HAL_SPI_GetState(SPI_HandleTypeDef * hspi)2971 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2972 {
2973 /* Return SPI handle state */
2974 return hspi->State;
2975 }
2976
2977 /**
2978 * @brief Return the SPI error code.
2979 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2980 * the configuration information for SPI module.
2981 * @retval SPI error code in bitmap format
2982 */
HAL_SPI_GetError(SPI_HandleTypeDef * hspi)2983 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2984 {
2985 /* Return SPI ErrorCode */
2986 return hspi->ErrorCode;
2987 }
2988
2989 /**
2990 * @}
2991 */
2992
2993 /**
2994 * @}
2995 */
2996
2997 /** @addtogroup SPI_Private_Functions
2998 * @brief Private functions
2999 * @{
3000 */
3001
3002 /**
3003 * @brief DMA SPI transmit process complete callback.
3004 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3005 * the configuration information for the specified DMA module.
3006 * @retval None
3007 */
SPI_DMATransmitCplt(DMA_HandleTypeDef * hdma)3008 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
3009 {
3010 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3011 uint32_t tickstart;
3012
3013 /* Init tickstart for timeout management*/
3014 tickstart = HAL_GetTick();
3015
3016 /* DMA Normal Mode */
3017 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3018 {
3019 /* Disable ERR interrupt */
3020 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3021
3022 /* Disable Tx DMA Request */
3023 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3024
3025 /* Check the end of the transaction */
3026 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3027 {
3028 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3029 }
3030
3031 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
3032 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3033 {
3034 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3035 }
3036
3037 hspi->TxXferCount = 0U;
3038 hspi->State = HAL_SPI_STATE_READY;
3039
3040 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3041 {
3042 /* Call user error callback */
3043 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3044 hspi->ErrorCallback(hspi);
3045 #else
3046 HAL_SPI_ErrorCallback(hspi);
3047 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3048 return;
3049 }
3050 }
3051 /* Call user Tx complete callback */
3052 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3053 hspi->TxCpltCallback(hspi);
3054 #else
3055 HAL_SPI_TxCpltCallback(hspi);
3056 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3057 }
3058
3059 /**
3060 * @brief DMA SPI receive process complete callback.
3061 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3062 * the configuration information for the specified DMA module.
3063 * @retval None
3064 */
SPI_DMAReceiveCplt(DMA_HandleTypeDef * hdma)3065 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
3066 {
3067 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3068 uint32_t tickstart;
3069 #if (USE_SPI_CRC != 0U)
3070 __IO uint32_t tmpreg = 0U;
3071 #endif /* USE_SPI_CRC */
3072
3073 /* Init tickstart for timeout management*/
3074 tickstart = HAL_GetTick();
3075
3076 /* DMA Normal Mode */
3077 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3078 {
3079 /* Disable ERR interrupt */
3080 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3081
3082 #if (USE_SPI_CRC != 0U)
3083 /* CRC handling */
3084 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3085 {
3086 /* Wait until RXNE flag */
3087 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3088 {
3089 /* Error on the CRC reception */
3090 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3091 }
3092 /* Read CRC */
3093 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
3094 {
3095 /* Read 16bit CRC */
3096 tmpreg = READ_REG(hspi->Instance->DR);
3097 /* To avoid GCC warning */
3098 UNUSED(tmpreg);
3099 }
3100 else
3101 {
3102 /* Read 8bit CRC */
3103 tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3104 /* To avoid GCC warning */
3105 UNUSED(tmpreg);
3106
3107 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
3108 {
3109 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3110 {
3111 /* Error on the CRC reception */
3112 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3113 }
3114 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
3115 tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3116 /* To avoid GCC warning */
3117 UNUSED(tmpreg);
3118 }
3119 }
3120 }
3121 #endif /* USE_SPI_CRC */
3122
3123 /* Check if we are in Master RX 2 line mode */
3124 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
3125 {
3126 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
3127 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3128 }
3129 else
3130 {
3131 /* Normal case */
3132 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3133 }
3134
3135 /* Check the end of the transaction */
3136 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3137 {
3138 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
3139 }
3140
3141 hspi->RxXferCount = 0U;
3142 hspi->State = HAL_SPI_STATE_READY;
3143
3144 #if (USE_SPI_CRC != 0U)
3145 /* Check if CRC error occurred */
3146 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3147 {
3148 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3149 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3150 }
3151 #endif /* USE_SPI_CRC */
3152
3153 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3154 {
3155 /* Call user error callback */
3156 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3157 hspi->ErrorCallback(hspi);
3158 #else
3159 HAL_SPI_ErrorCallback(hspi);
3160 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3161 return;
3162 }
3163 }
3164 /* Call user Rx complete callback */
3165 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3166 hspi->RxCpltCallback(hspi);
3167 #else
3168 HAL_SPI_RxCpltCallback(hspi);
3169 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3170 }
3171
3172 /**
3173 * @brief DMA SPI transmit receive process complete callback.
3174 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3175 * the configuration information for the specified DMA module.
3176 * @retval None
3177 */
SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef * hdma)3178 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3179 {
3180 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3181 uint32_t tickstart;
3182 #if (USE_SPI_CRC != 0U)
3183 __IO uint32_t tmpreg = 0U;
3184 #endif /* USE_SPI_CRC */
3185
3186 /* Init tickstart for timeout management*/
3187 tickstart = HAL_GetTick();
3188
3189 /* DMA Normal Mode */
3190 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3191 {
3192 /* Disable ERR interrupt */
3193 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3194
3195 #if (USE_SPI_CRC != 0U)
3196 /* CRC handling */
3197 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3198 {
3199 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
3200 {
3201 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
3202 tickstart) != HAL_OK)
3203 {
3204 /* Error on the CRC reception */
3205 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3206 }
3207 /* Read CRC to Flush DR and RXNE flag */
3208 tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3209 /* To avoid GCC warning */
3210 UNUSED(tmpreg);
3211 }
3212 else
3213 {
3214 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3215 {
3216 /* Error on the CRC reception */
3217 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3218 }
3219 /* Read CRC to Flush DR and RXNE flag */
3220 tmpreg = READ_REG(hspi->Instance->DR);
3221 /* To avoid GCC warning */
3222 UNUSED(tmpreg);
3223 }
3224 }
3225 #endif /* USE_SPI_CRC */
3226
3227 /* Check the end of the transaction */
3228 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3229 {
3230 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3231 }
3232
3233 /* Disable Rx/Tx DMA Request */
3234 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3235
3236 hspi->TxXferCount = 0U;
3237 hspi->RxXferCount = 0U;
3238 hspi->State = HAL_SPI_STATE_READY;
3239
3240 #if (USE_SPI_CRC != 0U)
3241 /* Check if CRC error occurred */
3242 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3243 {
3244 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3245 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3246 }
3247 #endif /* USE_SPI_CRC */
3248
3249 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3250 {
3251 /* Call user error callback */
3252 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3253 hspi->ErrorCallback(hspi);
3254 #else
3255 HAL_SPI_ErrorCallback(hspi);
3256 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3257 return;
3258 }
3259 }
3260 /* Call user TxRx complete callback */
3261 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3262 hspi->TxRxCpltCallback(hspi);
3263 #else
3264 HAL_SPI_TxRxCpltCallback(hspi);
3265 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3266 }
3267
3268 /**
3269 * @brief DMA SPI half transmit process complete callback.
3270 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3271 * the configuration information for the specified DMA module.
3272 * @retval None
3273 */
SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef * hdma)3274 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
3275 {
3276 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3277
3278 /* Call user Tx half complete callback */
3279 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3280 hspi->TxHalfCpltCallback(hspi);
3281 #else
3282 HAL_SPI_TxHalfCpltCallback(hspi);
3283 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3284 }
3285
3286 /**
3287 * @brief DMA SPI half receive process complete callback
3288 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3289 * the configuration information for the specified DMA module.
3290 * @retval None
3291 */
SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef * hdma)3292 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
3293 {
3294 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3295
3296 /* Call user Rx half complete callback */
3297 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3298 hspi->RxHalfCpltCallback(hspi);
3299 #else
3300 HAL_SPI_RxHalfCpltCallback(hspi);
3301 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3302 }
3303
3304 /**
3305 * @brief DMA SPI half transmit receive process complete callback.
3306 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3307 * the configuration information for the specified DMA module.
3308 * @retval None
3309 */
SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef * hdma)3310 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3311 {
3312 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3313
3314 /* Call user TxRx half complete callback */
3315 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3316 hspi->TxRxHalfCpltCallback(hspi);
3317 #else
3318 HAL_SPI_TxRxHalfCpltCallback(hspi);
3319 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3320 }
3321
3322 /**
3323 * @brief DMA SPI communication error callback.
3324 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3325 * the configuration information for the specified DMA module.
3326 * @retval None
3327 */
SPI_DMAError(DMA_HandleTypeDef * hdma)3328 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3329 {
3330 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3331
3332 /* Stop the disable DMA transfer on SPI side */
3333 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3334
3335 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3336 hspi->State = HAL_SPI_STATE_READY;
3337 /* Call user error callback */
3338 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3339 hspi->ErrorCallback(hspi);
3340 #else
3341 HAL_SPI_ErrorCallback(hspi);
3342 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3343 }
3344
3345 /**
3346 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
3347 * (To be called at end of DMA Abort procedure following error occurrence).
3348 * @param hdma DMA handle.
3349 * @retval None
3350 */
SPI_DMAAbortOnError(DMA_HandleTypeDef * hdma)3351 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3352 {
3353 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3354 hspi->RxXferCount = 0U;
3355 hspi->TxXferCount = 0U;
3356
3357 /* Call user error callback */
3358 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3359 hspi->ErrorCallback(hspi);
3360 #else
3361 HAL_SPI_ErrorCallback(hspi);
3362 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3363 }
3364
3365 /**
3366 * @brief DMA SPI Tx communication abort callback, when initiated by user
3367 * (To be called at end of DMA Tx Abort procedure following user abort request).
3368 * @note When this callback is executed, User Abort complete call back is called only if no
3369 * Abort still ongoing for Rx DMA Handle.
3370 * @param hdma DMA handle.
3371 * @retval None
3372 */
SPI_DMATxAbortCallback(DMA_HandleTypeDef * hdma)3373 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3374 {
3375 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3376
3377 hspi->hdmatx->XferAbortCallback = NULL;
3378
3379 /* Disable Tx DMA Request */
3380 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3381
3382 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3383 {
3384 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3385 }
3386
3387 /* Disable SPI Peripheral */
3388 __HAL_SPI_DISABLE(hspi);
3389
3390 /* Empty the FRLVL fifo */
3391 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3392 {
3393 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3394 }
3395
3396 /* Check if an Abort process is still ongoing */
3397 if (hspi->hdmarx != NULL)
3398 {
3399 if (hspi->hdmarx->XferAbortCallback != NULL)
3400 {
3401 return;
3402 }
3403 }
3404
3405 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3406 hspi->RxXferCount = 0U;
3407 hspi->TxXferCount = 0U;
3408
3409 /* Check no error during Abort procedure */
3410 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3411 {
3412 /* Reset errorCode */
3413 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3414 }
3415
3416 /* Clear the Error flags in the SR register */
3417 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3418 __HAL_SPI_CLEAR_FREFLAG(hspi);
3419
3420 /* Restore hspi->State to Ready */
3421 hspi->State = HAL_SPI_STATE_READY;
3422
3423 /* Call user Abort complete callback */
3424 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3425 hspi->AbortCpltCallback(hspi);
3426 #else
3427 HAL_SPI_AbortCpltCallback(hspi);
3428 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3429 }
3430
3431 /**
3432 * @brief DMA SPI Rx communication abort callback, when initiated by user
3433 * (To be called at end of DMA Rx Abort procedure following user abort request).
3434 * @note When this callback is executed, User Abort complete call back is called only if no
3435 * Abort still ongoing for Tx DMA Handle.
3436 * @param hdma DMA handle.
3437 * @retval None
3438 */
SPI_DMARxAbortCallback(DMA_HandleTypeDef * hdma)3439 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3440 {
3441 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3442
3443 /* Disable SPI Peripheral */
3444 __HAL_SPI_DISABLE(hspi);
3445
3446 hspi->hdmarx->XferAbortCallback = NULL;
3447
3448 /* Disable Rx DMA Request */
3449 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3450
3451 /* Control the BSY flag */
3452 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3453 {
3454 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3455 }
3456
3457 /* Empty the FRLVL fifo */
3458 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3459 {
3460 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3461 }
3462
3463 /* Check if an Abort process is still ongoing */
3464 if (hspi->hdmatx != NULL)
3465 {
3466 if (hspi->hdmatx->XferAbortCallback != NULL)
3467 {
3468 return;
3469 }
3470 }
3471
3472 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3473 hspi->RxXferCount = 0U;
3474 hspi->TxXferCount = 0U;
3475
3476 /* Check no error during Abort procedure */
3477 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3478 {
3479 /* Reset errorCode */
3480 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3481 }
3482
3483 /* Clear the Error flags in the SR register */
3484 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3485 __HAL_SPI_CLEAR_FREFLAG(hspi);
3486
3487 /* Restore hspi->State to Ready */
3488 hspi->State = HAL_SPI_STATE_READY;
3489
3490 /* Call user Abort complete callback */
3491 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3492 hspi->AbortCpltCallback(hspi);
3493 #else
3494 HAL_SPI_AbortCpltCallback(hspi);
3495 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3496 }
3497
3498 /**
3499 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3500 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3501 * the configuration information for SPI module.
3502 * @retval None
3503 */
SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3504 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3505 {
3506 /* Receive data in packing mode */
3507 if (hspi->RxXferCount > 1U)
3508 {
3509 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3510 hspi->pRxBuffPtr += sizeof(uint16_t);
3511 hspi->RxXferCount -= 2U;
3512 if (hspi->RxXferCount == 1U)
3513 {
3514 /* Set RX Fifo threshold according the reception data length: 8bit */
3515 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3516 }
3517 }
3518 /* Receive data in 8 Bit mode */
3519 else
3520 {
3521 *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3522 hspi->pRxBuffPtr++;
3523 hspi->RxXferCount--;
3524 }
3525
3526 /* Check end of the reception */
3527 if (hspi->RxXferCount == 0U)
3528 {
3529 #if (USE_SPI_CRC != 0U)
3530 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3531 {
3532 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3533 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
3534 return;
3535 }
3536 #endif /* USE_SPI_CRC */
3537
3538 /* Disable RXNE and ERR interrupt */
3539 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3540
3541 if (hspi->TxXferCount == 0U)
3542 {
3543 SPI_CloseRxTx_ISR(hspi);
3544 }
3545 }
3546 }
3547
3548 #if (USE_SPI_CRC != 0U)
3549 /**
3550 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3551 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3552 * the configuration information for SPI module.
3553 * @retval None
3554 */
SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3555 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3556 {
3557 __IO uint32_t tmpreg = 0U;
3558
3559 /* Read 8bit CRC to flush Data Register */
3560 tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3561 /* To avoid GCC warning */
3562 UNUSED(tmpreg);
3563
3564 hspi->CRCSize--;
3565
3566 /* Check end of the reception */
3567 if (hspi->CRCSize == 0U)
3568 {
3569 /* Disable RXNE and ERR interrupt */
3570 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3571
3572 if (hspi->TxXferCount == 0U)
3573 {
3574 SPI_CloseRxTx_ISR(hspi);
3575 }
3576 }
3577 }
3578 #endif /* USE_SPI_CRC */
3579
3580 /**
3581 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3582 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3583 * the configuration information for SPI module.
3584 * @retval None
3585 */
SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3586 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3587 {
3588 /* Transmit data in packing Bit mode */
3589 if (hspi->TxXferCount >= 2U)
3590 {
3591 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3592 hspi->pTxBuffPtr += sizeof(uint16_t);
3593 hspi->TxXferCount -= 2U;
3594 }
3595 /* Transmit data in 8 Bit mode */
3596 else
3597 {
3598 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3599 hspi->pTxBuffPtr++;
3600 hspi->TxXferCount--;
3601 }
3602
3603 /* Check the end of the transmission */
3604 if (hspi->TxXferCount == 0U)
3605 {
3606 #if (USE_SPI_CRC != 0U)
3607 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3608 {
3609 /* Set CRC Next Bit to send CRC */
3610 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3611 /* Disable TXE interrupt */
3612 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3613 return;
3614 }
3615 #endif /* USE_SPI_CRC */
3616
3617 /* Disable TXE interrupt */
3618 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3619
3620 if (hspi->RxXferCount == 0U)
3621 {
3622 SPI_CloseRxTx_ISR(hspi);
3623 }
3624 }
3625 }
3626
3627 /**
3628 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3629 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3630 * the configuration information for SPI module.
3631 * @retval None
3632 */
SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3633 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3634 {
3635 /* Receive data in 16 Bit mode */
3636 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3637 hspi->pRxBuffPtr += sizeof(uint16_t);
3638 hspi->RxXferCount--;
3639
3640 if (hspi->RxXferCount == 0U)
3641 {
3642 #if (USE_SPI_CRC != 0U)
3643 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3644 {
3645 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
3646 return;
3647 }
3648 #endif /* USE_SPI_CRC */
3649
3650 /* Disable RXNE interrupt */
3651 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3652
3653 if (hspi->TxXferCount == 0U)
3654 {
3655 SPI_CloseRxTx_ISR(hspi);
3656 }
3657 }
3658 }
3659
3660 #if (USE_SPI_CRC != 0U)
3661 /**
3662 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3663 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3664 * the configuration information for SPI module.
3665 * @retval None
3666 */
SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3667 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3668 {
3669 __IO uint32_t tmpreg = 0U;
3670
3671 /* Read 16bit CRC to flush Data Register */
3672 tmpreg = READ_REG(hspi->Instance->DR);
3673 /* To avoid GCC warning */
3674 UNUSED(tmpreg);
3675
3676 /* Disable RXNE interrupt */
3677 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3678
3679 SPI_CloseRxTx_ISR(hspi);
3680 }
3681 #endif /* USE_SPI_CRC */
3682
3683 /**
3684 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3685 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3686 * the configuration information for SPI module.
3687 * @retval None
3688 */
SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3689 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3690 {
3691 /* Transmit data in 16 Bit mode */
3692 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3693 hspi->pTxBuffPtr += sizeof(uint16_t);
3694 hspi->TxXferCount--;
3695
3696 /* Enable CRC Transmission */
3697 if (hspi->TxXferCount == 0U)
3698 {
3699 #if (USE_SPI_CRC != 0U)
3700 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3701 {
3702 /* Set CRC Next Bit to send CRC */
3703 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3704 /* Disable TXE interrupt */
3705 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3706 return;
3707 }
3708 #endif /* USE_SPI_CRC */
3709
3710 /* Disable TXE interrupt */
3711 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3712
3713 if (hspi->RxXferCount == 0U)
3714 {
3715 SPI_CloseRxTx_ISR(hspi);
3716 }
3717 }
3718 }
3719
3720 #if (USE_SPI_CRC != 0U)
3721 /**
3722 * @brief Manage the CRC 8-bit receive in Interrupt context.
3723 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3724 * the configuration information for SPI module.
3725 * @retval None
3726 */
SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3727 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3728 {
3729 __IO uint32_t tmpreg = 0U;
3730
3731 /* Read 8bit CRC to flush Data Register */
3732 tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3733 /* To avoid GCC warning */
3734 UNUSED(tmpreg);
3735
3736 hspi->CRCSize--;
3737
3738 if (hspi->CRCSize == 0U)
3739 {
3740 SPI_CloseRx_ISR(hspi);
3741 }
3742 }
3743 #endif /* USE_SPI_CRC */
3744
3745 /**
3746 * @brief Manage the receive 8-bit in Interrupt context.
3747 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3748 * the configuration information for SPI module.
3749 * @retval None
3750 */
SPI_RxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3751 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3752 {
3753 *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3754 hspi->pRxBuffPtr++;
3755 hspi->RxXferCount--;
3756
3757 #if (USE_SPI_CRC != 0U)
3758 /* Enable CRC Transmission */
3759 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3760 {
3761 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3762 }
3763 #endif /* USE_SPI_CRC */
3764
3765 if (hspi->RxXferCount == 0U)
3766 {
3767 #if (USE_SPI_CRC != 0U)
3768 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3769 {
3770 hspi->RxISR = SPI_RxISR_8BITCRC;
3771 return;
3772 }
3773 #endif /* USE_SPI_CRC */
3774 SPI_CloseRx_ISR(hspi);
3775 }
3776 }
3777
3778 #if (USE_SPI_CRC != 0U)
3779 /**
3780 * @brief Manage the CRC 16-bit receive in Interrupt context.
3781 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3782 * the configuration information for SPI module.
3783 * @retval None
3784 */
SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3785 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3786 {
3787 __IO uint32_t tmpreg = 0U;
3788
3789 /* Read 16bit CRC to flush Data Register */
3790 tmpreg = READ_REG(hspi->Instance->DR);
3791 /* To avoid GCC warning */
3792 UNUSED(tmpreg);
3793
3794 /* Disable RXNE and ERR interrupt */
3795 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3796
3797 SPI_CloseRx_ISR(hspi);
3798 }
3799 #endif /* USE_SPI_CRC */
3800
3801 /**
3802 * @brief Manage the 16-bit receive in Interrupt context.
3803 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3804 * the configuration information for SPI module.
3805 * @retval None
3806 */
SPI_RxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3807 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3808 {
3809 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3810 hspi->pRxBuffPtr += sizeof(uint16_t);
3811 hspi->RxXferCount--;
3812
3813 #if (USE_SPI_CRC != 0U)
3814 /* Enable CRC Transmission */
3815 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3816 {
3817 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3818 }
3819 #endif /* USE_SPI_CRC */
3820
3821 if (hspi->RxXferCount == 0U)
3822 {
3823 #if (USE_SPI_CRC != 0U)
3824 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3825 {
3826 hspi->RxISR = SPI_RxISR_16BITCRC;
3827 return;
3828 }
3829 #endif /* USE_SPI_CRC */
3830 SPI_CloseRx_ISR(hspi);
3831 }
3832 }
3833
3834 /**
3835 * @brief Handle the data 8-bit transmit in Interrupt mode.
3836 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3837 * the configuration information for SPI module.
3838 * @retval None
3839 */
SPI_TxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3840 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3841 {
3842 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3843 hspi->pTxBuffPtr++;
3844 hspi->TxXferCount--;
3845
3846 if (hspi->TxXferCount == 0U)
3847 {
3848 #if (USE_SPI_CRC != 0U)
3849 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3850 {
3851 /* Enable CRC Transmission */
3852 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3853 }
3854 #endif /* USE_SPI_CRC */
3855 SPI_CloseTx_ISR(hspi);
3856 }
3857 }
3858
3859 /**
3860 * @brief Handle the data 16-bit transmit in Interrupt mode.
3861 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3862 * the configuration information for SPI module.
3863 * @retval None
3864 */
SPI_TxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3865 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3866 {
3867 /* Transmit data in 16 Bit mode */
3868 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3869 hspi->pTxBuffPtr += sizeof(uint16_t);
3870 hspi->TxXferCount--;
3871
3872 if (hspi->TxXferCount == 0U)
3873 {
3874 #if (USE_SPI_CRC != 0U)
3875 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3876 {
3877 /* Enable CRC Transmission */
3878 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3879 }
3880 #endif /* USE_SPI_CRC */
3881 SPI_CloseTx_ISR(hspi);
3882 }
3883 }
3884
3885 /**
3886 * @brief Handle SPI Communication Timeout.
3887 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3888 * the configuration information for SPI module.
3889 * @param Flag SPI flag to check
3890 * @param State flag state to check
3891 * @param Timeout Timeout duration
3892 * @param Tickstart tick start value
3893 * @retval HAL status
3894 */
SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Flag,FlagStatus State,uint32_t Timeout,uint32_t Tickstart)3895 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3896 uint32_t Timeout, uint32_t Tickstart)
3897 {
3898 __IO uint32_t count;
3899 uint32_t tmp_timeout;
3900 uint32_t tmp_tickstart;
3901
3902 /* Adjust Timeout value in case of end of transfer */
3903 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
3904 tmp_tickstart = HAL_GetTick();
3905
3906 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
3907 count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
3908
3909 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3910 {
3911 if (Timeout != HAL_MAX_DELAY)
3912 {
3913 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
3914 {
3915 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3916 on both master and slave sides in order to resynchronize the master
3917 and slave for their respective CRC calculation */
3918
3919 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3920 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3921
3922 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3923 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3924 {
3925 /* Disable SPI peripheral */
3926 __HAL_SPI_DISABLE(hspi);
3927 }
3928
3929 /* Reset CRC Calculation */
3930 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3931 {
3932 SPI_RESET_CRC(hspi);
3933 }
3934
3935 hspi->State = HAL_SPI_STATE_READY;
3936
3937 /* Process Unlocked */
3938 __HAL_UNLOCK(hspi);
3939
3940 return HAL_TIMEOUT;
3941 }
3942 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
3943 if(count == 0U)
3944 {
3945 tmp_timeout = 0U;
3946 }
3947 count--;
3948 }
3949 }
3950
3951 return HAL_OK;
3952 }
3953
3954 /**
3955 * @brief Handle SPI FIFO Communication Timeout.
3956 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3957 * the configuration information for SPI module.
3958 * @param Fifo Fifo to check
3959 * @param State Fifo state to check
3960 * @param Timeout Timeout duration
3961 * @param Tickstart tick start value
3962 * @retval HAL status
3963 */
SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Fifo,uint32_t State,uint32_t Timeout,uint32_t Tickstart)3964 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
3965 uint32_t Timeout, uint32_t Tickstart)
3966 {
3967 __IO uint32_t tmpreg;
3968 __IO uint32_t count;
3969 uint32_t tmp_timeout;
3970 uint32_t tmp_tickstart;
3971
3972 /* Adjust Timeout value in case of end of transfer */
3973 tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
3974 tmp_tickstart = HAL_GetTick();
3975
3976 /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
3977 count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
3978
3979 while ((hspi->Instance->SR & Fifo) != State)
3980 {
3981 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
3982 {
3983 /* Flush Data Register by a blank read */
3984 tmpreg = READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
3985 /* To avoid GCC warning */
3986 UNUSED(tmpreg);
3987 }
3988
3989 if (Timeout != HAL_MAX_DELAY)
3990 {
3991 if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
3992 {
3993 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3994 on both master and slave sides in order to resynchronize the master
3995 and slave for their respective CRC calculation */
3996
3997 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3998 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3999
4000 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4001 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4002 {
4003 /* Disable SPI peripheral */
4004 __HAL_SPI_DISABLE(hspi);
4005 }
4006
4007 /* Reset CRC Calculation */
4008 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
4009 {
4010 SPI_RESET_CRC(hspi);
4011 }
4012
4013 hspi->State = HAL_SPI_STATE_READY;
4014
4015 /* Process Unlocked */
4016 __HAL_UNLOCK(hspi);
4017
4018 return HAL_TIMEOUT;
4019 }
4020 /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
4021 if(count == 0U)
4022 {
4023 tmp_timeout = 0U;
4024 }
4025 count--;
4026 }
4027 }
4028
4029 return HAL_OK;
4030 }
4031
4032 /**
4033 * @brief Handle the check of the RX transaction complete.
4034 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4035 * the configuration information for SPI module.
4036 * @param Timeout Timeout duration
4037 * @param Tickstart tick start value
4038 * @retval HAL status
4039 */
SPI_EndRxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4040 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4041 {
4042 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4043 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4044 {
4045 /* Disable SPI peripheral */
4046 __HAL_SPI_DISABLE(hspi);
4047 }
4048
4049 /* Control the BSY flag */
4050 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4051 {
4052 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4053 return HAL_TIMEOUT;
4054 }
4055
4056 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
4057 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
4058 {
4059 /* Empty the FRLVL fifo */
4060 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4061 {
4062 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4063 return HAL_TIMEOUT;
4064 }
4065 }
4066 return HAL_OK;
4067 }
4068
4069 /**
4070 * @brief Handle the check of the RXTX or TX transaction complete.
4071 * @param hspi SPI handle
4072 * @param Timeout Timeout duration
4073 * @param Tickstart tick start value
4074 * @retval HAL status
4075 */
SPI_EndRxTxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)4076 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
4077 {
4078 /* Control if the TX fifo is empty */
4079 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4080 {
4081 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4082 return HAL_TIMEOUT;
4083 }
4084
4085 /* Control the BSY flag */
4086 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
4087 {
4088 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4089 return HAL_TIMEOUT;
4090 }
4091
4092 /* Control if the RX fifo is empty */
4093 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
4094 {
4095 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4096 return HAL_TIMEOUT;
4097 }
4098
4099 return HAL_OK;
4100 }
4101
4102 /**
4103 * @brief Handle the end of the RXTX transaction.
4104 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4105 * the configuration information for SPI module.
4106 * @retval None
4107 */
SPI_CloseRxTx_ISR(SPI_HandleTypeDef * hspi)4108 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
4109 {
4110 uint32_t tickstart;
4111
4112 /* Init tickstart for timeout management */
4113 tickstart = HAL_GetTick();
4114
4115 /* Disable ERR interrupt */
4116 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
4117
4118 /* Check the end of the transaction */
4119 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4120 {
4121 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4122 }
4123
4124 #if (USE_SPI_CRC != 0U)
4125 /* Check if CRC error occurred */
4126 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4127 {
4128 hspi->State = HAL_SPI_STATE_READY;
4129 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4130 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4131 /* Call user error callback */
4132 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4133 hspi->ErrorCallback(hspi);
4134 #else
4135 HAL_SPI_ErrorCallback(hspi);
4136 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4137 }
4138 else
4139 {
4140 #endif /* USE_SPI_CRC */
4141 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4142 {
4143 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
4144 {
4145 hspi->State = HAL_SPI_STATE_READY;
4146 /* Call user Rx complete callback */
4147 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4148 hspi->RxCpltCallback(hspi);
4149 #else
4150 HAL_SPI_RxCpltCallback(hspi);
4151 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4152 }
4153 else
4154 {
4155 hspi->State = HAL_SPI_STATE_READY;
4156 /* Call user TxRx complete callback */
4157 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4158 hspi->TxRxCpltCallback(hspi);
4159 #else
4160 HAL_SPI_TxRxCpltCallback(hspi);
4161 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4162 }
4163 }
4164 else
4165 {
4166 hspi->State = HAL_SPI_STATE_READY;
4167 /* Call user error callback */
4168 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4169 hspi->ErrorCallback(hspi);
4170 #else
4171 HAL_SPI_ErrorCallback(hspi);
4172 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4173 }
4174 #if (USE_SPI_CRC != 0U)
4175 }
4176 #endif /* USE_SPI_CRC */
4177 }
4178
4179 /**
4180 * @brief Handle the end of the RX transaction.
4181 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4182 * the configuration information for SPI module.
4183 * @retval None
4184 */
SPI_CloseRx_ISR(SPI_HandleTypeDef * hspi)4185 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
4186 {
4187 /* Disable RXNE and ERR interrupt */
4188 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
4189
4190 /* Check the end of the transaction */
4191 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4192 {
4193 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4194 }
4195 hspi->State = HAL_SPI_STATE_READY;
4196
4197 #if (USE_SPI_CRC != 0U)
4198 /* Check if CRC error occurred */
4199 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4200 {
4201 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4202 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4203 /* Call user error callback */
4204 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4205 hspi->ErrorCallback(hspi);
4206 #else
4207 HAL_SPI_ErrorCallback(hspi);
4208 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4209 }
4210 else
4211 {
4212 #endif /* USE_SPI_CRC */
4213 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4214 {
4215 /* Call user Rx complete callback */
4216 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4217 hspi->RxCpltCallback(hspi);
4218 #else
4219 HAL_SPI_RxCpltCallback(hspi);
4220 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4221 }
4222 else
4223 {
4224 /* Call user error callback */
4225 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4226 hspi->ErrorCallback(hspi);
4227 #else
4228 HAL_SPI_ErrorCallback(hspi);
4229 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4230 }
4231 #if (USE_SPI_CRC != 0U)
4232 }
4233 #endif /* USE_SPI_CRC */
4234 }
4235
4236 /**
4237 * @brief Handle the end of the TX transaction.
4238 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4239 * the configuration information for SPI module.
4240 * @retval None
4241 */
SPI_CloseTx_ISR(SPI_HandleTypeDef * hspi)4242 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
4243 {
4244 uint32_t tickstart;
4245
4246 /* Init tickstart for timeout management*/
4247 tickstart = HAL_GetTick();
4248
4249 /* Disable TXE and ERR interrupt */
4250 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
4251
4252 /* Check the end of the transaction */
4253 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4254 {
4255 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4256 }
4257
4258 /* Clear overrun flag in 2 Lines communication mode because received is not read */
4259 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
4260 {
4261 __HAL_SPI_CLEAR_OVRFLAG(hspi);
4262 }
4263
4264 hspi->State = HAL_SPI_STATE_READY;
4265 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
4266 {
4267 /* Call user error callback */
4268 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4269 hspi->ErrorCallback(hspi);
4270 #else
4271 HAL_SPI_ErrorCallback(hspi);
4272 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4273 }
4274 else
4275 {
4276 /* Call user Rx complete callback */
4277 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4278 hspi->TxCpltCallback(hspi);
4279 #else
4280 HAL_SPI_TxCpltCallback(hspi);
4281 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4282 }
4283 }
4284
4285 /**
4286 * @brief Handle abort a Rx transaction.
4287 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4288 * the configuration information for SPI module.
4289 * @retval None
4290 */
SPI_AbortRx_ISR(SPI_HandleTypeDef * hspi)4291 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
4292 {
4293 __IO uint32_t count;
4294
4295 /* Disable SPI Peripheral */
4296 __HAL_SPI_DISABLE(hspi);
4297
4298 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4299
4300 /* Disable RXNEIE interrupt */
4301 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4302
4303 /* Check RXNEIE is disabled */
4304 do
4305 {
4306 if (count == 0U)
4307 {
4308 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4309 break;
4310 }
4311 count--;
4312 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4313
4314 /* Control the BSY flag */
4315 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4316 {
4317 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4318 }
4319
4320 /* Empty the FRLVL fifo */
4321 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4322 {
4323 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4324 }
4325
4326 hspi->State = HAL_SPI_STATE_ABORT;
4327 }
4328
4329 /**
4330 * @brief Handle abort a Tx or Rx/Tx transaction.
4331 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4332 * the configuration information for SPI module.
4333 * @retval None
4334 */
SPI_AbortTx_ISR(SPI_HandleTypeDef * hspi)4335 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
4336 {
4337 __IO uint32_t count;
4338
4339 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4340
4341 /* Disable TXEIE interrupt */
4342 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
4343
4344 /* Check TXEIE is disabled */
4345 do
4346 {
4347 if (count == 0U)
4348 {
4349 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4350 break;
4351 }
4352 count--;
4353 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
4354
4355 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4356 {
4357 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4358 }
4359
4360 /* Disable SPI Peripheral */
4361 __HAL_SPI_DISABLE(hspi);
4362
4363 /* Empty the FRLVL fifo */
4364 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4365 {
4366 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4367 }
4368
4369 /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
4370 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
4371 {
4372 /* Disable RXNEIE interrupt */
4373 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4374
4375 /* Check RXNEIE is disabled */
4376 do
4377 {
4378 if (count == 0U)
4379 {
4380 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4381 break;
4382 }
4383 count--;
4384 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4385
4386 /* Control the BSY flag */
4387 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4388 {
4389 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4390 }
4391
4392 /* Empty the FRLVL fifo */
4393 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4394 {
4395 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4396 }
4397 }
4398 hspi->State = HAL_SPI_STATE_ABORT;
4399 }
4400
4401 /**
4402 * @}
4403 */
4404
4405 #endif /* HAL_SPI_MODULE_ENABLED */
4406
4407 /**
4408 * @}
4409 */
4410
4411 /**
4412 * @}
4413 */
4414
4415 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4416
