1 /**
2 ******************************************************************************
3 * @file stm32l5xx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @brief Extended PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Extended Initialization and de-initialization functions
9 * + Extended Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
15 * All rights reserved.</center></h2>
16 *
17 * This software component is licensed by ST under BSD 3-Clause license,
18 * the "License"; You may not use this file except in compliance with the
19 * License. You may obtain a copy of the License at:
20 * opensource.org/licenses/BSD-3-Clause
21 *
22 ******************************************************************************
23 */
24
25 /* Includes ------------------------------------------------------------------*/
26 #include "stm32l5xx_hal.h"
27
28 /** @addtogroup STM32L5xx_HAL_Driver
29 * @{
30 */
31
32 /** @defgroup PWREx PWREx
33 * @brief PWR Extended HAL module driver
34 * @{
35 */
36
37 #ifdef HAL_PWR_MODULE_ENABLED
38
39 /* Private typedef -----------------------------------------------------------*/
40 /* Private define ------------------------------------------------------------*/
41
42 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
43 * @{
44 */
45
46 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
47
48 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
49 * @{
50 */
51 #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */
52 #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */
53 #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */
54 #define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */
55 /**
56 * @}
57 */
58
59 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
60 * @{
61 */
62 #define PWR_REGLP_SETTING_DELAY_VALUE 300UL /*!< Time out value for REGLPF flag setting */
63
64 #define PWR_VOSF_SETTING_DELAY_VALUE 50UL /*!< Time out value for VOSF flag setting */
65
66 #define PWR_MODE_CHANGE_DELAY_VALUE 1000UL /*!< Time out for step down converter operating mode */
67
68 /**
69 * @}
70 */
71
72 /**
73 * @}
74 */
75
76 /* Private macro -------------------------------------------------------------*/
77 /* Private variables ---------------------------------------------------------*/
78 /* Private function prototypes -----------------------------------------------*/
79 /* Exported functions --------------------------------------------------------*/
80
81 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
82 * @{
83 */
84
85 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
86 * @brief Extended Peripheral Control functions
87 *
88 @verbatim
89 ===============================================================================
90 ##### Extended Peripheral Initialization and de-initialization functions #####
91 ===============================================================================
92 [..]
93
94 @endverbatim
95 * @{
96 */
97
98
99 /**
100 * @brief Return Voltage Scaling Range.
101 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE0, PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2)
102 */
HAL_PWREx_GetVoltageRange(void)103 uint32_t HAL_PWREx_GetVoltageRange(void)
104 {
105 return (PWR->CR1 & PWR_CR1_VOS);
106 }
107
108 /**
109 * @brief Configure the main internal regulator output voltage.
110 * @param VoltageScaling specifies the regulator output voltage to achieve
111 * a tradeoff between performance and power consumption.
112 * This parameter can be one of the following values:
113 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE0 Regulator voltage output range 0 mode,
114 * typical output voltage at 1.28 V,
115 * system frequency up to 100 MHz.
116 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
117 * typical output voltage at 1.2 V,
118 * system frequency up to 80 MHz.
119 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
120 * typical output voltage at 1.0 V,
121 * system frequency up to 26 MHz.
122 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
123 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
124 * When moving from Range 2 to Range 1, the system frequency can be increased to
125 * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
126 * @note When moving from one Range to another , the API waits for VOSF flag to be
127 * cleared before returning the status. If the flag is not cleared within limited time duration,
128 * HAL_TIMEOUT status is reported.
129 * @note The VOS shall NOT be changed in LP Mode of if LP mode is asked.
130 * @note The function shall not be called in Low-power run mode (meaningless and misleading).
131 * @retval HAL Status
132 */
HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)133 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
134 {
135 uint32_t wait_loop_index;
136
137 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
138
139 uint32_t vos_old = READ_BIT(PWR->CR1, PWR_CR1_VOS);
140
141 /* VOS shall not be changed in LP Mode */
142 /* or if LP Mode is asked but not yet established */
143 if (HAL_PWREx_SMPS_GetEffectiveMode() == PWR_SMPS_LOW_POWER)
144 {
145 return HAL_ERROR;
146 }
147 if (READ_BIT(PWR->CR4, PWR_CR4_SMPSLPEN) == PWR_CR4_SMPSLPEN)
148 {
149 return HAL_ERROR;
150 }
151
152 /* No change, nothing to do */
153 if (vos_old == VoltageScaling)
154 {
155 return HAL_OK;
156 }
157
158 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
159
160 /* Wait until VOSF is cleared */
161 /* and at least one iteration loop */
162 wait_loop_index = ((PWR_VOSF_SETTING_DELAY_VALUE * (SystemCoreClock / 100000U)) / 10U) + 1U;
163
164 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
165 {
166 wait_loop_index--;
167 }
168
169 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
170 {
171 return HAL_TIMEOUT;
172 }
173
174 return HAL_OK;
175 }
176
177 /**
178 * @brief Enable battery charging.
179 * When VDD is present, charge the external battery on VBAT through an internal resistor.
180 * @param ResistorSelection specifies the resistor impedance.
181 * This parameter can be one of the following values:
182 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
183 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
184 * @retval None
185 */
HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)186 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
187 {
188 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
189
190 /* Specify resistor selection */
191 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
192
193 /* Enable battery charging */
194 SET_BIT(PWR->CR4, PWR_CR4_VBE);
195 }
196
197
198 /**
199 * @brief Disable battery charging.
200 * @retval None
201 */
HAL_PWREx_DisableBatteryCharging(void)202 void HAL_PWREx_DisableBatteryCharging(void)
203 {
204 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
205 }
206
207
208 #if defined(PWR_CR2_USV)
209 /**
210 * @brief Enable VDDUSB supply.
211 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
212 * @retval None
213 */
HAL_PWREx_EnableVddUSB(void)214 void HAL_PWREx_EnableVddUSB(void)
215 {
216 SET_BIT(PWR->CR2, PWR_CR2_USV);
217 }
218
219
220 /**
221 * @brief Disable VDDUSB supply.
222 * @retval None
223 */
HAL_PWREx_DisableVddUSB(void)224 void HAL_PWREx_DisableVddUSB(void)
225 {
226 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
227 }
228 #endif /* PWR_CR2_USV */
229
230 /**
231 * @brief Enable VDDIO2 supply.
232 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
233 * @retval None
234 */
HAL_PWREx_EnableVddIO2(void)235 void HAL_PWREx_EnableVddIO2(void)
236 {
237 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
238 }
239
240 /**
241 * @brief Disable VDDIO2 supply.
242 * @retval None
243 */
HAL_PWREx_DisableVddIO2(void)244 void HAL_PWREx_DisableVddIO2(void)
245 {
246 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
247 }
248
249 /**
250 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
251 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
252 * pull-up state in Standby and Shutdown modes.
253 * @note This state is effective in Standby and Shutdown modes only if APC bit
254 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
255 * @note The configuration is lost when exiting the Shutdown mode due to the
256 * power-on reset, maintained when exiting the Standby mode.
257 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
258 * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
259 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input
260 * parameter at the same time are set.
261 * @param GPIO specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
262 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
263 * @param GPIONumber specifies the I/O pins numbers.
264 * This parameter can be one of the following values:
265 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
266 * I/O pins are available) or the logical OR of several of them to set
267 * several bits for a given port in a single API call.
268 * @retval HAL Status
269 */
HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)270 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
271 {
272 HAL_StatusTypeDef status = HAL_OK;
273
274 assert_param(IS_PWR_GPIO(GPIO));
275 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
276
277 switch (GPIO)
278 {
279 case PWR_GPIO_A:
280 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
281 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
282 break;
283 case PWR_GPIO_B:
284 SET_BIT(PWR->PUCRB, GPIONumber);
285 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
286 break;
287 case PWR_GPIO_C:
288 SET_BIT(PWR->PUCRC, GPIONumber);
289 CLEAR_BIT(PWR->PDCRC, GPIONumber);
290 break;
291 case PWR_GPIO_D:
292 SET_BIT(PWR->PUCRD, GPIONumber);
293 CLEAR_BIT(PWR->PDCRD, GPIONumber);
294 break;
295 case PWR_GPIO_E:
296 SET_BIT(PWR->PUCRE, GPIONumber);
297 CLEAR_BIT(PWR->PDCRE, GPIONumber);
298 break;
299 case PWR_GPIO_F:
300 SET_BIT(PWR->PUCRF, GPIONumber);
301 CLEAR_BIT(PWR->PDCRF, GPIONumber);
302 break;
303 case PWR_GPIO_G:
304 SET_BIT(PWR->PUCRG, GPIONumber);
305 CLEAR_BIT(PWR->PDCRG, GPIONumber);
306 break;
307 case PWR_GPIO_H:
308 SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
309 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
310 break;
311 default:
312 status = HAL_ERROR;
313 break;
314 }
315
316 return status;
317 }
318
319
320 /**
321 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
322 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
323 * in pull-up state in Standby and Shutdown modes.
324 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input
325 * parameter at the same time are reset.
326 * @param GPIO specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
327 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
328 * @param GPIONumber specifies the I/O pins numbers.
329 * This parameter can be one of the following values:
330 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
331 * I/O pins are available) or the logical OR of several of them to reset
332 * several bits for a given port in a single API call.
333 * @retval HAL Status
334 */
HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)335 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
336 {
337 HAL_StatusTypeDef status = HAL_OK;
338
339 assert_param(IS_PWR_GPIO(GPIO));
340 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
341
342 switch (GPIO)
343 {
344 case PWR_GPIO_A:
345 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
346 break;
347 case PWR_GPIO_B:
348 CLEAR_BIT(PWR->PUCRB, GPIONumber);
349 break;
350 case PWR_GPIO_C:
351 CLEAR_BIT(PWR->PUCRC, GPIONumber);
352 break;
353 case PWR_GPIO_D:
354 CLEAR_BIT(PWR->PUCRD, GPIONumber);
355 break;
356 case PWR_GPIO_E:
357 CLEAR_BIT(PWR->PUCRE, GPIONumber);
358 break;
359 case PWR_GPIO_F:
360 CLEAR_BIT(PWR->PUCRF, GPIONumber);
361 break;
362 case PWR_GPIO_G:
363 CLEAR_BIT(PWR->PUCRG, GPIONumber);
364 break;
365 case PWR_GPIO_H:
366 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
367 break;
368 default:
369 status = HAL_ERROR;
370 break;
371 }
372
373 return status;
374 }
375
376
377
378 /**
379 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
380 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
381 * pull-down state in Standby and Shutdown modes.
382 * @note This state is effective in Standby and Shutdown modes only if APC bit
383 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
384 * @note The configuration is lost when exiting the Shutdown mode due to the
385 * power-on reset, maintained when exiting the Standby mode.
386 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
387 * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
388 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input
389 * parameter at the same time are set.
390 * @param GPIO specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
391 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
392 * @param GPIONumber specifies the I/O pins numbers.
393 * This parameter can be one of the following values:
394 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
395 * I/O pins are available) or the logical OR of several of them to set
396 * several bits for a given port in a single API call.
397 * @retval HAL Status
398 */
HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)399 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
400 {
401 HAL_StatusTypeDef status = HAL_OK;
402
403 assert_param(IS_PWR_GPIO(GPIO));
404 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
405
406 switch (GPIO)
407 {
408 case PWR_GPIO_A:
409 SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
410 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
411 break;
412 case PWR_GPIO_B:
413 SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
414 CLEAR_BIT(PWR->PUCRB, GPIONumber);
415 break;
416 case PWR_GPIO_C:
417 SET_BIT(PWR->PDCRC, GPIONumber);
418 CLEAR_BIT(PWR->PUCRC, GPIONumber);
419 break;
420 case PWR_GPIO_D:
421 SET_BIT(PWR->PDCRD, GPIONumber);
422 CLEAR_BIT(PWR->PUCRD, GPIONumber);
423 break;
424 case PWR_GPIO_E:
425 SET_BIT(PWR->PDCRE, GPIONumber);
426 CLEAR_BIT(PWR->PUCRE, GPIONumber);
427 break;
428 case PWR_GPIO_F:
429 SET_BIT(PWR->PDCRF, GPIONumber);
430 CLEAR_BIT(PWR->PUCRF, GPIONumber);
431 break;
432 case PWR_GPIO_G:
433 SET_BIT(PWR->PDCRG, GPIONumber);
434 CLEAR_BIT(PWR->PUCRG, GPIONumber);
435 break;
436 case PWR_GPIO_H:
437 SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
438 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
439 break;
440 default:
441 status = HAL_ERROR;
442 break;
443 }
444
445 return status;
446 }
447
448
449 /**
450 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
451 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
452 * in pull-down state in Standby and Shutdown modes.
453 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
454 * parameter at the same time are reset.
455 * @param GPIO specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
456 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
457 * @param GPIONumber specifies the I/O pins numbers.
458 * This parameter can be one of the following values:
459 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
460 * I/O pins are available) or the logical OR of several of them to reset
461 * several bits for a given port in a single API call.
462 * @retval HAL Status
463 */
HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)464 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
465 {
466 HAL_StatusTypeDef status = HAL_OK;
467
468 assert_param(IS_PWR_GPIO(GPIO));
469 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
470
471 switch (GPIO)
472 {
473 case PWR_GPIO_A:
474 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
475 break;
476 case PWR_GPIO_B:
477 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
478 break;
479 case PWR_GPIO_C:
480 CLEAR_BIT(PWR->PDCRC, GPIONumber);
481 break;
482 case PWR_GPIO_D:
483 CLEAR_BIT(PWR->PDCRD, GPIONumber);
484 break;
485 case PWR_GPIO_E:
486 CLEAR_BIT(PWR->PDCRE, GPIONumber);
487 break;
488 case PWR_GPIO_F:
489 CLEAR_BIT(PWR->PDCRF, GPIONumber);
490 break;
491 case PWR_GPIO_G:
492 CLEAR_BIT(PWR->PDCRG, GPIONumber);
493 break;
494 case PWR_GPIO_H:
495 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
496 break;
497 default:
498 status = HAL_ERROR;
499 break;
500 }
501
502 return status;
503 }
504
505
506
507 /**
508 * @brief Enable pull-up and pull-down configuration.
509 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
510 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
511 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
512 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
513 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
514 * is no conflict when setting PUy or PDy bit.
515 * @retval None
516 */
HAL_PWREx_EnablePullUpPullDownConfig(void)517 void HAL_PWREx_EnablePullUpPullDownConfig(void)
518 {
519 SET_BIT(PWR->CR3, PWR_CR3_APC);
520 }
521
522
523 /**
524 * @brief Disable pull-up and pull-down configuration.
525 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
526 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
527 * @retval None
528 */
HAL_PWREx_DisablePullUpPullDownConfig(void)529 void HAL_PWREx_DisablePullUpPullDownConfig(void)
530 {
531 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
532 }
533
534
535 /**
536 * @brief Configure SRAM2 content retention in Standby mode.
537 * @param SRAM2ContentRetention This parameter can be one of the following values:
538 * @arg @ref PWR_NO_SRAM2_RETENTION
539 * @arg @ref PWR_FULL_SRAM2_RETENTION
540 * @arg @ref PWR_4KBYTES_SRAM2_RETENTION
541 * @note This feature is secured by SMLPM bit when system implements security (TZEN=1).
542 * @retval HAL Status
543 */
HAL_PWREx_ConfigSRAM2ContentRetention(uint32_t SRAM2ContentRetention)544 HAL_StatusTypeDef HAL_PWREx_ConfigSRAM2ContentRetention(uint32_t SRAM2ContentRetention)
545 {
546 /* Check the parameters */
547 assert_param(IS_PWR_SRAM2CONTENT_RETENTION(SRAM2ContentRetention));
548
549 /* Set RRS bits */
550 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAM2ContentRetention);
551
552 return HAL_OK;
553 }
554
555
556 /**
557 * @brief Enable SRAM2 content retention in Standby mode.
558 * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in
559 * Standby mode and its content is kept.
560 * @retval None
561 */
HAL_PWREx_EnableSRAM2ContentRetention(void)562 void HAL_PWREx_EnableSRAM2ContentRetention(void)
563 {
564 (void) HAL_PWREx_ConfigSRAM2ContentRetention(PWR_FULL_SRAM2_RETENTION);
565 }
566
567
568 /**
569 * @brief Disable SRAM2 content retention in Standby mode.
570 * @note When RRS bit is reset, SRAM2 is powered off in Standby mode
571 * and its content is lost.
572 * @retval None
573 */
HAL_PWREx_DisableSRAM2ContentRetention(void)574 void HAL_PWREx_DisableSRAM2ContentRetention(void)
575 {
576 (void) HAL_PWREx_ConfigSRAM2ContentRetention(PWR_NO_SRAM2_RETENTION);
577 }
578
579
580 /**
581 * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2 V.
582 * @retval None
583 */
HAL_PWREx_EnablePVM1(void)584 void HAL_PWREx_EnablePVM1(void)
585 {
586 SET_BIT(PWR->CR2, PWR_PVM_1);
587 }
588
589 /**
590 * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2 V.
591 * @retval None
592 */
HAL_PWREx_DisablePVM1(void)593 void HAL_PWREx_DisablePVM1(void)
594 {
595 CLEAR_BIT(PWR->CR2, PWR_PVM_1);
596 }
597
598 /**
599 * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9 V.
600 * @retval None
601 */
HAL_PWREx_EnablePVM2(void)602 void HAL_PWREx_EnablePVM2(void)
603 {
604 SET_BIT(PWR->CR2, PWR_PVM_2);
605 }
606
607 /**
608 * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9 V.
609 * @retval None
610 */
HAL_PWREx_DisablePVM2(void)611 void HAL_PWREx_DisablePVM2(void)
612 {
613 CLEAR_BIT(PWR->CR2, PWR_PVM_2);
614 }
615
616
617 /**
618 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62 V.
619 * @retval None
620 */
HAL_PWREx_EnablePVM3(void)621 void HAL_PWREx_EnablePVM3(void)
622 {
623 SET_BIT(PWR->CR2, PWR_PVM_3);
624 }
625
626 /**
627 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62 V.
628 * @retval None
629 */
HAL_PWREx_DisablePVM3(void)630 void HAL_PWREx_DisablePVM3(void)
631 {
632 CLEAR_BIT(PWR->CR2, PWR_PVM_3);
633 }
634
635
636 /**
637 * @brief Enable the Power Voltage Monitoring 4: VDDA versus 1.8 V.
638 * @retval None
639 */
HAL_PWREx_EnablePVM4(void)640 void HAL_PWREx_EnablePVM4(void)
641 {
642 SET_BIT(PWR->CR2, PWR_PVM_4);
643 }
644
645 /**
646 * @brief Disable the Power Voltage Monitoring 4: VDDA versus 1.8 V.
647 * @retval None
648 */
HAL_PWREx_DisablePVM4(void)649 void HAL_PWREx_DisablePVM4(void)
650 {
651 CLEAR_BIT(PWR->CR2, PWR_PVM_4);
652 }
653
654
655
656
657 /**
658 * @brief Configure the Peripheral Voltage Monitoring (PVM).
659 * @param sConfigPVM pointer to a PWR_PVMTypeDef structure that contains the
660 * PVM configuration information.
661 * @note The API configures a single PVM according to the information contained
662 * in the input structure. To configure several PVMs, the API must be singly
663 * called for each PVM used.
664 * @note Refer to the electrical characteristics of your device datasheet for
665 * more details about the voltage thresholds corresponding to each
666 * detection level and to each monitored supply.
667 * @retval HAL status
668 */
HAL_PWREx_ConfigPVM(PWR_PVMTypeDef * sConfigPVM)669 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
670 {
671 HAL_StatusTypeDef status = HAL_OK;
672
673 /* Check the parameters */
674 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
675 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
676
677
678 /* Configure EXTI 35 to 38 interrupts if so required:
679 scan through PVMType to detect which PVMx is set and
680 configure the corresponding EXTI line accordingly. */
681 switch (sConfigPVM->PVMType)
682 {
683 case PWR_PVM_1:
684 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
685 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
686 __HAL_PWR_PVM1_EXTI_DISABLE_IT();
687 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
688 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
689
690 /* Configure interrupt mode */
691 if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
692 {
693 __HAL_PWR_PVM1_EXTI_ENABLE_IT();
694 }
695
696 /* Configure event mode */
697 if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
698 {
699 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
700 }
701
702 /* Configure the edge */
703 if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
704 {
705 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
706 }
707
708 if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
709 {
710 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
711 }
712 break;
713
714 case PWR_PVM_2:
715 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
716 __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
717 __HAL_PWR_PVM2_EXTI_DISABLE_IT();
718 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
719 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
720
721 /* Configure interrupt mode */
722 if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
723 {
724 __HAL_PWR_PVM2_EXTI_ENABLE_IT();
725 }
726
727 /* Configure event mode */
728 if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
729 {
730 __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
731 }
732
733 /* Configure the edge */
734 if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
735 {
736 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
737 }
738
739 if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
740 {
741 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
742 }
743 break;
744
745 case PWR_PVM_3:
746 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
747 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
748 __HAL_PWR_PVM3_EXTI_DISABLE_IT();
749 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
750 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
751
752 /* Configure interrupt mode */
753 if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
754 {
755 __HAL_PWR_PVM3_EXTI_ENABLE_IT();
756 }
757
758 /* Configure event mode */
759 if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
760 {
761 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
762 }
763
764 /* Configure the edge */
765 if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
766 {
767 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
768 }
769
770 if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
771 {
772 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
773 }
774 break;
775
776 case PWR_PVM_4:
777 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
778 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
779 __HAL_PWR_PVM4_EXTI_DISABLE_IT();
780 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
781 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
782
783 /* Configure interrupt mode */
784 if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
785 {
786 __HAL_PWR_PVM4_EXTI_ENABLE_IT();
787 }
788
789 /* Configure event mode */
790 if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
791 {
792 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
793 }
794
795 /* Configure the edge */
796 if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
797 {
798 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
799 }
800
801 if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
802 {
803 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
804 }
805 break;
806
807 default:
808 status = HAL_ERROR;
809 break;
810 }
811
812 return status;
813 }
814
815
816
817 /**
818 * @brief Enter Low-power Run mode
819 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
820 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
821 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
822 * Additionally, the clock frequency must be reduced below 2 MHz.
823 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
824 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
825 * @retval None
826 */
HAL_PWREx_EnableLowPowerRunMode(void)827 void HAL_PWREx_EnableLowPowerRunMode(void)
828 {
829 /* Set Regulator parameter */
830 SET_BIT(PWR->CR1, PWR_CR1_LPR);
831 }
832
833
834 /**
835 * @brief Exit Low-power Run mode.
836 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
837 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
838 * returns HAL_TIMEOUT status). The system clock frequency can then be
839 * increased above 2 MHz.
840 * @retval HAL Status
841 */
HAL_PWREx_DisableLowPowerRunMode(void)842 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
843 {
844 uint32_t wait_loop_index;
845
846 /* Clear LPR bit */
847 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
848
849 /* Wait until REGLPF is reset */
850 /* and at least one iteration loop */
851 wait_loop_index = ((PWR_REGLP_SETTING_DELAY_VALUE * (SystemCoreClock / 100000U)) / 10U) + 1U;
852
853 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
854 {
855 wait_loop_index--;
856 }
857 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
858 {
859 return HAL_TIMEOUT;
860 }
861
862 return HAL_OK;
863 }
864
865
866 /**
867 * @brief Enter Stop 0 mode.
868 * @note In Stop 0 mode, main and low voltage regulators are ON.
869 * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode.
870 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
871 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
872 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
873 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
874 * only to the peripheral requesting it.
875 * SRAM1, SRAM2 and register contents are preserved.
876 * The BOR is available.
877 * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
878 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
879 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
880 * @note By keeping the internal regulator ON during Stop 0 mode, the consumption
881 * is higher although the startup time is reduced.
882 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
883 * This parameter can be one of the following values:
884 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
885 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
886 * @retval None
887 */
HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)888 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
889 {
890 /* Check the parameters */
891 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
892
893 /* Stop 0 mode with Main Regulator */
894 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
895
896 /* Set SLEEPDEEP bit of Cortex System Control Register */
897 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
898
899 /* Select Stop mode entry --------------------------------------------------*/
900 if (STOPEntry == PWR_STOPENTRY_WFI)
901 {
902 /* Request Wait For Interrupt */
903 __WFI();
904 }
905 else
906 {
907 /* Request Wait For Event */
908 __SEV();
909 __WFE();
910 __WFE();
911 }
912
913 /* Reset SLEEPDEEP bit of Cortex System Control Register */
914 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
915 }
916
917
918 /**
919 * @brief Enter Stop 1 mode.
920 * @note In Stop 1 mode, only low power voltage regulator is ON.
921 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
922 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
923 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
924 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
925 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
926 * only to the peripheral requesting it.
927 * SRAM1, SRAM2 and register contents are preserved.
928 * The BOR is available.
929 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
930 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
931 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
932 * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
933 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
934 * This parameter can be one of the following values:
935 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
936 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
937 * @retval None
938 */
HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)939 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
940 {
941 /* Check the parameters */
942 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
943
944 /* Stop 1 mode with Low-Power Regulator */
945 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
946
947 /* Set SLEEPDEEP bit of Cortex System Control Register */
948 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
949
950 /* Select Stop mode entry --------------------------------------------------*/
951 if (STOPEntry == PWR_STOPENTRY_WFI)
952 {
953 /* Request Wait For Interrupt */
954 __WFI();
955 }
956 else
957 {
958 /* Request Wait For Event */
959 __SEV();
960 __WFE();
961 __WFE();
962 }
963
964 /* Reset SLEEPDEEP bit of Cortex System Control Register */
965 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
966 }
967
968
969 /**
970 * @brief Enter Stop 2 mode.
971 * @note In Stop 2 mode, only low power voltage regulator is ON.
972 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode.
973 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI,
974 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
975 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
976 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
977 * to the peripheral requesting it.
978 * SRAM1, SRAM2 and register contents are preserved.
979 * The BOR is available.
980 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
981 * Otherwise, Stop 1 mode is entered.
982 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
983 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
984 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
985 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
986 * This parameter can be one of the following values:
987 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
988 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
989 * @retval None
990 */
HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)991 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
992 {
993 /* Check the parameter */
994 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
995
996 /* Set Stop mode 2 */
997 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);
998
999 /* Set SLEEPDEEP bit of Cortex System Control Register */
1000 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1001
1002 /* Select Stop mode entry --------------------------------------------------*/
1003 if (STOPEntry == PWR_STOPENTRY_WFI)
1004 {
1005 /* Request Wait For Interrupt */
1006 __WFI();
1007 }
1008 else
1009 {
1010 /* Request Wait For Event */
1011 __SEV();
1012 __WFE();
1013 __WFE();
1014 }
1015
1016 /* Reset SLEEPDEEP bit of Cortex System Control Register */
1017 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1018 }
1019
1020
1021
1022
1023
1024 /**
1025 * @brief Enter Shutdown mode.
1026 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
1027 * off. The voltage regulator is disabled and Vcore domain is powered off.
1028 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
1029 * The BOR is not available.
1030 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
1031 * @retval None
1032 */
HAL_PWREx_EnterSHUTDOWNMode(void)1033 void HAL_PWREx_EnterSHUTDOWNMode(void)
1034 {
1035
1036 /* Set Shutdown mode */
1037 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
1038
1039 /* Set SLEEPDEEP bit of Cortex System Control Register */
1040 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1041
1042 /* This option is used to ensure that store operations are completed */
1043 #if defined ( __CC_ARM)
1044 __force_stores();
1045 #endif
1046 /* Request Wait For Interrupt */
1047 __WFI();
1048 }
1049
1050
1051
1052
1053 /**
1054 * @brief This function handles the PWR PVD/PVMx interrupt request.
1055 * @note This API should be called under the PVD_PVM_IRQHandler().
1056 * @retval None
1057 */
HAL_PWREx_PVD_PVM_IRQHandler(void)1058 void HAL_PWREx_PVD_PVM_IRQHandler(void)
1059 {
1060 uint32_t rising_flag;
1061 uint32_t falling_flag;
1062
1063 rising_flag = READ_REG(EXTI->RPR1);
1064 falling_flag = READ_REG(EXTI->FPR1);
1065
1066 /* Check PWR exti flags for PVD */
1067 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0x0U)
1068 {
1069 /* PWR PVD interrupt user callback */
1070 HAL_PWR_PVDCallback();
1071
1072 /* Clear PVD exti pending bit */
1073 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD);
1074 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD);
1075 }
1076
1077 /* Next, successively check PVMx exti flags */
1078 rising_flag = READ_REG(EXTI->RPR2);
1079 falling_flag = READ_REG(EXTI->FPR2);
1080
1081 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVM1) != 0x0U)
1082 {
1083 /* PWR PVM1 interrupt user callback */
1084 HAL_PWREx_PVM1Callback();
1085
1086 /* Clear PVM1 exti pending bit */
1087 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM1);
1088 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM1);
1089 }
1090 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVM2) != 0x0U)
1091 {
1092 /* PWR PVM2 interrupt user callback */
1093 HAL_PWREx_PVM2Callback();
1094
1095 /* Clear PVM2 exti pending bit */
1096 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM2);
1097 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM2);
1098 }
1099 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVM3) != 0x0U)
1100 {
1101 /* PWR PVM3 interrupt user callback */
1102 HAL_PWREx_PVM3Callback();
1103
1104 /* Clear PVM3 exti pending bit */
1105 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM3);
1106 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM3);
1107 }
1108 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVM4) != 0x0U)
1109 {
1110 /* PWR PVM4 interrupt user callback */
1111 HAL_PWREx_PVM4Callback();
1112
1113 /* Clear PVM4 exti pending bit */
1114 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM4);
1115 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM4);
1116 }
1117 }
1118
1119
1120 /**
1121 * @brief PWR PVM1 interrupt callback
1122 * @retval None
1123 */
HAL_PWREx_PVM1Callback(void)1124 __weak void HAL_PWREx_PVM1Callback(void)
1125 {
1126 /* NOTE : This function should not be modified; when the callback is needed,
1127 HAL_PWREx_PVM1Callback() API can be implemented in the user file
1128 */
1129 }
1130
1131 /**
1132 * @brief PWR PVM2 interrupt callback
1133 * @retval None
1134 */
HAL_PWREx_PVM2Callback(void)1135 __weak void HAL_PWREx_PVM2Callback(void)
1136 {
1137 /* NOTE : This function should not be modified; when the callback is needed,
1138 HAL_PWREx_PVM2Callback() API can be implemented in the user file
1139 */
1140 }
1141
1142 /**
1143 * @brief PWR PVM3 interrupt callback
1144 * @retval None
1145 */
HAL_PWREx_PVM3Callback(void)1146 __weak void HAL_PWREx_PVM3Callback(void)
1147 {
1148 /* NOTE : This function should not be modified; when the callback is needed,
1149 HAL_PWREx_PVM3Callback() API can be implemented in the user file
1150 */
1151 }
1152
1153 /**
1154 * @brief PWR PVM4 interrupt callback
1155 * @retval None
1156 */
HAL_PWREx_PVM4Callback(void)1157 __weak void HAL_PWREx_PVM4Callback(void)
1158 {
1159 /* NOTE : This function should not be modified; when the callback is needed,
1160 HAL_PWREx_PVM4Callback() API can be implemented in the user file
1161 */
1162 }
1163
1164 /**
1165 * @brief Enable UCPD configuration memorization in Standby.
1166 * @note This feature is secured by secured UCPD1 when system implements security (TZEN=1).
1167 * @retval None
1168 */
HAL_PWREx_EnableUCPDStandbyMode(void)1169 void HAL_PWREx_EnableUCPDStandbyMode(void)
1170 {
1171 /* Memorize UCPD configuration when entering standby mode */
1172 SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
1173 }
1174
1175 /**
1176 * @brief Disable UCPD configuration memorization in Standby.
1177 * @note This function must be called on exiting the Standby mode and before any UCPD
1178 * configuration update.
1179 * @note This feature is secured by secured UCPD1 when system implements security (TZEN=1).
1180 * @retval None
1181 */
HAL_PWREx_DisableUCPDStandbyMode(void)1182 void HAL_PWREx_DisableUCPDStandbyMode(void)
1183 {
1184 /* Write 0 immediately after Standby exit when using UCPD,
1185 and before writing any UCPD registers */
1186 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
1187 }
1188
1189 /**
1190 * @brief Enable the USB Type-C dead battery pull-down behavior
1191 * on UCPDx_CC1 and UCPDx_CC2 pins
1192 * @note This feature is secured by secured UCPD1 when system implements security (TZEN=1).
1193 * @retval None
1194 */
HAL_PWREx_EnableUCPDDeadBattery(void)1195 void HAL_PWREx_EnableUCPDDeadBattery(void)
1196 {
1197 /* Write 0 to enable the USB Type-C dead battery pull-down behavior */
1198 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
1199 }
1200
1201 /**
1202 * @brief Disable the USB Type-C dead battery pull-down behavior
1203 * on UCPDx_CC1 and UCPDx_CC2 pins
1204 * @note This feature is secured by secured UCPD1 when system implements security (TZEN=1).
1205 * @note After exiting reset, the USB Type-C dead battery behavior will be enabled,
1206 * which may have a pull-down effect on CC1 and CC2 pins.
1207 * It is recommended to disable it in all cases, either to stop this pull-down
1208 * or to hand over control to the UCPD (which should therefore be
1209 * initialized before doing the disable).
1210 * @retval None
1211 */
HAL_PWREx_DisableUCPDDeadBattery(void)1212 void HAL_PWREx_DisableUCPDDeadBattery(void)
1213 {
1214 /* Write 1 to disable the USB Type-C dead battery pull-down behavior */
1215 SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
1216 }
1217
1218 /**
1219 * @brief Enable ultra low power mode.
1220 * Enable ultra low power BORL, BORH and PVD in Standby/Shutdown mode.
1221 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1222 * @retval None
1223 */
HAL_PWREx_EnableUltraLowPowerMode(void)1224 void HAL_PWREx_EnableUltraLowPowerMode(void)
1225 {
1226 /* Enable ultra low power mode */
1227 SET_BIT(PWR->CR3, PWR_CR3_ULPMEN);
1228 }
1229
1230 /**
1231 * @brief Disable ultra low power mode.
1232 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1233 * @retval None
1234 */
HAL_PWREx_DisableUltraLowPowerMode(void)1235 void HAL_PWREx_DisableUltraLowPowerMode(void)
1236 {
1237 /* Disable ultra low power mode */
1238 CLEAR_BIT(PWR->CR3, PWR_CR3_ULPMEN);
1239 }
1240
1241 /**
1242 * @}
1243 */
1244
1245 /** @defgroup PWREx_Exported_Functions_Group2 Extended Power Control SMPS functions
1246 * @brief Extended Power Control SMPS functions
1247 *
1248 @verbatim
1249 ===============================================================================
1250 ##### Extended Power Control SMPS functions #####
1251 ===============================================================================
1252 [..]
1253 This subsection provides a set of functions allowing to control the
1254 SMPS mode.
1255
1256 @endverbatim
1257 * @{
1258 */
1259
1260 /**
1261 * @brief Set SMPS step down converter operating mode.
1262 * @param OperatingMode This parameter can be one of the following values:
1263 * @arg @ref PWR_SMPS_HIGH_POWER SMPS step down converter in high-power mode (default)
1264 * @arg @ref PWR_SMPS_LOW_POWER SMPS step down converter in low-power mode
1265 * @arg @ref PWR_SMPS_BYPASS SMPS step down converter in bypass mode
1266 * @note The High-power mode achieves the high efficiency at high current load.
1267 * @note The Low-power mode achieves the high efficiency at low current load.
1268 * @note The Low-power mode can be enabled only when the main regulator voltage is in range 2 mode.
1269 * When Low-power mode is enabled, the voltage scaling must not be modified. This mode can be
1270 * only selected when power consumption does not exceed 30 mA.
1271 * @note When switching from one power mode to another, HAL_PWREx_SMPS_SetMode() waits for the new
1272 * mode to be effective within a limited time duration before returning the status HAL_OK
1273 * else it returns HAL_TIMEOUT. A request for Low power mode when the voltage regulator is not
1274 * in range 2 is rejected with HAL_ERROR.
1275 * @note The Bypass mode can be enabled or disabled on the fly whatever the selected operation mode.
1276 * @note The function shall not be called in Low-power run mode (meaningless and misleading).
1277 * @retval HAL Status
1278 */
1279
HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode)1280 HAL_StatusTypeDef HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode)
1281 {
1282 HAL_StatusTypeDef status;
1283 uint32_t pwr_sr1;
1284 uint32_t wait_loop_index;
1285
1286 /* Check the parameters */
1287 assert_param(IS_PWR_SMPS_MODE(OperatingMode));
1288
1289 if (OperatingMode == PWR_SMPS_HIGH_POWER)
1290 {
1291 MODIFY_REG(PWR->CR4, (PWR_CR4_SMPSBYP | PWR_CR4_SMPSLPEN), 0U);
1292 }
1293 else if (OperatingMode == PWR_SMPS_LOW_POWER)
1294 {
1295 /* ------------------------------------------------------------------------ */
1296 /* SMPS Low-power mode can only be set in range 2 */
1297 if (HAL_PWREx_GetVoltageRange() != PWR_REGULATOR_VOLTAGE_SCALE2)
1298 {
1299 return HAL_ERROR;
1300 }
1301 else
1302 {
1303 pwr_sr1 = READ_REG(PWR->SR1);
1304
1305 if (READ_BIT(pwr_sr1, PWR_SR1_SMPSHPRDY | PWR_SR1_SMPSBYPRDY) == 0U)
1306 {
1307 /* Already in SMPS Low-power mode */
1308 /* Nothing to configure */
1309 }
1310 else
1311 {
1312 /* Switch to Low-power mode */
1313 MODIFY_REG(PWR->CR4, (PWR_CR4_SMPSBYP | PWR_CR4_SMPSLPEN), PWR_CR4_SMPSLPEN);
1314 }
1315 }
1316 }
1317 else /* PWR_SMPS_BYPASS */
1318 {
1319 HAL_PWREx_SMPS_EnableBypassMode();
1320 }
1321
1322 /* Wait until SMPS step down converter operating mode change */
1323 /* and at least one iteration loop */
1324 wait_loop_index = ((PWR_MODE_CHANGE_DELAY_VALUE * (SystemCoreClock / 100000U)) / 10U) + 1U;
1325
1326 while ((HAL_PWREx_SMPS_GetEffectiveMode() != OperatingMode) && (wait_loop_index != 0U))
1327 {
1328 wait_loop_index--;
1329 }
1330
1331 if (HAL_PWREx_SMPS_GetEffectiveMode() == OperatingMode)
1332 {
1333 status = HAL_OK;
1334 }
1335 else
1336 {
1337 status = HAL_TIMEOUT;
1338 }
1339 return status;
1340 }
1341
1342 /**
1343 * @brief Get SMPS effective step down converter operating mode
1344 * @retval Returned value can be one of the following values:
1345 * @arg @ref PWR_SMPS_HIGH_POWER SMPS step down converter in high-power mode (default)
1346 * @arg @ref PWR_SMPS_LOW_POWER SMPS step down converter in low-power mode
1347 * @arg @ref PWR_SMPS_BYPASS SMPS step down converter in bypass mode
1348 */
HAL_PWREx_SMPS_GetEffectiveMode(void)1349 uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void)
1350 {
1351 uint32_t mode;
1352 uint32_t pwr_sr1;
1353
1354 pwr_sr1 = READ_REG(PWR->SR1);
1355 if (READ_BIT(pwr_sr1, PWR_SR1_SMPSBYPRDY) != 0U)
1356 {
1357 mode = PWR_SMPS_BYPASS;
1358 }
1359 else if (READ_BIT(pwr_sr1, PWR_SR1_SMPSHPRDY) == 0U)
1360 {
1361 mode = PWR_SMPS_LOW_POWER;
1362 }
1363 else
1364 {
1365 mode = PWR_SMPS_HIGH_POWER;
1366 }
1367
1368 return mode;
1369 }
1370
1371 /**
1372 * @brief Enable SMPS step down converter fast start.
1373 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1374 * @retval None
1375 */
HAL_PWREx_SMPS_EnableFastStart(void)1376 void HAL_PWREx_SMPS_EnableFastStart(void)
1377 {
1378 SET_BIT(PWR->CR4, PWR_CR4_SMPSFSTEN);
1379 }
1380
1381 /**
1382 * @brief Disable SMPS step down converter fast start.
1383 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1384 * @retval None
1385 */
HAL_PWREx_SMPS_DisableFastStart(void)1386 void HAL_PWREx_SMPS_DisableFastStart(void)
1387 {
1388 CLEAR_BIT(PWR->CR4, PWR_CR4_SMPSFSTEN);
1389 }
1390
1391 /**
1392 * @brief Disable the SMPS Bypass.
1393 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1394 * @retval None
1395 */
HAL_PWREx_SMPS_DisableBypassMode(void)1396 void HAL_PWREx_SMPS_DisableBypassMode(void)
1397 {
1398 CLEAR_BIT(PWR->CR4, PWR_CR4_SMPSBYP);
1399 }
1400
1401 /**
1402 * @brief Enable the SMPS Bypass.
1403 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1404 * @retval None
1405 */
HAL_PWREx_SMPS_EnableBypassMode(void)1406 void HAL_PWREx_SMPS_EnableBypassMode(void)
1407 {
1408 SET_BIT(PWR->CR4, PWR_CR4_SMPSBYP);
1409 }
1410
1411
1412 /**
1413 * @brief Enable external SMPS when external SMPS switch closed.
1414 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1415 * @retval None
1416 */
HAL_PWREx_SMPS_EnableExternal(void)1417 void HAL_PWREx_SMPS_EnableExternal(void)
1418 {
1419 SET_BIT(PWR->CR4, PWR_CR4_EXTSMPSEN);
1420 }
1421
1422 /**
1423 * @brief Disable external SMPS when external SMPS switch closed.
1424 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1425 * @retval None
1426 */
HAL_PWREx_SMPS_DisableExternal(void)1427 void HAL_PWREx_SMPS_DisableExternal(void)
1428 {
1429 CLEAR_BIT(PWR->CR4, PWR_CR4_EXTSMPSEN);
1430 }
1431
1432 /**
1433 * @brief Get Main Regulator status for use with external SMPS
1434 * @retval Returned value can be one of the following values:
1435 * @arg @ref PWR_MAINREG_READY_FOR_EXTSMPS Main regulator ready for use with external SMPS
1436 * @arg @ref PWR_MAINREG_NOT_READY_FOR_EXTSMPS Main regulator not ready for use with external SMPS
1437 */
HAL_PWREx_SMPS_GetMainRegulatorExtSMPSReadyStatus(void)1438 uint32_t HAL_PWREx_SMPS_GetMainRegulatorExtSMPSReadyStatus(void)
1439 {
1440 uint32_t main_regulator_status;
1441 uint32_t pwr_sr1;
1442
1443 pwr_sr1 = READ_REG(PWR->SR1);
1444 if (READ_BIT(pwr_sr1, PWR_SR1_EXTSMPSRDY) != 0U)
1445 {
1446 main_regulator_status = PWR_MAINREG_READY_FOR_EXTSMPS;
1447 }
1448 else
1449 {
1450 main_regulator_status = PWR_MAINREG_NOT_READY_FOR_EXTSMPS;
1451 }
1452 return main_regulator_status;
1453 }
1454
1455 /**
1456 * @}
1457 */
1458
1459 /**
1460 * @}
1461 */
1462
1463 #endif /* HAL_PWR_MODULE_ENABLED */
1464 /**
1465 * @}
1466 */
1467
1468 /**
1469 * @}
1470 */
1471
1472 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1473
