1 /**
2 ******************************************************************************
3 * @file stm32l5xx_hal_icache.c
4 * @author MCD Application Team
5 * @brief ICACHE HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Instruction Cache (ICACHE).
8 * + Initialization and Configuration
9 * + Invalidate functions
10 * + Monitoring management
11 * + Memory address remap management
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### ICACHE main features #####
26 ==============================================================================
27 [..]
28 The Instruction Cache (ICACHE) is introduced on C-AHB code bus of
29 Cortex-M33 processor to improve performance when fetching instruction
30 and data from both internal and external memories. It allows close to
31 zero wait states performance.
32
33 (+) The ICACHE provides two performance counters (Hit and Miss),
34 cache invalidate maintenance operation, error management and TrustZone
35 security support.
36
37 (+) The ICACHE provides additionally the possibility to remap input address
38 falling into up to four memory regions (used to remap aliased code in
39 external memories to the internal Code region, for execution)
40
41 ===============================================================================
42 ##### How to use this driver #####
43 ===============================================================================
44 [..]
45 The ICACHE HAL driver can be used as follows:
46
47 (#) Optionally configure the Instruction Cache mode with
48 @ref HAL_ICACHE_ConfigAssociativityMode() if the default configuration
49 does not suit the application requirements.
50
51 (#) Enable and disable the Instruction Cache with respectively
52 @ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable().
53 Use @ref HAL_ICACHE_IsEnabled() to get the Instruction Cache status.
54
55 (#) Initiate the cache maintenance invalidation procedure with either
56 @ref HAL_ICACHE_Invalidate() (blocking mode) or @ref HAL_ICACHE_Invalidate_IT()
57 (interrupt mode). When interrupt mode is used, the callback function
58 @ref HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate
59 procedure is complete. The function @ref HAL_ICACHE_WaitForInvalidateComplete()
60 may be called to wait for the end of the invalidate procedure automatically
61 initiated when disabling the Instruction Cache with @ref HAL_ICACHE_Disable().
62 The cache operation is bypassed during the invalidation procedure.
63
64 (#) Use the performance monitoring counters for Hit and Miss with the following
65 functions: @ref HAL_ICACHE_Monitor_Start(), @ref HAL_ICACHE_Monitor_Stop(),
66 @ref HAL_ICACHE_Monitor_Reset(), @ref HAL_ICACHE_Monitor_GetHitValue() and
67 @ref HAL_ICACHE_Monitor_GetMissValue()
68
69 (#) Enable and disable up to four regions to remap input address from external
70 memories to the internal Code region for execution with
71 @ref HAL_ICACHE_EnableRemapRegion() and @ref HAL_ICACHE_DisableRemapRegion()
72
73 @endverbatim
74 */
75
76 /* Includes ------------------------------------------------------------------*/
77 #include "stm32l5xx_hal.h"
78
79 /** @addtogroup STM32L5xx_HAL_Driver
80 * @{
81 */
82
83 /** @defgroup ICACHE ICACHE
84 * @brief HAL ICACHE module driver
85 * @{
86 */
87 #ifdef HAL_ICACHE_MODULE_ENABLED
88
89 /* Private typedef -----------------------------------------------------------*/
90 /* Private constants ---------------------------------------------------------*/
91 /** @addtogroup ICACHE_Private_Constants ICACHE Private Constants
92 * @{
93 */
94 #define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */
95 #define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */
96
97 /**
98 * @}
99 */
100
101 /* Private macros ------------------------------------------------------------*/
102 /** @defgroup ICACHE_Private_Macros ICACHE Private Macros
103 * @{
104 */
105
106 #define IS_ICACHE_ASSOCIATIVITY_MODE(__MODE__) (((__MODE__) == ICACHE_1WAY) || \
107 ((__MODE__) == ICACHE_2WAYS))
108
109 #define IS_ICACHE_MONITOR_TYPE(__TYPE__) (((__TYPE__) == ICACHE_MONITOR_HIT_MISS) || \
110 ((__TYPE__) == ICACHE_MONITOR_HIT) || \
111 ((__TYPE__) == ICACHE_MONITOR_MISS))
112
113 #define IS_ICACHE_REGION_NUMBER(__NUMBER__) ((__NUMBER__) < 4U)
114
115 #define IS_ICACHE_REGION_SIZE(__SIZE__) (((__SIZE__) == ICACHE_REGIONSIZE_2MB) || \
116 ((__SIZE__) == ICACHE_REGIONSIZE_4MB) || \
117 ((__SIZE__) == ICACHE_REGIONSIZE_8MB) || \
118 ((__SIZE__) == ICACHE_REGIONSIZE_16MB) || \
119 ((__SIZE__) == ICACHE_REGIONSIZE_32MB) || \
120 ((__SIZE__) == ICACHE_REGIONSIZE_64MB) || \
121 ((__SIZE__) == ICACHE_REGIONSIZE_128MB))
122
123 #define IS_ICACHE_REGION_TRAFFIC_ROUTE(__TRAFFICROUTE__) (((__TRAFFICROUTE__) == ICACHE_MASTER1_PORT) || \
124 ((__TRAFFICROUTE__) == ICACHE_MASTER2_PORT))
125
126 #define IS_ICACHE_REGION_OUTPUT_BURST_TYPE(__OUTPUTBURSTTYPE_) (((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_WRAP) || \
127 ((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_INCR))
128
129 /**
130 * @}
131 */
132
133 /* Private variables ---------------------------------------------------------*/
134 /* Private function prototypes -----------------------------------------------*/
135
136 /* Exported functions --------------------------------------------------------*/
137
138 /** @defgroup ICACHE_Exported_Functions ICACHE Exported Functions
139 * @{
140 */
141
142 /** @defgroup ICACHE_Exported_Functions_Group1 Initialization and control functions
143 * @brief Initialization and control functions
144 *
145 @verbatim
146 ==============================================================================
147 ##### Initialization and control functions #####
148 ==============================================================================
149 [..]
150 This section provides functions allowing to initialize and control the
151 Instruction Cache (mode, invalidate procedure, performance counters).
152 @endverbatim
153 * @{
154 */
155
156 /**
157 * @brief Configure the Instruction Cache cache associativity mode selection.
158 * @param AssociativityMode Associativity mode selection
159 * This parameter can be one of the following values:
160 * @arg ICACHE_1WAY 1-way cache (direct mapped cache)
161 * @arg ICACHE_2WAYS 2-ways set associative cache (default)
162 * @retval HAL status (HAL_OK/HAL_ERROR)
163 */
HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode)164 HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode)
165 {
166 HAL_StatusTypeDef status = HAL_OK;
167
168 /* Check the parameters */
169 assert_param(IS_ICACHE_ASSOCIATIVITY_MODE(AssociativityMode));
170
171 /* Check cache is not enabled */
172 if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
173 {
174 status = HAL_ERROR;
175 }
176 else
177 {
178 MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode);
179 }
180
181 return status;
182 }
183
184 /**
185 * @brief DeInitialize the Instruction Cache.
186 * @retval HAL status (HAL_OK/HAL_TIMEOUT)
187 */
HAL_ICACHE_DeInit(void)188 HAL_StatusTypeDef HAL_ICACHE_DeInit(void)
189 {
190 HAL_StatusTypeDef status;
191
192 /* Disable cache with reset value for 2-ways set associative mode */
193 WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL);
194
195 /* Stop monitor and reset monitor values */
196 (void)HAL_ICACHE_Monitor_Stop(ICACHE_MONITOR_HIT_MISS);
197 (void)HAL_ICACHE_Monitor_Reset(ICACHE_MONITOR_HIT_MISS);
198
199 /* No remapped regions */
200 (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_0);
201 (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_1);
202 (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_2);
203 (void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_3);
204
205 /* Wait for end of invalidate cache procedure */
206 status = HAL_ICACHE_WaitForInvalidateComplete();
207
208 /* Clear any pending flags */
209 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF);
210
211 return status;
212 }
213
214 /**
215 * @brief Enable the Instruction Cache.
216 * @note This function always returns HAL_OK even if there is any ongoing
217 * cache operation. The Instruction Cache is bypassed until the
218 * cache operation completes.
219 * @retval HAL status (HAL_OK)
220 */
HAL_ICACHE_Enable(void)221 HAL_StatusTypeDef HAL_ICACHE_Enable(void)
222 {
223 SET_BIT(ICACHE->CR, ICACHE_CR_EN);
224
225 return HAL_OK;
226 }
227
228 /**
229 * @brief Disable the Instruction Cache.
230 * @note This function waits for the cache being disabled but
231 * not for the end of the automatic cache invalidation procedure.
232 * @retval HAL status (HAL_OK/HAL_TIMEOUT)
233 */
HAL_ICACHE_Disable(void)234 HAL_StatusTypeDef HAL_ICACHE_Disable(void)
235 {
236 HAL_StatusTypeDef status = HAL_OK;
237 uint32_t tickstart;
238
239 /* Make sure BSYENDF is reset before to disable the instruction cache */
240 /* as it automatically starts a cache invalidation procedure */
241 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
242
243 CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
244
245 /* Get tick */
246 tickstart = HAL_GetTick();
247
248 /* Wait for instruction cache being disabled */
249 while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
250 {
251 if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE)
252 {
253 /* New check to avoid false timeout detection in case of preemption */
254 if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
255 {
256 status = HAL_TIMEOUT;
257 break;
258 }
259 }
260 }
261
262 return status;
263 }
264
265 /**
266 * @brief Check whether the Instruction Cache is enabled or not.
267 * @retval Status (0: disabled, 1: enabled)
268 */
HAL_ICACHE_IsEnabled(void)269 uint32_t HAL_ICACHE_IsEnabled(void)
270 {
271 return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL);
272 }
273
274 /**
275 * @brief Invalidate the Instruction Cache.
276 * @note This function waits for the end of cache invalidation procedure
277 * and clears the associated BSYENDF flag.
278 * @retval HAL status (HAL_OK/HAL_ERROR/HAL_TIMEOUT)
279 */
HAL_ICACHE_Invalidate(void)280 HAL_StatusTypeDef HAL_ICACHE_Invalidate(void)
281 {
282 HAL_StatusTypeDef status;
283
284 /* Check no ongoing operation */
285 if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
286 {
287 status = HAL_ERROR;
288 }
289 else
290 {
291 /* Make sure BSYENDF is reset before to start cache invalidation */
292 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
293
294 /* Launch cache invalidation */
295 SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
296
297 status = HAL_ICACHE_WaitForInvalidateComplete();
298 }
299
300 return status;
301 }
302
303 /**
304 * @brief Invalidate the Instruction Cache with interrupt.
305 * @note This function launches cache invalidation and returns.
306 * User application shall resort to interrupt generation to check
307 * the end of the cache invalidation with the BSYENDF flag and the
308 * HAL_ICACHE_InvalidateCompleteCallback() callback.
309 * @retval HAL status (HAL_OK/HAL_ERROR)
310 */
HAL_ICACHE_Invalidate_IT(void)311 HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void)
312 {
313 HAL_StatusTypeDef status = HAL_OK;
314
315 /* Check no ongoing operation */
316 if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
317 {
318 status = HAL_ERROR;
319 }
320 else
321 {
322 /* Make sure BSYENDF is reset before to start cache invalidation */
323 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
324
325 /* Enable end of cache invalidation interrupt */
326 SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
327
328 /* Launch cache invalidation */
329 SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
330 }
331
332 return status;
333 }
334
335 /**
336 * @brief Wait for the end of the Instruction Cache invalidate procedure.
337 * @note This function checks and clears the BSYENDF flag when set.
338 * @retval HAL status (HAL_OK/HAL_TIMEOUT)
339 */
HAL_ICACHE_WaitForInvalidateComplete(void)340 HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void)
341 {
342 HAL_StatusTypeDef status = HAL_OK;
343 uint32_t tickstart;
344
345 /* Check if ongoing invalidation operation */
346 if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
347 {
348 /* Get tick */
349 tickstart = HAL_GetTick();
350
351 /* Wait for end of cache invalidation */
352 while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
353 {
354 if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE)
355 {
356 /* New check to avoid false timeout detection in case of preemption */
357 if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
358 {
359 status = HAL_TIMEOUT;
360 break;
361 }
362 }
363 }
364 }
365
366 /* Clear BSYENDF */
367 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
368
369 return status;
370 }
371
372
373 /**
374 * @brief Start the Instruction Cache performance monitoring.
375 * @param MonitorType Monitoring type
376 * This parameter can be one of the following values:
377 * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
378 * @arg ICACHE_MONITOR_HIT Hit monitoring
379 * @arg ICACHE_MONITOR_MISS Miss monitoring
380 * @retval HAL status (HAL_OK)
381 */
HAL_ICACHE_Monitor_Start(uint32_t MonitorType)382 HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType)
383 {
384 /* Check the parameters */
385 assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
386
387 SET_BIT(ICACHE->CR, MonitorType);
388
389 return HAL_OK;
390 }
391
392 /**
393 * @brief Stop the Instruction Cache performance monitoring.
394 * @note Stopping the monitoring does not reset the values.
395 * @param MonitorType Monitoring type
396 * This parameter can be one of the following values:
397 * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
398 * @arg ICACHE_MONITOR_HIT Hit monitoring
399 * @arg ICACHE_MONITOR_MISS Miss monitoring
400 * @retval HAL status (HAL_OK)
401 */
HAL_ICACHE_Monitor_Stop(uint32_t MonitorType)402 HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType)
403 {
404 /* Check the parameters */
405 assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
406
407 CLEAR_BIT(ICACHE->CR, MonitorType);
408
409 return HAL_OK;
410 }
411
412 /**
413 * @brief Reset the Instruction Cache performance monitoring values.
414 * @param MonitorType Monitoring type
415 * This parameter can be one of the following values:
416 * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
417 * @arg ICACHE_MONITOR_HIT Hit monitoring
418 * @arg ICACHE_MONITOR_MISS Miss monitoring
419 * @retval HAL status (HAL_OK)
420 */
HAL_ICACHE_Monitor_Reset(uint32_t MonitorType)421 HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType)
422 {
423 /* Check the parameters */
424 assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
425
426 /* Force/Release reset */
427 SET_BIT(ICACHE->CR, (MonitorType << 2U));
428 CLEAR_BIT(ICACHE->CR, (MonitorType << 2U));
429
430 return HAL_OK;
431 }
432
433 /**
434 * @brief Get the Instruction Cache performance Hit monitoring value.
435 * @note Upon reaching the 32-bit maximum value, monitor does not wrap.
436 * @retval Hit monitoring value
437 */
HAL_ICACHE_Monitor_GetHitValue(void)438 uint32_t HAL_ICACHE_Monitor_GetHitValue(void)
439 {
440 return (ICACHE->HMONR);
441 }
442
443 /**
444 * @brief Get the Instruction Cache performance Miss monitoring value.
445 * @note Upon reaching the 32-bit maximum value, monitor does not wrap.
446 * @retval Miss monitoring value
447 */
HAL_ICACHE_Monitor_GetMissValue(void)448 uint32_t HAL_ICACHE_Monitor_GetMissValue(void)
449 {
450 return (ICACHE->MMONR);
451 }
452
453 /**
454 * @}
455 */
456
457 /** @defgroup ICACHE_Exported_Functions_Group2 IRQ and callback functions
458 * @brief IRQ and callback functions
459 *
460 @verbatim
461 ==============================================================================
462 ##### IRQ and callback functions #####
463 ==============================================================================
464 [..]
465 This section provides functions allowing to handle ICACHE global interrupt
466 and the associated callback functions.
467 @endverbatim
468 * @{
469 */
470
471 /**
472 * @brief Handle the Instruction Cache interrupt request.
473 * @note This function should be called under the ICACHE_IRQHandler().
474 * @note This function respectively disables the interrupt and clears the
475 * flag of any pending flag before calling the associated user callback.
476 * @retval None
477 */
HAL_ICACHE_IRQHandler(void)478 void HAL_ICACHE_IRQHandler(void)
479 {
480 /* Get current interrupt flags and interrupt sources value */
481 uint32_t itflags = READ_REG(ICACHE->SR);
482 uint32_t itsources = READ_REG(ICACHE->IER);
483
484 /* Check Instruction cache Error interrupt flag */
485 if (((itflags & itsources) & ICACHE_FLAG_ERROR) != 0U)
486 {
487 /* Disable error interrupt */
488 CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
489
490 /* Clear ERR pending flag */
491 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
492
493 /* Instruction cache error interrupt user callback */
494 HAL_ICACHE_ErrorCallback();
495 }
496
497 /* Check Instruction cache BusyEnd interrupt flag */
498 if (((itflags & itsources) & ICACHE_FLAG_BUSYEND) != 0U)
499 {
500 /* Disable end of cache invalidation interrupt */
501 CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
502
503 /* Clear BSYENDF pending flag */
504 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
505
506 /* Instruction cache busyend interrupt user callback */
507 HAL_ICACHE_InvalidateCompleteCallback();
508 }
509 }
510
511 /**
512 * @brief Cache invalidation complete callback.
513 */
HAL_ICACHE_InvalidateCompleteCallback(void)514 __weak void HAL_ICACHE_InvalidateCompleteCallback(void)
515 {
516 /* NOTE : This function should not be modified, when the callback is needed,
517 the HAL_ICACHE_InvalidateCompleteCallback() should be implemented in the user file
518 */
519 }
520
521 /**
522 * @brief Error callback.
523 */
HAL_ICACHE_ErrorCallback(void)524 __weak void HAL_ICACHE_ErrorCallback(void)
525 {
526 /* NOTE : This function should not be modified, when the callback is needed,
527 the HAL_ICACHE_ErrorCallback() should be implemented in the user file
528 */
529 }
530
531 /**
532 * @}
533 */
534
535 /** @defgroup ICACHE_Exported_Functions_Group3 Memory remapped regions functions
536 * @brief Memory remapped regions functions
537 *
538 @verbatim
539 ==============================================================================
540 ##### Memory remapped regions functions #####
541 ==============================================================================
542 [..]
543 This section provides functions allowing to manage the remapping of
544 external memories to internal Code for execution.
545 @endverbatim
546 * @{
547 */
548
549 /**
550 * @brief Configure and enable a region for memory remapping.
551 * @note The Instruction Cache and the region must be disabled.
552 * @param Region Region number
553 This parameter can be a value of @arg @ref ICACHE_Region
554 * @param pRegionConfig Pointer to structure of ICACHE region configuration parameters
555 * @retval HAL status (HAL_OK/HAL_ERROR)
556 */
HAL_ICACHE_EnableRemapRegion(uint32_t Region,const ICACHE_RegionConfigTypeDef * const pRegionConfig)557 HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig)
558 {
559 HAL_StatusTypeDef status = HAL_OK;
560 __IO uint32_t *p_reg;
561 uint32_t value;
562
563 /* Check the parameters */
564 assert_param(IS_ICACHE_REGION_NUMBER(Region));
565 assert_param(IS_ICACHE_REGION_SIZE(pRegionConfig->Size));
566 assert_param(IS_ICACHE_REGION_TRAFFIC_ROUTE(pRegionConfig->TrafficRoute));
567 assert_param(IS_ICACHE_REGION_OUTPUT_BURST_TYPE(pRegionConfig->OutputBurstType));
568
569 /* Check cache is not enabled */
570 if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
571 {
572 status = HAL_ERROR;
573 }
574 else
575 {
576 /* Get region control register address */
577 p_reg = &(ICACHE->CRR0) + (1U * Region);
578
579 /* Check region is not already enabled */
580 if ((*p_reg & ICACHE_CRRx_REN) != 0U)
581 {
582 status = HAL_ERROR;
583 }
584 else
585 {
586 /* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */
587 /* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */
588 /* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */
589 /* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */
590 /* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */
591 /* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */
592 /* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */
593 value = ((pRegionConfig->BaseAddress & 0x1FFFFFFFU) >> 21U) & \
594 (0xFFU & ~(pRegionConfig->Size - 1U));
595 value |= ((pRegionConfig->RemapAddress >> 5U) & \
596 ((uint32_t)(0x7FFU & ~(pRegionConfig->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos));
597 value |= (pRegionConfig->Size << ICACHE_CRRx_RSIZE_Pos) | pRegionConfig->TrafficRoute | \
598 pRegionConfig->OutputBurstType;
599 *p_reg = (value | ICACHE_CRRx_REN);
600 }
601 }
602
603 return status;
604 }
605
606 /**
607 * @brief Disable the memory remapping for a predefined region.
608 * @param Region Region number
609 This parameter can be a value of @arg @ref ICACHE_Region
610 * @retval HAL status (HAL_OK/HAL_ERROR)
611 */
HAL_ICACHE_DisableRemapRegion(uint32_t Region)612 HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region)
613 {
614 HAL_StatusTypeDef status = HAL_OK;
615 __IO uint32_t *p_reg;
616
617 /* Check the parameters */
618 assert_param(IS_ICACHE_REGION_NUMBER(Region));
619
620 /* Check cache is not enabled */
621 if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
622 {
623 status = HAL_ERROR;
624 }
625 else
626 {
627 /* Get region control register address */
628 p_reg = &(ICACHE->CRR0) + (1U * Region);
629
630 *p_reg &= ~ICACHE_CRRx_REN;
631 }
632
633 return status;
634 }
635
636
637 /**
638 * @}
639 */
640
641 /**
642 * @}
643 */
644
645 #endif /* HAL_ICACHE_MODULE_ENABLED */
646
647 /**
648 * @}
649 */
650
651 /**
652 * @}
653 */
654
