1 /**
2 ******************************************************************************
3 * @file stm32l5xx_hal_gtzc.c
4 * @author MCD Application Team
5 * @brief GTZC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of GTZC peripheral:
8 * + TZSC Initialization and Configuration functions
9 * + TZSC-MPCWM Initialization and Configuration functions
10 * + MPCBB Initialization and Configuration functions
11 * + TZSC, TZSC-MPCWM and MPCBB Lock functions
12 * + TZIC Initialization and Configuration functions
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2019 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### GTZC main features #####
28 ==============================================================================
29 [..]
30 (+) Global TrustZone Controller (GTZC) composed of three sub-blocks:
31 (++) TZSC: TrustZone security controller
32 This sub-block defines the secure/privileged state of master and slave
33 peripherals. It also controls the secure state of subregions
34 for the watermark memory peripheral controller (MPCWM).
35 (++) MPCBB: Block-Based memory protection controller
36 This sub-block defines the secure state of all blocks
37 (256-byte pages) of the associated SRAM.
38 (++) TZIC: TrustZone illegal access controller
39 This sub-block gathers all illegal access events in the system and
40 generates a secure interrupt towards NVIC.
41
42 (+) These sub-blocks are used to configure TrustZone system security in
43 a product having bus agents with programmable-security and privileged
44 attributes (securable) such as:
45 (++) on-chip RAM with programmable secure blocks (pages)
46 (++) AHB and APB peripherals with programmable security and/or privilege access
47 (++) AHB master granted as secure and/or privilege
48 (++) off-chip memories with secure areas
49
50 [..]
51 (+) TZIC accessible only with secure privileged transactions.
52 (+) Secure and non-secure access supported for privileged and unprivileged
53 part of TZSC and MPCBB
54
55 ==============================================================================
56 ##### How to use this driver #####
57 ==============================================================================
58 [..]
59 The GTZC HAL driver can be used as follows:
60
61 (#) Configure or get back securable peripherals attributes using
62 HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes()
63
64 (#) Configure or get back MPCWM memories attributes using
65 HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() / HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes()
66
67 (#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() /
68 HAL_GTZC_TZSC_GetLock()
69
70 (#) Configure or get back MPCBB memories complete configuration using
71 HAL_GTZC_MPCBB_ConfigMem() / HAL_GTZC_MPCBB_GetConfigMem()
72
73 (#) Configure or get back MPCBB memories attributes using
74 HAL_GTZC_MPCBB_ConfigMemAttributes() / HAL_GTZC_MPCBB_GetConfigMemAttributes()
75
76 (#) Lock MPCBB configuration or get lock status using HAL_GTZC_MPCBB_Lock() /
77 HAL_GTZC_MPCBB_GetLock()
78
79 (#) Lock MPCBB super-blocks or get lock status using HAL_GTZC_MPCBB_LockConfig() /
80 HAL_GTZC_MPCBB_GetLockConfig()
81
82 (#) Illegal access detection can be configured through TZIC sub-block using
83 following functions: HAL_GTZC_TZIC_DisableIT() / HAL_GTZC_TZIC_EnableIT()
84
85 (#) Illegal access flags can be retrieved through HAL_GTZC_TZIC_GetFlag() and
86 HAL_GTZC_TZIC_ClearFlag() functions
87
88 (#) Illegal access interrupt service routines are served by HAL_GTZC_IRQHandler()
89 and user can add his own code using HAL_GTZC_TZIC_Callback()
90
91 @endverbatim
92 ******************************************************************************
93 */
94
95 /* Includes ------------------------------------------------------------------*/
96 #include "stm32l5xx_hal.h"
97
98 /** @addtogroup STM32L5xx_HAL_Driver
99 * @{
100 */
101
102 /** @defgroup GTZC GTZC
103 * @brief GTZC HAL module driver
104 * @{
105 */
106
107 #ifdef HAL_GTZC_MODULE_ENABLED
108
109 /* Private typedef -----------------------------------------------------------*/
110 /* Private constants ---------------------------------------------------------*/
111
112 /** @defgroup GTZC_Private_Constants GTZC Private Constants
113 * @{
114 */
115
116 /* Definitions for GTZC_TZSC_MPCWM */
117 #define GTZC_TZSC_MPCWM1_MEM_SIZE 0x10000000U /* 256MB max size */
118 #define GTZC_TZSC_MPCWM2_MEM_SIZE 0x10000000U /* 256MB max size */
119 #define GTZC_TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */
120
121 /* Definitions for GTZC TZSC & TZIC ALL register values */
122 #define TZSC_SECCFGR1_ALL (0xFFFFFFFFUL)
123 #if defined (STM32L562xx)
124 #define TZSC_SECCFGR2_ALL (0x0007FFFFUL)
125 #else
126 #define TZSC_SECCFGR2_ALL (0x00076FFFUL)
127 #endif /* STM32L562xx */
128 #define TZSC_PRIVCFGR1_ALL (0xFFFFFFFFUL)
129 #if defined (STM32L562xx)
130 #define TZSC_PRIVCFGR2_ALL (0x0007FFFFUL)
131 #else
132 #define TZSC_PRIVCFGR2_ALL (0x00076FFFUL)
133 #endif /* STM32L562xx */
134 #define TZIC_IER1_ALL (0xFFFFFFFFUL)
135 #if defined (STM32L562xx)
136 #define TZIC_IER2_ALL (0x3FFFFFFFUL)
137 #else
138 #define TZIC_IER2_ALL (0x3FFF6FFFUL)
139 #endif /* STM32L562xx */
140 #define TZIC_IER3_ALL (0x000000FFUL)
141 #define TZIC_FCR1_ALL (0xFFFFFFFFUL)
142 #if defined (STM32L562xx)
143 #define TZIC_FCR2_ALL (0x3FFFFFFFUL)
144 #else
145 #define TZIC_FCR2_ALL (0x3FFF6FFFUL)
146 #endif /* STM32L562xx */
147 #define TZIC_FCR3_ALL (0x000000FFUL)
148
149 /**
150 * @}
151 */
152
153 /* Private macros ------------------------------------------------------------*/
154
155 /** @defgroup GTZC_Private_Macros GTZC Private Macros
156 * @{
157 */
158
159 #define IS_ADDRESS_IN(mem, address)\
160 ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
161 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \
162 || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
163 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) )
164
165 #define IS_ADDRESS_IN_S(mem, address)\
166 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
167 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
168
169 #define IS_ADDRESS_IN_NS(mem, address)\
170 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
171 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
172
173 #define GTZC_BASE_ADDRESS(mem)\
174 ( mem ## _BASE )
175
176 /**
177 * @}
178 */
179
180 /* Private variables ---------------------------------------------------------*/
181 /* Private function prototypes -----------------------------------------------*/
182 /* Exported functions --------------------------------------------------------*/
183
184 /** @defgroup GTZC_Exported_Functions GTZC Exported Functions
185 * @{
186 */
187
188 /** @defgroup GTZC_Exported_Functions_Group1 TZSC Configuration functions
189 * @brief TZSC Configuration functions
190 *
191 @verbatim
192 ==============================================================================
193 ##### TZSC Configuration functions #####
194 ==============================================================================
195 [..]
196 This section provides functions allowing to configure TZSC
197 TZSC is TrustZone Security Controller
198 @endverbatim
199 * @{
200 */
201
202 /**
203 * @brief Configure TZSC on a single peripheral or on all peripherals.
204 * @note Secure and non-secure attributes can only be set from the secure
205 * state when the system implements the security (TZEN=1).
206 * @note Privilege and non-privilege attributes can only be set from the
207 * privilege state when TZEN=0 or TZEN=1
208 * @note Security and privilege attributes can be set independently.
209 * @note Default state is non-secure and unprivileged access allowed.
210 * @param PeriphId Peripheral identifier
211 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
212 * Use GTZC_PERIPH_ALL to select all peripherals.
213 * @param PeriphAttributes Peripheral attributes, see @ref GTZC_TZSC_PeriphAttributes.
214 * @retval HAL status.
215 */
HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,uint32_t PeriphAttributes)216 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
217 uint32_t PeriphAttributes)
218 {
219 uint32_t register_address;
220
221 /* check entry parameters */
222 if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV))
223 || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
224 || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
225 {
226 return HAL_ERROR;
227 }
228
229 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
230 {
231 /* special case where same attributes are applied to all peripherals */
232
233 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
234 /* secure configuration */
235 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
236 {
237 SET_BIT(GTZC_TZSC->SECCFGR1, TZSC_SECCFGR1_ALL);
238 SET_BIT(GTZC_TZSC->SECCFGR2, TZSC_SECCFGR2_ALL);
239 }
240 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
241 {
242 CLEAR_BIT(GTZC_TZSC->SECCFGR1, TZSC_SECCFGR1_ALL);
243 CLEAR_BIT(GTZC_TZSC->SECCFGR2, TZSC_SECCFGR2_ALL);
244 }
245 else
246 {
247 /* do nothing */
248 }
249 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
250
251 /* privilege configuration */
252 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
253 {
254 SET_BIT(GTZC_TZSC->PRIVCFGR1, TZSC_PRIVCFGR1_ALL);
255 SET_BIT(GTZC_TZSC->PRIVCFGR2, TZSC_PRIVCFGR2_ALL);
256 }
257 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
258 {
259 CLEAR_BIT(GTZC_TZSC->PRIVCFGR1, TZSC_PRIVCFGR1_ALL);
260 CLEAR_BIT(GTZC_TZSC->PRIVCFGR2, TZSC_PRIVCFGR2_ALL);
261 }
262 else
263 {
264 /* do nothing */
265 }
266 }
267 else
268 {
269 /* common case where only one peripheral is configured */
270
271 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
272 /* secure configuration */
273 register_address = (uint32_t) &(GTZC_TZSC->SECCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
274 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
275 {
276 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
277 }
278 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
279 {
280 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
281 }
282 else
283 {
284 /* do nothing */
285 }
286 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
287
288 /* privilege configuration */
289 register_address = (uint32_t) &(GTZC_TZSC->PRIVCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
290 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
291 {
292 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
293 }
294 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
295 {
296 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
297 }
298 else
299 {
300 /* do nothing */
301 }
302 }
303 return HAL_OK;
304 }
305
306 /**
307 * @brief Get TZSC configuration on a single peripheral or on all peripherals.
308 * @param PeriphId Peripheral identifier.
309 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
310 * Use GTZC_PERIPH_ALL to select all peripherals.
311 * @param PeriphAttributes Peripheral attribute pointer.
312 * This parameter can be a value of @ref GTZC_TZSC_PeriphAttributes.
313 * If PeriphId target a single peripheral, pointer on a single element.
314 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array of
315 * GTZC_TZSC_PERIPH_NUMBER elements is to be provided.
316 * @retval HAL status.
317 */
HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,uint32_t * PeriphAttributes)318 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
319 uint32_t *PeriphAttributes)
320 {
321 uint32_t i;
322 uint32_t reg_value;
323 uint32_t register_address;
324
325 /* check entry parameters */
326 if ((PeriphAttributes == NULL)
327 || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
328 || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
329 {
330 return HAL_ERROR;
331 }
332
333 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
334 {
335 /* get secure configuration: read each register and deploy each bit value
336 * of corresponding index in the destination array
337 */
338 reg_value = READ_REG(GTZC_TZSC->SECCFGR1);
339 for (i = 0U; i < 32U; i++)
340 {
341 if (((reg_value & (1UL << i)) >> i) != 0U)
342 {
343 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
344 }
345 else
346 {
347 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
348 }
349 }
350
351 reg_value = READ_REG(GTZC_TZSC->SECCFGR2);
352 for (/*i = 32U*/; i < GTZC_TZSC_PERIPH_NUMBER; i++)
353 {
354 if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
355 {
356 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
357 }
358 else
359 {
360 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
361 }
362 }
363
364 /* get privilege configuration: read each register and deploy each bit value
365 * of corresponding index in the destination array
366 */
367 reg_value = READ_REG(GTZC_TZSC->PRIVCFGR1);
368 for (i = 0U; i < 32U; i++)
369 {
370 if (((reg_value & (1UL << i)) >> i) != 0U)
371 {
372 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
373 }
374 else
375 {
376 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
377 }
378 }
379
380 reg_value = READ_REG(GTZC_TZSC->PRIVCFGR2);
381 for (/*i = 32U*/; i < GTZC_TZSC_PERIPH_NUMBER; i++)
382 {
383 if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
384 {
385 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
386 }
387 else
388 {
389 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
390 }
391 }
392
393 }
394 else
395 {
396 /* common case where only one peripheral is configured */
397
398 /* secure configuration */
399 register_address = (uint32_t) &(GTZC_TZSC->SECCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
400
401 if (((READ_BIT(*(__IO uint32_t *)register_address,
402 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
403 != 0U)
404 {
405 *PeriphAttributes = GTZC_TZSC_PERIPH_SEC;
406 }
407 else
408 {
409 *PeriphAttributes = GTZC_TZSC_PERIPH_NSEC;
410 }
411
412 /* privilege configuration */
413 register_address = (uint32_t) &(GTZC_TZSC->PRIVCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
414
415 if (((READ_BIT(*(__IO uint32_t *)register_address,
416 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
417 != 0U)
418 {
419 *PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV;
420 }
421 else
422 {
423 *PeriphAttributes |= GTZC_TZSC_PERIPH_NPRIV;
424 }
425 }
426 return HAL_OK;
427 }
428
429 /**
430 * @}
431 */
432
433 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
434
435 /** @defgroup GTZC_Exported_Functions_Group2 MPCWM Configuration functions
436 * @brief MPCWM Configuration functions
437 *
438 @verbatim
439 ==============================================================================
440 ##### MPCWM Configuration functions #####
441 ==============================================================================
442 [..]
443 This section provides functions allowing to configure MPCWM
444 MPCWM is Memory Protection Controller WaterMark
445 @endverbatim
446 * @{
447 */
448
449 /**
450 * @brief Configure a TZSC-MPCWM area.
451 * @param MemBaseAddress WM identifier.
452 * @param pMPCWM_Desc TZSC-MPCWM descriptor pointer.
453 * The structure description is available in @ref GTZC_Exported_Types.
454 * @retval HAL status.
455 */
HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,const MPCWM_ConfigTypeDef * pMPCWM_Desc)456 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
457 const MPCWM_ConfigTypeDef *pMPCWM_Desc)
458 {
459 uint32_t register_address;
460 uint32_t reg_value;
461 uint32_t size;
462 uint32_t start_pos, start_msk;
463 uint32_t length_pos, length_msk;
464
465 /* check entry parameters */
466 if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2)
467 || ((MemBaseAddress == FMC_BANK3) && (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2))
468 || ((pMPCWM_Desc->Offset % GTZC_TZSC_MPCWM_GRANULARITY) != 0U)
469 || ((pMPCWM_Desc->Length % GTZC_TZSC_MPCWM_GRANULARITY) != 0U))
470 {
471 return HAL_ERROR;
472 }
473
474 /* check descriptor content vs. memory capacity */
475 switch (MemBaseAddress)
476 {
477 case OCTOSPI1_BASE:
478 size = GTZC_TZSC_MPCWM1_MEM_SIZE;
479 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
480 {
481 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR1);
482 start_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Pos;
483 start_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Msk;
484 length_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Pos;
485 length_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Msk;
486 }
487 else
488 {
489 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
490 * (Parameter already checked)
491 */
492 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR2);
493 start_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Pos;
494 start_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Msk;
495 length_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Pos;
496 length_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Msk;
497 }
498 break;
499 case FMC_BANK1:
500 size = GTZC_TZSC_MPCWM1_MEM_SIZE;
501 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
502 {
503 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR1);
504 start_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Pos;
505 start_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Msk;
506 length_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Pos;
507 length_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Msk;
508 }
509 else
510 {
511 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
512 * (Parameter already checked)
513 */
514 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR2);
515 start_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Pos;
516 start_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Msk;
517 length_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Pos;
518 length_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Msk;
519 }
520 break;
521 case FMC_BANK3:
522 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
523 * (Parameter already checked)
524 */
525 size = GTZC_TZSC_MPCWM3_MEM_SIZE;
526 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM3_NSWMR1);
527 start_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Pos;
528 start_msk = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Msk;
529 length_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Pos;
530 length_msk = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Msk;
531 break;
532 default:
533 return HAL_ERROR;
534 break;
535 }
536
537 if ((pMPCWM_Desc->Offset > size)
538 || ((pMPCWM_Desc->Offset + pMPCWM_Desc->Length) > size))
539 {
540 return HAL_ERROR;
541 }
542
543 /* write descriptor value */
544 reg_value = ((pMPCWM_Desc->Offset / GTZC_TZSC_MPCWM_GRANULARITY) << start_pos) & start_msk;
545 reg_value |= ((pMPCWM_Desc->Length / GTZC_TZSC_MPCWM_GRANULARITY) << length_pos) & length_msk;
546 MODIFY_REG(*(__IO uint32_t *)register_address, start_msk | length_msk, reg_value);
547
548 return HAL_OK;
549 }
550
551 /**
552 * @brief Get a TZSC-MPCWM area configuration.
553 * @param MemBaseAddress WM identifier.
554 * @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor.
555 * The structure description is available in @ref GTZC_Exported_Types.
556 * @retval HAL status.
557 */
HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,MPCWM_ConfigTypeDef * pMPCWM_Desc)558 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,
559 MPCWM_ConfigTypeDef *pMPCWM_Desc)
560 {
561 uint32_t register_address;
562 uint32_t reg_value;
563 uint32_t start_pos, start_msk;
564 uint32_t length_pos, length_msk;
565
566 /* firstly take care of the first area, present on all MPCWM sub-blocks */
567 switch (MemBaseAddress)
568 {
569 case OCTOSPI1_BASE:
570 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR1);
571 start_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Pos;
572 start_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Msk;
573 length_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Pos;
574 length_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Msk;
575 break;
576 case FMC_BANK1:
577 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR1);
578 start_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Pos;
579 start_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Msk;
580 length_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Pos;
581 length_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Msk;
582 break;
583 case FMC_BANK3:
584 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM3_NSWMR1);
585 start_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Pos;
586 start_msk = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Msk;
587 length_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Pos;
588 length_msk = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Msk;
589 break;
590 default:
591 return HAL_ERROR;
592 break;
593 }
594
595 /* read register and update the descriptor for first area*/
596 reg_value = READ_REG(*(__IO uint32_t *)register_address);
597 pMPCWM_Desc[0].AreaId = GTZC_TZSC_MPCWM_ID1;
598 pMPCWM_Desc[0].Offset = ((reg_value & start_msk) >> start_pos) * GTZC_TZSC_MPCWM_GRANULARITY;
599 pMPCWM_Desc[0].Length = ((reg_value & length_msk) >> length_pos) * GTZC_TZSC_MPCWM_GRANULARITY;
600
601 if (MemBaseAddress != FMC_BANK3)
602 {
603 /* Here MemBaseAddress = OCTOSPI1_BASE
604 * or FMC_BANK1 (already tested)
605 * Now take care of the second area, present on these sub-blocks
606 */
607 switch (MemBaseAddress)
608 {
609 case OCTOSPI1_BASE:
610 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR2);
611 start_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Pos;
612 start_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Msk;
613 length_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Pos;
614 length_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Msk;
615 break;
616 case FMC_BANK1:
617 register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR2);
618 start_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Pos;
619 start_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Msk;
620 length_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Pos;
621 length_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Msk;
622 break;
623 default:
624 return HAL_ERROR;
625 break;
626 }
627
628 /* read register and update the descriptor for second area*/
629 reg_value = READ_REG(*(__IO uint32_t *)register_address);
630 pMPCWM_Desc[1].AreaId = GTZC_TZSC_MPCWM_ID2;
631 pMPCWM_Desc[1].Offset = ((reg_value & start_msk) >> start_pos) * GTZC_TZSC_MPCWM_GRANULARITY;
632 pMPCWM_Desc[1].Length = ((reg_value & length_msk) >> length_pos) * GTZC_TZSC_MPCWM_GRANULARITY;
633 }
634
635 return HAL_OK;
636 }
637
638 /**
639 * @}
640 */
641
642 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
643
644 /** @defgroup GTZC_Exported_Functions_Group3 TZSC and TZSC-MPCWM Lock functions
645 * @brief TZSC and TZSC-MPCWM Lock functions
646 *
647 @verbatim
648 ==============================================================================
649 ##### TZSC and TZSC-MPCWM Lock functions #####
650 ==============================================================================
651 [..]
652 This section provides functions allowing to manage the common TZSC and
653 TZSC-MPCWM lock. It includes lock enable, and current value read.
654 TZSC is TrustZone Security Controller
655 MPCWM is Memory Protection Controller WaterMark
656 @endverbatim
657 * @{
658 */
659
660 /**
661 * @brief Lock TZSC and TZSC-MPCWM configuration.
662 * @param TZSC_Instance TZSC sub-block instance.
663 */
664 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
665
HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef * TZSC_Instance)666 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance)
667 {
668 SET_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
669 }
670
671 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
672
673 /**
674 * @brief Get TZSC and TZSC-MPCWM configuration lock state.
675 * @param TZSC_Instance TZSC sub-block instance.
676 * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON)
677 */
HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef * TZSC_Instance)678 uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance)
679 {
680 return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
681 }
682
683 /**
684 * @}
685 */
686
687 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
688
689 /** @defgroup GTZC_Exported_Functions_Group4 MPCBB Configuration functions
690 * @brief MPCBB Configuration functions
691 *
692 @verbatim
693 ==============================================================================
694 ##### MPCBB Configuration functions #####
695 ==============================================================================
696 [..]
697 This section provides functions allowing to configure MPCBB
698 MPCBB is Memory Protection Controller Block Base
699 @endverbatim
700 * @{
701 */
702
703 /**
704 * @brief Set a complete MPCBB configuration on the SRAM passed as parameter.
705 * @param MemBaseAddress MPCBB identifier.
706 * @param pMPCBB_desc pointer to MPCBB descriptor.
707 * The structure description is available in @ref GTZC_Exported_Types.
708 * @retval HAL status.
709 */
HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,const MPCBB_ConfigTypeDef * pMPCBB_desc)710 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
711 const MPCBB_ConfigTypeDef *pMPCBB_desc)
712 {
713 GTZC_MPCBB_TypeDef *mpcbb_ptr;
714 uint32_t reg_value;
715 uint32_t mem_size;
716 uint32_t size_mask;
717 uint32_t size_in_superblocks;
718 uint32_t i;
719
720 /* check entry parameters */
721 if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
722 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
723 || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE)
724 && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE))
725 || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
726 && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)))
727 {
728 return HAL_ERROR;
729 }
730
731 /* write InvertSecureState and SecureRWIllegalMode properties */
732 /* assume their Position/Mask is identical for all sub-blocks */
733 reg_value = pMPCBB_desc->InvertSecureState;
734 reg_value |= pMPCBB_desc->SecureRWIllegalMode;
735 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
736 {
737 mpcbb_ptr = GTZC_MPCBB1_S;
738 mem_size = GTZC_MEM_SIZE(SRAM1);
739 }
740 else
741 {
742 /* Here MemBaseAddress is inside SRAM2 (already tested) */
743 mpcbb_ptr = GTZC_MPCBB2_S;
744 mem_size = GTZC_MEM_SIZE(SRAM2);
745 }
746
747 /* write vector register information */
748 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
749 for (i = 0U; i < size_in_superblocks; i++)
750 {
751 WRITE_REG(mpcbb_ptr->VCTR[i],
752 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]);
753 }
754
755 /* write configuration and lock register information */
756 MODIFY_REG(mpcbb_ptr->CR,
757 GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value);
758
759 size_mask = (1UL << (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE)) - 1U;
760 /* limitation: code not portable with memory > 256K */
761 MODIFY_REG(mpcbb_ptr->LCKVTR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]);
762
763 return HAL_OK;
764 }
765
766 /**
767 * @brief Get a complete MPCBB configuration on the SRAM passed as parameter.
768 * @param MemBaseAddress MPCBB identifier.
769 * @param pMPCBB_desc pointer to a MPCBB descriptor.
770 * The structure description is available in @ref GTZC_Exported_Types.
771 * @retval HAL status.
772 */
HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,MPCBB_ConfigTypeDef * pMPCBB_desc)773 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
774 MPCBB_ConfigTypeDef *pMPCBB_desc)
775 {
776 GTZC_MPCBB_TypeDef *mpcbb_ptr;
777 uint32_t reg_value;
778 uint32_t mem_size;
779 uint32_t size_mask;
780 uint32_t size_in_superblocks;
781 uint32_t i;
782
783 /* check entry parameters */
784 if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
785 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
786 {
787 return HAL_ERROR;
788 }
789
790 /* read InvertSecureState and SecureRWIllegalMode properties */
791 /* assume their Position/Mask is identical for all sub-blocks */
792 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
793 {
794 mpcbb_ptr = GTZC_MPCBB1_S;
795 mem_size = GTZC_MEM_SIZE(SRAM1);
796 }
797 else
798 {
799 mpcbb_ptr = GTZC_MPCBB2_S;
800 mem_size = GTZC_MEM_SIZE(SRAM2);
801 }
802
803 /* read configuration and lock register information */
804 reg_value = READ_REG(mpcbb_ptr->CR);
805 pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk);
806 pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk);
807 size_mask = (1UL << (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE)) - 1U;
808 /* limitation: code not portable with memory > 256K */
809 pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->LCKVTR1)& size_mask;
810
811 /* read vector register information */
812 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
813 for (i = 0U; i < size_in_superblocks; i++)
814 {
815 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i] = mpcbb_ptr->VCTR[i];
816 }
817
818 return HAL_OK;
819 }
820
821 /**
822 * @brief Set a MPCBB attribute configuration on the SRAM passed as parameter
823 * for a number of blocks.
824 * @param MemAddress MPCBB identifier, and start block to configure
825 * (must be 256 Bytes aligned).
826 * @param NbBlocks Number of blocks to configure.
827 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
828 * with each element must be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC.
829 * @retval HAL status.
830 */
HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,const uint32_t * pMemAttributes)831 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
832 uint32_t NbBlocks,
833 const uint32_t *pMemAttributes)
834 {
835 GTZC_MPCBB_TypeDef *mpcbb_ptr;
836 uint32_t base_address, end_address;
837 uint32_t block_start, offset_reg_start, offset_bit_start;
838 uint32_t i;
839
840 /* firstly check that MemAddress is well 256 Bytes aligned */
841 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
842 {
843 return HAL_ERROR;
844 }
845
846 /* check entry parameters and deduce physical base address */
847 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
848 if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
849 && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U)
850 {
851 mpcbb_ptr = GTZC_MPCBB1_S;
852 base_address = SRAM1_BASE_NS;
853 }
854 else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress))
855 && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U)
856 {
857 mpcbb_ptr = GTZC_MPCBB1_S;
858 base_address = SRAM1_BASE_S;
859 }
860 else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
861 && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U)
862 {
863 mpcbb_ptr = GTZC_MPCBB2_S;
864 base_address = SRAM2_BASE_NS;
865 }
866 else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress))
867 && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U)
868 {
869 mpcbb_ptr = GTZC_MPCBB2_S;
870 base_address = SRAM2_BASE_S;
871 }
872 else
873 {
874 return HAL_ERROR;
875 }
876
877 /* get start coordinates of the configuration */
878 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
879 offset_reg_start = block_start / 32U;
880 offset_bit_start = block_start % 32U;
881
882 for (i = 0U; i < NbBlocks; i++)
883 {
884 if (pMemAttributes[i] == GTZC_MCPBB_BLOCK_SEC)
885 {
886 SET_BIT(mpcbb_ptr->VCTR[offset_reg_start],
887 1UL << (offset_bit_start % 32U));
888 }
889 else if (pMemAttributes[i] == GTZC_MCPBB_BLOCK_NSEC)
890 {
891 CLEAR_BIT(mpcbb_ptr->VCTR[offset_reg_start],
892 1UL << (offset_bit_start % 32U));
893 }
894 else
895 {
896 break;
897 }
898
899 offset_bit_start++;
900 if (offset_bit_start == 32U)
901 {
902 offset_bit_start = 0U;
903 offset_reg_start++;
904 }
905 }
906
907 /* an unexpected value in pMemAttributes array leads to error status */
908 if (i != NbBlocks)
909 {
910 return HAL_ERROR;
911 }
912
913 return HAL_OK;
914 }
915
916 /**
917 * @brief Get a MPCBB attribute configuration on the SRAM passed as parameter
918 * for a number of blocks.
919 * @param MemAddress MPCBB identifier, and start block to get configuration
920 * (must be 256 Bytes aligned).
921 * @param NbBlocks Number of blocks to get configuration.
922 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
923 * with each element will be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC.
924 * @retval HAL status.
925 */
HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,uint32_t * pMemAttributes)926 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
927 uint32_t NbBlocks,
928 uint32_t *pMemAttributes)
929 {
930 GTZC_MPCBB_TypeDef *mpcbb_ptr;
931 uint32_t base_address, end_address;
932 uint32_t block_start, offset_reg_start, offset_bit_start;
933 uint32_t i;
934
935 /* firstly check that MemAddress is well 256 Bytes aligned */
936 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
937 {
938 return HAL_ERROR;
939 }
940
941 /* check entry parameters and deduce physical base address */
942 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
943 if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
944 && (IS_ADDRESS_IN_NS(SRAM1, end_address)))
945 {
946 mpcbb_ptr = GTZC_MPCBB1_S;
947 base_address = SRAM1_BASE_NS;
948 }
949 else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress))
950 && (IS_ADDRESS_IN_S(SRAM1, end_address)))
951 {
952 mpcbb_ptr = GTZC_MPCBB1_S;
953 base_address = SRAM1_BASE_S;
954 }
955 else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
956 && (IS_ADDRESS_IN_NS(SRAM2, end_address)))
957 {
958 mpcbb_ptr = GTZC_MPCBB2_S;
959 base_address = SRAM2_BASE_NS;
960 }
961 else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress))
962 && (IS_ADDRESS_IN_S(SRAM2, end_address)))
963 {
964 mpcbb_ptr = GTZC_MPCBB2_S;
965 base_address = SRAM2_BASE_S;
966 }
967 else
968 {
969 return HAL_ERROR;
970 }
971
972 /* get start coordinates of the configuration */
973 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
974 offset_reg_start = block_start / 32U;
975 offset_bit_start = block_start % 32U;
976
977 for (i = 0U; i < NbBlocks; i++)
978 {
979 pMemAttributes[i] = READ_BIT(mpcbb_ptr->VCTR[offset_reg_start],
980 1UL << (offset_bit_start % 32U))
981 >> (offset_bit_start % 32U);
982
983 offset_bit_start++;
984 if (offset_bit_start == 32U)
985 {
986 offset_bit_start = 0U;
987 offset_reg_start++;
988 }
989 }
990
991 return HAL_OK;
992 }
993
994 /**
995 * @brief Lock MPCBB super-blocks on the SRAM passed as parameter.
996 * @param MemAddress MPCBB identifier, and start super-block to configure
997 * (must be 8KBytes aligned).
998 * @param NbSuperBlocks Number of super-blocks to configure.
999 * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
1000 * with for each element:
1001 * value 0 super-block is unlocked, value 1 super-block is locked
1002 * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
1003 * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
1004 * @retval HAL status.
1005 */
HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,const uint32_t * pLockAttributes)1006 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
1007 uint32_t NbSuperBlocks,
1008 const uint32_t *pLockAttributes)
1009 {
1010 __IO uint32_t *reg_mpcbb;
1011 uint32_t base_address;
1012 uint32_t superblock_start, offset_bit_start;
1013 uint32_t i;
1014
1015 /* firstly check that MemAddress is well 8KBytes aligned */
1016 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1017 {
1018 return HAL_ERROR;
1019 }
1020
1021 /* check entry parameters */
1022 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1023 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1024 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1025 - 1U))))
1026 {
1027 base_address = GTZC_BASE_ADDRESS(SRAM1);
1028 /* limitation: code not portable with memory > 256K */
1029 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->LCKVTR1;
1030 }
1031 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1032 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1033 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1034 - 1U))))
1035 {
1036 base_address = GTZC_BASE_ADDRESS(SRAM2);
1037 /* limitation: code not portable with memory > 256K */
1038 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->LCKVTR1;
1039 }
1040 else
1041 {
1042 return HAL_ERROR;
1043 }
1044
1045 /* get start coordinates of the configuration */
1046 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1047 offset_bit_start = superblock_start % 32U;
1048
1049 for (i = 0U; i < NbSuperBlocks; i++)
1050 {
1051 if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_LOCKED)
1052 {
1053 SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1054 }
1055 else if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_UNLOCKED)
1056 {
1057 CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1058 }
1059 else
1060 {
1061 break;
1062 }
1063
1064 offset_bit_start++;
1065 }
1066
1067 /* an unexpected value in pLockAttributes array leads to an error status */
1068 if (i != NbSuperBlocks)
1069 {
1070 return HAL_ERROR;
1071 }
1072
1073 return HAL_OK;
1074 }
1075
1076 /**
1077 * @brief Get MPCBB super-blocks lock configuration on the SRAM passed as parameter.
1078 * @param MemAddress MPCBB identifier, and start super-block to get
1079 * configuration (must be 8KBytes aligned).
1080 * @param NbSuperBlocks Number of super-blocks to get configuration.
1081 * @param pLockAttributes pointer to an array (size is NbSuperBlocks),
1082 * with for each element:
1083 * value 0 super-block is unlocked, value 1 super-block is locked
1084 * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
1085 * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
1086 * @retval HAL status.
1087 */
HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,uint32_t * pLockAttributes)1088 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
1089 uint32_t NbSuperBlocks,
1090 uint32_t *pLockAttributes)
1091 {
1092 uint32_t reg_mpcbb;
1093 uint32_t base_address;
1094 uint32_t superblock_start, offset_bit_start;
1095 uint32_t i;
1096
1097 /* firstly check that MemAddress is well 8KBytes aligned */
1098 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1099 {
1100 return HAL_ERROR;
1101 }
1102
1103 /* check entry parameters */
1104 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1105 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1106 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1107 - 1U))))
1108 {
1109 base_address = GTZC_BASE_ADDRESS(SRAM1);
1110 /* limitation: code not portable with memory > 256K */
1111 reg_mpcbb = GTZC_MPCBB1_S->LCKVTR1;
1112 }
1113 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1114 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1115 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1116 - 1U))))
1117 {
1118 base_address = GTZC_BASE_ADDRESS(SRAM2);
1119 /* limitation: code not portable with memory > 256K */
1120 reg_mpcbb = GTZC_MPCBB2_S->LCKVTR1;
1121 }
1122 else
1123 {
1124 return HAL_ERROR;
1125 }
1126
1127 /* get start coordinates of the configuration */
1128 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1129 offset_bit_start = superblock_start % 32U;
1130
1131 for (i = 0U; i < NbSuperBlocks; i++)
1132 {
1133 pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U)))
1134 >> (offset_bit_start % 32U);
1135 offset_bit_start++;
1136 }
1137
1138 return HAL_OK;
1139 }
1140
1141 /**
1142 * @brief Lock a MPCBB configuration on the SRAM base address passed as parameter.
1143 * @param MemBaseAddress MPCBB identifier.
1144 * @retval HAL status.
1145 */
HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)1146 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)
1147 {
1148 /* check entry parameters */
1149 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1150 {
1151 SET_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_LCK_Msk);
1152 }
1153 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1154 {
1155 SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_LCK_Msk);
1156 }
1157 else
1158 {
1159 return HAL_ERROR;
1160 }
1161
1162 return HAL_OK;
1163 }
1164
1165 /**
1166 * @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter.
1167 * @param MemBaseAddress MPCBB identifier.
1168 * @param pLockState pointer to Lock State (GTZC_MCPBB_LOCK_OFF or GTZC_MCPBB_LOCK_ON).
1169 * @retval HAL status.
1170 */
HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,uint32_t * pLockState)1171 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
1172 uint32_t *pLockState)
1173 {
1174 /* check entry parameters */
1175 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1176 {
1177 *pLockState = READ_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_LCK_Msk);
1178 }
1179 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1180 {
1181 *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_LCK_Msk);
1182 }
1183 else
1184 {
1185 return HAL_ERROR;
1186 }
1187
1188 return HAL_OK;
1189 }
1190
1191 /**
1192 * @}
1193 */
1194
1195 /** @defgroup GTZC_Exported_Functions_Group5 TZIC Configuration and Control functions
1196 * @brief TZIC Configuration and Control functions
1197 *
1198 @verbatim
1199 ==============================================================================
1200 ##### TZIC Configuration and Control functions #####
1201 ==============================================================================
1202 [..]
1203 This section provides functions allowing to configure and control TZIC
1204 TZIC is Trust Zone Interrupt Controller
1205 @endverbatim
1206 * @{
1207 */
1208
1209 /**
1210 * @brief Disable the interrupt associated to a single TZIC peripheral or on all peripherals.
1211 * @param PeriphId Peripheral identifier.
1212 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1213 * Use GTZC_PERIPH_ALL to select all peripherals.
1214 * @retval HAL status.
1215 */
HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)1216 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)
1217 {
1218 uint32_t register_address;
1219
1220 /* check entry parameters */
1221 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1222 || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1223 {
1224 return HAL_ERROR;
1225 }
1226
1227 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1228 {
1229 /* same configuration is applied to all peripherals */
1230 WRITE_REG(GTZC_TZIC->IER1, 0U);
1231 WRITE_REG(GTZC_TZIC->IER2, 0U);
1232 WRITE_REG(GTZC_TZIC->IER3, 0U);
1233 }
1234 else
1235 {
1236 /* common case where only one peripheral is configured */
1237 register_address = (uint32_t) &(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
1238 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1239 }
1240
1241 return HAL_OK;
1242 }
1243
1244 /**
1245 * @brief Enable the interrupt associated to a single TZIC peripheral or on all peripherals.
1246 * @param PeriphId Peripheral identifier.
1247 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1248 * Use GTZC_PERIPH_ALL to select all peripherals.
1249 * @retval HAL status.
1250 */
HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)1251 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)
1252 {
1253 uint32_t register_address;
1254
1255 /* check entry parameters */
1256 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1257 || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1258 {
1259 return HAL_ERROR;
1260 }
1261
1262 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1263 {
1264 /* same configuration is applied to all peripherals */
1265 WRITE_REG(GTZC_TZIC->IER1, TZIC_IER1_ALL);
1266 WRITE_REG(GTZC_TZIC->IER2, TZIC_IER2_ALL);
1267 WRITE_REG(GTZC_TZIC->IER3, TZIC_IER3_ALL);
1268 }
1269 else
1270 {
1271 /* common case where only one peripheral is configured */
1272 register_address = (uint32_t) &(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
1273 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1274 }
1275
1276 return HAL_OK;
1277 }
1278
1279 /**
1280 * @brief Get TZIC flag on a single TZIC peripheral or on all peripherals.
1281 * @param PeriphId Peripheral identifier.
1282 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1283 * Use GTZC_PERIPH_ALL to select all peripherals.
1284 * @param pFlag Pointer to the flags.
1285 * If PeriphId target a single peripheral, pointer on a single element.
1286 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array
1287 * of GTZC_TZIC_PERIPH_NUMBER elements.
1288 * Element content is either GTZC_TZIC_NO_ILA_EVENT
1289 * or GTZC_TZSC_ILA_EVENT_PENDING.
1290 * @retval HAL status
1291 */
HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId,uint32_t * pFlag)1292 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag)
1293 {
1294 uint32_t i;
1295 uint32_t reg_value;
1296 uint32_t register_address;
1297
1298 /* check entry parameters */
1299 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1300 || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1301 {
1302 return HAL_ERROR;
1303 }
1304
1305 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1306 {
1307 /* special case where it is applied to all peripherals */
1308 reg_value = READ_REG(GTZC_TZIC->SR1);
1309 for (i = 0U; i < 32U; i++)
1310 {
1311 pFlag[i] = (reg_value & (1UL << i)) >> i;
1312 }
1313
1314 reg_value = READ_REG(GTZC_TZIC->SR2);
1315 for (/*i = 32U*/; i < 64U; i++)
1316 {
1317 pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U);
1318 }
1319
1320 reg_value = READ_REG(GTZC_TZIC->SR3);
1321 for (/*i = 64U*/; i < GTZC_TZIC_PERIPH_NUMBER; i++)
1322 {
1323 pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U);
1324 }
1325 }
1326 else
1327 {
1328 /* common case where only one peripheral is concerned */
1329 register_address = (uint32_t) &(GTZC_TZIC->SR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
1330 *pFlag = READ_BIT(*(__IO uint32_t *)register_address,
1331 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId);
1332 }
1333
1334 return HAL_OK;
1335 }
1336
1337 /**
1338 * @brief Clear TZIC flag on a single TZIC peripheral or on all peripherals.
1339 * @param PeriphId Peripheral identifier.
1340 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1341 * Use GTZC_PERIPH_ALL to select all peripherals.
1342 * @retval HAL status.
1343 */
HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)1344 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)
1345 {
1346 uint32_t register_address;
1347
1348 /* check entry parameters */
1349 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1350 || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1351 {
1352 return HAL_ERROR;
1353 }
1354
1355 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1356 {
1357 /* same configuration is applied to all peripherals */
1358 WRITE_REG(GTZC_TZIC->FCR1, TZIC_FCR1_ALL);
1359 WRITE_REG(GTZC_TZIC->FCR2, TZIC_FCR2_ALL);
1360 WRITE_REG(GTZC_TZIC->FCR3, TZIC_FCR3_ALL);
1361 }
1362 else
1363 {
1364 /* common case where only one peripheral is configured */
1365 register_address = (uint32_t) &(GTZC_TZIC->FCR1) + (4U * GTZC_GET_REG_INDEX(PeriphId));
1366 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1367 }
1368
1369 return HAL_OK;
1370 }
1371
1372 /**
1373 * @}
1374 */
1375
1376 /** @defgroup GTZC_Exported_Functions_Group6 IRQ related functions
1377 * @brief IRQ related functions
1378 *
1379 @verbatim
1380 ==============================================================================
1381 ##### TZIC IRQ Handler and Callback functions #####
1382 ==============================================================================
1383 [..]
1384 This section provides functions allowing to treat ISR and provide user callback
1385 @endverbatim
1386 * @{
1387 */
1388
1389 /**
1390 * @brief This function handles GTZC interrupt request.
1391 * @retval None.
1392 */
HAL_GTZC_IRQHandler(void)1393 void HAL_GTZC_IRQHandler(void)
1394 {
1395 uint32_t position;
1396 uint32_t flag;
1397 uint32_t ier_itsources;
1398 uint32_t sr_flags;
1399
1400 /* Get current IT Flags and IT sources value on 1st register */
1401 ier_itsources = READ_REG(GTZC_TZIC->IER1);
1402 sr_flags = READ_REG(GTZC_TZIC->SR1);
1403
1404 /* Get Mask interrupt and then clear them */
1405 flag = ier_itsources & sr_flags;
1406 if (flag != 0U)
1407 {
1408 WRITE_REG(GTZC_TZIC->FCR1, flag);
1409
1410 /* Loop on flag to check, which ones have been raised */
1411 position = 0U;
1412 while ((flag >> position) != 0U)
1413 {
1414 if ((flag & (1UL << position)) != 0U)
1415 {
1416 HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG1 | position);
1417 }
1418
1419 /* Position bit to be updated */
1420 position++;
1421 }
1422 }
1423
1424 /* Get current IT Flags and IT sources value on 2nd register */
1425 ier_itsources = READ_REG(GTZC_TZIC->IER2);
1426 sr_flags = READ_REG(GTZC_TZIC->SR2);
1427
1428 /* Get Mask interrupt and then clear them */
1429 flag = ier_itsources & sr_flags;
1430 if (flag != 0U)
1431 {
1432 WRITE_REG(GTZC_TZIC->FCR2, flag);
1433
1434 /* Loop on flag to check, which ones have been raised */
1435 position = 0U;
1436 while ((flag >> position) != 0U)
1437 {
1438 if ((flag & (1UL << position)) != 0U)
1439 {
1440 HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG2 | position);
1441 }
1442
1443 /* Position bit to be updated */
1444 position++;
1445 }
1446 }
1447
1448 /* Get current IT Flags and IT sources value on 3rd register */
1449 ier_itsources = READ_REG(GTZC_TZIC->IER3);
1450 sr_flags = READ_REG(GTZC_TZIC->SR3);
1451
1452 /* Get Mask interrupt and then clear them */
1453 flag = ier_itsources & sr_flags;
1454 if (flag != 0U)
1455 {
1456 WRITE_REG(GTZC_TZIC->FCR3, flag);
1457
1458 /* Loop on flag to check, which ones have been raised */
1459 position = 0U;
1460 while ((flag >> position) != 0U)
1461 {
1462 if ((flag & (1UL << position)) != 0U)
1463 {
1464 HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG3 | position);
1465 }
1466
1467 /* Position bit to be updated */
1468 position++;
1469 }
1470 }
1471 }
1472
1473 /**
1474 * @brief GTZC TZIC sub-block interrupt callback.
1475 * @param PeriphId Peripheral identifier triggering the illegal access.
1476 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId
1477 * @retval None.
1478 */
HAL_GTZC_TZIC_Callback(uint32_t PeriphId)1479 __weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId)
1480 {
1481 /* Prevent unused argument(s) compilation warning */
1482 UNUSED(PeriphId);
1483
1484 /* NOTE: This function should not be modified. When the callback is needed,
1485 * the HAL_GTZC_TZIC_Callback is to be implemented in the user file
1486 */
1487 }
1488
1489 /**
1490 * @}
1491 */
1492
1493 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1494
1495 /**
1496 * @}
1497 */
1498
1499 #endif /*HAL_GTZC_MODULE_ENABLED*/
1500
1501 /**
1502 * @}
1503 */
1504
1505 /**
1506 * @}
1507 */
1508
