1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32l4xx_ll_tim.h"
22 #include "stm32l4xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
71
72 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
73 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
74
75 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
76 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
77
78 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
79 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
80
81 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
82 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
83 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
84
85 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
86 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
87 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
89
90 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
106
107 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
108 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
109 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
110
111 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
112 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
113 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
114
115 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
116 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
117
118 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
119 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
120
121 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
122 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
123
124 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
125 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
126 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
127 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
128
129 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
130 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
131
132 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
133 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
134
135 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
136 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
137 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
138 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
139 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
140 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
141 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
142 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
143 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
151
152 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
153 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
154
155 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
156 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
157
158 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
159 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
160 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
161 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
162 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
163 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
164 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
165 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
166 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
167 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
168 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
169 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
174
175 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
176 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
177 /**
178 * @}
179 */
180
181
182 /* Private function prototypes -----------------------------------------------*/
183 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
184 * @{
185 */
186 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
187 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
188 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
189 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
190 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
191 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
192 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
193 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
194 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
195 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
196 /**
197 * @}
198 */
199
200 /* Exported functions --------------------------------------------------------*/
201 /** @addtogroup TIM_LL_Exported_Functions
202 * @{
203 */
204
205 /** @addtogroup TIM_LL_EF_Init
206 * @{
207 */
208
209 /**
210 * @brief Set TIMx registers to their reset values.
211 * @param TIMx Timer instance
212 * @retval An ErrorStatus enumeration value:
213 * - SUCCESS: TIMx registers are de-initialized
214 * - ERROR: invalid TIMx instance
215 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)216 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
217 {
218 ErrorStatus result = SUCCESS;
219
220 /* Check the parameters */
221 assert_param(IS_TIM_INSTANCE(TIMx));
222
223 if (TIMx == TIM1)
224 {
225 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
226 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
227 }
228 else if (TIMx == TIM2)
229 {
230 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
231 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
232 }
233 #if defined(TIM3)
234 else if (TIMx == TIM3)
235 {
236 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
237 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
238 }
239 #endif /* TIM3 */
240 #if defined(TIM4)
241 else if (TIMx == TIM4)
242 {
243 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
244 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
245 }
246 #endif /* TIM4 */
247 #if defined(TIM5)
248 else if (TIMx == TIM5)
249 {
250 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
251 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
252 }
253 #endif /* TIM5 */
254 else if (TIMx == TIM6)
255 {
256 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
257 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
258 }
259 #if defined (TIM7)
260 else if (TIMx == TIM7)
261 {
262 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
263 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
264 }
265 #endif /* TIM7 */
266 #if defined(TIM8)
267 else if (TIMx == TIM8)
268 {
269 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
270 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
271 }
272 #endif /* TIM8 */
273 else if (TIMx == TIM15)
274 {
275 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
276 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
277 }
278 else if (TIMx == TIM16)
279 {
280 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
281 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
282 }
283 #if defined(TIM17)
284 else if (TIMx == TIM17)
285 {
286 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
287 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
288 }
289 #endif /* TIM17 */
290 else
291 {
292 result = ERROR;
293 }
294
295 return result;
296 }
297
298 /**
299 * @brief Set the fields of the time base unit configuration data structure
300 * to their default values.
301 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
302 * @retval None
303 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)304 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
305 {
306 /* Set the default configuration */
307 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
308 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
309 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
310 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
311 TIM_InitStruct->RepetitionCounter = 0x00000000U;
312 }
313
314 /**
315 * @brief Configure the TIMx time base unit.
316 * @param TIMx Timer Instance
317 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
318 * (TIMx time base unit configuration data structure)
319 * @retval An ErrorStatus enumeration value:
320 * - SUCCESS: TIMx registers are de-initialized
321 * - ERROR: not applicable
322 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)323 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
324 {
325 uint32_t tmpcr1;
326
327 /* Check the parameters */
328 assert_param(IS_TIM_INSTANCE(TIMx));
329 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
330 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
331
332 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
333
334 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
335 {
336 /* Select the Counter Mode */
337 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
338 }
339
340 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
341 {
342 /* Set the clock division */
343 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
344 }
345
346 /* Write to TIMx CR1 */
347 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
348
349 /* Set the Autoreload value */
350 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
351
352 /* Set the Prescaler value */
353 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
354
355 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
356 {
357 /* Set the Repetition Counter value */
358 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
359 }
360
361 /* Generate an update event to reload the Prescaler
362 and the repetition counter value (if applicable) immediately */
363 LL_TIM_GenerateEvent_UPDATE(TIMx);
364
365 return SUCCESS;
366 }
367
368 /**
369 * @brief Set the fields of the TIMx output channel configuration data
370 * structure to their default values.
371 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
372 * (the output channel configuration data structure)
373 * @retval None
374 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)375 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
376 {
377 /* Set the default configuration */
378 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
379 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
380 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
381 TIM_OC_InitStruct->CompareValue = 0x00000000U;
382 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
383 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
384 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
385 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
386 }
387
388 /**
389 * @brief Configure the TIMx output channel.
390 * @param TIMx Timer Instance
391 * @param Channel This parameter can be one of the following values:
392 * @arg @ref LL_TIM_CHANNEL_CH1
393 * @arg @ref LL_TIM_CHANNEL_CH2
394 * @arg @ref LL_TIM_CHANNEL_CH3
395 * @arg @ref LL_TIM_CHANNEL_CH4
396 * @arg @ref LL_TIM_CHANNEL_CH5
397 * @arg @ref LL_TIM_CHANNEL_CH6
398 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
399 * data structure)
400 * @retval An ErrorStatus enumeration value:
401 * - SUCCESS: TIMx output channel is initialized
402 * - ERROR: TIMx output channel is not initialized
403 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)404 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
405 {
406 ErrorStatus result = ERROR;
407
408 switch (Channel)
409 {
410 case LL_TIM_CHANNEL_CH1:
411 result = OC1Config(TIMx, TIM_OC_InitStruct);
412 break;
413 case LL_TIM_CHANNEL_CH2:
414 result = OC2Config(TIMx, TIM_OC_InitStruct);
415 break;
416 case LL_TIM_CHANNEL_CH3:
417 result = OC3Config(TIMx, TIM_OC_InitStruct);
418 break;
419 case LL_TIM_CHANNEL_CH4:
420 result = OC4Config(TIMx, TIM_OC_InitStruct);
421 break;
422 case LL_TIM_CHANNEL_CH5:
423 result = OC5Config(TIMx, TIM_OC_InitStruct);
424 break;
425 case LL_TIM_CHANNEL_CH6:
426 result = OC6Config(TIMx, TIM_OC_InitStruct);
427 break;
428 default:
429 break;
430 }
431
432 return result;
433 }
434
435 /**
436 * @brief Set the fields of the TIMx input channel configuration data
437 * structure to their default values.
438 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
439 * data structure)
440 * @retval None
441 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)442 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
443 {
444 /* Set the default configuration */
445 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
446 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
447 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
448 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
449 }
450
451 /**
452 * @brief Configure the TIMx input channel.
453 * @param TIMx Timer Instance
454 * @param Channel This parameter can be one of the following values:
455 * @arg @ref LL_TIM_CHANNEL_CH1
456 * @arg @ref LL_TIM_CHANNEL_CH2
457 * @arg @ref LL_TIM_CHANNEL_CH3
458 * @arg @ref LL_TIM_CHANNEL_CH4
459 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
460 * structure)
461 * @retval An ErrorStatus enumeration value:
462 * - SUCCESS: TIMx output channel is initialized
463 * - ERROR: TIMx output channel is not initialized
464 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)465 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
466 {
467 ErrorStatus result = ERROR;
468
469 switch (Channel)
470 {
471 case LL_TIM_CHANNEL_CH1:
472 result = IC1Config(TIMx, TIM_IC_InitStruct);
473 break;
474 case LL_TIM_CHANNEL_CH2:
475 result = IC2Config(TIMx, TIM_IC_InitStruct);
476 break;
477 case LL_TIM_CHANNEL_CH3:
478 result = IC3Config(TIMx, TIM_IC_InitStruct);
479 break;
480 case LL_TIM_CHANNEL_CH4:
481 result = IC4Config(TIMx, TIM_IC_InitStruct);
482 break;
483 default:
484 break;
485 }
486
487 return result;
488 }
489
490 /**
491 * @brief Fills each TIM_EncoderInitStruct field with its default value
492 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
493 * configuration data structure)
494 * @retval None
495 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)496 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
497 {
498 /* Set the default configuration */
499 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
500 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
501 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
502 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
503 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
504 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
505 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
506 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
507 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
508 }
509
510 /**
511 * @brief Configure the encoder interface of the timer instance.
512 * @param TIMx Timer Instance
513 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
514 * configuration data structure)
515 * @retval An ErrorStatus enumeration value:
516 * - SUCCESS: TIMx registers are de-initialized
517 * - ERROR: not applicable
518 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)519 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
520 {
521 uint32_t tmpccmr1;
522 uint32_t tmpccer;
523
524 /* Check the parameters */
525 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
526 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
527 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
528 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
529 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
530 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
531 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
532 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
533 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
534 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
535
536 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
537 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
538
539 /* Get the TIMx CCMR1 register value */
540 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
541
542 /* Get the TIMx CCER register value */
543 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
544
545 /* Configure TI1 */
546 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
547 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
548 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
549 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
550
551 /* Configure TI2 */
552 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
553 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
554 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
555 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
556
557 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
558 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
559 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
560 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
561 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
562
563 /* Set encoder mode */
564 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
565
566 /* Write to TIMx CCMR1 */
567 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
568
569 /* Write to TIMx CCER */
570 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
571
572 return SUCCESS;
573 }
574
575 /**
576 * @brief Set the fields of the TIMx Hall sensor interface configuration data
577 * structure to their default values.
578 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
579 * configuration data structure)
580 * @retval None
581 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)582 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
583 {
584 /* Set the default configuration */
585 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
586 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
587 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
588 TIM_HallSensorInitStruct->CommutationDelay = 0U;
589 }
590
591 /**
592 * @brief Configure the Hall sensor interface of the timer instance.
593 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
594 * to the TI1 input channel
595 * @note TIMx slave mode controller is configured in reset mode.
596 Selected internal trigger is TI1F_ED.
597 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
598 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
599 * between 2 changes on the inputs. It gives information about motor speed.
600 * @note Channel 2 is configured in output PWM 2 mode.
601 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
602 * @note OC2REF is selected as trigger output on TRGO.
603 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
604 * when TIMx operates in Hall sensor interface mode.
605 * @param TIMx Timer Instance
606 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
607 * interface configuration data structure)
608 * @retval An ErrorStatus enumeration value:
609 * - SUCCESS: TIMx registers are de-initialized
610 * - ERROR: not applicable
611 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)612 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
613 {
614 uint32_t tmpcr2;
615 uint32_t tmpccmr1;
616 uint32_t tmpccer;
617 uint32_t tmpsmcr;
618
619 /* Check the parameters */
620 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
621 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
622 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
623 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
624
625 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
626 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
627
628 /* Get the TIMx CR2 register value */
629 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
630
631 /* Get the TIMx CCMR1 register value */
632 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
633
634 /* Get the TIMx CCER register value */
635 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
636
637 /* Get the TIMx SMCR register value */
638 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
639
640 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
641 tmpcr2 |= TIM_CR2_TI1S;
642
643 /* OC2REF signal is used as trigger output (TRGO) */
644 tmpcr2 |= LL_TIM_TRGO_OC2REF;
645
646 /* Configure the slave mode controller */
647 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
648 tmpsmcr |= LL_TIM_TS_TI1F_ED;
649 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
650
651 /* Configure input channel 1 */
652 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
653 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
654 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
655 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
656
657 /* Configure input channel 2 */
658 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
659 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
660
661 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
662 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
663 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
664 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
665
666 /* Write to TIMx CR2 */
667 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
668
669 /* Write to TIMx SMCR */
670 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
671
672 /* Write to TIMx CCMR1 */
673 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
674
675 /* Write to TIMx CCER */
676 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
677
678 /* Write to TIMx CCR2 */
679 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
680
681 return SUCCESS;
682 }
683
684 /**
685 * @brief Set the fields of the Break and Dead Time configuration data structure
686 * to their default values.
687 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
688 * data structure)
689 * @retval None
690 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)691 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
692 {
693 /* Set the default configuration */
694 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
695 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
696 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
697 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
698 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
699 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
700 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
701 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
702 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
703 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
704 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
705 }
706
707 /**
708 * @brief Configure the Break and Dead Time feature of the timer instance.
709 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
710 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
711 * can be necessary to configure all of them during the first write access to
712 * the TIMx_BDTR register.
713 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
714 * a timer instance provides a break input.
715 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
716 * a timer instance provides a second break input.
717 * @param TIMx Timer Instance
718 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
719 * data structure)
720 * @retval An ErrorStatus enumeration value:
721 * - SUCCESS: Break and Dead Time is initialized
722 * - ERROR: not applicable
723 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)724 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
725 {
726 uint32_t tmpbdtr = 0;
727
728 /* Check the parameters */
729 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
730 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
731 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
732 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
733 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
734 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
735 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
736 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
737
738 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
739 the OSSI State, the dead time value and the Automatic Output Enable Bit */
740
741 /* Set the BDTR bits */
742 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
743 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
744 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
745 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
746 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
747 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
748 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
749 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
750
751 if (IS_TIM_BKIN2_INSTANCE(TIMx))
752 {
753 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
754 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
755 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
756
757 /* Set the BREAK2 input related BDTR bit-fields */
758 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
759 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
760 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
761 }
762
763 /* Set TIMx_BDTR */
764 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
765
766 return SUCCESS;
767 }
768 /**
769 * @}
770 */
771
772 /**
773 * @}
774 */
775
776 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
777 * @brief Private functions
778 * @{
779 */
780 /**
781 * @brief Configure the TIMx output channel 1.
782 * @param TIMx Timer Instance
783 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
784 * @retval An ErrorStatus enumeration value:
785 * - SUCCESS: TIMx registers are de-initialized
786 * - ERROR: not applicable
787 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)788 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
789 {
790 uint32_t tmpccmr1;
791 uint32_t tmpccer;
792 uint32_t tmpcr2;
793
794 /* Check the parameters */
795 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
796 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
797 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
798 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
799
800 /* Disable the Channel 1: Reset the CC1E Bit */
801 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
802
803 /* Get the TIMx CCER register value */
804 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
805
806 /* Get the TIMx CR2 register value */
807 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
808
809 /* Get the TIMx CCMR1 register value */
810 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
811
812 /* Reset Capture/Compare selection Bits */
813 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
814
815 /* Set the Output Compare Mode */
816 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
817
818 /* Set the Output Compare Polarity */
819 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
820
821 /* Set the Output State */
822 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
823
824 if (IS_TIM_BREAK_INSTANCE(TIMx))
825 {
826 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
827 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
828 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
829 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
830
831 /* Set the complementary output Polarity */
832 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
833
834 /* Set the complementary output State */
835 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
836
837 /* Set the Output Idle state */
838 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
839
840 /* Set the complementary output Idle state */
841 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
842 }
843
844 /* Write to TIMx CR2 */
845 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
846
847 /* Write to TIMx CCMR1 */
848 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
849
850 /* Set the Capture Compare Register value */
851 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
852
853 /* Write to TIMx CCER */
854 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
855
856 return SUCCESS;
857 }
858
859 /**
860 * @brief Configure the TIMx output channel 2.
861 * @param TIMx Timer Instance
862 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
863 * @retval An ErrorStatus enumeration value:
864 * - SUCCESS: TIMx registers are de-initialized
865 * - ERROR: not applicable
866 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)867 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
868 {
869 uint32_t tmpccmr1;
870 uint32_t tmpccer;
871 uint32_t tmpcr2;
872
873 /* Check the parameters */
874 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
875 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
876 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
877 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
878
879 /* Disable the Channel 2: Reset the CC2E Bit */
880 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
881
882 /* Get the TIMx CCER register value */
883 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
884
885 /* Get the TIMx CR2 register value */
886 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
887
888 /* Get the TIMx CCMR1 register value */
889 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
890
891 /* Reset Capture/Compare selection Bits */
892 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
893
894 /* Select the Output Compare Mode */
895 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
896
897 /* Set the Output Compare Polarity */
898 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
899
900 /* Set the Output State */
901 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
902
903 if (IS_TIM_BREAK_INSTANCE(TIMx))
904 {
905 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
906 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
907 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
908 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
909
910 /* Set the complementary output Polarity */
911 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
912
913 /* Set the complementary output State */
914 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
915
916 /* Set the Output Idle state */
917 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
918
919 /* Set the complementary output Idle state */
920 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
921 }
922
923 /* Write to TIMx CR2 */
924 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
925
926 /* Write to TIMx CCMR1 */
927 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
928
929 /* Set the Capture Compare Register value */
930 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
931
932 /* Write to TIMx CCER */
933 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
934
935 return SUCCESS;
936 }
937
938 /**
939 * @brief Configure the TIMx output channel 3.
940 * @param TIMx Timer Instance
941 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
942 * @retval An ErrorStatus enumeration value:
943 * - SUCCESS: TIMx registers are de-initialized
944 * - ERROR: not applicable
945 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)946 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
947 {
948 uint32_t tmpccmr2;
949 uint32_t tmpccer;
950 uint32_t tmpcr2;
951
952 /* Check the parameters */
953 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
954 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
955 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
956 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
957
958 /* Disable the Channel 3: Reset the CC3E Bit */
959 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
960
961 /* Get the TIMx CCER register value */
962 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
963
964 /* Get the TIMx CR2 register value */
965 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
966
967 /* Get the TIMx CCMR2 register value */
968 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
969
970 /* Reset Capture/Compare selection Bits */
971 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
972
973 /* Select the Output Compare Mode */
974 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
975
976 /* Set the Output Compare Polarity */
977 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
978
979 /* Set the Output State */
980 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
981
982 if (IS_TIM_BREAK_INSTANCE(TIMx))
983 {
984 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
985 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
986 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
987 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
988
989 /* Set the complementary output Polarity */
990 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
991
992 /* Set the complementary output State */
993 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
994
995 /* Set the Output Idle state */
996 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
997
998 /* Set the complementary output Idle state */
999 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1000 }
1001
1002 /* Write to TIMx CR2 */
1003 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1004
1005 /* Write to TIMx CCMR2 */
1006 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1007
1008 /* Set the Capture Compare Register value */
1009 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1010
1011 /* Write to TIMx CCER */
1012 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1013
1014 return SUCCESS;
1015 }
1016
1017 /**
1018 * @brief Configure the TIMx output channel 4.
1019 * @param TIMx Timer Instance
1020 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1021 * @retval An ErrorStatus enumeration value:
1022 * - SUCCESS: TIMx registers are de-initialized
1023 * - ERROR: not applicable
1024 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1025 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1026 {
1027 uint32_t tmpccmr2;
1028 uint32_t tmpccer;
1029 uint32_t tmpcr2;
1030
1031 /* Check the parameters */
1032 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1033 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1034 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1035 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1036
1037 /* Disable the Channel 4: Reset the CC4E Bit */
1038 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1039
1040 /* Get the TIMx CCER register value */
1041 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1042
1043 /* Get the TIMx CR2 register value */
1044 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1045
1046 /* Get the TIMx CCMR2 register value */
1047 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1048
1049 /* Reset Capture/Compare selection Bits */
1050 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1051
1052 /* Select the Output Compare Mode */
1053 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1054
1055 /* Set the Output Compare Polarity */
1056 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1057
1058 /* Set the Output State */
1059 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1060
1061 if (IS_TIM_BREAK_INSTANCE(TIMx))
1062 {
1063 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1064
1065 /* Set the Output Idle state */
1066 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1067 }
1068
1069 /* Write to TIMx CR2 */
1070 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1071
1072 /* Write to TIMx CCMR2 */
1073 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1074
1075 /* Set the Capture Compare Register value */
1076 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1077
1078 /* Write to TIMx CCER */
1079 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1080
1081 return SUCCESS;
1082 }
1083
1084 /**
1085 * @brief Configure the TIMx output channel 5.
1086 * @param TIMx Timer Instance
1087 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1088 * @retval An ErrorStatus enumeration value:
1089 * - SUCCESS: TIMx registers are de-initialized
1090 * - ERROR: not applicable
1091 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1092 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1093 {
1094 uint32_t tmpccmr3;
1095 uint32_t tmpccer;
1096
1097 /* Check the parameters */
1098 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1099 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1100 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1101 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1102 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1103 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1104
1105 /* Disable the Channel 5: Reset the CC5E Bit */
1106 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1107
1108 /* Get the TIMx CCER register value */
1109 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1110
1111 /* Get the TIMx CCMR3 register value */
1112 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1113
1114 /* Select the Output Compare Mode */
1115 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1116
1117 /* Set the Output Compare Polarity */
1118 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1119
1120 /* Set the Output State */
1121 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1122
1123 if (IS_TIM_BREAK_INSTANCE(TIMx))
1124 {
1125 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1126 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1127
1128 /* Set the Output Idle state */
1129 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1130
1131 }
1132
1133 /* Write to TIMx CCMR3 */
1134 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1135
1136 /* Set the Capture Compare Register value */
1137 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1138
1139 /* Write to TIMx CCER */
1140 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1141
1142 return SUCCESS;
1143 }
1144
1145 /**
1146 * @brief Configure the TIMx output channel 6.
1147 * @param TIMx Timer Instance
1148 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1149 * @retval An ErrorStatus enumeration value:
1150 * - SUCCESS: TIMx registers are de-initialized
1151 * - ERROR: not applicable
1152 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1153 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1154 {
1155 uint32_t tmpccmr3;
1156 uint32_t tmpccer;
1157
1158 /* Check the parameters */
1159 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1160 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1161 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1162 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1163 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1164 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1165
1166 /* Disable the Channel 5: Reset the CC6E Bit */
1167 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1168
1169 /* Get the TIMx CCER register value */
1170 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1171
1172 /* Get the TIMx CCMR3 register value */
1173 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1174
1175 /* Select the Output Compare Mode */
1176 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1177
1178 /* Set the Output Compare Polarity */
1179 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1180
1181 /* Set the Output State */
1182 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1183
1184 if (IS_TIM_BREAK_INSTANCE(TIMx))
1185 {
1186 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1187 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1188
1189 /* Set the Output Idle state */
1190 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1191 }
1192
1193 /* Write to TIMx CCMR3 */
1194 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1195
1196 /* Set the Capture Compare Register value */
1197 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1198
1199 /* Write to TIMx CCER */
1200 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1201
1202 return SUCCESS;
1203 }
1204
1205 /**
1206 * @brief Configure the TIMx input channel 1.
1207 * @param TIMx Timer Instance
1208 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1209 * @retval An ErrorStatus enumeration value:
1210 * - SUCCESS: TIMx registers are de-initialized
1211 * - ERROR: not applicable
1212 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1213 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1214 {
1215 /* Check the parameters */
1216 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1217 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1218 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1219 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1220 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1221
1222 /* Disable the Channel 1: Reset the CC1E Bit */
1223 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1224
1225 /* Select the Input and set the filter and the prescaler value */
1226 MODIFY_REG(TIMx->CCMR1,
1227 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1228 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1229
1230 /* Select the Polarity and set the CC1E Bit */
1231 MODIFY_REG(TIMx->CCER,
1232 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1233 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1234
1235 return SUCCESS;
1236 }
1237
1238 /**
1239 * @brief Configure the TIMx input channel 2.
1240 * @param TIMx Timer Instance
1241 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1242 * @retval An ErrorStatus enumeration value:
1243 * - SUCCESS: TIMx registers are de-initialized
1244 * - ERROR: not applicable
1245 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1246 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1247 {
1248 /* Check the parameters */
1249 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1250 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1251 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1252 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1253 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1254
1255 /* Disable the Channel 2: Reset the CC2E Bit */
1256 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1257
1258 /* Select the Input and set the filter and the prescaler value */
1259 MODIFY_REG(TIMx->CCMR1,
1260 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1261 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1262
1263 /* Select the Polarity and set the CC2E Bit */
1264 MODIFY_REG(TIMx->CCER,
1265 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1266 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1267
1268 return SUCCESS;
1269 }
1270
1271 /**
1272 * @brief Configure the TIMx input channel 3.
1273 * @param TIMx Timer Instance
1274 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1275 * @retval An ErrorStatus enumeration value:
1276 * - SUCCESS: TIMx registers are de-initialized
1277 * - ERROR: not applicable
1278 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1279 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1280 {
1281 /* Check the parameters */
1282 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1283 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1284 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1285 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1286 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1287
1288 /* Disable the Channel 3: Reset the CC3E Bit */
1289 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1290
1291 /* Select the Input and set the filter and the prescaler value */
1292 MODIFY_REG(TIMx->CCMR2,
1293 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1294 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1295
1296 /* Select the Polarity and set the CC3E Bit */
1297 MODIFY_REG(TIMx->CCER,
1298 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1299 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1300
1301 return SUCCESS;
1302 }
1303
1304 /**
1305 * @brief Configure the TIMx input channel 4.
1306 * @param TIMx Timer Instance
1307 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1308 * @retval An ErrorStatus enumeration value:
1309 * - SUCCESS: TIMx registers are de-initialized
1310 * - ERROR: not applicable
1311 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1312 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1313 {
1314 /* Check the parameters */
1315 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1316 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1317 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1318 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1319 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1320
1321 /* Disable the Channel 4: Reset the CC4E Bit */
1322 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1323
1324 /* Select the Input and set the filter and the prescaler value */
1325 MODIFY_REG(TIMx->CCMR2,
1326 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1327 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1328
1329 /* Select the Polarity and set the CC4E Bit */
1330 MODIFY_REG(TIMx->CCER,
1331 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1332 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1333
1334 return SUCCESS;
1335 }
1336
1337
1338 /**
1339 * @}
1340 */
1341
1342 /**
1343 * @}
1344 */
1345
1346 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
1347
1348 /**
1349 * @}
1350 */
1351
1352 #endif /* USE_FULL_LL_DRIVER */
1353
1354
