1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_sram.c
4 * @author MCD Application Team
5 * @brief SRAM HAL module driver.
6 * This file provides a generic firmware to drive SRAM memories
7 * mounted as external device.
8 *
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2017 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 This driver is a generic layered driver which contains a set of APIs used to
26 control SRAM memories. It uses the FMC layer functions to interface
27 with SRAM devices.
28 The following sequence should be followed to configure the FMC to interface
29 with SRAM/PSRAM memories:
30
31 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
32 SRAM_HandleTypeDef hsram; and:
33
34 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
35 values of the structure member.
36
37 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
38 base register instance for NOR or SRAM device
39
40 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
41 base register instance for NOR or SRAM extended mode
42
43 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
44 mode timings; for example:
45 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
46 and fill its fields with the allowed values of the structure member.
47
48 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
49 performs the following sequence:
50
51 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
52 (##) Control register configuration using the FMC NORSRAM interface function
53 FMC_NORSRAM_Init()
54 (##) Timing register configuration using the FMC NORSRAM interface function
55 FMC_NORSRAM_Timing_Init()
56 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
57 FMC_NORSRAM_Extended_Timing_Init()
58 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
59
60 (#) At this stage you can perform read/write accesses from/to the memory connected
61 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
62 following APIs:
63 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
64 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
65
66 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
67 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
68
69 (#) You can continuously monitor the SRAM device HAL state by calling the function
70 HAL_SRAM_GetState()
71
72 *** Callback registration ***
73 =============================================
74 [..]
75 The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
76 allows the user to configure dynamically the driver callbacks.
77
78 Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
79 it allows to register following callbacks:
80 (+) MspInitCallback : SRAM MspInit.
81 (+) MspDeInitCallback : SRAM MspDeInit.
82 This function takes as parameters the HAL peripheral handle, the Callback ID
83 and a pointer to the user callback function.
84
85 Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
86 weak (surcharged) function. It allows to reset following callbacks:
87 (+) MspInitCallback : SRAM MspInit.
88 (+) MspDeInitCallback : SRAM MspDeInit.
89 This function) takes as parameters the HAL peripheral handle and the Callback ID.
90
91 By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
92 all callbacks are reset to the corresponding legacy weak (surcharged) functions.
93 Exception done for MspInit and MspDeInit callbacks that are respectively
94 reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init
95 and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
96 If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
97 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
98
99 Callbacks can be registered/unregistered in READY state only.
100 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
101 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
102 during the Init/DeInit.
103 In that case first register the MspInit/MspDeInit user callbacks
104 using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
105 or HAL_SRAM_Init function.
106
107 When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
108 not defined, the callback registering feature is not available
109 and weak (surcharged) callbacks are used.
110
111 @endverbatim
112 ******************************************************************************
113 */
114
115 /* Includes ------------------------------------------------------------------*/
116 #include "stm32l4xx_hal.h"
117
118 #if defined(FMC_BANK1)
119
120 /** @addtogroup STM32L4xx_HAL_Driver
121 * @{
122 */
123
124 #ifdef HAL_SRAM_MODULE_ENABLED
125
126 /** @defgroup SRAM SRAM
127 * @brief SRAM driver modules
128 * @{
129 */
130
131 /* Private typedef -----------------------------------------------------------*/
132 /* Private define ------------------------------------------------------------*/
133 /* Private macro -------------------------------------------------------------*/
134 /* Private variables ---------------------------------------------------------*/
135 /* Private function prototypes -----------------------------------------------*/
136 static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
137 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
138 static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
139
140 /* Exported functions --------------------------------------------------------*/
141
142 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
143 * @{
144 */
145
146 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
147 * @brief Initialization and Configuration functions.
148 *
149 @verbatim
150 ==============================================================================
151 ##### SRAM Initialization and de_initialization functions #####
152 ==============================================================================
153 [..] This section provides functions allowing to initialize/de-initialize
154 the SRAM memory
155
156 @endverbatim
157 * @{
158 */
159
160 /**
161 * @brief Performs the SRAM device initialization sequence
162 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
163 * the configuration information for SRAM module.
164 * @param Timing Pointer to SRAM control timing structure
165 * @param ExtTiming Pointer to SRAM extended mode timing structure
166 * @retval HAL status
167 */
HAL_SRAM_Init(SRAM_HandleTypeDef * hsram,FMC_NORSRAM_TimingTypeDef * Timing,FMC_NORSRAM_TimingTypeDef * ExtTiming)168 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
169 FMC_NORSRAM_TimingTypeDef *ExtTiming)
170 {
171 /* Check the SRAM handle parameter */
172 if (hsram == NULL)
173 {
174 return HAL_ERROR;
175 }
176
177 if (hsram->State == HAL_SRAM_STATE_RESET)
178 {
179 /* Allocate lock resource and initialize it */
180 hsram->Lock = HAL_UNLOCKED;
181
182 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
183 if (hsram->MspInitCallback == NULL)
184 {
185 hsram->MspInitCallback = HAL_SRAM_MspInit;
186 }
187 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
188 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
189
190 /* Init the low level hardware */
191 hsram->MspInitCallback(hsram);
192 #else
193 /* Initialize the low level hardware (MSP) */
194 HAL_SRAM_MspInit(hsram);
195 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
196 }
197
198 /* Initialize SRAM control Interface */
199 (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
200
201 /* Initialize SRAM timing Interface */
202 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
203
204 /* Initialize SRAM extended mode timing Interface */
205 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
206 hsram->Init.ExtendedMode);
207
208 /* Enable the NORSRAM device */
209 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
210
211 /* Initialize the SRAM controller state */
212 hsram->State = HAL_SRAM_STATE_READY;
213
214 return HAL_OK;
215 }
216
217 /**
218 * @brief Performs the SRAM device De-initialization sequence.
219 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
220 * the configuration information for SRAM module.
221 * @retval HAL status
222 */
HAL_SRAM_DeInit(SRAM_HandleTypeDef * hsram)223 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
224 {
225 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
226 if (hsram->MspDeInitCallback == NULL)
227 {
228 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
229 }
230
231 /* DeInit the low level hardware */
232 hsram->MspDeInitCallback(hsram);
233 #else
234 /* De-Initialize the low level hardware (MSP) */
235 HAL_SRAM_MspDeInit(hsram);
236 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
237
238 /* Configure the SRAM registers with their reset values */
239 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
240
241 /* Reset the SRAM controller state */
242 hsram->State = HAL_SRAM_STATE_RESET;
243
244 /* Release Lock */
245 __HAL_UNLOCK(hsram);
246
247 return HAL_OK;
248 }
249
250 /**
251 * @brief SRAM MSP Init.
252 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
253 * the configuration information for SRAM module.
254 * @retval None
255 */
HAL_SRAM_MspInit(SRAM_HandleTypeDef * hsram)256 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
257 {
258 /* Prevent unused argument(s) compilation warning */
259 UNUSED(hsram);
260
261 /* NOTE : This function Should not be modified, when the callback is needed,
262 the HAL_SRAM_MspInit could be implemented in the user file
263 */
264 }
265
266 /**
267 * @brief SRAM MSP DeInit.
268 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
269 * the configuration information for SRAM module.
270 * @retval None
271 */
HAL_SRAM_MspDeInit(SRAM_HandleTypeDef * hsram)272 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
273 {
274 /* Prevent unused argument(s) compilation warning */
275 UNUSED(hsram);
276
277 /* NOTE : This function Should not be modified, when the callback is needed,
278 the HAL_SRAM_MspDeInit could be implemented in the user file
279 */
280 }
281
282 /**
283 * @brief DMA transfer complete callback.
284 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
285 * the configuration information for SRAM module.
286 * @retval None
287 */
HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef * hdma)288 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
289 {
290 /* Prevent unused argument(s) compilation warning */
291 UNUSED(hdma);
292
293 /* NOTE : This function Should not be modified, when the callback is needed,
294 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
295 */
296 }
297
298 /**
299 * @brief DMA transfer complete error callback.
300 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
301 * the configuration information for SRAM module.
302 * @retval None
303 */
HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef * hdma)304 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
305 {
306 /* Prevent unused argument(s) compilation warning */
307 UNUSED(hdma);
308
309 /* NOTE : This function Should not be modified, when the callback is needed,
310 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
311 */
312 }
313
314 /**
315 * @}
316 */
317
318 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
319 * @brief Input Output and memory control functions
320 *
321 @verbatim
322 ==============================================================================
323 ##### SRAM Input and Output functions #####
324 ==============================================================================
325 [..]
326 This section provides functions allowing to use and control the SRAM memory
327
328 @endverbatim
329 * @{
330 */
331
332 /**
333 * @brief Reads 8-bit buffer from SRAM memory.
334 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
335 * the configuration information for SRAM module.
336 * @param pAddress Pointer to read start address
337 * @param pDstBuffer Pointer to destination buffer
338 * @param BufferSize Size of the buffer to read from memory
339 * @retval HAL status
340 */
HAL_SRAM_Read_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)341 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
342 uint32_t BufferSize)
343 {
344 uint32_t size;
345 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
346 uint8_t *pdestbuff = pDstBuffer;
347 HAL_SRAM_StateTypeDef state = hsram->State;
348
349 /* Check the SRAM controller state */
350 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
351 {
352 /* Process Locked */
353 __HAL_LOCK(hsram);
354
355 /* Update the SRAM controller state */
356 hsram->State = HAL_SRAM_STATE_BUSY;
357
358 /* Read data from memory */
359 for (size = BufferSize; size != 0U; size--)
360 {
361 *pdestbuff = *psramaddress;
362 pdestbuff++;
363 psramaddress++;
364 }
365
366 /* Update the SRAM controller state */
367 hsram->State = state;
368
369 /* Process unlocked */
370 __HAL_UNLOCK(hsram);
371 }
372 else
373 {
374 return HAL_ERROR;
375 }
376
377 return HAL_OK;
378 }
379
380 /**
381 * @brief Writes 8-bit buffer to SRAM memory.
382 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
383 * the configuration information for SRAM module.
384 * @param pAddress Pointer to write start address
385 * @param pSrcBuffer Pointer to source buffer to write
386 * @param BufferSize Size of the buffer to write to memory
387 * @retval HAL status
388 */
HAL_SRAM_Write_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)389 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
390 uint32_t BufferSize)
391 {
392 uint32_t size;
393 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
394 uint8_t *psrcbuff = pSrcBuffer;
395
396 /* Check the SRAM controller state */
397 if (hsram->State == HAL_SRAM_STATE_READY)
398 {
399 /* Process Locked */
400 __HAL_LOCK(hsram);
401
402 /* Update the SRAM controller state */
403 hsram->State = HAL_SRAM_STATE_BUSY;
404
405 /* Write data to memory */
406 for (size = BufferSize; size != 0U; size--)
407 {
408 *psramaddress = *psrcbuff;
409 psrcbuff++;
410 psramaddress++;
411 }
412
413 /* Update the SRAM controller state */
414 hsram->State = HAL_SRAM_STATE_READY;
415
416 /* Process unlocked */
417 __HAL_UNLOCK(hsram);
418 }
419 else
420 {
421 return HAL_ERROR;
422 }
423
424 return HAL_OK;
425 }
426
427 /**
428 * @brief Reads 16-bit buffer from SRAM memory.
429 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
430 * the configuration information for SRAM module.
431 * @param pAddress Pointer to read start address
432 * @param pDstBuffer Pointer to destination buffer
433 * @param BufferSize Size of the buffer to read from memory
434 * @retval HAL status
435 */
HAL_SRAM_Read_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)436 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
437 uint32_t BufferSize)
438 {
439 uint32_t size;
440 __IO uint32_t *psramaddress = pAddress;
441 uint16_t *pdestbuff = pDstBuffer;
442 uint8_t limit;
443 HAL_SRAM_StateTypeDef state = hsram->State;
444
445 /* Check the SRAM controller state */
446 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
447 {
448 /* Process Locked */
449 __HAL_LOCK(hsram);
450
451 /* Update the SRAM controller state */
452 hsram->State = HAL_SRAM_STATE_BUSY;
453
454 /* Check if the size is a 32-bits multiple */
455 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
456
457 /* Read data from memory */
458 for (size = BufferSize; size != limit; size -= 2U)
459 {
460 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
461 pdestbuff++;
462 *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
463 pdestbuff++;
464 psramaddress++;
465 }
466
467 /* Read last 16-bits if size is not 32-bits multiple */
468 if (limit != 0U)
469 {
470 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
471 }
472
473 /* Update the SRAM controller state */
474 hsram->State = state;
475
476 /* Process unlocked */
477 __HAL_UNLOCK(hsram);
478 }
479 else
480 {
481 return HAL_ERROR;
482 }
483
484 return HAL_OK;
485 }
486
487 /**
488 * @brief Writes 16-bit buffer to SRAM memory.
489 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
490 * the configuration information for SRAM module.
491 * @param pAddress Pointer to write start address
492 * @param pSrcBuffer Pointer to source buffer to write
493 * @param BufferSize Size of the buffer to write to memory
494 * @retval HAL status
495 */
HAL_SRAM_Write_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)496 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
497 uint32_t BufferSize)
498 {
499 uint32_t size;
500 __IO uint32_t *psramaddress = pAddress;
501 uint16_t *psrcbuff = pSrcBuffer;
502 uint8_t limit;
503
504 /* Check the SRAM controller state */
505 if (hsram->State == HAL_SRAM_STATE_READY)
506 {
507 /* Process Locked */
508 __HAL_LOCK(hsram);
509
510 /* Update the SRAM controller state */
511 hsram->State = HAL_SRAM_STATE_BUSY;
512
513 /* Check if the size is a 32-bits multiple */
514 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
515
516 /* Write data to memory */
517 for (size = BufferSize; size != limit; size -= 2U)
518 {
519 *psramaddress = (uint32_t)(*psrcbuff);
520 psrcbuff++;
521 *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
522 psrcbuff++;
523 psramaddress++;
524 }
525
526 /* Write last 16-bits if size is not 32-bits multiple */
527 if (limit != 0U)
528 {
529 *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
530 }
531
532 /* Update the SRAM controller state */
533 hsram->State = HAL_SRAM_STATE_READY;
534
535 /* Process unlocked */
536 __HAL_UNLOCK(hsram);
537 }
538 else
539 {
540 return HAL_ERROR;
541 }
542
543 return HAL_OK;
544 }
545
546 /**
547 * @brief Reads 32-bit buffer from SRAM memory.
548 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
549 * the configuration information for SRAM module.
550 * @param pAddress Pointer to read start address
551 * @param pDstBuffer Pointer to destination buffer
552 * @param BufferSize Size of the buffer to read from memory
553 * @retval HAL status
554 */
HAL_SRAM_Read_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)555 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
556 uint32_t BufferSize)
557 {
558 uint32_t size;
559 __IO uint32_t *psramaddress = pAddress;
560 uint32_t *pdestbuff = pDstBuffer;
561 HAL_SRAM_StateTypeDef state = hsram->State;
562
563 /* Check the SRAM controller state */
564 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
565 {
566 /* Process Locked */
567 __HAL_LOCK(hsram);
568
569 /* Update the SRAM controller state */
570 hsram->State = HAL_SRAM_STATE_BUSY;
571
572 /* Read data from memory */
573 for (size = BufferSize; size != 0U; size--)
574 {
575 *pdestbuff = *psramaddress;
576 pdestbuff++;
577 psramaddress++;
578 }
579
580 /* Update the SRAM controller state */
581 hsram->State = state;
582
583 /* Process unlocked */
584 __HAL_UNLOCK(hsram);
585 }
586 else
587 {
588 return HAL_ERROR;
589 }
590
591 return HAL_OK;
592 }
593
594 /**
595 * @brief Writes 32-bit buffer to SRAM memory.
596 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
597 * the configuration information for SRAM module.
598 * @param pAddress Pointer to write start address
599 * @param pSrcBuffer Pointer to source buffer to write
600 * @param BufferSize Size of the buffer to write to memory
601 * @retval HAL status
602 */
HAL_SRAM_Write_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)603 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
604 uint32_t BufferSize)
605 {
606 uint32_t size;
607 __IO uint32_t *psramaddress = pAddress;
608 uint32_t *psrcbuff = pSrcBuffer;
609
610 /* Check the SRAM controller state */
611 if (hsram->State == HAL_SRAM_STATE_READY)
612 {
613 /* Process Locked */
614 __HAL_LOCK(hsram);
615
616 /* Update the SRAM controller state */
617 hsram->State = HAL_SRAM_STATE_BUSY;
618
619 /* Write data to memory */
620 for (size = BufferSize; size != 0U; size--)
621 {
622 *psramaddress = *psrcbuff;
623 psrcbuff++;
624 psramaddress++;
625 }
626
627 /* Update the SRAM controller state */
628 hsram->State = HAL_SRAM_STATE_READY;
629
630 /* Process unlocked */
631 __HAL_UNLOCK(hsram);
632 }
633 else
634 {
635 return HAL_ERROR;
636 }
637
638 return HAL_OK;
639 }
640
641 /**
642 * @brief Reads a Words data from the SRAM memory using DMA transfer.
643 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
644 * the configuration information for SRAM module.
645 * @param pAddress Pointer to read start address
646 * @param pDstBuffer Pointer to destination buffer
647 * @param BufferSize Size of the buffer to read from memory
648 * @retval HAL status
649 */
HAL_SRAM_Read_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)650 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
651 uint32_t BufferSize)
652 {
653 HAL_StatusTypeDef status;
654 HAL_SRAM_StateTypeDef state = hsram->State;
655
656 /* Check the SRAM controller state */
657 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
658 {
659 /* Process Locked */
660 __HAL_LOCK(hsram);
661
662 /* Update the SRAM controller state */
663 hsram->State = HAL_SRAM_STATE_BUSY;
664
665 /* Configure DMA user callbacks */
666 if (state == HAL_SRAM_STATE_READY)
667 {
668 hsram->hdma->XferCpltCallback = SRAM_DMACplt;
669 }
670 else
671 {
672 hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
673 }
674 hsram->hdma->XferErrorCallback = SRAM_DMAError;
675
676 /* Enable the DMA Stream */
677 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
678
679 /* Process unlocked */
680 __HAL_UNLOCK(hsram);
681 }
682 else
683 {
684 status = HAL_ERROR;
685 }
686
687 return status;
688 }
689
690 /**
691 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
692 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
693 * the configuration information for SRAM module.
694 * @param pAddress Pointer to write start address
695 * @param pSrcBuffer Pointer to source buffer to write
696 * @param BufferSize Size of the buffer to write to memory
697 * @retval HAL status
698 */
HAL_SRAM_Write_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)699 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
700 uint32_t BufferSize)
701 {
702 HAL_StatusTypeDef status;
703
704 /* Check the SRAM controller state */
705 if (hsram->State == HAL_SRAM_STATE_READY)
706 {
707 /* Process Locked */
708 __HAL_LOCK(hsram);
709
710 /* Update the SRAM controller state */
711 hsram->State = HAL_SRAM_STATE_BUSY;
712
713 /* Configure DMA user callbacks */
714 hsram->hdma->XferCpltCallback = SRAM_DMACplt;
715 hsram->hdma->XferErrorCallback = SRAM_DMAError;
716
717 /* Enable the DMA Stream */
718 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
719
720 /* Process unlocked */
721 __HAL_UNLOCK(hsram);
722 }
723 else
724 {
725 status = HAL_ERROR;
726 }
727
728 return status;
729 }
730
731 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
732 /**
733 * @brief Register a User SRAM Callback
734 * To be used instead of the weak (surcharged) predefined callback
735 * @param hsram : SRAM handle
736 * @param CallbackId : ID of the callback to be registered
737 * This parameter can be one of the following values:
738 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
739 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
740 * @param pCallback : pointer to the Callback function
741 * @retval status
742 */
HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_CallbackTypeDef pCallback)743 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
744 pSRAM_CallbackTypeDef pCallback)
745 {
746 HAL_StatusTypeDef status = HAL_OK;
747 HAL_SRAM_StateTypeDef state;
748
749 if (pCallback == NULL)
750 {
751 return HAL_ERROR;
752 }
753
754 /* Process locked */
755 __HAL_LOCK(hsram);
756
757 state = hsram->State;
758 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
759 {
760 switch (CallbackId)
761 {
762 case HAL_SRAM_MSP_INIT_CB_ID :
763 hsram->MspInitCallback = pCallback;
764 break;
765 case HAL_SRAM_MSP_DEINIT_CB_ID :
766 hsram->MspDeInitCallback = pCallback;
767 break;
768 default :
769 /* update return status */
770 status = HAL_ERROR;
771 break;
772 }
773 }
774 else
775 {
776 /* update return status */
777 status = HAL_ERROR;
778 }
779
780 /* Release Lock */
781 __HAL_UNLOCK(hsram);
782 return status;
783 }
784
785 /**
786 * @brief Unregister a User SRAM Callback
787 * SRAM Callback is redirected to the weak (surcharged) predefined callback
788 * @param hsram : SRAM handle
789 * @param CallbackId : ID of the callback to be unregistered
790 * This parameter can be one of the following values:
791 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
792 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
793 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
794 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
795 * @retval status
796 */
HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId)797 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
798 {
799 HAL_StatusTypeDef status = HAL_OK;
800 HAL_SRAM_StateTypeDef state;
801
802 /* Process locked */
803 __HAL_LOCK(hsram);
804
805 state = hsram->State;
806 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
807 {
808 switch (CallbackId)
809 {
810 case HAL_SRAM_MSP_INIT_CB_ID :
811 hsram->MspInitCallback = HAL_SRAM_MspInit;
812 break;
813 case HAL_SRAM_MSP_DEINIT_CB_ID :
814 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
815 break;
816 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
817 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
818 break;
819 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
820 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
821 break;
822 default :
823 /* update return status */
824 status = HAL_ERROR;
825 break;
826 }
827 }
828 else if (state == HAL_SRAM_STATE_RESET)
829 {
830 switch (CallbackId)
831 {
832 case HAL_SRAM_MSP_INIT_CB_ID :
833 hsram->MspInitCallback = HAL_SRAM_MspInit;
834 break;
835 case HAL_SRAM_MSP_DEINIT_CB_ID :
836 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
837 break;
838 default :
839 /* update return status */
840 status = HAL_ERROR;
841 break;
842 }
843 }
844 else
845 {
846 /* update return status */
847 status = HAL_ERROR;
848 }
849
850 /* Release Lock */
851 __HAL_UNLOCK(hsram);
852 return status;
853 }
854
855 /**
856 * @brief Register a User SRAM Callback for DMA transfers
857 * To be used instead of the weak (surcharged) predefined callback
858 * @param hsram : SRAM handle
859 * @param CallbackId : ID of the callback to be registered
860 * This parameter can be one of the following values:
861 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
862 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
863 * @param pCallback : pointer to the Callback function
864 * @retval status
865 */
HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_DmaCallbackTypeDef pCallback)866 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
867 pSRAM_DmaCallbackTypeDef pCallback)
868 {
869 HAL_StatusTypeDef status = HAL_OK;
870 HAL_SRAM_StateTypeDef state;
871
872 if (pCallback == NULL)
873 {
874 return HAL_ERROR;
875 }
876
877 /* Process locked */
878 __HAL_LOCK(hsram);
879
880 state = hsram->State;
881 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
882 {
883 switch (CallbackId)
884 {
885 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
886 hsram->DmaXferCpltCallback = pCallback;
887 break;
888 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
889 hsram->DmaXferErrorCallback = pCallback;
890 break;
891 default :
892 /* update return status */
893 status = HAL_ERROR;
894 break;
895 }
896 }
897 else
898 {
899 /* update return status */
900 status = HAL_ERROR;
901 }
902
903 /* Release Lock */
904 __HAL_UNLOCK(hsram);
905 return status;
906 }
907 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
908
909 /**
910 * @}
911 */
912
913 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
914 * @brief Control functions
915 *
916 @verbatim
917 ==============================================================================
918 ##### SRAM Control functions #####
919 ==============================================================================
920 [..]
921 This subsection provides a set of functions allowing to control dynamically
922 the SRAM interface.
923
924 @endverbatim
925 * @{
926 */
927
928 /**
929 * @brief Enables dynamically SRAM write operation.
930 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
931 * the configuration information for SRAM module.
932 * @retval HAL status
933 */
HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef * hsram)934 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
935 {
936 /* Check the SRAM controller state */
937 if (hsram->State == HAL_SRAM_STATE_PROTECTED)
938 {
939 /* Process Locked */
940 __HAL_LOCK(hsram);
941
942 /* Update the SRAM controller state */
943 hsram->State = HAL_SRAM_STATE_BUSY;
944
945 /* Enable write operation */
946 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
947
948 /* Update the SRAM controller state */
949 hsram->State = HAL_SRAM_STATE_READY;
950
951 /* Process unlocked */
952 __HAL_UNLOCK(hsram);
953 }
954 else
955 {
956 return HAL_ERROR;
957 }
958
959 return HAL_OK;
960 }
961
962 /**
963 * @brief Disables dynamically SRAM write operation.
964 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
965 * the configuration information for SRAM module.
966 * @retval HAL status
967 */
HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef * hsram)968 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
969 {
970 /* Check the SRAM controller state */
971 if (hsram->State == HAL_SRAM_STATE_READY)
972 {
973 /* Process Locked */
974 __HAL_LOCK(hsram);
975
976 /* Update the SRAM controller state */
977 hsram->State = HAL_SRAM_STATE_BUSY;
978
979 /* Disable write operation */
980 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
981
982 /* Update the SRAM controller state */
983 hsram->State = HAL_SRAM_STATE_PROTECTED;
984
985 /* Process unlocked */
986 __HAL_UNLOCK(hsram);
987 }
988 else
989 {
990 return HAL_ERROR;
991 }
992
993 return HAL_OK;
994 }
995
996 /**
997 * @}
998 */
999
1000 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
1001 * @brief Peripheral State functions
1002 *
1003 @verbatim
1004 ==============================================================================
1005 ##### SRAM State functions #####
1006 ==============================================================================
1007 [..]
1008 This subsection permits to get in run-time the status of the SRAM controller
1009 and the data flow.
1010
1011 @endverbatim
1012 * @{
1013 */
1014
1015 /**
1016 * @brief Returns the SRAM controller state
1017 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
1018 * the configuration information for SRAM module.
1019 * @retval HAL state
1020 */
HAL_SRAM_GetState(SRAM_HandleTypeDef * hsram)1021 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
1022 {
1023 return hsram->State;
1024 }
1025
1026 /**
1027 * @}
1028 */
1029
1030 /**
1031 * @}
1032 */
1033
1034 /**
1035 * @brief DMA SRAM process complete callback.
1036 * @param hdma : DMA handle
1037 * @retval None
1038 */
SRAM_DMACplt(DMA_HandleTypeDef * hdma)1039 static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
1040 {
1041 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1042
1043 /* Disable the DMA channel */
1044 __HAL_DMA_DISABLE(hdma);
1045
1046 /* Update the SRAM controller state */
1047 hsram->State = HAL_SRAM_STATE_READY;
1048
1049 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1050 hsram->DmaXferCpltCallback(hdma);
1051 #else
1052 HAL_SRAM_DMA_XferCpltCallback(hdma);
1053 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1054 }
1055
1056 /**
1057 * @brief DMA SRAM process complete callback.
1058 * @param hdma : DMA handle
1059 * @retval None
1060 */
SRAM_DMACpltProt(DMA_HandleTypeDef * hdma)1061 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
1062 {
1063 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1064
1065 /* Disable the DMA channel */
1066 __HAL_DMA_DISABLE(hdma);
1067
1068 /* Update the SRAM controller state */
1069 hsram->State = HAL_SRAM_STATE_PROTECTED;
1070
1071 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1072 hsram->DmaXferCpltCallback(hdma);
1073 #else
1074 HAL_SRAM_DMA_XferCpltCallback(hdma);
1075 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1076 }
1077
1078 /**
1079 * @brief DMA SRAM error callback.
1080 * @param hdma : DMA handle
1081 * @retval None
1082 */
SRAM_DMAError(DMA_HandleTypeDef * hdma)1083 static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
1084 {
1085 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1086
1087 /* Disable the DMA channel */
1088 __HAL_DMA_DISABLE(hdma);
1089
1090 /* Update the SRAM controller state */
1091 hsram->State = HAL_SRAM_STATE_ERROR;
1092
1093 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1094 hsram->DmaXferErrorCallback(hdma);
1095 #else
1096 HAL_SRAM_DMA_XferErrorCallback(hdma);
1097 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1098 }
1099
1100 /**
1101 * @}
1102 */
1103
1104 #endif /* HAL_SRAM_MODULE_ENABLED */
1105
1106 /**
1107 * @}
1108 */
1109
1110 #endif /* FMC_BANK1 */
1111
