1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_fsmc.c
4 * @author MCD Application Team
5 * @brief FSMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FSMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2016 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### FSMC peripheral features #####
27 ==============================================================================
28 [..] The Flexible memory controller (FSMC) includes following memory controllers:
29 (+) The NOR/PSRAM memory controller
30
31 [..] The FSMC functional block makes the interface with synchronous and asynchronous static
32 memories. Its main purposes are:
33 (+) to translate AHB transactions into the appropriate external device protocol
34 (+) to meet the access time requirements of the external memory devices
35
36 [..] All external memories share the addresses, data and control signals with the controller.
37 Each external device is accessed by means of a unique Chip Select. The FSMC performs
38 only one access at a time to an external device.
39 The main features of the FSMC controller are the following:
40 (+) Interface with static-memory mapped devices including:
41 (++) Static random access memory (SRAM)
42 (++) Read-only memory (ROM)
43 (++) NOR Flash memory/OneNAND Flash memory
44 (++) PSRAM (4 memory banks)
45 (+) Independent Chip Select control for each memory bank
46 (+) Independent configuration for each memory bank
47
48 @endverbatim
49 ******************************************************************************
50 */
51
52 /* Includes ------------------------------------------------------------------*/
53 #include "stm32l1xx_hal.h"
54
55 /** @addtogroup STM32L1xx_HAL_Driver
56 * @{
57 */
58 #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED)
59
60 /** @defgroup FSMC_LL FSMC Low Layer
61 * @brief FSMC driver modules
62 * @{
63 */
64
65 /* Private typedef -----------------------------------------------------------*/
66 /* Private define ------------------------------------------------------------*/
67
68 /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
69 * @{
70 */
71
72 /* ----------------------- FSMC registers bit mask --------------------------- */
73
74 #if defined(FSMC_BANK1)
75 /* --- BCR Register ---*/
76 /* BCR register clear mask */
77
78 /* --- BTR Register ---*/
79 /* BTR register clear mask */
80 #define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD |\
81 FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
82 FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT |\
83 FSMC_BTRx_ACCMOD))
84
85 /* --- BWTR Register ---*/
86 /* BWTR register clear mask */
87 #define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD |\
88 FSMC_BWTRx_DATAST | FSMC_BWTRx_BUSTURN |\
89 FSMC_BWTRx_ACCMOD))
90 #endif /* FSMC_BANK1 */
91
92 /**
93 * @}
94 */
95
96 /* Private macro -------------------------------------------------------------*/
97 /* Private variables ---------------------------------------------------------*/
98 /* Private function prototypes -----------------------------------------------*/
99 /* Exported functions --------------------------------------------------------*/
100
101 /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
102 * @{
103 */
104
105 #if defined(FSMC_BANK1)
106
107 /** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions
108 * @brief NORSRAM Controller functions
109 *
110 @verbatim
111 ==============================================================================
112 ##### How to use NORSRAM device driver #####
113 ==============================================================================
114
115 [..]
116 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
117 to run the NORSRAM external devices.
118
119 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
120 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
121 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
122 (+) FSMC NORSRAM bank extended timing configuration using the function
123 FSMC_NORSRAM_Extended_Timing_Init()
124 (+) FSMC NORSRAM bank enable/disable write operation using the functions
125 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
126
127 @endverbatim
128 * @{
129 */
130
131 /** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
132 * @brief Initialization and Configuration functions
133 *
134 @verbatim
135 ==============================================================================
136 ##### Initialization and de_initialization functions #####
137 ==============================================================================
138 [..]
139 This section provides functions allowing to:
140 (+) Initialize and configure the FSMC NORSRAM interface
141 (+) De-initialize the FSMC NORSRAM interface
142 (+) Configure the FSMC clock and associated GPIOs
143
144 @endverbatim
145 * @{
146 */
147
148 /**
149 * @brief Initialize the FSMC_NORSRAM device according to the specified
150 * control parameters in the FSMC_NORSRAM_InitTypeDef
151 * @param Device Pointer to NORSRAM device instance
152 * @param Init Pointer to NORSRAM Initialization structure
153 * @retval HAL status
154 */
FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef * Device,FSMC_NORSRAM_InitTypeDef * Init)155 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
156 FSMC_NORSRAM_InitTypeDef *Init)
157 {
158 uint32_t flashaccess;
159 uint32_t btcr_reg;
160 uint32_t mask;
161
162 /* Check the parameters */
163 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
164 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
165 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
166 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
167 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
168 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
169 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
170 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
171 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
172 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
173 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
174 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
175 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
176 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
177 assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
178
179 /* Disable NORSRAM Device */
180 __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
181
182 /* Set NORSRAM device control parameters */
183 if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
184 {
185 flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
186 }
187 else
188 {
189 flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
190 }
191
192 btcr_reg = (flashaccess | \
193 Init->DataAddressMux | \
194 Init->MemoryType | \
195 Init->MemoryDataWidth | \
196 Init->BurstAccessMode | \
197 Init->WaitSignalPolarity | \
198 Init->WaitSignalActive | \
199 Init->WriteOperation | \
200 Init->WaitSignal | \
201 Init->ExtendedMode | \
202 Init->AsynchronousWait | \
203 Init->WriteBurst);
204
205 btcr_reg |= Init->WrapMode;
206 btcr_reg |= Init->PageSize;
207
208 mask = (FSMC_BCRx_MBKEN |
209 FSMC_BCRx_MUXEN |
210 FSMC_BCRx_MTYP |
211 FSMC_BCRx_MWID |
212 FSMC_BCRx_FACCEN |
213 FSMC_BCRx_BURSTEN |
214 FSMC_BCRx_WAITPOL |
215 FSMC_BCRx_WAITCFG |
216 FSMC_BCRx_WREN |
217 FSMC_BCRx_WAITEN |
218 FSMC_BCRx_EXTMOD |
219 FSMC_BCRx_ASYNCWAIT |
220 FSMC_BCRx_CBURSTRW);
221
222 mask |= FSMC_BCRx_WRAPMOD;
223 mask |= FSMC_BCRx_CPSIZE;
224
225 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
226
227
228 return HAL_OK;
229 }
230
231 /**
232 * @brief DeInitialize the FSMC_NORSRAM peripheral
233 * @param Device Pointer to NORSRAM device instance
234 * @param ExDevice Pointer to NORSRAM extended mode device instance
235 * @param Bank NORSRAM bank number
236 * @retval HAL status
237 */
FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef * Device,FSMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)238 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
239 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
240 {
241 /* Check the parameters */
242 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
243 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
244 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
245
246 /* Disable the FSMC_NORSRAM device */
247 __FSMC_NORSRAM_DISABLE(Device, Bank);
248
249 /* De-initialize the FSMC_NORSRAM device */
250 /* FSMC_NORSRAM_BANK1 */
251 if (Bank == FSMC_NORSRAM_BANK1)
252 {
253 Device->BTCR[Bank] = 0x000030DBU;
254 }
255 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
256 else
257 {
258 Device->BTCR[Bank] = 0x000030D2U;
259 }
260
261 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
262 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
263
264 return HAL_OK;
265 }
266
267 /**
268 * @brief Initialize the FSMC_NORSRAM Timing according to the specified
269 * parameters in the FSMC_NORSRAM_TimingTypeDef
270 * @param Device Pointer to NORSRAM device instance
271 * @param Timing Pointer to NORSRAM Timing structure
272 * @param Bank NORSRAM bank number
273 * @retval HAL status
274 */
FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef * Device,FSMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)275 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
276 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
277 {
278
279 /* Check the parameters */
280 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
281 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
282 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
283 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
284 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
285 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
286 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
287 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
288 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
289
290 /* Set FSMC_NORSRAM device timing parameters */
291 MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
292 ((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) |
293 ((Timing->DataSetupTime) << FSMC_BTRx_DATAST_Pos) |
294 ((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) |
295 (((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) |
296 (((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) |
297 (Timing->AccessMode)));
298
299 return HAL_OK;
300 }
301
302 /**
303 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
304 * parameters in the FSMC_NORSRAM_TimingTypeDef
305 * @param Device Pointer to NORSRAM device instance
306 * @param Timing Pointer to NORSRAM Timing structure
307 * @param Bank NORSRAM bank number
308 * @param ExtendedMode FSMC Extended Mode
309 * This parameter can be one of the following values:
310 * @arg FSMC_EXTENDED_MODE_DISABLE
311 * @arg FSMC_EXTENDED_MODE_ENABLE
312 * @retval HAL status
313 */
FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef * Device,FSMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)314 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
315 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
316 uint32_t ExtendedMode)
317 {
318 /* Check the parameters */
319 assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
320
321 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
322 if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
323 {
324 /* Check the parameters */
325 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
326 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
327 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
328 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
329 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
330 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
331 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
332
333 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
334 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
335 ((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) |
336 ((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) |
337 Timing->AccessMode |
338 ((Timing->BusTurnAroundDuration) << FSMC_BWTRx_BUSTURN_Pos)));
339 }
340 else
341 {
342 Device->BWTR[Bank] = 0x0FFFFFFFU;
343 }
344
345 return HAL_OK;
346 }
347 /**
348 * @}
349 */
350
351 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
352 * @brief management functions
353 *
354 @verbatim
355 ==============================================================================
356 ##### FSMC_NORSRAM Control functions #####
357 ==============================================================================
358 [..]
359 This subsection provides a set of functions allowing to control dynamically
360 the FSMC NORSRAM interface.
361
362 @endverbatim
363 * @{
364 */
365
366 /**
367 * @brief Enables dynamically FSMC_NORSRAM write operation.
368 * @param Device Pointer to NORSRAM device instance
369 * @param Bank NORSRAM bank number
370 * @retval HAL status
371 */
FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef * Device,uint32_t Bank)372 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
373 {
374 /* Check the parameters */
375 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
376 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
377
378 /* Enable write operation */
379 SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
380
381 return HAL_OK;
382 }
383
384 /**
385 * @brief Disables dynamically FSMC_NORSRAM write operation.
386 * @param Device Pointer to NORSRAM device instance
387 * @param Bank NORSRAM bank number
388 * @retval HAL status
389 */
FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef * Device,uint32_t Bank)390 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
391 {
392 /* Check the parameters */
393 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
394 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
395
396 /* Disable write operation */
397 CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
398
399 return HAL_OK;
400 }
401
402 /**
403 * @}
404 */
405
406 /**
407 * @}
408 */
409 #endif /* FSMC_BANK1 */
410
411
412
413
414 /**
415 * @}
416 */
417
418 /**
419 * @}
420 */
421
422 #endif /* HAL_NOR_MODULE_ENABLED */
423 /**
424 * @}
425 */
426 /**
427 * @}
428 */
429
