1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32l1xx_ll_dma.h"
22 #include "stm32l1xx_ll_bus.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif
28
29 /** @addtogroup STM32L1xx_LL_Driver
30 * @{
31 */
32
33 #if defined (DMA1) || defined (DMA2)
34
35 /** @defgroup DMA_LL DMA
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 /** @addtogroup DMA_LL_Private_Macros
44 * @{
45 */
46 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
47 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
48 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
49
50 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
51 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
52
53 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
54 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
55
56 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
57 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
58
59 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
60 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
61 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
62
63 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
64 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
65 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
66
67 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
68
69
70 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
71 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
72 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
73 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
74
75 #if defined (DMA2)
76 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
77 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
78 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
79 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
80 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
81 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
82 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
83 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
84 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
85 (((INSTANCE) == DMA2) && \
86 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
87 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
88 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
89 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
90 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
91 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
92 ((CHANNEL) == LL_DMA_CHANNEL_7))))
93 #else
94 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
95 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
96 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
97 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
98 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
99 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
100 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
101 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
102 (((INSTANCE) == DMA2) && \
103 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
104 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
105 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
106 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
107 ((CHANNEL) == LL_DMA_CHANNEL_5))))
108 #endif
109 #else
110 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
111 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
112 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
113 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
114 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
115 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
116 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
117 ((CHANNEL) == LL_DMA_CHANNEL_7))))
118 #endif
119 /**
120 * @}
121 */
122
123 /* Private function prototypes -----------------------------------------------*/
124
125 /* Exported functions --------------------------------------------------------*/
126 /** @addtogroup DMA_LL_Exported_Functions
127 * @{
128 */
129
130 /** @addtogroup DMA_LL_EF_Init
131 * @{
132 */
133
134 /**
135 * @brief De-initialize the DMA registers to their default reset values.
136 * @param DMAx DMAx Instance
137 * @param Channel This parameter can be one of the following values:
138 * @arg @ref LL_DMA_CHANNEL_1
139 * @arg @ref LL_DMA_CHANNEL_2
140 * @arg @ref LL_DMA_CHANNEL_3
141 * @arg @ref LL_DMA_CHANNEL_4
142 * @arg @ref LL_DMA_CHANNEL_5
143 * @arg @ref LL_DMA_CHANNEL_6
144 * @arg @ref LL_DMA_CHANNEL_7
145 * @arg @ref LL_DMA_CHANNEL_ALL
146 * @retval An ErrorStatus enumeration value:
147 * - SUCCESS: DMA registers are de-initialized
148 * - ERROR: DMA registers are not de-initialized
149 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)150 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
151 {
152 DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
153 ErrorStatus status = SUCCESS;
154
155 /* Check the DMA Instance DMAx and Channel parameters*/
156 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
157
158 if (Channel == LL_DMA_CHANNEL_ALL)
159 {
160 if (DMAx == DMA1)
161 {
162 /* Force reset of DMA clock */
163 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
164
165 /* Release reset of DMA clock */
166 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
167 }
168 #if defined(DMA2)
169 else if (DMAx == DMA2)
170 {
171 /* Force reset of DMA clock */
172 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
173
174 /* Release reset of DMA clock */
175 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
176 }
177 #endif
178 else
179 {
180 status = ERROR;
181 }
182 }
183 else
184 {
185 tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
186
187 /* Disable the selected DMAx_Channely */
188 CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
189
190 /* Reset DMAx_Channely control register */
191 LL_DMA_WriteReg(tmp, CCR, 0U);
192
193 /* Reset DMAx_Channely remaining bytes register */
194 LL_DMA_WriteReg(tmp, CNDTR, 0U);
195
196 /* Reset DMAx_Channely peripheral address register */
197 LL_DMA_WriteReg(tmp, CPAR, 0U);
198
199 /* Reset DMAx_Channely memory address register */
200 LL_DMA_WriteReg(tmp, CMAR, 0U);
201
202
203 if (Channel == LL_DMA_CHANNEL_1)
204 {
205 /* Reset interrupt pending bits for DMAx Channel1 */
206 LL_DMA_ClearFlag_GI1(DMAx);
207 }
208 else if (Channel == LL_DMA_CHANNEL_2)
209 {
210 /* Reset interrupt pending bits for DMAx Channel2 */
211 LL_DMA_ClearFlag_GI2(DMAx);
212 }
213 else if (Channel == LL_DMA_CHANNEL_3)
214 {
215 /* Reset interrupt pending bits for DMAx Channel3 */
216 LL_DMA_ClearFlag_GI3(DMAx);
217 }
218 else if (Channel == LL_DMA_CHANNEL_4)
219 {
220 /* Reset interrupt pending bits for DMAx Channel4 */
221 LL_DMA_ClearFlag_GI4(DMAx);
222 }
223 else if (Channel == LL_DMA_CHANNEL_5)
224 {
225 /* Reset interrupt pending bits for DMAx Channel5 */
226 LL_DMA_ClearFlag_GI5(DMAx);
227 }
228
229 else if (Channel == LL_DMA_CHANNEL_6)
230 {
231 /* Reset interrupt pending bits for DMAx Channel6 */
232 LL_DMA_ClearFlag_GI6(DMAx);
233 }
234 else if (Channel == LL_DMA_CHANNEL_7)
235 {
236 /* Reset interrupt pending bits for DMAx Channel7 */
237 LL_DMA_ClearFlag_GI7(DMAx);
238 }
239 else
240 {
241 status = ERROR;
242 }
243 }
244
245 return status;
246 }
247
248 /**
249 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
250 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
251 * @arg @ref __LL_DMA_GET_INSTANCE
252 * @arg @ref __LL_DMA_GET_CHANNEL
253 * @param DMAx DMAx Instance
254 * @param Channel This parameter can be one of the following values:
255 * @arg @ref LL_DMA_CHANNEL_1
256 * @arg @ref LL_DMA_CHANNEL_2
257 * @arg @ref LL_DMA_CHANNEL_3
258 * @arg @ref LL_DMA_CHANNEL_4
259 * @arg @ref LL_DMA_CHANNEL_5
260 * @arg @ref LL_DMA_CHANNEL_6
261 * @arg @ref LL_DMA_CHANNEL_7
262 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
263 * @retval An ErrorStatus enumeration value:
264 * - SUCCESS: DMA registers are initialized
265 * - ERROR: Not applicable
266 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitTypeDef * DMA_InitStruct)267 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
268 {
269 /* Check the DMA Instance DMAx and Channel parameters*/
270 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
271
272 /* Check the DMA parameters from DMA_InitStruct */
273 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
274 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
275 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
276 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
277 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
278 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
279 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
280 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
281
282 /*---------------------------- DMAx CCR Configuration ------------------------
283 * Configure DMAx_Channely: data transfer direction, data transfer mode,
284 * peripheral and memory increment mode,
285 * data size alignment and priority level with parameters :
286 * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
287 * - Mode: DMA_CCR_CIRC bit
288 * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
289 * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
290 * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
291 * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
292 * - Priority: DMA_CCR_PL[1:0] bits
293 */
294 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
295 DMA_InitStruct->Mode | \
296 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
297 DMA_InitStruct->MemoryOrM2MDstIncMode | \
298 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
299 DMA_InitStruct->MemoryOrM2MDstDataSize | \
300 DMA_InitStruct->Priority);
301
302 /*-------------------------- DMAx CMAR Configuration -------------------------
303 * Configure the memory or destination base address with parameter :
304 * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
305 */
306 LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
307
308 /*-------------------------- DMAx CPAR Configuration -------------------------
309 * Configure the peripheral or source base address with parameter :
310 * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
311 */
312 LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
313
314 /*--------------------------- DMAx CNDTR Configuration -----------------------
315 * Configure the peripheral base address with parameter :
316 * - NbData: DMA_CNDTR_NDT[15:0] bits
317 */
318 LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
319
320
321 return SUCCESS;
322 }
323
324 /**
325 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
326 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
327 * @retval None
328 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)329 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
330 {
331 /* Set DMA_InitStruct fields to default values */
332 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
333 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
334 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
335 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
336 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
337 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
338 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
339 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
340 DMA_InitStruct->NbData = 0x00000000U;
341 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
342 }
343
344 /**
345 * @}
346 */
347
348 /**
349 * @}
350 */
351
352 /**
353 * @}
354 */
355
356 #endif /* DMA1 || DMA2 */
357
358 /**
359 * @}
360 */
361
362 #endif /* USE_FULL_LL_DRIVER */
363
364
