1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17 #if defined(USE_FULL_LL_DRIVER)
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32l0xx_ll_rcc.h"
21 #ifdef USE_FULL_ASSERT
22 #include "stm32_assert.h"
23 #else
24 #define assert_param(expr) ((void)0U)
25 #endif /* USE_FULL_ASSERT */
26 /** @addtogroup STM32L0xx_LL_Driver
27 * @{
28 */
29
30 #if defined(RCC)
31
32 /** @defgroup RCC_LL RCC
33 * @{
34 */
35
36 /* Private types -------------------------------------------------------------*/
37 /* Private variables ---------------------------------------------------------*/
38
39 /* Private constants ---------------------------------------------------------*/
40 /* Private macros ------------------------------------------------------------*/
41 /** @addtogroup RCC_LL_Private_Macros
42 * @{
43 */
44 #if defined(RCC_CCIPR_USART1SEL) && defined(RCC_CCIPR_USART2SEL)
45 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
46 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
47 #elif defined(RCC_CCIPR_USART1SEL) && !defined(RCC_CCIPR_USART2SEL)
48 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE))
49 #else
50 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
51 #endif /* RCC_CCIPR_USART1SEL && RCC_CCIPR_USART2SEL */
52
53 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
54
55 #if defined(RCC_CCIPR_I2C3SEL)
56 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
57 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
58 #else
59 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
60 #endif /* RCC_CCIPR_I2C3SEL */
61
62 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)
63
64 #if defined(USB)
65 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
66 #endif /* USB */
67
68 /**
69 * @}
70 */
71
72 /* Private function prototypes -----------------------------------------------*/
73 /** @defgroup RCC_LL_Private_Functions RCC Private functions
74 * @{
75 */
76 static uint32_t RCC_GetSystemClockFreq(void);
77 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
78 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
79 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
80 static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
81 /**
82 * @}
83 */
84
85
86 /* Exported functions --------------------------------------------------------*/
87 /** @addtogroup RCC_LL_Exported_Functions
88 * @{
89 */
90
91 /** @addtogroup RCC_LL_EF_Init
92 * @{
93 */
94
95 /**
96 * @brief Reset the RCC clock configuration to the default reset state.
97 * @note The default reset state of the clock configuration is given below:
98 * - MSI ON and used as system clock source
99 * - HSE, HSI and PLL OFF
100 * - AHB, APB1 and APB2 prescaler set to 1.
101 * - CSS, MCO OFF
102 * - All interrupts disabled
103 * @note This function doesn't modify the configuration of the
104 * - Peripheral clocks
105 * - LSI, LSE and RTC clocks
106 * @retval An ErrorStatus enumeration value:
107 * - SUCCESS: RCC registers are de-initialized
108 * - ERROR: not applicable
109 */
LL_RCC_DeInit(void)110 ErrorStatus LL_RCC_DeInit(void)
111 {
112 __IO uint32_t vl_mask;
113
114 /* Set MSION bit */
115 LL_RCC_MSI_Enable();
116
117 /* Insure MSIRDY bit is set before writing default MSIRANGE value */
118 while (LL_RCC_MSI_IsReady() == 0U)
119 {
120 __NOP();
121 }
122
123 /* Set MSIRANGE default value */
124 LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5);
125 /* Set MSITRIM bits to the reset value*/
126 LL_RCC_MSI_SetCalibTrimming(0U);
127
128 /* Set HSITRIM bits to the reset value*/
129 LL_RCC_HSI_SetCalibTrimming(0x10U);
130
131 /* Reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE bits */
132 vl_mask = 0xFFFFFFFFU;
133 CLEAR_BIT(vl_mask, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | \
134 RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE);
135 LL_RCC_WriteReg(CFGR, vl_mask);
136
137 /* Reset HSI, HSE, PLL */
138 vl_mask = LL_RCC_ReadReg(CR);
139 #if defined(RCC_CR_HSIOUTEN)
140 CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
141 RCC_CR_HSEON | RCC_CR_PLLON);
142 #else
143 CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \
144 RCC_CR_HSEON | RCC_CR_PLLON);
145 #endif
146 LL_RCC_WriteReg(CR, vl_mask);
147 /* Delay after an RCC peripheral clock */
148 vl_mask = LL_RCC_ReadReg(CR);
149
150 /* Reset HSEBYP bit */
151 LL_RCC_HSE_DisableBypass();
152
153 /* Set RCC_CR_RTCPRE to 0b00*/
154 CLEAR_BIT(vl_mask, RCC_CR_RTCPRE);
155 LL_RCC_WriteReg(CR, vl_mask);
156
157 /* Insure PLL is disabled before to reset PLLSRC/PLLMUL/PLLDIV in CFGR register */
158 while(LL_RCC_PLL_IsReady() != 0U) {};
159
160 /* Reset CFGR register */
161 LL_RCC_WriteReg(CFGR, 0x00000000U);
162
163 #if defined(RCC_HSI48_SUPPORT)
164
165 /* Reset CRRCR register to disable HSI48 */
166 #if defined(RCC_CRRCR_HSI48DIV6OUTEN)
167 CLEAR_BIT(RCC->CRRCR, (RCC_CRRCR_HSI48ON | RCC_CRRCR_HSI48DIV6OUTEN));
168 #else
169 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
170 #endif
171
172 #endif /*RCC_HSI48_SUPPORT*/
173
174 /* Disable all interrupts */
175 LL_RCC_WriteReg(CIER, 0x00000000U);
176
177 /* Disable all interrupt flags */
178 LL_RCC_WriteReg(CICR, 0xFFFFFFFFU);
179
180 /* Clear reset flags */
181 LL_RCC_ClearResetFlags();
182
183 return SUCCESS;
184 }
185
186 /**
187 * @}
188 */
189
190 /** @addtogroup RCC_LL_EF_Get_Freq
191 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
192 * and different peripheral clocks available on the device.
193 * @note If SYSCLK source is MSI, function returns values based on MSI clock(*)
194 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
195 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
196 * @note If SYSCLK source is PLL, function returns values based on
197 * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
198 * @note (*) MSI clock depends on the selected MSI range but the real value
199 * may vary depending on the variations in voltage and temperature.
200 * @note (**) HSI_VALUE is a defined constant but the real value may vary
201 * depending on the variations in voltage and temperature.
202 * @note (***) HSE_VALUE is a defined constant, user has to ensure that
203 * HSE_VALUE is same as the real frequency of the crystal used.
204 * Otherwise, this function may have wrong result.
205 * @note The result of this function could be incorrect when using fractional
206 * value for HSE crystal.
207 * @note This function can be used by the user application to compute the
208 * baud-rate for the communication peripherals or configure other parameters.
209 * @{
210 */
211
212 /**
213 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
214 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
215 * must be called to update structure fields. Otherwise, any
216 * configuration based on this function will be incorrect.
217 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
218 * @retval None
219 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)220 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
221 {
222 /* Get SYSCLK frequency */
223 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
224
225 /* HCLK clock frequency */
226 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
227
228 /* PCLK1 clock frequency */
229 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
230
231 /* PCLK2 clock frequency */
232 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
233 }
234
235 /**
236 * @brief Return USARTx clock frequency
237 * @param USARTxSource This parameter can be one of the following values:
238 * @arg @ref LL_RCC_USART1_CLKSOURCE
239 * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
240 *
241 * (*) value not defined in all devices.
242 * @retval USART clock frequency (in Hz)
243 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
244 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)245 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
246 {
247 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
248
249 /* Check parameter */
250 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
251 #if defined(RCC_CCIPR_USART1SEL)
252 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
253 {
254 /* USART1CLK clock frequency */
255 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
256 {
257 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
258 usart_frequency = RCC_GetSystemClockFreq();
259 break;
260
261 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
262 if (LL_RCC_HSI_IsReady() != 0U)
263 {
264 if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
265 {
266 usart_frequency = (HSI_VALUE >> 2U);
267 }
268 else
269 {
270 usart_frequency = HSI_VALUE;
271 }
272 }
273 break;
274
275 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
276 if (LL_RCC_LSE_IsReady() != 0U)
277 {
278 usart_frequency = LSE_VALUE;
279 }
280 break;
281
282 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
283 default:
284 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
285 break;
286 }
287 }
288 #endif /* RCC_CCIPR_USART1SEL */
289
290 #if defined(RCC_CCIPR_USART2SEL)
291 if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
292 {
293 /* USART2CLK clock frequency */
294 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
295 {
296 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
297 usart_frequency = RCC_GetSystemClockFreq();
298 break;
299
300 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
301 if (LL_RCC_HSI_IsReady() != 0U)
302 {
303 if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
304 {
305 usart_frequency = (HSI_VALUE >> 2U);
306 }
307 else
308 {
309 usart_frequency = HSI_VALUE;
310 }
311 }
312 break;
313
314 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
315 if (LL_RCC_LSE_IsReady() != 0U)
316 {
317 usart_frequency = LSE_VALUE;
318 }
319 break;
320
321 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
322 default:
323 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
324 break;
325 }
326 }
327 #endif /* RCC_CCIPR_USART2SEL */
328
329 return usart_frequency;
330 }
331
332 /**
333 * @brief Return I2Cx clock frequency
334 * @param I2CxSource This parameter can be one of the following values:
335 * @arg @ref LL_RCC_I2C1_CLKSOURCE
336 * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
337 *
338 * (*) value not defined in all devices
339 * @retval I2C clock frequency (in Hz)
340 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
341 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)342 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
343 {
344 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
345
346 /* Check parameter */
347 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
348
349 /* I2C1 CLK clock frequency */
350 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
351 {
352 switch (LL_RCC_GetI2CClockSource(I2CxSource))
353 {
354 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
355 i2c_frequency = RCC_GetSystemClockFreq();
356 break;
357
358 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
359 if (LL_RCC_HSI_IsReady() != 0U)
360 {
361 if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
362 {
363 i2c_frequency = (HSI_VALUE >> 2U);
364 }
365 else
366 {
367 i2c_frequency = HSI_VALUE;
368 }
369 }
370 break;
371
372 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
373 default:
374 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
375 break;
376 }
377 }
378
379 #if defined(RCC_CCIPR_I2C3SEL)
380 /* I2C3 CLK clock frequency */
381 if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
382 {
383 switch (LL_RCC_GetI2CClockSource(I2CxSource))
384 {
385 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
386 i2c_frequency = RCC_GetSystemClockFreq();
387 break;
388
389 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
390 if (LL_RCC_HSI_IsReady() != 0U)
391 {
392 if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
393 {
394 i2c_frequency = (HSI_VALUE >> 2U);
395 }
396 else
397 {
398 i2c_frequency = HSI_VALUE;
399 }
400 }
401 break;
402
403 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
404 default:
405 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
406 break;
407 }
408 }
409 #endif /*RCC_CCIPR_I2C3SEL*/
410
411 return i2c_frequency;
412 }
413
414 /**
415 * @brief Return LPUARTx clock frequency
416 * @param LPUARTxSource This parameter can be one of the following values:
417 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
418 * @retval LPUART clock frequency (in Hz)
419 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
420 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)421 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
422 {
423 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
424
425 /* Check parameter */
426 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
427
428 /* LPUART1CLK clock frequency */
429 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
430 {
431 case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
432 lpuart_frequency = RCC_GetSystemClockFreq();
433 break;
434
435 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
436 if (LL_RCC_HSI_IsReady() != 0U)
437 {
438 if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
439 {
440 lpuart_frequency = (HSI_VALUE >> 2U);
441 }
442 else
443 {
444 lpuart_frequency = HSI_VALUE;
445 }
446 }
447 break;
448
449 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
450 if (LL_RCC_LSE_IsReady() != 0U)
451 {
452 lpuart_frequency = LSE_VALUE;
453 }
454 break;
455
456 case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */
457 default:
458 lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
459 break;
460 }
461
462 return lpuart_frequency;
463 }
464
465 /**
466 * @brief Return LPTIMx clock frequency
467 * @param LPTIMxSource This parameter can be one of the following values:
468 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
469 * @retval LPTIM clock frequency (in Hz)
470 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
471 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)472 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
473 {
474 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
475
476 /* Check parameter */
477 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
478
479 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
480 {
481 /* LPTIM1CLK clock frequency */
482 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
483 {
484 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
485 if (LL_RCC_LSI_IsReady() != 0U)
486 {
487 lptim_frequency = LSI_VALUE;
488 }
489 break;
490
491 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
492 if (LL_RCC_HSI_IsReady() != 0U)
493 {
494 if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
495 {
496 lptim_frequency = (HSI_VALUE >> 2U);
497 }
498 else
499 {
500 lptim_frequency = HSI_VALUE;
501 }
502 }
503 break;
504
505 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
506 if (LL_RCC_LSE_IsReady() != 0U)
507 {
508 lptim_frequency = LSE_VALUE;
509 }
510 break;
511
512 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
513 default:
514 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
515 break;
516 }
517 }
518
519 return lptim_frequency;
520 }
521
522 #if defined(USB)
523 /**
524 * @brief Return USBx clock frequency
525 * @param USBxSource This parameter can be one of the following values:
526 * @arg @ref LL_RCC_USB_CLKSOURCE
527 * @retval USB clock frequency (in Hz)
528 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
529 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
530 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)531 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
532 {
533 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
534
535 /* Check parameter */
536 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
537
538 /* USBCLK clock frequency */
539 switch (LL_RCC_GetUSBClockSource(USBxSource))
540 {
541 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
542 if (LL_RCC_PLL_IsReady() != 0U)
543 {
544 usb_frequency = RCC_PLL_GetFreqDomain_SYS();
545 }
546 break;
547
548 case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */
549 default:
550 if (LL_RCC_HSI48_IsReady() != 0U)
551 {
552 usb_frequency = HSI48_VALUE;
553 }
554 break;
555 }
556
557 return usb_frequency;
558 }
559 #endif /* USB */
560
561 /**
562 * @}
563 */
564
565 /**
566 * @}
567 */
568
569 /** @addtogroup RCC_LL_Private_Functions
570 * @{
571 */
572
573 /**
574 * @brief Return SYSTEM clock frequency
575 * @retval SYSTEM clock frequency (in Hz)
576 */
RCC_GetSystemClockFreq(void)577 static uint32_t RCC_GetSystemClockFreq(void)
578 {
579 uint32_t frequency;
580
581 /* Get SYSCLK source -------------------------------------------------------*/
582 switch (LL_RCC_GetSysClkSource())
583 {
584 case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
585 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
586 break;
587
588 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
589 if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
590 {
591 frequency = (HSI_VALUE >> 2U);
592 }
593 else
594 {
595 frequency = HSI_VALUE;
596 }
597 break;
598
599 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
600 frequency = HSE_VALUE;
601 break;
602
603 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
604 frequency = RCC_PLL_GetFreqDomain_SYS();
605 break;
606
607 default:
608 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
609 break;
610 }
611
612 return frequency;
613 }
614
615 /**
616 * @brief Return HCLK clock frequency
617 * @param SYSCLK_Frequency SYSCLK clock frequency
618 * @retval HCLK clock frequency (in Hz)
619 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)620 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
621 {
622 /* HCLK clock frequency */
623 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
624 }
625
626 /**
627 * @brief Return PCLK1 clock frequency
628 * @param HCLK_Frequency HCLK clock frequency
629 * @retval PCLK1 clock frequency (in Hz)
630 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)631 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
632 {
633 /* PCLK1 clock frequency */
634 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
635 }
636
637 /**
638 * @brief Return PCLK2 clock frequency
639 * @param HCLK_Frequency HCLK clock frequency
640 * @retval PCLK2 clock frequency (in Hz)
641 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)642 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
643 {
644 /* PCLK2 clock frequency */
645 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
646 }
647
648 /**
649 * @brief Return PLL clock frequency used for system domain
650 * @retval PLL clock frequency (in Hz)
651 */
RCC_PLL_GetFreqDomain_SYS(void)652 static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
653 {
654 uint32_t pllinputfreq, pllsource;
655
656 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
657
658 /* Get PLL source */
659 pllsource = LL_RCC_PLL_GetMainSource();
660
661 switch (pllsource)
662 {
663 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
664 if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
665 {
666 pllinputfreq = (HSI_VALUE >> 2U);
667 }
668 else
669 {
670 pllinputfreq = HSI_VALUE;
671 }
672 break;
673
674 default: /* HSE used as PLL clock source */
675 pllinputfreq = HSE_VALUE;
676 break;
677 }
678 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider());
679 }
680 /**
681 * @}
682 */
683
684 /**
685 * @}
686 */
687
688 #endif /* defined(RCC) */
689
690 /**
691 * @}
692 */
693
694 #endif /* USE_FULL_LL_DRIVER */
695
696
