1 /**
2 ******************************************************************************
3 * @file stm32l0xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2016 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
88 Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function HAL_TIM_RegisterCallback() to register a callback.
118 HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
142 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
143 (+) TriggerCallback : TIM Trigger Callback.
144 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
145 (+) IC_CaptureCallback : TIM Input Capture Callback.
146 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
147 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
148 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
149 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
150 (+) ErrorCallback : TIM Error Callback.
151
152 [..]
153 By default, after the Init and when the state is HAL_TIM_STATE_RESET
154 all interrupt callbacks are set to the corresponding weak functions:
155 examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
156
157 [..]
158 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
159 functionalities in the Init / DeInit only when these callbacks are null
160 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
161 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
162
163 [..]
164 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
165 Exception done MspInit / MspDeInit that can be registered / unregistered
166 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
167 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
168 In that case first register the MspInit/MspDeInit user callbacks
169 using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
170
171 [..]
172 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
173 not defined, the callback registration feature is not available and all callbacks
174 are set to the corresponding weak functions.
175
176 @endverbatim
177 ******************************************************************************
178 */
179
180 /* Includes ------------------------------------------------------------------*/
181 #include "stm32l0xx_hal.h"
182
183 /** @addtogroup STM32L0xx_HAL_Driver
184 * @{
185 */
186
187 /** @defgroup TIM TIM
188 * @brief TIM HAL module driver
189 * @{
190 */
191
192 #ifdef HAL_TIM_MODULE_ENABLED
193
194 /* Private typedef -----------------------------------------------------------*/
195 /* Private define ------------------------------------------------------------*/
196 /* Private macros ------------------------------------------------------------*/
197 /* Private variables ---------------------------------------------------------*/
198 /* Private function prototypes -----------------------------------------------*/
199 /** @addtogroup TIM_Private_Functions
200 * @{
201 */
202 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
203 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
204 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
205 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
206 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
207 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
208 uint32_t TIM_ICFilter);
209 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
210 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
211 uint32_t TIM_ICFilter);
212 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
213 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
214 uint32_t TIM_ICFilter);
215 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
216 uint32_t TIM_ICFilter);
217 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
218 static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
219 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
220 static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
221 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
222 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
223 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
224 static void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
225 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
226 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
227 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
228 const TIM_SlaveConfigTypeDef *sSlaveConfig);
229 /**
230 * @}
231 */
232 /* Exported functions --------------------------------------------------------*/
233
234 /** @defgroup TIM_Exported_Functions TIM Exported Functions
235 * @{
236 */
237
238 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
239 * @brief Time Base functions
240 *
241 @verbatim
242 ==============================================================================
243 ##### Time Base functions #####
244 ==============================================================================
245 [..]
246 This section provides functions allowing to:
247 (+) Initialize and configure the TIM base.
248 (+) De-initialize the TIM base.
249 (+) Start the Time Base.
250 (+) Stop the Time Base.
251 (+) Start the Time Base and enable interrupt.
252 (+) Stop the Time Base and disable interrupt.
253 (+) Start the Time Base and enable DMA transfer.
254 (+) Stop the Time Base and disable DMA transfer.
255
256 @endverbatim
257 * @{
258 */
259 /**
260 * @brief Initializes the TIM Time base Unit according to the specified
261 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
262 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
263 * requires a timer reset to avoid unexpected direction
264 * due to DIR bit readonly in center aligned mode.
265 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
266 * @param htim TIM Base handle
267 * @retval HAL status
268 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)269 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
270 {
271 /* Check the TIM handle allocation */
272 if (htim == NULL)
273 {
274 return HAL_ERROR;
275 }
276
277 /* Check the parameters */
278 assert_param(IS_TIM_INSTANCE(htim->Instance));
279 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
280 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
281 assert_param(IS_TIM_PERIOD(htim->Init.Period));
282 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
283 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
284
285 if (htim->State == HAL_TIM_STATE_RESET)
286 {
287 /* Allocate lock resource and initialize it */
288 htim->Lock = HAL_UNLOCKED;
289
290 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
291 /* Reset interrupt callbacks to legacy weak callbacks */
292 TIM_ResetCallback(htim);
293
294 if (htim->Base_MspInitCallback == NULL)
295 {
296 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
297 }
298 /* Init the low level hardware : GPIO, CLOCK, NVIC */
299 htim->Base_MspInitCallback(htim);
300 #else
301 /* Init the low level hardware : GPIO, CLOCK, NVIC */
302 HAL_TIM_Base_MspInit(htim);
303 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
304 }
305
306 /* Set the TIM state */
307 htim->State = HAL_TIM_STATE_BUSY;
308
309 /* Set the Time Base configuration */
310 TIM_Base_SetConfig(htim->Instance, &htim->Init);
311
312 /* Initialize the DMA burst operation state */
313 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
314
315 /* Initialize the TIM channels state */
316 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
317
318 /* Initialize the TIM state*/
319 htim->State = HAL_TIM_STATE_READY;
320
321 return HAL_OK;
322 }
323
324 /**
325 * @brief DeInitializes the TIM Base peripheral
326 * @param htim TIM Base handle
327 * @retval HAL status
328 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)329 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
330 {
331 /* Check the parameters */
332 assert_param(IS_TIM_INSTANCE(htim->Instance));
333
334 htim->State = HAL_TIM_STATE_BUSY;
335
336 /* Disable the TIM Peripheral Clock */
337 __HAL_TIM_DISABLE(htim);
338
339 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
340 if (htim->Base_MspDeInitCallback == NULL)
341 {
342 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
343 }
344 /* DeInit the low level hardware */
345 htim->Base_MspDeInitCallback(htim);
346 #else
347 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
348 HAL_TIM_Base_MspDeInit(htim);
349 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
350
351 /* Change the DMA burst operation state */
352 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
353
354 /* Change the TIM channels state */
355 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
356
357 /* Change TIM state */
358 htim->State = HAL_TIM_STATE_RESET;
359
360 /* Release Lock */
361 __HAL_UNLOCK(htim);
362
363 return HAL_OK;
364 }
365
366 /**
367 * @brief Initializes the TIM Base MSP.
368 * @param htim TIM Base handle
369 * @retval None
370 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)371 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
372 {
373 /* Prevent unused argument(s) compilation warning */
374 UNUSED(htim);
375
376 /* NOTE : This function should not be modified, when the callback is needed,
377 the HAL_TIM_Base_MspInit could be implemented in the user file
378 */
379 }
380
381 /**
382 * @brief DeInitializes TIM Base MSP.
383 * @param htim TIM Base handle
384 * @retval None
385 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)386 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
387 {
388 /* Prevent unused argument(s) compilation warning */
389 UNUSED(htim);
390
391 /* NOTE : This function should not be modified, when the callback is needed,
392 the HAL_TIM_Base_MspDeInit could be implemented in the user file
393 */
394 }
395
396
397 /**
398 * @brief Starts the TIM Base generation.
399 * @param htim TIM Base handle
400 * @retval HAL status
401 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)402 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
403 {
404 uint32_t tmpsmcr;
405
406 /* Check the parameters */
407 assert_param(IS_TIM_INSTANCE(htim->Instance));
408
409 /* Check the TIM state */
410 if (htim->State != HAL_TIM_STATE_READY)
411 {
412 return HAL_ERROR;
413 }
414
415 /* Set the TIM state */
416 htim->State = HAL_TIM_STATE_BUSY;
417
418 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
419 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
420 {
421 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
422 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
423 {
424 __HAL_TIM_ENABLE(htim);
425 }
426 }
427 else
428 {
429 __HAL_TIM_ENABLE(htim);
430 }
431
432 /* Return function status */
433 return HAL_OK;
434 }
435
436 /**
437 * @brief Stops the TIM Base generation.
438 * @param htim TIM Base handle
439 * @retval HAL status
440 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)441 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
442 {
443 /* Check the parameters */
444 assert_param(IS_TIM_INSTANCE(htim->Instance));
445
446 /* Disable the Peripheral */
447 __HAL_TIM_DISABLE(htim);
448
449 /* Set the TIM state */
450 htim->State = HAL_TIM_STATE_READY;
451
452 /* Return function status */
453 return HAL_OK;
454 }
455
456 /**
457 * @brief Starts the TIM Base generation in interrupt mode.
458 * @param htim TIM Base handle
459 * @retval HAL status
460 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)461 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
462 {
463 uint32_t tmpsmcr;
464
465 /* Check the parameters */
466 assert_param(IS_TIM_INSTANCE(htim->Instance));
467
468 /* Check the TIM state */
469 if (htim->State != HAL_TIM_STATE_READY)
470 {
471 return HAL_ERROR;
472 }
473
474 /* Set the TIM state */
475 htim->State = HAL_TIM_STATE_BUSY;
476
477 /* Enable the TIM Update interrupt */
478 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
479
480 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
481 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
482 {
483 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
484 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
485 {
486 __HAL_TIM_ENABLE(htim);
487 }
488 }
489 else
490 {
491 __HAL_TIM_ENABLE(htim);
492 }
493
494 /* Return function status */
495 return HAL_OK;
496 }
497
498 /**
499 * @brief Stops the TIM Base generation in interrupt mode.
500 * @param htim TIM Base handle
501 * @retval HAL status
502 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)503 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
504 {
505 /* Check the parameters */
506 assert_param(IS_TIM_INSTANCE(htim->Instance));
507
508 /* Disable the TIM Update interrupt */
509 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
510
511 /* Disable the Peripheral */
512 __HAL_TIM_DISABLE(htim);
513
514 /* Set the TIM state */
515 htim->State = HAL_TIM_STATE_READY;
516
517 /* Return function status */
518 return HAL_OK;
519 }
520
521 /**
522 * @brief Starts the TIM Base generation in DMA mode.
523 * @param htim TIM Base handle
524 * @param pData The source Buffer address.
525 * @param Length The length of data to be transferred from memory to peripheral.
526 * @retval HAL status
527 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,const uint32_t * pData,uint16_t Length)528 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
529 {
530 uint32_t tmpsmcr;
531
532 /* Check the parameters */
533 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
534
535 /* Set the TIM state */
536 if (htim->State == HAL_TIM_STATE_BUSY)
537 {
538 return HAL_BUSY;
539 }
540 else if (htim->State == HAL_TIM_STATE_READY)
541 {
542 if ((pData == NULL) || (Length == 0U))
543 {
544 return HAL_ERROR;
545 }
546 else
547 {
548 htim->State = HAL_TIM_STATE_BUSY;
549 }
550 }
551 else
552 {
553 return HAL_ERROR;
554 }
555
556 /* Set the DMA Period elapsed callbacks */
557 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
558 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
559
560 /* Set the DMA error callback */
561 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
562
563 /* Enable the DMA channel */
564 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
565 Length) != HAL_OK)
566 {
567 /* Return error status */
568 return HAL_ERROR;
569 }
570
571 /* Enable the TIM Update DMA request */
572 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
573
574 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
575 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
576 {
577 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
578 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
579 {
580 __HAL_TIM_ENABLE(htim);
581 }
582 }
583 else
584 {
585 __HAL_TIM_ENABLE(htim);
586 }
587
588 /* Return function status */
589 return HAL_OK;
590 }
591
592 /**
593 * @brief Stops the TIM Base generation in DMA mode.
594 * @param htim TIM Base handle
595 * @retval HAL status
596 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)597 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
598 {
599 /* Check the parameters */
600 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
601
602 /* Disable the TIM Update DMA request */
603 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
604
605 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
606
607 /* Disable the Peripheral */
608 __HAL_TIM_DISABLE(htim);
609
610 /* Set the TIM state */
611 htim->State = HAL_TIM_STATE_READY;
612
613 /* Return function status */
614 return HAL_OK;
615 }
616
617 /**
618 * @}
619 */
620
621 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
622 * @brief TIM Output Compare functions
623 *
624 @verbatim
625 ==============================================================================
626 ##### TIM Output Compare functions #####
627 ==============================================================================
628 [..]
629 This section provides functions allowing to:
630 (+) Initialize and configure the TIM Output Compare.
631 (+) De-initialize the TIM Output Compare.
632 (+) Start the TIM Output Compare.
633 (+) Stop the TIM Output Compare.
634 (+) Start the TIM Output Compare and enable interrupt.
635 (+) Stop the TIM Output Compare and disable interrupt.
636 (+) Start the TIM Output Compare and enable DMA transfer.
637 (+) Stop the TIM Output Compare and disable DMA transfer.
638
639 @endverbatim
640 * @{
641 */
642 /**
643 * @brief Initializes the TIM Output Compare according to the specified
644 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
645 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
646 * requires a timer reset to avoid unexpected direction
647 * due to DIR bit readonly in center aligned mode.
648 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
649 * @param htim TIM Output Compare handle
650 * @retval HAL status
651 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)652 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
653 {
654 /* Check the TIM handle allocation */
655 if (htim == NULL)
656 {
657 return HAL_ERROR;
658 }
659
660 /* Check the parameters */
661 assert_param(IS_TIM_INSTANCE(htim->Instance));
662 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
663 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
664 assert_param(IS_TIM_PERIOD(htim->Init.Period));
665 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
666 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
667
668 if (htim->State == HAL_TIM_STATE_RESET)
669 {
670 /* Allocate lock resource and initialize it */
671 htim->Lock = HAL_UNLOCKED;
672
673 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
674 /* Reset interrupt callbacks to legacy weak callbacks */
675 TIM_ResetCallback(htim);
676
677 if (htim->OC_MspInitCallback == NULL)
678 {
679 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
680 }
681 /* Init the low level hardware : GPIO, CLOCK, NVIC */
682 htim->OC_MspInitCallback(htim);
683 #else
684 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
685 HAL_TIM_OC_MspInit(htim);
686 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
687 }
688
689 /* Set the TIM state */
690 htim->State = HAL_TIM_STATE_BUSY;
691
692 /* Init the base time for the Output Compare */
693 TIM_Base_SetConfig(htim->Instance, &htim->Init);
694
695 /* Initialize the DMA burst operation state */
696 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
697
698 /* Initialize the TIM channels state */
699 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
700
701 /* Initialize the TIM state*/
702 htim->State = HAL_TIM_STATE_READY;
703
704 return HAL_OK;
705 }
706
707 /**
708 * @brief DeInitializes the TIM peripheral
709 * @param htim TIM Output Compare handle
710 * @retval HAL status
711 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)712 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
713 {
714 /* Check the parameters */
715 assert_param(IS_TIM_INSTANCE(htim->Instance));
716
717 htim->State = HAL_TIM_STATE_BUSY;
718
719 /* Disable the TIM Peripheral Clock */
720 __HAL_TIM_DISABLE(htim);
721
722 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
723 if (htim->OC_MspDeInitCallback == NULL)
724 {
725 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
726 }
727 /* DeInit the low level hardware */
728 htim->OC_MspDeInitCallback(htim);
729 #else
730 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
731 HAL_TIM_OC_MspDeInit(htim);
732 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
733
734 /* Change the DMA burst operation state */
735 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
736
737 /* Change the TIM channels state */
738 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
739
740 /* Change TIM state */
741 htim->State = HAL_TIM_STATE_RESET;
742
743 /* Release Lock */
744 __HAL_UNLOCK(htim);
745
746 return HAL_OK;
747 }
748
749 /**
750 * @brief Initializes the TIM Output Compare MSP.
751 * @param htim TIM Output Compare handle
752 * @retval None
753 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)754 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
755 {
756 /* Prevent unused argument(s) compilation warning */
757 UNUSED(htim);
758
759 /* NOTE : This function should not be modified, when the callback is needed,
760 the HAL_TIM_OC_MspInit could be implemented in the user file
761 */
762 }
763
764 /**
765 * @brief DeInitializes TIM Output Compare MSP.
766 * @param htim TIM Output Compare handle
767 * @retval None
768 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)769 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
770 {
771 /* Prevent unused argument(s) compilation warning */
772 UNUSED(htim);
773
774 /* NOTE : This function should not be modified, when the callback is needed,
775 the HAL_TIM_OC_MspDeInit could be implemented in the user file
776 */
777 }
778
779 /**
780 * @brief Starts the TIM Output Compare signal generation.
781 * @param htim TIM Output Compare handle
782 * @param Channel TIM Channel to be enabled
783 * This parameter can be one of the following values:
784 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
785 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
786 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
787 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
788 * @retval HAL status
789 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)790 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
791 {
792 uint32_t tmpsmcr;
793
794 /* Check the parameters */
795 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
796
797 /* Check the TIM channel state */
798 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
799 {
800 return HAL_ERROR;
801 }
802
803 /* Set the TIM channel state */
804 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
805
806 /* Enable the Output compare channel */
807 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
808
809 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
810 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
811 {
812 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
813 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
814 {
815 __HAL_TIM_ENABLE(htim);
816 }
817 }
818 else
819 {
820 __HAL_TIM_ENABLE(htim);
821 }
822
823 /* Return function status */
824 return HAL_OK;
825 }
826
827 /**
828 * @brief Stops the TIM Output Compare signal generation.
829 * @param htim TIM Output Compare handle
830 * @param Channel TIM Channel to be disabled
831 * This parameter can be one of the following values:
832 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
833 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
834 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
835 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
836 * @retval HAL status
837 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)838 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
839 {
840 /* Check the parameters */
841 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
842
843 /* Disable the Output compare channel */
844 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
845
846 /* Disable the Peripheral */
847 __HAL_TIM_DISABLE(htim);
848
849 /* Set the TIM channel state */
850 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
851
852 /* Return function status */
853 return HAL_OK;
854 }
855
856 /**
857 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
858 * @param htim TIM Output Compare handle
859 * @param Channel TIM Channel to be enabled
860 * This parameter can be one of the following values:
861 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
862 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
863 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
864 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
865 * @retval HAL status
866 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)867 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
868 {
869 HAL_StatusTypeDef status = HAL_OK;
870 uint32_t tmpsmcr;
871
872 /* Check the parameters */
873 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
874
875 /* Check the TIM channel state */
876 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
877 {
878 return HAL_ERROR;
879 }
880
881 /* Set the TIM channel state */
882 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
883
884 switch (Channel)
885 {
886 case TIM_CHANNEL_1:
887 {
888 /* Enable the TIM Capture/Compare 1 interrupt */
889 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
890 break;
891 }
892
893 case TIM_CHANNEL_2:
894 {
895 /* Enable the TIM Capture/Compare 2 interrupt */
896 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
897 break;
898 }
899
900 case TIM_CHANNEL_3:
901 {
902 /* Enable the TIM Capture/Compare 3 interrupt */
903 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
904 break;
905 }
906
907 case TIM_CHANNEL_4:
908 {
909 /* Enable the TIM Capture/Compare 4 interrupt */
910 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
911 break;
912 }
913
914 default:
915 status = HAL_ERROR;
916 break;
917 }
918
919 if (status == HAL_OK)
920 {
921 /* Enable the Output compare channel */
922 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
923
924 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
925 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
926 {
927 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
928 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
929 {
930 __HAL_TIM_ENABLE(htim);
931 }
932 }
933 else
934 {
935 __HAL_TIM_ENABLE(htim);
936 }
937 }
938
939 /* Return function status */
940 return status;
941 }
942
943 /**
944 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
945 * @param htim TIM Output Compare handle
946 * @param Channel TIM Channel to be disabled
947 * This parameter can be one of the following values:
948 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
949 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
950 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
951 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
952 * @retval HAL status
953 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)954 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
955 {
956 HAL_StatusTypeDef status = HAL_OK;
957
958 /* Check the parameters */
959 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
960
961 switch (Channel)
962 {
963 case TIM_CHANNEL_1:
964 {
965 /* Disable the TIM Capture/Compare 1 interrupt */
966 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
967 break;
968 }
969
970 case TIM_CHANNEL_2:
971 {
972 /* Disable the TIM Capture/Compare 2 interrupt */
973 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
974 break;
975 }
976
977 case TIM_CHANNEL_3:
978 {
979 /* Disable the TIM Capture/Compare 3 interrupt */
980 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
981 break;
982 }
983
984 case TIM_CHANNEL_4:
985 {
986 /* Disable the TIM Capture/Compare 4 interrupt */
987 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
988 break;
989 }
990
991 default:
992 status = HAL_ERROR;
993 break;
994 }
995
996 if (status == HAL_OK)
997 {
998 /* Disable the Output compare channel */
999 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1000
1001 /* Disable the Peripheral */
1002 __HAL_TIM_DISABLE(htim);
1003
1004 /* Set the TIM channel state */
1005 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1006 }
1007
1008 /* Return function status */
1009 return status;
1010 }
1011
1012 /**
1013 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1014 * @param htim TIM Output Compare handle
1015 * @param Channel TIM Channel to be enabled
1016 * This parameter can be one of the following values:
1017 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1018 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1019 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1020 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1021 * @param pData The source Buffer address.
1022 * @param Length The length of data to be transferred from memory to TIM peripheral
1023 * @retval HAL status
1024 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1025 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1026 uint16_t Length)
1027 {
1028 HAL_StatusTypeDef status = HAL_OK;
1029 uint32_t tmpsmcr;
1030
1031 /* Check the parameters */
1032 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1033
1034 /* Set the TIM channel state */
1035 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1036 {
1037 return HAL_BUSY;
1038 }
1039 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1040 {
1041 if ((pData == NULL) || (Length == 0U))
1042 {
1043 return HAL_ERROR;
1044 }
1045 else
1046 {
1047 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1048 }
1049 }
1050 else
1051 {
1052 return HAL_ERROR;
1053 }
1054
1055 switch (Channel)
1056 {
1057 case TIM_CHANNEL_1:
1058 {
1059 /* Set the DMA compare callbacks */
1060 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1061 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1062
1063 /* Set the DMA error callback */
1064 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1065
1066 /* Enable the DMA channel */
1067 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1068 Length) != HAL_OK)
1069 {
1070 /* Return error status */
1071 return HAL_ERROR;
1072 }
1073
1074 /* Enable the TIM Capture/Compare 1 DMA request */
1075 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1076 break;
1077 }
1078
1079 case TIM_CHANNEL_2:
1080 {
1081 /* Set the DMA compare callbacks */
1082 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1083 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1084
1085 /* Set the DMA error callback */
1086 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1087
1088 /* Enable the DMA channel */
1089 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1090 Length) != HAL_OK)
1091 {
1092 /* Return error status */
1093 return HAL_ERROR;
1094 }
1095
1096 /* Enable the TIM Capture/Compare 2 DMA request */
1097 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1098 break;
1099 }
1100
1101 case TIM_CHANNEL_3:
1102 {
1103 /* Set the DMA compare callbacks */
1104 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1105 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1106
1107 /* Set the DMA error callback */
1108 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1109
1110 /* Enable the DMA channel */
1111 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1112 Length) != HAL_OK)
1113 {
1114 /* Return error status */
1115 return HAL_ERROR;
1116 }
1117 /* Enable the TIM Capture/Compare 3 DMA request */
1118 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1119 break;
1120 }
1121
1122 case TIM_CHANNEL_4:
1123 {
1124 /* Set the DMA compare callbacks */
1125 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1126 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1127
1128 /* Set the DMA error callback */
1129 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1130
1131 /* Enable the DMA channel */
1132 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1133 Length) != HAL_OK)
1134 {
1135 /* Return error status */
1136 return HAL_ERROR;
1137 }
1138 /* Enable the TIM Capture/Compare 4 DMA request */
1139 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1140 break;
1141 }
1142
1143 default:
1144 status = HAL_ERROR;
1145 break;
1146 }
1147
1148 if (status == HAL_OK)
1149 {
1150 /* Enable the Output compare channel */
1151 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1152
1153 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1154 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1155 {
1156 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1157 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1158 {
1159 __HAL_TIM_ENABLE(htim);
1160 }
1161 }
1162 else
1163 {
1164 __HAL_TIM_ENABLE(htim);
1165 }
1166 }
1167
1168 /* Return function status */
1169 return status;
1170 }
1171
1172 /**
1173 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1174 * @param htim TIM Output Compare handle
1175 * @param Channel TIM Channel to be disabled
1176 * This parameter can be one of the following values:
1177 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1178 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1179 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1180 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1181 * @retval HAL status
1182 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1183 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1184 {
1185 HAL_StatusTypeDef status = HAL_OK;
1186
1187 /* Check the parameters */
1188 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1189
1190 switch (Channel)
1191 {
1192 case TIM_CHANNEL_1:
1193 {
1194 /* Disable the TIM Capture/Compare 1 DMA request */
1195 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1196 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1197 break;
1198 }
1199
1200 case TIM_CHANNEL_2:
1201 {
1202 /* Disable the TIM Capture/Compare 2 DMA request */
1203 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1204 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1205 break;
1206 }
1207
1208 case TIM_CHANNEL_3:
1209 {
1210 /* Disable the TIM Capture/Compare 3 DMA request */
1211 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1212 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1213 break;
1214 }
1215
1216 case TIM_CHANNEL_4:
1217 {
1218 /* Disable the TIM Capture/Compare 4 interrupt */
1219 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1220 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1221 break;
1222 }
1223
1224 default:
1225 status = HAL_ERROR;
1226 break;
1227 }
1228
1229 if (status == HAL_OK)
1230 {
1231 /* Disable the Output compare channel */
1232 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1233
1234 /* Disable the Peripheral */
1235 __HAL_TIM_DISABLE(htim);
1236
1237 /* Set the TIM channel state */
1238 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1239 }
1240
1241 /* Return function status */
1242 return status;
1243 }
1244
1245 /**
1246 * @}
1247 */
1248
1249 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1250 * @brief TIM PWM functions
1251 *
1252 @verbatim
1253 ==============================================================================
1254 ##### TIM PWM functions #####
1255 ==============================================================================
1256 [..]
1257 This section provides functions allowing to:
1258 (+) Initialize and configure the TIM PWM.
1259 (+) De-initialize the TIM PWM.
1260 (+) Start the TIM PWM.
1261 (+) Stop the TIM PWM.
1262 (+) Start the TIM PWM and enable interrupt.
1263 (+) Stop the TIM PWM and disable interrupt.
1264 (+) Start the TIM PWM and enable DMA transfer.
1265 (+) Stop the TIM PWM and disable DMA transfer.
1266
1267 @endverbatim
1268 * @{
1269 */
1270 /**
1271 * @brief Initializes the TIM PWM Time Base according to the specified
1272 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1273 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1274 * requires a timer reset to avoid unexpected direction
1275 * due to DIR bit readonly in center aligned mode.
1276 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1277 * @param htim TIM PWM handle
1278 * @retval HAL status
1279 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1280 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1281 {
1282 /* Check the TIM handle allocation */
1283 if (htim == NULL)
1284 {
1285 return HAL_ERROR;
1286 }
1287
1288 /* Check the parameters */
1289 assert_param(IS_TIM_INSTANCE(htim->Instance));
1290 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1291 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1292 assert_param(IS_TIM_PERIOD(htim->Init.Period));
1293 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
1294 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1295
1296 if (htim->State == HAL_TIM_STATE_RESET)
1297 {
1298 /* Allocate lock resource and initialize it */
1299 htim->Lock = HAL_UNLOCKED;
1300
1301 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1302 /* Reset interrupt callbacks to legacy weak callbacks */
1303 TIM_ResetCallback(htim);
1304
1305 if (htim->PWM_MspInitCallback == NULL)
1306 {
1307 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1308 }
1309 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1310 htim->PWM_MspInitCallback(htim);
1311 #else
1312 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1313 HAL_TIM_PWM_MspInit(htim);
1314 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1315 }
1316
1317 /* Set the TIM state */
1318 htim->State = HAL_TIM_STATE_BUSY;
1319
1320 /* Init the base time for the PWM */
1321 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1322
1323 /* Initialize the DMA burst operation state */
1324 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1325
1326 /* Initialize the TIM channels state */
1327 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1328
1329 /* Initialize the TIM state*/
1330 htim->State = HAL_TIM_STATE_READY;
1331
1332 return HAL_OK;
1333 }
1334
1335 /**
1336 * @brief DeInitializes the TIM peripheral
1337 * @param htim TIM PWM handle
1338 * @retval HAL status
1339 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1340 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1341 {
1342 /* Check the parameters */
1343 assert_param(IS_TIM_INSTANCE(htim->Instance));
1344
1345 htim->State = HAL_TIM_STATE_BUSY;
1346
1347 /* Disable the TIM Peripheral Clock */
1348 __HAL_TIM_DISABLE(htim);
1349
1350 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1351 if (htim->PWM_MspDeInitCallback == NULL)
1352 {
1353 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1354 }
1355 /* DeInit the low level hardware */
1356 htim->PWM_MspDeInitCallback(htim);
1357 #else
1358 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1359 HAL_TIM_PWM_MspDeInit(htim);
1360 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1361
1362 /* Change the DMA burst operation state */
1363 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1364
1365 /* Change the TIM channels state */
1366 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1367
1368 /* Change TIM state */
1369 htim->State = HAL_TIM_STATE_RESET;
1370
1371 /* Release Lock */
1372 __HAL_UNLOCK(htim);
1373
1374 return HAL_OK;
1375 }
1376
1377 /**
1378 * @brief Initializes the TIM PWM MSP.
1379 * @param htim TIM PWM handle
1380 * @retval None
1381 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1382 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1383 {
1384 /* Prevent unused argument(s) compilation warning */
1385 UNUSED(htim);
1386
1387 /* NOTE : This function should not be modified, when the callback is needed,
1388 the HAL_TIM_PWM_MspInit could be implemented in the user file
1389 */
1390 }
1391
1392 /**
1393 * @brief DeInitializes TIM PWM MSP.
1394 * @param htim TIM PWM handle
1395 * @retval None
1396 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1397 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1398 {
1399 /* Prevent unused argument(s) compilation warning */
1400 UNUSED(htim);
1401
1402 /* NOTE : This function should not be modified, when the callback is needed,
1403 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1404 */
1405 }
1406
1407 /**
1408 * @brief Starts the PWM signal generation.
1409 * @param htim TIM handle
1410 * @param Channel TIM Channels to be enabled
1411 * This parameter can be one of the following values:
1412 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1413 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1414 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1415 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1416 * @retval HAL status
1417 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1418 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1419 {
1420 uint32_t tmpsmcr;
1421
1422 /* Check the parameters */
1423 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1424
1425 /* Check the TIM channel state */
1426 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1427 {
1428 return HAL_ERROR;
1429 }
1430
1431 /* Set the TIM channel state */
1432 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1433
1434 /* Enable the Capture compare channel */
1435 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1436
1437 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1438 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1439 {
1440 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1441 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1442 {
1443 __HAL_TIM_ENABLE(htim);
1444 }
1445 }
1446 else
1447 {
1448 __HAL_TIM_ENABLE(htim);
1449 }
1450
1451 /* Return function status */
1452 return HAL_OK;
1453 }
1454
1455 /**
1456 * @brief Stops the PWM signal generation.
1457 * @param htim TIM PWM handle
1458 * @param Channel TIM Channels to be disabled
1459 * This parameter can be one of the following values:
1460 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1461 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1462 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1463 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1464 * @retval HAL status
1465 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1466 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1467 {
1468 /* Check the parameters */
1469 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1470
1471 /* Disable the Capture compare channel */
1472 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1473
1474 /* Disable the Peripheral */
1475 __HAL_TIM_DISABLE(htim);
1476
1477 /* Set the TIM channel state */
1478 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1479
1480 /* Return function status */
1481 return HAL_OK;
1482 }
1483
1484 /**
1485 * @brief Starts the PWM signal generation in interrupt mode.
1486 * @param htim TIM PWM handle
1487 * @param Channel TIM Channel to be enabled
1488 * This parameter can be one of the following values:
1489 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1490 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1491 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1492 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1493 * @retval HAL status
1494 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1495 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1496 {
1497 HAL_StatusTypeDef status = HAL_OK;
1498 uint32_t tmpsmcr;
1499
1500 /* Check the parameters */
1501 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1502
1503 /* Check the TIM channel state */
1504 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1505 {
1506 return HAL_ERROR;
1507 }
1508
1509 /* Set the TIM channel state */
1510 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1511
1512 switch (Channel)
1513 {
1514 case TIM_CHANNEL_1:
1515 {
1516 /* Enable the TIM Capture/Compare 1 interrupt */
1517 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1518 break;
1519 }
1520
1521 case TIM_CHANNEL_2:
1522 {
1523 /* Enable the TIM Capture/Compare 2 interrupt */
1524 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1525 break;
1526 }
1527
1528 case TIM_CHANNEL_3:
1529 {
1530 /* Enable the TIM Capture/Compare 3 interrupt */
1531 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1532 break;
1533 }
1534
1535 case TIM_CHANNEL_4:
1536 {
1537 /* Enable the TIM Capture/Compare 4 interrupt */
1538 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1539 break;
1540 }
1541
1542 default:
1543 status = HAL_ERROR;
1544 break;
1545 }
1546
1547 if (status == HAL_OK)
1548 {
1549 /* Enable the Capture compare channel */
1550 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1551
1552 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1553 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1554 {
1555 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1556 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1557 {
1558 __HAL_TIM_ENABLE(htim);
1559 }
1560 }
1561 else
1562 {
1563 __HAL_TIM_ENABLE(htim);
1564 }
1565 }
1566
1567 /* Return function status */
1568 return status;
1569 }
1570
1571 /**
1572 * @brief Stops the PWM signal generation in interrupt mode.
1573 * @param htim TIM PWM handle
1574 * @param Channel TIM Channels to be disabled
1575 * This parameter can be one of the following values:
1576 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1577 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1578 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1579 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1580 * @retval HAL status
1581 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1582 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1583 {
1584 HAL_StatusTypeDef status = HAL_OK;
1585
1586 /* Check the parameters */
1587 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1588
1589 switch (Channel)
1590 {
1591 case TIM_CHANNEL_1:
1592 {
1593 /* Disable the TIM Capture/Compare 1 interrupt */
1594 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1595 break;
1596 }
1597
1598 case TIM_CHANNEL_2:
1599 {
1600 /* Disable the TIM Capture/Compare 2 interrupt */
1601 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1602 break;
1603 }
1604
1605 case TIM_CHANNEL_3:
1606 {
1607 /* Disable the TIM Capture/Compare 3 interrupt */
1608 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1609 break;
1610 }
1611
1612 case TIM_CHANNEL_4:
1613 {
1614 /* Disable the TIM Capture/Compare 4 interrupt */
1615 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1616 break;
1617 }
1618
1619 default:
1620 status = HAL_ERROR;
1621 break;
1622 }
1623
1624 if (status == HAL_OK)
1625 {
1626 /* Disable the Capture compare channel */
1627 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1628
1629 /* Disable the Peripheral */
1630 __HAL_TIM_DISABLE(htim);
1631
1632 /* Set the TIM channel state */
1633 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1634 }
1635
1636 /* Return function status */
1637 return status;
1638 }
1639
1640 /**
1641 * @brief Starts the TIM PWM signal generation in DMA mode.
1642 * @param htim TIM PWM handle
1643 * @param Channel TIM Channels to be enabled
1644 * This parameter can be one of the following values:
1645 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1646 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1647 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1648 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1649 * @param pData The source Buffer address.
1650 * @param Length The length of data to be transferred from memory to TIM peripheral
1651 * @retval HAL status
1652 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1653 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1654 uint16_t Length)
1655 {
1656 HAL_StatusTypeDef status = HAL_OK;
1657 uint32_t tmpsmcr;
1658
1659 /* Check the parameters */
1660 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1661
1662 /* Set the TIM channel state */
1663 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1664 {
1665 return HAL_BUSY;
1666 }
1667 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1668 {
1669 if ((pData == NULL) || (Length == 0U))
1670 {
1671 return HAL_ERROR;
1672 }
1673 else
1674 {
1675 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1676 }
1677 }
1678 else
1679 {
1680 return HAL_ERROR;
1681 }
1682
1683 switch (Channel)
1684 {
1685 case TIM_CHANNEL_1:
1686 {
1687 /* Set the DMA compare callbacks */
1688 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1689 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1690
1691 /* Set the DMA error callback */
1692 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1693
1694 /* Enable the DMA channel */
1695 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1696 Length) != HAL_OK)
1697 {
1698 /* Return error status */
1699 return HAL_ERROR;
1700 }
1701
1702 /* Enable the TIM Capture/Compare 1 DMA request */
1703 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1704 break;
1705 }
1706
1707 case TIM_CHANNEL_2:
1708 {
1709 /* Set the DMA compare callbacks */
1710 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1711 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1712
1713 /* Set the DMA error callback */
1714 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1715
1716 /* Enable the DMA channel */
1717 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1718 Length) != HAL_OK)
1719 {
1720 /* Return error status */
1721 return HAL_ERROR;
1722 }
1723 /* Enable the TIM Capture/Compare 2 DMA request */
1724 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1725 break;
1726 }
1727
1728 case TIM_CHANNEL_3:
1729 {
1730 /* Set the DMA compare callbacks */
1731 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1732 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1733
1734 /* Set the DMA error callback */
1735 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1736
1737 /* Enable the DMA channel */
1738 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1739 Length) != HAL_OK)
1740 {
1741 /* Return error status */
1742 return HAL_ERROR;
1743 }
1744 /* Enable the TIM Output Capture/Compare 3 request */
1745 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1746 break;
1747 }
1748
1749 case TIM_CHANNEL_4:
1750 {
1751 /* Set the DMA compare callbacks */
1752 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1753 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1754
1755 /* Set the DMA error callback */
1756 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1757
1758 /* Enable the DMA channel */
1759 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1760 Length) != HAL_OK)
1761 {
1762 /* Return error status */
1763 return HAL_ERROR;
1764 }
1765 /* Enable the TIM Capture/Compare 4 DMA request */
1766 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1767 break;
1768 }
1769
1770 default:
1771 status = HAL_ERROR;
1772 break;
1773 }
1774
1775 if (status == HAL_OK)
1776 {
1777 /* Enable the Capture compare channel */
1778 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1779
1780 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1781 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1782 {
1783 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1784 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1785 {
1786 __HAL_TIM_ENABLE(htim);
1787 }
1788 }
1789 else
1790 {
1791 __HAL_TIM_ENABLE(htim);
1792 }
1793 }
1794
1795 /* Return function status */
1796 return status;
1797 }
1798
1799 /**
1800 * @brief Stops the TIM PWM signal generation in DMA mode.
1801 * @param htim TIM PWM handle
1802 * @param Channel TIM Channels to be disabled
1803 * This parameter can be one of the following values:
1804 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1805 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1806 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1807 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1808 * @retval HAL status
1809 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1810 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1811 {
1812 HAL_StatusTypeDef status = HAL_OK;
1813
1814 /* Check the parameters */
1815 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1816
1817 switch (Channel)
1818 {
1819 case TIM_CHANNEL_1:
1820 {
1821 /* Disable the TIM Capture/Compare 1 DMA request */
1822 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1823 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1824 break;
1825 }
1826
1827 case TIM_CHANNEL_2:
1828 {
1829 /* Disable the TIM Capture/Compare 2 DMA request */
1830 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1831 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1832 break;
1833 }
1834
1835 case TIM_CHANNEL_3:
1836 {
1837 /* Disable the TIM Capture/Compare 3 DMA request */
1838 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1839 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1840 break;
1841 }
1842
1843 case TIM_CHANNEL_4:
1844 {
1845 /* Disable the TIM Capture/Compare 4 interrupt */
1846 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1847 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1848 break;
1849 }
1850
1851 default:
1852 status = HAL_ERROR;
1853 break;
1854 }
1855
1856 if (status == HAL_OK)
1857 {
1858 /* Disable the Capture compare channel */
1859 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1860
1861 /* Disable the Peripheral */
1862 __HAL_TIM_DISABLE(htim);
1863
1864 /* Set the TIM channel state */
1865 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1866 }
1867
1868 /* Return function status */
1869 return status;
1870 }
1871
1872 /**
1873 * @}
1874 */
1875
1876 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1877 * @brief TIM Input Capture functions
1878 *
1879 @verbatim
1880 ==============================================================================
1881 ##### TIM Input Capture functions #####
1882 ==============================================================================
1883 [..]
1884 This section provides functions allowing to:
1885 (+) Initialize and configure the TIM Input Capture.
1886 (+) De-initialize the TIM Input Capture.
1887 (+) Start the TIM Input Capture.
1888 (+) Stop the TIM Input Capture.
1889 (+) Start the TIM Input Capture and enable interrupt.
1890 (+) Stop the TIM Input Capture and disable interrupt.
1891 (+) Start the TIM Input Capture and enable DMA transfer.
1892 (+) Stop the TIM Input Capture and disable DMA transfer.
1893
1894 @endverbatim
1895 * @{
1896 */
1897 /**
1898 * @brief Initializes the TIM Input Capture Time base according to the specified
1899 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1900 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1901 * requires a timer reset to avoid unexpected direction
1902 * due to DIR bit readonly in center aligned mode.
1903 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1904 * @param htim TIM Input Capture handle
1905 * @retval HAL status
1906 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1907 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1908 {
1909 /* Check the TIM handle allocation */
1910 if (htim == NULL)
1911 {
1912 return HAL_ERROR;
1913 }
1914
1915 /* Check the parameters */
1916 assert_param(IS_TIM_INSTANCE(htim->Instance));
1917 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1918 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1919 assert_param(IS_TIM_PERIOD(htim->Init.Period));
1920 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
1921 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1922
1923 if (htim->State == HAL_TIM_STATE_RESET)
1924 {
1925 /* Allocate lock resource and initialize it */
1926 htim->Lock = HAL_UNLOCKED;
1927
1928 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1929 /* Reset interrupt callbacks to legacy weak callbacks */
1930 TIM_ResetCallback(htim);
1931
1932 if (htim->IC_MspInitCallback == NULL)
1933 {
1934 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
1935 }
1936 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1937 htim->IC_MspInitCallback(htim);
1938 #else
1939 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1940 HAL_TIM_IC_MspInit(htim);
1941 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1942 }
1943
1944 /* Set the TIM state */
1945 htim->State = HAL_TIM_STATE_BUSY;
1946
1947 /* Init the base time for the input capture */
1948 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1949
1950 /* Initialize the DMA burst operation state */
1951 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1952
1953 /* Initialize the TIM channels state */
1954 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1955
1956 /* Initialize the TIM state*/
1957 htim->State = HAL_TIM_STATE_READY;
1958
1959 return HAL_OK;
1960 }
1961
1962 /**
1963 * @brief DeInitializes the TIM peripheral
1964 * @param htim TIM Input Capture handle
1965 * @retval HAL status
1966 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)1967 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1968 {
1969 /* Check the parameters */
1970 assert_param(IS_TIM_INSTANCE(htim->Instance));
1971
1972 htim->State = HAL_TIM_STATE_BUSY;
1973
1974 /* Disable the TIM Peripheral Clock */
1975 __HAL_TIM_DISABLE(htim);
1976
1977 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1978 if (htim->IC_MspDeInitCallback == NULL)
1979 {
1980 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
1981 }
1982 /* DeInit the low level hardware */
1983 htim->IC_MspDeInitCallback(htim);
1984 #else
1985 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1986 HAL_TIM_IC_MspDeInit(htim);
1987 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1988
1989 /* Change the DMA burst operation state */
1990 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1991
1992 /* Change the TIM channels state */
1993 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1994
1995 /* Change TIM state */
1996 htim->State = HAL_TIM_STATE_RESET;
1997
1998 /* Release Lock */
1999 __HAL_UNLOCK(htim);
2000
2001 return HAL_OK;
2002 }
2003
2004 /**
2005 * @brief Initializes the TIM Input Capture MSP.
2006 * @param htim TIM Input Capture handle
2007 * @retval None
2008 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2009 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2010 {
2011 /* Prevent unused argument(s) compilation warning */
2012 UNUSED(htim);
2013
2014 /* NOTE : This function should not be modified, when the callback is needed,
2015 the HAL_TIM_IC_MspInit could be implemented in the user file
2016 */
2017 }
2018
2019 /**
2020 * @brief DeInitializes TIM Input Capture MSP.
2021 * @param htim TIM handle
2022 * @retval None
2023 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2024 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2025 {
2026 /* Prevent unused argument(s) compilation warning */
2027 UNUSED(htim);
2028
2029 /* NOTE : This function should not be modified, when the callback is needed,
2030 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2031 */
2032 }
2033
2034 /**
2035 * @brief Starts the TIM Input Capture measurement.
2036 * @param htim TIM Input Capture handle
2037 * @param Channel TIM Channels to be enabled
2038 * This parameter can be one of the following values:
2039 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2040 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2041 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2042 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2043 * @retval HAL status
2044 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2045 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2046 {
2047 uint32_t tmpsmcr;
2048 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2049
2050 /* Check the parameters */
2051 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2052
2053 /* Check the TIM channel state */
2054 if (channel_state != HAL_TIM_CHANNEL_STATE_READY)
2055 {
2056 return HAL_ERROR;
2057 }
2058
2059 /* Set the TIM channel state */
2060 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2061
2062 /* Enable the Input Capture channel */
2063 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2064
2065 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2066 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2067 {
2068 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2069 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2070 {
2071 __HAL_TIM_ENABLE(htim);
2072 }
2073 }
2074 else
2075 {
2076 __HAL_TIM_ENABLE(htim);
2077 }
2078
2079 /* Return function status */
2080 return HAL_OK;
2081 }
2082
2083 /**
2084 * @brief Stops the TIM Input Capture measurement.
2085 * @param htim TIM Input Capture handle
2086 * @param Channel TIM Channels to be disabled
2087 * This parameter can be one of the following values:
2088 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2089 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2090 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2091 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2092 * @retval HAL status
2093 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2094 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2095 {
2096 /* Check the parameters */
2097 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2098
2099 /* Disable the Input Capture channel */
2100 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2101
2102 /* Disable the Peripheral */
2103 __HAL_TIM_DISABLE(htim);
2104
2105 /* Set the TIM channel state */
2106 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2107
2108 /* Return function status */
2109 return HAL_OK;
2110 }
2111
2112 /**
2113 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2114 * @param htim TIM Input Capture handle
2115 * @param Channel TIM Channels to be enabled
2116 * This parameter can be one of the following values:
2117 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2118 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2119 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2120 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2121 * @retval HAL status
2122 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2123 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2124 {
2125 HAL_StatusTypeDef status = HAL_OK;
2126 uint32_t tmpsmcr;
2127
2128 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2129
2130 /* Check the parameters */
2131 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2132
2133 /* Check the TIM channel state */
2134 if (channel_state != HAL_TIM_CHANNEL_STATE_READY)
2135 {
2136 return HAL_ERROR;
2137 }
2138
2139 /* Set the TIM channel state */
2140 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2141
2142 switch (Channel)
2143 {
2144 case TIM_CHANNEL_1:
2145 {
2146 /* Enable the TIM Capture/Compare 1 interrupt */
2147 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2148 break;
2149 }
2150
2151 case TIM_CHANNEL_2:
2152 {
2153 /* Enable the TIM Capture/Compare 2 interrupt */
2154 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2155 break;
2156 }
2157
2158 case TIM_CHANNEL_3:
2159 {
2160 /* Enable the TIM Capture/Compare 3 interrupt */
2161 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2162 break;
2163 }
2164
2165 case TIM_CHANNEL_4:
2166 {
2167 /* Enable the TIM Capture/Compare 4 interrupt */
2168 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2169 break;
2170 }
2171
2172 default:
2173 status = HAL_ERROR;
2174 break;
2175 }
2176
2177 if (status == HAL_OK)
2178 {
2179 /* Enable the Input Capture channel */
2180 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2181
2182 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2183 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2184 {
2185 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2186 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2187 {
2188 __HAL_TIM_ENABLE(htim);
2189 }
2190 }
2191 else
2192 {
2193 __HAL_TIM_ENABLE(htim);
2194 }
2195 }
2196
2197 /* Return function status */
2198 return status;
2199 }
2200
2201 /**
2202 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2203 * @param htim TIM Input Capture handle
2204 * @param Channel TIM Channels to be disabled
2205 * This parameter can be one of the following values:
2206 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2207 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2208 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2209 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2210 * @retval HAL status
2211 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2212 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2213 {
2214 HAL_StatusTypeDef status = HAL_OK;
2215
2216 /* Check the parameters */
2217 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2218
2219 switch (Channel)
2220 {
2221 case TIM_CHANNEL_1:
2222 {
2223 /* Disable the TIM Capture/Compare 1 interrupt */
2224 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2225 break;
2226 }
2227
2228 case TIM_CHANNEL_2:
2229 {
2230 /* Disable the TIM Capture/Compare 2 interrupt */
2231 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2232 break;
2233 }
2234
2235 case TIM_CHANNEL_3:
2236 {
2237 /* Disable the TIM Capture/Compare 3 interrupt */
2238 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2239 break;
2240 }
2241
2242 case TIM_CHANNEL_4:
2243 {
2244 /* Disable the TIM Capture/Compare 4 interrupt */
2245 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2246 break;
2247 }
2248
2249 default:
2250 status = HAL_ERROR;
2251 break;
2252 }
2253
2254 if (status == HAL_OK)
2255 {
2256 /* Disable the Input Capture channel */
2257 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2258
2259 /* Disable the Peripheral */
2260 __HAL_TIM_DISABLE(htim);
2261
2262 /* Set the TIM channel state */
2263 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2264 }
2265
2266 /* Return function status */
2267 return status;
2268 }
2269
2270 /**
2271 * @brief Starts the TIM Input Capture measurement in DMA mode.
2272 * @param htim TIM Input Capture handle
2273 * @param Channel TIM Channels to be enabled
2274 * This parameter can be one of the following values:
2275 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2276 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2277 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2278 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2279 * @param pData The destination Buffer address.
2280 * @param Length The length of data to be transferred from TIM peripheral to memory.
2281 * @retval HAL status
2282 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2283 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2284 {
2285 HAL_StatusTypeDef status = HAL_OK;
2286 uint32_t tmpsmcr;
2287
2288 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2289
2290 /* Check the parameters */
2291 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2292 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2293
2294 /* Set the TIM channel state */
2295 if (channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2296 {
2297 return HAL_BUSY;
2298 }
2299 if (channel_state == HAL_TIM_CHANNEL_STATE_READY)
2300 {
2301 if ((pData == NULL) || (Length == 0U))
2302 {
2303 return HAL_ERROR;
2304 }
2305 else
2306 {
2307 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2308 }
2309 }
2310 else
2311 {
2312 return HAL_ERROR;
2313 }
2314
2315 /* Enable the Input Capture channel */
2316 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2317
2318 switch (Channel)
2319 {
2320 case TIM_CHANNEL_1:
2321 {
2322 /* Set the DMA capture callbacks */
2323 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2324 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2325
2326 /* Set the DMA error callback */
2327 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2328
2329 /* Enable the DMA channel */
2330 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2331 Length) != HAL_OK)
2332 {
2333 /* Return error status */
2334 return HAL_ERROR;
2335 }
2336 /* Enable the TIM Capture/Compare 1 DMA request */
2337 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2338 break;
2339 }
2340
2341 case TIM_CHANNEL_2:
2342 {
2343 /* Set the DMA capture callbacks */
2344 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2345 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2346
2347 /* Set the DMA error callback */
2348 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2349
2350 /* Enable the DMA channel */
2351 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2352 Length) != HAL_OK)
2353 {
2354 /* Return error status */
2355 return HAL_ERROR;
2356 }
2357 /* Enable the TIM Capture/Compare 2 DMA request */
2358 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2359 break;
2360 }
2361
2362 case TIM_CHANNEL_3:
2363 {
2364 /* Set the DMA capture callbacks */
2365 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2366 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2367
2368 /* Set the DMA error callback */
2369 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2370
2371 /* Enable the DMA channel */
2372 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2373 Length) != HAL_OK)
2374 {
2375 /* Return error status */
2376 return HAL_ERROR;
2377 }
2378 /* Enable the TIM Capture/Compare 3 DMA request */
2379 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2380 break;
2381 }
2382
2383 case TIM_CHANNEL_4:
2384 {
2385 /* Set the DMA capture callbacks */
2386 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2387 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2388
2389 /* Set the DMA error callback */
2390 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2391
2392 /* Enable the DMA channel */
2393 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2394 Length) != HAL_OK)
2395 {
2396 /* Return error status */
2397 return HAL_ERROR;
2398 }
2399 /* Enable the TIM Capture/Compare 4 DMA request */
2400 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2401 break;
2402 }
2403
2404 default:
2405 status = HAL_ERROR;
2406 break;
2407 }
2408
2409 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2410 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2411 {
2412 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2413 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2414 {
2415 __HAL_TIM_ENABLE(htim);
2416 }
2417 }
2418 else
2419 {
2420 __HAL_TIM_ENABLE(htim);
2421 }
2422
2423 /* Return function status */
2424 return status;
2425 }
2426
2427 /**
2428 * @brief Stops the TIM Input Capture measurement in DMA mode.
2429 * @param htim TIM Input Capture handle
2430 * @param Channel TIM Channels to be disabled
2431 * This parameter can be one of the following values:
2432 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2433 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2434 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2435 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2436 * @retval HAL status
2437 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2438 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2439 {
2440 HAL_StatusTypeDef status = HAL_OK;
2441
2442 /* Check the parameters */
2443 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2444 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2445
2446 /* Disable the Input Capture channel */
2447 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2448
2449 switch (Channel)
2450 {
2451 case TIM_CHANNEL_1:
2452 {
2453 /* Disable the TIM Capture/Compare 1 DMA request */
2454 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2455 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2456 break;
2457 }
2458
2459 case TIM_CHANNEL_2:
2460 {
2461 /* Disable the TIM Capture/Compare 2 DMA request */
2462 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2463 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2464 break;
2465 }
2466
2467 case TIM_CHANNEL_3:
2468 {
2469 /* Disable the TIM Capture/Compare 3 DMA request */
2470 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2471 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2472 break;
2473 }
2474
2475 case TIM_CHANNEL_4:
2476 {
2477 /* Disable the TIM Capture/Compare 4 DMA request */
2478 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2479 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2480 break;
2481 }
2482
2483 default:
2484 status = HAL_ERROR;
2485 break;
2486 }
2487
2488 if (status == HAL_OK)
2489 {
2490 /* Disable the Peripheral */
2491 __HAL_TIM_DISABLE(htim);
2492
2493 /* Set the TIM channel state */
2494 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2495 }
2496
2497 /* Return function status */
2498 return status;
2499 }
2500 /**
2501 * @}
2502 */
2503
2504 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2505 * @brief TIM One Pulse functions
2506 *
2507 @verbatim
2508 ==============================================================================
2509 ##### TIM One Pulse functions #####
2510 ==============================================================================
2511 [..]
2512 This section provides functions allowing to:
2513 (+) Initialize and configure the TIM One Pulse.
2514 (+) De-initialize the TIM One Pulse.
2515 (+) Start the TIM One Pulse.
2516 (+) Stop the TIM One Pulse.
2517 (+) Start the TIM One Pulse and enable interrupt.
2518 (+) Stop the TIM One Pulse and disable interrupt.
2519 (+) Start the TIM One Pulse and enable DMA transfer.
2520 (+) Stop the TIM One Pulse and disable DMA transfer.
2521
2522 @endverbatim
2523 * @{
2524 */
2525 /**
2526 * @brief Initializes the TIM One Pulse Time Base according to the specified
2527 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2528 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2529 * requires a timer reset to avoid unexpected direction
2530 * due to DIR bit readonly in center aligned mode.
2531 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2532 * @note When the timer instance is initialized in One Pulse mode, timer
2533 * channels 1 and channel 2 are reserved and cannot be used for other
2534 * purpose.
2535 * @param htim TIM One Pulse handle
2536 * @param OnePulseMode Select the One pulse mode.
2537 * This parameter can be one of the following values:
2538 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2539 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2540 * @retval HAL status
2541 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2542 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2543 {
2544 /* Check the TIM handle allocation */
2545 if (htim == NULL)
2546 {
2547 return HAL_ERROR;
2548 }
2549
2550 /* Check the parameters */
2551 assert_param(IS_TIM_INSTANCE(htim->Instance));
2552 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2553 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2554 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2555 assert_param(IS_TIM_PERIOD(htim->Init.Period));
2556 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
2557 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2558
2559 if (htim->State == HAL_TIM_STATE_RESET)
2560 {
2561 /* Allocate lock resource and initialize it */
2562 htim->Lock = HAL_UNLOCKED;
2563
2564 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2565 /* Reset interrupt callbacks to legacy weak callbacks */
2566 TIM_ResetCallback(htim);
2567
2568 if (htim->OnePulse_MspInitCallback == NULL)
2569 {
2570 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2571 }
2572 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2573 htim->OnePulse_MspInitCallback(htim);
2574 #else
2575 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2576 HAL_TIM_OnePulse_MspInit(htim);
2577 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2578 }
2579
2580 /* Set the TIM state */
2581 htim->State = HAL_TIM_STATE_BUSY;
2582
2583 /* Configure the Time base in the One Pulse Mode */
2584 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2585
2586 /* Reset the OPM Bit */
2587 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2588
2589 /* Configure the OPM Mode */
2590 htim->Instance->CR1 |= OnePulseMode;
2591
2592 /* Initialize the DMA burst operation state */
2593 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2594
2595 /* Initialize the TIM channels state */
2596 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2597 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2598
2599 /* Initialize the TIM state*/
2600 htim->State = HAL_TIM_STATE_READY;
2601
2602 return HAL_OK;
2603 }
2604
2605 /**
2606 * @brief DeInitializes the TIM One Pulse
2607 * @param htim TIM One Pulse handle
2608 * @retval HAL status
2609 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2610 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2611 {
2612 /* Check the parameters */
2613 assert_param(IS_TIM_INSTANCE(htim->Instance));
2614
2615 htim->State = HAL_TIM_STATE_BUSY;
2616
2617 /* Disable the TIM Peripheral Clock */
2618 __HAL_TIM_DISABLE(htim);
2619
2620 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2621 if (htim->OnePulse_MspDeInitCallback == NULL)
2622 {
2623 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2624 }
2625 /* DeInit the low level hardware */
2626 htim->OnePulse_MspDeInitCallback(htim);
2627 #else
2628 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2629 HAL_TIM_OnePulse_MspDeInit(htim);
2630 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2631
2632 /* Change the DMA burst operation state */
2633 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2634
2635 /* Set the TIM channel state */
2636 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2637 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2638
2639 /* Change TIM state */
2640 htim->State = HAL_TIM_STATE_RESET;
2641
2642 /* Release Lock */
2643 __HAL_UNLOCK(htim);
2644
2645 return HAL_OK;
2646 }
2647
2648 /**
2649 * @brief Initializes the TIM One Pulse MSP.
2650 * @param htim TIM One Pulse handle
2651 * @retval None
2652 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2653 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2654 {
2655 /* Prevent unused argument(s) compilation warning */
2656 UNUSED(htim);
2657
2658 /* NOTE : This function should not be modified, when the callback is needed,
2659 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2660 */
2661 }
2662
2663 /**
2664 * @brief DeInitializes TIM One Pulse MSP.
2665 * @param htim TIM One Pulse handle
2666 * @retval None
2667 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2668 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2669 {
2670 /* Prevent unused argument(s) compilation warning */
2671 UNUSED(htim);
2672
2673 /* NOTE : This function should not be modified, when the callback is needed,
2674 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2675 */
2676 }
2677
2678 /**
2679 * @brief Starts the TIM One Pulse signal generation.
2680 * @note Though OutputChannel parameter is deprecated and ignored by the function
2681 * it has been kept to avoid HAL_TIM API compatibility break.
2682 * @note The pulse output channel is determined when calling
2683 * @ref HAL_TIM_OnePulse_ConfigChannel().
2684 * @param htim TIM One Pulse handle
2685 * @param OutputChannel See note above
2686 * @retval HAL status
2687 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2688 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2689 {
2690 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2691 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2692
2693 /* Prevent unused argument(s) compilation warning */
2694 UNUSED(OutputChannel);
2695
2696 /* Check the TIM channels state */
2697 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2698 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2699 {
2700 return HAL_ERROR;
2701 }
2702
2703 /* Set the TIM channels state */
2704 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2705 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2706
2707 /* Enable the Capture compare and the Input Capture channels
2708 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2709 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2710 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2711 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2712
2713 No need to enable the counter, it's enabled automatically by hardware
2714 (the counter starts in response to a stimulus and generate a pulse */
2715
2716 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2717 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2718
2719 /* Return function status */
2720 return HAL_OK;
2721 }
2722
2723 /**
2724 * @brief Stops the TIM One Pulse signal generation.
2725 * @note Though OutputChannel parameter is deprecated and ignored by the function
2726 * it has been kept to avoid HAL_TIM API compatibility break.
2727 * @note The pulse output channel is determined when calling
2728 * @ref HAL_TIM_OnePulse_ConfigChannel().
2729 * @param htim TIM One Pulse handle
2730 * @param OutputChannel See note above
2731 * @retval HAL status
2732 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2733 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2734 {
2735 /* Prevent unused argument(s) compilation warning */
2736 UNUSED(OutputChannel);
2737
2738 /* Disable the Capture compare and the Input Capture channels
2739 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2740 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2741 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2742 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2743
2744 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2745 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2746
2747 /* Disable the Peripheral */
2748 __HAL_TIM_DISABLE(htim);
2749
2750 /* Set the TIM channels state */
2751 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2752 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2753
2754 /* Return function status */
2755 return HAL_OK;
2756 }
2757
2758 /**
2759 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2760 * @note Though OutputChannel parameter is deprecated and ignored by the function
2761 * it has been kept to avoid HAL_TIM API compatibility break.
2762 * @note The pulse output channel is determined when calling
2763 * @ref HAL_TIM_OnePulse_ConfigChannel().
2764 * @param htim TIM One Pulse handle
2765 * @param OutputChannel See note above
2766 * @retval HAL status
2767 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2768 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2769 {
2770 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2771 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2772
2773 /* Prevent unused argument(s) compilation warning */
2774 UNUSED(OutputChannel);
2775
2776 /* Check the TIM channels state */
2777 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2778 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2779 {
2780 return HAL_ERROR;
2781 }
2782
2783 /* Set the TIM channels state */
2784 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2785 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2786
2787 /* Enable the Capture compare and the Input Capture channels
2788 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2789 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2790 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2791 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2792
2793 No need to enable the counter, it's enabled automatically by hardware
2794 (the counter starts in response to a stimulus and generate a pulse */
2795
2796 /* Enable the TIM Capture/Compare 1 interrupt */
2797 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2798
2799 /* Enable the TIM Capture/Compare 2 interrupt */
2800 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2801
2802 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2803 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2804
2805 /* Return function status */
2806 return HAL_OK;
2807 }
2808
2809 /**
2810 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2811 * @note Though OutputChannel parameter is deprecated and ignored by the function
2812 * it has been kept to avoid HAL_TIM API compatibility break.
2813 * @note The pulse output channel is determined when calling
2814 * @ref HAL_TIM_OnePulse_ConfigChannel().
2815 * @param htim TIM One Pulse handle
2816 * @param OutputChannel See note above
2817 * @retval HAL status
2818 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2819 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2820 {
2821 /* Prevent unused argument(s) compilation warning */
2822 UNUSED(OutputChannel);
2823
2824 /* Disable the TIM Capture/Compare 1 interrupt */
2825 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2826
2827 /* Disable the TIM Capture/Compare 2 interrupt */
2828 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2829
2830 /* Disable the Capture compare and the Input Capture channels
2831 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2832 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2833 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2834 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2835 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2836 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2837
2838 /* Disable the Peripheral */
2839 __HAL_TIM_DISABLE(htim);
2840
2841 /* Set the TIM channels state */
2842 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2843 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2844
2845 /* Return function status */
2846 return HAL_OK;
2847 }
2848
2849 /**
2850 * @}
2851 */
2852
2853 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2854 * @brief TIM Encoder functions
2855 *
2856 @verbatim
2857 ==============================================================================
2858 ##### TIM Encoder functions #####
2859 ==============================================================================
2860 [..]
2861 This section provides functions allowing to:
2862 (+) Initialize and configure the TIM Encoder.
2863 (+) De-initialize the TIM Encoder.
2864 (+) Start the TIM Encoder.
2865 (+) Stop the TIM Encoder.
2866 (+) Start the TIM Encoder and enable interrupt.
2867 (+) Stop the TIM Encoder and disable interrupt.
2868 (+) Start the TIM Encoder and enable DMA transfer.
2869 (+) Stop the TIM Encoder and disable DMA transfer.
2870
2871 @endverbatim
2872 * @{
2873 */
2874 /**
2875 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
2876 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2877 * requires a timer reset to avoid unexpected direction
2878 * due to DIR bit readonly in center aligned mode.
2879 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
2880 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
2881 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
2882 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
2883 * @note When the timer instance is initialized in Encoder mode, timer
2884 * channels 1 and channel 2 are reserved and cannot be used for other
2885 * purpose.
2886 * @param htim TIM Encoder Interface handle
2887 * @param sConfig TIM Encoder Interface configuration structure
2888 * @retval HAL status
2889 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,const TIM_Encoder_InitTypeDef * sConfig)2890 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
2891 {
2892 uint32_t tmpsmcr;
2893 uint32_t tmpccmr1;
2894 uint32_t tmpccer;
2895
2896 /* Check the TIM handle allocation */
2897 if (htim == NULL)
2898 {
2899 return HAL_ERROR;
2900 }
2901
2902 /* Check the parameters */
2903 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2904 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2905 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2906 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2907 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2908 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2909 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2910 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
2911 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
2912 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2913 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2914 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2915 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2916 assert_param(IS_TIM_PERIOD(htim->Init.Period));
2917 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
2918
2919 if (htim->State == HAL_TIM_STATE_RESET)
2920 {
2921 /* Allocate lock resource and initialize it */
2922 htim->Lock = HAL_UNLOCKED;
2923
2924 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2925 /* Reset interrupt callbacks to legacy weak callbacks */
2926 TIM_ResetCallback(htim);
2927
2928 if (htim->Encoder_MspInitCallback == NULL)
2929 {
2930 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
2931 }
2932 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2933 htim->Encoder_MspInitCallback(htim);
2934 #else
2935 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2936 HAL_TIM_Encoder_MspInit(htim);
2937 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2938 }
2939
2940 /* Set the TIM state */
2941 htim->State = HAL_TIM_STATE_BUSY;
2942
2943 /* Reset the SMS and ECE bits */
2944 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
2945
2946 /* Configure the Time base in the Encoder Mode */
2947 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2948
2949 /* Get the TIMx SMCR register value */
2950 tmpsmcr = htim->Instance->SMCR;
2951
2952 /* Get the TIMx CCMR1 register value */
2953 tmpccmr1 = htim->Instance->CCMR1;
2954
2955 /* Get the TIMx CCER register value */
2956 tmpccer = htim->Instance->CCER;
2957
2958 /* Set the encoder Mode */
2959 tmpsmcr |= sConfig->EncoderMode;
2960
2961 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2962 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2963 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
2964
2965 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2966 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2967 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2968 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
2969 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
2970
2971 /* Set the TI1 and the TI2 Polarities */
2972 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2973 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2974 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
2975
2976 /* Write to TIMx SMCR */
2977 htim->Instance->SMCR = tmpsmcr;
2978
2979 /* Write to TIMx CCMR1 */
2980 htim->Instance->CCMR1 = tmpccmr1;
2981
2982 /* Write to TIMx CCER */
2983 htim->Instance->CCER = tmpccer;
2984
2985 /* Initialize the DMA burst operation state */
2986 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2987
2988 /* Set the TIM channels state */
2989 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2990 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2991
2992 /* Initialize the TIM state*/
2993 htim->State = HAL_TIM_STATE_READY;
2994
2995 return HAL_OK;
2996 }
2997
2998
2999 /**
3000 * @brief DeInitializes the TIM Encoder interface
3001 * @param htim TIM Encoder Interface handle
3002 * @retval HAL status
3003 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3004 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3005 {
3006 /* Check the parameters */
3007 assert_param(IS_TIM_INSTANCE(htim->Instance));
3008
3009 htim->State = HAL_TIM_STATE_BUSY;
3010
3011 /* Disable the TIM Peripheral Clock */
3012 __HAL_TIM_DISABLE(htim);
3013
3014 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3015 if (htim->Encoder_MspDeInitCallback == NULL)
3016 {
3017 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3018 }
3019 /* DeInit the low level hardware */
3020 htim->Encoder_MspDeInitCallback(htim);
3021 #else
3022 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3023 HAL_TIM_Encoder_MspDeInit(htim);
3024 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3025
3026 /* Change the DMA burst operation state */
3027 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3028
3029 /* Set the TIM channels state */
3030 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3031 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3032
3033 /* Change TIM state */
3034 htim->State = HAL_TIM_STATE_RESET;
3035
3036 /* Release Lock */
3037 __HAL_UNLOCK(htim);
3038
3039 return HAL_OK;
3040 }
3041
3042 /**
3043 * @brief Initializes the TIM Encoder Interface MSP.
3044 * @param htim TIM Encoder Interface handle
3045 * @retval None
3046 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3047 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3048 {
3049 /* Prevent unused argument(s) compilation warning */
3050 UNUSED(htim);
3051
3052 /* NOTE : This function should not be modified, when the callback is needed,
3053 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3054 */
3055 }
3056
3057 /**
3058 * @brief DeInitializes TIM Encoder Interface MSP.
3059 * @param htim TIM Encoder Interface handle
3060 * @retval None
3061 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3062 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3063 {
3064 /* Prevent unused argument(s) compilation warning */
3065 UNUSED(htim);
3066
3067 /* NOTE : This function should not be modified, when the callback is needed,
3068 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3069 */
3070 }
3071
3072 /**
3073 * @brief Starts the TIM Encoder Interface.
3074 * @param htim TIM Encoder Interface handle
3075 * @param Channel TIM Channels to be enabled
3076 * This parameter can be one of the following values:
3077 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3078 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3079 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3080 * @retval HAL status
3081 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3082 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3083 {
3084 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3085 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3086
3087 /* Check the parameters */
3088 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3089
3090 /* Set the TIM channel(s) state */
3091 if (Channel == TIM_CHANNEL_1)
3092 {
3093 if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3094 {
3095 return HAL_ERROR;
3096 }
3097 else
3098 {
3099 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3100 }
3101 }
3102 else if (Channel == TIM_CHANNEL_2)
3103 {
3104 if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3105 {
3106 return HAL_ERROR;
3107 }
3108 else
3109 {
3110 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3111 }
3112 }
3113 else
3114 {
3115 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3116 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3117 {
3118 return HAL_ERROR;
3119 }
3120 else
3121 {
3122 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3123 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3124 }
3125 }
3126
3127 /* Enable the encoder interface channels */
3128 switch (Channel)
3129 {
3130 case TIM_CHANNEL_1:
3131 {
3132 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3133 break;
3134 }
3135
3136 case TIM_CHANNEL_2:
3137 {
3138 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3139 break;
3140 }
3141
3142 default :
3143 {
3144 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3145 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3146 break;
3147 }
3148 }
3149 /* Enable the Peripheral */
3150 __HAL_TIM_ENABLE(htim);
3151
3152 /* Return function status */
3153 return HAL_OK;
3154 }
3155
3156 /**
3157 * @brief Stops the TIM Encoder Interface.
3158 * @param htim TIM Encoder Interface handle
3159 * @param Channel TIM Channels to be disabled
3160 * This parameter can be one of the following values:
3161 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3162 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3163 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3164 * @retval HAL status
3165 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3166 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3167 {
3168 /* Check the parameters */
3169 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3170
3171 /* Disable the Input Capture channels 1 and 2
3172 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3173 switch (Channel)
3174 {
3175 case TIM_CHANNEL_1:
3176 {
3177 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3178 break;
3179 }
3180
3181 case TIM_CHANNEL_2:
3182 {
3183 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3184 break;
3185 }
3186
3187 default :
3188 {
3189 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3190 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3191 break;
3192 }
3193 }
3194
3195 /* Disable the Peripheral */
3196 __HAL_TIM_DISABLE(htim);
3197
3198 /* Set the TIM channel(s) state */
3199 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3200 {
3201 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3202 }
3203 else
3204 {
3205 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3206 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3207 }
3208
3209 /* Return function status */
3210 return HAL_OK;
3211 }
3212
3213 /**
3214 * @brief Starts the TIM Encoder Interface in interrupt mode.
3215 * @param htim TIM Encoder Interface handle
3216 * @param Channel TIM Channels to be enabled
3217 * This parameter can be one of the following values:
3218 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3219 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3220 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3221 * @retval HAL status
3222 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3223 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3224 {
3225 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3226 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3227
3228 /* Check the parameters */
3229 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3230
3231 /* Set the TIM channel(s) state */
3232 if (Channel == TIM_CHANNEL_1)
3233 {
3234 if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3235 {
3236 return HAL_ERROR;
3237 }
3238 else
3239 {
3240 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3241 }
3242 }
3243 else if (Channel == TIM_CHANNEL_2)
3244 {
3245 if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3246 {
3247 return HAL_ERROR;
3248 }
3249 else
3250 {
3251 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3252 }
3253 }
3254 else
3255 {
3256 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3257 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3258 {
3259 return HAL_ERROR;
3260 }
3261 else
3262 {
3263 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3264 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3265 }
3266 }
3267
3268 /* Enable the encoder interface channels */
3269 /* Enable the capture compare Interrupts 1 and/or 2 */
3270 switch (Channel)
3271 {
3272 case TIM_CHANNEL_1:
3273 {
3274 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3275 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3276 break;
3277 }
3278
3279 case TIM_CHANNEL_2:
3280 {
3281 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3282 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3283 break;
3284 }
3285
3286 default :
3287 {
3288 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3289 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3290 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3291 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3292 break;
3293 }
3294 }
3295
3296 /* Enable the Peripheral */
3297 __HAL_TIM_ENABLE(htim);
3298
3299 /* Return function status */
3300 return HAL_OK;
3301 }
3302
3303 /**
3304 * @brief Stops the TIM Encoder Interface in interrupt mode.
3305 * @param htim TIM Encoder Interface handle
3306 * @param Channel TIM Channels to be disabled
3307 * This parameter can be one of the following values:
3308 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3309 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3310 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3311 * @retval HAL status
3312 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3313 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3314 {
3315 /* Check the parameters */
3316 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3317
3318 /* Disable the Input Capture channels 1 and 2
3319 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3320 if (Channel == TIM_CHANNEL_1)
3321 {
3322 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3323
3324 /* Disable the capture compare Interrupts 1 */
3325 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3326 }
3327 else if (Channel == TIM_CHANNEL_2)
3328 {
3329 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3330
3331 /* Disable the capture compare Interrupts 2 */
3332 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3333 }
3334 else
3335 {
3336 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3337 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3338
3339 /* Disable the capture compare Interrupts 1 and 2 */
3340 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3341 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3342 }
3343
3344 /* Disable the Peripheral */
3345 __HAL_TIM_DISABLE(htim);
3346
3347 /* Set the TIM channel(s) state */
3348 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3349 {
3350 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3351 }
3352 else
3353 {
3354 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3355 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3356 }
3357
3358 /* Return function status */
3359 return HAL_OK;
3360 }
3361
3362 /**
3363 * @brief Starts the TIM Encoder Interface in DMA mode.
3364 * @param htim TIM Encoder Interface handle
3365 * @param Channel TIM Channels to be enabled
3366 * This parameter can be one of the following values:
3367 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3368 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3369 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3370 * @param pData1 The destination Buffer address for IC1.
3371 * @param pData2 The destination Buffer address for IC2.
3372 * @param Length The length of data to be transferred from TIM peripheral to memory.
3373 * @retval HAL status
3374 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3375 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3376 uint32_t *pData2, uint16_t Length)
3377 {
3378 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3379 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3380
3381 /* Check the parameters */
3382 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3383
3384 /* Set the TIM channel(s) state */
3385 if (Channel == TIM_CHANNEL_1)
3386 {
3387 if (channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3388 {
3389 return HAL_BUSY;
3390 }
3391 else if (channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3392 {
3393 if ((pData1 == NULL) || (Length == 0U))
3394 {
3395 return HAL_ERROR;
3396 }
3397 else
3398 {
3399 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3400 }
3401 }
3402 else
3403 {
3404 return HAL_ERROR;
3405 }
3406 }
3407 else if (Channel == TIM_CHANNEL_2)
3408 {
3409 if (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3410 {
3411 return HAL_BUSY;
3412 }
3413 else if (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3414 {
3415 if ((pData2 == NULL) || (Length == 0U))
3416 {
3417 return HAL_ERROR;
3418 }
3419 else
3420 {
3421 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3422 }
3423 }
3424 else
3425 {
3426 return HAL_ERROR;
3427 }
3428 }
3429 else
3430 {
3431 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3432 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3433 {
3434 return HAL_BUSY;
3435 }
3436 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3437 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3438 {
3439 if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3440 {
3441 return HAL_ERROR;
3442 }
3443 else
3444 {
3445 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3446 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3447 }
3448 }
3449 else
3450 {
3451 return HAL_ERROR;
3452 }
3453 }
3454
3455 switch (Channel)
3456 {
3457 case TIM_CHANNEL_1:
3458 {
3459 /* Set the DMA capture callbacks */
3460 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3461 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3462
3463 /* Set the DMA error callback */
3464 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3465
3466 /* Enable the DMA channel */
3467 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3468 Length) != HAL_OK)
3469 {
3470 /* Return error status */
3471 return HAL_ERROR;
3472 }
3473 /* Enable the TIM Input Capture DMA request */
3474 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3475
3476 /* Enable the Capture compare channel */
3477 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3478
3479 /* Enable the Peripheral */
3480 __HAL_TIM_ENABLE(htim);
3481
3482 break;
3483 }
3484
3485 case TIM_CHANNEL_2:
3486 {
3487 /* Set the DMA capture callbacks */
3488 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3489 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3490
3491 /* Set the DMA error callback */
3492 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3493 /* Enable the DMA channel */
3494 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3495 Length) != HAL_OK)
3496 {
3497 /* Return error status */
3498 return HAL_ERROR;
3499 }
3500 /* Enable the TIM Input Capture DMA request */
3501 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3502
3503 /* Enable the Capture compare channel */
3504 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3505
3506 /* Enable the Peripheral */
3507 __HAL_TIM_ENABLE(htim);
3508
3509 break;
3510 }
3511
3512 default:
3513 {
3514 /* Set the DMA capture callbacks */
3515 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3516 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3517
3518 /* Set the DMA error callback */
3519 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3520
3521 /* Enable the DMA channel */
3522 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3523 Length) != HAL_OK)
3524 {
3525 /* Return error status */
3526 return HAL_ERROR;
3527 }
3528
3529 /* Set the DMA capture callbacks */
3530 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3531 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3532
3533 /* Set the DMA error callback */
3534 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3535
3536 /* Enable the DMA channel */
3537 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3538 Length) != HAL_OK)
3539 {
3540 /* Return error status */
3541 return HAL_ERROR;
3542 }
3543
3544 /* Enable the TIM Input Capture DMA request */
3545 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3546 /* Enable the TIM Input Capture DMA request */
3547 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3548
3549 /* Enable the Capture compare channel */
3550 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3551 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3552
3553 /* Enable the Peripheral */
3554 __HAL_TIM_ENABLE(htim);
3555
3556 break;
3557 }
3558 }
3559
3560 /* Return function status */
3561 return HAL_OK;
3562 }
3563
3564 /**
3565 * @brief Stops the TIM Encoder Interface in DMA mode.
3566 * @param htim TIM Encoder Interface handle
3567 * @param Channel TIM Channels to be enabled
3568 * This parameter can be one of the following values:
3569 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3570 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3571 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3572 * @retval HAL status
3573 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3574 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3575 {
3576 /* Check the parameters */
3577 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3578
3579 /* Disable the Input Capture channels 1 and 2
3580 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3581 if (Channel == TIM_CHANNEL_1)
3582 {
3583 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3584
3585 /* Disable the capture compare DMA Request 1 */
3586 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3587 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3588 }
3589 else if (Channel == TIM_CHANNEL_2)
3590 {
3591 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3592
3593 /* Disable the capture compare DMA Request 2 */
3594 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3595 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3596 }
3597 else
3598 {
3599 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3600 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3601
3602 /* Disable the capture compare DMA Request 1 and 2 */
3603 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3604 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3605 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3606 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3607 }
3608
3609 /* Disable the Peripheral */
3610 __HAL_TIM_DISABLE(htim);
3611
3612 /* Set the TIM channel(s) state */
3613 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3614 {
3615 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3616 }
3617 else
3618 {
3619 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3620 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3621 }
3622
3623 /* Return function status */
3624 return HAL_OK;
3625 }
3626
3627 /**
3628 * @}
3629 */
3630 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3631 * @brief TIM IRQ handler management
3632 *
3633 @verbatim
3634 ==============================================================================
3635 ##### IRQ handler management #####
3636 ==============================================================================
3637 [..]
3638 This section provides Timer IRQ handler function.
3639
3640 @endverbatim
3641 * @{
3642 */
3643 /**
3644 * @brief This function handles TIM interrupts requests.
3645 * @param htim TIM handle
3646 * @retval None
3647 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3648 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3649 {
3650 /* Capture compare 1 event */
3651 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3652 {
3653 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3654 {
3655 {
3656 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3657 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3658
3659 /* Input capture event */
3660 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3661 {
3662 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3663 htim->IC_CaptureCallback(htim);
3664 #else
3665 HAL_TIM_IC_CaptureCallback(htim);
3666 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3667 }
3668 /* Output compare event */
3669 else
3670 {
3671 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3672 htim->OC_DelayElapsedCallback(htim);
3673 htim->PWM_PulseFinishedCallback(htim);
3674 #else
3675 HAL_TIM_OC_DelayElapsedCallback(htim);
3676 HAL_TIM_PWM_PulseFinishedCallback(htim);
3677 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3678 }
3679 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3680 }
3681 }
3682 }
3683 /* Capture compare 2 event */
3684 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3685 {
3686 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3687 {
3688 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3689 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3690 /* Input capture event */
3691 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3692 {
3693 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3694 htim->IC_CaptureCallback(htim);
3695 #else
3696 HAL_TIM_IC_CaptureCallback(htim);
3697 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3698 }
3699 /* Output compare event */
3700 else
3701 {
3702 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3703 htim->OC_DelayElapsedCallback(htim);
3704 htim->PWM_PulseFinishedCallback(htim);
3705 #else
3706 HAL_TIM_OC_DelayElapsedCallback(htim);
3707 HAL_TIM_PWM_PulseFinishedCallback(htim);
3708 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3709 }
3710 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3711 }
3712 }
3713 /* Capture compare 3 event */
3714 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3715 {
3716 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3717 {
3718 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3719 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3720 /* Input capture event */
3721 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3722 {
3723 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3724 htim->IC_CaptureCallback(htim);
3725 #else
3726 HAL_TIM_IC_CaptureCallback(htim);
3727 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3728 }
3729 /* Output compare event */
3730 else
3731 {
3732 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3733 htim->OC_DelayElapsedCallback(htim);
3734 htim->PWM_PulseFinishedCallback(htim);
3735 #else
3736 HAL_TIM_OC_DelayElapsedCallback(htim);
3737 HAL_TIM_PWM_PulseFinishedCallback(htim);
3738 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3739 }
3740 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3741 }
3742 }
3743 /* Capture compare 4 event */
3744 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3745 {
3746 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3747 {
3748 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3749 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3750 /* Input capture event */
3751 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3752 {
3753 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3754 htim->IC_CaptureCallback(htim);
3755 #else
3756 HAL_TIM_IC_CaptureCallback(htim);
3757 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3758 }
3759 /* Output compare event */
3760 else
3761 {
3762 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3763 htim->OC_DelayElapsedCallback(htim);
3764 htim->PWM_PulseFinishedCallback(htim);
3765 #else
3766 HAL_TIM_OC_DelayElapsedCallback(htim);
3767 HAL_TIM_PWM_PulseFinishedCallback(htim);
3768 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3769 }
3770 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3771 }
3772 }
3773 /* TIM Update event */
3774 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3775 {
3776 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3777 {
3778 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3779 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3780 htim->PeriodElapsedCallback(htim);
3781 #else
3782 HAL_TIM_PeriodElapsedCallback(htim);
3783 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3784 }
3785 }
3786 /* TIM Trigger detection event */
3787 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
3788 {
3789 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
3790 {
3791 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
3792 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3793 htim->TriggerCallback(htim);
3794 #else
3795 HAL_TIM_TriggerCallback(htim);
3796 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3797 }
3798 }
3799 }
3800
3801 /**
3802 * @}
3803 */
3804
3805 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
3806 * @brief TIM Peripheral Control functions
3807 *
3808 @verbatim
3809 ==============================================================================
3810 ##### Peripheral Control functions #####
3811 ==============================================================================
3812 [..]
3813 This section provides functions allowing to:
3814 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
3815 (+) Configure External Clock source.
3816 (+) Configure Master and the Slave synchronization.
3817 (+) Configure the DMA Burst Mode.
3818
3819 @endverbatim
3820 * @{
3821 */
3822
3823 /**
3824 * @brief Initializes the TIM Output Compare Channels according to the specified
3825 * parameters in the TIM_OC_InitTypeDef.
3826 * @param htim TIM Output Compare handle
3827 * @param sConfig TIM Output Compare configuration structure
3828 * @param Channel TIM Channels to configure
3829 * This parameter can be one of the following values:
3830 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3831 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3832 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3833 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3834 * @retval HAL status
3835 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3836 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
3837 const TIM_OC_InitTypeDef *sConfig,
3838 uint32_t Channel)
3839 {
3840 HAL_StatusTypeDef status = HAL_OK;
3841
3842 /* Check the parameters */
3843 assert_param(IS_TIM_CHANNELS(Channel));
3844 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
3845 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3846
3847 /* Process Locked */
3848 __HAL_LOCK(htim);
3849
3850 switch (Channel)
3851 {
3852 case TIM_CHANNEL_1:
3853 {
3854 /* Check the parameters */
3855 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3856
3857 /* Configure the TIM Channel 1 in Output Compare */
3858 TIM_OC1_SetConfig(htim->Instance, sConfig);
3859 break;
3860 }
3861
3862 case TIM_CHANNEL_2:
3863 {
3864 /* Check the parameters */
3865 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3866
3867 /* Configure the TIM Channel 2 in Output Compare */
3868 TIM_OC2_SetConfig(htim->Instance, sConfig);
3869 break;
3870 }
3871
3872 case TIM_CHANNEL_3:
3873 {
3874 /* Check the parameters */
3875 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3876
3877 /* Configure the TIM Channel 3 in Output Compare */
3878 TIM_OC3_SetConfig(htim->Instance, sConfig);
3879 break;
3880 }
3881
3882 case TIM_CHANNEL_4:
3883 {
3884 /* Check the parameters */
3885 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3886
3887 /* Configure the TIM Channel 4 in Output Compare */
3888 TIM_OC4_SetConfig(htim->Instance, sConfig);
3889 break;
3890 }
3891
3892 default:
3893 status = HAL_ERROR;
3894 break;
3895 }
3896
3897 __HAL_UNLOCK(htim);
3898
3899 return status;
3900 }
3901
3902 /**
3903 * @brief Initializes the TIM Input Capture Channels according to the specified
3904 * parameters in the TIM_IC_InitTypeDef.
3905 * @param htim TIM IC handle
3906 * @param sConfig TIM Input Capture configuration structure
3907 * @param Channel TIM Channel to configure
3908 * This parameter can be one of the following values:
3909 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3910 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3911 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3912 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3913 * @retval HAL status
3914 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_IC_InitTypeDef * sConfig,uint32_t Channel)3915 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
3916 {
3917 HAL_StatusTypeDef status = HAL_OK;
3918
3919 /* Check the parameters */
3920 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3921 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
3922 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
3923 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
3924 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
3925
3926 /* Process Locked */
3927 __HAL_LOCK(htim);
3928
3929 if (Channel == TIM_CHANNEL_1)
3930 {
3931 /* TI1 Configuration */
3932 TIM_TI1_SetConfig(htim->Instance,
3933 sConfig->ICPolarity,
3934 sConfig->ICSelection,
3935 sConfig->ICFilter);
3936
3937 /* Reset the IC1PSC Bits */
3938 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3939
3940 /* Set the IC1PSC value */
3941 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
3942 }
3943 else if (Channel == TIM_CHANNEL_2)
3944 {
3945 /* TI2 Configuration */
3946 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3947
3948 TIM_TI2_SetConfig(htim->Instance,
3949 sConfig->ICPolarity,
3950 sConfig->ICSelection,
3951 sConfig->ICFilter);
3952
3953 /* Reset the IC2PSC Bits */
3954 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3955
3956 /* Set the IC2PSC value */
3957 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
3958 }
3959 else if (Channel == TIM_CHANNEL_3)
3960 {
3961 /* TI3 Configuration */
3962 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3963
3964 TIM_TI3_SetConfig(htim->Instance,
3965 sConfig->ICPolarity,
3966 sConfig->ICSelection,
3967 sConfig->ICFilter);
3968
3969 /* Reset the IC3PSC Bits */
3970 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
3971
3972 /* Set the IC3PSC value */
3973 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
3974 }
3975 else if (Channel == TIM_CHANNEL_4)
3976 {
3977 /* TI4 Configuration */
3978 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3979
3980 TIM_TI4_SetConfig(htim->Instance,
3981 sConfig->ICPolarity,
3982 sConfig->ICSelection,
3983 sConfig->ICFilter);
3984
3985 /* Reset the IC4PSC Bits */
3986 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
3987
3988 /* Set the IC4PSC value */
3989 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
3990 }
3991 else
3992 {
3993 status = HAL_ERROR;
3994 }
3995
3996 __HAL_UNLOCK(htim);
3997
3998 return status;
3999 }
4000
4001 /**
4002 * @brief Initializes the TIM PWM channels according to the specified
4003 * parameters in the TIM_OC_InitTypeDef.
4004 * @param htim TIM PWM handle
4005 * @param sConfig TIM PWM configuration structure
4006 * @param Channel TIM Channels to be configured
4007 * This parameter can be one of the following values:
4008 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4009 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4010 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4011 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4012 * @retval HAL status
4013 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4014 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4015 const TIM_OC_InitTypeDef *sConfig,
4016 uint32_t Channel)
4017 {
4018 HAL_StatusTypeDef status = HAL_OK;
4019
4020 /* Check the parameters */
4021 assert_param(IS_TIM_CHANNELS(Channel));
4022 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4023 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4024 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4025
4026 /* Process Locked */
4027 __HAL_LOCK(htim);
4028
4029 switch (Channel)
4030 {
4031 case TIM_CHANNEL_1:
4032 {
4033 /* Check the parameters */
4034 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4035
4036 /* Configure the Channel 1 in PWM mode */
4037 TIM_OC1_SetConfig(htim->Instance, sConfig);
4038
4039 /* Set the Preload enable bit for channel1 */
4040 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4041
4042 /* Configure the Output Fast mode */
4043 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4044 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4045 break;
4046 }
4047
4048 case TIM_CHANNEL_2:
4049 {
4050 /* Check the parameters */
4051 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4052
4053 /* Configure the Channel 2 in PWM mode */
4054 TIM_OC2_SetConfig(htim->Instance, sConfig);
4055
4056 /* Set the Preload enable bit for channel2 */
4057 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4058
4059 /* Configure the Output Fast mode */
4060 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4061 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4062 break;
4063 }
4064
4065 case TIM_CHANNEL_3:
4066 {
4067 /* Check the parameters */
4068 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4069
4070 /* Configure the Channel 3 in PWM mode */
4071 TIM_OC3_SetConfig(htim->Instance, sConfig);
4072
4073 /* Set the Preload enable bit for channel3 */
4074 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4075
4076 /* Configure the Output Fast mode */
4077 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4078 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4079 break;
4080 }
4081
4082 case TIM_CHANNEL_4:
4083 {
4084 /* Check the parameters */
4085 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4086
4087 /* Configure the Channel 4 in PWM mode */
4088 TIM_OC4_SetConfig(htim->Instance, sConfig);
4089
4090 /* Set the Preload enable bit for channel4 */
4091 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4092
4093 /* Configure the Output Fast mode */
4094 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4095 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4096 break;
4097 }
4098
4099 default:
4100 status = HAL_ERROR;
4101 break;
4102 }
4103
4104 __HAL_UNLOCK(htim);
4105
4106 return status;
4107 }
4108
4109 /**
4110 * @brief Initializes the TIM One Pulse Channels according to the specified
4111 * parameters in the TIM_OnePulse_InitTypeDef.
4112 * @param htim TIM One Pulse handle
4113 * @param sConfig TIM One Pulse configuration structure
4114 * @param OutputChannel TIM output channel to configure
4115 * This parameter can be one of the following values:
4116 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4117 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4118 * @param InputChannel TIM input Channel to configure
4119 * This parameter can be one of the following values:
4120 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4121 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4122 * @note To output a waveform with a minimum delay user can enable the fast
4123 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4124 * output is forced in response to the edge detection on TIx input,
4125 * without taking in account the comparison.
4126 * @retval HAL status
4127 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4128 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4129 uint32_t OutputChannel, uint32_t InputChannel)
4130 {
4131 HAL_StatusTypeDef status = HAL_OK;
4132 TIM_OC_InitTypeDef temp1;
4133
4134 /* Check the parameters */
4135 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4136 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4137
4138 if (OutputChannel != InputChannel)
4139 {
4140 /* Process Locked */
4141 __HAL_LOCK(htim);
4142
4143 htim->State = HAL_TIM_STATE_BUSY;
4144
4145 /* Extract the Output compare configuration from sConfig structure */
4146 temp1.OCMode = sConfig->OCMode;
4147 temp1.Pulse = sConfig->Pulse;
4148 temp1.OCPolarity = sConfig->OCPolarity;
4149
4150 switch (OutputChannel)
4151 {
4152 case TIM_CHANNEL_1:
4153 {
4154 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4155
4156 TIM_OC1_SetConfig(htim->Instance, &temp1);
4157 break;
4158 }
4159
4160 case TIM_CHANNEL_2:
4161 {
4162 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4163
4164 TIM_OC2_SetConfig(htim->Instance, &temp1);
4165 break;
4166 }
4167
4168 default:
4169 status = HAL_ERROR;
4170 break;
4171 }
4172
4173 if (status == HAL_OK)
4174 {
4175 switch (InputChannel)
4176 {
4177 case TIM_CHANNEL_1:
4178 {
4179 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4180
4181 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4182 sConfig->ICSelection, sConfig->ICFilter);
4183
4184 /* Reset the IC1PSC Bits */
4185 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4186
4187 /* Select the Trigger source */
4188 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4189 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4190
4191 /* Select the Slave Mode */
4192 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4193 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4194 break;
4195 }
4196
4197 case TIM_CHANNEL_2:
4198 {
4199 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4200
4201 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4202 sConfig->ICSelection, sConfig->ICFilter);
4203
4204 /* Reset the IC2PSC Bits */
4205 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4206
4207 /* Select the Trigger source */
4208 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4209 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4210
4211 /* Select the Slave Mode */
4212 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4213 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4214 break;
4215 }
4216
4217 default:
4218 status = HAL_ERROR;
4219 break;
4220 }
4221 }
4222
4223 htim->State = HAL_TIM_STATE_READY;
4224
4225 __HAL_UNLOCK(htim);
4226
4227 return status;
4228 }
4229 else
4230 {
4231 return HAL_ERROR;
4232 }
4233 }
4234
4235 /**
4236 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4237 * @param htim TIM handle
4238 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4239 * This parameter can be one of the following values:
4240 * @arg TIM_DMABASE_CR1
4241 * @arg TIM_DMABASE_CR2
4242 * @arg TIM_DMABASE_SMCR
4243 * @arg TIM_DMABASE_DIER
4244 * @arg TIM_DMABASE_SR
4245 * @arg TIM_DMABASE_EGR
4246 * @arg TIM_DMABASE_CCMR1
4247 * @arg TIM_DMABASE_CCMR2
4248 * @arg TIM_DMABASE_CCER
4249 * @arg TIM_DMABASE_CNT
4250 * @arg TIM_DMABASE_PSC
4251 * @arg TIM_DMABASE_ARR
4252 * @arg TIM_DMABASE_CCR1
4253 * @arg TIM_DMABASE_CCR2
4254 * @arg TIM_DMABASE_CCR3
4255 * @arg TIM_DMABASE_CCR4
4256 * @arg TIM_DMABASE_OR
4257 * @param BurstRequestSrc TIM DMA Request sources
4258 * This parameter can be one of the following values:
4259 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4260 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4261 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4262 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4263 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4264 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4265 * @param BurstBuffer The Buffer address.
4266 * @param BurstLength DMA Burst length. This parameter can be one value
4267 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4268 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4269 * @retval HAL status
4270 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength)4271 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4272 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
4273 {
4274 HAL_StatusTypeDef status;
4275
4276 status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4277 ((BurstLength) >> 8U) + 1U);
4278
4279
4280
4281 return status;
4282 }
4283
4284 /**
4285 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4286 * @param htim TIM handle
4287 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4288 * This parameter can be one of the following values:
4289 * @arg TIM_DMABASE_CR1
4290 * @arg TIM_DMABASE_CR2
4291 * @arg TIM_DMABASE_SMCR
4292 * @arg TIM_DMABASE_DIER
4293 * @arg TIM_DMABASE_SR
4294 * @arg TIM_DMABASE_EGR
4295 * @arg TIM_DMABASE_CCMR1
4296 * @arg TIM_DMABASE_CCMR2
4297 * @arg TIM_DMABASE_CCER
4298 * @arg TIM_DMABASE_CNT
4299 * @arg TIM_DMABASE_PSC
4300 * @arg TIM_DMABASE_ARR
4301 * @arg TIM_DMABASE_CCR1
4302 * @arg TIM_DMABASE_CCR2
4303 * @arg TIM_DMABASE_CCR3
4304 * @arg TIM_DMABASE_CCR4
4305 * @arg TIM_DMABASE_OR
4306 * @param BurstRequestSrc TIM DMA Request sources
4307 * This parameter can be one of the following values:
4308 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4309 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4310 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4311 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4312 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4313 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4314 * @param BurstBuffer The Buffer address.
4315 * @param BurstLength DMA Burst length. This parameter can be one value
4316 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4317 * @param DataLength Data length. This parameter can be one value
4318 * between 1 and 0xFFFF.
4319 * @retval HAL status
4320 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4321 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4322 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4323 uint32_t BurstLength, uint32_t DataLength)
4324 {
4325 HAL_StatusTypeDef status = HAL_OK;
4326
4327 /* Check the parameters */
4328 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4329 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4330 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4331 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4332 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4333
4334 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4335 {
4336 return HAL_BUSY;
4337 }
4338 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4339 {
4340 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4341 {
4342 return HAL_ERROR;
4343 }
4344 else
4345 {
4346 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4347 }
4348 }
4349 else
4350 {
4351 /* nothing to do */
4352 }
4353
4354 switch (BurstRequestSrc)
4355 {
4356 case TIM_DMA_UPDATE:
4357 {
4358 /* Set the DMA Period elapsed callbacks */
4359 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4360 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4361
4362 /* Set the DMA error callback */
4363 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4364
4365 /* Enable the DMA channel */
4366 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4367 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4368 {
4369 /* Return error status */
4370 return HAL_ERROR;
4371 }
4372 break;
4373 }
4374 case TIM_DMA_CC1:
4375 {
4376 /* Set the DMA compare callbacks */
4377 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4378 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4379
4380 /* Set the DMA error callback */
4381 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4382
4383 /* Enable the DMA channel */
4384 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4385 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4386 {
4387 /* Return error status */
4388 return HAL_ERROR;
4389 }
4390 break;
4391 }
4392 case TIM_DMA_CC2:
4393 {
4394 /* Set the DMA compare callbacks */
4395 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4396 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4397
4398 /* Set the DMA error callback */
4399 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4400
4401 /* Enable the DMA channel */
4402 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4403 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4404 {
4405 /* Return error status */
4406 return HAL_ERROR;
4407 }
4408 break;
4409 }
4410 case TIM_DMA_CC3:
4411 {
4412 /* Set the DMA compare callbacks */
4413 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4414 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4415
4416 /* Set the DMA error callback */
4417 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4418
4419 /* Enable the DMA channel */
4420 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4421 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4422 {
4423 /* Return error status */
4424 return HAL_ERROR;
4425 }
4426 break;
4427 }
4428 case TIM_DMA_CC4:
4429 {
4430 /* Set the DMA compare callbacks */
4431 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4432 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4433
4434 /* Set the DMA error callback */
4435 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4436
4437 /* Enable the DMA channel */
4438 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4439 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4440 {
4441 /* Return error status */
4442 return HAL_ERROR;
4443 }
4444 break;
4445 }
4446 case TIM_DMA_TRIGGER:
4447 {
4448 /* Set the DMA trigger callbacks */
4449 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4450 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4451
4452 /* Set the DMA error callback */
4453 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4454
4455 /* Enable the DMA channel */
4456 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4457 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4458 {
4459 /* Return error status */
4460 return HAL_ERROR;
4461 }
4462 break;
4463 }
4464 default:
4465 status = HAL_ERROR;
4466 break;
4467 }
4468
4469 if (status == HAL_OK)
4470 {
4471 /* Configure the DMA Burst Mode */
4472 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4473 /* Enable the TIM DMA Request */
4474 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4475 }
4476
4477 /* Return function status */
4478 return status;
4479 }
4480
4481 /**
4482 * @brief Stops the TIM DMA Burst mode
4483 * @param htim TIM handle
4484 * @param BurstRequestSrc TIM DMA Request sources to disable
4485 * @retval HAL status
4486 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4487 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4488 {
4489 HAL_StatusTypeDef status = HAL_OK;
4490
4491 /* Check the parameters */
4492 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4493
4494 /* Abort the DMA transfer (at least disable the DMA channel) */
4495 switch (BurstRequestSrc)
4496 {
4497 case TIM_DMA_UPDATE:
4498 {
4499 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4500 break;
4501 }
4502 case TIM_DMA_CC1:
4503 {
4504 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4505 break;
4506 }
4507 case TIM_DMA_CC2:
4508 {
4509 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4510 break;
4511 }
4512 case TIM_DMA_CC3:
4513 {
4514 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4515 break;
4516 }
4517 case TIM_DMA_CC4:
4518 {
4519 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4520 break;
4521 }
4522 case TIM_DMA_TRIGGER:
4523 {
4524 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4525 break;
4526 }
4527 default:
4528 status = HAL_ERROR;
4529 break;
4530 }
4531
4532 if (status == HAL_OK)
4533 {
4534 /* Disable the TIM Update DMA request */
4535 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4536
4537 /* Change the DMA burst operation state */
4538 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4539 }
4540
4541 /* Return function status */
4542 return status;
4543 }
4544
4545 /**
4546 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4547 * @param htim TIM handle
4548 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4549 * This parameter can be one of the following values:
4550 * @arg TIM_DMABASE_CR1
4551 * @arg TIM_DMABASE_CR2
4552 * @arg TIM_DMABASE_SMCR
4553 * @arg TIM_DMABASE_DIER
4554 * @arg TIM_DMABASE_SR
4555 * @arg TIM_DMABASE_EGR
4556 * @arg TIM_DMABASE_CCMR1
4557 * @arg TIM_DMABASE_CCMR2
4558 * @arg TIM_DMABASE_CCER
4559 * @arg TIM_DMABASE_CNT
4560 * @arg TIM_DMABASE_PSC
4561 * @arg TIM_DMABASE_ARR
4562 * @arg TIM_DMABASE_CCR1
4563 * @arg TIM_DMABASE_CCR2
4564 * @arg TIM_DMABASE_CCR3
4565 * @arg TIM_DMABASE_CCR4
4566 * @arg TIM_DMABASE_OR
4567 * @param BurstRequestSrc TIM DMA Request sources
4568 * This parameter can be one of the following values:
4569 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4570 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4571 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4572 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4573 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4574 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4575 * @param BurstBuffer The Buffer address.
4576 * @param BurstLength DMA Burst length. This parameter can be one value
4577 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4578 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4579 * @retval HAL status
4580 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4581 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4582 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4583 {
4584 HAL_StatusTypeDef status;
4585
4586 status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4587 ((BurstLength) >> 8U) + 1U);
4588
4589
4590 return status;
4591 }
4592
4593 /**
4594 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4595 * @param htim TIM handle
4596 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4597 * This parameter can be one of the following values:
4598 * @arg TIM_DMABASE_CR1
4599 * @arg TIM_DMABASE_CR2
4600 * @arg TIM_DMABASE_SMCR
4601 * @arg TIM_DMABASE_DIER
4602 * @arg TIM_DMABASE_SR
4603 * @arg TIM_DMABASE_EGR
4604 * @arg TIM_DMABASE_CCMR1
4605 * @arg TIM_DMABASE_CCMR2
4606 * @arg TIM_DMABASE_CCER
4607 * @arg TIM_DMABASE_CNT
4608 * @arg TIM_DMABASE_PSC
4609 * @arg TIM_DMABASE_ARR
4610 * @arg TIM_DMABASE_CCR1
4611 * @arg TIM_DMABASE_CCR2
4612 * @arg TIM_DMABASE_CCR3
4613 * @arg TIM_DMABASE_CCR4
4614 * @arg TIM_DMABASE_OR
4615 * @param BurstRequestSrc TIM DMA Request sources
4616 * This parameter can be one of the following values:
4617 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4618 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4619 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4620 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4621 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4622 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4623 * @param BurstBuffer The Buffer address.
4624 * @param BurstLength DMA Burst length. This parameter can be one value
4625 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4626 * @param DataLength Data length. This parameter can be one value
4627 * between 1 and 0xFFFF.
4628 * @retval HAL status
4629 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4630 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4631 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4632 uint32_t BurstLength, uint32_t DataLength)
4633 {
4634 HAL_StatusTypeDef status = HAL_OK;
4635
4636 /* Check the parameters */
4637 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4638 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4639 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4640 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4641 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4642
4643 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4644 {
4645 return HAL_BUSY;
4646 }
4647 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4648 {
4649 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4650 {
4651 return HAL_ERROR;
4652 }
4653 else
4654 {
4655 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4656 }
4657 }
4658 else
4659 {
4660 /* nothing to do */
4661 }
4662 switch (BurstRequestSrc)
4663 {
4664 case TIM_DMA_UPDATE:
4665 {
4666 /* Set the DMA Period elapsed callbacks */
4667 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4668 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4669
4670 /* Set the DMA error callback */
4671 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4672
4673 /* Enable the DMA channel */
4674 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4675 DataLength) != HAL_OK)
4676 {
4677 /* Return error status */
4678 return HAL_ERROR;
4679 }
4680 break;
4681 }
4682 case TIM_DMA_CC1:
4683 {
4684 /* Set the DMA capture callbacks */
4685 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
4686 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4687
4688 /* Set the DMA error callback */
4689 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4690
4691 /* Enable the DMA channel */
4692 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4693 DataLength) != HAL_OK)
4694 {
4695 /* Return error status */
4696 return HAL_ERROR;
4697 }
4698 break;
4699 }
4700 case TIM_DMA_CC2:
4701 {
4702 /* Set the DMA capture callbacks */
4703 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
4704 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4705
4706 /* Set the DMA error callback */
4707 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4708
4709 /* Enable the DMA channel */
4710 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4711 DataLength) != HAL_OK)
4712 {
4713 /* Return error status */
4714 return HAL_ERROR;
4715 }
4716 break;
4717 }
4718 case TIM_DMA_CC3:
4719 {
4720 /* Set the DMA capture callbacks */
4721 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
4722 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4723
4724 /* Set the DMA error callback */
4725 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4726
4727 /* Enable the DMA channel */
4728 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4729 DataLength) != HAL_OK)
4730 {
4731 /* Return error status */
4732 return HAL_ERROR;
4733 }
4734 break;
4735 }
4736 case TIM_DMA_CC4:
4737 {
4738 /* Set the DMA capture callbacks */
4739 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
4740 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4741
4742 /* Set the DMA error callback */
4743 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4744
4745 /* Enable the DMA channel */
4746 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4747 DataLength) != HAL_OK)
4748 {
4749 /* Return error status */
4750 return HAL_ERROR;
4751 }
4752 break;
4753 }
4754 case TIM_DMA_TRIGGER:
4755 {
4756 /* Set the DMA trigger callbacks */
4757 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4758 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4759
4760 /* Set the DMA error callback */
4761 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4762
4763 /* Enable the DMA channel */
4764 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4765 DataLength) != HAL_OK)
4766 {
4767 /* Return error status */
4768 return HAL_ERROR;
4769 }
4770 break;
4771 }
4772 default:
4773 status = HAL_ERROR;
4774 break;
4775 }
4776
4777 if (status == HAL_OK)
4778 {
4779 /* Configure the DMA Burst Mode */
4780 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4781
4782 /* Enable the TIM DMA Request */
4783 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4784 }
4785
4786 /* Return function status */
4787 return status;
4788 }
4789
4790 /**
4791 * @brief Stop the DMA burst reading
4792 * @param htim TIM handle
4793 * @param BurstRequestSrc TIM DMA Request sources to disable.
4794 * @retval HAL status
4795 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4796 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4797 {
4798 HAL_StatusTypeDef status = HAL_OK;
4799
4800 /* Check the parameters */
4801 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4802
4803 /* Abort the DMA transfer (at least disable the DMA channel) */
4804 switch (BurstRequestSrc)
4805 {
4806 case TIM_DMA_UPDATE:
4807 {
4808 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4809 break;
4810 }
4811 case TIM_DMA_CC1:
4812 {
4813 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4814 break;
4815 }
4816 case TIM_DMA_CC2:
4817 {
4818 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4819 break;
4820 }
4821 case TIM_DMA_CC3:
4822 {
4823 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4824 break;
4825 }
4826 case TIM_DMA_CC4:
4827 {
4828 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4829 break;
4830 }
4831 case TIM_DMA_TRIGGER:
4832 {
4833 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4834 break;
4835 }
4836 default:
4837 status = HAL_ERROR;
4838 break;
4839 }
4840
4841 if (status == HAL_OK)
4842 {
4843 /* Disable the TIM Update DMA request */
4844 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4845
4846 /* Change the DMA burst operation state */
4847 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4848 }
4849
4850 /* Return function status */
4851 return status;
4852 }
4853
4854 /**
4855 * @brief Generate a software event
4856 * @param htim TIM handle
4857 * @param EventSource specifies the event source.
4858 * This parameter can be one of the following values:
4859 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
4860 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
4861 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
4862 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
4863 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
4864 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
4865 * @note Basic timers can only generate an update event.
4866 * @retval HAL status
4867 */
4868
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)4869 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
4870 {
4871 /* Check the parameters */
4872 assert_param(IS_TIM_INSTANCE(htim->Instance));
4873 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
4874
4875 /* Process Locked */
4876 __HAL_LOCK(htim);
4877
4878 /* Change the TIM state */
4879 htim->State = HAL_TIM_STATE_BUSY;
4880
4881 /* Set the event sources */
4882 htim->Instance->EGR = EventSource;
4883
4884 /* Change the TIM state */
4885 htim->State = HAL_TIM_STATE_READY;
4886
4887 __HAL_UNLOCK(htim);
4888
4889 /* Return function status */
4890 return HAL_OK;
4891 }
4892
4893 /**
4894 * @brief Configures the OCRef clear feature
4895 * @param htim TIM handle
4896 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
4897 * contains the OCREF clear feature and parameters for the TIM peripheral.
4898 * @param Channel specifies the TIM Channel
4899 * This parameter can be one of the following values:
4900 * @arg TIM_CHANNEL_1: TIM Channel 1
4901 * @arg TIM_CHANNEL_2: TIM Channel 2
4902 * @arg TIM_CHANNEL_3: TIM Channel 3
4903 * @arg TIM_CHANNEL_4: TIM Channel 4
4904 * @retval HAL status
4905 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,const TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)4906 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
4907 const TIM_ClearInputConfigTypeDef *sClearInputConfig,
4908 uint32_t Channel)
4909 {
4910 HAL_StatusTypeDef status = HAL_OK;
4911
4912 /* Check the parameters */
4913 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
4914 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
4915
4916 /* Process Locked */
4917 __HAL_LOCK(htim);
4918
4919 htim->State = HAL_TIM_STATE_BUSY;
4920
4921 switch (sClearInputConfig->ClearInputSource)
4922 {
4923 case TIM_CLEARINPUTSOURCE_NONE:
4924 {
4925 /* Clear the OCREF clear selection bit and the the ETR Bits */
4926 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
4927 break;
4928 }
4929
4930 case TIM_CLEARINPUTSOURCE_ETR:
4931 {
4932 /* Check the parameters */
4933 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
4934 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
4935 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
4936
4937 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
4938 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
4939 {
4940 htim->State = HAL_TIM_STATE_READY;
4941 __HAL_UNLOCK(htim);
4942 return HAL_ERROR;
4943 }
4944
4945 TIM_ETR_SetConfig(htim->Instance,
4946 sClearInputConfig->ClearInputPrescaler,
4947 sClearInputConfig->ClearInputPolarity,
4948 sClearInputConfig->ClearInputFilter);
4949 break;
4950 }
4951
4952 default:
4953 status = HAL_ERROR;
4954 break;
4955 }
4956
4957 if (status == HAL_OK)
4958 {
4959 switch (Channel)
4960 {
4961 case TIM_CHANNEL_1:
4962 {
4963 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4964 {
4965 /* Enable the OCREF clear feature for Channel 1 */
4966 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
4967 }
4968 else
4969 {
4970 /* Disable the OCREF clear feature for Channel 1 */
4971 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
4972 }
4973 break;
4974 }
4975 case TIM_CHANNEL_2:
4976 {
4977 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4978 {
4979 /* Enable the OCREF clear feature for Channel 2 */
4980 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
4981 }
4982 else
4983 {
4984 /* Disable the OCREF clear feature for Channel 2 */
4985 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
4986 }
4987 break;
4988 }
4989 case TIM_CHANNEL_3:
4990 {
4991 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4992 {
4993 /* Enable the OCREF clear feature for Channel 3 */
4994 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
4995 }
4996 else
4997 {
4998 /* Disable the OCREF clear feature for Channel 3 */
4999 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5000 }
5001 break;
5002 }
5003 case TIM_CHANNEL_4:
5004 {
5005 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5006 {
5007 /* Enable the OCREF clear feature for Channel 4 */
5008 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5009 }
5010 else
5011 {
5012 /* Disable the OCREF clear feature for Channel 4 */
5013 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5014 }
5015 break;
5016 }
5017 default:
5018 break;
5019 }
5020 }
5021
5022 htim->State = HAL_TIM_STATE_READY;
5023
5024 __HAL_UNLOCK(htim);
5025
5026 return status;
5027 }
5028
5029 /**
5030 * @brief Configures the clock source to be used
5031 * @param htim TIM handle
5032 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5033 * contains the clock source information for the TIM peripheral.
5034 * @retval HAL status
5035 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,const TIM_ClockConfigTypeDef * sClockSourceConfig)5036 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5037 {
5038 HAL_StatusTypeDef status = HAL_OK;
5039 uint32_t tmpsmcr;
5040
5041 /* Process Locked */
5042 __HAL_LOCK(htim);
5043
5044 htim->State = HAL_TIM_STATE_BUSY;
5045
5046 /* Check the parameters */
5047 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5048
5049 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5050 tmpsmcr = htim->Instance->SMCR;
5051 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5052 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5053 htim->Instance->SMCR = tmpsmcr;
5054
5055 switch (sClockSourceConfig->ClockSource)
5056 {
5057 case TIM_CLOCKSOURCE_INTERNAL:
5058 {
5059 assert_param(IS_TIM_INSTANCE(htim->Instance));
5060 break;
5061 }
5062
5063 case TIM_CLOCKSOURCE_ETRMODE1:
5064 {
5065 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5066 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5067
5068 /* Check ETR input conditioning related parameters */
5069 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5070 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5071 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5072
5073 /* Configure the ETR Clock source */
5074 TIM_ETR_SetConfig(htim->Instance,
5075 sClockSourceConfig->ClockPrescaler,
5076 sClockSourceConfig->ClockPolarity,
5077 sClockSourceConfig->ClockFilter);
5078
5079 /* Select the External clock mode1 and the ETRF trigger */
5080 tmpsmcr = htim->Instance->SMCR;
5081 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5082 /* Write to TIMx SMCR */
5083 htim->Instance->SMCR = tmpsmcr;
5084 break;
5085 }
5086
5087 case TIM_CLOCKSOURCE_ETRMODE2:
5088 {
5089 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5090 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5091
5092 /* Check ETR input conditioning related parameters */
5093 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5094 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5095 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5096
5097 /* Configure the ETR Clock source */
5098 TIM_ETR_SetConfig(htim->Instance,
5099 sClockSourceConfig->ClockPrescaler,
5100 sClockSourceConfig->ClockPolarity,
5101 sClockSourceConfig->ClockFilter);
5102 /* Enable the External clock mode2 */
5103 htim->Instance->SMCR |= TIM_SMCR_ECE;
5104 break;
5105 }
5106
5107 case TIM_CLOCKSOURCE_TI1:
5108 {
5109 /* Check whether or not the timer instance supports external clock mode 1 */
5110 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5111
5112 /* Check TI1 input conditioning related parameters */
5113 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5114 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5115
5116 TIM_TI1_ConfigInputStage(htim->Instance,
5117 sClockSourceConfig->ClockPolarity,
5118 sClockSourceConfig->ClockFilter);
5119 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5120 break;
5121 }
5122
5123 case TIM_CLOCKSOURCE_TI2:
5124 {
5125 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5126 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5127
5128 /* Check TI2 input conditioning related parameters */
5129 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5130 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5131
5132 TIM_TI2_ConfigInputStage(htim->Instance,
5133 sClockSourceConfig->ClockPolarity,
5134 sClockSourceConfig->ClockFilter);
5135 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5136 break;
5137 }
5138
5139 case TIM_CLOCKSOURCE_TI1ED:
5140 {
5141 /* Check whether or not the timer instance supports external clock mode 1 */
5142 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5143
5144 /* Check TI1 input conditioning related parameters */
5145 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5146 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5147
5148 TIM_TI1_ConfigInputStage(htim->Instance,
5149 sClockSourceConfig->ClockPolarity,
5150 sClockSourceConfig->ClockFilter);
5151 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5152 break;
5153 }
5154
5155 case TIM_CLOCKSOURCE_ITR0:
5156 case TIM_CLOCKSOURCE_ITR1:
5157 case TIM_CLOCKSOURCE_ITR2:
5158 case TIM_CLOCKSOURCE_ITR3:
5159 {
5160 /* Check whether or not the timer instance supports internal trigger input */
5161 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
5162
5163 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5164 break;
5165 }
5166
5167 default:
5168 status = HAL_ERROR;
5169 break;
5170 }
5171 htim->State = HAL_TIM_STATE_READY;
5172
5173 __HAL_UNLOCK(htim);
5174
5175 return status;
5176 }
5177
5178 /**
5179 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5180 * or a XOR combination between CH1_input, CH2_input & CH3_input
5181 * @param htim TIM handle.
5182 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5183 * output of a XOR gate.
5184 * This parameter can be one of the following values:
5185 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5186 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5187 * pins are connected to the TI1 input (XOR combination)
5188 * @retval HAL status
5189 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5190 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5191 {
5192 uint32_t tmpcr2;
5193
5194 /* Check the parameters */
5195 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5196 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5197
5198 /* Get the TIMx CR2 register value */
5199 tmpcr2 = htim->Instance->CR2;
5200
5201 /* Reset the TI1 selection */
5202 tmpcr2 &= ~TIM_CR2_TI1S;
5203
5204 /* Set the TI1 selection */
5205 tmpcr2 |= TI1_Selection;
5206
5207 /* Write to TIMxCR2 */
5208 htim->Instance->CR2 = tmpcr2;
5209
5210 return HAL_OK;
5211 }
5212
5213 /**
5214 * @brief Configures the TIM in Slave mode
5215 * @param htim TIM handle.
5216 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5217 * contains the selected trigger (internal trigger input, filtered
5218 * timer input or external trigger input) and the Slave mode
5219 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5220 * @retval HAL status
5221 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5222 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5223 {
5224 /* Check the parameters */
5225 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5226 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5227 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5228
5229 __HAL_LOCK(htim);
5230
5231 htim->State = HAL_TIM_STATE_BUSY;
5232
5233 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5234 {
5235 htim->State = HAL_TIM_STATE_READY;
5236 __HAL_UNLOCK(htim);
5237 return HAL_ERROR;
5238 }
5239
5240 /* Disable Trigger Interrupt */
5241 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5242
5243 /* Disable Trigger DMA request */
5244 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5245
5246 htim->State = HAL_TIM_STATE_READY;
5247
5248 __HAL_UNLOCK(htim);
5249
5250 return HAL_OK;
5251 }
5252
5253 /**
5254 * @brief Configures the TIM in Slave mode in interrupt mode
5255 * @param htim TIM handle.
5256 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5257 * contains the selected trigger (internal trigger input, filtered
5258 * timer input or external trigger input) and the Slave mode
5259 * (Disable, Reset, Gated, Trigger, External clock mode 1).
5260 * @retval HAL status
5261 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5262 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5263 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5264 {
5265 /* Check the parameters */
5266 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5267 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5268 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
5269
5270 __HAL_LOCK(htim);
5271
5272 htim->State = HAL_TIM_STATE_BUSY;
5273
5274 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5275 {
5276 htim->State = HAL_TIM_STATE_READY;
5277 __HAL_UNLOCK(htim);
5278 return HAL_ERROR;
5279 }
5280
5281 /* Enable Trigger Interrupt */
5282 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5283
5284 /* Disable Trigger DMA request */
5285 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5286
5287 htim->State = HAL_TIM_STATE_READY;
5288
5289 __HAL_UNLOCK(htim);
5290
5291 return HAL_OK;
5292 }
5293
5294 /**
5295 * @brief Read the captured value from Capture Compare unit
5296 * @param htim TIM handle.
5297 * @param Channel TIM Channels to be enabled
5298 * This parameter can be one of the following values:
5299 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5300 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5301 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5302 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5303 * @retval Captured value
5304 */
HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef * htim,uint32_t Channel)5305 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
5306 {
5307 uint32_t tmpreg = 0U;
5308
5309 switch (Channel)
5310 {
5311 case TIM_CHANNEL_1:
5312 {
5313 /* Check the parameters */
5314 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5315
5316 /* Return the capture 1 value */
5317 tmpreg = htim->Instance->CCR1;
5318
5319 break;
5320 }
5321 case TIM_CHANNEL_2:
5322 {
5323 /* Check the parameters */
5324 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5325
5326 /* Return the capture 2 value */
5327 tmpreg = htim->Instance->CCR2;
5328
5329 break;
5330 }
5331
5332 case TIM_CHANNEL_3:
5333 {
5334 /* Check the parameters */
5335 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5336
5337 /* Return the capture 3 value */
5338 tmpreg = htim->Instance->CCR3;
5339
5340 break;
5341 }
5342
5343 case TIM_CHANNEL_4:
5344 {
5345 /* Check the parameters */
5346 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5347
5348 /* Return the capture 4 value */
5349 tmpreg = htim->Instance->CCR4;
5350
5351 break;
5352 }
5353
5354 default:
5355 break;
5356 }
5357
5358 return tmpreg;
5359 }
5360
5361 /**
5362 * @}
5363 */
5364
5365 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5366 * @brief TIM Callbacks functions
5367 *
5368 @verbatim
5369 ==============================================================================
5370 ##### TIM Callbacks functions #####
5371 ==============================================================================
5372 [..]
5373 This section provides TIM callback functions:
5374 (+) TIM Period elapsed callback
5375 (+) TIM Output Compare callback
5376 (+) TIM Input capture callback
5377 (+) TIM Trigger callback
5378 (+) TIM Error callback
5379
5380 @endverbatim
5381 * @{
5382 */
5383
5384 /**
5385 * @brief Period elapsed callback in non-blocking mode
5386 * @param htim TIM handle
5387 * @retval None
5388 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5389 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5390 {
5391 /* Prevent unused argument(s) compilation warning */
5392 UNUSED(htim);
5393
5394 /* NOTE : This function should not be modified, when the callback is needed,
5395 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5396 */
5397 }
5398
5399 /**
5400 * @brief Period elapsed half complete callback in non-blocking mode
5401 * @param htim TIM handle
5402 * @retval None
5403 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5404 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5405 {
5406 /* Prevent unused argument(s) compilation warning */
5407 UNUSED(htim);
5408
5409 /* NOTE : This function should not be modified, when the callback is needed,
5410 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5411 */
5412 }
5413
5414 /**
5415 * @brief Output Compare callback in non-blocking mode
5416 * @param htim TIM OC handle
5417 * @retval None
5418 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5419 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5420 {
5421 /* Prevent unused argument(s) compilation warning */
5422 UNUSED(htim);
5423
5424 /* NOTE : This function should not be modified, when the callback is needed,
5425 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5426 */
5427 }
5428
5429 /**
5430 * @brief Input Capture callback in non-blocking mode
5431 * @param htim TIM IC handle
5432 * @retval None
5433 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5434 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5435 {
5436 /* Prevent unused argument(s) compilation warning */
5437 UNUSED(htim);
5438
5439 /* NOTE : This function should not be modified, when the callback is needed,
5440 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5441 */
5442 }
5443
5444 /**
5445 * @brief Input Capture half complete callback in non-blocking mode
5446 * @param htim TIM IC handle
5447 * @retval None
5448 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5449 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5450 {
5451 /* Prevent unused argument(s) compilation warning */
5452 UNUSED(htim);
5453
5454 /* NOTE : This function should not be modified, when the callback is needed,
5455 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5456 */
5457 }
5458
5459 /**
5460 * @brief PWM Pulse finished callback in non-blocking mode
5461 * @param htim TIM handle
5462 * @retval None
5463 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5464 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5465 {
5466 /* Prevent unused argument(s) compilation warning */
5467 UNUSED(htim);
5468
5469 /* NOTE : This function should not be modified, when the callback is needed,
5470 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5471 */
5472 }
5473
5474 /**
5475 * @brief PWM Pulse finished half complete callback in non-blocking mode
5476 * @param htim TIM handle
5477 * @retval None
5478 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5479 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5480 {
5481 /* Prevent unused argument(s) compilation warning */
5482 UNUSED(htim);
5483
5484 /* NOTE : This function should not be modified, when the callback is needed,
5485 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5486 */
5487 }
5488
5489 /**
5490 * @brief Hall Trigger detection callback in non-blocking mode
5491 * @param htim TIM handle
5492 * @retval None
5493 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5494 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5495 {
5496 /* Prevent unused argument(s) compilation warning */
5497 UNUSED(htim);
5498
5499 /* NOTE : This function should not be modified, when the callback is needed,
5500 the HAL_TIM_TriggerCallback could be implemented in the user file
5501 */
5502 }
5503
5504 /**
5505 * @brief Hall Trigger detection half complete callback in non-blocking mode
5506 * @param htim TIM handle
5507 * @retval None
5508 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5509 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5510 {
5511 /* Prevent unused argument(s) compilation warning */
5512 UNUSED(htim);
5513
5514 /* NOTE : This function should not be modified, when the callback is needed,
5515 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5516 */
5517 }
5518
5519 /**
5520 * @brief Timer error callback in non-blocking mode
5521 * @param htim TIM handle
5522 * @retval None
5523 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5524 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5525 {
5526 /* Prevent unused argument(s) compilation warning */
5527 UNUSED(htim);
5528
5529 /* NOTE : This function should not be modified, when the callback is needed,
5530 the HAL_TIM_ErrorCallback could be implemented in the user file
5531 */
5532 }
5533
5534 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5535 /**
5536 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5537 * @param htim tim handle
5538 * @param CallbackID ID of the callback to be registered
5539 * This parameter can be one of the following values:
5540 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5541 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5542 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5543 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5544 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5545 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5546 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5547 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5548 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5549 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5550 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5551 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5552 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5553 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5554 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5555 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5556 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5557 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5558 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5559 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5560 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5561 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5562 * @param pCallback pointer to the callback function
5563 * @retval status
5564 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)5565 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5566 pTIM_CallbackTypeDef pCallback)
5567 {
5568 HAL_StatusTypeDef status = HAL_OK;
5569
5570 if (pCallback == NULL)
5571 {
5572 return HAL_ERROR;
5573 }
5574
5575 if (htim->State == HAL_TIM_STATE_READY)
5576 {
5577 switch (CallbackID)
5578 {
5579 case HAL_TIM_BASE_MSPINIT_CB_ID :
5580 htim->Base_MspInitCallback = pCallback;
5581 break;
5582
5583 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5584 htim->Base_MspDeInitCallback = pCallback;
5585 break;
5586
5587 case HAL_TIM_IC_MSPINIT_CB_ID :
5588 htim->IC_MspInitCallback = pCallback;
5589 break;
5590
5591 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5592 htim->IC_MspDeInitCallback = pCallback;
5593 break;
5594
5595 case HAL_TIM_OC_MSPINIT_CB_ID :
5596 htim->OC_MspInitCallback = pCallback;
5597 break;
5598
5599 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5600 htim->OC_MspDeInitCallback = pCallback;
5601 break;
5602
5603 case HAL_TIM_PWM_MSPINIT_CB_ID :
5604 htim->PWM_MspInitCallback = pCallback;
5605 break;
5606
5607 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5608 htim->PWM_MspDeInitCallback = pCallback;
5609 break;
5610
5611 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5612 htim->OnePulse_MspInitCallback = pCallback;
5613 break;
5614
5615 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5616 htim->OnePulse_MspDeInitCallback = pCallback;
5617 break;
5618
5619 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5620 htim->Encoder_MspInitCallback = pCallback;
5621 break;
5622
5623 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5624 htim->Encoder_MspDeInitCallback = pCallback;
5625 break;
5626
5627 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5628 htim->PeriodElapsedCallback = pCallback;
5629 break;
5630
5631 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5632 htim->PeriodElapsedHalfCpltCallback = pCallback;
5633 break;
5634
5635 case HAL_TIM_TRIGGER_CB_ID :
5636 htim->TriggerCallback = pCallback;
5637 break;
5638
5639 case HAL_TIM_TRIGGER_HALF_CB_ID :
5640 htim->TriggerHalfCpltCallback = pCallback;
5641 break;
5642
5643 case HAL_TIM_IC_CAPTURE_CB_ID :
5644 htim->IC_CaptureCallback = pCallback;
5645 break;
5646
5647 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5648 htim->IC_CaptureHalfCpltCallback = pCallback;
5649 break;
5650
5651 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5652 htim->OC_DelayElapsedCallback = pCallback;
5653 break;
5654
5655 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5656 htim->PWM_PulseFinishedCallback = pCallback;
5657 break;
5658
5659 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5660 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
5661 break;
5662
5663 case HAL_TIM_ERROR_CB_ID :
5664 htim->ErrorCallback = pCallback;
5665 break;
5666
5667 default :
5668 /* Return error status */
5669 status = HAL_ERROR;
5670 break;
5671 }
5672 }
5673 else if (htim->State == HAL_TIM_STATE_RESET)
5674 {
5675 switch (CallbackID)
5676 {
5677 case HAL_TIM_BASE_MSPINIT_CB_ID :
5678 htim->Base_MspInitCallback = pCallback;
5679 break;
5680
5681 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5682 htim->Base_MspDeInitCallback = pCallback;
5683 break;
5684
5685 case HAL_TIM_IC_MSPINIT_CB_ID :
5686 htim->IC_MspInitCallback = pCallback;
5687 break;
5688
5689 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5690 htim->IC_MspDeInitCallback = pCallback;
5691 break;
5692
5693 case HAL_TIM_OC_MSPINIT_CB_ID :
5694 htim->OC_MspInitCallback = pCallback;
5695 break;
5696
5697 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5698 htim->OC_MspDeInitCallback = pCallback;
5699 break;
5700
5701 case HAL_TIM_PWM_MSPINIT_CB_ID :
5702 htim->PWM_MspInitCallback = pCallback;
5703 break;
5704
5705 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5706 htim->PWM_MspDeInitCallback = pCallback;
5707 break;
5708
5709 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5710 htim->OnePulse_MspInitCallback = pCallback;
5711 break;
5712
5713 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5714 htim->OnePulse_MspDeInitCallback = pCallback;
5715 break;
5716
5717 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5718 htim->Encoder_MspInitCallback = pCallback;
5719 break;
5720
5721 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5722 htim->Encoder_MspDeInitCallback = pCallback;
5723 break;
5724
5725 default :
5726 /* Return error status */
5727 status = HAL_ERROR;
5728 break;
5729 }
5730 }
5731 else
5732 {
5733 /* Return error status */
5734 status = HAL_ERROR;
5735 }
5736
5737 return status;
5738 }
5739
5740 /**
5741 * @brief Unregister a TIM callback
5742 * TIM callback is redirected to the weak predefined callback
5743 * @param htim tim handle
5744 * @param CallbackID ID of the callback to be unregistered
5745 * This parameter can be one of the following values:
5746 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5747 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5748 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5749 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5750 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5751 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5752 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5753 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5754 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5755 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5756 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5757 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5758 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5759 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5760 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5761 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5762 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5763 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5764 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5765 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5766 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5767 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5768 * @retval status
5769 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)5770 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
5771 {
5772 HAL_StatusTypeDef status = HAL_OK;
5773
5774 if (htim->State == HAL_TIM_STATE_READY)
5775 {
5776 switch (CallbackID)
5777 {
5778 case HAL_TIM_BASE_MSPINIT_CB_ID :
5779 /* Legacy weak Base MspInit Callback */
5780 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
5781 break;
5782
5783 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5784 /* Legacy weak Base Msp DeInit Callback */
5785 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
5786 break;
5787
5788 case HAL_TIM_IC_MSPINIT_CB_ID :
5789 /* Legacy weak IC Msp Init Callback */
5790 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
5791 break;
5792
5793 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5794 /* Legacy weak IC Msp DeInit Callback */
5795 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
5796 break;
5797
5798 case HAL_TIM_OC_MSPINIT_CB_ID :
5799 /* Legacy weak OC Msp Init Callback */
5800 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
5801 break;
5802
5803 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5804 /* Legacy weak OC Msp DeInit Callback */
5805 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
5806 break;
5807
5808 case HAL_TIM_PWM_MSPINIT_CB_ID :
5809 /* Legacy weak PWM Msp Init Callback */
5810 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
5811 break;
5812
5813 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5814 /* Legacy weak PWM Msp DeInit Callback */
5815 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
5816 break;
5817
5818 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5819 /* Legacy weak One Pulse Msp Init Callback */
5820 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
5821 break;
5822
5823 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5824 /* Legacy weak One Pulse Msp DeInit Callback */
5825 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
5826 break;
5827
5828 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5829 /* Legacy weak Encoder Msp Init Callback */
5830 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
5831 break;
5832
5833 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5834 /* Legacy weak Encoder Msp DeInit Callback */
5835 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
5836 break;
5837
5838 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5839 /* Legacy weak Period Elapsed Callback */
5840 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
5841 break;
5842
5843 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5844 /* Legacy weak Period Elapsed half complete Callback */
5845 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
5846 break;
5847
5848 case HAL_TIM_TRIGGER_CB_ID :
5849 /* Legacy weak Trigger Callback */
5850 htim->TriggerCallback = HAL_TIM_TriggerCallback;
5851 break;
5852
5853 case HAL_TIM_TRIGGER_HALF_CB_ID :
5854 /* Legacy weak Trigger half complete Callback */
5855 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
5856 break;
5857
5858 case HAL_TIM_IC_CAPTURE_CB_ID :
5859 /* Legacy weak IC Capture Callback */
5860 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
5861 break;
5862
5863 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5864 /* Legacy weak IC Capture half complete Callback */
5865 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
5866 break;
5867
5868 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5869 /* Legacy weak OC Delay Elapsed Callback */
5870 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
5871 break;
5872
5873 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5874 /* Legacy weak PWM Pulse Finished Callback */
5875 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
5876 break;
5877
5878 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5879 /* Legacy weak PWM Pulse Finished half complete Callback */
5880 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
5881 break;
5882
5883 case HAL_TIM_ERROR_CB_ID :
5884 /* Legacy weak Error Callback */
5885 htim->ErrorCallback = HAL_TIM_ErrorCallback;
5886 break;
5887
5888 default :
5889 /* Return error status */
5890 status = HAL_ERROR;
5891 break;
5892 }
5893 }
5894 else if (htim->State == HAL_TIM_STATE_RESET)
5895 {
5896 switch (CallbackID)
5897 {
5898 case HAL_TIM_BASE_MSPINIT_CB_ID :
5899 /* Legacy weak Base MspInit Callback */
5900 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
5901 break;
5902
5903 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5904 /* Legacy weak Base Msp DeInit Callback */
5905 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
5906 break;
5907
5908 case HAL_TIM_IC_MSPINIT_CB_ID :
5909 /* Legacy weak IC Msp Init Callback */
5910 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
5911 break;
5912
5913 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5914 /* Legacy weak IC Msp DeInit Callback */
5915 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
5916 break;
5917
5918 case HAL_TIM_OC_MSPINIT_CB_ID :
5919 /* Legacy weak OC Msp Init Callback */
5920 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
5921 break;
5922
5923 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5924 /* Legacy weak OC Msp DeInit Callback */
5925 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
5926 break;
5927
5928 case HAL_TIM_PWM_MSPINIT_CB_ID :
5929 /* Legacy weak PWM Msp Init Callback */
5930 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
5931 break;
5932
5933 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5934 /* Legacy weak PWM Msp DeInit Callback */
5935 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
5936 break;
5937
5938 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5939 /* Legacy weak One Pulse Msp Init Callback */
5940 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
5941 break;
5942
5943 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5944 /* Legacy weak One Pulse Msp DeInit Callback */
5945 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
5946 break;
5947
5948 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5949 /* Legacy weak Encoder Msp Init Callback */
5950 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
5951 break;
5952
5953 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5954 /* Legacy weak Encoder Msp DeInit Callback */
5955 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
5956 break;
5957
5958 default :
5959 /* Return error status */
5960 status = HAL_ERROR;
5961 break;
5962 }
5963 }
5964 else
5965 {
5966 /* Return error status */
5967 status = HAL_ERROR;
5968 }
5969
5970 return status;
5971 }
5972 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5973
5974 /**
5975 * @}
5976 */
5977
5978 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
5979 * @brief TIM Peripheral State functions
5980 *
5981 @verbatim
5982 ==============================================================================
5983 ##### Peripheral State functions #####
5984 ==============================================================================
5985 [..]
5986 This subsection permits to get in run-time the status of the peripheral
5987 and the data flow.
5988
5989 @endverbatim
5990 * @{
5991 */
5992
5993 /**
5994 * @brief Return the TIM Base handle state.
5995 * @param htim TIM Base handle
5996 * @retval HAL state
5997 */
HAL_TIM_Base_GetState(const TIM_HandleTypeDef * htim)5998 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
5999 {
6000 return htim->State;
6001 }
6002
6003 /**
6004 * @brief Return the TIM OC handle state.
6005 * @param htim TIM Output Compare handle
6006 * @retval HAL state
6007 */
HAL_TIM_OC_GetState(const TIM_HandleTypeDef * htim)6008 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6009 {
6010 return htim->State;
6011 }
6012
6013 /**
6014 * @brief Return the TIM PWM handle state.
6015 * @param htim TIM handle
6016 * @retval HAL state
6017 */
HAL_TIM_PWM_GetState(const TIM_HandleTypeDef * htim)6018 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6019 {
6020 return htim->State;
6021 }
6022
6023 /**
6024 * @brief Return the TIM Input Capture handle state.
6025 * @param htim TIM IC handle
6026 * @retval HAL state
6027 */
HAL_TIM_IC_GetState(const TIM_HandleTypeDef * htim)6028 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6029 {
6030 return htim->State;
6031 }
6032
6033 /**
6034 * @brief Return the TIM One Pulse Mode handle state.
6035 * @param htim TIM OPM handle
6036 * @retval HAL state
6037 */
HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef * htim)6038 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6039 {
6040 return htim->State;
6041 }
6042
6043 /**
6044 * @brief Return the TIM Encoder Mode handle state.
6045 * @param htim TIM Encoder Interface handle
6046 * @retval HAL state
6047 */
HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef * htim)6048 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6049 {
6050 return htim->State;
6051 }
6052
6053 /**
6054 * @brief Return the TIM Encoder Mode handle state.
6055 * @param htim TIM handle
6056 * @retval Active channel
6057 */
HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef * htim)6058 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6059 {
6060 return htim->Channel;
6061 }
6062
6063 /**
6064 * @brief Return actual state of the TIM channel.
6065 * @param htim TIM handle
6066 * @param Channel TIM Channel
6067 * This parameter can be one of the following values:
6068 * @arg TIM_CHANNEL_1: TIM Channel 1
6069 * @arg TIM_CHANNEL_2: TIM Channel 2
6070 * @arg TIM_CHANNEL_3: TIM Channel 3
6071 * @arg TIM_CHANNEL_4: TIM Channel 4
6072 * @arg TIM_CHANNEL_5: TIM Channel 5
6073 * @arg TIM_CHANNEL_6: TIM Channel 6
6074 * @retval TIM Channel state
6075 */
HAL_TIM_GetChannelState(const TIM_HandleTypeDef * htim,uint32_t Channel)6076 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
6077 {
6078 HAL_TIM_ChannelStateTypeDef channel_state;
6079
6080 /* Check the parameters */
6081 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6082
6083 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6084
6085 return channel_state;
6086 }
6087
6088 /**
6089 * @brief Return actual state of a DMA burst operation.
6090 * @param htim TIM handle
6091 * @retval DMA burst state
6092 */
HAL_TIM_DMABurstState(const TIM_HandleTypeDef * htim)6093 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6094 {
6095 /* Check the parameters */
6096 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6097
6098 return htim->DMABurstState;
6099 }
6100
6101 /**
6102 * @}
6103 */
6104
6105 /**
6106 * @}
6107 */
6108
6109 /** @defgroup TIM_Private_Functions TIM Private Functions
6110 * @{
6111 */
6112
6113 /**
6114 * @brief TIM DMA error callback
6115 * @param hdma pointer to DMA handle.
6116 * @retval None
6117 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6118 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6119 {
6120 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6121
6122 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6123 {
6124 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6125 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6126 }
6127 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6128 {
6129 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6130 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6131 }
6132 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6133 {
6134 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6135 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6136 }
6137 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6138 {
6139 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6140 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6141 }
6142 else
6143 {
6144 htim->State = HAL_TIM_STATE_READY;
6145 }
6146
6147 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6148 htim->ErrorCallback(htim);
6149 #else
6150 HAL_TIM_ErrorCallback(htim);
6151 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6152
6153 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6154 }
6155
6156 /**
6157 * @brief TIM DMA Delay Pulse complete callback.
6158 * @param hdma pointer to DMA handle.
6159 * @retval None
6160 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)6161 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6162 {
6163 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6164
6165 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6166 {
6167 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6168
6169 if (hdma->Init.Mode == DMA_NORMAL)
6170 {
6171 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6172 }
6173 }
6174 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6175 {
6176 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6177
6178 if (hdma->Init.Mode == DMA_NORMAL)
6179 {
6180 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6181 }
6182 }
6183 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6184 {
6185 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6186
6187 if (hdma->Init.Mode == DMA_NORMAL)
6188 {
6189 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6190 }
6191 }
6192 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6193 {
6194 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6195
6196 if (hdma->Init.Mode == DMA_NORMAL)
6197 {
6198 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6199 }
6200 }
6201 else
6202 {
6203 /* nothing to do */
6204 }
6205
6206 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6207 htim->PWM_PulseFinishedCallback(htim);
6208 #else
6209 HAL_TIM_PWM_PulseFinishedCallback(htim);
6210 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6211
6212 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6213 }
6214
6215 /**
6216 * @brief TIM DMA Delay Pulse half complete callback.
6217 * @param hdma pointer to DMA handle.
6218 * @retval None
6219 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)6220 static void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6221 {
6222 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6223
6224 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6225 {
6226 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6227 }
6228 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6229 {
6230 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6231 }
6232 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6233 {
6234 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6235 }
6236 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6237 {
6238 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6239 }
6240 else
6241 {
6242 /* nothing to do */
6243 }
6244
6245 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6246 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6247 #else
6248 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6249 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6250
6251 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6252 }
6253
6254 /**
6255 * @brief TIM DMA Capture complete callback.
6256 * @param hdma pointer to DMA handle.
6257 * @retval None
6258 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)6259 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6260 {
6261 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6262
6263 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6264 {
6265 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6266
6267 if (hdma->Init.Mode == DMA_NORMAL)
6268 {
6269 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6270 }
6271 }
6272 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6273 {
6274 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6275
6276 if (hdma->Init.Mode == DMA_NORMAL)
6277 {
6278 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6279 }
6280 }
6281 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6282 {
6283 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6284
6285 if (hdma->Init.Mode == DMA_NORMAL)
6286 {
6287 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6288 }
6289 }
6290 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6291 {
6292 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6293
6294 if (hdma->Init.Mode == DMA_NORMAL)
6295 {
6296 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6297 }
6298 }
6299 else
6300 {
6301 /* nothing to do */
6302 }
6303
6304 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6305 htim->IC_CaptureCallback(htim);
6306 #else
6307 HAL_TIM_IC_CaptureCallback(htim);
6308 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6309
6310 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6311 }
6312
6313 /**
6314 * @brief TIM DMA Capture half complete callback.
6315 * @param hdma pointer to DMA handle.
6316 * @retval None
6317 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)6318 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6319 {
6320 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6321
6322 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6323 {
6324 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6325 }
6326 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6327 {
6328 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6329 }
6330 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6331 {
6332 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6333 }
6334 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6335 {
6336 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6337 }
6338 else
6339 {
6340 /* nothing to do */
6341 }
6342
6343 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6344 htim->IC_CaptureHalfCpltCallback(htim);
6345 #else
6346 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6347 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6348
6349 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6350 }
6351
6352 /**
6353 * @brief TIM DMA Period Elapse complete callback.
6354 * @param hdma pointer to DMA handle.
6355 * @retval None
6356 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)6357 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6358 {
6359 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6360
6361 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6362 {
6363 htim->State = HAL_TIM_STATE_READY;
6364 }
6365
6366 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6367 htim->PeriodElapsedCallback(htim);
6368 #else
6369 HAL_TIM_PeriodElapsedCallback(htim);
6370 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6371 }
6372
6373 /**
6374 * @brief TIM DMA Period Elapse half complete callback.
6375 * @param hdma pointer to DMA handle.
6376 * @retval None
6377 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)6378 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6379 {
6380 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6381
6382 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6383 htim->PeriodElapsedHalfCpltCallback(htim);
6384 #else
6385 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6386 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6387 }
6388
6389 /**
6390 * @brief TIM DMA Trigger callback.
6391 * @param hdma pointer to DMA handle.
6392 * @retval None
6393 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)6394 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6395 {
6396 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6397
6398 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
6399 {
6400 htim->State = HAL_TIM_STATE_READY;
6401 }
6402
6403 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6404 htim->TriggerCallback(htim);
6405 #else
6406 HAL_TIM_TriggerCallback(htim);
6407 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6408 }
6409
6410 /**
6411 * @brief TIM DMA Trigger half complete callback.
6412 * @param hdma pointer to DMA handle.
6413 * @retval None
6414 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)6415 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6416 {
6417 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6418
6419 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6420 htim->TriggerHalfCpltCallback(htim);
6421 #else
6422 HAL_TIM_TriggerHalfCpltCallback(htim);
6423 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6424 }
6425
6426 /**
6427 * @brief Time Base configuration
6428 * @param TIMx TIM peripheral
6429 * @param Structure TIM Base configuration structure
6430 * @retval None
6431 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,const TIM_Base_InitTypeDef * Structure)6432 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
6433 {
6434 uint32_t tmpcr1;
6435 tmpcr1 = TIMx->CR1;
6436
6437 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6438 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6439 {
6440 /* Select the Counter Mode */
6441 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6442 tmpcr1 |= Structure->CounterMode;
6443 }
6444
6445 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6446 {
6447 /* Set the clock division */
6448 tmpcr1 &= ~TIM_CR1_CKD;
6449 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6450 }
6451
6452 /* Set the auto-reload preload */
6453 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6454
6455 TIMx->CR1 = tmpcr1;
6456
6457 /* Set the Autoreload value */
6458 TIMx->ARR = (uint32_t)Structure->Period ;
6459
6460 /* Set the Prescaler value */
6461 TIMx->PSC = Structure->Prescaler;
6462
6463 /* Generate an update event to reload the Prescaler
6464 and the repetition counter (only for advanced timer) value immediately */
6465 TIMx->EGR = TIM_EGR_UG;
6466 }
6467
6468 /**
6469 * @brief Timer Output Compare 1 configuration
6470 * @param TIMx to select the TIM peripheral
6471 * @param OC_Config The output configuration structure
6472 * @retval None
6473 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6474 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6475 {
6476 uint32_t tmpccmrx;
6477 uint32_t tmpccer;
6478 uint32_t tmpcr2;
6479
6480 /* Disable the Channel 1: Reset the CC1E Bit */
6481 TIMx->CCER &= ~TIM_CCER_CC1E;
6482
6483 /* Get the TIMx CCER register value */
6484 tmpccer = TIMx->CCER;
6485 /* Get the TIMx CR2 register value */
6486 tmpcr2 = TIMx->CR2;
6487
6488 /* Get the TIMx CCMR1 register value */
6489 tmpccmrx = TIMx->CCMR1;
6490
6491 /* Reset the Output Compare Mode Bits */
6492 tmpccmrx &= ~TIM_CCMR1_OC1M;
6493 tmpccmrx &= ~TIM_CCMR1_CC1S;
6494 /* Select the Output Compare Mode */
6495 tmpccmrx |= OC_Config->OCMode;
6496
6497 /* Reset the Output Polarity level */
6498 tmpccer &= ~TIM_CCER_CC1P;
6499 /* Set the Output Compare Polarity */
6500 tmpccer |= OC_Config->OCPolarity;
6501
6502 /* Write to TIMx CR2 */
6503 TIMx->CR2 = tmpcr2;
6504
6505 /* Write to TIMx CCMR1 */
6506 TIMx->CCMR1 = tmpccmrx;
6507
6508 /* Set the Capture Compare Register value */
6509 TIMx->CCR1 = OC_Config->Pulse;
6510
6511 /* Write to TIMx CCER */
6512 TIMx->CCER = tmpccer;
6513 }
6514
6515 /**
6516 * @brief Timer Output Compare 2 configuration
6517 * @param TIMx to select the TIM peripheral
6518 * @param OC_Config The output configuration structure
6519 * @retval None
6520 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6521 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6522 {
6523 uint32_t tmpccmrx;
6524 uint32_t tmpccer;
6525 uint32_t tmpcr2;
6526
6527 /* Disable the Channel 2: Reset the CC2E Bit */
6528 TIMx->CCER &= ~TIM_CCER_CC2E;
6529
6530 /* Get the TIMx CCER register value */
6531 tmpccer = TIMx->CCER;
6532 /* Get the TIMx CR2 register value */
6533 tmpcr2 = TIMx->CR2;
6534
6535 /* Get the TIMx CCMR1 register value */
6536 tmpccmrx = TIMx->CCMR1;
6537
6538 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6539 tmpccmrx &= ~TIM_CCMR1_OC2M;
6540 tmpccmrx &= ~TIM_CCMR1_CC2S;
6541
6542 /* Select the Output Compare Mode */
6543 tmpccmrx |= (OC_Config->OCMode << 8U);
6544
6545 /* Reset the Output Polarity level */
6546 tmpccer &= ~TIM_CCER_CC2P;
6547 /* Set the Output Compare Polarity */
6548 tmpccer |= (OC_Config->OCPolarity << 4U);
6549
6550 /* Write to TIMx CR2 */
6551 TIMx->CR2 = tmpcr2;
6552
6553 /* Write to TIMx CCMR1 */
6554 TIMx->CCMR1 = tmpccmrx;
6555
6556 /* Set the Capture Compare Register value */
6557 TIMx->CCR2 = OC_Config->Pulse;
6558
6559 /* Write to TIMx CCER */
6560 TIMx->CCER = tmpccer;
6561 }
6562
6563 /**
6564 * @brief Timer Output Compare 3 configuration
6565 * @param TIMx to select the TIM peripheral
6566 * @param OC_Config The output configuration structure
6567 * @retval None
6568 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6569 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6570 {
6571 uint32_t tmpccmrx;
6572 uint32_t tmpccer;
6573 uint32_t tmpcr2;
6574
6575 /* Disable the Channel 3: Reset the CC2E Bit */
6576 TIMx->CCER &= ~TIM_CCER_CC3E;
6577
6578 /* Get the TIMx CCER register value */
6579 tmpccer = TIMx->CCER;
6580 /* Get the TIMx CR2 register value */
6581 tmpcr2 = TIMx->CR2;
6582
6583 /* Get the TIMx CCMR2 register value */
6584 tmpccmrx = TIMx->CCMR2;
6585
6586 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6587 tmpccmrx &= ~TIM_CCMR2_OC3M;
6588 tmpccmrx &= ~TIM_CCMR2_CC3S;
6589 /* Select the Output Compare Mode */
6590 tmpccmrx |= OC_Config->OCMode;
6591
6592 /* Reset the Output Polarity level */
6593 tmpccer &= ~TIM_CCER_CC3P;
6594 /* Set the Output Compare Polarity */
6595 tmpccer |= (OC_Config->OCPolarity << 8U);
6596
6597 /* Write to TIMx CR2 */
6598 TIMx->CR2 = tmpcr2;
6599
6600 /* Write to TIMx CCMR2 */
6601 TIMx->CCMR2 = tmpccmrx;
6602
6603 /* Set the Capture Compare Register value */
6604 TIMx->CCR3 = OC_Config->Pulse;
6605
6606 /* Write to TIMx CCER */
6607 TIMx->CCER = tmpccer;
6608 }
6609
6610 /**
6611 * @brief Timer Output Compare 4 configuration
6612 * @param TIMx to select the TIM peripheral
6613 * @param OC_Config The output configuration structure
6614 * @retval None
6615 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)6616 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
6617 {
6618 uint32_t tmpccmrx;
6619 uint32_t tmpccer;
6620 uint32_t tmpcr2;
6621
6622 /* Disable the Channel 4: Reset the CC4E Bit */
6623 TIMx->CCER &= ~TIM_CCER_CC4E;
6624
6625 /* Get the TIMx CCER register value */
6626 tmpccer = TIMx->CCER;
6627 /* Get the TIMx CR2 register value */
6628 tmpcr2 = TIMx->CR2;
6629
6630 /* Get the TIMx CCMR2 register value */
6631 tmpccmrx = TIMx->CCMR2;
6632
6633 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6634 tmpccmrx &= ~TIM_CCMR2_OC4M;
6635 tmpccmrx &= ~TIM_CCMR2_CC4S;
6636
6637 /* Select the Output Compare Mode */
6638 tmpccmrx |= (OC_Config->OCMode << 8U);
6639
6640 /* Reset the Output Polarity level */
6641 tmpccer &= ~TIM_CCER_CC4P;
6642 /* Set the Output Compare Polarity */
6643 tmpccer |= (OC_Config->OCPolarity << 12U);
6644
6645 /* Write to TIMx CR2 */
6646 TIMx->CR2 = tmpcr2;
6647
6648 /* Write to TIMx CCMR2 */
6649 TIMx->CCMR2 = tmpccmrx;
6650
6651 /* Set the Capture Compare Register value */
6652 TIMx->CCR4 = OC_Config->Pulse;
6653
6654 /* Write to TIMx CCER */
6655 TIMx->CCER = tmpccer;
6656 }
6657
6658 /**
6659 * @brief Slave Timer configuration function
6660 * @param htim TIM handle
6661 * @param sSlaveConfig Slave timer configuration
6662 * @retval None
6663 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)6664 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
6665 const TIM_SlaveConfigTypeDef *sSlaveConfig)
6666 {
6667 HAL_StatusTypeDef status = HAL_OK;
6668 uint32_t tmpsmcr;
6669 uint32_t tmpccmr1;
6670 uint32_t tmpccer;
6671
6672 /* Get the TIMx SMCR register value */
6673 tmpsmcr = htim->Instance->SMCR;
6674
6675 /* Reset the Trigger Selection Bits */
6676 tmpsmcr &= ~TIM_SMCR_TS;
6677 /* Set the Input Trigger source */
6678 tmpsmcr |= sSlaveConfig->InputTrigger;
6679
6680 /* Reset the slave mode Bits */
6681 tmpsmcr &= ~TIM_SMCR_SMS;
6682 /* Set the slave mode */
6683 tmpsmcr |= sSlaveConfig->SlaveMode;
6684
6685 /* Write to TIMx SMCR */
6686 htim->Instance->SMCR = tmpsmcr;
6687
6688 /* Configure the trigger prescaler, filter, and polarity */
6689 switch (sSlaveConfig->InputTrigger)
6690 {
6691 case TIM_TS_ETRF:
6692 {
6693 /* Check the parameters */
6694 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
6695 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
6696 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6697 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6698 /* Configure the ETR Trigger source */
6699 TIM_ETR_SetConfig(htim->Instance,
6700 sSlaveConfig->TriggerPrescaler,
6701 sSlaveConfig->TriggerPolarity,
6702 sSlaveConfig->TriggerFilter);
6703 break;
6704 }
6705
6706 case TIM_TS_TI1F_ED:
6707 {
6708 /* Check the parameters */
6709 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6710 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6711
6712 if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
6713 {
6714 return HAL_ERROR;
6715 }
6716
6717 /* Disable the Channel 1: Reset the CC1E Bit */
6718 tmpccer = htim->Instance->CCER;
6719 htim->Instance->CCER &= ~TIM_CCER_CC1E;
6720 tmpccmr1 = htim->Instance->CCMR1;
6721
6722 /* Set the filter */
6723 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6724 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
6725
6726 /* Write to TIMx CCMR1 and CCER registers */
6727 htim->Instance->CCMR1 = tmpccmr1;
6728 htim->Instance->CCER = tmpccer;
6729 break;
6730 }
6731
6732 case TIM_TS_TI1FP1:
6733 {
6734 /* Check the parameters */
6735 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6736 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6737 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6738
6739 /* Configure TI1 Filter and Polarity */
6740 TIM_TI1_ConfigInputStage(htim->Instance,
6741 sSlaveConfig->TriggerPolarity,
6742 sSlaveConfig->TriggerFilter);
6743 break;
6744 }
6745
6746 case TIM_TS_TI2FP2:
6747 {
6748 /* Check the parameters */
6749 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6750 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6751 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6752
6753 /* Configure TI2 Filter and Polarity */
6754 TIM_TI2_ConfigInputStage(htim->Instance,
6755 sSlaveConfig->TriggerPolarity,
6756 sSlaveConfig->TriggerFilter);
6757 break;
6758 }
6759
6760 case TIM_TS_ITR0:
6761 case TIM_TS_ITR1:
6762 case TIM_TS_ITR2:
6763 case TIM_TS_ITR3:
6764 {
6765 /* Check the parameter */
6766 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6767 break;
6768 }
6769
6770 default:
6771 status = HAL_ERROR;
6772 break;
6773 }
6774
6775 return status;
6776 }
6777
6778 /**
6779 * @brief Configure the TI1 as Input.
6780 * @param TIMx to select the TIM peripheral.
6781 * @param TIM_ICPolarity The Input Polarity.
6782 * This parameter can be one of the following values:
6783 * @arg TIM_ICPOLARITY_RISING
6784 * @arg TIM_ICPOLARITY_FALLING
6785 * @arg TIM_ICPOLARITY_BOTHEDGE
6786 * @param TIM_ICSelection specifies the input to be used.
6787 * This parameter can be one of the following values:
6788 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
6789 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
6790 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
6791 * @param TIM_ICFilter Specifies the Input Capture Filter.
6792 * This parameter must be a value between 0x00 and 0x0F.
6793 * @retval None
6794 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
6795 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
6796 * protected against un-initialized filter and polarity values.
6797 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6798 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6799 uint32_t TIM_ICFilter)
6800 {
6801 uint32_t tmpccmr1;
6802 uint32_t tmpccer;
6803
6804 /* Disable the Channel 1: Reset the CC1E Bit */
6805 TIMx->CCER &= ~TIM_CCER_CC1E;
6806 tmpccmr1 = TIMx->CCMR1;
6807 tmpccer = TIMx->CCER;
6808
6809 /* Select the Input */
6810 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
6811 {
6812 tmpccmr1 &= ~TIM_CCMR1_CC1S;
6813 tmpccmr1 |= TIM_ICSelection;
6814 }
6815 else
6816 {
6817 tmpccmr1 |= TIM_CCMR1_CC1S_0;
6818 }
6819
6820 /* Set the filter */
6821 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6822 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
6823
6824 /* Select the Polarity and set the CC1E Bit */
6825 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
6826 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
6827
6828 /* Write to TIMx CCMR1 and CCER registers */
6829 TIMx->CCMR1 = tmpccmr1;
6830 TIMx->CCER = tmpccer;
6831 }
6832
6833 /**
6834 * @brief Configure the Polarity and Filter for TI1.
6835 * @param TIMx to select the TIM peripheral.
6836 * @param TIM_ICPolarity The Input Polarity.
6837 * This parameter can be one of the following values:
6838 * @arg TIM_ICPOLARITY_RISING
6839 * @arg TIM_ICPOLARITY_FALLING
6840 * @arg TIM_ICPOLARITY_BOTHEDGE
6841 * @param TIM_ICFilter Specifies the Input Capture Filter.
6842 * This parameter must be a value between 0x00 and 0x0F.
6843 * @retval None
6844 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)6845 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
6846 {
6847 uint32_t tmpccmr1;
6848 uint32_t tmpccer;
6849
6850 /* Disable the Channel 1: Reset the CC1E Bit */
6851 tmpccer = TIMx->CCER;
6852 TIMx->CCER &= ~TIM_CCER_CC1E;
6853 tmpccmr1 = TIMx->CCMR1;
6854
6855 /* Set the filter */
6856 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6857 tmpccmr1 |= (TIM_ICFilter << 4U);
6858
6859 /* Select the Polarity and set the CC1E Bit */
6860 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
6861 tmpccer |= TIM_ICPolarity;
6862
6863 /* Write to TIMx CCMR1 and CCER registers */
6864 TIMx->CCMR1 = tmpccmr1;
6865 TIMx->CCER = tmpccer;
6866 }
6867
6868 /**
6869 * @brief Configure the TI2 as Input.
6870 * @param TIMx to select the TIM peripheral
6871 * @param TIM_ICPolarity The Input Polarity.
6872 * This parameter can be one of the following values:
6873 * @arg TIM_ICPOLARITY_RISING
6874 * @arg TIM_ICPOLARITY_FALLING
6875 * @arg TIM_ICPOLARITY_BOTHEDGE
6876 * @param TIM_ICSelection specifies the input to be used.
6877 * This parameter can be one of the following values:
6878 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
6879 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
6880 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
6881 * @param TIM_ICFilter Specifies the Input Capture Filter.
6882 * This parameter must be a value between 0x00 and 0x0F.
6883 * @retval None
6884 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
6885 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
6886 * protected against un-initialized filter and polarity values.
6887 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6888 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6889 uint32_t TIM_ICFilter)
6890 {
6891 uint32_t tmpccmr1;
6892 uint32_t tmpccer;
6893
6894 /* Disable the Channel 2: Reset the CC2E Bit */
6895 TIMx->CCER &= ~TIM_CCER_CC2E;
6896 tmpccmr1 = TIMx->CCMR1;
6897 tmpccer = TIMx->CCER;
6898
6899 /* Select the Input */
6900 tmpccmr1 &= ~TIM_CCMR1_CC2S;
6901 tmpccmr1 |= (TIM_ICSelection << 8U);
6902
6903 /* Set the filter */
6904 tmpccmr1 &= ~TIM_CCMR1_IC2F;
6905 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
6906
6907 /* Select the Polarity and set the CC2E Bit */
6908 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
6909 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
6910
6911 /* Write to TIMx CCMR1 and CCER registers */
6912 TIMx->CCMR1 = tmpccmr1 ;
6913 TIMx->CCER = tmpccer;
6914 }
6915
6916 /**
6917 * @brief Configure the Polarity and Filter for TI2.
6918 * @param TIMx to select the TIM peripheral.
6919 * @param TIM_ICPolarity The Input Polarity.
6920 * This parameter can be one of the following values:
6921 * @arg TIM_ICPOLARITY_RISING
6922 * @arg TIM_ICPOLARITY_FALLING
6923 * @arg TIM_ICPOLARITY_BOTHEDGE
6924 * @param TIM_ICFilter Specifies the Input Capture Filter.
6925 * This parameter must be a value between 0x00 and 0x0F.
6926 * @retval None
6927 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)6928 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
6929 {
6930 uint32_t tmpccmr1;
6931 uint32_t tmpccer;
6932
6933 /* Disable the Channel 2: Reset the CC2E Bit */
6934 TIMx->CCER &= ~TIM_CCER_CC2E;
6935 tmpccmr1 = TIMx->CCMR1;
6936 tmpccer = TIMx->CCER;
6937
6938 /* Set the filter */
6939 tmpccmr1 &= ~TIM_CCMR1_IC2F;
6940 tmpccmr1 |= (TIM_ICFilter << 12U);
6941
6942 /* Select the Polarity and set the CC2E Bit */
6943 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
6944 tmpccer |= (TIM_ICPolarity << 4U);
6945
6946 /* Write to TIMx CCMR1 and CCER registers */
6947 TIMx->CCMR1 = tmpccmr1 ;
6948 TIMx->CCER = tmpccer;
6949 }
6950
6951 /**
6952 * @brief Configure the TI3 as Input.
6953 * @param TIMx to select the TIM peripheral
6954 * @param TIM_ICPolarity The Input Polarity.
6955 * This parameter can be one of the following values:
6956 * @arg TIM_ICPOLARITY_RISING
6957 * @arg TIM_ICPOLARITY_FALLING
6958 * @arg TIM_ICPOLARITY_BOTHEDGE
6959 * @param TIM_ICSelection specifies the input to be used.
6960 * This parameter can be one of the following values:
6961 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
6962 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
6963 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
6964 * @param TIM_ICFilter Specifies the Input Capture Filter.
6965 * This parameter must be a value between 0x00 and 0x0F.
6966 * @retval None
6967 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
6968 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
6969 * protected against un-initialized filter and polarity values.
6970 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6971 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6972 uint32_t TIM_ICFilter)
6973 {
6974 uint32_t tmpccmr2;
6975 uint32_t tmpccer;
6976
6977 /* Disable the Channel 3: Reset the CC3E Bit */
6978 TIMx->CCER &= ~TIM_CCER_CC3E;
6979 tmpccmr2 = TIMx->CCMR2;
6980 tmpccer = TIMx->CCER;
6981
6982 /* Select the Input */
6983 tmpccmr2 &= ~TIM_CCMR2_CC3S;
6984 tmpccmr2 |= TIM_ICSelection;
6985
6986 /* Set the filter */
6987 tmpccmr2 &= ~TIM_CCMR2_IC3F;
6988 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
6989
6990 /* Select the Polarity and set the CC3E Bit */
6991 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
6992 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
6993
6994 /* Write to TIMx CCMR2 and CCER registers */
6995 TIMx->CCMR2 = tmpccmr2;
6996 TIMx->CCER = tmpccer;
6997 }
6998
6999 /**
7000 * @brief Configure the TI4 as Input.
7001 * @param TIMx to select the TIM peripheral
7002 * @param TIM_ICPolarity The Input Polarity.
7003 * This parameter can be one of the following values:
7004 * @arg TIM_ICPOLARITY_RISING
7005 * @arg TIM_ICPOLARITY_FALLING
7006 * @arg TIM_ICPOLARITY_BOTHEDGE
7007 * @param TIM_ICSelection specifies the input to be used.
7008 * This parameter can be one of the following values:
7009 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7010 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7011 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7012 * @param TIM_ICFilter Specifies the Input Capture Filter.
7013 * This parameter must be a value between 0x00 and 0x0F.
7014 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7015 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7016 * protected against un-initialized filter and polarity values.
7017 * @retval None
7018 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7019 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7020 uint32_t TIM_ICFilter)
7021 {
7022 uint32_t tmpccmr2;
7023 uint32_t tmpccer;
7024
7025 /* Disable the Channel 4: Reset the CC4E Bit */
7026 TIMx->CCER &= ~TIM_CCER_CC4E;
7027 tmpccmr2 = TIMx->CCMR2;
7028 tmpccer = TIMx->CCER;
7029
7030 /* Select the Input */
7031 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7032 tmpccmr2 |= (TIM_ICSelection << 8U);
7033
7034 /* Set the filter */
7035 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7036 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7037
7038 /* Select the Polarity and set the CC4E Bit */
7039 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
7040 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
7041
7042 /* Write to TIMx CCMR2 and CCER registers */
7043 TIMx->CCMR2 = tmpccmr2;
7044 TIMx->CCER = tmpccer ;
7045 }
7046
7047 /**
7048 * @brief Selects the Input Trigger source
7049 * @param TIMx to select the TIM peripheral
7050 * @param InputTriggerSource The Input Trigger source.
7051 * This parameter can be one of the following values:
7052 * @arg TIM_TS_ITR0: Internal Trigger 0
7053 * @arg TIM_TS_ITR1: Internal Trigger 1
7054 * @arg TIM_TS_ITR2: Internal Trigger 2
7055 * @arg TIM_TS_ITR3: Internal Trigger 3
7056 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7057 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7058 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7059 * @arg TIM_TS_ETRF: External Trigger input
7060 * @retval None
7061 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)7062 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7063 {
7064 uint32_t tmpsmcr;
7065
7066 /* Get the TIMx SMCR register value */
7067 tmpsmcr = TIMx->SMCR;
7068 /* Reset the TS Bits */
7069 tmpsmcr &= ~TIM_SMCR_TS;
7070 /* Set the Input Trigger source and the slave mode*/
7071 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7072 /* Write to TIMx SMCR */
7073 TIMx->SMCR = tmpsmcr;
7074 }
7075 /**
7076 * @brief Configures the TIMx External Trigger (ETR).
7077 * @param TIMx to select the TIM peripheral
7078 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
7079 * This parameter can be one of the following values:
7080 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7081 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7082 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7083 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7084 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
7085 * This parameter can be one of the following values:
7086 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7087 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7088 * @param ExtTRGFilter External Trigger Filter.
7089 * This parameter must be a value between 0x00 and 0x0F
7090 * @retval None
7091 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)7092 static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7093 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7094 {
7095 uint32_t tmpsmcr;
7096
7097 tmpsmcr = TIMx->SMCR;
7098
7099 /* Reset the ETR Bits */
7100 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7101
7102 /* Set the Prescaler, the Filter value and the Polarity */
7103 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7104
7105 /* Write to TIMx SMCR */
7106 TIMx->SMCR = tmpsmcr;
7107 }
7108
7109 /**
7110 * @brief Enables or disables the TIM Capture Compare Channel x.
7111 * @param TIMx to select the TIM peripheral
7112 * @param Channel specifies the TIM Channel
7113 * This parameter can be one of the following values:
7114 * @arg TIM_CHANNEL_1: TIM Channel 1
7115 * @arg TIM_CHANNEL_2: TIM Channel 2
7116 * @arg TIM_CHANNEL_3: TIM Channel 3
7117 * @arg TIM_CHANNEL_4: TIM Channel 4
7118 * @param ChannelState specifies the TIM Channel CCxE bit new state.
7119 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7120 * @retval None
7121 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)7122 static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7123 {
7124 uint32_t tmp;
7125
7126 /* Check the parameters */
7127 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7128 assert_param(IS_TIM_CHANNELS(Channel));
7129
7130 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7131
7132 /* Reset the CCxE Bit */
7133 TIMx->CCER &= ~tmp;
7134
7135 /* Set or reset the CCxE Bit */
7136 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7137 }
7138
7139 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7140 /**
7141 * @brief Reset interrupt callbacks to the legacy weak callbacks.
7142 * @param htim pointer to a TIM_HandleTypeDef structure that contains
7143 * the configuration information for TIM module.
7144 * @retval None
7145 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)7146 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7147 {
7148 /* Reset the TIM callback to the legacy weak callbacks */
7149 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
7150 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
7151 htim->TriggerCallback = HAL_TIM_TriggerCallback;
7152 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
7153 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
7154 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
7155 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
7156 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
7157 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
7158 htim->ErrorCallback = HAL_TIM_ErrorCallback;
7159 }
7160 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7161
7162 /**
7163 * @}
7164 */
7165
7166 #endif /* HAL_TIM_MODULE_ENABLED */
7167 /**
7168 * @}
7169 */
7170
7171 /**
7172 * @}
7173 */
7174
