1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32h7xx_ll_tim.h"
22 #include "stm32h7xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
71
72 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
73 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
74
75 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
76 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
77
78 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
79 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
80
81 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
82 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
83 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
84
85 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
86 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
87 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
89
90 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
106
107 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
108 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
109 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
110
111 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
112 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
113 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
114
115 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
116 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
117
118 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
119 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
120
121 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
122 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
123
124 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
125 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
126 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
127 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
128
129 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
130 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
131
132 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
133 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
134
135 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
136 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
137 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
138 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
139 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
140 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
141 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
142 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
143 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
151 #if defined(TIM_BDTR_BKBID)
152
153 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
154 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
155 #endif /* TIM_BDTR_BKBID */
156
157 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
158 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
159
160 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
161 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
162
163 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
164 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
165 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
166 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
167 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
168 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
169 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
177 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
178 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
179 #if defined(TIM_BDTR_BKBID)
180
181 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
182 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
183 #endif /*TIM_BDTR_BKBID */
184
185 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
186 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
187 /**
188 * @}
189 */
190
191
192 /* Private function prototypes -----------------------------------------------*/
193 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
194 * @{
195 */
196 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
197 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
198 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
199 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
200 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
201 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
202 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
203 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
204 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
205 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
206 /**
207 * @}
208 */
209
210 /* Exported functions --------------------------------------------------------*/
211 /** @addtogroup TIM_LL_Exported_Functions
212 * @{
213 */
214
215 /** @addtogroup TIM_LL_EF_Init
216 * @{
217 */
218
219 /**
220 * @brief Set TIMx registers to their reset values.
221 * @param TIMx Timer instance
222 * @retval An ErrorStatus enumeration value:
223 * - SUCCESS: TIMx registers are de-initialized
224 * - ERROR: invalid TIMx instance
225 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)226 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
227 {
228 ErrorStatus result = SUCCESS;
229
230 /* Check the parameters */
231 assert_param(IS_TIM_INSTANCE(TIMx));
232
233 if (TIMx == TIM1)
234 {
235 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
236 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
237 }
238 #if defined(TIM2)
239 else if (TIMx == TIM2)
240 {
241 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
242 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
243 }
244 #endif /* TIM2 */
245 #if defined(TIM3)
246 else if (TIMx == TIM3)
247 {
248 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
249 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
250 }
251 #endif /* TIM3 */
252 #if defined(TIM4)
253 else if (TIMx == TIM4)
254 {
255 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
256 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
257 }
258 #endif /* TIM4 */
259 #if defined(TIM5)
260 else if (TIMx == TIM5)
261 {
262 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
263 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
264 }
265 #endif /* TIM5 */
266 #if defined(TIM6)
267 else if (TIMx == TIM6)
268 {
269 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
270 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
271 }
272 #endif /* TIM6 */
273 #if defined (TIM7)
274 else if (TIMx == TIM7)
275 {
276 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
277 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
278 }
279 #endif /* TIM7 */
280 #if defined(TIM8)
281 else if (TIMx == TIM8)
282 {
283 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
284 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
285 }
286 #endif /* TIM8 */
287 #if defined(TIM12)
288 else if (TIMx == TIM12)
289 {
290 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
291 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
292 }
293 #endif /* TIM12 */
294 #if defined(TIM13)
295 else if (TIMx == TIM13)
296 {
297 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
298 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
299 }
300 #endif /* TIM13 */
301 #if defined(TIM14)
302 else if (TIMx == TIM14)
303 {
304 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
305 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
306 }
307 #endif /* TIM14 */
308 #if defined(TIM15)
309 else if (TIMx == TIM15)
310 {
311 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
312 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
313 }
314 #endif /* TIM15 */
315 #if defined(TIM16)
316 else if (TIMx == TIM16)
317 {
318 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
319 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
320 }
321 #endif /* TIM16 */
322 #if defined(TIM17)
323 else if (TIMx == TIM17)
324 {
325 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
326 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
327 }
328 #endif /* TIM17 */
329 else
330 {
331 result = ERROR;
332 }
333
334 return result;
335 }
336
337 /**
338 * @brief Set the fields of the time base unit configuration data structure
339 * to their default values.
340 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
341 * @retval None
342 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)343 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
344 {
345 /* Set the default configuration */
346 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
347 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
348 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
349 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
350 TIM_InitStruct->RepetitionCounter = 0x00000000U;
351 }
352
353 /**
354 * @brief Configure the TIMx time base unit.
355 * @param TIMx Timer Instance
356 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
357 * (TIMx time base unit configuration data structure)
358 * @retval An ErrorStatus enumeration value:
359 * - SUCCESS: TIMx registers are de-initialized
360 * - ERROR: not applicable
361 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)362 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
363 {
364 uint32_t tmpcr1;
365
366 /* Check the parameters */
367 assert_param(IS_TIM_INSTANCE(TIMx));
368 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
369 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
370
371 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
372
373 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
374 {
375 /* Select the Counter Mode */
376 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
377 }
378
379 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
380 {
381 /* Set the clock division */
382 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
383 }
384
385 /* Write to TIMx CR1 */
386 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
387
388 /* Set the Autoreload value */
389 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
390
391 /* Set the Prescaler value */
392 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
393
394 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
395 {
396 /* Set the Repetition Counter value */
397 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
398 }
399
400 /* Generate an update event to reload the Prescaler
401 and the repetition counter value (if applicable) immediately */
402 LL_TIM_GenerateEvent_UPDATE(TIMx);
403
404 return SUCCESS;
405 }
406
407 /**
408 * @brief Set the fields of the TIMx output channel configuration data
409 * structure to their default values.
410 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
411 * (the output channel configuration data structure)
412 * @retval None
413 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)414 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
415 {
416 /* Set the default configuration */
417 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
418 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
419 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
420 TIM_OC_InitStruct->CompareValue = 0x00000000U;
421 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
422 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
423 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
424 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
425 }
426
427 /**
428 * @brief Configure the TIMx output channel.
429 * @param TIMx Timer Instance
430 * @param Channel This parameter can be one of the following values:
431 * @arg @ref LL_TIM_CHANNEL_CH1
432 * @arg @ref LL_TIM_CHANNEL_CH2
433 * @arg @ref LL_TIM_CHANNEL_CH3
434 * @arg @ref LL_TIM_CHANNEL_CH4
435 * @arg @ref LL_TIM_CHANNEL_CH5
436 * @arg @ref LL_TIM_CHANNEL_CH6
437 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
438 * data structure)
439 * @retval An ErrorStatus enumeration value:
440 * - SUCCESS: TIMx output channel is initialized
441 * - ERROR: TIMx output channel is not initialized
442 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)443 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
444 {
445 ErrorStatus result = ERROR;
446
447 switch (Channel)
448 {
449 case LL_TIM_CHANNEL_CH1:
450 result = OC1Config(TIMx, TIM_OC_InitStruct);
451 break;
452 case LL_TIM_CHANNEL_CH2:
453 result = OC2Config(TIMx, TIM_OC_InitStruct);
454 break;
455 case LL_TIM_CHANNEL_CH3:
456 result = OC3Config(TIMx, TIM_OC_InitStruct);
457 break;
458 case LL_TIM_CHANNEL_CH4:
459 result = OC4Config(TIMx, TIM_OC_InitStruct);
460 break;
461 case LL_TIM_CHANNEL_CH5:
462 result = OC5Config(TIMx, TIM_OC_InitStruct);
463 break;
464 case LL_TIM_CHANNEL_CH6:
465 result = OC6Config(TIMx, TIM_OC_InitStruct);
466 break;
467 default:
468 break;
469 }
470
471 return result;
472 }
473
474 /**
475 * @brief Set the fields of the TIMx input channel configuration data
476 * structure to their default values.
477 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
478 * data structure)
479 * @retval None
480 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)481 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
482 {
483 /* Set the default configuration */
484 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
485 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
486 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
487 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
488 }
489
490 /**
491 * @brief Configure the TIMx input channel.
492 * @param TIMx Timer Instance
493 * @param Channel This parameter can be one of the following values:
494 * @arg @ref LL_TIM_CHANNEL_CH1
495 * @arg @ref LL_TIM_CHANNEL_CH2
496 * @arg @ref LL_TIM_CHANNEL_CH3
497 * @arg @ref LL_TIM_CHANNEL_CH4
498 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
499 * structure)
500 * @retval An ErrorStatus enumeration value:
501 * - SUCCESS: TIMx output channel is initialized
502 * - ERROR: TIMx output channel is not initialized
503 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)504 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
505 {
506 ErrorStatus result = ERROR;
507
508 switch (Channel)
509 {
510 case LL_TIM_CHANNEL_CH1:
511 result = IC1Config(TIMx, TIM_IC_InitStruct);
512 break;
513 case LL_TIM_CHANNEL_CH2:
514 result = IC2Config(TIMx, TIM_IC_InitStruct);
515 break;
516 case LL_TIM_CHANNEL_CH3:
517 result = IC3Config(TIMx, TIM_IC_InitStruct);
518 break;
519 case LL_TIM_CHANNEL_CH4:
520 result = IC4Config(TIMx, TIM_IC_InitStruct);
521 break;
522 default:
523 break;
524 }
525
526 return result;
527 }
528
529 /**
530 * @brief Fills each TIM_EncoderInitStruct field with its default value
531 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
532 * configuration data structure)
533 * @retval None
534 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)535 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
536 {
537 /* Set the default configuration */
538 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
539 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
540 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
541 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
542 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
543 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
544 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
545 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
546 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
547 }
548
549 /**
550 * @brief Configure the encoder interface of the timer instance.
551 * @param TIMx Timer Instance
552 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
553 * configuration data structure)
554 * @retval An ErrorStatus enumeration value:
555 * - SUCCESS: TIMx registers are de-initialized
556 * - ERROR: not applicable
557 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)558 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
559 {
560 uint32_t tmpccmr1;
561 uint32_t tmpccer;
562
563 /* Check the parameters */
564 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
565 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
566 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
567 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
568 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
569 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
570 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
571 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
572 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
573 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
574
575 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
576 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
577
578 /* Get the TIMx CCMR1 register value */
579 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
580
581 /* Get the TIMx CCER register value */
582 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
583
584 /* Configure TI1 */
585 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
586 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
587 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
588 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
589
590 /* Configure TI2 */
591 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
592 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
593 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
594 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
595
596 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
597 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
598 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
599 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
600 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
601
602 /* Set encoder mode */
603 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
604
605 /* Write to TIMx CCMR1 */
606 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
607
608 /* Write to TIMx CCER */
609 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
610
611 return SUCCESS;
612 }
613
614 /**
615 * @brief Set the fields of the TIMx Hall sensor interface configuration data
616 * structure to their default values.
617 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
618 * configuration data structure)
619 * @retval None
620 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)621 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
622 {
623 /* Set the default configuration */
624 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
625 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
626 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
627 TIM_HallSensorInitStruct->CommutationDelay = 0U;
628 }
629
630 /**
631 * @brief Configure the Hall sensor interface of the timer instance.
632 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
633 * to the TI1 input channel
634 * @note TIMx slave mode controller is configured in reset mode.
635 Selected internal trigger is TI1F_ED.
636 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
637 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
638 * between 2 changes on the inputs. It gives information about motor speed.
639 * @note Channel 2 is configured in output PWM 2 mode.
640 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
641 * @note OC2REF is selected as trigger output on TRGO.
642 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
643 * when TIMx operates in Hall sensor interface mode.
644 * @param TIMx Timer Instance
645 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
646 * interface configuration data structure)
647 * @retval An ErrorStatus enumeration value:
648 * - SUCCESS: TIMx registers are de-initialized
649 * - ERROR: not applicable
650 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)651 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
652 {
653 uint32_t tmpcr2;
654 uint32_t tmpccmr1;
655 uint32_t tmpccer;
656 uint32_t tmpsmcr;
657
658 /* Check the parameters */
659 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
660 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
661 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
662 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
663
664 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
665 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
666
667 /* Get the TIMx CR2 register value */
668 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
669
670 /* Get the TIMx CCMR1 register value */
671 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
672
673 /* Get the TIMx CCER register value */
674 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
675
676 /* Get the TIMx SMCR register value */
677 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
678
679 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
680 tmpcr2 |= TIM_CR2_TI1S;
681
682 /* OC2REF signal is used as trigger output (TRGO) */
683 tmpcr2 |= LL_TIM_TRGO_OC2REF;
684
685 /* Configure the slave mode controller */
686 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
687 tmpsmcr |= LL_TIM_TS_TI1F_ED;
688 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
689
690 /* Configure input channel 1 */
691 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
692 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
693 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
694 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
695
696 /* Configure input channel 2 */
697 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
698 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
699
700 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
701 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
702 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
703 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
704
705 /* Write to TIMx CR2 */
706 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
707
708 /* Write to TIMx SMCR */
709 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
710
711 /* Write to TIMx CCMR1 */
712 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
713
714 /* Write to TIMx CCER */
715 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
716
717 /* Write to TIMx CCR2 */
718 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
719
720 return SUCCESS;
721 }
722
723 /**
724 * @brief Set the fields of the Break and Dead Time configuration data structure
725 * to their default values.
726 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
727 * data structure)
728 * @retval None
729 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)730 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
731 {
732 /* Set the default configuration */
733 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
734 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
735 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
736 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
737 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
738 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
739 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
740 #if defined(TIM_BDTR_BKBID)
741 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
742 #endif /* TIM_BDTR_BKBID */
743 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
744 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
745 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
746 #if defined(TIM_BDTR_BKBID)
747 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
748 #endif /*TIM_BDTR_BKBID */
749 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
750 }
751
752 /**
753 * @brief Configure the Break and Dead Time feature of the timer instance.
754 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
755 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
756 * can be necessary to configure all of them during the first write access to
757 * the TIMx_BDTR register.
758 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
759 * a timer instance provides a break input.
760 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
761 * a timer instance provides a second break input.
762 * @param TIMx Timer Instance
763 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
764 * data structure)
765 * @retval An ErrorStatus enumeration value:
766 * - SUCCESS: Break and Dead Time is initialized
767 * - ERROR: not applicable
768 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)769 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
770 {
771 uint32_t tmpbdtr = 0;
772
773 /* Check the parameters */
774 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
775 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
776 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
777 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
778 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
779 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
780 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
781 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
782 #if defined(TIM_BDTR_BKBID)
783 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
784 #endif /*TIM_BDTR_BKBID */
785
786 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
787 the OSSI State, the dead time value and the Automatic Output Enable Bit */
788
789 /* Set the BDTR bits */
790 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
791 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
792 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
793 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
794 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
795 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
796 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
797 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
798 #if defined(TIM_BDTR_BKBID)
799 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
800 #endif /*TIM_BDTR_BKBID */
801
802 if (IS_TIM_BKIN2_INSTANCE(TIMx))
803 {
804 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
805 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
806 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
807 #if defined(TIM_BDTR_BKBID)
808 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
809 #endif /*TIM_BDTR_BKBID */
810
811 /* Set the BREAK2 input related BDTR bit-fields */
812 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
813 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
814 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
815 #if defined(TIM_BDTR_BKBID)
816 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
817 #endif /*TIM_BDTR_BKBID */
818 }
819
820 /* Set TIMx_BDTR */
821 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
822
823 return SUCCESS;
824 }
825 /**
826 * @}
827 */
828
829 /**
830 * @}
831 */
832
833 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
834 * @brief Private functions
835 * @{
836 */
837 /**
838 * @brief Configure the TIMx output channel 1.
839 * @param TIMx Timer Instance
840 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
841 * @retval An ErrorStatus enumeration value:
842 * - SUCCESS: TIMx registers are de-initialized
843 * - ERROR: not applicable
844 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)845 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
846 {
847 uint32_t tmpccmr1;
848 uint32_t tmpccer;
849 uint32_t tmpcr2;
850
851 /* Check the parameters */
852 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
853 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
854 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
855 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
856
857 /* Disable the Channel 1: Reset the CC1E Bit */
858 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
859
860 /* Get the TIMx CCER register value */
861 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
862
863 /* Get the TIMx CR2 register value */
864 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
865
866 /* Get the TIMx CCMR1 register value */
867 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
868
869 /* Reset Capture/Compare selection Bits */
870 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
871
872 /* Set the Output Compare Mode */
873 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
874
875 /* Set the Output Compare Polarity */
876 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
877
878 /* Set the Output State */
879 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
880
881 if (IS_TIM_BREAK_INSTANCE(TIMx))
882 {
883 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
884 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
885 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
886 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
887
888 /* Set the complementary output Polarity */
889 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
890
891 /* Set the complementary output State */
892 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
893
894 /* Set the Output Idle state */
895 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
896
897 /* Set the complementary output Idle state */
898 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
899 }
900
901 /* Write to TIMx CR2 */
902 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
903
904 /* Write to TIMx CCMR1 */
905 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
906
907 /* Set the Capture Compare Register value */
908 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
909
910 /* Write to TIMx CCER */
911 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
912
913 return SUCCESS;
914 }
915
916 /**
917 * @brief Configure the TIMx output channel 2.
918 * @param TIMx Timer Instance
919 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
920 * @retval An ErrorStatus enumeration value:
921 * - SUCCESS: TIMx registers are de-initialized
922 * - ERROR: not applicable
923 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)924 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
925 {
926 uint32_t tmpccmr1;
927 uint32_t tmpccer;
928 uint32_t tmpcr2;
929
930 /* Check the parameters */
931 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
932 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
933 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
934 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
935
936 /* Disable the Channel 2: Reset the CC2E Bit */
937 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
938
939 /* Get the TIMx CCER register value */
940 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
941
942 /* Get the TIMx CR2 register value */
943 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
944
945 /* Get the TIMx CCMR1 register value */
946 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
947
948 /* Reset Capture/Compare selection Bits */
949 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
950
951 /* Select the Output Compare Mode */
952 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
953
954 /* Set the Output Compare Polarity */
955 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
956
957 /* Set the Output State */
958 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
959
960 if (IS_TIM_BREAK_INSTANCE(TIMx))
961 {
962 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
963 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
964 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
965 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
966
967 /* Set the complementary output Polarity */
968 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
969
970 /* Set the complementary output State */
971 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
972
973 /* Set the Output Idle state */
974 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
975
976 /* Set the complementary output Idle state */
977 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
978 }
979
980 /* Write to TIMx CR2 */
981 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
982
983 /* Write to TIMx CCMR1 */
984 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
985
986 /* Set the Capture Compare Register value */
987 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
988
989 /* Write to TIMx CCER */
990 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
991
992 return SUCCESS;
993 }
994
995 /**
996 * @brief Configure the TIMx output channel 3.
997 * @param TIMx Timer Instance
998 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
999 * @retval An ErrorStatus enumeration value:
1000 * - SUCCESS: TIMx registers are de-initialized
1001 * - ERROR: not applicable
1002 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1003 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1004 {
1005 uint32_t tmpccmr2;
1006 uint32_t tmpccer;
1007 uint32_t tmpcr2;
1008
1009 /* Check the parameters */
1010 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1011 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1012 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1013 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1014
1015 /* Disable the Channel 3: Reset the CC3E Bit */
1016 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
1017
1018 /* Get the TIMx CCER register value */
1019 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1020
1021 /* Get the TIMx CR2 register value */
1022 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1023
1024 /* Get the TIMx CCMR2 register value */
1025 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1026
1027 /* Reset Capture/Compare selection Bits */
1028 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
1029
1030 /* Select the Output Compare Mode */
1031 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
1032
1033 /* Set the Output Compare Polarity */
1034 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
1035
1036 /* Set the Output State */
1037 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1038
1039 if (IS_TIM_BREAK_INSTANCE(TIMx))
1040 {
1041 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1042 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1043 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1044 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1045
1046 /* Set the complementary output Polarity */
1047 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1048
1049 /* Set the complementary output State */
1050 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1051
1052 /* Set the Output Idle state */
1053 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1054
1055 /* Set the complementary output Idle state */
1056 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1057 }
1058
1059 /* Write to TIMx CR2 */
1060 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1061
1062 /* Write to TIMx CCMR2 */
1063 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1064
1065 /* Set the Capture Compare Register value */
1066 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1067
1068 /* Write to TIMx CCER */
1069 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1070
1071 return SUCCESS;
1072 }
1073
1074 /**
1075 * @brief Configure the TIMx output channel 4.
1076 * @param TIMx Timer Instance
1077 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1078 * @retval An ErrorStatus enumeration value:
1079 * - SUCCESS: TIMx registers are de-initialized
1080 * - ERROR: not applicable
1081 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1082 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1083 {
1084 uint32_t tmpccmr2;
1085 uint32_t tmpccer;
1086 uint32_t tmpcr2;
1087
1088 /* Check the parameters */
1089 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1090 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1091 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1092 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1093
1094 /* Disable the Channel 4: Reset the CC4E Bit */
1095 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1096
1097 /* Get the TIMx CCER register value */
1098 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1099
1100 /* Get the TIMx CR2 register value */
1101 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1102
1103 /* Get the TIMx CCMR2 register value */
1104 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1105
1106 /* Reset Capture/Compare selection Bits */
1107 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1108
1109 /* Select the Output Compare Mode */
1110 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1111
1112 /* Set the Output Compare Polarity */
1113 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1114
1115 /* Set the Output State */
1116 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1117
1118 if (IS_TIM_BREAK_INSTANCE(TIMx))
1119 {
1120 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1121
1122 /* Set the Output Idle state */
1123 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1124 }
1125
1126 /* Write to TIMx CR2 */
1127 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1128
1129 /* Write to TIMx CCMR2 */
1130 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1131
1132 /* Set the Capture Compare Register value */
1133 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1134
1135 /* Write to TIMx CCER */
1136 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1137
1138 return SUCCESS;
1139 }
1140
1141 /**
1142 * @brief Configure the TIMx output channel 5.
1143 * @param TIMx Timer Instance
1144 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1145 * @retval An ErrorStatus enumeration value:
1146 * - SUCCESS: TIMx registers are de-initialized
1147 * - ERROR: not applicable
1148 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1149 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1150 {
1151 uint32_t tmpccmr3;
1152 uint32_t tmpccer;
1153
1154 /* Check the parameters */
1155 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1156 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1157 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1158 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1159 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1160 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1161
1162 /* Disable the Channel 5: Reset the CC5E Bit */
1163 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1164
1165 /* Get the TIMx CCER register value */
1166 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1167
1168 /* Get the TIMx CCMR3 register value */
1169 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1170
1171 /* Select the Output Compare Mode */
1172 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1173
1174 /* Set the Output Compare Polarity */
1175 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1176
1177 /* Set the Output State */
1178 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1179
1180 if (IS_TIM_BREAK_INSTANCE(TIMx))
1181 {
1182 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1183 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1184
1185 /* Set the Output Idle state */
1186 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1187
1188 }
1189
1190 /* Write to TIMx CCMR3 */
1191 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1192
1193 /* Set the Capture Compare Register value */
1194 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1195
1196 /* Write to TIMx CCER */
1197 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1198
1199 return SUCCESS;
1200 }
1201
1202 /**
1203 * @brief Configure the TIMx output channel 6.
1204 * @param TIMx Timer Instance
1205 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1206 * @retval An ErrorStatus enumeration value:
1207 * - SUCCESS: TIMx registers are de-initialized
1208 * - ERROR: not applicable
1209 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1210 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1211 {
1212 uint32_t tmpccmr3;
1213 uint32_t tmpccer;
1214
1215 /* Check the parameters */
1216 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1217 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1218 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1219 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1220 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1221 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1222
1223 /* Disable the Channel 5: Reset the CC6E Bit */
1224 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1225
1226 /* Get the TIMx CCER register value */
1227 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1228
1229 /* Get the TIMx CCMR3 register value */
1230 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1231
1232 /* Select the Output Compare Mode */
1233 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1234
1235 /* Set the Output Compare Polarity */
1236 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1237
1238 /* Set the Output State */
1239 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1240
1241 if (IS_TIM_BREAK_INSTANCE(TIMx))
1242 {
1243 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1244 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1245
1246 /* Set the Output Idle state */
1247 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1248 }
1249
1250 /* Write to TIMx CCMR3 */
1251 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1252
1253 /* Set the Capture Compare Register value */
1254 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1255
1256 /* Write to TIMx CCER */
1257 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1258
1259 return SUCCESS;
1260 }
1261
1262 /**
1263 * @brief Configure the TIMx input channel 1.
1264 * @param TIMx Timer Instance
1265 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1266 * @retval An ErrorStatus enumeration value:
1267 * - SUCCESS: TIMx registers are de-initialized
1268 * - ERROR: not applicable
1269 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1270 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1271 {
1272 /* Check the parameters */
1273 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1274 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1275 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1276 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1277 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1278
1279 /* Disable the Channel 1: Reset the CC1E Bit */
1280 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1281
1282 /* Select the Input and set the filter and the prescaler value */
1283 MODIFY_REG(TIMx->CCMR1,
1284 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1285 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1286
1287 /* Select the Polarity and set the CC1E Bit */
1288 MODIFY_REG(TIMx->CCER,
1289 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1290 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1291
1292 return SUCCESS;
1293 }
1294
1295 /**
1296 * @brief Configure the TIMx input channel 2.
1297 * @param TIMx Timer Instance
1298 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1299 * @retval An ErrorStatus enumeration value:
1300 * - SUCCESS: TIMx registers are de-initialized
1301 * - ERROR: not applicable
1302 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1303 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1304 {
1305 /* Check the parameters */
1306 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1307 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1308 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1309 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1310 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1311
1312 /* Disable the Channel 2: Reset the CC2E Bit */
1313 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1314
1315 /* Select the Input and set the filter and the prescaler value */
1316 MODIFY_REG(TIMx->CCMR1,
1317 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1318 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1319
1320 /* Select the Polarity and set the CC2E Bit */
1321 MODIFY_REG(TIMx->CCER,
1322 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1323 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1324
1325 return SUCCESS;
1326 }
1327
1328 /**
1329 * @brief Configure the TIMx input channel 3.
1330 * @param TIMx Timer Instance
1331 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1332 * @retval An ErrorStatus enumeration value:
1333 * - SUCCESS: TIMx registers are de-initialized
1334 * - ERROR: not applicable
1335 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1336 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1337 {
1338 /* Check the parameters */
1339 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1340 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1341 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1342 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1343 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1344
1345 /* Disable the Channel 3: Reset the CC3E Bit */
1346 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1347
1348 /* Select the Input and set the filter and the prescaler value */
1349 MODIFY_REG(TIMx->CCMR2,
1350 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1351 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1352
1353 /* Select the Polarity and set the CC3E Bit */
1354 MODIFY_REG(TIMx->CCER,
1355 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1356 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1357
1358 return SUCCESS;
1359 }
1360
1361 /**
1362 * @brief Configure the TIMx input channel 4.
1363 * @param TIMx Timer Instance
1364 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1365 * @retval An ErrorStatus enumeration value:
1366 * - SUCCESS: TIMx registers are de-initialized
1367 * - ERROR: not applicable
1368 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1369 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1370 {
1371 /* Check the parameters */
1372 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1373 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1374 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1375 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1376 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1377
1378 /* Disable the Channel 4: Reset the CC4E Bit */
1379 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1380
1381 /* Select the Input and set the filter and the prescaler value */
1382 MODIFY_REG(TIMx->CCMR2,
1383 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1384 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1385
1386 /* Select the Polarity and set the CC4E Bit */
1387 MODIFY_REG(TIMx->CCER,
1388 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1389 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1390
1391 return SUCCESS;
1392 }
1393
1394
1395 /**
1396 * @}
1397 */
1398
1399 /**
1400 * @}
1401 */
1402
1403 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 || TIM23 || TIM24 */
1404
1405 /**
1406 * @}
1407 */
1408
1409 #endif /* USE_FULL_LL_DRIVER */
1410
1411
