1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_bdma.c
4 * @author MCD Application Team
5 * @brief BDMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32h7xx_ll_bdma.h"
23 #include "stm32h7xx_ll_bus.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (BDMA) || defined (BDMA1) || defined (BDMA2)
35
36 /** @addtogroup BDMA_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup BDMA_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_BDMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_BDMA_DIRECTION_PERIPH_TO_MEMORY) || \
48 ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH) || \
49 ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_MEMORY))
50
51 #define IS_LL_BDMA_MODE(__VALUE__) (((__VALUE__) == LL_BDMA_MODE_NORMAL) || \
52 ((__VALUE__) == LL_BDMA_MODE_CIRCULAR))
53
54 #define IS_LL_BDMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_BDMA_PERIPH_INCREMENT) || \
55 ((__VALUE__) == LL_BDMA_PERIPH_NOINCREMENT))
56
57 #define IS_LL_BDMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_BDMA_MEMORY_INCREMENT) || \
58 ((__VALUE__) == LL_BDMA_MEMORY_NOINCREMENT))
59
60 #define IS_LL_BDMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_BDMA_PDATAALIGN_BYTE) || \
61 ((__VALUE__) == LL_BDMA_PDATAALIGN_HALFWORD) || \
62 ((__VALUE__) == LL_BDMA_PDATAALIGN_WORD))
63
64 #define IS_LL_BDMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_BDMA_MDATAALIGN_BYTE) || \
65 ((__VALUE__) == LL_BDMA_MDATAALIGN_HALFWORD) || \
66 ((__VALUE__) == LL_BDMA_MDATAALIGN_WORD))
67
68 #define IS_LL_BDMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
69
70 #if defined(ADC3)
71 #define IS_LL_BDMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX2_REQ_ADC3)
72 #else
73 #define IS_LL_BDMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX2_REQ_DFSDM2_FLT0)
74 #endif /* ADC3 */
75
76 #define IS_LL_BDMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_BDMA_PRIORITY_LOW) || \
77 ((__VALUE__) == LL_BDMA_PRIORITY_MEDIUM) || \
78 ((__VALUE__) == LL_BDMA_PRIORITY_HIGH) || \
79 ((__VALUE__) == LL_BDMA_PRIORITY_VERYHIGH))
80
81 #define IS_LL_BDMA_DOUBLEBUFFER_MODE(__VALUE__) (((__VALUE__) == LL_BDMA_DOUBLEBUFFER_MODE_DISABLE) || \
82 ((__VALUE__) == LL_BDMA_DOUBLEBUFFER_MODE_ENABLE))
83
84 #define IS_LL_BDMA_DOUBLEBUFFER_TARGETMEM(__VALUE__) (((__VALUE__) == LL_BDMA_CURRENTTARGETMEM0) || \
85 ((__VALUE__) == LL_BDMA_CURRENTTARGETMEM1))
86
87 #define IS_LL_BDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == BDMA) && \
88 (((CHANNEL) == LL_BDMA_CHANNEL_0) || \
89 ((CHANNEL) == LL_BDMA_CHANNEL_1) || \
90 ((CHANNEL) == LL_BDMA_CHANNEL_2) || \
91 ((CHANNEL) == LL_BDMA_CHANNEL_3) || \
92 ((CHANNEL) == LL_BDMA_CHANNEL_4) || \
93 ((CHANNEL) == LL_BDMA_CHANNEL_5) || \
94 ((CHANNEL) == LL_BDMA_CHANNEL_6) || \
95 ((CHANNEL) == LL_BDMA_CHANNEL_7))))
96
97 /**
98 * @}
99 */
100
101 /* Private function prototypes -----------------------------------------------*/
102
103 /* Exported functions --------------------------------------------------------*/
104 /** @addtogroup BDMA_LL_Exported_Functions
105 * @{
106 */
107
108 /** @addtogroup BDMA_LL_EF_Init
109 * @{
110 */
111
112 /**
113 * @brief De-initialize the DMA registers to their default reset values.
114 * @param BDMAx BDMAx Instance
115 * @param Channel This parameter can be one of the following values:
116 * @arg @ref LL_BDMA_CHANNEL_0
117 * @arg @ref LL_BDMA_CHANNEL_1
118 * @arg @ref LL_BDMA_CHANNEL_2
119 * @arg @ref LL_BDMA_CHANNEL_3
120 * @arg @ref LL_BDMA_CHANNEL_4
121 * @arg @ref LL_BDMA_CHANNEL_5
122 * @arg @ref LL_BDMA_CHANNEL_6
123 * @arg @ref LL_BDMA_CHANNEL_7
124 * @arg @ref LL_BDMA_CHANNEL_ALL
125 * @retval An ErrorStatus enumeration value:
126 * - SUCCESS: DMA registers are de-initialized
127 * - ERROR: DMA registers are not de-initialized
128 */
LL_BDMA_DeInit(BDMA_TypeDef * BDMAx,uint32_t Channel)129 uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel)
130 {
131 BDMA_Channel_TypeDef *tmp ;
132 ErrorStatus status = SUCCESS;
133
134 /* Check the DMA Instance DMAx and Channel parameters */
135 assert_param(IS_LL_BDMA_ALL_CHANNEL_INSTANCE(BDMAx, Channel) || (Channel == LL_BDMA_CHANNEL_ALL));
136
137 if (Channel == LL_BDMA_CHANNEL_ALL)
138 {
139 if (BDMAx == BDMA)
140 {
141 /* Force reset of BDMA clock */
142 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
143
144 /* Release reset of BDMA clock */
145 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
146 }
147 else
148 {
149 status = ERROR;
150 }
151 }
152 else
153 {
154 tmp = (BDMA_Channel_TypeDef *)(__LL_BDMA_GET_CHANNEL_INSTANCE(BDMAx, Channel));
155
156 /* Disable the selected DMAx_Channely */
157 CLEAR_BIT(tmp->CCR, BDMA_CCR_EN);
158
159 /* Reset DMAx_Channely control register */
160 LL_BDMA_WriteReg(tmp, CCR, 0U);
161
162 /* Reset DMAx_Channely remaining bytes register */
163 LL_BDMA_WriteReg(tmp, CNDTR, 0U);
164
165 /* Reset DMAx_Channely peripheral address register */
166 LL_BDMA_WriteReg(tmp, CPAR, 0U);
167
168 /* Reset DMAx_Channely memory 0 address register */
169 LL_BDMA_WriteReg(tmp, CM0AR, 0U);
170
171 /* Reset DMAx_Channely memory 1 address register */
172 LL_BDMA_WriteReg(tmp, CM1AR, 0U);
173
174 /* Reset Request register field for BDMAx Channel */
175 LL_BDMA_SetPeriphRequest(BDMAx, Channel, LL_DMAMUX2_REQ_MEM2MEM);
176
177 if (Channel == LL_BDMA_CHANNEL_0)
178 {
179 /* Reset interrupt pending bits for DMAx Channel0 */
180 LL_BDMA_ClearFlag_GI0(BDMAx);
181 }
182 else if (Channel == LL_BDMA_CHANNEL_1)
183 {
184 /* Reset interrupt pending bits for DMAx Channel1 */
185 LL_BDMA_ClearFlag_GI1(BDMAx);
186 }
187 else if (Channel == LL_BDMA_CHANNEL_2)
188 {
189 /* Reset interrupt pending bits for DMAx Channel2 */
190 LL_BDMA_ClearFlag_GI2(BDMAx);
191 }
192 else if (Channel == LL_BDMA_CHANNEL_3)
193 {
194 /* Reset interrupt pending bits for DMAx Channel3 */
195 LL_BDMA_ClearFlag_GI3(BDMAx);
196 }
197 else if (Channel == LL_BDMA_CHANNEL_4)
198 {
199 /* Reset interrupt pending bits for DMAx Channel4 */
200 LL_BDMA_ClearFlag_GI4(BDMAx);
201 }
202 else if (Channel == LL_BDMA_CHANNEL_5)
203 {
204 /* Reset interrupt pending bits for DMAx Channel5 */
205 LL_BDMA_ClearFlag_GI5(BDMAx);
206 }
207
208 else if (Channel == LL_BDMA_CHANNEL_6)
209 {
210 /* Reset interrupt pending bits for DMAx Channel6 */
211 LL_BDMA_ClearFlag_GI6(BDMAx);
212 }
213 else if (Channel == LL_BDMA_CHANNEL_7)
214 {
215 /* Reset interrupt pending bits for DMAx Channel7 */
216 LL_BDMA_ClearFlag_GI7(BDMAx);
217 }
218 else
219 {
220 status = ERROR;
221 }
222 }
223
224 return (uint32_t)status;
225 }
226
227 /**
228 * @brief Initialize the BDMA registers according to the specified parameters in BDMA_InitStruct.
229 * @note To convert BDMAx_Channely Instance to BDMAx Instance and Channely, use helper macros :
230 * @arg @ref __LL_BDMA_GET_INSTANCE
231 * @arg @ref __LL_BDMA_GET_CHANNEL
232 * @param BDMAx BDMAx Instance
233 * @param Channel This parameter can be one of the following values:
234 * @arg @ref LL_BDMA_CHANNEL_0
235 * @arg @ref LL_BDMA_CHANNEL_1
236 * @arg @ref LL_BDMA_CHANNEL_2
237 * @arg @ref LL_BDMA_CHANNEL_3
238 * @arg @ref LL_BDMA_CHANNEL_4
239 * @arg @ref LL_BDMA_CHANNEL_5
240 * @arg @ref LL_BDMA_CHANNEL_6
241 * @arg @ref LL_BDMA_CHANNEL_7
242 * @param BDMA_InitStruct pointer to a @ref LL_BDMA_InitTypeDef structure.
243 * @retval An ErrorStatus enumeration value:
244 * - SUCCESS: DMA registers are initialized
245 * - ERROR: Not applicable
246 */
LL_BDMA_Init(BDMA_TypeDef * BDMAx,uint32_t Channel,LL_BDMA_InitTypeDef * BDMA_InitStruct)247 uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct)
248 {
249 /* Check the DMA Instance DMAx and Channel parameters */
250 assert_param(IS_LL_BDMA_ALL_CHANNEL_INSTANCE(BDMAx, Channel));
251
252 /* Check the DMA parameters from BDMA_InitStruct */
253 assert_param(IS_LL_BDMA_DIRECTION(BDMA_InitStruct->Direction));
254 assert_param(IS_LL_BDMA_MODE(BDMA_InitStruct->Mode));
255 assert_param(IS_LL_BDMA_PERIPHINCMODE(BDMA_InitStruct->PeriphOrM2MSrcIncMode));
256 assert_param(IS_LL_BDMA_MEMORYINCMODE(BDMA_InitStruct->MemoryOrM2MDstIncMode));
257 assert_param(IS_LL_BDMA_PERIPHDATASIZE(BDMA_InitStruct->PeriphOrM2MSrcDataSize));
258 assert_param(IS_LL_BDMA_MEMORYDATASIZE(BDMA_InitStruct->MemoryOrM2MDstDataSize));
259 assert_param(IS_LL_BDMA_NBDATA(BDMA_InitStruct->NbData));
260 assert_param(IS_LL_BDMA_PERIPHREQUEST(BDMA_InitStruct->PeriphRequest));
261 assert_param(IS_LL_BDMA_PRIORITY(BDMA_InitStruct->Priority));
262 assert_param(IS_LL_BDMA_DOUBLEBUFFER_MODE(BDMA_InitStruct->DoubleBufferMode));
263 assert_param(IS_LL_BDMA_DOUBLEBUFFER_TARGETMEM(BDMA_InitStruct->TargetMemInDoubleBufferMode));
264
265 /*---------------------------- DMAx CCR Configuration ------------------------
266 * Configure DMAx_Channely: data transfer direction, data transfer mode,
267 * peripheral and memory increment mode,
268 * data size alignment and priority level with parameters :
269 * - Direction: BDMA_CCR_DIR and BDMA_CCR_MEM2MEM bits
270 * - Mode: BDMA_CCR_CIRC bit
271 * - PeriphOrM2MSrcIncMode: BDMA_CCR_PINC bit
272 * - MemoryOrM2MDstIncMode: BDMA_CCR_MINC bit
273 * - PeriphOrM2MSrcDataSize: BDMA_CCR_PSIZE[1:0] bits
274 * - MemoryOrM2MDstDataSize: BDMA_CCR_MSIZE[1:0] bits
275 * - Priority: BDMA_CCR_PL[1:0] bits
276 * - DoubleBufferMode: BDMA_CCR_DBM bit
277 * - TargetMemInDoubleBufferMode: BDMA_CCR_CT bit
278 */
279 LL_BDMA_ConfigTransfer(BDMAx, Channel,
280 BDMA_InitStruct->Direction | \
281 BDMA_InitStruct->Mode | \
282 BDMA_InitStruct->PeriphOrM2MSrcIncMode | \
283 BDMA_InitStruct->MemoryOrM2MDstIncMode | \
284 BDMA_InitStruct->PeriphOrM2MSrcDataSize | \
285 BDMA_InitStruct->MemoryOrM2MDstDataSize | \
286 BDMA_InitStruct->Priority | \
287 BDMA_InitStruct->DoubleBufferMode | \
288 BDMA_InitStruct->TargetMemInDoubleBufferMode);
289
290 /*-------------------------- DMAx CMAR Configuration -------------------------
291 * Configure the memory or destination base address with parameter :
292 * - MemoryOrM2MDstAddress: BDMA_CMAR_MA[31:0] bits
293 */
294 LL_BDMA_SetMemoryAddress(BDMAx, Channel, BDMA_InitStruct->MemoryOrM2MDstAddress);
295
296 /*-------------------------- DMAx CPAR Configuration -------------------------
297 * Configure the peripheral or source base address with parameter :
298 * - PeriphOrM2MSrcAddress: BDMA_CPAR_PA[31:0] bits
299 */
300 LL_BDMA_SetPeriphAddress(BDMAx, Channel, BDMA_InitStruct->PeriphOrM2MSrcAddress);
301
302 /*--------------------------- DMAx CNDTR Configuration -----------------------
303 * Configure the peripheral base address with parameter :
304 * - NbData: BDMA_CNDTR_NDT[15:0] bits
305 */
306 LL_BDMA_SetDataLength(BDMAx, Channel, BDMA_InitStruct->NbData);
307
308 /*--------------------------- DMAMUXx CCR Configuration ----------------------
309 * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
310 * - PeriphRequest: BDMA_CxCR[7:0] bits
311 */
312 LL_BDMA_SetPeriphRequest(BDMAx, Channel, BDMA_InitStruct->PeriphRequest);
313
314 return (uint32_t)SUCCESS;
315 }
316
317 /**
318 * @brief Set each @ref LL_BDMA_InitTypeDef field to default value.
319 * @param BDMA_InitStruct Pointer to a @ref LL_BDMA_InitTypeDef structure.
320 * @retval None
321 */
LL_BDMA_StructInit(LL_BDMA_InitTypeDef * BDMA_InitStruct)322 void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct)
323 {
324 /* Set BDMA_InitStruct fields to default values */
325 BDMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
326 BDMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
327 BDMA_InitStruct->Direction = LL_BDMA_DIRECTION_PERIPH_TO_MEMORY;
328 BDMA_InitStruct->Mode = LL_BDMA_MODE_NORMAL;
329 BDMA_InitStruct->PeriphOrM2MSrcIncMode = LL_BDMA_PERIPH_NOINCREMENT;
330 BDMA_InitStruct->MemoryOrM2MDstIncMode = LL_BDMA_MEMORY_NOINCREMENT;
331 BDMA_InitStruct->PeriphOrM2MSrcDataSize = LL_BDMA_PDATAALIGN_BYTE;
332 BDMA_InitStruct->MemoryOrM2MDstDataSize = LL_BDMA_MDATAALIGN_BYTE;
333 BDMA_InitStruct->NbData = 0x00000000U;
334 BDMA_InitStruct->PeriphRequest = LL_DMAMUX2_REQ_MEM2MEM;
335 BDMA_InitStruct->Priority = LL_BDMA_PRIORITY_LOW;
336 BDMA_InitStruct->DoubleBufferMode = LL_BDMA_DOUBLEBUFFER_MODE_DISABLE;
337 BDMA_InitStruct->TargetMemInDoubleBufferMode = LL_BDMA_CURRENTTARGETMEM0;
338 }
339
340 /**
341 * @}
342 */
343
344 /**
345 * @}
346 */
347
348 /**
349 * @}
350 */
351
352 #endif /* BDMA || BDMA1 || BDMA2 */
353
354 /**
355 * @}
356 */
357
358 #endif /* USE_FULL_LL_DRIVER */
359
360
