1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @brief Extended PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of PWR extension peripheral:
8 * + Peripheral Extended features functions
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2017 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply
26 with the following different setups according to hardware (support SMPS):
27 (+) PWR_DIRECT_SMPS_SUPPLY
28 (+) PWR_SMPS_1V8_SUPPLIES_LDO
29 (+) PWR_SMPS_2V5_SUPPLIES_LDO
30 (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
31 (+) PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
32 (+) PWR_SMPS_1V8_SUPPLIES_EXT
33 (+) PWR_SMPS_2V5_SUPPLIES_EXT
34 (+) PWR_LDO_SUPPLY
35 (+) PWR_EXTERNAL_SOURCE_SUPPLY
36
37 (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup.
38
39 (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main
40 internal regulator output voltage. The voltage scaling could be one of
41 the following scales :
42 (+) PWR_REGULATOR_VOLTAGE_SCALE0
43 (+) PWR_REGULATOR_VOLTAGE_SCALE1
44 (+) PWR_REGULATOR_VOLTAGE_SCALE2
45 (+) PWR_REGULATOR_VOLTAGE_SCALE3
46
47 (#) Call HAL_PWREx_GetVoltageRange() function to get the current output
48 voltage applied to the main regulator.
49
50 (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the
51 main internal regulator output voltage in STOP mode. The voltage scaling
52 in STOP mode could be one of the following scales :
53 (+) PWR_REGULATOR_SVOS_SCALE3
54 (+) PWR_REGULATOR_SVOS_SCALE4
55 (+) PWR_REGULATOR_SVOS_SCALE5
56
57 (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current
58 output voltage applied to the main regulator in STOP mode.
59
60 (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the system in STOP mode
61 with core domain in D2STOP mode. This API is used only for STM32H7Axxx
62 and STM32H7Bxxx devices.
63 Please ensure to clear all CPU pending events by calling
64 HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
65 in DEEP-SLEEP mode with __WFE() entry.
66
67 (#) Call HAL_PWREx_EnterSTOPMode() function to enter the selected domain in
68 DSTOP mode. Call this API with all available power domains to enter the
69 system in STOP mode.
70 Please ensure to clear all CPU pending events by calling
71 HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
72 in DEEP-SLEEP mode with __WFE() entry.
73
74 (#) Call HAL_PWREx_ClearPendingEvent() function always before entring the
75 Cortex-Mx in any low power mode (SLEEP/DEEP-SLEEP) using WFE entry.
76
77 (#) Call HAL_PWREx_EnterSTANDBYMode() function to enter the selected domain
78 in DSTANDBY mode. Call this API with all available power domains to enter
79 the system in STANDBY mode.
80
81 (#) Call HAL_PWREx_ConfigD3Domain() function to setup the D3/SRD domain state
82 (RUN/STOP) when the system enter to low power mode.
83
84 (#) Call HAL_PWREx_ClearDomainFlags() function to clear the CPU flags for the
85 selected power domain. This API is used only for dual core devices.
86
87 (#) Call HAL_PWREx_HoldCore() and HAL_PWREx_ReleaseCore() functions to hold
88 and release the selected CPU and and their domain peripherals when
89 exiting STOP mode. These APIs are used only for dual core devices.
90
91 (#) Call HAL_PWREx_EnableFlashPowerDown() and
92 HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the
93 Flash Power Down in STOP mode.
94
95 (#) Call HAL_PWREx_EnableMemoryShutOff() and
96 HAL_PWREx_DisableMemoryShutOff() functions to enable and disable the
97 memory block shut-off in DStop or DStop2. These APIs are used only for
98 STM32H7Axxx and STM32H7Bxxx lines.
99
100 (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin()
101 functions to enable and disable the Wake-up pin functionality for
102 the selected pin.
103
104 (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag()
105 functions to manage wake-up flag for the selected pin.
106
107 (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up
108 pins interrupts.
109
110 (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions
111 to enable and disable the backup domain regulator.
112
113 (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(),
114 HAL_PWREx_EnableUSBVoltageDetector() and
115 HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power
116 regulation functionalities.
117
118 (#) Call HAL_PWREx_EnableBatteryCharging() and
119 HAL_PWREx_DisableBatteryCharging() functions to enable and disable the
120 battery charging feature with the selected resistor.
121
122 (#) Call HAL_PWREx_EnableAnalogBooster() and
123 HAL_PWREx_DisableAnalogBooster() functions to enable and disable the
124 AVD boost feature when the VDD supply voltage is below 2V7.
125
126 (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring()
127 functions to enable and disable the VBAT and Temperature monitoring.
128 When VBAT and Temperature monitoring feature is enables, use
129 HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get
130 respectively the Temperature level and VBAT level.
131
132 (#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring()
133 function to get VDDMMC voltage level. This API is used only for
134 STM32H7Axxx and STM32H7Bxxx lines
135
136 (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured
137 (event mode and voltage threshold) in order to set up the Analog Voltage
138 Detector then use HAL_PWREx_EnableAVD() and HAL_PWREx_DisableAVD()
139 functions to start and stop the AVD detection.
140 (+) AVD level could be one of the following values :
141 (++) 1V7
142 (++) 2V1
143 (++) 2V5
144 (++) 2V8
145
146 (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and
147 AVD interrupt request.
148
149 @endverbatim
150 */
151
152 /* Includes ------------------------------------------------------------------*/
153 #include "stm32h7xx_hal.h"
154
155 /** @addtogroup STM32H7xx_HAL_Driver
156 * @{
157 */
158
159 /** @defgroup PWREx PWREx
160 * @brief PWR Extended HAL module driver
161 * @{
162 */
163
164 #ifdef HAL_PWR_MODULE_ENABLED
165
166 /* Private typedef -----------------------------------------------------------*/
167 /* Private define ------------------------------------------------------------*/
168
169 /** @addtogroup PWREx_Private_Constants
170 * @{
171 */
172
173 /** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask
174 * @{
175 */
176 #define AVD_MODE_IT (0x00010000U)
177 #define AVD_MODE_EVT (0x00020000U)
178 #define AVD_RISING_EDGE (0x00000001U)
179 #define AVD_FALLING_EDGE (0x00000002U)
180 #define AVD_RISING_FALLING_EDGE (0x00000003U)
181 /**
182 * @}
183 */
184
185 /** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value
186 * @{
187 */
188 #define PWR_FLAG_SETTING_DELAY (1000U)
189 /**
190 * @}
191 */
192
193 /** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets
194 * @{
195 */
196 /* Wake-Up Pins EXTI register mask */
197 #if defined (EXTI_IMR2_IM57)
198 #define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\
199 EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\
200 EXTI_IMR2_IM59 | EXTI_IMR2_IM60)
201 #else
202 #define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\
203 EXTI_IMR2_IM58 | EXTI_IMR2_IM60)
204 #endif /* defined (EXTI_IMR2_IM57) */
205
206 /* Wake-Up Pins PWR Pin Pull shift offsets */
207 #define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)
208 /**
209 * @}
210 */
211
212 /**
213 * @}
214 */
215
216 /* Private macro -------------------------------------------------------------*/
217 /* Private variables ---------------------------------------------------------*/
218 /* Private function prototypes -----------------------------------------------*/
219 /* Private functions ---------------------------------------------------------*/
220 /* Exported types ------------------------------------------------------------*/
221 /* Exported functions --------------------------------------------------------*/
222
223 /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
224 * @{
225 */
226
227 /** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
228 * @brief Power supply control functions
229 *
230 @verbatim
231 ===============================================================================
232 ##### Power supply control functions #####
233 ===============================================================================
234 [..]
235 (#) When the system is powered on, the POR monitors VDD supply. Once VDD is
236 above the POR threshold level, the voltage regulator is enabled in the
237 default supply configuration:
238 (+) The Voltage converter output level is set at 1V0 in accordance with
239 the VOS3 level configured in PWR (D3/SRD) domain control register
240 (PWR_D3CR/PWR_SRDCR).
241 (+) The system is kept in reset mode as long as VCORE is not ok.
242 (+) Once VCORE is ok, the system is taken out of reset and the HSI
243 oscillator is enabled.
244 (+) Once the oscillator is stable, the system is initialized: Flash memory
245 and option bytes are loaded and the CPU starts in Run* mode.
246 (+) The software shall then initialize the system including supply
247 configuration programming using the HAL_PWREx_ConfigSupply().
248 (+) Once the supply configuration has been configured, the
249 HAL_PWREx_ConfigSupply() function checks the ACTVOSRDY bit in PWR
250 control status register 1 (PWR_CSR1) to guarantee a valid voltage
251 levels:
252 (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the
253 system is in limited Run* mode, write accesses to the RAMs are not
254 permitted and VOS shall not be changed.
255 (++) Once ACTVOSRDY indicates that voltage levels are valid, the system
256 is in normal Run mode, write accesses to RAMs are allowed and VOS
257 can be changed.
258
259 @endverbatim
260 * @{
261 */
262
263 /**
264 * @brief Configure the system Power Supply.
265 * @param SupplySource : Specifies the Power Supply source to set after a
266 * system startup.
267 * This parameter can be one of the following values :
268 * @arg PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power
269 * Domains. The LDO is Bypassed.
270 * @arg PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies
271 * the LDO. The Vcore Power Domains
272 * are supplied from the LDO.
273 * @arg PWR_SMPS_2V5_SUPPLIES_LDO : The SMPS 2.5V output supplies
274 * the LDO. The Vcore Power Domains
275 * are supplied from the LDO.
276 * @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output
277 * supplies external
278 * circuits and the LDO.
279 * The Vcore Power Domains
280 * are supplied from the
281 * LDO.
282 * @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : The SMPS 2.5V output
283 * supplies external
284 * circuits and the LDO.
285 * The Vcore Power Domains
286 * are supplied from the
287 * LDO.
288 * @arg PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies
289 * external circuits. The LDO is
290 * Bypassed. The Vcore Power
291 * Domains are supplied from
292 * external source.
293 * @arg PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies
294 * external circuits. The LDO is
295 * Bypassed. The Vcore Power
296 * Domains are supplied from
297 * external source.
298 * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power
299 * Domains. The SMPS regulator is Bypassed.
300 * @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are
301 * Bypassed. The Vcore Power
302 * Domains are supplied from
303 * external source.
304 * @note The PWR_LDO_SUPPLY and PWR_EXTERNAL_SOURCE_SUPPLY are used by all
305 * H7 lines.
306 * The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO,
307 * PWR_SMPS_2V5_SUPPLIES_LDO, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO,
308 * PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and
309 * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
310 * regulator.
311 * @note This API is deprecated and is kept only for backward compatibility's sake.
312 * The power supply configuration is handled as part of the system initialization
313 * process during startup.
314 * For more details, please refer to the power control chapter in the reference manual
315 * @retval HAL status.
316 */
HAL_PWREx_ConfigSupply(uint32_t SupplySource)317 HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
318 {
319 uint32_t tickstart;
320
321 /* Check the parameters */
322 assert_param (IS_PWR_SUPPLY (SupplySource));
323
324 /* Check if supply source was configured */
325 #if defined (PWR_FLAG_SCUEN)
326 if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
327 #else
328 if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
329 #endif /* defined (PWR_FLAG_SCUEN) */
330 {
331 /* Check supply configuration */
332 if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
333 {
334 /* Supply configuration update locked, can't apply a new supply config */
335 return HAL_ERROR;
336 }
337 else
338 {
339 /* Supply configuration update locked, but new supply configuration
340 matches with old supply configuration : nothing to do
341 */
342 return HAL_OK;
343 }
344 }
345
346 /* Set the power supply configuration */
347 MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
348
349 /* Get tick */
350 tickstart = HAL_GetTick ();
351
352 /* Wait till voltage level flag is set */
353 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
354 {
355 if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
356 {
357 return HAL_ERROR;
358 }
359 }
360
361 #if defined (SMPS)
362 /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */
363 if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||
364 (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||
365 (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT) ||
366 (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT))
367 {
368 /* Get the current tick number */
369 tickstart = HAL_GetTick ();
370
371 /* Wait till SMPS external supply ready flag is set */
372 while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U)
373 {
374 if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
375 {
376 return HAL_ERROR;
377 }
378 }
379 }
380 #endif /* defined (SMPS) */
381
382 return HAL_OK;
383 }
384
385 /**
386 * @brief Get the power supply configuration.
387 * @retval The supply configuration.
388 */
HAL_PWREx_GetSupplyConfig(void)389 uint32_t HAL_PWREx_GetSupplyConfig (void)
390 {
391 return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK);
392 }
393
394 /**
395 * @brief Configure the main internal regulator output voltage.
396 * @param VoltageScaling : Specifies the regulator output voltage to achieve
397 * a tradeoff between performance and power
398 * consumption.
399 * This parameter can be one of the following values :
400 * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
401 * Scale 0 mode.
402 * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
403 * range 1 mode.
404 * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
405 * range 2 mode.
406 * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
407 * range 3 mode.
408 * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is
409 * only possible when Vcore is supplied from LDO (Low DropOut). The
410 * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE()
411 * macro before configuring Voltage Scale 0.
412 * To enter low power mode , and if current regulator voltage is
413 * Voltage Scale 0 then first switch to Voltage Scale 1 before entering
414 * low power mode.
415 * @retval HAL Status
416 */
HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)417 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
418 {
419 uint32_t tickstart;
420
421 /* Check the parameters */
422 assert_param (IS_PWR_REGULATOR_VOLTAGE (VoltageScaling));
423
424 /* Get the voltage scaling */
425 if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == VoltageScaling)
426 {
427 /* Old and new voltage scaling configuration match : nothing to do */
428 return HAL_OK;
429 }
430
431 #if defined (PWR_SRDCR_VOS)
432 /* Set the voltage range */
433 MODIFY_REG (PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
434 #else
435 #if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
436 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE0)
437 {
438 if ((PWR->CR3 & PWR_CR3_LDOEN) == PWR_CR3_LDOEN)
439 {
440 /* Set the voltage range */
441 MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
442
443 /* Get tick */
444 tickstart = HAL_GetTick ();
445
446 /* Wait till voltage level flag is set */
447 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
448 {
449 if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
450 {
451 return HAL_ERROR;
452 }
453 }
454
455 /* Enable the PWR overdrive */
456 SET_BIT (SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
457 }
458 else
459 {
460 /* The voltage scale 0 is only possible when LDO regulator is enabled */
461 return HAL_ERROR;
462 }
463 }
464 else
465 {
466 if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == PWR_REGULATOR_VOLTAGE_SCALE1)
467 {
468 if ((SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN) != 0U)
469 {
470 /* Disable the PWR overdrive */
471 CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
472
473 /* Get tick */
474 tickstart = HAL_GetTick ();
475
476 /* Wait till voltage level flag is set */
477 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
478 {
479 if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
480 {
481 return HAL_ERROR;
482 }
483 }
484 }
485 }
486
487 /* Set the voltage range */
488 MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
489 }
490 #else /* STM32H72xxx and STM32H73xxx lines */
491 /* Set the voltage range */
492 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
493 #endif /* defined (SYSCFG_PWRCR_ODEN) */
494 #endif /* defined (PWR_SRDCR_VOS) */
495
496 /* Get tick */
497 tickstart = HAL_GetTick ();
498
499 /* Wait till voltage level flag is set */
500 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
501 {
502 if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY)
503 {
504 return HAL_ERROR;
505 }
506 }
507
508 return HAL_OK;
509 }
510
511 /**
512 * @brief Get the main internal regulator output voltage. Reflecting the last
513 * VOS value applied to the PMU.
514 * @retval The current applied VOS selection.
515 */
HAL_PWREx_GetVoltageRange(void)516 uint32_t HAL_PWREx_GetVoltageRange (void)
517 {
518 /* Get the active voltage scaling */
519 return (PWR->CSR1 & PWR_CSR1_ACTVOS);
520 }
521
522 /**
523 * @brief Configure the main internal regulator output voltage in STOP mode.
524 * @param VoltageScaling : Specifies the regulator output voltage when the
525 * system enters Stop mode to achieve a tradeoff between performance
526 * and power consumption.
527 * This parameter can be one of the following values:
528 * @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range
529 * 3 mode.
530 * @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range
531 * 4 mode.
532 * @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range
533 * 5 mode.
534 * @note The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage
535 * regulator in Low-power (LP) mode to further reduce power consumption.
536 * When preselecting SVOS3, the use of the voltage regulator low-power
537 * mode (LP) can be selected by LPDS register bit.
538 * @note The selected SVOS4 and SVOS5 levels add an additional startup delay
539 * when exiting from system Stop mode.
540 * @retval HAL Status.
541 */
HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling)542 HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling)
543 {
544 /* Check the parameters */
545 assert_param (IS_PWR_STOP_MODE_REGULATOR_VOLTAGE (VoltageScaling));
546
547 /* Return the stop mode voltage range */
548 MODIFY_REG (PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
549
550 return HAL_OK;
551 }
552
553 /**
554 * @brief Get the main internal regulator output voltage in STOP mode.
555 * @retval The actual applied VOS selection.
556 */
HAL_PWREx_GetStopModeVoltageRange(void)557 uint32_t HAL_PWREx_GetStopModeVoltageRange (void)
558 {
559 /* Return the stop voltage scaling */
560 return (PWR->CR1 & PWR_CR1_SVOS);
561 }
562 /**
563 * @}
564 */
565
566 /** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
567 * @brief Low power control functions
568 *
569 @verbatim
570 ===============================================================================
571 ##### Low power control functions #####
572 ===============================================================================
573
574 *** Domains Low Power modes configuration ***
575 =============================================
576 [..]
577 This section provides the extended low power mode control APIs.
578 The system presents 3 principles domains (D1, D2 and D3) that can be
579 operated in low-power modes (DSTOP or DSTANDBY mode):
580
581 (+) DSTOP mode to enters a domain to STOP mode:
582 (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU
583 subsystem is in CSTOP mode and has allocated peripheral in the
584 domain.
585 In DSTOP mode the domain bus matrix clock is stopped.
586 (++) The system enters STOP mode using one of the following scenarios:
587 (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains
588 enter DSTOP mode.
589 (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains
590 enter DSTOP mode.
591 (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains
592 enter DSTOP mode.
593 (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain
594 enters DSTOP mode.
595 (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain
596 enters DSTOP mode.
597 (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain
598 enters DSTOP mode.
599 (+++) D1, D2 and D3 domains enter DSTOP mode.
600 (++) When the system enters STOP mode, the clocks are stopped and the
601 regulator is running in main or low power mode.
602 (++) D3 domain can be kept in Run mode regardless of the CPU status when
603 enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function.
604
605 (+) DSTANDBY mode to enters a domain to STANDBY mode:
606 (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control
607 register (PWR_CPUCR) for the Dn domain selects Standby mode.
608 (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter
609 DSTANDBY mode. Consequently the VCORE supply regulator is powered
610 off.
611
612 *** DSTOP mode ***
613 ==================
614 [..]
615 In DStop mode the domain bus matrix clock is stopped.
616 The Flash memory can enter low-power Stop mode when it is enabled through
617 FLPS in PWR_CR1 register. This allows a trade-off between domain DStop
618 restart time and low power consumption.
619 [..]
620 In DStop mode domain peripherals using the LSI or LSE clock and
621 peripherals having a kernel clock request are still able to operate.
622 [..]
623 Before entering DSTOP mode it is recommended to call SCB_CleanDCache
624 function in order to clean the D-Cache and guarantee the data integrity
625 for the SRAM memories.
626
627 (+) Entry:
628 The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator,
629 STOPEntry, Domain) function with:
630 (++) Regulator:
631 (+++) PWR_MAINREGULATOR_ON : Main regulator ON.
632 (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON.
633 (++) STOPEntry:
634 (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction
635 (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction
636 (++) Domain:
637 (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTOP mode.
638 (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode.
639 (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTOP mode.
640
641 (+) Exit:
642 Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
643
644 *** DSTANDBY mode ***
645 =====================
646 [..]
647 In DStandby mode:
648 (+) The domain bus matrix clock is stopped.
649 (+) The domain is powered down and the domain RAM and register contents
650 are lost.
651 [..]
652 Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache
653 function in order to clean the D-Cache and guarantee the data integrity
654 for the SRAM memories.
655
656 (+) Entry:
657 The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode
658 (Domain) function with:
659 (++) Domain:
660 (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTANDBY mode.
661 (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode.
662 (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTANDBY mode.
663
664 (+) Exit:
665 WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
666 wakeup, tamper event, time stamp event, external reset in NRST pin,
667 IWDG reset.
668
669 *** Keep D3/SRD in RUN mode ***
670 ===============================
671 [..]
672 D3/SRD domain can be kept in Run mode regardless of the CPU status when
673 entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function
674 with :
675 (+) D3State:
676 (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system
677 mode.
678 (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless
679 of CPU subsystem mode.
680
681 *** FLASH Power Down configuration ****
682 =======================================
683 [..]
684 By setting the FLPS bit in the PWR_CR1 register using the
685 HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters
686 power down mode when the device enters STOP mode. When the Flash memory is
687 in power down mode, an additional startup delay is incurred when waking up
688 from STOP mode.
689
690 *** Wakeup Pins configuration ****
691 ===================================
692 [..]
693 Wakeup pins allow the system to exit from Standby mode. The configuration
694 of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams)
695 function with:
696 (+) sPinParams: structure to enable and configure a wakeup pin:
697 (++) WakeUpPin: Wakeup pin to be enabled.
698 (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
699 (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
700 [..]
701 The wakeup pins are internally connected to the EXTI lines [55-60] to
702 generate an interrupt if enabled. The EXTI lines configuration is done by
703 the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c
704 file.
705 [..]
706 When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is
707 called and the appropriate flag is set in the PWR_WKUPFR register. Then in
708 the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be
709 cleared and the appropriate user callback will be called. The user can add
710 his own code by customization of function pointer HAL_PWREx_WKUPx_Callback.
711
712 @endverbatim
713 * @{
714 */
715
716 #if defined (PWR_CPUCR_RETDS_CD)
717 /**
718 * @brief Enter the system to STOP mode with main domain in DSTOP2.
719 * @note In STOP mode, the domain bus matrix clock is stalled.
720 * @note In STOP mode, memories and registers are maintained and peripherals
721 * in CPU domain are no longer operational.
722 * @note All clocks in the VCORE domain are stopped, the PLL, the HSI and the
723 * HSE oscillators are disabled. Only Peripherals that have wakeup
724 * capability can switch on the HSI to receive a frame, and switch off
725 * the HSI after receiving the frame if it is not a wakeup frame. In
726 * this case the HSI clock is propagated only to the peripheral
727 * requesting it.
728 * @note When exiting STOP mode by issuing an interrupt or a wakeup event,
729 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in
730 * RCC_CFGR register is set.
731 * @param Regulator : Specifies the regulator state in STOP mode.
732 * This parameter can be one of the following values:
733 * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON.
734 * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
735 * regulator ON.
736 * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE
737 * intrinsic instruction.
738 * This parameter can be one of the following values:
739 * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
740 * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
741 * @retval None.
742 */
HAL_PWREx_EnterSTOP2Mode(uint32_t Regulator,uint8_t STOPEntry)743 void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry)
744 {
745 /* Check the parameters */
746 assert_param (IS_PWR_REGULATOR (Regulator));
747 assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
748
749 /* Select the regulator state in Stop mode */
750 MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
751
752 /* Go to DStop2 mode (deep retention) when CPU domain enters Deepsleep */
753 SET_BIT (PWR->CPUCR, PWR_CPUCR_RETDS_CD);
754
755 /* Keep DSTOP mode when SmartRun domain enters Deepsleep */
756 CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_SRD);
757
758 /* Set SLEEPDEEP bit of Cortex System Control Register */
759 SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
760
761 /* Ensure that all instructions are done before entering STOP mode */
762 __ISB ();
763 __DSB ();
764
765 /* Select Stop mode entry */
766 if (STOPEntry == PWR_STOPENTRY_WFI)
767 {
768 /* Request Wait For Interrupt */
769 __WFI ();
770 }
771 else
772 {
773 /* Request Wait For Event */
774 __WFE ();
775 }
776
777 /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
778 CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
779 }
780 #endif /* defined (PWR_CPUCR_RETDS_CD) */
781
782 /**
783 * @brief Enter a Domain to DSTOP mode.
784 * @note This API gives flexibility to manage independently each domain STOP
785 * mode. For dual core lines, this API should be executed with the
786 * corresponding Cortex-Mx to enter domain to DSTOP mode. When it is
787 * executed by all available Cortex-Mx, the system enter to STOP mode.
788 * For single core lines, calling this API with domain parameter set to
789 * PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode
790 * independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the
791 * CPUCR_RUN_D3 is cleared.
792 * @note In DStop mode the domain bus matrix clock is stopped.
793 * @note The system D3/SRD domain enter Stop mode only when the CPU subsystem
794 * is in CStop mode, the EXTI wakeup sources are inactive and at least
795 * one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for
796 * any domain request Stop.
797 * @note Before entering DSTOP mode it is recommended to call SCB_CleanDCache
798 * function in order to clean the D-Cache and guarantee the data
799 * integrity for the SRAM memories.
800 * @note In System Stop mode, the domain peripherals that use the LSI or LSE
801 * clock, and the peripherals that have a kernel clock request to
802 * select HSI or CSI as source, are still able to operate.
803 * @param Regulator : Specifies the regulator state in STOP mode.
804 * This parameter can be one of the following values:
805 * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON.
806 * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
807 * regulator ON.
808 * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE
809 * intrinsic instruction.
810 * This parameter can be one of the following values:
811 * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
812 * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
813 * @param Domain : Specifies the Domain to enter in DSTOP mode.
814 * This parameter can be one of the following values:
815 * @arg PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode.
816 * @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode.
817 * @arg PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode.
818 * @retval None.
819 */
HAL_PWREx_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry,uint32_t Domain)820 void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
821 {
822 /* Check the parameters */
823 assert_param (IS_PWR_REGULATOR (Regulator));
824 assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
825 assert_param (IS_PWR_DOMAIN (Domain));
826
827 /* Select the regulator state in Stop mode */
828 MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
829
830 /* Select the domain Power Down DeepSleep */
831 if (Domain == PWR_D1_DOMAIN)
832 {
833 #if defined (DUAL_CORE)
834 /* Check current core */
835 if (HAL_GetCurrentCPUID () != CM7_CPUID)
836 {
837 /*
838 When the domain selected and the cortex-mx don't match, entering stop
839 mode will not be performed
840 */
841 return;
842 }
843 #endif /* defined (DUAL_CORE) */
844
845 /* Keep DSTOP mode when D1/CD domain enters Deepsleep */
846 CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D1);
847
848 /* Set SLEEPDEEP bit of Cortex System Control Register */
849 SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
850
851 /* Ensure that all instructions are done before entering STOP mode */
852 __DSB ();
853 __ISB ();
854
855 /* Select Stop mode entry */
856 if (STOPEntry == PWR_STOPENTRY_WFI)
857 {
858 /* Request Wait For Interrupt */
859 __WFI ();
860 }
861 else
862 {
863 /* Request Wait For Event */
864 __WFE ();
865 }
866
867 /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
868 CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
869 }
870 #if defined (PWR_CPUCR_PDDS_D2)
871 else if (Domain == PWR_D2_DOMAIN)
872 {
873 #if defined (DUAL_CORE)
874 /* Check current core */
875 if (HAL_GetCurrentCPUID () != CM4_CPUID)
876 {
877 /*
878 When the domain selected and the cortex-mx don't match, entering stop
879 mode will not be performed
880 */
881 return;
882 }
883
884 /* Keep DSTOP mode when D2 domain enters Deepsleep */
885 CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D2);
886
887 /* Set SLEEPDEEP bit of Cortex System Control Register */
888 SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
889
890 /* Ensure that all instructions are done before entering STOP mode */
891 __DSB ();
892 __ISB ();
893
894 /* Select Stop mode entry */
895 if (STOPEntry == PWR_STOPENTRY_WFI)
896 {
897 /* Request Wait For Interrupt */
898 __WFI ();
899 }
900 else
901 {
902 /* Request Wait For Event */
903 __WFE ();
904 }
905
906 /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
907 CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
908 #else
909 /* Keep DSTOP mode when D2 domain enters Deepsleep */
910 CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
911 #endif /* defined (DUAL_CORE) */
912 }
913 #endif /* defined (PWR_CPUCR_PDDS_D2) */
914 else
915 {
916 #if defined (DUAL_CORE)
917 /* Check current core */
918 if (HAL_GetCurrentCPUID () == CM7_CPUID)
919 {
920 /* Keep DSTOP mode when D3 domain enters Deepsleep */
921 CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
922 }
923 else
924 {
925 /* Keep DSTOP mode when D3 domain enters Deepsleep */
926 CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3);
927 }
928 #else
929 /* Keep DSTOP mode when D3/SRD domain enters Deepsleep */
930 CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
931 #endif /* defined (DUAL_CORE) */
932 }
933 }
934
935 /**
936 * @brief Clear pending event.
937 * @note This API clears the pending event in order to enter a given CPU
938 * to CSLEEP or CSTOP. It should be called just before APIs performing
939 * enter low power mode using Wait For Event request.
940 * @note Cortex-M7 must be in CRUN mode when calling this API by Cortex-M4.
941 * @retval None.
942 */
HAL_PWREx_ClearPendingEvent(void)943 void HAL_PWREx_ClearPendingEvent (void)
944 {
945 #if defined (DUAL_CORE)
946 /* Check the current Core */
947 if (HAL_GetCurrentCPUID () == CM7_CPUID)
948 {
949 __WFE ();
950 }
951 else
952 {
953 __SEV ();
954 __WFE ();
955 }
956 #else
957 __WFE ();
958 #endif /* defined (DUAL_CORE) */
959 }
960
961 /**
962 * @brief Enter a Domain to DSTANDBY mode.
963 * @note This API gives flexibility to manage independently each domain
964 * STANDBY mode. For dual core lines, this API should be executed with
965 * the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When
966 * it is executed by all available Cortex-Mx, the system enter STANDBY
967 * mode.
968 * For single core lines, calling this API with D1/SRD the selected
969 * domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0
970 * and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1.
971 * @note The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for
972 * the Dn domain select Standby mode. When the system enters Standby
973 * mode, the voltage regulator is disabled.
974 * @note When D2 or D3 domain is in DStandby mode and the CPU sets the
975 * domain PDDS_Dn bit to select Stop mode, the domain remains in
976 * DStandby mode. The domain will only exit DStandby when the CPU
977 * allocates a peripheral in the domain.
978 * @note The system D3/SRD domain enters Standby mode only when the D1 and D2
979 * domain are in DStandby.
980 * @note Before entering DSTANDBY mode it is recommended to call
981 * SCB_CleanDCache function in order to clean the D-Cache and guarantee
982 * the data integrity for the SRAM memories.
983 * @param Domain : Specifies the Domain to enter to STANDBY mode.
984 * This parameter can be one of the following values:
985 * @arg PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode.
986 * @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
987 * @arg PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode.
988 * @retval None
989 */
HAL_PWREx_EnterSTANDBYMode(uint32_t Domain)990 void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
991 {
992 /* Check the parameters */
993 assert_param (IS_PWR_DOMAIN (Domain));
994
995 /* Select the domain Power Down DeepSleep */
996 if (Domain == PWR_D1_DOMAIN)
997 {
998 #if defined (DUAL_CORE)
999 /* Check current core */
1000 if (HAL_GetCurrentCPUID () != CM7_CPUID)
1001 {
1002 /*
1003 When the domain selected and the cortex-mx don't match, entering
1004 standby mode will not be performed
1005 */
1006 return;
1007 }
1008 #endif /* defined (DUAL_CORE) */
1009
1010 /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
1011 SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D1);
1012
1013 #if defined (DUAL_CORE)
1014 /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
1015 SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1);
1016 #endif /*DUAL_CORE*/
1017
1018 /* Set SLEEPDEEP bit of Cortex System Control Register */
1019 SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
1020
1021 /* This option is used to ensure that store operations are completed */
1022 #if defined (__CC_ARM)
1023 __force_stores ();
1024 #endif /* defined (__CC_ARM) */
1025
1026 /* Request Wait For Interrupt */
1027 __WFI ();
1028 }
1029 #if defined (PWR_CPUCR_PDDS_D2)
1030 else if (Domain == PWR_D2_DOMAIN)
1031 {
1032 /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
1033 SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D2);
1034
1035 #if defined (DUAL_CORE)
1036 /* Check current core */
1037 if (HAL_GetCurrentCPUID () != CM4_CPUID)
1038 {
1039 /*
1040 When the domain selected and the cortex-mx don't match, entering
1041 standby mode will not be performed
1042 */
1043 return;
1044 }
1045
1046 /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
1047 SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2);
1048
1049 /* Set SLEEPDEEP bit of Cortex System Control Register */
1050 SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
1051
1052 /* This option is used to ensure that store operations are completed */
1053 #if defined (__CC_ARM)
1054 __force_stores ();
1055 #endif /* defined (__CC_ARM) */
1056
1057 /* Request Wait For Interrupt */
1058 __WFI ();
1059 #endif /* defined (DUAL_CORE) */
1060 }
1061 #endif /* defined (PWR_CPUCR_PDDS_D2) */
1062 else
1063 {
1064 /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
1065 SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
1066
1067 #if defined (DUAL_CORE)
1068 /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
1069 SET_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3);
1070 #endif /* defined (DUAL_CORE) */
1071 }
1072 }
1073
1074 /**
1075 * @brief Configure the D3/SRD Domain state when the System in low power mode.
1076 * @param D3State : Specifies the D3/SRD state.
1077 * This parameter can be one of the following values :
1078 * @arg PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep
1079 * CPU sub-system low power mode.
1080 * @arg PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode
1081 * regardless of the CPU sub-system low
1082 * power mode.
1083 * @retval None
1084 */
HAL_PWREx_ConfigD3Domain(uint32_t D3State)1085 void HAL_PWREx_ConfigD3Domain (uint32_t D3State)
1086 {
1087 /* Check the parameter */
1088 assert_param (IS_D3_STATE (D3State));
1089
1090 /* Keep D3/SRD in run mode */
1091 MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State);
1092 }
1093
1094 #if defined (DUAL_CORE)
1095 /**
1096 * @brief Clear HOLD2F, HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a
1097 * given domain.
1098 * @param DomainFlags : Specifies the Domain flags to be cleared.
1099 * This parameter can be one of the following values:
1100 * @arg PWR_D1_DOMAIN_FLAGS : Clear D1 Domain flags.
1101 * @arg PWR_D2_DOMAIN_FLAGS : Clear D2 Domain flags.
1102 * @arg PWR_ALL_DOMAIN_FLAGS : Clear D1 and D2 Domain flags.
1103 * @retval None.
1104 */
HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags)1105 void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags)
1106 {
1107 /* Check the parameter */
1108 assert_param (IS_PWR_DOMAIN_FLAG (DomainFlags));
1109
1110 /* D1 CPU flags */
1111 if (DomainFlags == PWR_D1_DOMAIN_FLAGS)
1112 {
1113 /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
1114 SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
1115 }
1116 /* D2 CPU flags */
1117 else if (DomainFlags == PWR_D2_DOMAIN_FLAGS)
1118 {
1119 /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
1120 SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
1121 }
1122 else
1123 {
1124 /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
1125 SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
1126 /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
1127 SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
1128 }
1129 }
1130
1131 /**
1132 * @brief Hold the CPU and their domain peripherals when exiting STOP mode.
1133 * @param CPU : Specifies the core to be held.
1134 * This parameter can be one of the following values:
1135 * @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master.
1136 * @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master.
1137 * @retval HAL status
1138 */
HAL_PWREx_HoldCore(uint32_t CPU)1139 HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU)
1140 {
1141 HAL_StatusTypeDef status = HAL_OK;
1142
1143 /* Check the parameters */
1144 assert_param (IS_PWR_CORE (CPU));
1145
1146 /* Check CPU index */
1147 if (CPU == PWR_CORE_CPU2)
1148 {
1149 /* If CPU1 is not held */
1150 if ((PWR->CPU2CR & PWR_CPU2CR_HOLD1) != PWR_CPU2CR_HOLD1)
1151 {
1152 /* Set HOLD2 bit */
1153 SET_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
1154 }
1155 else
1156 {
1157 status = HAL_ERROR;
1158 }
1159 }
1160 else
1161 {
1162 /* If CPU2 is not held */
1163 if ((PWR->CPUCR & PWR_CPUCR_HOLD2) != PWR_CPUCR_HOLD2)
1164 {
1165 /* Set HOLD1 bit */
1166 SET_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
1167 }
1168 else
1169 {
1170 status = HAL_ERROR;
1171 }
1172 }
1173
1174 return status;
1175 }
1176
1177 /**
1178 * @brief Release the CPU and their domain peripherals after a wake-up from
1179 * STOP mode.
1180 * @param CPU: Specifies the core to be released.
1181 * This parameter can be one of the following values:
1182 * @arg PWR_CORE_CPU1: Release the CPU1 and their domain
1183 * peripherals from holding.
1184 * @arg PWR_CORE_CPU2: Release the CPU2 and their domain
1185 * peripherals from holding.
1186 * @retval None
1187 */
HAL_PWREx_ReleaseCore(uint32_t CPU)1188 void HAL_PWREx_ReleaseCore (uint32_t CPU)
1189 {
1190 /* Check the parameters */
1191 assert_param (IS_PWR_CORE (CPU));
1192
1193 /* Check CPU index */
1194 if (CPU == PWR_CORE_CPU2)
1195 {
1196 /* Reset HOLD2 bit */
1197 CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
1198 }
1199 else
1200 {
1201 /* Reset HOLD1 bit */
1202 CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
1203 }
1204 }
1205 #endif /* defined (DUAL_CORE) */
1206
1207
1208 /**
1209 * @brief Enable the Flash Power Down in Stop mode.
1210 * @note When Flash Power Down is enabled the Flash memory enters low-power
1211 * mode when D1/SRD domain is in DStop mode. This feature allows to
1212 * obtain the best trade-off between low-power consumption and restart
1213 * time when exiting from DStop mode.
1214 * @retval None.
1215 */
HAL_PWREx_EnableFlashPowerDown(void)1216 void HAL_PWREx_EnableFlashPowerDown (void)
1217 {
1218 /* Enable the Flash Power Down */
1219 SET_BIT (PWR->CR1, PWR_CR1_FLPS);
1220 }
1221
1222 /**
1223 * @brief Disable the Flash Power Down in Stop mode.
1224 * @note When Flash Power Down is disabled the Flash memory is kept on
1225 * normal mode when D1/SRD domain is in DStop mode. This feature allows
1226 * to obtain the best trade-off between low-power consumption and
1227 * restart time when exiting from DStop mode.
1228 * @retval None.
1229 */
HAL_PWREx_DisableFlashPowerDown(void)1230 void HAL_PWREx_DisableFlashPowerDown (void)
1231 {
1232 /* Disable the Flash Power Down */
1233 CLEAR_BIT (PWR->CR1, PWR_CR1_FLPS);
1234 }
1235
1236 #if defined (PWR_CR1_SRDRAMSO)
1237 /**
1238 * @brief Enable memory block shut-off in DStop or DStop2 modes
1239 * @note In DStop or DStop2 mode, the content of the memory blocks is
1240 * maintained. Further power optimization can be obtained by switching
1241 * off some memory blocks. This optimization implies loss of the memory
1242 * content. The user can select which memory is discarded during STOP
1243 * mode by means of xxSO bits.
1244 * @param MemoryBlock : Specifies the memory block to shut-off during DStop or
1245 * DStop2 mode.
1246 * This parameter can be one of the following values:
1247 * @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
1248 * @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
1249 * FDCAN memories.
1250 * @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
1251 * @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
1252 * @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
1253 * @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
1254 * @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
1255 * @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
1256 * @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
1257 * @retval None.
1258 */
HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock)1259 void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock)
1260 {
1261 /* Check the parameter */
1262 assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
1263
1264 /* Enable memory block shut-off */
1265 SET_BIT (PWR->CR1, MemoryBlock);
1266 }
1267
1268 /**
1269 * @brief Disable memory block shut-off in DStop or DStop2 modes
1270 * @param MemoryBlock : Specifies the memory block to keep content during
1271 * DStop or DStop2 mode.
1272 * This parameter can be one of the following values:
1273 * @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
1274 * @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
1275 * FDCAN memories.
1276 * @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
1277 * @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
1278 * @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
1279 * @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
1280 * @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
1281 * @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
1282 * @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
1283 * @retval None.
1284 */
HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock)1285 void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock)
1286 {
1287 /* Check the parameter */
1288 assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
1289
1290 /* Disable memory block shut-off */
1291 CLEAR_BIT (PWR->CR1, MemoryBlock);
1292 }
1293 #endif /* defined (PWR_CR1_SRDRAMSO) */
1294
1295 /**
1296 * @brief Enable the Wake-up PINx functionality.
1297 * @param sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that
1298 * contains the configuration information for the wake-up
1299 * Pin.
1300 * @note For dual core devices, please ensure to configure the EXTI lines for
1301 * the different Cortex-Mx. All combination are allowed: wake up only
1302 * Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and
1303 * Cortex-M4.
1304 * @retval None.
1305 */
HAL_PWREx_EnableWakeUpPin(const PWREx_WakeupPinTypeDef * sPinParams)1306 void HAL_PWREx_EnableWakeUpPin (const PWREx_WakeupPinTypeDef *sPinParams)
1307 {
1308 uint32_t pinConfig;
1309 uint32_t regMask;
1310 const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1;
1311
1312 /* Check the parameters */
1313 assert_param (IS_PWR_WAKEUP_PIN (sPinParams->WakeUpPin));
1314 assert_param (IS_PWR_WAKEUP_PIN_POLARITY (sPinParams->PinPolarity));
1315 assert_param (IS_PWR_WAKEUP_PIN_PULL (sPinParams->PinPull));
1316
1317 pinConfig = sPinParams->WakeUpPin | \
1318 (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \
1319 (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) + PWR_WKUPEPR_WKUPPUPD1_Pos) & 0x1FU));
1320
1321 regMask = sPinParams->WakeUpPin | \
1322 (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
1323 (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU));
1324
1325 /* Enable and Specify the Wake-Up pin polarity and the pull configuration
1326 for the event detection (rising or falling edge) */
1327 MODIFY_REG (PWR->WKUPEPR, regMask, pinConfig);
1328 #ifndef DUAL_CORE
1329 /* Configure the Wakeup Pin EXTI Line */
1330 MODIFY_REG (EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos));
1331 #endif /* !DUAL_CORE */
1332 }
1333
1334 /**
1335 * @brief Disable the Wake-up PINx functionality.
1336 * @param WakeUpPin : Specifies the Wake-Up pin to be disabled.
1337 * This parameter can be one of the following values:
1338 * @arg PWR_WAKEUP_PIN1 : Disable PA0 wake-up PIN.
1339 * @arg PWR_WAKEUP_PIN2 : Disable PA2 wake-up PIN.
1340 * @arg PWR_WAKEUP_PIN3 : Disable PI8 wake-up PIN.
1341 * @arg PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN.
1342 * @arg PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN.
1343 * @arg PWR_WAKEUP_PIN6 : Disable PC1 wake-up PIN.
1344 * @note The PWR_WAKEUP_PIN3 and PWR_WAKEUP_PIN5 are available only for
1345 * devices that support GPIOI port.
1346 * @retval None
1347 */
HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin)1348 void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
1349 {
1350 /* Check the parameter */
1351 assert_param (IS_PWR_WAKEUP_PIN (WakeUpPin));
1352
1353 /* Disable the WakeUpPin */
1354 CLEAR_BIT (PWR->WKUPEPR, WakeUpPin);
1355 }
1356
1357 /**
1358 * @brief Get the Wake-Up Pin pending flags.
1359 * @param WakeUpFlag : Specifies the Wake-Up PIN flag to be checked.
1360 * This parameter can be one of the following values:
1361 * @arg PWR_WAKEUP_FLAG1 : Get wakeup event received from PA0.
1362 * @arg PWR_WAKEUP_FLAG2 : Get wakeup event received from PA2.
1363 * @arg PWR_WAKEUP_FLAG3 : Get wakeup event received from PI8.
1364 * @arg PWR_WAKEUP_FLAG4 : Get wakeup event received from PC13.
1365 * @arg PWR_WAKEUP_FLAG5 : Get wakeup event received from PI11.
1366 * @arg PWR_WAKEUP_FLAG6 : Get wakeup event received from PC1.
1367 * @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all
1368 * wake up pins.
1369 * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for
1370 * devices that support GPIOI port.
1371 * @retval The Wake-Up pin flag.
1372 */
HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag)1373 uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
1374 {
1375 /* Check the parameters */
1376 assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
1377
1378 /* Return the wake up pin flag */
1379 return (PWR->WKUPFR & WakeUpFlag);
1380 }
1381
1382 /**
1383 * @brief Clear the Wake-Up pin pending flag.
1384 * @param WakeUpFlag: Specifies the Wake-Up PIN flag to clear.
1385 * This parameter can be one of the following values:
1386 * @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0.
1387 * @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2.
1388 * @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PI8.
1389 * @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13.
1390 * @arg PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI11.
1391 * @arg PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PC1.
1392 * @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from
1393 * all wake up pins.
1394 * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for
1395 * devices that support GPIOI port.
1396 * @retval HAL status.
1397 */
HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag)1398 HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
1399 {
1400 /* Check the parameter */
1401 assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
1402
1403 /* Clear the wake up event received from wake up pin x */
1404 SET_BIT (PWR->WKUPCR, WakeUpFlag);
1405
1406 /* Check if the wake up event is well cleared */
1407 if ((PWR->WKUPFR & WakeUpFlag) != 0U)
1408 {
1409 return HAL_ERROR;
1410 }
1411
1412 return HAL_OK;
1413 }
1414
1415 /**
1416 * @brief This function handles the PWR WAKEUP PIN interrupt request.
1417 * @note This API should be called under the WAKEUP_PIN_IRQHandler().
1418 * @retval None.
1419 */
HAL_PWREx_WAKEUP_PIN_IRQHandler(void)1420 void HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
1421 {
1422 /* Wakeup pin EXTI line interrupt detected */
1423 if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U)
1424 {
1425 /* Clear PWR WKUPF1 flag */
1426 __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP1);
1427
1428 /* PWR WKUP1 interrupt user callback */
1429 HAL_PWREx_WKUP1_Callback ();
1430 }
1431 else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U)
1432 {
1433 /* Clear PWR WKUPF2 flag */
1434 __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP2);
1435
1436 /* PWR WKUP2 interrupt user callback */
1437 HAL_PWREx_WKUP2_Callback ();
1438 }
1439 #if defined (PWR_WKUPFR_WKUPF3)
1440 else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U)
1441 {
1442 /* Clear PWR WKUPF3 flag */
1443 __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP3);
1444
1445 /* PWR WKUP3 interrupt user callback */
1446 HAL_PWREx_WKUP3_Callback ();
1447 }
1448 #endif /* defined (PWR_WKUPFR_WKUPF3) */
1449 else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U)
1450 {
1451 /* Clear PWR WKUPF4 flag */
1452 __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP4);
1453
1454 /* PWR WKUP4 interrupt user callback */
1455 HAL_PWREx_WKUP4_Callback ();
1456 }
1457 #if defined (PWR_WKUPFR_WKUPF5)
1458 else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U)
1459 {
1460 /* Clear PWR WKUPF5 flag */
1461 __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP5);
1462
1463 /* PWR WKUP5 interrupt user callback */
1464 HAL_PWREx_WKUP5_Callback ();
1465 }
1466 #endif /* defined (PWR_WKUPFR_WKUPF5) */
1467 else
1468 {
1469 /* Clear PWR WKUPF6 flag */
1470 __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP6);
1471
1472 /* PWR WKUP6 interrupt user callback */
1473 HAL_PWREx_WKUP6_Callback ();
1474 }
1475 }
1476
1477 /**
1478 * @brief PWR WKUP1 interrupt callback.
1479 * @retval None.
1480 */
HAL_PWREx_WKUP1_Callback(void)1481 __weak void HAL_PWREx_WKUP1_Callback (void)
1482 {
1483 /* NOTE : This function should not be modified, when the callback is needed,
1484 the HAL_PWREx_WKUP1Callback can be implemented in the user file
1485 */
1486 }
1487
1488 /**
1489 * @brief PWR WKUP2 interrupt callback.
1490 * @retval None.
1491 */
HAL_PWREx_WKUP2_Callback(void)1492 __weak void HAL_PWREx_WKUP2_Callback (void)
1493 {
1494 /* NOTE : This function should not be modified, when the callback is needed,
1495 the HAL_PWREx_WKUP2Callback can be implemented in the user file
1496 */
1497 }
1498
1499 #if defined (PWR_WKUPFR_WKUPF3)
1500 /**
1501 * @brief PWR WKUP3 interrupt callback.
1502 * @retval None.
1503 */
HAL_PWREx_WKUP3_Callback(void)1504 __weak void HAL_PWREx_WKUP3_Callback (void)
1505 {
1506 /* NOTE : This function should not be modified, when the callback is needed,
1507 the HAL_PWREx_WKUP3Callback can be implemented in the user file
1508 */
1509 }
1510 #endif /* defined (PWR_WKUPFR_WKUPF3) */
1511
1512 /**
1513 * @brief PWR WKUP4 interrupt callback.
1514 * @retval None.
1515 */
HAL_PWREx_WKUP4_Callback(void)1516 __weak void HAL_PWREx_WKUP4_Callback (void)
1517 {
1518 /* NOTE : This function should not be modified, when the callback is needed,
1519 the HAL_PWREx_WKUP4Callback can be implemented in the user file
1520 */
1521 }
1522
1523 #if defined (PWR_WKUPFR_WKUPF5)
1524 /**
1525 * @brief PWR WKUP5 interrupt callback.
1526 * @retval None.
1527 */
HAL_PWREx_WKUP5_Callback(void)1528 __weak void HAL_PWREx_WKUP5_Callback (void)
1529 {
1530 /* NOTE : This function should not be modified, when the callback is needed,
1531 the HAL_PWREx_WKUP5Callback can be implemented in the user file
1532 */
1533 }
1534 #endif /* defined (PWR_WKUPFR_WKUPF5) */
1535
1536 /**
1537 * @brief PWR WKUP6 interrupt callback.
1538 * @retval None.
1539 */
HAL_PWREx_WKUP6_Callback(void)1540 __weak void HAL_PWREx_WKUP6_Callback (void)
1541 {
1542 /* NOTE : This function should not be modified, when the callback is needed,
1543 the HAL_PWREx_WKUP6Callback can be implemented in the user file
1544 */
1545 }
1546 /**
1547 * @}
1548 */
1549
1550 /** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions
1551 * @brief Peripherals control functions
1552 *
1553 @verbatim
1554 ===============================================================================
1555 ##### Peripherals control functions #####
1556 ===============================================================================
1557
1558 *** Main and Backup Regulators configuration ***
1559 ================================================
1560 [..]
1561 (+) The backup domain includes 4 Kbytes of backup SRAM accessible only
1562 from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its
1563 content is retained even in Standby or VBAT mode when the low power
1564 backup regulator is enabled. It can be considered as an internal
1565 EEPROM when VBAT is always present. You can use the
1566 HAL_PWREx_EnableBkUpReg() function to enable the low power backup
1567 regulator.
1568 (+) When the backup domain is supplied by VDD (analog switch connected to
1569 VDD) the backup SRAM is powered from VDD which replaces the VBAT power
1570 supply to save battery life.
1571 (+) The backup SRAM is not mass erased by a tamper event. It is read
1572 protected to prevent confidential data, such as cryptographic private
1573 key, from being accessed. The backup SRAM can be erased only through
1574 the Flash interface when a protection level change from level 1 to
1575 level 0 is requested.
1576 -@- Refer to the description of Read protection (RDP) in the Flash
1577 programming manual.
1578 (+) The main internal regulator can be configured to have a tradeoff
1579 between performance and power consumption when the device does not
1580 operate at the maximum frequency. This is done through
1581 HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS
1582 bit in PWR_D3CR register.
1583 (+) The main internal regulator can be configured to operate in Low Power
1584 mode when the system enters STOP mode to further reduce power
1585 consumption.
1586 This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS)
1587 function which configure the SVOS bit in PWR_CR1 register.
1588 The selected SVOS4 and SVOS5 levels add an additional startup delay
1589 when exiting from system Stop mode.
1590 -@- Refer to the product datasheets for more details.
1591
1592 *** USB Regulator configuration ***
1593 ===================================
1594 [..]
1595 (+) The USB transceivers are supplied from a dedicated VDD33USB supply
1596 that can be provided either by the integrated USB regulator, or by an
1597 external USB supply.
1598 (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the
1599 VDD33USB is then provided from the USB regulator.
1600 (+) When the USB regulator is enabled, the VDD33USB supply level detector
1601 shall be enabled through HAL_PWREx_EnableUSBVoltageDetector()
1602 function.
1603 (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg()
1604 function and VDD33USB can be provided from an external supply. In this
1605 case VDD33USB and VDD50USB shall be connected together.
1606
1607 *** VBAT battery charging ***
1608 =============================
1609 [..]
1610 (+) When VDD is present, the external battery connected to VBAT can be
1611 charged through an internal resistance. VBAT charging can be performed
1612 either through a 5 KOhm resistor or through a 1.5 KOhm resistor.
1613 (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging
1614 (ResistorValue) function with:
1615 (++) ResistorValue:
1616 (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
1617 (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
1618 (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging()
1619 function.
1620
1621 @endverbatim
1622 * @{
1623 */
1624
1625 /**
1626 * @brief Enable the Backup Regulator.
1627 * @retval HAL status.
1628 */
HAL_PWREx_EnableBkUpReg(void)1629 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void)
1630 {
1631 uint32_t tickstart;
1632
1633 /* Enable the Backup regulator */
1634 SET_BIT (PWR->CR2, PWR_CR2_BREN);
1635
1636 /* Get tick */
1637 tickstart = HAL_GetTick ();
1638
1639 /* Wait till Backup regulator ready flag is set */
1640 while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) == 0U)
1641 {
1642 if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
1643 {
1644 return HAL_ERROR;
1645 }
1646 }
1647
1648 return HAL_OK;
1649 }
1650
1651 /**
1652 * @brief Disable the Backup Regulator.
1653 * @retval HAL status.
1654 */
HAL_PWREx_DisableBkUpReg(void)1655 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void)
1656 {
1657 uint32_t tickstart;
1658
1659 /* Disable the Backup regulator */
1660 CLEAR_BIT (PWR->CR2, PWR_CR2_BREN);
1661
1662 /* Get tick */
1663 tickstart = HAL_GetTick ();
1664
1665 /* Wait till Backup regulator ready flag is reset */
1666 while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) != 0U)
1667 {
1668 if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
1669 {
1670 return HAL_ERROR;
1671 }
1672 }
1673
1674 return HAL_OK;
1675 }
1676
1677 /**
1678 * @brief Enable the USB Regulator.
1679 * @retval HAL status.
1680 */
HAL_PWREx_EnableUSBReg(void)1681 HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void)
1682 {
1683 uint32_t tickstart;
1684
1685 /* Enable the USB regulator */
1686 SET_BIT (PWR->CR3, PWR_CR3_USBREGEN);
1687
1688 /* Get tick */
1689 tickstart = HAL_GetTick ();
1690
1691 /* Wait till the USB regulator ready flag is set */
1692 while (__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) == 0U)
1693 {
1694 if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
1695 {
1696 return HAL_ERROR;
1697 }
1698 }
1699
1700 return HAL_OK;
1701 }
1702
1703 /**
1704 * @brief Disable the USB Regulator.
1705 * @retval HAL status.
1706 */
HAL_PWREx_DisableUSBReg(void)1707 HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void)
1708 {
1709 uint32_t tickstart;
1710
1711 /* Disable the USB regulator */
1712 CLEAR_BIT (PWR->CR3, PWR_CR3_USBREGEN);
1713
1714 /* Get tick */
1715 tickstart = HAL_GetTick ();
1716
1717 /* Wait till the USB regulator ready flag is reset */
1718 while(__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) != 0U)
1719 {
1720 if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
1721 {
1722 return HAL_ERROR;
1723 }
1724 }
1725
1726 return HAL_OK;
1727 }
1728
1729 /**
1730 * @brief Enable the USB voltage level detector.
1731 * @retval None.
1732 */
HAL_PWREx_EnableUSBVoltageDetector(void)1733 void HAL_PWREx_EnableUSBVoltageDetector (void)
1734 {
1735 /* Enable the USB voltage detector */
1736 SET_BIT (PWR->CR3, PWR_CR3_USB33DEN);
1737 }
1738
1739 /**
1740 * @brief Disable the USB voltage level detector.
1741 * @retval None.
1742 */
HAL_PWREx_DisableUSBVoltageDetector(void)1743 void HAL_PWREx_DisableUSBVoltageDetector (void)
1744 {
1745 /* Disable the USB voltage detector */
1746 CLEAR_BIT (PWR->CR3, PWR_CR3_USB33DEN);
1747 }
1748
1749 /**
1750 * @brief Enable the Battery charging.
1751 * @note When VDD is present, charge the external battery through an internal
1752 * resistor.
1753 * @param ResistorValue : Specifies the charging resistor.
1754 * This parameter can be one of the following values :
1755 * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor.
1756 * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor.
1757 * @retval None.
1758 */
HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue)1759 void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue)
1760 {
1761 /* Check the parameter */
1762 assert_param (IS_PWR_BATTERY_RESISTOR_SELECT (ResistorValue));
1763
1764 /* Specify the charging resistor */
1765 MODIFY_REG (PWR->CR3, PWR_CR3_VBRS, ResistorValue);
1766
1767 /* Enable the Battery charging */
1768 SET_BIT (PWR->CR3, PWR_CR3_VBE);
1769 }
1770
1771 /**
1772 * @brief Disable the Battery charging.
1773 * @retval None.
1774 */
HAL_PWREx_DisableBatteryCharging(void)1775 void HAL_PWREx_DisableBatteryCharging (void)
1776 {
1777 /* Disable the Battery charging */
1778 CLEAR_BIT (PWR->CR3, PWR_CR3_VBE);
1779 }
1780
1781 #if defined (PWR_CR1_BOOSTE)
1782 /**
1783 * @brief Enable the booster to guarantee the analog switch AC performance when
1784 * the VDD supply voltage is below 2V7.
1785 * @note The VDD supply voltage can be monitored through the PVD and the PLS
1786 * field bits.
1787 * @retval None.
1788 */
HAL_PWREx_EnableAnalogBooster(void)1789 void HAL_PWREx_EnableAnalogBooster (void)
1790 {
1791 /* Enable the Analog voltage */
1792 SET_BIT (PWR->CR1, PWR_CR1_AVD_READY);
1793
1794 /* Enable VDDA booster */
1795 SET_BIT (PWR->CR1, PWR_CR1_BOOSTE);
1796 }
1797
1798 /**
1799 * @brief Disable the analog booster.
1800 * @retval None.
1801 */
HAL_PWREx_DisableAnalogBooster(void)1802 void HAL_PWREx_DisableAnalogBooster (void)
1803 {
1804 /* Disable VDDA booster */
1805 CLEAR_BIT (PWR->CR1, PWR_CR1_BOOSTE);
1806
1807 /* Disable the Analog voltage */
1808 CLEAR_BIT (PWR->CR1, PWR_CR1_AVD_READY);
1809 }
1810 #endif /* defined (PWR_CR1_BOOSTE) */
1811 /**
1812 * @}
1813 */
1814
1815 /** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions
1816 * @brief Power Monitoring functions
1817 *
1818 @verbatim
1819 ===============================================================================
1820 ##### Power Monitoring functions #####
1821 ===============================================================================
1822
1823 *** VBAT and Temperature supervision ***
1824 ========================================
1825 [..]
1826 (+) The VBAT battery voltage supply can be monitored by comparing it with
1827 two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags
1828 in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or
1829 lower than the threshold.
1830 (+) The temperature can be monitored by comparing it with two threshold
1831 levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR
1832 control register 2 (PWR_CR2), indicate whether the device temperature
1833 is higher or lower than the threshold.
1834 (+) The VBAT and the temperature monitoring is enabled by
1835 HAL_PWREx_EnableMonitoring() function and disabled by
1836 HAL_PWREx_DisableMonitoring() function.
1837 (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can
1838 be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
1839 PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
1840 (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature
1841 level which can be :
1842 PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
1843 PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.
1844
1845 *** AVD configuration ***
1846 =========================
1847 [..]
1848 (+) The AVD is used to monitor the VDDA power supply by comparing it to a
1849 threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1
1850 register).
1851 (+) A AVDO flag is available to indicate if VDDA is higher or lower
1852 than the AVD threshold. This event is internally connected to the EXTI
1853 line 16 to generate an interrupt if enabled.
1854 It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro.
1855 (+) The AVD is stopped in System Standby mode.
1856
1857 @endverbatim
1858 * @{
1859 */
1860
1861 /**
1862 * @brief Enable the VBAT and temperature monitoring.
1863 * @retval HAL status.
1864 */
HAL_PWREx_EnableMonitoring(void)1865 void HAL_PWREx_EnableMonitoring (void)
1866 {
1867 /* Enable the VBAT and Temperature monitoring */
1868 SET_BIT (PWR->CR2, PWR_CR2_MONEN);
1869 }
1870
1871 /**
1872 * @brief Disable the VBAT and temperature monitoring.
1873 * @retval HAL status.
1874 */
HAL_PWREx_DisableMonitoring(void)1875 void HAL_PWREx_DisableMonitoring (void)
1876 {
1877 /* Disable the VBAT and Temperature monitoring */
1878 CLEAR_BIT (PWR->CR2, PWR_CR2_MONEN);
1879 }
1880
1881 /**
1882 * @brief Indicate whether the junction temperature is between, above or below
1883 * the thresholds.
1884 * @retval Temperature level.
1885 */
HAL_PWREx_GetTemperatureLevel(void)1886 uint32_t HAL_PWREx_GetTemperatureLevel (void)
1887 {
1888 uint32_t tempLevel, regValue;
1889
1890 /* Read the temperature flags */
1891 regValue = READ_BIT (PWR->CR2, (PWR_CR2_TEMPH | PWR_CR2_TEMPL));
1892
1893 /* Check if the temperature is below the threshold */
1894 if (regValue == PWR_CR2_TEMPL)
1895 {
1896 tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD;
1897 }
1898 /* Check if the temperature is above the threshold */
1899 else if (regValue == PWR_CR2_TEMPH)
1900 {
1901 tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD;
1902 }
1903 /* The temperature is between the thresholds */
1904 else
1905 {
1906 tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD;
1907 }
1908
1909 return tempLevel;
1910 }
1911
1912 /**
1913 * @brief Indicate whether the Battery voltage level is between, above or below
1914 * the thresholds.
1915 * @retval VBAT level.
1916 */
HAL_PWREx_GetVBATLevel(void)1917 uint32_t HAL_PWREx_GetVBATLevel (void)
1918 {
1919 uint32_t VBATLevel, regValue;
1920
1921 /* Read the VBAT flags */
1922 regValue = READ_BIT (PWR->CR2, (PWR_CR2_VBATH | PWR_CR2_VBATL));
1923
1924 /* Check if the VBAT is below the threshold */
1925 if (regValue == PWR_CR2_VBATL)
1926 {
1927 VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD;
1928 }
1929 /* Check if the VBAT is above the threshold */
1930 else if (regValue == PWR_CR2_VBATH)
1931 {
1932 VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD;
1933 }
1934 /* The VBAT is between the thresholds */
1935 else
1936 {
1937 VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD;
1938 }
1939
1940 return VBATLevel;
1941 }
1942
1943 #if defined (PWR_CSR1_MMCVDO)
1944 /**
1945 * @brief Get the VDDMMC voltage level.
1946 * @retval The VDDMMC voltage level.
1947 */
HAL_PWREx_GetMMCVoltage(void)1948 PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void)
1949 {
1950 PWREx_MMC_VoltageLevel mmc_voltage;
1951
1952 /* Check voltage detector output on VDDMMC value */
1953 if ((PWR->CSR1 & PWR_CSR1_MMCVDO_Msk) == 0U)
1954 {
1955 mmc_voltage = PWR_MMC_VOLTAGE_BELOW_1V2;
1956 }
1957 else
1958 {
1959 mmc_voltage = PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2;
1960 }
1961
1962 return mmc_voltage;
1963 }
1964 #endif /* defined (PWR_CSR1_MMCVDO) */
1965
1966 /**
1967 * @brief Configure the event mode and the voltage threshold detected by the
1968 * Analog Voltage Detector (AVD).
1969 * @param sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains
1970 * the configuration information for the AVD.
1971 * @note Refer to the electrical characteristics of your device datasheet for
1972 * more details about the voltage threshold corresponding to each
1973 * detection level.
1974 * @note For dual core devices, please ensure to configure the EXTI lines for
1975 * the different Cortex-Mx through PWR_Exported_Macro provided by this
1976 * driver. All combination are allowed: wake up only Cortex-M7, wake up
1977 * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4.
1978 * @retval None.
1979 */
HAL_PWREx_ConfigAVD(const PWREx_AVDTypeDef * sConfigAVD)1980 void HAL_PWREx_ConfigAVD (const PWREx_AVDTypeDef *sConfigAVD)
1981 {
1982 /* Check the parameters */
1983 assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel));
1984 assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode));
1985
1986 /* Set the ALS[18:17] bits according to AVDLevel value */
1987 MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
1988
1989 /* Clear any previous config */
1990 #if !defined (DUAL_CORE)
1991 __HAL_PWR_AVD_EXTI_DISABLE_EVENT ();
1992 __HAL_PWR_AVD_EXTI_DISABLE_IT ();
1993 #endif /* !defined (DUAL_CORE) */
1994
1995 __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE ();
1996 __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE ();
1997
1998 #if !defined (DUAL_CORE)
1999 /* Configure the interrupt mode */
2000 if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT)
2001 {
2002 __HAL_PWR_AVD_EXTI_ENABLE_IT ();
2003 }
2004
2005 /* Configure the event mode */
2006 if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT)
2007 {
2008 __HAL_PWR_AVD_EXTI_ENABLE_EVENT ();
2009 }
2010 #endif /* !defined (DUAL_CORE) */
2011
2012 /* Rising edge configuration */
2013 if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE)
2014 {
2015 __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE ();
2016 }
2017
2018 /* Falling edge configuration */
2019 if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE)
2020 {
2021 __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE ();
2022 }
2023 }
2024
2025 /**
2026 * @brief Enable the Analog Voltage Detector (AVD).
2027 * @retval None.
2028 */
HAL_PWREx_EnableAVD(void)2029 void HAL_PWREx_EnableAVD (void)
2030 {
2031 /* Enable the Analog Voltage Detector */
2032 SET_BIT (PWR->CR1, PWR_CR1_AVDEN);
2033 }
2034
2035 /**
2036 * @brief Disable the Analog Voltage Detector(AVD).
2037 * @retval None.
2038 */
HAL_PWREx_DisableAVD(void)2039 void HAL_PWREx_DisableAVD (void)
2040 {
2041 /* Disable the Analog Voltage Detector */
2042 CLEAR_BIT (PWR->CR1, PWR_CR1_AVDEN);
2043 }
2044
2045 /**
2046 * @brief This function handles the PWR PVD/AVD interrupt request.
2047 * @note This API should be called under the PVD_AVD_IRQHandler().
2048 * @retval None
2049 */
HAL_PWREx_PVD_AVD_IRQHandler(void)2050 void HAL_PWREx_PVD_AVD_IRQHandler (void)
2051 {
2052 /* Check if the Programmable Voltage Detector is enabled (PVD) */
2053 if (READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U)
2054 {
2055 #if defined (DUAL_CORE)
2056 if (HAL_GetCurrentCPUID () == CM7_CPUID)
2057 #endif /* defined (DUAL_CORE) */
2058 {
2059 /* Check PWR D1/CD EXTI flag */
2060 if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
2061 {
2062 /* PWR PVD interrupt user callback */
2063 HAL_PWR_PVDCallback ();
2064
2065 if(__HAL_PWR_GET_FLAG (PWR_FLAG_AVDO) == 0U)
2066 {
2067 /* Clear PWR EXTI D1/CD pending bit */
2068 __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
2069 }
2070 }
2071 }
2072 #if defined (DUAL_CORE)
2073 else
2074 {
2075 /* Check PWR EXTI D2 flag */
2076 if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
2077 {
2078 /* PWR PVD interrupt user callback */
2079 HAL_PWR_PVDCallback ();
2080
2081 if(__HAL_PWR_GET_FLAG (PWR_FLAG_AVDO) == 0U)
2082 {
2083 /* Clear PWR EXTI D2 pending bit */
2084 __HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
2085 }
2086 }
2087 }
2088 #endif /* defined (DUAL_CORE) */
2089 }
2090
2091 /* Check if the Analog Voltage Detector is enabled (AVD) */
2092 if (READ_BIT (PWR->CR1, PWR_CR1_AVDEN) != 0U)
2093 {
2094 #if defined (DUAL_CORE)
2095 if (HAL_GetCurrentCPUID () == CM7_CPUID)
2096 #endif /* defined (DUAL_CORE) */
2097 {
2098 /* Check PWR EXTI D1/CD flag */
2099 if (__HAL_PWR_AVD_EXTI_GET_FLAG () != 0U)
2100 {
2101 /* PWR AVD interrupt user callback */
2102 HAL_PWREx_AVDCallback ();
2103
2104 if(__HAL_PWR_GET_FLAG (PWR_FLAG_PVDO) == 0U)
2105 {
2106 /* Clear PWR EXTI D1/CD pending bit */
2107 __HAL_PWR_AVD_EXTI_CLEAR_FLAG ();
2108 }
2109 }
2110 }
2111 #if defined (DUAL_CORE)
2112 else
2113 {
2114 /* Check PWR EXTI D2 flag */
2115 if (__HAL_PWR_AVD_EXTID2_GET_FLAG () != 0U)
2116 {
2117 /* PWR AVD interrupt user callback */
2118 HAL_PWREx_AVDCallback ();
2119
2120 if(__HAL_PWR_GET_FLAG (PWR_FLAG_PVDO) == 0U)
2121 {
2122 /* Clear PWR EXTI D2 pending bit */
2123 __HAL_PWR_AVD_EXTID2_CLEAR_FLAG ();
2124 }
2125 }
2126 }
2127 #endif /* defined (DUAL_CORE) */
2128 }
2129 }
2130
2131 /**
2132 * @brief PWR AVD interrupt callback.
2133 * @retval None.
2134 */
HAL_PWREx_AVDCallback(void)2135 __weak void HAL_PWREx_AVDCallback (void)
2136 {
2137 /* NOTE : This function should not be modified, when the callback is needed,
2138 the HAL_PWR_AVDCallback can be implemented in the user file
2139 */
2140 }
2141 /**
2142 * @}
2143 */
2144
2145 /**
2146 * @}
2147 */
2148
2149 #endif /* HAL_PWR_MODULE_ENABLED */
2150
2151 /**
2152 * @}
2153 */
2154
2155 /**
2156 * @}
2157 */
2158
2159
