1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2017 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for
43 the transmit or receive stream or channel depends on Instance
44 (+++) Enable the DMAx interface clock using
45 (+++) Configure the DMA handle parameters
46 (+++) Configure the DMA Tx or Rx stream or channel depends on Instance
47 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
48 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
49 the DMA Tx or Rx stream or channel depends on Instance
50
51 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
52 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
53
54 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
55 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
56
57 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
58
59 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
60
61 *** Polling mode IO operation ***
62 =================================
63 [..]
64 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
65 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
66 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
67 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
68
69 *** Polling mode IO MEM operation ***
70 =====================================
71 [..]
72 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
73 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
74
75
76 *** Interrupt mode IO operation ***
77 ===================================
78 [..]
79 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
80 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
81 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
82 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
83 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
84 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
85 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
86 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
87 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
88 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
89 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
90 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
91 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
92 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
93 (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
94 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
95 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
96 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
97 This action will inform Master to generate a Stop condition to discard the communication.
98
99
100 *** Interrupt mode or DMA mode IO sequential operation ***
101 ==========================================================
102 [..]
103 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
104 when a direction change during transfer
105 [..]
106 (+) A specific option field manage the different steps of a sequential transfer
107 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
108 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
109 no sequential mode
110 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
111 and data to transfer without a final stop condition
112 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
113 start condition, address and data to transfer without a final stop condition,
114 an then permit a call the same master sequential interface several times
115 (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
116 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
117 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
118 and with new data to transfer if the direction change or manage only the new data to
119 transfer
120 if no direction change and without a final stop condition in both cases
121 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
122 and with new data to transfer if the direction change or manage only the new data to
123 transfer
124 if no direction change and with a final stop condition in both cases
125 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
126 after several call of the same master sequential interface several times
127 (link with option I2C_FIRST_AND_NEXT_FRAME).
128 Usage can, transfer several bytes one by one using
129 HAL_I2C_Master_Seq_Transmit_IT
130 or HAL_I2C_Master_Seq_Receive_IT
131 or HAL_I2C_Master_Seq_Transmit_DMA
132 or HAL_I2C_Master_Seq_Receive_DMA
133 with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
134 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
135 Receive sequence permit to call the opposite interface Receive or Transmit
136 without stopping the communication and so generate a restart condition.
137 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
138 each call of the same master sequential
139 interface.
140 Usage can, transfer several bytes one by one with a restart with slave address between
141 each bytes using
142 HAL_I2C_Master_Seq_Transmit_IT
143 or HAL_I2C_Master_Seq_Receive_IT
144 or HAL_I2C_Master_Seq_Transmit_DMA
145 or HAL_I2C_Master_Seq_Receive_DMA
146 with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
147 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
148 generation of STOP condition.
149
150 (+) Different sequential I2C interfaces are listed below:
151 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
152 HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
153 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
154 users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
155 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
156 HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
157 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
158 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
159 (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
160 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
161 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
162 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
163 HAL_I2C_DisableListen_IT()
164 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
165 add their own code to check the Address Match Code and the transmission direction request by master
166 (Write/Read).
167 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
168 add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
169 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
170 HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
171 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
172 users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
173 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
174 HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
175 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
176 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
177 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
178 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
179 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
180 This action will inform Master to generate a Stop condition to discard the communication.
181
182 *** Interrupt mode IO MEM operation ***
183 =======================================
184 [..]
185 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
186 HAL_I2C_Mem_Write_IT()
187 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
188 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
189 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
190 HAL_I2C_Mem_Read_IT()
191 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
192 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
193 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
194 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
195
196 *** DMA mode IO operation ***
197 ==============================
198 [..]
199 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
200 HAL_I2C_Master_Transmit_DMA()
201 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
202 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
203 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
204 HAL_I2C_Master_Receive_DMA()
205 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
206 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
207 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
208 HAL_I2C_Slave_Transmit_DMA()
209 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
210 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
211 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
212 HAL_I2C_Slave_Receive_DMA()
213 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
214 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
215 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
216 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
217 (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
218 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
219 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
220 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
221 This action will inform Master to generate a Stop condition to discard the communication.
222
223 *** DMA mode IO MEM operation ***
224 =================================
225 [..]
226 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
227 HAL_I2C_Mem_Write_DMA()
228 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
229 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
230 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
231 HAL_I2C_Mem_Read_DMA()
232 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
233 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
234 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
235 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
236
237
238 *** I2C HAL driver macros list ***
239 ==================================
240 [..]
241 Below the list of most used macros in I2C HAL driver.
242
243 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
244 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
245 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
246 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
247 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
248 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
249 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
250
251 *** Callback registration ***
252 =============================================
253 [..]
254 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
255 allows the user to configure dynamically the driver callbacks.
256 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
257 to register an interrupt callback.
258 [..]
259 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
260 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
261 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
262 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
263 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
264 (+) ListenCpltCallback : callback for end of listen mode.
265 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
266 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
267 (+) ErrorCallback : callback for error detection.
268 (+) AbortCpltCallback : callback for abort completion process.
269 (+) MspInitCallback : callback for Msp Init.
270 (+) MspDeInitCallback : callback for Msp DeInit.
271 This function takes as parameters the HAL peripheral handle, the Callback ID
272 and a pointer to the user callback function.
273 [..]
274 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
275 [..]
276 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
277 weak function.
278 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
279 and the Callback ID.
280 This function allows to reset following callbacks:
281 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
282 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
283 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
284 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
285 (+) ListenCpltCallback : callback for end of listen mode.
286 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
287 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
288 (+) ErrorCallback : callback for error detection.
289 (+) AbortCpltCallback : callback for abort completion process.
290 (+) MspInitCallback : callback for Msp Init.
291 (+) MspDeInitCallback : callback for Msp DeInit.
292 [..]
293 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
294 [..]
295 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
296 all callbacks are set to the corresponding weak functions:
297 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
298 Exception done for MspInit and MspDeInit functions that are
299 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
300 these callbacks are null (not registered beforehand).
301 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
302 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
303 [..]
304 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
305 Exception done MspInit/MspDeInit functions that can be registered/unregistered
306 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
307 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
308 Then, the user first registers the MspInit/MspDeInit user callbacks
309 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
310 or HAL_I2C_Init() function.
311 [..]
312 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
313 not defined, the callback registration feature is not available and all callbacks
314 are set to the corresponding weak functions.
315
316 [..]
317 (@) You can refer to the I2C HAL driver header file for more useful macros
318
319 @endverbatim
320 */
321
322 /* Includes ------------------------------------------------------------------*/
323 #include "stm32h7xx_hal.h"
324
325 /** @addtogroup STM32H7xx_HAL_Driver
326 * @{
327 */
328
329 /** @defgroup I2C I2C
330 * @brief I2C HAL module driver
331 * @{
332 */
333
334 #ifdef HAL_I2C_MODULE_ENABLED
335
336 /* Private typedef -----------------------------------------------------------*/
337 /* Private define ------------------------------------------------------------*/
338
339 /** @defgroup I2C_Private_Define I2C Private Define
340 * @{
341 */
342 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
343 #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
344 #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
345 #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
346 #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
347 #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
348 #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
349 #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
350 #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
351 #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
352
353 #define MAX_NBYTE_SIZE 255U
354 #define SLAVE_ADDR_SHIFT 7U
355 #define SLAVE_ADDR_MSK 0x06U
356
357 /* Private define for @ref PreviousState usage */
358 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
359 (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
360 (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
361 /*!< Mask State define, keep only RX and TX bits */
362 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
363 /*!< Default Value */
364 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
365 (uint32_t)HAL_I2C_MODE_MASTER))
366 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
367 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
368 (uint32_t)HAL_I2C_MODE_MASTER))
369 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
370 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
371 (uint32_t)HAL_I2C_MODE_SLAVE))
372 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
373 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
374 (uint32_t)HAL_I2C_MODE_SLAVE))
375 /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
376 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
377 (uint32_t)HAL_I2C_MODE_MEM))
378 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
379 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
380 (uint32_t)HAL_I2C_MODE_MEM))
381 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
382
383
384 /* Private define to centralize the enable/disable of Interrupts */
385 #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
386 @ref I2C_XFER_LISTEN_IT */
387 #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
388 @ref I2C_XFER_LISTEN_IT */
389 #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
390 and @ref I2C_XFER_RX_IT */
391
392 #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
393 and NACK treatment */
394 #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
395 #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
396
397 /* Private define Sequential Transfer Options default/reset value */
398 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
399 /**
400 * @}
401 */
402
403 /* Private macros ------------------------------------------------------------*/
404 /** @addtogroup I2C_Private_Macro
405 * @{
406 */
407 /* Macro to get remaining data to transfer on DMA side */
408 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
409 /**
410 * @}
411 */
412
413 /* Private variables ---------------------------------------------------------*/
414 /* Private function prototypes -----------------------------------------------*/
415
416 /** @defgroup I2C_Private_Functions I2C Private Functions
417 * @{
418 */
419 /* Private functions to handle DMA transfer */
420 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
421 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
422 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
423 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
424 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
425 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
426
427
428 /* Private functions to handle IT transfer */
429 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
430 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
431 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
432 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
433 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
434 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
435 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
436
437 /* Private functions to handle IT transfer */
438 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
439 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
440 uint32_t Tickstart);
441 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
442 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
443 uint32_t Tickstart);
444
445 /* Private functions for I2C transfer IRQ handler */
446 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
447 uint32_t ITSources);
448 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
449 uint32_t ITSources);
450 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
451 uint32_t ITSources);
452 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
453 uint32_t ITSources);
454 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
455 uint32_t ITSources);
456 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
457 uint32_t ITSources);
458
459 /* Private functions to handle flags during polling transfer */
460 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
461 uint32_t Timeout, uint32_t Tickstart);
462 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
463 uint32_t Tickstart);
464 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
465 uint32_t Tickstart);
466 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
467 uint32_t Tickstart);
468 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
469 uint32_t Tickstart);
470
471 /* Private functions to centralize the enable/disable of Interrupts */
472 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
473 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
474
475 /* Private function to treat different error callback */
476 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
477
478 /* Private function to flush TXDR register */
479 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
480
481 /* Private function to handle start, restart or stop a transfer */
482 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
483 uint32_t Request);
484
485 /* Private function to Convert Specific options */
486 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
487 /**
488 * @}
489 */
490
491 /* Exported functions --------------------------------------------------------*/
492
493 /** @defgroup I2C_Exported_Functions I2C Exported Functions
494 * @{
495 */
496
497 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
498 * @brief Initialization and Configuration functions
499 *
500 @verbatim
501 ===============================================================================
502 ##### Initialization and de-initialization functions #####
503 ===============================================================================
504 [..] This subsection provides a set of functions allowing to initialize and
505 deinitialize the I2Cx peripheral:
506
507 (+) User must Implement HAL_I2C_MspInit() function in which he configures
508 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
509
510 (+) Call the function HAL_I2C_Init() to configure the selected device with
511 the selected configuration:
512 (++) Clock Timing
513 (++) Own Address 1
514 (++) Addressing mode (Master, Slave)
515 (++) Dual Addressing mode
516 (++) Own Address 2
517 (++) Own Address 2 Mask
518 (++) General call mode
519 (++) Nostretch mode
520
521 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
522 of the selected I2Cx peripheral.
523
524 @endverbatim
525 * @{
526 */
527
528 /**
529 * @brief Initializes the I2C according to the specified parameters
530 * in the I2C_InitTypeDef and initialize the associated handle.
531 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
532 * the configuration information for the specified I2C.
533 * @retval HAL status
534 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)535 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
536 {
537 /* Check the I2C handle allocation */
538 if (hi2c == NULL)
539 {
540 return HAL_ERROR;
541 }
542
543 /* Check the parameters */
544 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
545 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
546 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
547 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
548 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
549 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
550 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
551 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
552
553 if (hi2c->State == HAL_I2C_STATE_RESET)
554 {
555 /* Allocate lock resource and initialize it */
556 hi2c->Lock = HAL_UNLOCKED;
557
558 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
559 /* Init the I2C Callback settings */
560 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
561 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
562 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
563 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
564 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
565 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
566 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
567 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
568 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
569 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
570
571 if (hi2c->MspInitCallback == NULL)
572 {
573 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
574 }
575
576 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
577 hi2c->MspInitCallback(hi2c);
578 #else
579 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
580 HAL_I2C_MspInit(hi2c);
581 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
582 }
583
584 hi2c->State = HAL_I2C_STATE_BUSY;
585
586 /* Disable the selected I2C peripheral */
587 __HAL_I2C_DISABLE(hi2c);
588
589 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
590 /* Configure I2Cx: Frequency range */
591 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
592
593 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
594 /* Disable Own Address1 before set the Own Address1 configuration */
595 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
596
597 /* Configure I2Cx: Own Address1 and ack own address1 mode */
598 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
599 {
600 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
601 }
602 else /* I2C_ADDRESSINGMODE_10BIT */
603 {
604 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
605 }
606
607 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
608 /* Configure I2Cx: Addressing Master mode */
609 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
610 {
611 SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
612 }
613 else
614 {
615 /* Clear the I2C ADD10 bit */
616 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
617 }
618 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
619 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
620
621 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
622 /* Disable Own Address2 before set the Own Address2 configuration */
623 hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
624
625 /* Configure I2Cx: Dual mode and Own Address2 */
626 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
627 (hi2c->Init.OwnAddress2Masks << 8));
628
629 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
630 /* Configure I2Cx: Generalcall and NoStretch mode */
631 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
632
633 /* Enable the selected I2C peripheral */
634 __HAL_I2C_ENABLE(hi2c);
635
636 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
637 hi2c->State = HAL_I2C_STATE_READY;
638 hi2c->PreviousState = I2C_STATE_NONE;
639 hi2c->Mode = HAL_I2C_MODE_NONE;
640
641 return HAL_OK;
642 }
643
644 /**
645 * @brief DeInitialize the I2C peripheral.
646 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
647 * the configuration information for the specified I2C.
648 * @retval HAL status
649 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)650 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
651 {
652 /* Check the I2C handle allocation */
653 if (hi2c == NULL)
654 {
655 return HAL_ERROR;
656 }
657
658 /* Check the parameters */
659 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
660
661 hi2c->State = HAL_I2C_STATE_BUSY;
662
663 /* Disable the I2C Peripheral Clock */
664 __HAL_I2C_DISABLE(hi2c);
665
666 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
667 if (hi2c->MspDeInitCallback == NULL)
668 {
669 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
670 }
671
672 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
673 hi2c->MspDeInitCallback(hi2c);
674 #else
675 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
676 HAL_I2C_MspDeInit(hi2c);
677 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
678
679 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
680 hi2c->State = HAL_I2C_STATE_RESET;
681 hi2c->PreviousState = I2C_STATE_NONE;
682 hi2c->Mode = HAL_I2C_MODE_NONE;
683
684 /* Release Lock */
685 __HAL_UNLOCK(hi2c);
686
687 return HAL_OK;
688 }
689
690 /**
691 * @brief Initialize the I2C MSP.
692 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
693 * the configuration information for the specified I2C.
694 * @retval None
695 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)696 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
697 {
698 /* Prevent unused argument(s) compilation warning */
699 UNUSED(hi2c);
700
701 /* NOTE : This function should not be modified, when the callback is needed,
702 the HAL_I2C_MspInit could be implemented in the user file
703 */
704 }
705
706 /**
707 * @brief DeInitialize the I2C MSP.
708 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
709 * the configuration information for the specified I2C.
710 * @retval None
711 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)712 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
713 {
714 /* Prevent unused argument(s) compilation warning */
715 UNUSED(hi2c);
716
717 /* NOTE : This function should not be modified, when the callback is needed,
718 the HAL_I2C_MspDeInit could be implemented in the user file
719 */
720 }
721
722 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
723 /**
724 * @brief Register a User I2C Callback
725 * To be used instead of the weak predefined callback
726 * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
727 * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
728 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
729 * the configuration information for the specified I2C.
730 * @param CallbackID ID of the callback to be registered
731 * This parameter can be one of the following values:
732 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
733 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
734 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
735 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
736 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
737 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
738 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
739 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
740 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
741 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
742 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
743 * @param pCallback pointer to the Callback function
744 * @retval HAL status
745 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)746 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
747 pI2C_CallbackTypeDef pCallback)
748 {
749 HAL_StatusTypeDef status = HAL_OK;
750
751 if (pCallback == NULL)
752 {
753 /* Update the error code */
754 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
755
756 return HAL_ERROR;
757 }
758
759 if (HAL_I2C_STATE_READY == hi2c->State)
760 {
761 switch (CallbackID)
762 {
763 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
764 hi2c->MasterTxCpltCallback = pCallback;
765 break;
766
767 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
768 hi2c->MasterRxCpltCallback = pCallback;
769 break;
770
771 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
772 hi2c->SlaveTxCpltCallback = pCallback;
773 break;
774
775 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
776 hi2c->SlaveRxCpltCallback = pCallback;
777 break;
778
779 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
780 hi2c->ListenCpltCallback = pCallback;
781 break;
782
783 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
784 hi2c->MemTxCpltCallback = pCallback;
785 break;
786
787 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
788 hi2c->MemRxCpltCallback = pCallback;
789 break;
790
791 case HAL_I2C_ERROR_CB_ID :
792 hi2c->ErrorCallback = pCallback;
793 break;
794
795 case HAL_I2C_ABORT_CB_ID :
796 hi2c->AbortCpltCallback = pCallback;
797 break;
798
799 case HAL_I2C_MSPINIT_CB_ID :
800 hi2c->MspInitCallback = pCallback;
801 break;
802
803 case HAL_I2C_MSPDEINIT_CB_ID :
804 hi2c->MspDeInitCallback = pCallback;
805 break;
806
807 default :
808 /* Update the error code */
809 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
810
811 /* Return error status */
812 status = HAL_ERROR;
813 break;
814 }
815 }
816 else if (HAL_I2C_STATE_RESET == hi2c->State)
817 {
818 switch (CallbackID)
819 {
820 case HAL_I2C_MSPINIT_CB_ID :
821 hi2c->MspInitCallback = pCallback;
822 break;
823
824 case HAL_I2C_MSPDEINIT_CB_ID :
825 hi2c->MspDeInitCallback = pCallback;
826 break;
827
828 default :
829 /* Update the error code */
830 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
831
832 /* Return error status */
833 status = HAL_ERROR;
834 break;
835 }
836 }
837 else
838 {
839 /* Update the error code */
840 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
841
842 /* Return error status */
843 status = HAL_ERROR;
844 }
845
846 return status;
847 }
848
849 /**
850 * @brief Unregister an I2C Callback
851 * I2C callback is redirected to the weak predefined callback
852 * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
853 * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
854 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
855 * the configuration information for the specified I2C.
856 * @param CallbackID ID of the callback to be unregistered
857 * This parameter can be one of the following values:
858 * This parameter can be one of the following values:
859 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
860 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
861 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
862 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
863 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
864 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
865 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
866 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
867 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
868 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
869 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
870 * @retval HAL status
871 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)872 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
873 {
874 HAL_StatusTypeDef status = HAL_OK;
875
876 if (HAL_I2C_STATE_READY == hi2c->State)
877 {
878 switch (CallbackID)
879 {
880 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
881 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
882 break;
883
884 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
885 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
886 break;
887
888 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
889 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
890 break;
891
892 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
893 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
894 break;
895
896 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
897 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
898 break;
899
900 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
901 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
902 break;
903
904 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
905 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
906 break;
907
908 case HAL_I2C_ERROR_CB_ID :
909 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
910 break;
911
912 case HAL_I2C_ABORT_CB_ID :
913 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
914 break;
915
916 case HAL_I2C_MSPINIT_CB_ID :
917 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
918 break;
919
920 case HAL_I2C_MSPDEINIT_CB_ID :
921 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
922 break;
923
924 default :
925 /* Update the error code */
926 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
927
928 /* Return error status */
929 status = HAL_ERROR;
930 break;
931 }
932 }
933 else if (HAL_I2C_STATE_RESET == hi2c->State)
934 {
935 switch (CallbackID)
936 {
937 case HAL_I2C_MSPINIT_CB_ID :
938 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
939 break;
940
941 case HAL_I2C_MSPDEINIT_CB_ID :
942 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
943 break;
944
945 default :
946 /* Update the error code */
947 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
948
949 /* Return error status */
950 status = HAL_ERROR;
951 break;
952 }
953 }
954 else
955 {
956 /* Update the error code */
957 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
958
959 /* Return error status */
960 status = HAL_ERROR;
961 }
962
963 return status;
964 }
965
966 /**
967 * @brief Register the Slave Address Match I2C Callback
968 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
969 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
970 * the configuration information for the specified I2C.
971 * @param pCallback pointer to the Address Match Callback function
972 * @retval HAL status
973 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)974 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
975 {
976 HAL_StatusTypeDef status = HAL_OK;
977
978 if (pCallback == NULL)
979 {
980 /* Update the error code */
981 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
982
983 return HAL_ERROR;
984 }
985
986 if (HAL_I2C_STATE_READY == hi2c->State)
987 {
988 hi2c->AddrCallback = pCallback;
989 }
990 else
991 {
992 /* Update the error code */
993 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
994
995 /* Return error status */
996 status = HAL_ERROR;
997 }
998
999 return status;
1000 }
1001
1002 /**
1003 * @brief UnRegister the Slave Address Match I2C Callback
1004 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
1005 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1006 * the configuration information for the specified I2C.
1007 * @retval HAL status
1008 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)1009 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
1010 {
1011 HAL_StatusTypeDef status = HAL_OK;
1012
1013 if (HAL_I2C_STATE_READY == hi2c->State)
1014 {
1015 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
1016 }
1017 else
1018 {
1019 /* Update the error code */
1020 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1021
1022 /* Return error status */
1023 status = HAL_ERROR;
1024 }
1025
1026 return status;
1027 }
1028
1029 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
1030
1031 /**
1032 * @}
1033 */
1034
1035 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
1036 * @brief Data transfers functions
1037 *
1038 @verbatim
1039 ===============================================================================
1040 ##### IO operation functions #####
1041 ===============================================================================
1042 [..]
1043 This subsection provides a set of functions allowing to manage the I2C data
1044 transfers.
1045
1046 (#) There are two modes of transfer:
1047 (++) Blocking mode : The communication is performed in the polling mode.
1048 The status of all data processing is returned by the same function
1049 after finishing transfer.
1050 (++) No-Blocking mode : The communication is performed using Interrupts
1051 or DMA. These functions return the status of the transfer startup.
1052 The end of the data processing will be indicated through the
1053 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
1054 using DMA mode.
1055
1056 (#) Blocking mode functions are :
1057 (++) HAL_I2C_Master_Transmit()
1058 (++) HAL_I2C_Master_Receive()
1059 (++) HAL_I2C_Slave_Transmit()
1060 (++) HAL_I2C_Slave_Receive()
1061 (++) HAL_I2C_Mem_Write()
1062 (++) HAL_I2C_Mem_Read()
1063 (++) HAL_I2C_IsDeviceReady()
1064
1065 (#) No-Blocking mode functions with Interrupt are :
1066 (++) HAL_I2C_Master_Transmit_IT()
1067 (++) HAL_I2C_Master_Receive_IT()
1068 (++) HAL_I2C_Slave_Transmit_IT()
1069 (++) HAL_I2C_Slave_Receive_IT()
1070 (++) HAL_I2C_Mem_Write_IT()
1071 (++) HAL_I2C_Mem_Read_IT()
1072 (++) HAL_I2C_Master_Seq_Transmit_IT()
1073 (++) HAL_I2C_Master_Seq_Receive_IT()
1074 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1075 (++) HAL_I2C_Slave_Seq_Receive_IT()
1076 (++) HAL_I2C_EnableListen_IT()
1077 (++) HAL_I2C_DisableListen_IT()
1078 (++) HAL_I2C_Master_Abort_IT()
1079
1080 (#) No-Blocking mode functions with DMA are :
1081 (++) HAL_I2C_Master_Transmit_DMA()
1082 (++) HAL_I2C_Master_Receive_DMA()
1083 (++) HAL_I2C_Slave_Transmit_DMA()
1084 (++) HAL_I2C_Slave_Receive_DMA()
1085 (++) HAL_I2C_Mem_Write_DMA()
1086 (++) HAL_I2C_Mem_Read_DMA()
1087 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1088 (++) HAL_I2C_Master_Seq_Receive_DMA()
1089 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1090 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1091
1092 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1093 (++) HAL_I2C_MasterTxCpltCallback()
1094 (++) HAL_I2C_MasterRxCpltCallback()
1095 (++) HAL_I2C_SlaveTxCpltCallback()
1096 (++) HAL_I2C_SlaveRxCpltCallback()
1097 (++) HAL_I2C_MemTxCpltCallback()
1098 (++) HAL_I2C_MemRxCpltCallback()
1099 (++) HAL_I2C_AddrCallback()
1100 (++) HAL_I2C_ListenCpltCallback()
1101 (++) HAL_I2C_ErrorCallback()
1102 (++) HAL_I2C_AbortCpltCallback()
1103
1104 @endverbatim
1105 * @{
1106 */
1107
1108 /**
1109 * @brief Transmits in master mode an amount of data in blocking mode.
1110 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1111 * the configuration information for the specified I2C.
1112 * @param DevAddress Target device address: The device 7 bits address value
1113 * in datasheet must be shifted to the left before calling the interface
1114 * @param pData Pointer to data buffer
1115 * @param Size Amount of data to be sent
1116 * @param Timeout Timeout duration
1117 * @retval HAL status
1118 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1119 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1120 uint16_t Size, uint32_t Timeout)
1121 {
1122 uint32_t tickstart;
1123 uint32_t xfermode;
1124
1125 if (hi2c->State == HAL_I2C_STATE_READY)
1126 {
1127 /* Process Locked */
1128 __HAL_LOCK(hi2c);
1129
1130 /* Init tickstart for timeout management*/
1131 tickstart = HAL_GetTick();
1132
1133 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1134 {
1135 return HAL_ERROR;
1136 }
1137
1138 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1139 hi2c->Mode = HAL_I2C_MODE_MASTER;
1140 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1141
1142 /* Prepare transfer parameters */
1143 hi2c->pBuffPtr = pData;
1144 hi2c->XferCount = Size;
1145 hi2c->XferISR = NULL;
1146
1147 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1148 {
1149 hi2c->XferSize = MAX_NBYTE_SIZE;
1150 xfermode = I2C_RELOAD_MODE;
1151 }
1152 else
1153 {
1154 hi2c->XferSize = hi2c->XferCount;
1155 xfermode = I2C_AUTOEND_MODE;
1156 }
1157
1158 if (hi2c->XferSize > 0U)
1159 {
1160 /* Preload TX register */
1161 /* Write data to TXDR */
1162 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1163
1164 /* Increment Buffer pointer */
1165 hi2c->pBuffPtr++;
1166
1167 hi2c->XferCount--;
1168 hi2c->XferSize--;
1169
1170 /* Send Slave Address */
1171 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1172 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
1173 I2C_GENERATE_START_WRITE);
1174 }
1175 else
1176 {
1177 /* Send Slave Address */
1178 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1179 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
1180 I2C_GENERATE_START_WRITE);
1181 }
1182
1183 while (hi2c->XferCount > 0U)
1184 {
1185 /* Wait until TXIS flag is set */
1186 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1187 {
1188 return HAL_ERROR;
1189 }
1190 /* Write data to TXDR */
1191 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1192
1193 /* Increment Buffer pointer */
1194 hi2c->pBuffPtr++;
1195
1196 hi2c->XferCount--;
1197 hi2c->XferSize--;
1198
1199 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1200 {
1201 /* Wait until TCR flag is set */
1202 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1203 {
1204 return HAL_ERROR;
1205 }
1206
1207 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1208 {
1209 hi2c->XferSize = MAX_NBYTE_SIZE;
1210 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1211 I2C_NO_STARTSTOP);
1212 }
1213 else
1214 {
1215 hi2c->XferSize = hi2c->XferCount;
1216 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1217 I2C_NO_STARTSTOP);
1218 }
1219 }
1220 }
1221
1222 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1223 /* Wait until STOPF flag is set */
1224 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1225 {
1226 return HAL_ERROR;
1227 }
1228
1229 /* Clear STOP Flag */
1230 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1231
1232 /* Clear Configuration Register 2 */
1233 I2C_RESET_CR2(hi2c);
1234
1235 hi2c->State = HAL_I2C_STATE_READY;
1236 hi2c->Mode = HAL_I2C_MODE_NONE;
1237
1238 /* Process Unlocked */
1239 __HAL_UNLOCK(hi2c);
1240
1241 return HAL_OK;
1242 }
1243 else
1244 {
1245 return HAL_BUSY;
1246 }
1247 }
1248
1249 /**
1250 * @brief Receives in master mode an amount of data in blocking mode.
1251 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1252 * the configuration information for the specified I2C.
1253 * @param DevAddress Target device address: The device 7 bits address value
1254 * in datasheet must be shifted to the left before calling the interface
1255 * @param pData Pointer to data buffer
1256 * @param Size Amount of data to be sent
1257 * @param Timeout Timeout duration
1258 * @retval HAL status
1259 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1260 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1261 uint16_t Size, uint32_t Timeout)
1262 {
1263 uint32_t tickstart;
1264
1265 if (hi2c->State == HAL_I2C_STATE_READY)
1266 {
1267 /* Process Locked */
1268 __HAL_LOCK(hi2c);
1269
1270 /* Init tickstart for timeout management*/
1271 tickstart = HAL_GetTick();
1272
1273 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1274 {
1275 return HAL_ERROR;
1276 }
1277
1278 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1279 hi2c->Mode = HAL_I2C_MODE_MASTER;
1280 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1281
1282 /* Prepare transfer parameters */
1283 hi2c->pBuffPtr = pData;
1284 hi2c->XferCount = Size;
1285 hi2c->XferISR = NULL;
1286
1287 /* Send Slave Address */
1288 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1289 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1290 {
1291 hi2c->XferSize = MAX_NBYTE_SIZE;
1292 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1293 I2C_GENERATE_START_READ);
1294 }
1295 else
1296 {
1297 hi2c->XferSize = hi2c->XferCount;
1298 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1299 I2C_GENERATE_START_READ);
1300 }
1301
1302 while (hi2c->XferCount > 0U)
1303 {
1304 /* Wait until RXNE flag is set */
1305 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1306 {
1307 return HAL_ERROR;
1308 }
1309
1310 /* Read data from RXDR */
1311 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1312
1313 /* Increment Buffer pointer */
1314 hi2c->pBuffPtr++;
1315
1316 hi2c->XferSize--;
1317 hi2c->XferCount--;
1318
1319 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1320 {
1321 /* Wait until TCR flag is set */
1322 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1323 {
1324 return HAL_ERROR;
1325 }
1326
1327 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1328 {
1329 hi2c->XferSize = MAX_NBYTE_SIZE;
1330 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1331 I2C_NO_STARTSTOP);
1332 }
1333 else
1334 {
1335 hi2c->XferSize = hi2c->XferCount;
1336 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1337 I2C_NO_STARTSTOP);
1338 }
1339 }
1340 }
1341
1342 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1343 /* Wait until STOPF flag is set */
1344 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1345 {
1346 return HAL_ERROR;
1347 }
1348
1349 /* Clear STOP Flag */
1350 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1351
1352 /* Clear Configuration Register 2 */
1353 I2C_RESET_CR2(hi2c);
1354
1355 hi2c->State = HAL_I2C_STATE_READY;
1356 hi2c->Mode = HAL_I2C_MODE_NONE;
1357
1358 /* Process Unlocked */
1359 __HAL_UNLOCK(hi2c);
1360
1361 return HAL_OK;
1362 }
1363 else
1364 {
1365 return HAL_BUSY;
1366 }
1367 }
1368
1369 /**
1370 * @brief Transmits in slave mode an amount of data in blocking mode.
1371 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1372 * the configuration information for the specified I2C.
1373 * @param pData Pointer to data buffer
1374 * @param Size Amount of data to be sent
1375 * @param Timeout Timeout duration
1376 * @retval HAL status
1377 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1378 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1379 uint32_t Timeout)
1380 {
1381 uint32_t tickstart;
1382 uint16_t tmpXferCount;
1383 HAL_StatusTypeDef error;
1384
1385 if (hi2c->State == HAL_I2C_STATE_READY)
1386 {
1387 if ((pData == NULL) || (Size == 0U))
1388 {
1389 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1390 return HAL_ERROR;
1391 }
1392 /* Process Locked */
1393 __HAL_LOCK(hi2c);
1394
1395 /* Init tickstart for timeout management*/
1396 tickstart = HAL_GetTick();
1397
1398 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1399 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1400 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1401
1402 /* Prepare transfer parameters */
1403 hi2c->pBuffPtr = pData;
1404 hi2c->XferCount = Size;
1405 hi2c->XferISR = NULL;
1406
1407 /* Enable Address Acknowledge */
1408 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1409
1410 /* Preload TX data if no stretch enable */
1411 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1412 {
1413 /* Preload TX register */
1414 /* Write data to TXDR */
1415 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1416
1417 /* Increment Buffer pointer */
1418 hi2c->pBuffPtr++;
1419
1420 hi2c->XferCount--;
1421 }
1422
1423 /* Wait until ADDR flag is set */
1424 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1425 {
1426 /* Disable Address Acknowledge */
1427 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1428
1429 /* Flush TX register */
1430 I2C_Flush_TXDR(hi2c);
1431
1432 return HAL_ERROR;
1433 }
1434
1435 /* Clear ADDR flag */
1436 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1437
1438 /* If 10bit addressing mode is selected */
1439 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1440 {
1441 /* Wait until ADDR flag is set */
1442 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1443 {
1444 /* Disable Address Acknowledge */
1445 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1446
1447 /* Flush TX register */
1448 I2C_Flush_TXDR(hi2c);
1449
1450 return HAL_ERROR;
1451 }
1452
1453 /* Clear ADDR flag */
1454 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1455 }
1456
1457 /* Wait until DIR flag is set Transmitter mode */
1458 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
1459 {
1460 /* Disable Address Acknowledge */
1461 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1462
1463 /* Flush TX register */
1464 I2C_Flush_TXDR(hi2c);
1465
1466 return HAL_ERROR;
1467 }
1468
1469 while (hi2c->XferCount > 0U)
1470 {
1471 /* Wait until TXIS flag is set */
1472 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1473 {
1474 /* Disable Address Acknowledge */
1475 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1476 return HAL_ERROR;
1477 }
1478
1479 /* Write data to TXDR */
1480 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1481
1482 /* Increment Buffer pointer */
1483 hi2c->pBuffPtr++;
1484
1485 hi2c->XferCount--;
1486 }
1487
1488 /* Wait until AF flag is set */
1489 error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
1490
1491 if (error != HAL_OK)
1492 {
1493 /* Check that I2C transfer finished */
1494 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
1495 /* Mean XferCount == 0 */
1496
1497 tmpXferCount = hi2c->XferCount;
1498 if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
1499 {
1500 /* Reset ErrorCode to NONE */
1501 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1502 }
1503 else
1504 {
1505 /* Disable Address Acknowledge */
1506 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1507 return HAL_ERROR;
1508 }
1509 }
1510 else
1511 {
1512 /* Flush TX register */
1513 I2C_Flush_TXDR(hi2c);
1514
1515 /* Clear AF flag */
1516 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1517
1518 /* Wait until STOP flag is set */
1519 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1520 {
1521 /* Disable Address Acknowledge */
1522 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1523
1524 return HAL_ERROR;
1525 }
1526
1527 /* Clear STOP flag */
1528 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1529 }
1530
1531 /* Wait until BUSY flag is reset */
1532 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1533 {
1534 /* Disable Address Acknowledge */
1535 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1536 return HAL_ERROR;
1537 }
1538
1539 /* Disable Address Acknowledge */
1540 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1541
1542 hi2c->State = HAL_I2C_STATE_READY;
1543 hi2c->Mode = HAL_I2C_MODE_NONE;
1544
1545 /* Process Unlocked */
1546 __HAL_UNLOCK(hi2c);
1547
1548 return HAL_OK;
1549 }
1550 else
1551 {
1552 return HAL_BUSY;
1553 }
1554 }
1555
1556 /**
1557 * @brief Receive in slave mode an amount of data in blocking mode
1558 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1559 * the configuration information for the specified I2C.
1560 * @param pData Pointer to data buffer
1561 * @param Size Amount of data to be sent
1562 * @param Timeout Timeout duration
1563 * @retval HAL status
1564 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1565 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1566 uint32_t Timeout)
1567 {
1568 uint32_t tickstart;
1569
1570 if (hi2c->State == HAL_I2C_STATE_READY)
1571 {
1572 if ((pData == NULL) || (Size == 0U))
1573 {
1574 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1575 return HAL_ERROR;
1576 }
1577 /* Process Locked */
1578 __HAL_LOCK(hi2c);
1579
1580 /* Init tickstart for timeout management*/
1581 tickstart = HAL_GetTick();
1582
1583 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1584 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1585 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1586
1587 /* Prepare transfer parameters */
1588 hi2c->pBuffPtr = pData;
1589 hi2c->XferCount = Size;
1590 hi2c->XferSize = hi2c->XferCount;
1591 hi2c->XferISR = NULL;
1592
1593 /* Enable Address Acknowledge */
1594 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1595
1596 /* Wait until ADDR flag is set */
1597 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1598 {
1599 /* Disable Address Acknowledge */
1600 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1601 return HAL_ERROR;
1602 }
1603
1604 /* Clear ADDR flag */
1605 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1606
1607 /* Wait until DIR flag is reset Receiver mode */
1608 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1609 {
1610 /* Disable Address Acknowledge */
1611 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1612 return HAL_ERROR;
1613 }
1614
1615 while (hi2c->XferCount > 0U)
1616 {
1617 /* Wait until RXNE flag is set */
1618 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1619 {
1620 /* Disable Address Acknowledge */
1621 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1622
1623 /* Store Last receive data if any */
1624 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1625 {
1626 /* Read data from RXDR */
1627 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1628
1629 /* Increment Buffer pointer */
1630 hi2c->pBuffPtr++;
1631
1632 hi2c->XferCount--;
1633 hi2c->XferSize--;
1634 }
1635
1636 return HAL_ERROR;
1637 }
1638
1639 /* Read data from RXDR */
1640 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1641
1642 /* Increment Buffer pointer */
1643 hi2c->pBuffPtr++;
1644
1645 hi2c->XferCount--;
1646 hi2c->XferSize--;
1647 }
1648
1649 /* Wait until STOP flag is set */
1650 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1651 {
1652 /* Disable Address Acknowledge */
1653 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1654 return HAL_ERROR;
1655 }
1656
1657 /* Clear STOP flag */
1658 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1659
1660 /* Wait until BUSY flag is reset */
1661 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1662 {
1663 /* Disable Address Acknowledge */
1664 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1665 return HAL_ERROR;
1666 }
1667
1668 /* Disable Address Acknowledge */
1669 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1670
1671 hi2c->State = HAL_I2C_STATE_READY;
1672 hi2c->Mode = HAL_I2C_MODE_NONE;
1673
1674 /* Process Unlocked */
1675 __HAL_UNLOCK(hi2c);
1676
1677 return HAL_OK;
1678 }
1679 else
1680 {
1681 return HAL_BUSY;
1682 }
1683 }
1684
1685 /**
1686 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1687 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1688 * the configuration information for the specified I2C.
1689 * @param DevAddress Target device address: The device 7 bits address value
1690 * in datasheet must be shifted to the left before calling the interface
1691 * @param pData Pointer to data buffer
1692 * @param Size Amount of data to be sent
1693 * @retval HAL status
1694 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1695 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1696 uint16_t Size)
1697 {
1698 uint32_t xfermode;
1699
1700 if (hi2c->State == HAL_I2C_STATE_READY)
1701 {
1702 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1703 {
1704 return HAL_BUSY;
1705 }
1706
1707 /* Process Locked */
1708 __HAL_LOCK(hi2c);
1709
1710 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1711 hi2c->Mode = HAL_I2C_MODE_MASTER;
1712 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1713
1714 /* Prepare transfer parameters */
1715 hi2c->pBuffPtr = pData;
1716 hi2c->XferCount = Size;
1717 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1718 hi2c->XferISR = I2C_Master_ISR_IT;
1719
1720 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1721 {
1722 hi2c->XferSize = MAX_NBYTE_SIZE;
1723 xfermode = I2C_RELOAD_MODE;
1724 }
1725 else
1726 {
1727 hi2c->XferSize = hi2c->XferCount;
1728 xfermode = I2C_AUTOEND_MODE;
1729 }
1730
1731 /* Send Slave Address */
1732 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1733 if (hi2c->XferSize > 0U)
1734 {
1735 /* Preload TX register */
1736 /* Write data to TXDR */
1737 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1738
1739 /* Increment Buffer pointer */
1740 hi2c->pBuffPtr++;
1741
1742 hi2c->XferCount--;
1743 hi2c->XferSize--;
1744
1745 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
1746 I2C_GENERATE_START_WRITE);
1747 }
1748 else
1749 {
1750 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
1751 I2C_GENERATE_START_WRITE);
1752 }
1753
1754 /* Process Unlocked */
1755 __HAL_UNLOCK(hi2c);
1756
1757 /* Note : The I2C interrupts must be enabled after unlocking current process
1758 to avoid the risk of I2C interrupt handle execution before current
1759 process unlock */
1760
1761 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1762 /* possible to enable all of these */
1763 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1764 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1765 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1766
1767 return HAL_OK;
1768 }
1769 else
1770 {
1771 return HAL_BUSY;
1772 }
1773 }
1774
1775 /**
1776 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1777 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1778 * the configuration information for the specified I2C.
1779 * @param DevAddress Target device address: The device 7 bits address value
1780 * in datasheet must be shifted to the left before calling the interface
1781 * @param pData Pointer to data buffer
1782 * @param Size Amount of data to be sent
1783 * @retval HAL status
1784 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1785 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1786 uint16_t Size)
1787 {
1788 uint32_t xfermode;
1789
1790 if (hi2c->State == HAL_I2C_STATE_READY)
1791 {
1792 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1793 {
1794 return HAL_BUSY;
1795 }
1796
1797 /* Process Locked */
1798 __HAL_LOCK(hi2c);
1799
1800 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1801 hi2c->Mode = HAL_I2C_MODE_MASTER;
1802 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1803
1804 /* Prepare transfer parameters */
1805 hi2c->pBuffPtr = pData;
1806 hi2c->XferCount = Size;
1807 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1808 hi2c->XferISR = I2C_Master_ISR_IT;
1809
1810 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1811 {
1812 hi2c->XferSize = MAX_NBYTE_SIZE;
1813 xfermode = I2C_RELOAD_MODE;
1814 }
1815 else
1816 {
1817 hi2c->XferSize = hi2c->XferCount;
1818 xfermode = I2C_AUTOEND_MODE;
1819 }
1820
1821 /* Send Slave Address */
1822 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1823 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1824
1825 /* Process Unlocked */
1826 __HAL_UNLOCK(hi2c);
1827
1828 /* Note : The I2C interrupts must be enabled after unlocking current process
1829 to avoid the risk of I2C interrupt handle execution before current
1830 process unlock */
1831
1832 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1833 /* possible to enable all of these */
1834 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1835 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1836 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1837
1838 return HAL_OK;
1839 }
1840 else
1841 {
1842 return HAL_BUSY;
1843 }
1844 }
1845
1846 /**
1847 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1848 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1849 * the configuration information for the specified I2C.
1850 * @param pData Pointer to data buffer
1851 * @param Size Amount of data to be sent
1852 * @retval HAL status
1853 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1854 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1855 {
1856 if (hi2c->State == HAL_I2C_STATE_READY)
1857 {
1858 /* Process Locked */
1859 __HAL_LOCK(hi2c);
1860
1861 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1862 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1863 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1864
1865 /* Enable Address Acknowledge */
1866 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1867
1868 /* Prepare transfer parameters */
1869 hi2c->pBuffPtr = pData;
1870 hi2c->XferCount = Size;
1871 hi2c->XferSize = hi2c->XferCount;
1872 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1873 hi2c->XferISR = I2C_Slave_ISR_IT;
1874
1875 /* Preload TX data if no stretch enable */
1876 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1877 {
1878 /* Preload TX register */
1879 /* Write data to TXDR */
1880 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1881
1882 /* Increment Buffer pointer */
1883 hi2c->pBuffPtr++;
1884
1885 hi2c->XferCount--;
1886 hi2c->XferSize--;
1887 }
1888
1889 /* Process Unlocked */
1890 __HAL_UNLOCK(hi2c);
1891
1892 /* Note : The I2C interrupts must be enabled after unlocking current process
1893 to avoid the risk of I2C interrupt handle execution before current
1894 process unlock */
1895
1896 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1897 /* possible to enable all of these */
1898 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1899 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1900 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1901
1902 return HAL_OK;
1903 }
1904 else
1905 {
1906 return HAL_BUSY;
1907 }
1908 }
1909
1910 /**
1911 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1912 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1913 * the configuration information for the specified I2C.
1914 * @param pData Pointer to data buffer
1915 * @param Size Amount of data to be sent
1916 * @retval HAL status
1917 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1918 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1919 {
1920 if (hi2c->State == HAL_I2C_STATE_READY)
1921 {
1922 /* Process Locked */
1923 __HAL_LOCK(hi2c);
1924
1925 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1926 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1927 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1928
1929 /* Enable Address Acknowledge */
1930 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1931
1932 /* Prepare transfer parameters */
1933 hi2c->pBuffPtr = pData;
1934 hi2c->XferCount = Size;
1935 hi2c->XferSize = hi2c->XferCount;
1936 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1937 hi2c->XferISR = I2C_Slave_ISR_IT;
1938
1939 /* Process Unlocked */
1940 __HAL_UNLOCK(hi2c);
1941
1942 /* Note : The I2C interrupts must be enabled after unlocking current process
1943 to avoid the risk of I2C interrupt handle execution before current
1944 process unlock */
1945
1946 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1947 /* possible to enable all of these */
1948 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1949 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1950 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1951
1952 return HAL_OK;
1953 }
1954 else
1955 {
1956 return HAL_BUSY;
1957 }
1958 }
1959
1960 /**
1961 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1962 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1963 * the configuration information for the specified I2C.
1964 * @param DevAddress Target device address: The device 7 bits address value
1965 * in datasheet must be shifted to the left before calling the interface
1966 * @param pData Pointer to data buffer
1967 * @param Size Amount of data to be sent
1968 * @retval HAL status
1969 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1970 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1971 uint16_t Size)
1972 {
1973 uint32_t xfermode;
1974 HAL_StatusTypeDef dmaxferstatus;
1975 uint32_t sizetoxfer = 0U;
1976
1977 if (hi2c->State == HAL_I2C_STATE_READY)
1978 {
1979 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1980 {
1981 return HAL_BUSY;
1982 }
1983
1984 /* Process Locked */
1985 __HAL_LOCK(hi2c);
1986
1987 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1988 hi2c->Mode = HAL_I2C_MODE_MASTER;
1989 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1990
1991 /* Prepare transfer parameters */
1992 hi2c->pBuffPtr = pData;
1993 hi2c->XferCount = Size;
1994 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1995 hi2c->XferISR = I2C_Master_ISR_DMA;
1996
1997 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1998 {
1999 hi2c->XferSize = MAX_NBYTE_SIZE;
2000 xfermode = I2C_RELOAD_MODE;
2001 }
2002 else
2003 {
2004 hi2c->XferSize = hi2c->XferCount;
2005 xfermode = I2C_AUTOEND_MODE;
2006 }
2007
2008 if (hi2c->XferSize > 0U)
2009 {
2010 /* Preload TX register */
2011 /* Write data to TXDR */
2012 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2013
2014 /* Increment Buffer pointer */
2015 hi2c->pBuffPtr++;
2016
2017 sizetoxfer = hi2c->XferSize;
2018 hi2c->XferCount--;
2019 hi2c->XferSize--;
2020 }
2021
2022 if (hi2c->XferSize > 0U)
2023 {
2024 if (hi2c->hdmatx != NULL)
2025 {
2026 /* Set the I2C DMA transfer complete callback */
2027 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
2028
2029 /* Set the DMA error callback */
2030 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2031
2032 /* Set the unused DMA callbacks to NULL */
2033 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2034 hi2c->hdmatx->XferAbortCallback = NULL;
2035
2036 /* Enable the DMA stream or channel depends on Instance */
2037 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
2038 (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
2039 }
2040 else
2041 {
2042 /* Update I2C state */
2043 hi2c->State = HAL_I2C_STATE_READY;
2044 hi2c->Mode = HAL_I2C_MODE_NONE;
2045
2046 /* Update I2C error code */
2047 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2048
2049 /* Process Unlocked */
2050 __HAL_UNLOCK(hi2c);
2051
2052 return HAL_ERROR;
2053 }
2054
2055 if (dmaxferstatus == HAL_OK)
2056 {
2057 /* Send Slave Address */
2058 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2059 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U),
2060 xfermode, I2C_GENERATE_START_WRITE);
2061
2062 /* Update XferCount value */
2063 hi2c->XferCount -= hi2c->XferSize;
2064
2065 /* Process Unlocked */
2066 __HAL_UNLOCK(hi2c);
2067
2068 /* Note : The I2C interrupts must be enabled after unlocking current process
2069 to avoid the risk of I2C interrupt handle execution before current
2070 process unlock */
2071 /* Enable ERR and NACK interrupts */
2072 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2073
2074 /* Enable DMA Request */
2075 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2076 }
2077 else
2078 {
2079 /* Update I2C state */
2080 hi2c->State = HAL_I2C_STATE_READY;
2081 hi2c->Mode = HAL_I2C_MODE_NONE;
2082
2083 /* Update I2C error code */
2084 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2085
2086 /* Process Unlocked */
2087 __HAL_UNLOCK(hi2c);
2088
2089 return HAL_ERROR;
2090 }
2091 }
2092 else
2093 {
2094 /* Update Transfer ISR function pointer */
2095 hi2c->XferISR = I2C_Master_ISR_IT;
2096
2097 /* Send Slave Address */
2098 /* Set NBYTES to write and generate START condition */
2099 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE,
2100 I2C_GENERATE_START_WRITE);
2101
2102 /* Process Unlocked */
2103 __HAL_UNLOCK(hi2c);
2104
2105 /* Note : The I2C interrupts must be enabled after unlocking current process
2106 to avoid the risk of I2C interrupt handle execution before current
2107 process unlock */
2108 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2109 /* possible to enable all of these */
2110 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2111 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2112 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2113 }
2114
2115 return HAL_OK;
2116 }
2117 else
2118 {
2119 return HAL_BUSY;
2120 }
2121 }
2122
2123 /**
2124 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2125 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2126 * the configuration information for the specified I2C.
2127 * @param DevAddress Target device address: The device 7 bits address value
2128 * in datasheet must be shifted to the left before calling the interface
2129 * @param pData Pointer to data buffer
2130 * @param Size Amount of data to be sent
2131 * @retval HAL status
2132 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2133 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
2134 uint16_t Size)
2135 {
2136 uint32_t xfermode;
2137 HAL_StatusTypeDef dmaxferstatus;
2138
2139 if (hi2c->State == HAL_I2C_STATE_READY)
2140 {
2141 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2142 {
2143 return HAL_BUSY;
2144 }
2145
2146 /* Process Locked */
2147 __HAL_LOCK(hi2c);
2148
2149 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2150 hi2c->Mode = HAL_I2C_MODE_MASTER;
2151 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2152
2153 /* Prepare transfer parameters */
2154 hi2c->pBuffPtr = pData;
2155 hi2c->XferCount = Size;
2156 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2157 hi2c->XferISR = I2C_Master_ISR_DMA;
2158
2159 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2160 {
2161 hi2c->XferSize = MAX_NBYTE_SIZE;
2162 xfermode = I2C_RELOAD_MODE;
2163 }
2164 else
2165 {
2166 hi2c->XferSize = hi2c->XferCount;
2167 xfermode = I2C_AUTOEND_MODE;
2168 }
2169
2170 if (hi2c->XferSize > 0U)
2171 {
2172 if (hi2c->hdmarx != NULL)
2173 {
2174 /* Set the I2C DMA transfer complete callback */
2175 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2176
2177 /* Set the DMA error callback */
2178 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2179
2180 /* Set the unused DMA callbacks to NULL */
2181 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2182 hi2c->hdmarx->XferAbortCallback = NULL;
2183
2184 /* Enable the DMA stream or channel depends on Instance */
2185 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2186 hi2c->XferSize);
2187 }
2188 else
2189 {
2190 /* Update I2C state */
2191 hi2c->State = HAL_I2C_STATE_READY;
2192 hi2c->Mode = HAL_I2C_MODE_NONE;
2193
2194 /* Update I2C error code */
2195 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2196
2197 /* Process Unlocked */
2198 __HAL_UNLOCK(hi2c);
2199
2200 return HAL_ERROR;
2201 }
2202
2203 if (dmaxferstatus == HAL_OK)
2204 {
2205 /* Send Slave Address */
2206 /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2207 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2208
2209 /* Update XferCount value */
2210 hi2c->XferCount -= hi2c->XferSize;
2211
2212 /* Process Unlocked */
2213 __HAL_UNLOCK(hi2c);
2214
2215 /* Note : The I2C interrupts must be enabled after unlocking current process
2216 to avoid the risk of I2C interrupt handle execution before current
2217 process unlock */
2218 /* Enable ERR and NACK interrupts */
2219 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2220
2221 /* Enable DMA Request */
2222 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2223 }
2224 else
2225 {
2226 /* Update I2C state */
2227 hi2c->State = HAL_I2C_STATE_READY;
2228 hi2c->Mode = HAL_I2C_MODE_NONE;
2229
2230 /* Update I2C error code */
2231 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2232
2233 /* Process Unlocked */
2234 __HAL_UNLOCK(hi2c);
2235
2236 return HAL_ERROR;
2237 }
2238 }
2239 else
2240 {
2241 /* Update Transfer ISR function pointer */
2242 hi2c->XferISR = I2C_Master_ISR_IT;
2243
2244 /* Send Slave Address */
2245 /* Set NBYTES to read and generate START condition */
2246 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2247 I2C_GENERATE_START_READ);
2248
2249 /* Process Unlocked */
2250 __HAL_UNLOCK(hi2c);
2251
2252 /* Note : The I2C interrupts must be enabled after unlocking current process
2253 to avoid the risk of I2C interrupt handle execution before current
2254 process unlock */
2255 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2256 /* possible to enable all of these */
2257 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2258 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2259 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
2260 }
2261
2262 return HAL_OK;
2263 }
2264 else
2265 {
2266 return HAL_BUSY;
2267 }
2268 }
2269
2270 /**
2271 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2272 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2273 * the configuration information for the specified I2C.
2274 * @param pData Pointer to data buffer
2275 * @param Size Amount of data to be sent
2276 * @retval HAL status
2277 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2278 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2279 {
2280 HAL_StatusTypeDef dmaxferstatus;
2281
2282 if (hi2c->State == HAL_I2C_STATE_READY)
2283 {
2284 if ((pData == NULL) || (Size == 0U))
2285 {
2286 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2287 return HAL_ERROR;
2288 }
2289 /* Process Locked */
2290 __HAL_LOCK(hi2c);
2291
2292 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2293 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2294 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2295
2296 /* Prepare transfer parameters */
2297 hi2c->pBuffPtr = pData;
2298 hi2c->XferCount = Size;
2299 hi2c->XferSize = hi2c->XferCount;
2300 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2301 hi2c->XferISR = I2C_Slave_ISR_DMA;
2302
2303 /* Preload TX data if no stretch enable */
2304 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
2305 {
2306 /* Preload TX register */
2307 /* Write data to TXDR */
2308 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2309
2310 /* Increment Buffer pointer */
2311 hi2c->pBuffPtr++;
2312
2313 hi2c->XferCount--;
2314 hi2c->XferSize--;
2315 }
2316
2317 if (hi2c->XferCount != 0U)
2318 {
2319 if (hi2c->hdmatx != NULL)
2320 {
2321 /* Set the I2C DMA transfer complete callback */
2322 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
2323
2324 /* Set the DMA error callback */
2325 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2326
2327 /* Set the unused DMA callbacks to NULL */
2328 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2329 hi2c->hdmatx->XferAbortCallback = NULL;
2330
2331 /* Enable the DMA stream or channel depends on Instance */
2332 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
2333 (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
2334 hi2c->XferSize);
2335 }
2336 else
2337 {
2338 /* Update I2C state */
2339 hi2c->State = HAL_I2C_STATE_LISTEN;
2340 hi2c->Mode = HAL_I2C_MODE_NONE;
2341
2342 /* Update I2C error code */
2343 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2344
2345 /* Process Unlocked */
2346 __HAL_UNLOCK(hi2c);
2347
2348 return HAL_ERROR;
2349 }
2350
2351 if (dmaxferstatus == HAL_OK)
2352 {
2353 /* Enable Address Acknowledge */
2354 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2355
2356 /* Process Unlocked */
2357 __HAL_UNLOCK(hi2c);
2358
2359 /* Note : The I2C interrupts must be enabled after unlocking current process
2360 to avoid the risk of I2C interrupt handle execution before current
2361 process unlock */
2362 /* Enable ERR, STOP, NACK, ADDR interrupts */
2363 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2364
2365 /* Enable DMA Request */
2366 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2367 }
2368 else
2369 {
2370 /* Update I2C state */
2371 hi2c->State = HAL_I2C_STATE_LISTEN;
2372 hi2c->Mode = HAL_I2C_MODE_NONE;
2373
2374 /* Update I2C error code */
2375 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2376
2377 /* Process Unlocked */
2378 __HAL_UNLOCK(hi2c);
2379
2380 return HAL_ERROR;
2381 }
2382 }
2383 else
2384 {
2385 /* Enable Address Acknowledge */
2386 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2387
2388 /* Process Unlocked */
2389 __HAL_UNLOCK(hi2c);
2390
2391 /* Note : The I2C interrupts must be enabled after unlocking current process
2392 to avoid the risk of I2C interrupt handle execution before current
2393 process unlock */
2394 /* Enable ERR, STOP, NACK, ADDR interrupts */
2395 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2396 }
2397
2398 return HAL_OK;
2399 }
2400 else
2401 {
2402 return HAL_BUSY;
2403 }
2404 }
2405
2406 /**
2407 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2408 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2409 * the configuration information for the specified I2C.
2410 * @param pData Pointer to data buffer
2411 * @param Size Amount of data to be sent
2412 * @retval HAL status
2413 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2414 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2415 {
2416 HAL_StatusTypeDef dmaxferstatus;
2417
2418 if (hi2c->State == HAL_I2C_STATE_READY)
2419 {
2420 if ((pData == NULL) || (Size == 0U))
2421 {
2422 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2423 return HAL_ERROR;
2424 }
2425 /* Process Locked */
2426 __HAL_LOCK(hi2c);
2427
2428 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2429 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2430 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2431
2432 /* Prepare transfer parameters */
2433 hi2c->pBuffPtr = pData;
2434 hi2c->XferCount = Size;
2435 hi2c->XferSize = hi2c->XferCount;
2436 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2437 hi2c->XferISR = I2C_Slave_ISR_DMA;
2438
2439 if (hi2c->hdmarx != NULL)
2440 {
2441 /* Set the I2C DMA transfer complete callback */
2442 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
2443
2444 /* Set the DMA error callback */
2445 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2446
2447 /* Set the unused DMA callbacks to NULL */
2448 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2449 hi2c->hdmarx->XferAbortCallback = NULL;
2450
2451 /* Enable the DMA stream or channel depends on Instance */
2452 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2453 hi2c->XferSize);
2454 }
2455 else
2456 {
2457 /* Update I2C state */
2458 hi2c->State = HAL_I2C_STATE_LISTEN;
2459 hi2c->Mode = HAL_I2C_MODE_NONE;
2460
2461 /* Update I2C error code */
2462 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2463
2464 /* Process Unlocked */
2465 __HAL_UNLOCK(hi2c);
2466
2467 return HAL_ERROR;
2468 }
2469
2470 if (dmaxferstatus == HAL_OK)
2471 {
2472 /* Enable Address Acknowledge */
2473 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2474
2475 /* Process Unlocked */
2476 __HAL_UNLOCK(hi2c);
2477
2478 /* Note : The I2C interrupts must be enabled after unlocking current process
2479 to avoid the risk of I2C interrupt handle execution before current
2480 process unlock */
2481 /* Enable ERR, STOP, NACK, ADDR interrupts */
2482 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2483
2484 /* Enable DMA Request */
2485 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2486 }
2487 else
2488 {
2489 /* Update I2C state */
2490 hi2c->State = HAL_I2C_STATE_LISTEN;
2491 hi2c->Mode = HAL_I2C_MODE_NONE;
2492
2493 /* Update I2C error code */
2494 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2495
2496 /* Process Unlocked */
2497 __HAL_UNLOCK(hi2c);
2498
2499 return HAL_ERROR;
2500 }
2501
2502 return HAL_OK;
2503 }
2504 else
2505 {
2506 return HAL_BUSY;
2507 }
2508 }
2509
2510 /**
2511 * @brief Write an amount of data in blocking mode to a specific memory address
2512 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2513 * the configuration information for the specified I2C.
2514 * @param DevAddress Target device address: The device 7 bits address value
2515 * in datasheet must be shifted to the left before calling the interface
2516 * @param MemAddress Internal memory address
2517 * @param MemAddSize Size of internal memory address
2518 * @param pData Pointer to data buffer
2519 * @param Size Amount of data to be sent
2520 * @param Timeout Timeout duration
2521 * @retval HAL status
2522 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2523 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2524 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2525 {
2526 uint32_t tickstart;
2527
2528 /* Check the parameters */
2529 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2530
2531 if (hi2c->State == HAL_I2C_STATE_READY)
2532 {
2533 if ((pData == NULL) || (Size == 0U))
2534 {
2535 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2536 return HAL_ERROR;
2537 }
2538
2539 /* Process Locked */
2540 __HAL_LOCK(hi2c);
2541
2542 /* Init tickstart for timeout management*/
2543 tickstart = HAL_GetTick();
2544
2545 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2546 {
2547 return HAL_ERROR;
2548 }
2549
2550 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2551 hi2c->Mode = HAL_I2C_MODE_MEM;
2552 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2553
2554 /* Prepare transfer parameters */
2555 hi2c->pBuffPtr = pData;
2556 hi2c->XferCount = Size;
2557 hi2c->XferISR = NULL;
2558
2559 /* Send Slave Address and Memory Address */
2560 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2561 {
2562 /* Process Unlocked */
2563 __HAL_UNLOCK(hi2c);
2564 return HAL_ERROR;
2565 }
2566
2567 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
2568 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2569 {
2570 hi2c->XferSize = MAX_NBYTE_SIZE;
2571 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2572 }
2573 else
2574 {
2575 hi2c->XferSize = hi2c->XferCount;
2576 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2577 }
2578
2579 do
2580 {
2581 /* Wait until TXIS flag is set */
2582 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2583 {
2584 return HAL_ERROR;
2585 }
2586
2587 /* Write data to TXDR */
2588 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2589
2590 /* Increment Buffer pointer */
2591 hi2c->pBuffPtr++;
2592
2593 hi2c->XferCount--;
2594 hi2c->XferSize--;
2595
2596 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2597 {
2598 /* Wait until TCR flag is set */
2599 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2600 {
2601 return HAL_ERROR;
2602 }
2603
2604 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2605 {
2606 hi2c->XferSize = MAX_NBYTE_SIZE;
2607 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2608 I2C_NO_STARTSTOP);
2609 }
2610 else
2611 {
2612 hi2c->XferSize = hi2c->XferCount;
2613 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2614 I2C_NO_STARTSTOP);
2615 }
2616 }
2617
2618 } while (hi2c->XferCount > 0U);
2619
2620 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2621 /* Wait until STOPF flag is reset */
2622 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2623 {
2624 return HAL_ERROR;
2625 }
2626
2627 /* Clear STOP Flag */
2628 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2629
2630 /* Clear Configuration Register 2 */
2631 I2C_RESET_CR2(hi2c);
2632
2633 hi2c->State = HAL_I2C_STATE_READY;
2634 hi2c->Mode = HAL_I2C_MODE_NONE;
2635
2636 /* Process Unlocked */
2637 __HAL_UNLOCK(hi2c);
2638
2639 return HAL_OK;
2640 }
2641 else
2642 {
2643 return HAL_BUSY;
2644 }
2645 }
2646
2647 /**
2648 * @brief Read an amount of data in blocking mode from a specific memory address
2649 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2650 * the configuration information for the specified I2C.
2651 * @param DevAddress Target device address: The device 7 bits address value
2652 * in datasheet must be shifted to the left before calling the interface
2653 * @param MemAddress Internal memory address
2654 * @param MemAddSize Size of internal memory address
2655 * @param pData Pointer to data buffer
2656 * @param Size Amount of data to be sent
2657 * @param Timeout Timeout duration
2658 * @retval HAL status
2659 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2660 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2661 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2662 {
2663 uint32_t tickstart;
2664
2665 /* Check the parameters */
2666 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2667
2668 if (hi2c->State == HAL_I2C_STATE_READY)
2669 {
2670 if ((pData == NULL) || (Size == 0U))
2671 {
2672 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2673 return HAL_ERROR;
2674 }
2675
2676 /* Process Locked */
2677 __HAL_LOCK(hi2c);
2678
2679 /* Init tickstart for timeout management*/
2680 tickstart = HAL_GetTick();
2681
2682 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2683 {
2684 return HAL_ERROR;
2685 }
2686
2687 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2688 hi2c->Mode = HAL_I2C_MODE_MEM;
2689 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2690
2691 /* Prepare transfer parameters */
2692 hi2c->pBuffPtr = pData;
2693 hi2c->XferCount = Size;
2694 hi2c->XferISR = NULL;
2695
2696 /* Send Slave Address and Memory Address */
2697 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2698 {
2699 /* Process Unlocked */
2700 __HAL_UNLOCK(hi2c);
2701 return HAL_ERROR;
2702 }
2703
2704 /* Send Slave Address */
2705 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2706 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2707 {
2708 hi2c->XferSize = MAX_NBYTE_SIZE;
2709 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2710 I2C_GENERATE_START_READ);
2711 }
2712 else
2713 {
2714 hi2c->XferSize = hi2c->XferCount;
2715 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2716 I2C_GENERATE_START_READ);
2717 }
2718
2719 do
2720 {
2721 /* Wait until RXNE flag is set */
2722 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
2723 {
2724 return HAL_ERROR;
2725 }
2726
2727 /* Read data from RXDR */
2728 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
2729
2730 /* Increment Buffer pointer */
2731 hi2c->pBuffPtr++;
2732
2733 hi2c->XferSize--;
2734 hi2c->XferCount--;
2735
2736 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2737 {
2738 /* Wait until TCR flag is set */
2739 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2740 {
2741 return HAL_ERROR;
2742 }
2743
2744 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2745 {
2746 hi2c->XferSize = MAX_NBYTE_SIZE;
2747 I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
2748 I2C_NO_STARTSTOP);
2749 }
2750 else
2751 {
2752 hi2c->XferSize = hi2c->XferCount;
2753 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2754 I2C_NO_STARTSTOP);
2755 }
2756 }
2757 } while (hi2c->XferCount > 0U);
2758
2759 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2760 /* Wait until STOPF flag is reset */
2761 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2762 {
2763 return HAL_ERROR;
2764 }
2765
2766 /* Clear STOP Flag */
2767 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2768
2769 /* Clear Configuration Register 2 */
2770 I2C_RESET_CR2(hi2c);
2771
2772 hi2c->State = HAL_I2C_STATE_READY;
2773 hi2c->Mode = HAL_I2C_MODE_NONE;
2774
2775 /* Process Unlocked */
2776 __HAL_UNLOCK(hi2c);
2777
2778 return HAL_OK;
2779 }
2780 else
2781 {
2782 return HAL_BUSY;
2783 }
2784 }
2785 /**
2786 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2787 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2788 * the configuration information for the specified I2C.
2789 * @param DevAddress Target device address: The device 7 bits address value
2790 * in datasheet must be shifted to the left before calling the interface
2791 * @param MemAddress Internal memory address
2792 * @param MemAddSize Size of internal memory address
2793 * @param pData Pointer to data buffer
2794 * @param Size Amount of data to be sent
2795 * @retval HAL status
2796 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2797 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2798 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2799 {
2800 /* Check the parameters */
2801 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2802
2803 if (hi2c->State == HAL_I2C_STATE_READY)
2804 {
2805 if ((pData == NULL) || (Size == 0U))
2806 {
2807 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2808 return HAL_ERROR;
2809 }
2810
2811 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2812 {
2813 return HAL_BUSY;
2814 }
2815
2816 /* Process Locked */
2817 __HAL_LOCK(hi2c);
2818
2819 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2820 hi2c->Mode = HAL_I2C_MODE_MEM;
2821 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2822
2823 /* Prepare transfer parameters */
2824 hi2c->XferSize = 0U;
2825 hi2c->pBuffPtr = pData;
2826 hi2c->XferCount = Size;
2827 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2828 hi2c->XferISR = I2C_Mem_ISR_IT;
2829 hi2c->Devaddress = DevAddress;
2830
2831 /* If Memory address size is 8Bit */
2832 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2833 {
2834 /* Prefetch Memory Address */
2835 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2836
2837 /* Reset Memaddress content */
2838 hi2c->Memaddress = 0xFFFFFFFFU;
2839 }
2840 /* If Memory address size is 16Bit */
2841 else
2842 {
2843 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2844 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2845
2846 /* Prepare Memaddress buffer for LSB part */
2847 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2848 }
2849 /* Send Slave Address and Memory Address */
2850 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2851
2852 /* Process Unlocked */
2853 __HAL_UNLOCK(hi2c);
2854
2855 /* Note : The I2C interrupts must be enabled after unlocking current process
2856 to avoid the risk of I2C interrupt handle execution before current
2857 process unlock */
2858
2859 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2860 /* possible to enable all of these */
2861 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2862 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2863 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2864
2865 return HAL_OK;
2866 }
2867 else
2868 {
2869 return HAL_BUSY;
2870 }
2871 }
2872
2873 /**
2874 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2875 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2876 * the configuration information for the specified I2C.
2877 * @param DevAddress Target device address: The device 7 bits address value
2878 * in datasheet must be shifted to the left before calling the interface
2879 * @param MemAddress Internal memory address
2880 * @param MemAddSize Size of internal memory address
2881 * @param pData Pointer to data buffer
2882 * @param Size Amount of data to be sent
2883 * @retval HAL status
2884 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2885 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2886 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2887 {
2888 /* Check the parameters */
2889 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2890
2891 if (hi2c->State == HAL_I2C_STATE_READY)
2892 {
2893 if ((pData == NULL) || (Size == 0U))
2894 {
2895 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2896 return HAL_ERROR;
2897 }
2898
2899 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2900 {
2901 return HAL_BUSY;
2902 }
2903
2904 /* Process Locked */
2905 __HAL_LOCK(hi2c);
2906
2907 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2908 hi2c->Mode = HAL_I2C_MODE_MEM;
2909 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2910
2911 /* Prepare transfer parameters */
2912 hi2c->pBuffPtr = pData;
2913 hi2c->XferCount = Size;
2914 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2915 hi2c->XferISR = I2C_Mem_ISR_IT;
2916 hi2c->Devaddress = DevAddress;
2917
2918 /* If Memory address size is 8Bit */
2919 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2920 {
2921 /* Prefetch Memory Address */
2922 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2923
2924 /* Reset Memaddress content */
2925 hi2c->Memaddress = 0xFFFFFFFFU;
2926 }
2927 /* If Memory address size is 16Bit */
2928 else
2929 {
2930 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2931 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2932
2933 /* Prepare Memaddress buffer for LSB part */
2934 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2935 }
2936 /* Send Slave Address and Memory Address */
2937 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
2938
2939 /* Process Unlocked */
2940 __HAL_UNLOCK(hi2c);
2941
2942 /* Note : The I2C interrupts must be enabled after unlocking current process
2943 to avoid the risk of I2C interrupt handle execution before current
2944 process unlock */
2945
2946 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2947 /* possible to enable all of these */
2948 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2949 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2950 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2951
2952 return HAL_OK;
2953 }
2954 else
2955 {
2956 return HAL_BUSY;
2957 }
2958 }
2959
2960 /**
2961 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
2962 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2963 * the configuration information for the specified I2C.
2964 * @param DevAddress Target device address: The device 7 bits address value
2965 * in datasheet must be shifted to the left before calling the interface
2966 * @param MemAddress Internal memory address
2967 * @param MemAddSize Size of internal memory address
2968 * @param pData Pointer to data buffer
2969 * @param Size Amount of data to be sent
2970 * @retval HAL status
2971 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2972 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2973 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2974 {
2975 HAL_StatusTypeDef dmaxferstatus;
2976
2977 /* Check the parameters */
2978 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2979
2980 if (hi2c->State == HAL_I2C_STATE_READY)
2981 {
2982 if ((pData == NULL) || (Size == 0U))
2983 {
2984 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2985 return HAL_ERROR;
2986 }
2987
2988 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2989 {
2990 return HAL_BUSY;
2991 }
2992
2993 /* Process Locked */
2994 __HAL_LOCK(hi2c);
2995
2996 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2997 hi2c->Mode = HAL_I2C_MODE_MEM;
2998 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2999
3000 /* Prepare transfer parameters */
3001 hi2c->pBuffPtr = pData;
3002 hi2c->XferCount = Size;
3003 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3004 hi2c->XferISR = I2C_Mem_ISR_DMA;
3005 hi2c->Devaddress = DevAddress;
3006
3007 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3008 {
3009 hi2c->XferSize = MAX_NBYTE_SIZE;
3010 }
3011 else
3012 {
3013 hi2c->XferSize = hi2c->XferCount;
3014 }
3015
3016 /* If Memory address size is 8Bit */
3017 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3018 {
3019 /* Prefetch Memory Address */
3020 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3021
3022 /* Reset Memaddress content */
3023 hi2c->Memaddress = 0xFFFFFFFFU;
3024 }
3025 /* If Memory address size is 16Bit */
3026 else
3027 {
3028 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3029 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3030
3031 /* Prepare Memaddress buffer for LSB part */
3032 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3033 }
3034
3035 if (hi2c->hdmatx != NULL)
3036 {
3037 /* Set the I2C DMA transfer complete callback */
3038 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3039
3040 /* Set the DMA error callback */
3041 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3042
3043 /* Set the unused DMA callbacks to NULL */
3044 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3045 hi2c->hdmatx->XferAbortCallback = NULL;
3046
3047 /* Enable the DMA stream or channel depends on Instance */
3048 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3049 hi2c->XferSize);
3050 }
3051 else
3052 {
3053 /* Update I2C state */
3054 hi2c->State = HAL_I2C_STATE_READY;
3055 hi2c->Mode = HAL_I2C_MODE_NONE;
3056
3057 /* Update I2C error code */
3058 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3059
3060 /* Process Unlocked */
3061 __HAL_UNLOCK(hi2c);
3062
3063 return HAL_ERROR;
3064 }
3065
3066 if (dmaxferstatus == HAL_OK)
3067 {
3068 /* Send Slave Address and Memory Address */
3069 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
3070
3071 /* Process Unlocked */
3072 __HAL_UNLOCK(hi2c);
3073
3074 /* Note : The I2C interrupts must be enabled after unlocking current process
3075 to avoid the risk of I2C interrupt handle execution before current
3076 process unlock */
3077 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3078 /* possible to enable all of these */
3079 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3080 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3081 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3082 }
3083 else
3084 {
3085 /* Update I2C state */
3086 hi2c->State = HAL_I2C_STATE_READY;
3087 hi2c->Mode = HAL_I2C_MODE_NONE;
3088
3089 /* Update I2C error code */
3090 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3091
3092 /* Process Unlocked */
3093 __HAL_UNLOCK(hi2c);
3094
3095 return HAL_ERROR;
3096 }
3097
3098 return HAL_OK;
3099 }
3100 else
3101 {
3102 return HAL_BUSY;
3103 }
3104 }
3105
3106 /**
3107 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3108 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3109 * the configuration information for the specified I2C.
3110 * @param DevAddress Target device address: The device 7 bits address value
3111 * in datasheet must be shifted to the left before calling the interface
3112 * @param MemAddress Internal memory address
3113 * @param MemAddSize Size of internal memory address
3114 * @param pData Pointer to data buffer
3115 * @param Size Amount of data to be read
3116 * @retval HAL status
3117 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3118 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3119 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3120 {
3121 HAL_StatusTypeDef dmaxferstatus;
3122
3123 /* Check the parameters */
3124 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3125
3126 if (hi2c->State == HAL_I2C_STATE_READY)
3127 {
3128 if ((pData == NULL) || (Size == 0U))
3129 {
3130 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3131 return HAL_ERROR;
3132 }
3133
3134 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3135 {
3136 return HAL_BUSY;
3137 }
3138
3139 /* Process Locked */
3140 __HAL_LOCK(hi2c);
3141
3142 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3143 hi2c->Mode = HAL_I2C_MODE_MEM;
3144 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3145
3146 /* Prepare transfer parameters */
3147 hi2c->pBuffPtr = pData;
3148 hi2c->XferCount = Size;
3149 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3150 hi2c->XferISR = I2C_Mem_ISR_DMA;
3151 hi2c->Devaddress = DevAddress;
3152
3153 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3154 {
3155 hi2c->XferSize = MAX_NBYTE_SIZE;
3156 }
3157 else
3158 {
3159 hi2c->XferSize = hi2c->XferCount;
3160 }
3161
3162 /* If Memory address size is 8Bit */
3163 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3164 {
3165 /* Prefetch Memory Address */
3166 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3167
3168 /* Reset Memaddress content */
3169 hi2c->Memaddress = 0xFFFFFFFFU;
3170 }
3171 /* If Memory address size is 16Bit */
3172 else
3173 {
3174 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3175 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3176
3177 /* Prepare Memaddress buffer for LSB part */
3178 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3179 }
3180
3181 if (hi2c->hdmarx != NULL)
3182 {
3183 /* Set the I2C DMA transfer complete callback */
3184 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3185
3186 /* Set the DMA error callback */
3187 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3188
3189 /* Set the unused DMA callbacks to NULL */
3190 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3191 hi2c->hdmarx->XferAbortCallback = NULL;
3192
3193 /* Enable the DMA stream or channel depends on Instance */
3194 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3195 hi2c->XferSize);
3196 }
3197 else
3198 {
3199 /* Update I2C state */
3200 hi2c->State = HAL_I2C_STATE_READY;
3201 hi2c->Mode = HAL_I2C_MODE_NONE;
3202
3203 /* Update I2C error code */
3204 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3205
3206 /* Process Unlocked */
3207 __HAL_UNLOCK(hi2c);
3208
3209 return HAL_ERROR;
3210 }
3211
3212 if (dmaxferstatus == HAL_OK)
3213 {
3214 /* Send Slave Address and Memory Address */
3215 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3216
3217 /* Process Unlocked */
3218 __HAL_UNLOCK(hi2c);
3219
3220 /* Note : The I2C interrupts must be enabled after unlocking current process
3221 to avoid the risk of I2C interrupt handle execution before current
3222 process unlock */
3223 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3224 /* possible to enable all of these */
3225 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3226 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3227 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3228 }
3229 else
3230 {
3231 /* Update I2C state */
3232 hi2c->State = HAL_I2C_STATE_READY;
3233 hi2c->Mode = HAL_I2C_MODE_NONE;
3234
3235 /* Update I2C error code */
3236 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3237
3238 /* Process Unlocked */
3239 __HAL_UNLOCK(hi2c);
3240
3241 return HAL_ERROR;
3242 }
3243
3244 return HAL_OK;
3245 }
3246 else
3247 {
3248 return HAL_BUSY;
3249 }
3250 }
3251
3252 /**
3253 * @brief Checks if target device is ready for communication.
3254 * @note This function is used with Memory devices
3255 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3256 * the configuration information for the specified I2C.
3257 * @param DevAddress Target device address: The device 7 bits address value
3258 * in datasheet must be shifted to the left before calling the interface
3259 * @param Trials Number of trials
3260 * @param Timeout Timeout duration
3261 * @retval HAL status
3262 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3263 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
3264 uint32_t Timeout)
3265 {
3266 uint32_t tickstart;
3267
3268 __IO uint32_t I2C_Trials = 0UL;
3269
3270 HAL_StatusTypeDef status = HAL_OK;
3271
3272 FlagStatus tmp1;
3273 FlagStatus tmp2;
3274
3275 if (hi2c->State == HAL_I2C_STATE_READY)
3276 {
3277 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3278 {
3279 return HAL_BUSY;
3280 }
3281
3282 /* Process Locked */
3283 __HAL_LOCK(hi2c);
3284
3285 hi2c->State = HAL_I2C_STATE_BUSY;
3286 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3287
3288 do
3289 {
3290 /* Generate Start */
3291 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
3292
3293 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
3294 /* Wait until STOPF flag is set or a NACK flag is set*/
3295 tickstart = HAL_GetTick();
3296
3297 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3298 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3299
3300 while ((tmp1 == RESET) && (tmp2 == RESET))
3301 {
3302 if (Timeout != HAL_MAX_DELAY)
3303 {
3304 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3305 {
3306 /* Update I2C state */
3307 hi2c->State = HAL_I2C_STATE_READY;
3308
3309 /* Update I2C error code */
3310 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3311
3312 /* Process Unlocked */
3313 __HAL_UNLOCK(hi2c);
3314
3315 return HAL_ERROR;
3316 }
3317 }
3318
3319 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3320 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3321 }
3322
3323 /* Check if the NACKF flag has not been set */
3324 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
3325 {
3326 /* Wait until STOPF flag is reset */
3327 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3328 {
3329 /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */
3330 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
3331 {
3332 /* Clear STOP Flag */
3333 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3334
3335 /* Reset the error code for next trial */
3336 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3337 }
3338 else
3339 {
3340 status = HAL_ERROR;
3341 }
3342 }
3343 else
3344 {
3345 /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */
3346
3347 /* Clear STOP Flag */
3348 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3349
3350 /* Device is ready */
3351 hi2c->State = HAL_I2C_STATE_READY;
3352
3353 /* Process Unlocked */
3354 __HAL_UNLOCK(hi2c);
3355
3356 return HAL_OK;
3357 }
3358 }
3359 else
3360 {
3361 /* A non acknowledge is detected, this mean that device not respond to its address,
3362 a new trial must be performed */
3363
3364 /* Clear NACK Flag */
3365 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3366
3367 /* Wait until STOPF flag is reset */
3368 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3369 {
3370 status = HAL_ERROR;
3371 }
3372 else
3373 {
3374 /* Clear STOP Flag, auto generated with autoend*/
3375 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3376 }
3377 }
3378
3379 /* Increment Trials */
3380 I2C_Trials++;
3381
3382 if ((I2C_Trials < Trials) && (status == HAL_ERROR))
3383 {
3384 status = HAL_OK;
3385 }
3386
3387 } while (I2C_Trials < Trials);
3388
3389 /* Update I2C state */
3390 hi2c->State = HAL_I2C_STATE_READY;
3391
3392 /* Update I2C error code */
3393 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3394
3395 /* Process Unlocked */
3396 __HAL_UNLOCK(hi2c);
3397
3398 return HAL_ERROR;
3399 }
3400 else
3401 {
3402 return HAL_BUSY;
3403 }
3404 }
3405
3406 /**
3407 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3408 * @note This interface allow to manage repeated start condition when a direction change during transfer
3409 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3410 * the configuration information for the specified I2C.
3411 * @param DevAddress Target device address: The device 7 bits address value
3412 * in datasheet must be shifted to the left before calling the interface
3413 * @param pData Pointer to data buffer
3414 * @param Size Amount of data to be sent
3415 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3416 * @retval HAL status
3417 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3418 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3419 uint16_t Size, uint32_t XferOptions)
3420 {
3421 uint32_t xfermode;
3422 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3423 uint32_t sizetoxfer = 0U;
3424
3425 /* Check the parameters */
3426 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3427
3428 if (hi2c->State == HAL_I2C_STATE_READY)
3429 {
3430 /* Process Locked */
3431 __HAL_LOCK(hi2c);
3432
3433 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3434 hi2c->Mode = HAL_I2C_MODE_MASTER;
3435 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3436
3437 /* Prepare transfer parameters */
3438 hi2c->pBuffPtr = pData;
3439 hi2c->XferCount = Size;
3440 hi2c->XferOptions = XferOptions;
3441 hi2c->XferISR = I2C_Master_ISR_IT;
3442
3443 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3444 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3445 {
3446 hi2c->XferSize = MAX_NBYTE_SIZE;
3447 xfermode = I2C_RELOAD_MODE;
3448 }
3449 else
3450 {
3451 hi2c->XferSize = hi2c->XferCount;
3452 xfermode = hi2c->XferOptions;
3453 }
3454
3455 if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
3456 (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
3457 {
3458 /* Preload TX register */
3459 /* Write data to TXDR */
3460 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
3461
3462 /* Increment Buffer pointer */
3463 hi2c->pBuffPtr++;
3464
3465 sizetoxfer = hi2c->XferSize;
3466 hi2c->XferCount--;
3467 hi2c->XferSize--;
3468 }
3469
3470 /* If transfer direction not change and there is no request to start another frame,
3471 do not generate Restart Condition */
3472 /* Mean Previous state is same as current state */
3473 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3474 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3475 {
3476 xferrequest = I2C_NO_STARTSTOP;
3477 }
3478 else
3479 {
3480 /* Convert OTHER_xxx XferOptions if any */
3481 I2C_ConvertOtherXferOptions(hi2c);
3482
3483 /* Update xfermode accordingly if no reload is necessary */
3484 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3485 {
3486 xfermode = hi2c->XferOptions;
3487 }
3488 }
3489
3490 /* Send Slave Address and set NBYTES to write */
3491 if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
3492 {
3493 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
3494 }
3495 else
3496 {
3497 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3498 }
3499
3500 /* Process Unlocked */
3501 __HAL_UNLOCK(hi2c);
3502
3503 /* Note : The I2C interrupts must be enabled after unlocking current process
3504 to avoid the risk of I2C interrupt handle execution before current
3505 process unlock */
3506 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3507 /* possible to enable all of these */
3508 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3509 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3510 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3511
3512 return HAL_OK;
3513 }
3514 else
3515 {
3516 return HAL_BUSY;
3517 }
3518 }
3519
3520 /**
3521 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3522 * @note This interface allow to manage repeated start condition when a direction change during transfer
3523 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3524 * the configuration information for the specified I2C.
3525 * @param DevAddress Target device address: The device 7 bits address value
3526 * in datasheet must be shifted to the left before calling the interface
3527 * @param pData Pointer to data buffer
3528 * @param Size Amount of data to be sent
3529 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3530 * @retval HAL status
3531 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3532 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3533 uint16_t Size, uint32_t XferOptions)
3534 {
3535 uint32_t xfermode;
3536 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3537 HAL_StatusTypeDef dmaxferstatus;
3538 uint32_t sizetoxfer = 0U;
3539
3540 /* Check the parameters */
3541 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3542
3543 if (hi2c->State == HAL_I2C_STATE_READY)
3544 {
3545 /* Process Locked */
3546 __HAL_LOCK(hi2c);
3547
3548 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3549 hi2c->Mode = HAL_I2C_MODE_MASTER;
3550 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3551
3552 /* Prepare transfer parameters */
3553 hi2c->pBuffPtr = pData;
3554 hi2c->XferCount = Size;
3555 hi2c->XferOptions = XferOptions;
3556 hi2c->XferISR = I2C_Master_ISR_DMA;
3557
3558 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3559 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3560 {
3561 hi2c->XferSize = MAX_NBYTE_SIZE;
3562 xfermode = I2C_RELOAD_MODE;
3563 }
3564 else
3565 {
3566 hi2c->XferSize = hi2c->XferCount;
3567 xfermode = hi2c->XferOptions;
3568 }
3569
3570 if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
3571 (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
3572 {
3573 /* Preload TX register */
3574 /* Write data to TXDR */
3575 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
3576
3577 /* Increment Buffer pointer */
3578 hi2c->pBuffPtr++;
3579
3580 sizetoxfer = hi2c->XferSize;
3581 hi2c->XferCount--;
3582 hi2c->XferSize--;
3583 }
3584
3585 /* If transfer direction not change and there is no request to start another frame,
3586 do not generate Restart Condition */
3587 /* Mean Previous state is same as current state */
3588 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3589 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3590 {
3591 xferrequest = I2C_NO_STARTSTOP;
3592 }
3593 else
3594 {
3595 /* Convert OTHER_xxx XferOptions if any */
3596 I2C_ConvertOtherXferOptions(hi2c);
3597
3598 /* Update xfermode accordingly if no reload is necessary */
3599 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3600 {
3601 xfermode = hi2c->XferOptions;
3602 }
3603 }
3604
3605 if (hi2c->XferSize > 0U)
3606 {
3607 if (hi2c->hdmatx != NULL)
3608 {
3609 /* Set the I2C DMA transfer complete callback */
3610 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3611
3612 /* Set the DMA error callback */
3613 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3614
3615 /* Set the unused DMA callbacks to NULL */
3616 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3617 hi2c->hdmatx->XferAbortCallback = NULL;
3618
3619 /* Enable the DMA stream or channel depends on Instance */
3620 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
3621 (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
3622 }
3623 else
3624 {
3625 /* Update I2C state */
3626 hi2c->State = HAL_I2C_STATE_READY;
3627 hi2c->Mode = HAL_I2C_MODE_NONE;
3628
3629 /* Update I2C error code */
3630 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3631
3632 /* Process Unlocked */
3633 __HAL_UNLOCK(hi2c);
3634
3635 return HAL_ERROR;
3636 }
3637
3638 if (dmaxferstatus == HAL_OK)
3639 {
3640 /* Send Slave Address and set NBYTES to write */
3641 if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
3642 {
3643 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
3644 }
3645 else
3646 {
3647 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3648 }
3649
3650 /* Update XferCount value */
3651 hi2c->XferCount -= hi2c->XferSize;
3652
3653 /* Process Unlocked */
3654 __HAL_UNLOCK(hi2c);
3655
3656 /* Note : The I2C interrupts must be enabled after unlocking current process
3657 to avoid the risk of I2C interrupt handle execution before current
3658 process unlock */
3659 /* Enable ERR and NACK interrupts */
3660 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3661
3662 /* Enable DMA Request */
3663 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3664 }
3665 else
3666 {
3667 /* Update I2C state */
3668 hi2c->State = HAL_I2C_STATE_READY;
3669 hi2c->Mode = HAL_I2C_MODE_NONE;
3670
3671 /* Update I2C error code */
3672 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3673
3674 /* Process Unlocked */
3675 __HAL_UNLOCK(hi2c);
3676
3677 return HAL_ERROR;
3678 }
3679 }
3680 else
3681 {
3682 /* Update Transfer ISR function pointer */
3683 hi2c->XferISR = I2C_Master_ISR_IT;
3684
3685 /* Send Slave Address */
3686 /* Set NBYTES to write and generate START condition */
3687 if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
3688 {
3689 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
3690 }
3691 else
3692 {
3693 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3694 }
3695
3696 /* Process Unlocked */
3697 __HAL_UNLOCK(hi2c);
3698
3699 /* Note : The I2C interrupts must be enabled after unlocking current process
3700 to avoid the risk of I2C interrupt handle execution before current
3701 process unlock */
3702 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3703 /* possible to enable all of these */
3704 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3705 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3706 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3707 }
3708
3709 return HAL_OK;
3710 }
3711 else
3712 {
3713 return HAL_BUSY;
3714 }
3715 }
3716
3717 /**
3718 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3719 * @note This interface allow to manage repeated start condition when a direction change during transfer
3720 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3721 * the configuration information for the specified I2C.
3722 * @param DevAddress Target device address: The device 7 bits address value
3723 * in datasheet must be shifted to the left before calling the interface
3724 * @param pData Pointer to data buffer
3725 * @param Size Amount of data to be sent
3726 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3727 * @retval HAL status
3728 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3729 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3730 uint16_t Size, uint32_t XferOptions)
3731 {
3732 uint32_t xfermode;
3733 uint32_t xferrequest = I2C_GENERATE_START_READ;
3734
3735 /* Check the parameters */
3736 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3737
3738 if (hi2c->State == HAL_I2C_STATE_READY)
3739 {
3740 /* Process Locked */
3741 __HAL_LOCK(hi2c);
3742
3743 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3744 hi2c->Mode = HAL_I2C_MODE_MASTER;
3745 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3746
3747 /* Prepare transfer parameters */
3748 hi2c->pBuffPtr = pData;
3749 hi2c->XferCount = Size;
3750 hi2c->XferOptions = XferOptions;
3751 hi2c->XferISR = I2C_Master_ISR_IT;
3752
3753 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3754 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3755 {
3756 hi2c->XferSize = MAX_NBYTE_SIZE;
3757 xfermode = I2C_RELOAD_MODE;
3758 }
3759 else
3760 {
3761 hi2c->XferSize = hi2c->XferCount;
3762 xfermode = hi2c->XferOptions;
3763 }
3764
3765 /* If transfer direction not change and there is no request to start another frame,
3766 do not generate Restart Condition */
3767 /* Mean Previous state is same as current state */
3768 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3769 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3770 {
3771 xferrequest = I2C_NO_STARTSTOP;
3772 }
3773 else
3774 {
3775 /* Convert OTHER_xxx XferOptions if any */
3776 I2C_ConvertOtherXferOptions(hi2c);
3777
3778 /* Update xfermode accordingly if no reload is necessary */
3779 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3780 {
3781 xfermode = hi2c->XferOptions;
3782 }
3783 }
3784
3785 /* Send Slave Address and set NBYTES to read */
3786 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3787
3788 /* Process Unlocked */
3789 __HAL_UNLOCK(hi2c);
3790
3791 /* Note : The I2C interrupts must be enabled after unlocking current process
3792 to avoid the risk of I2C interrupt handle execution before current
3793 process unlock */
3794 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3795
3796 return HAL_OK;
3797 }
3798 else
3799 {
3800 return HAL_BUSY;
3801 }
3802 }
3803
3804 /**
3805 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
3806 * @note This interface allow to manage repeated start condition when a direction change during transfer
3807 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3808 * the configuration information for the specified I2C.
3809 * @param DevAddress Target device address: The device 7 bits address value
3810 * in datasheet must be shifted to the left before calling the interface
3811 * @param pData Pointer to data buffer
3812 * @param Size Amount of data to be sent
3813 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3814 * @retval HAL status
3815 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3816 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3817 uint16_t Size, uint32_t XferOptions)
3818 {
3819 uint32_t xfermode;
3820 uint32_t xferrequest = I2C_GENERATE_START_READ;
3821 HAL_StatusTypeDef dmaxferstatus;
3822
3823 /* Check the parameters */
3824 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3825
3826 if (hi2c->State == HAL_I2C_STATE_READY)
3827 {
3828 /* Process Locked */
3829 __HAL_LOCK(hi2c);
3830
3831 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3832 hi2c->Mode = HAL_I2C_MODE_MASTER;
3833 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3834
3835 /* Prepare transfer parameters */
3836 hi2c->pBuffPtr = pData;
3837 hi2c->XferCount = Size;
3838 hi2c->XferOptions = XferOptions;
3839 hi2c->XferISR = I2C_Master_ISR_DMA;
3840
3841 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3842 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3843 {
3844 hi2c->XferSize = MAX_NBYTE_SIZE;
3845 xfermode = I2C_RELOAD_MODE;
3846 }
3847 else
3848 {
3849 hi2c->XferSize = hi2c->XferCount;
3850 xfermode = hi2c->XferOptions;
3851 }
3852
3853 /* If transfer direction not change and there is no request to start another frame,
3854 do not generate Restart Condition */
3855 /* Mean Previous state is same as current state */
3856 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3857 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3858 {
3859 xferrequest = I2C_NO_STARTSTOP;
3860 }
3861 else
3862 {
3863 /* Convert OTHER_xxx XferOptions if any */
3864 I2C_ConvertOtherXferOptions(hi2c);
3865
3866 /* Update xfermode accordingly if no reload is necessary */
3867 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3868 {
3869 xfermode = hi2c->XferOptions;
3870 }
3871 }
3872
3873 if (hi2c->XferSize > 0U)
3874 {
3875 if (hi2c->hdmarx != NULL)
3876 {
3877 /* Set the I2C DMA transfer complete callback */
3878 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3879
3880 /* Set the DMA error callback */
3881 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3882
3883 /* Set the unused DMA callbacks to NULL */
3884 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3885 hi2c->hdmarx->XferAbortCallback = NULL;
3886
3887 /* Enable the DMA stream or channel depends on Instance */
3888 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3889 hi2c->XferSize);
3890 }
3891 else
3892 {
3893 /* Update I2C state */
3894 hi2c->State = HAL_I2C_STATE_READY;
3895 hi2c->Mode = HAL_I2C_MODE_NONE;
3896
3897 /* Update I2C error code */
3898 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3899
3900 /* Process Unlocked */
3901 __HAL_UNLOCK(hi2c);
3902
3903 return HAL_ERROR;
3904 }
3905
3906 if (dmaxferstatus == HAL_OK)
3907 {
3908 /* Send Slave Address and set NBYTES to read */
3909 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3910
3911 /* Update XferCount value */
3912 hi2c->XferCount -= hi2c->XferSize;
3913
3914 /* Process Unlocked */
3915 __HAL_UNLOCK(hi2c);
3916
3917 /* Note : The I2C interrupts must be enabled after unlocking current process
3918 to avoid the risk of I2C interrupt handle execution before current
3919 process unlock */
3920 /* Enable ERR and NACK interrupts */
3921 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3922
3923 /* Enable DMA Request */
3924 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
3925 }
3926 else
3927 {
3928 /* Update I2C state */
3929 hi2c->State = HAL_I2C_STATE_READY;
3930 hi2c->Mode = HAL_I2C_MODE_NONE;
3931
3932 /* Update I2C error code */
3933 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3934
3935 /* Process Unlocked */
3936 __HAL_UNLOCK(hi2c);
3937
3938 return HAL_ERROR;
3939 }
3940 }
3941 else
3942 {
3943 /* Update Transfer ISR function pointer */
3944 hi2c->XferISR = I2C_Master_ISR_IT;
3945
3946 /* Send Slave Address */
3947 /* Set NBYTES to read and generate START condition */
3948 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3949 I2C_GENERATE_START_READ);
3950
3951 /* Process Unlocked */
3952 __HAL_UNLOCK(hi2c);
3953
3954 /* Note : The I2C interrupts must be enabled after unlocking current process
3955 to avoid the risk of I2C interrupt handle execution before current
3956 process unlock */
3957 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
3958 /* possible to enable all of these */
3959 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3960 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3961 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3962 }
3963
3964 return HAL_OK;
3965 }
3966 else
3967 {
3968 return HAL_BUSY;
3969 }
3970 }
3971
3972 /**
3973 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
3974 * @note This interface allow to manage repeated start condition when a direction change during transfer
3975 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3976 * the configuration information for the specified I2C.
3977 * @param pData Pointer to data buffer
3978 * @param Size Amount of data to be sent
3979 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3980 * @retval HAL status
3981 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3982 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
3983 uint32_t XferOptions)
3984 {
3985 /* Declaration of tmp to prevent undefined behavior of volatile usage */
3986 FlagStatus tmp;
3987
3988 /* Check the parameters */
3989 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3990
3991 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3992 {
3993 if ((pData == NULL) || (Size == 0U))
3994 {
3995 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3996 return HAL_ERROR;
3997 }
3998
3999 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4000 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4001
4002 /* Process Locked */
4003 __HAL_LOCK(hi2c);
4004
4005 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4006 /* and then toggle the HAL slave RX state to TX state */
4007 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4008 {
4009 /* Disable associated Interrupts */
4010 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4011
4012 /* Abort DMA Xfer if any */
4013 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4014 {
4015 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4016
4017 if (hi2c->hdmarx != NULL)
4018 {
4019 /* Set the I2C DMA Abort callback :
4020 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4021 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4022
4023 /* Abort DMA RX */
4024 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4025 {
4026 /* Call Directly XferAbortCallback function in case of error */
4027 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4028 }
4029 }
4030 }
4031 }
4032
4033 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4034 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4035 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4036
4037 /* Enable Address Acknowledge */
4038 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4039
4040 /* Prepare transfer parameters */
4041 hi2c->pBuffPtr = pData;
4042 hi2c->XferCount = Size;
4043 hi2c->XferSize = hi2c->XferCount;
4044 hi2c->XferOptions = XferOptions;
4045 hi2c->XferISR = I2C_Slave_ISR_IT;
4046
4047 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4048 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4049 {
4050 /* Clear ADDR flag after prepare the transfer parameters */
4051 /* This action will generate an acknowledge to the Master */
4052 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4053 }
4054
4055 /* Process Unlocked */
4056 __HAL_UNLOCK(hi2c);
4057
4058 /* Note : The I2C interrupts must be enabled after unlocking current process
4059 to avoid the risk of I2C interrupt handle execution before current
4060 process unlock */
4061 /* REnable ADDR interrupt */
4062 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
4063
4064 return HAL_OK;
4065 }
4066 else
4067 {
4068 return HAL_ERROR;
4069 }
4070 }
4071
4072 /**
4073 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
4074 * @note This interface allow to manage repeated start condition when a direction change during transfer
4075 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4076 * the configuration information for the specified I2C.
4077 * @param pData Pointer to data buffer
4078 * @param Size Amount of data to be sent
4079 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4080 * @retval HAL status
4081 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4082 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4083 uint32_t XferOptions)
4084 {
4085 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4086 FlagStatus tmp;
4087 HAL_StatusTypeDef dmaxferstatus;
4088
4089 /* Check the parameters */
4090 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4091
4092 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4093 {
4094 if ((pData == NULL) || (Size == 0U))
4095 {
4096 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4097 return HAL_ERROR;
4098 }
4099
4100 /* Process Locked */
4101 __HAL_LOCK(hi2c);
4102
4103 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4104 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4105
4106 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4107 /* and then toggle the HAL slave RX state to TX state */
4108 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4109 {
4110 /* Disable associated Interrupts */
4111 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4112
4113 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4114 {
4115 /* Abort DMA Xfer if any */
4116 if (hi2c->hdmarx != NULL)
4117 {
4118 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4119
4120 /* Set the I2C DMA Abort callback :
4121 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4122 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4123
4124 /* Abort DMA RX */
4125 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4126 {
4127 /* Call Directly XferAbortCallback function in case of error */
4128 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4129 }
4130 }
4131 }
4132 }
4133 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4134 {
4135 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4136 {
4137 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4138
4139 /* Abort DMA Xfer if any */
4140 if (hi2c->hdmatx != NULL)
4141 {
4142 /* Set the I2C DMA Abort callback :
4143 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4144 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4145
4146 /* Abort DMA TX */
4147 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4148 {
4149 /* Call Directly XferAbortCallback function in case of error */
4150 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4151 }
4152 }
4153 }
4154 }
4155 else
4156 {
4157 /* Nothing to do */
4158 }
4159
4160 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4161 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4162 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4163
4164 /* Enable Address Acknowledge */
4165 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4166
4167 /* Prepare transfer parameters */
4168 hi2c->pBuffPtr = pData;
4169 hi2c->XferCount = Size;
4170 hi2c->XferSize = hi2c->XferCount;
4171 hi2c->XferOptions = XferOptions;
4172 hi2c->XferISR = I2C_Slave_ISR_DMA;
4173
4174 if (hi2c->hdmatx != NULL)
4175 {
4176 /* Set the I2C DMA transfer complete callback */
4177 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
4178
4179 /* Set the DMA error callback */
4180 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4181
4182 /* Set the unused DMA callbacks to NULL */
4183 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4184 hi2c->hdmatx->XferAbortCallback = NULL;
4185
4186 /* Enable the DMA stream or channel depends on Instance */
4187 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
4188 hi2c->XferSize);
4189 }
4190 else
4191 {
4192 /* Update I2C state */
4193 hi2c->State = HAL_I2C_STATE_LISTEN;
4194 hi2c->Mode = HAL_I2C_MODE_NONE;
4195
4196 /* Update I2C error code */
4197 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4198
4199 /* Process Unlocked */
4200 __HAL_UNLOCK(hi2c);
4201
4202 return HAL_ERROR;
4203 }
4204
4205 if (dmaxferstatus == HAL_OK)
4206 {
4207 /* Update XferCount value */
4208 hi2c->XferCount -= hi2c->XferSize;
4209
4210 /* Reset XferSize */
4211 hi2c->XferSize = 0;
4212 }
4213 else
4214 {
4215 /* Update I2C state */
4216 hi2c->State = HAL_I2C_STATE_LISTEN;
4217 hi2c->Mode = HAL_I2C_MODE_NONE;
4218
4219 /* Update I2C error code */
4220 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4221
4222 /* Process Unlocked */
4223 __HAL_UNLOCK(hi2c);
4224
4225 return HAL_ERROR;
4226 }
4227
4228 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4229 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4230 {
4231 /* Clear ADDR flag after prepare the transfer parameters */
4232 /* This action will generate an acknowledge to the Master */
4233 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4234 }
4235
4236 /* Process Unlocked */
4237 __HAL_UNLOCK(hi2c);
4238
4239 /* Enable DMA Request */
4240 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
4241
4242 /* Note : The I2C interrupts must be enabled after unlocking current process
4243 to avoid the risk of I2C interrupt handle execution before current
4244 process unlock */
4245 /* Enable ERR, STOP, NACK, ADDR interrupts */
4246 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4247
4248 return HAL_OK;
4249 }
4250 else
4251 {
4252 return HAL_ERROR;
4253 }
4254 }
4255
4256 /**
4257 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4258 * @note This interface allow to manage repeated start condition when a direction change during transfer
4259 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4260 * the configuration information for the specified I2C.
4261 * @param pData Pointer to data buffer
4262 * @param Size Amount of data to be sent
4263 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4264 * @retval HAL status
4265 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4266 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4267 uint32_t XferOptions)
4268 {
4269 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4270 FlagStatus tmp;
4271
4272 /* Check the parameters */
4273 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4274
4275 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4276 {
4277 if ((pData == NULL) || (Size == 0U))
4278 {
4279 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4280 return HAL_ERROR;
4281 }
4282
4283 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4284 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4285
4286 /* Process Locked */
4287 __HAL_LOCK(hi2c);
4288
4289 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4290 /* and then toggle the HAL slave TX state to RX state */
4291 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4292 {
4293 /* Disable associated Interrupts */
4294 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4295
4296 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4297 {
4298 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4299
4300 /* Abort DMA Xfer if any */
4301 if (hi2c->hdmatx != NULL)
4302 {
4303 /* Set the I2C DMA Abort callback :
4304 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4305 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4306
4307 /* Abort DMA TX */
4308 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4309 {
4310 /* Call Directly XferAbortCallback function in case of error */
4311 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4312 }
4313 }
4314 }
4315 }
4316
4317 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4318 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4319 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4320
4321 /* Enable Address Acknowledge */
4322 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4323
4324 /* Prepare transfer parameters */
4325 hi2c->pBuffPtr = pData;
4326 hi2c->XferCount = Size;
4327 hi2c->XferSize = hi2c->XferCount;
4328 hi2c->XferOptions = XferOptions;
4329 hi2c->XferISR = I2C_Slave_ISR_IT;
4330
4331 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4332 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4333 {
4334 /* Clear ADDR flag after prepare the transfer parameters */
4335 /* This action will generate an acknowledge to the Master */
4336 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4337 }
4338
4339 /* Process Unlocked */
4340 __HAL_UNLOCK(hi2c);
4341
4342 /* Note : The I2C interrupts must be enabled after unlocking current process
4343 to avoid the risk of I2C interrupt handle execution before current
4344 process unlock */
4345 /* REnable ADDR interrupt */
4346 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4347
4348 return HAL_OK;
4349 }
4350 else
4351 {
4352 return HAL_ERROR;
4353 }
4354 }
4355
4356 /**
4357 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
4358 * @note This interface allow to manage repeated start condition when a direction change during transfer
4359 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4360 * the configuration information for the specified I2C.
4361 * @param pData Pointer to data buffer
4362 * @param Size Amount of data to be sent
4363 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4364 * @retval HAL status
4365 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4366 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4367 uint32_t XferOptions)
4368 {
4369 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4370 FlagStatus tmp;
4371 HAL_StatusTypeDef dmaxferstatus;
4372
4373 /* Check the parameters */
4374 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4375
4376 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4377 {
4378 if ((pData == NULL) || (Size == 0U))
4379 {
4380 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4381 return HAL_ERROR;
4382 }
4383
4384 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4385 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4386
4387 /* Process Locked */
4388 __HAL_LOCK(hi2c);
4389
4390 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4391 /* and then toggle the HAL slave TX state to RX state */
4392 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4393 {
4394 /* Disable associated Interrupts */
4395 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4396
4397 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4398 {
4399 /* Abort DMA Xfer if any */
4400 if (hi2c->hdmatx != NULL)
4401 {
4402 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4403
4404 /* Set the I2C DMA Abort callback :
4405 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4406 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4407
4408 /* Abort DMA TX */
4409 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4410 {
4411 /* Call Directly XferAbortCallback function in case of error */
4412 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4413 }
4414 }
4415 }
4416 }
4417 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4418 {
4419 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4420 {
4421 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4422
4423 /* Abort DMA Xfer if any */
4424 if (hi2c->hdmarx != NULL)
4425 {
4426 /* Set the I2C DMA Abort callback :
4427 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4428 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4429
4430 /* Abort DMA RX */
4431 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4432 {
4433 /* Call Directly XferAbortCallback function in case of error */
4434 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4435 }
4436 }
4437 }
4438 }
4439 else
4440 {
4441 /* Nothing to do */
4442 }
4443
4444 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4445 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4446 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4447
4448 /* Enable Address Acknowledge */
4449 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4450
4451 /* Prepare transfer parameters */
4452 hi2c->pBuffPtr = pData;
4453 hi2c->XferCount = Size;
4454 hi2c->XferSize = hi2c->XferCount;
4455 hi2c->XferOptions = XferOptions;
4456 hi2c->XferISR = I2C_Slave_ISR_DMA;
4457
4458 if (hi2c->hdmarx != NULL)
4459 {
4460 /* Set the I2C DMA transfer complete callback */
4461 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
4462
4463 /* Set the DMA error callback */
4464 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4465
4466 /* Set the unused DMA callbacks to NULL */
4467 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4468 hi2c->hdmarx->XferAbortCallback = NULL;
4469
4470 /* Enable the DMA stream or channel depends on Instance */
4471 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
4472 (uint32_t)pData, hi2c->XferSize);
4473 }
4474 else
4475 {
4476 /* Update I2C state */
4477 hi2c->State = HAL_I2C_STATE_LISTEN;
4478 hi2c->Mode = HAL_I2C_MODE_NONE;
4479
4480 /* Update I2C error code */
4481 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4482
4483 /* Process Unlocked */
4484 __HAL_UNLOCK(hi2c);
4485
4486 return HAL_ERROR;
4487 }
4488
4489 if (dmaxferstatus == HAL_OK)
4490 {
4491 /* Update XferCount value */
4492 hi2c->XferCount -= hi2c->XferSize;
4493
4494 /* Reset XferSize */
4495 hi2c->XferSize = 0;
4496 }
4497 else
4498 {
4499 /* Update I2C state */
4500 hi2c->State = HAL_I2C_STATE_LISTEN;
4501 hi2c->Mode = HAL_I2C_MODE_NONE;
4502
4503 /* Update I2C error code */
4504 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4505
4506 /* Process Unlocked */
4507 __HAL_UNLOCK(hi2c);
4508
4509 return HAL_ERROR;
4510 }
4511
4512 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4513 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4514 {
4515 /* Clear ADDR flag after prepare the transfer parameters */
4516 /* This action will generate an acknowledge to the Master */
4517 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4518 }
4519
4520 /* Process Unlocked */
4521 __HAL_UNLOCK(hi2c);
4522
4523 /* Enable DMA Request */
4524 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4525
4526 /* Note : The I2C interrupts must be enabled after unlocking current process
4527 to avoid the risk of I2C interrupt handle execution before current
4528 process unlock */
4529 /* REnable ADDR interrupt */
4530 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4531
4532 return HAL_OK;
4533 }
4534 else
4535 {
4536 return HAL_ERROR;
4537 }
4538 }
4539
4540 /**
4541 * @brief Enable the Address listen mode with Interrupt.
4542 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4543 * the configuration information for the specified I2C.
4544 * @retval HAL status
4545 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4546 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4547 {
4548 if (hi2c->State == HAL_I2C_STATE_READY)
4549 {
4550 hi2c->State = HAL_I2C_STATE_LISTEN;
4551 hi2c->XferISR = I2C_Slave_ISR_IT;
4552
4553 /* Enable the Address Match interrupt */
4554 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4555
4556 return HAL_OK;
4557 }
4558 else
4559 {
4560 return HAL_BUSY;
4561 }
4562 }
4563
4564 /**
4565 * @brief Disable the Address listen mode with Interrupt.
4566 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4567 * the configuration information for the specified I2C
4568 * @retval HAL status
4569 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4570 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4571 {
4572 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4573 uint32_t tmp;
4574
4575 /* Disable Address listen mode only if a transfer is not ongoing */
4576 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4577 {
4578 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4579 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4580 hi2c->State = HAL_I2C_STATE_READY;
4581 hi2c->Mode = HAL_I2C_MODE_NONE;
4582 hi2c->XferISR = NULL;
4583
4584 /* Disable the Address Match interrupt */
4585 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4586
4587 return HAL_OK;
4588 }
4589 else
4590 {
4591 return HAL_BUSY;
4592 }
4593 }
4594
4595 /**
4596 * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt.
4597 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4598 * the configuration information for the specified I2C.
4599 * @param DevAddress Target device address: The device 7 bits address value
4600 * in datasheet must be shifted to the left before calling the interface
4601 * @retval HAL status
4602 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4603 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4604 {
4605 HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
4606
4607 if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM))
4608 {
4609 /* Process Locked */
4610 __HAL_LOCK(hi2c);
4611
4612 /* Disable Interrupts and Store Previous state */
4613 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
4614 {
4615 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4616 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
4617 }
4618 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4619 {
4620 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4621 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
4622 }
4623 else
4624 {
4625 /* Do nothing */
4626 }
4627
4628 /* Set State at HAL_I2C_STATE_ABORT */
4629 hi2c->State = HAL_I2C_STATE_ABORT;
4630
4631 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
4632 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
4633 I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
4634
4635 /* Process Unlocked */
4636 __HAL_UNLOCK(hi2c);
4637
4638 /* Note : The I2C interrupts must be enabled after unlocking current process
4639 to avoid the risk of I2C interrupt handle execution before current
4640 process unlock */
4641 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4642
4643 return HAL_OK;
4644 }
4645 else
4646 {
4647 /* Wrong usage of abort function */
4648 /* This function should be used only in case of abort monitored by master device */
4649 return HAL_ERROR;
4650 }
4651 }
4652
4653 /**
4654 * @}
4655 */
4656
4657 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4658 * @{
4659 */
4660
4661 /**
4662 * @brief This function handles I2C event interrupt request.
4663 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4664 * the configuration information for the specified I2C.
4665 * @retval None
4666 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4667 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
4668 {
4669 /* Get current IT Flags and IT sources value */
4670 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4671 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4672
4673 /* I2C events treatment -------------------------------------*/
4674 if (hi2c->XferISR != NULL)
4675 {
4676 hi2c->XferISR(hi2c, itflags, itsources);
4677 }
4678 }
4679
4680 /**
4681 * @brief This function handles I2C error interrupt request.
4682 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4683 * the configuration information for the specified I2C.
4684 * @retval None
4685 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4686 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4687 {
4688 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4689 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4690 uint32_t tmperror;
4691
4692 /* I2C Bus error interrupt occurred ------------------------------------*/
4693 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
4694 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4695 {
4696 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
4697
4698 /* Clear BERR flag */
4699 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4700 }
4701
4702 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
4703 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
4704 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4705 {
4706 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
4707
4708 /* Clear OVR flag */
4709 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4710 }
4711
4712 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
4713 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
4714 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4715 {
4716 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
4717
4718 /* Clear ARLO flag */
4719 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4720 }
4721
4722 /* Store current volatile hi2c->ErrorCode, misra rule */
4723 tmperror = hi2c->ErrorCode;
4724
4725 /* Call the Error Callback in case of Error detected */
4726 if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
4727 {
4728 I2C_ITError(hi2c, tmperror);
4729 }
4730 }
4731
4732 /**
4733 * @brief Master Tx Transfer completed callback.
4734 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4735 * the configuration information for the specified I2C.
4736 * @retval None
4737 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4738 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4739 {
4740 /* Prevent unused argument(s) compilation warning */
4741 UNUSED(hi2c);
4742
4743 /* NOTE : This function should not be modified, when the callback is needed,
4744 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4745 */
4746 }
4747
4748 /**
4749 * @brief Master Rx Transfer completed callback.
4750 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4751 * the configuration information for the specified I2C.
4752 * @retval None
4753 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)4754 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4755 {
4756 /* Prevent unused argument(s) compilation warning */
4757 UNUSED(hi2c);
4758
4759 /* NOTE : This function should not be modified, when the callback is needed,
4760 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
4761 */
4762 }
4763
4764 /** @brief Slave Tx Transfer completed callback.
4765 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4766 * the configuration information for the specified I2C.
4767 * @retval None
4768 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)4769 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
4770 {
4771 /* Prevent unused argument(s) compilation warning */
4772 UNUSED(hi2c);
4773
4774 /* NOTE : This function should not be modified, when the callback is needed,
4775 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
4776 */
4777 }
4778
4779 /**
4780 * @brief Slave Rx Transfer completed callback.
4781 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4782 * the configuration information for the specified I2C.
4783 * @retval None
4784 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)4785 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
4786 {
4787 /* Prevent unused argument(s) compilation warning */
4788 UNUSED(hi2c);
4789
4790 /* NOTE : This function should not be modified, when the callback is needed,
4791 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
4792 */
4793 }
4794
4795 /**
4796 * @brief Slave Address Match callback.
4797 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4798 * the configuration information for the specified I2C.
4799 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
4800 * @param AddrMatchCode Address Match Code
4801 * @retval None
4802 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)4803 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
4804 {
4805 /* Prevent unused argument(s) compilation warning */
4806 UNUSED(hi2c);
4807 UNUSED(TransferDirection);
4808 UNUSED(AddrMatchCode);
4809
4810 /* NOTE : This function should not be modified, when the callback is needed,
4811 the HAL_I2C_AddrCallback() could be implemented in the user file
4812 */
4813 }
4814
4815 /**
4816 * @brief Listen Complete callback.
4817 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4818 * the configuration information for the specified I2C.
4819 * @retval None
4820 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)4821 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
4822 {
4823 /* Prevent unused argument(s) compilation warning */
4824 UNUSED(hi2c);
4825
4826 /* NOTE : This function should not be modified, when the callback is needed,
4827 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
4828 */
4829 }
4830
4831 /**
4832 * @brief Memory Tx Transfer completed callback.
4833 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4834 * the configuration information for the specified I2C.
4835 * @retval None
4836 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)4837 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
4838 {
4839 /* Prevent unused argument(s) compilation warning */
4840 UNUSED(hi2c);
4841
4842 /* NOTE : This function should not be modified, when the callback is needed,
4843 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
4844 */
4845 }
4846
4847 /**
4848 * @brief Memory Rx Transfer completed callback.
4849 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4850 * the configuration information for the specified I2C.
4851 * @retval None
4852 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)4853 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
4854 {
4855 /* Prevent unused argument(s) compilation warning */
4856 UNUSED(hi2c);
4857
4858 /* NOTE : This function should not be modified, when the callback is needed,
4859 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
4860 */
4861 }
4862
4863 /**
4864 * @brief I2C error callback.
4865 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4866 * the configuration information for the specified I2C.
4867 * @retval None
4868 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)4869 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
4870 {
4871 /* Prevent unused argument(s) compilation warning */
4872 UNUSED(hi2c);
4873
4874 /* NOTE : This function should not be modified, when the callback is needed,
4875 the HAL_I2C_ErrorCallback could be implemented in the user file
4876 */
4877 }
4878
4879 /**
4880 * @brief I2C abort callback.
4881 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4882 * the configuration information for the specified I2C.
4883 * @retval None
4884 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)4885 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
4886 {
4887 /* Prevent unused argument(s) compilation warning */
4888 UNUSED(hi2c);
4889
4890 /* NOTE : This function should not be modified, when the callback is needed,
4891 the HAL_I2C_AbortCpltCallback could be implemented in the user file
4892 */
4893 }
4894
4895 /**
4896 * @}
4897 */
4898
4899 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
4900 * @brief Peripheral State, Mode and Error functions
4901 *
4902 @verbatim
4903 ===============================================================================
4904 ##### Peripheral State, Mode and Error functions #####
4905 ===============================================================================
4906 [..]
4907 This subsection permit to get in run-time the status of the peripheral
4908 and the data flow.
4909
4910 @endverbatim
4911 * @{
4912 */
4913
4914 /**
4915 * @brief Return the I2C handle state.
4916 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4917 * the configuration information for the specified I2C.
4918 * @retval HAL state
4919 */
HAL_I2C_GetState(const I2C_HandleTypeDef * hi2c)4920 HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
4921 {
4922 /* Return I2C handle state */
4923 return hi2c->State;
4924 }
4925
4926 /**
4927 * @brief Returns the I2C Master, Slave, Memory or no mode.
4928 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4929 * the configuration information for I2C module
4930 * @retval HAL mode
4931 */
HAL_I2C_GetMode(const I2C_HandleTypeDef * hi2c)4932 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
4933 {
4934 return hi2c->Mode;
4935 }
4936
4937 /**
4938 * @brief Return the I2C error code.
4939 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4940 * the configuration information for the specified I2C.
4941 * @retval I2C Error Code
4942 */
HAL_I2C_GetError(const I2C_HandleTypeDef * hi2c)4943 uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
4944 {
4945 return hi2c->ErrorCode;
4946 }
4947
4948 /**
4949 * @}
4950 */
4951
4952 /**
4953 * @}
4954 */
4955
4956 /** @addtogroup I2C_Private_Functions
4957 * @{
4958 */
4959
4960 /**
4961 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
4962 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4963 * the configuration information for the specified I2C.
4964 * @param ITFlags Interrupt flags to handle.
4965 * @param ITSources Interrupt sources enabled.
4966 * @retval HAL status
4967 */
I2C_Master_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)4968 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
4969 uint32_t ITSources)
4970 {
4971 uint16_t devaddress;
4972 uint32_t tmpITFlags = ITFlags;
4973
4974 /* Process Locked */
4975 __HAL_LOCK(hi2c);
4976
4977 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
4978 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
4979 {
4980 /* Clear NACK Flag */
4981 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4982
4983 /* Set corresponding Error Code */
4984 /* No need to generate STOP, it is automatically done */
4985 /* Error callback will be send during stop flag treatment */
4986 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4987
4988 /* Flush TX register */
4989 I2C_Flush_TXDR(hi2c);
4990 }
4991 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
4992 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
4993 {
4994 /* Remove RXNE flag on temporary variable as read done */
4995 tmpITFlags &= ~I2C_FLAG_RXNE;
4996
4997 /* Read data from RXDR */
4998 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
4999
5000 /* Increment Buffer pointer */
5001 hi2c->pBuffPtr++;
5002
5003 hi2c->XferSize--;
5004 hi2c->XferCount--;
5005 }
5006 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \
5007 ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5008 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)))
5009 {
5010 /* Write data to TXDR */
5011 if (hi2c->XferCount != 0U)
5012 {
5013 /* Write data to TXDR */
5014 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5015
5016 /* Increment Buffer pointer */
5017 hi2c->pBuffPtr++;
5018
5019 hi2c->XferSize--;
5020 hi2c->XferCount--;
5021 }
5022 }
5023 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5024 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5025 {
5026 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5027 {
5028 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5029
5030 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5031 {
5032 hi2c->XferSize = MAX_NBYTE_SIZE;
5033 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5034 }
5035 else
5036 {
5037 hi2c->XferSize = hi2c->XferCount;
5038 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5039 {
5040 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5041 hi2c->XferOptions, I2C_NO_STARTSTOP);
5042 }
5043 else
5044 {
5045 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5046 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5047 }
5048 }
5049 }
5050 else
5051 {
5052 /* Call TxCpltCallback() if no stop mode is set */
5053 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5054 {
5055 /* Call I2C Master Sequential complete process */
5056 I2C_ITMasterSeqCplt(hi2c);
5057 }
5058 else
5059 {
5060 /* Wrong size Status regarding TCR flag event */
5061 /* Call the corresponding callback to inform upper layer of End of Transfer */
5062 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5063 }
5064 }
5065 }
5066 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5067 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5068 {
5069 if (hi2c->XferCount == 0U)
5070 {
5071 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5072 {
5073 /* Generate a stop condition in case of no transfer option */
5074 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5075 {
5076 /* Generate Stop */
5077 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5078 }
5079 else
5080 {
5081 /* Call I2C Master Sequential complete process */
5082 I2C_ITMasterSeqCplt(hi2c);
5083 }
5084 }
5085 }
5086 else
5087 {
5088 /* Wrong size Status regarding TC flag event */
5089 /* Call the corresponding callback to inform upper layer of End of Transfer */
5090 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5091 }
5092 }
5093 else
5094 {
5095 /* Nothing to do */
5096 }
5097
5098 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5099 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5100 {
5101 /* Call I2C Master complete process */
5102 I2C_ITMasterCplt(hi2c, tmpITFlags);
5103 }
5104
5105 /* Process Unlocked */
5106 __HAL_UNLOCK(hi2c);
5107
5108 return HAL_OK;
5109 }
5110
5111 /**
5112 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
5113 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5114 * the configuration information for the specified I2C.
5115 * @param ITFlags Interrupt flags to handle.
5116 * @param ITSources Interrupt sources enabled.
5117 * @retval HAL status
5118 */
I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5119 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5120 uint32_t ITSources)
5121 {
5122 uint32_t direction = I2C_GENERATE_START_WRITE;
5123 uint32_t tmpITFlags = ITFlags;
5124
5125 /* Process Locked */
5126 __HAL_LOCK(hi2c);
5127
5128 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5129 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5130 {
5131 /* Clear NACK Flag */
5132 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5133
5134 /* Set corresponding Error Code */
5135 /* No need to generate STOP, it is automatically done */
5136 /* Error callback will be send during stop flag treatment */
5137 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5138
5139 /* Flush TX register */
5140 I2C_Flush_TXDR(hi2c);
5141 }
5142 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5143 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5144 {
5145 /* Remove RXNE flag on temporary variable as read done */
5146 tmpITFlags &= ~I2C_FLAG_RXNE;
5147
5148 /* Read data from RXDR */
5149 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5150
5151 /* Increment Buffer pointer */
5152 hi2c->pBuffPtr++;
5153
5154 hi2c->XferSize--;
5155 hi2c->XferCount--;
5156 }
5157 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5158 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5159 {
5160 if (hi2c->Memaddress == 0xFFFFFFFFU)
5161 {
5162 /* Write data to TXDR */
5163 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5164
5165 /* Increment Buffer pointer */
5166 hi2c->pBuffPtr++;
5167
5168 hi2c->XferSize--;
5169 hi2c->XferCount--;
5170 }
5171 else
5172 {
5173 /* Write LSB part of Memory Address */
5174 hi2c->Instance->TXDR = hi2c->Memaddress;
5175
5176 /* Reset Memaddress content */
5177 hi2c->Memaddress = 0xFFFFFFFFU;
5178 }
5179 }
5180 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5181 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5182 {
5183 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5184 {
5185 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5186 {
5187 hi2c->XferSize = MAX_NBYTE_SIZE;
5188 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5189 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5190 }
5191 else
5192 {
5193 hi2c->XferSize = hi2c->XferCount;
5194 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5195 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5196 }
5197 }
5198 else
5199 {
5200 /* Wrong size Status regarding TCR flag event */
5201 /* Call the corresponding callback to inform upper layer of End of Transfer */
5202 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5203 }
5204 }
5205 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5206 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5207 {
5208 /* Disable Interrupt related to address step */
5209 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5210
5211 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
5212 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
5213
5214 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5215 {
5216 direction = I2C_GENERATE_START_READ;
5217 }
5218
5219 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5220 {
5221 hi2c->XferSize = MAX_NBYTE_SIZE;
5222
5223 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5224 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5225 I2C_RELOAD_MODE, direction);
5226 }
5227 else
5228 {
5229 hi2c->XferSize = hi2c->XferCount;
5230
5231 /* Set NBYTES to write and generate RESTART */
5232 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5233 I2C_AUTOEND_MODE, direction);
5234 }
5235 }
5236 else
5237 {
5238 /* Nothing to do */
5239 }
5240
5241 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5242 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5243 {
5244 /* Call I2C Master complete process */
5245 I2C_ITMasterCplt(hi2c, tmpITFlags);
5246 }
5247
5248 /* Process Unlocked */
5249 __HAL_UNLOCK(hi2c);
5250
5251 return HAL_OK;
5252 }
5253
5254 /**
5255 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
5256 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5257 * the configuration information for the specified I2C.
5258 * @param ITFlags Interrupt flags to handle.
5259 * @param ITSources Interrupt sources enabled.
5260 * @retval HAL status
5261 */
I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5262 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5263 uint32_t ITSources)
5264 {
5265 uint32_t tmpoptions = hi2c->XferOptions;
5266 uint32_t tmpITFlags = ITFlags;
5267
5268 /* Process locked */
5269 __HAL_LOCK(hi2c);
5270
5271 /* Check if STOPF is set */
5272 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5273 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5274 {
5275 /* Call I2C Slave complete process */
5276 I2C_ITSlaveCplt(hi2c, tmpITFlags);
5277 }
5278 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5279 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5280 {
5281 /* Check that I2C transfer finished */
5282 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5283 /* Mean XferCount == 0*/
5284 /* So clear Flag NACKF only */
5285 if (hi2c->XferCount == 0U)
5286 {
5287 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5288 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5289 Warning[Pa134]: left and right operands are identical */
5290 {
5291 /* Call I2C Listen complete process */
5292 I2C_ITListenCplt(hi2c, tmpITFlags);
5293 }
5294 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5295 {
5296 /* Clear NACK Flag */
5297 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5298
5299 /* Flush TX register */
5300 I2C_Flush_TXDR(hi2c);
5301
5302 /* Last Byte is Transmitted */
5303 /* Call I2C Slave Sequential complete process */
5304 I2C_ITSlaveSeqCplt(hi2c);
5305 }
5306 else
5307 {
5308 /* Clear NACK Flag */
5309 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5310 }
5311 }
5312 else
5313 {
5314 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5315 /* Clear NACK Flag */
5316 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5317
5318 /* Set ErrorCode corresponding to a Non-Acknowledge */
5319 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5320
5321 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5322 {
5323 /* Call the corresponding callback to inform upper layer of End of Transfer */
5324 I2C_ITError(hi2c, hi2c->ErrorCode);
5325 }
5326 }
5327 }
5328 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5329 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5330 {
5331 if (hi2c->XferCount > 0U)
5332 {
5333 /* Read data from RXDR */
5334 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5335
5336 /* Increment Buffer pointer */
5337 hi2c->pBuffPtr++;
5338
5339 hi2c->XferSize--;
5340 hi2c->XferCount--;
5341 }
5342
5343 if ((hi2c->XferCount == 0U) && \
5344 (tmpoptions != I2C_NO_OPTION_FRAME))
5345 {
5346 /* Call I2C Slave Sequential complete process */
5347 I2C_ITSlaveSeqCplt(hi2c);
5348 }
5349 }
5350 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
5351 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5352 {
5353 I2C_ITAddrCplt(hi2c, tmpITFlags);
5354 }
5355 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5356 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5357 {
5358 /* Write data to TXDR only if XferCount not reach "0" */
5359 /* A TXIS flag can be set, during STOP treatment */
5360 /* Check if all Data have already been sent */
5361 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
5362 if (hi2c->XferCount > 0U)
5363 {
5364 /* Write data to TXDR */
5365 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5366
5367 /* Increment Buffer pointer */
5368 hi2c->pBuffPtr++;
5369
5370 hi2c->XferCount--;
5371 hi2c->XferSize--;
5372 }
5373 else
5374 {
5375 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
5376 {
5377 /* Last Byte is Transmitted */
5378 /* Call I2C Slave Sequential complete process */
5379 I2C_ITSlaveSeqCplt(hi2c);
5380 }
5381 }
5382 }
5383 else
5384 {
5385 /* Nothing to do */
5386 }
5387
5388 /* Process Unlocked */
5389 __HAL_UNLOCK(hi2c);
5390
5391 return HAL_OK;
5392 }
5393
5394 /**
5395 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
5396 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5397 * the configuration information for the specified I2C.
5398 * @param ITFlags Interrupt flags to handle.
5399 * @param ITSources Interrupt sources enabled.
5400 * @retval HAL status
5401 */
I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5402 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5403 uint32_t ITSources)
5404 {
5405 uint16_t devaddress;
5406 uint32_t xfermode;
5407
5408 /* Process Locked */
5409 __HAL_LOCK(hi2c);
5410
5411 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5412 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5413 {
5414 /* Clear NACK Flag */
5415 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5416
5417 /* Set corresponding Error Code */
5418 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5419
5420 /* No need to generate STOP, it is automatically done */
5421 /* But enable STOP interrupt, to treat it */
5422 /* Error callback will be send during stop flag treatment */
5423 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5424
5425 /* Flush TX register */
5426 I2C_Flush_TXDR(hi2c);
5427 }
5428 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5429 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5430 {
5431 /* Disable TC interrupt */
5432 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
5433
5434 if (hi2c->XferCount != 0U)
5435 {
5436 /* Recover Slave address */
5437 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5438
5439 /* Prepare the new XferSize to transfer */
5440 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5441 {
5442 hi2c->XferSize = MAX_NBYTE_SIZE;
5443 xfermode = I2C_RELOAD_MODE;
5444 }
5445 else
5446 {
5447 hi2c->XferSize = hi2c->XferCount;
5448 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5449 {
5450 xfermode = hi2c->XferOptions;
5451 }
5452 else
5453 {
5454 xfermode = I2C_AUTOEND_MODE;
5455 }
5456 }
5457
5458 /* Set the new XferSize in Nbytes register */
5459 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
5460
5461 /* Update XferCount value */
5462 hi2c->XferCount -= hi2c->XferSize;
5463
5464 /* Enable DMA Request */
5465 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5466 {
5467 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5468 }
5469 else
5470 {
5471 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5472 }
5473 }
5474 else
5475 {
5476 /* Call TxCpltCallback() if no stop mode is set */
5477 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5478 {
5479 /* Call I2C Master Sequential complete process */
5480 I2C_ITMasterSeqCplt(hi2c);
5481 }
5482 else
5483 {
5484 /* Wrong size Status regarding TCR flag event */
5485 /* Call the corresponding callback to inform upper layer of End of Transfer */
5486 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5487 }
5488 }
5489 }
5490 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5491 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5492 {
5493 if (hi2c->XferCount == 0U)
5494 {
5495 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5496 {
5497 /* Generate a stop condition in case of no transfer option */
5498 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5499 {
5500 /* Generate Stop */
5501 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5502 }
5503 else
5504 {
5505 /* Call I2C Master Sequential complete process */
5506 I2C_ITMasterSeqCplt(hi2c);
5507 }
5508 }
5509 }
5510 else
5511 {
5512 /* Wrong size Status regarding TC flag event */
5513 /* Call the corresponding callback to inform upper layer of End of Transfer */
5514 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5515 }
5516 }
5517 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5518 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5519 {
5520 /* Call I2C Master complete process */
5521 I2C_ITMasterCplt(hi2c, ITFlags);
5522 }
5523 else
5524 {
5525 /* Nothing to do */
5526 }
5527
5528 /* Process Unlocked */
5529 __HAL_UNLOCK(hi2c);
5530
5531 return HAL_OK;
5532 }
5533
5534 /**
5535 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
5536 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5537 * the configuration information for the specified I2C.
5538 * @param ITFlags Interrupt flags to handle.
5539 * @param ITSources Interrupt sources enabled.
5540 * @retval HAL status
5541 */
I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5542 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5543 uint32_t ITSources)
5544 {
5545 uint32_t direction = I2C_GENERATE_START_WRITE;
5546
5547 /* Process Locked */
5548 __HAL_LOCK(hi2c);
5549
5550 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5551 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5552 {
5553 /* Clear NACK Flag */
5554 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5555
5556 /* Set corresponding Error Code */
5557 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5558
5559 /* No need to generate STOP, it is automatically done */
5560 /* But enable STOP interrupt, to treat it */
5561 /* Error callback will be send during stop flag treatment */
5562 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5563
5564 /* Flush TX register */
5565 I2C_Flush_TXDR(hi2c);
5566 }
5567 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
5568 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5569 {
5570 /* Write LSB part of Memory Address */
5571 hi2c->Instance->TXDR = hi2c->Memaddress;
5572
5573 /* Reset Memaddress content */
5574 hi2c->Memaddress = 0xFFFFFFFFU;
5575 }
5576 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5577 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5578 {
5579 /* Disable Interrupt related to address step */
5580 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5581
5582 /* Enable only Error interrupt */
5583 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5584
5585 if (hi2c->XferCount != 0U)
5586 {
5587 /* Prepare the new XferSize to transfer */
5588 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5589 {
5590 hi2c->XferSize = MAX_NBYTE_SIZE;
5591 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5592 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5593 }
5594 else
5595 {
5596 hi2c->XferSize = hi2c->XferCount;
5597 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5598 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5599 }
5600
5601 /* Update XferCount value */
5602 hi2c->XferCount -= hi2c->XferSize;
5603
5604 /* Enable DMA Request */
5605 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5606 {
5607 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5608 }
5609 else
5610 {
5611 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5612 }
5613 }
5614 else
5615 {
5616 /* Wrong size Status regarding TCR flag event */
5617 /* Call the corresponding callback to inform upper layer of End of Transfer */
5618 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5619 }
5620 }
5621 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5622 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5623 {
5624 /* Disable Interrupt related to address step */
5625 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5626
5627 /* Enable only Error and NACK interrupt for data transfer */
5628 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5629
5630 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5631 {
5632 direction = I2C_GENERATE_START_READ;
5633 }
5634
5635 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5636 {
5637 hi2c->XferSize = MAX_NBYTE_SIZE;
5638
5639 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5640 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5641 I2C_RELOAD_MODE, direction);
5642 }
5643 else
5644 {
5645 hi2c->XferSize = hi2c->XferCount;
5646
5647 /* Set NBYTES to write and generate RESTART */
5648 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5649 I2C_AUTOEND_MODE, direction);
5650 }
5651
5652 /* Update XferCount value */
5653 hi2c->XferCount -= hi2c->XferSize;
5654
5655 /* Enable DMA Request */
5656 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5657 {
5658 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5659 }
5660 else
5661 {
5662 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5663 }
5664 }
5665 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5666 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5667 {
5668 /* Call I2C Master complete process */
5669 I2C_ITMasterCplt(hi2c, ITFlags);
5670 }
5671 else
5672 {
5673 /* Nothing to do */
5674 }
5675
5676 /* Process Unlocked */
5677 __HAL_UNLOCK(hi2c);
5678
5679 return HAL_OK;
5680 }
5681
5682 /**
5683 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
5684 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5685 * the configuration information for the specified I2C.
5686 * @param ITFlags Interrupt flags to handle.
5687 * @param ITSources Interrupt sources enabled.
5688 * @retval HAL status
5689 */
I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5690 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5691 uint32_t ITSources)
5692 {
5693 uint32_t tmpoptions = hi2c->XferOptions;
5694 uint32_t treatdmanack = 0U;
5695 HAL_I2C_StateTypeDef tmpstate;
5696
5697 /* Process locked */
5698 __HAL_LOCK(hi2c);
5699
5700 /* Check if STOPF is set */
5701 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5702 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5703 {
5704 /* Call I2C Slave complete process */
5705 I2C_ITSlaveCplt(hi2c, ITFlags);
5706 }
5707 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5708 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5709 {
5710 /* Check that I2C transfer finished */
5711 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5712 /* Mean XferCount == 0 */
5713 /* So clear Flag NACKF only */
5714 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
5715 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
5716 {
5717 /* Split check of hdmarx, for MISRA compliance */
5718 if (hi2c->hdmarx != NULL)
5719 {
5720 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5721 {
5722 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
5723 {
5724 treatdmanack = 1U;
5725 }
5726 }
5727 }
5728
5729 /* Split check of hdmatx, for MISRA compliance */
5730 if (hi2c->hdmatx != NULL)
5731 {
5732 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5733 {
5734 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
5735 {
5736 treatdmanack = 1U;
5737 }
5738 }
5739 }
5740
5741 if (treatdmanack == 1U)
5742 {
5743 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5744 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5745 Warning[Pa134]: left and right operands are identical */
5746 {
5747 /* Call I2C Listen complete process */
5748 I2C_ITListenCplt(hi2c, ITFlags);
5749 }
5750 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5751 {
5752 /* Clear NACK Flag */
5753 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5754
5755 /* Flush TX register */
5756 I2C_Flush_TXDR(hi2c);
5757
5758 /* Last Byte is Transmitted */
5759 /* Call I2C Slave Sequential complete process */
5760 I2C_ITSlaveSeqCplt(hi2c);
5761 }
5762 else
5763 {
5764 /* Clear NACK Flag */
5765 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5766 }
5767 }
5768 else
5769 {
5770 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5771 /* Clear NACK Flag */
5772 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5773
5774 /* Set ErrorCode corresponding to a Non-Acknowledge */
5775 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5776
5777 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
5778 tmpstate = hi2c->State;
5779
5780 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5781 {
5782 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
5783 {
5784 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5785 }
5786 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
5787 {
5788 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5789 }
5790 else
5791 {
5792 /* Do nothing */
5793 }
5794
5795 /* Call the corresponding callback to inform upper layer of End of Transfer */
5796 I2C_ITError(hi2c, hi2c->ErrorCode);
5797 }
5798 }
5799 }
5800 else
5801 {
5802 /* Only Clear NACK Flag, no DMA treatment is pending */
5803 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5804 }
5805 }
5806 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
5807 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5808 {
5809 I2C_ITAddrCplt(hi2c, ITFlags);
5810 }
5811 else
5812 {
5813 /* Nothing to do */
5814 }
5815
5816 /* Process Unlocked */
5817 __HAL_UNLOCK(hi2c);
5818
5819 return HAL_OK;
5820 }
5821
5822 /**
5823 * @brief Master sends target device address followed by internal memory address for write request.
5824 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5825 * the configuration information for the specified I2C.
5826 * @param DevAddress Target device address: The device 7 bits address value
5827 * in datasheet must be shifted to the left before calling the interface
5828 * @param MemAddress Internal memory address
5829 * @param MemAddSize Size of internal memory address
5830 * @param Timeout Timeout duration
5831 * @param Tickstart Tick start value
5832 * @retval HAL status
5833 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5834 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5835 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5836 uint32_t Tickstart)
5837 {
5838 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
5839
5840 /* Wait until TXIS flag is set */
5841 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5842 {
5843 return HAL_ERROR;
5844 }
5845
5846 /* If Memory address size is 8Bit */
5847 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5848 {
5849 /* Send Memory Address */
5850 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5851 }
5852 /* If Memory address size is 16Bit */
5853 else
5854 {
5855 /* Send MSB of Memory Address */
5856 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5857
5858 /* Wait until TXIS flag is set */
5859 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5860 {
5861 return HAL_ERROR;
5862 }
5863
5864 /* Send LSB of Memory Address */
5865 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5866 }
5867
5868 /* Wait until TCR flag is set */
5869 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
5870 {
5871 return HAL_ERROR;
5872 }
5873
5874 return HAL_OK;
5875 }
5876
5877 /**
5878 * @brief Master sends target device address followed by internal memory address for read request.
5879 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5880 * the configuration information for the specified I2C.
5881 * @param DevAddress Target device address: The device 7 bits address value
5882 * in datasheet must be shifted to the left before calling the interface
5883 * @param MemAddress Internal memory address
5884 * @param MemAddSize Size of internal memory address
5885 * @param Timeout Timeout duration
5886 * @param Tickstart Tick start value
5887 * @retval HAL status
5888 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5889 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5890 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5891 uint32_t Tickstart)
5892 {
5893 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
5894
5895 /* Wait until TXIS flag is set */
5896 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5897 {
5898 return HAL_ERROR;
5899 }
5900
5901 /* If Memory address size is 8Bit */
5902 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5903 {
5904 /* Send Memory Address */
5905 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5906 }
5907 /* If Memory address size is 16Bit */
5908 else
5909 {
5910 /* Send MSB of Memory Address */
5911 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5912
5913 /* Wait until TXIS flag is set */
5914 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5915 {
5916 return HAL_ERROR;
5917 }
5918
5919 /* Send LSB of Memory Address */
5920 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5921 }
5922
5923 /* Wait until TC flag is set */
5924 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
5925 {
5926 return HAL_ERROR;
5927 }
5928
5929 return HAL_OK;
5930 }
5931
5932 /**
5933 * @brief I2C Address complete process callback.
5934 * @param hi2c I2C handle.
5935 * @param ITFlags Interrupt flags to handle.
5936 * @retval None
5937 */
I2C_ITAddrCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)5938 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5939 {
5940 uint8_t transferdirection;
5941 uint16_t slaveaddrcode;
5942 uint16_t ownadd1code;
5943 uint16_t ownadd2code;
5944
5945 /* Prevent unused argument(s) compilation warning */
5946 UNUSED(ITFlags);
5947
5948 /* In case of Listen state, need to inform upper layer of address match code event */
5949 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
5950 {
5951 transferdirection = I2C_GET_DIR(hi2c);
5952 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
5953 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
5954 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
5955
5956 /* If 10bits addressing mode is selected */
5957 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
5958 {
5959 if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
5960 {
5961 slaveaddrcode = ownadd1code;
5962 hi2c->AddrEventCount++;
5963 if (hi2c->AddrEventCount == 2U)
5964 {
5965 /* Reset Address Event counter */
5966 hi2c->AddrEventCount = 0U;
5967
5968 /* Clear ADDR flag */
5969 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5970
5971 /* Process Unlocked */
5972 __HAL_UNLOCK(hi2c);
5973
5974 /* Call Slave Addr callback */
5975 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5976 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5977 #else
5978 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5979 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5980 }
5981 }
5982 else
5983 {
5984 slaveaddrcode = ownadd2code;
5985
5986 /* Disable ADDR Interrupts */
5987 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5988
5989 /* Process Unlocked */
5990 __HAL_UNLOCK(hi2c);
5991
5992 /* Call Slave Addr callback */
5993 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5994 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5995 #else
5996 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5997 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5998 }
5999 }
6000 /* else 7 bits addressing mode is selected */
6001 else
6002 {
6003 /* Disable ADDR Interrupts */
6004 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
6005
6006 /* Process Unlocked */
6007 __HAL_UNLOCK(hi2c);
6008
6009 /* Call Slave Addr callback */
6010 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6011 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6012 #else
6013 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6014 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6015 }
6016 }
6017 /* Else clear address flag only */
6018 else
6019 {
6020 /* Clear ADDR flag */
6021 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
6022
6023 /* Process Unlocked */
6024 __HAL_UNLOCK(hi2c);
6025 }
6026 }
6027
6028 /**
6029 * @brief I2C Master sequential complete process.
6030 * @param hi2c I2C handle.
6031 * @retval None
6032 */
I2C_ITMasterSeqCplt(I2C_HandleTypeDef * hi2c)6033 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
6034 {
6035 /* Reset I2C handle mode */
6036 hi2c->Mode = HAL_I2C_MODE_NONE;
6037
6038 /* No Generate Stop, to permit restart mode */
6039 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
6040 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6041 {
6042 hi2c->State = HAL_I2C_STATE_READY;
6043 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6044 hi2c->XferISR = NULL;
6045
6046 /* Disable Interrupts */
6047 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6048
6049 /* Process Unlocked */
6050 __HAL_UNLOCK(hi2c);
6051
6052 /* Call the corresponding callback to inform upper layer of End of Transfer */
6053 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6054 hi2c->MasterTxCpltCallback(hi2c);
6055 #else
6056 HAL_I2C_MasterTxCpltCallback(hi2c);
6057 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6058 }
6059 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6060 else
6061 {
6062 hi2c->State = HAL_I2C_STATE_READY;
6063 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6064 hi2c->XferISR = NULL;
6065
6066 /* Disable Interrupts */
6067 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6068
6069 /* Process Unlocked */
6070 __HAL_UNLOCK(hi2c);
6071
6072 /* Call the corresponding callback to inform upper layer of End of Transfer */
6073 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6074 hi2c->MasterRxCpltCallback(hi2c);
6075 #else
6076 HAL_I2C_MasterRxCpltCallback(hi2c);
6077 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6078 }
6079 }
6080
6081 /**
6082 * @brief I2C Slave sequential complete process.
6083 * @param hi2c I2C handle.
6084 * @retval None
6085 */
I2C_ITSlaveSeqCplt(I2C_HandleTypeDef * hi2c)6086 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
6087 {
6088 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6089
6090 /* Reset I2C handle mode */
6091 hi2c->Mode = HAL_I2C_MODE_NONE;
6092
6093 /* If a DMA is ongoing, Update handle size context */
6094 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6095 {
6096 /* Disable DMA Request */
6097 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6098 }
6099 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6100 {
6101 /* Disable DMA Request */
6102 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6103 }
6104 else
6105 {
6106 /* Do nothing */
6107 }
6108
6109 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
6110 {
6111 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
6112 hi2c->State = HAL_I2C_STATE_LISTEN;
6113 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6114
6115 /* Disable Interrupts */
6116 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6117
6118 /* Process Unlocked */
6119 __HAL_UNLOCK(hi2c);
6120
6121 /* Call the corresponding callback to inform upper layer of End of Transfer */
6122 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6123 hi2c->SlaveTxCpltCallback(hi2c);
6124 #else
6125 HAL_I2C_SlaveTxCpltCallback(hi2c);
6126 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6127 }
6128
6129 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
6130 {
6131 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
6132 hi2c->State = HAL_I2C_STATE_LISTEN;
6133 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6134
6135 /* Disable Interrupts */
6136 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6137
6138 /* Process Unlocked */
6139 __HAL_UNLOCK(hi2c);
6140
6141 /* Call the corresponding callback to inform upper layer of End of Transfer */
6142 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6143 hi2c->SlaveRxCpltCallback(hi2c);
6144 #else
6145 HAL_I2C_SlaveRxCpltCallback(hi2c);
6146 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6147 }
6148 else
6149 {
6150 /* Nothing to do */
6151 }
6152 }
6153
6154 /**
6155 * @brief I2C Master complete process.
6156 * @param hi2c I2C handle.
6157 * @param ITFlags Interrupt flags to handle.
6158 * @retval None
6159 */
I2C_ITMasterCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6160 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6161 {
6162 uint32_t tmperror;
6163 uint32_t tmpITFlags = ITFlags;
6164 __IO uint32_t tmpreg;
6165
6166 /* Clear STOP Flag */
6167 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6168
6169 /* Disable Interrupts and Store Previous state */
6170 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6171 {
6172 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6173 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6174 }
6175 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6176 {
6177 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6178 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6179 }
6180 else
6181 {
6182 /* Do nothing */
6183 }
6184
6185 /* Clear Configuration Register 2 */
6186 I2C_RESET_CR2(hi2c);
6187
6188 /* Reset handle parameters */
6189 hi2c->XferISR = NULL;
6190 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6191
6192 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
6193 {
6194 /* Clear NACK Flag */
6195 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6196
6197 /* Set acknowledge error code */
6198 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6199 }
6200
6201 /* Fetch Last receive data if any */
6202 if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
6203 {
6204 /* Read data from RXDR */
6205 tmpreg = (uint8_t)hi2c->Instance->RXDR;
6206 UNUSED(tmpreg);
6207 }
6208
6209 /* Flush TX register */
6210 I2C_Flush_TXDR(hi2c);
6211
6212 /* Store current volatile hi2c->ErrorCode, misra rule */
6213 tmperror = hi2c->ErrorCode;
6214
6215 /* Call the corresponding callback to inform upper layer of End of Transfer */
6216 if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
6217 {
6218 /* Call the corresponding callback to inform upper layer of End of Transfer */
6219 I2C_ITError(hi2c, hi2c->ErrorCode);
6220 }
6221 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
6222 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6223 {
6224 hi2c->State = HAL_I2C_STATE_READY;
6225 hi2c->PreviousState = I2C_STATE_NONE;
6226
6227 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6228 {
6229 hi2c->Mode = HAL_I2C_MODE_NONE;
6230
6231 /* Process Unlocked */
6232 __HAL_UNLOCK(hi2c);
6233
6234 /* Call the corresponding callback to inform upper layer of End of Transfer */
6235 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6236 hi2c->MemTxCpltCallback(hi2c);
6237 #else
6238 HAL_I2C_MemTxCpltCallback(hi2c);
6239 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6240 }
6241 else
6242 {
6243 hi2c->Mode = HAL_I2C_MODE_NONE;
6244
6245 /* Process Unlocked */
6246 __HAL_UNLOCK(hi2c);
6247
6248 /* Call the corresponding callback to inform upper layer of End of Transfer */
6249 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6250 hi2c->MasterTxCpltCallback(hi2c);
6251 #else
6252 HAL_I2C_MasterTxCpltCallback(hi2c);
6253 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6254 }
6255 }
6256 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6257 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6258 {
6259 hi2c->State = HAL_I2C_STATE_READY;
6260 hi2c->PreviousState = I2C_STATE_NONE;
6261
6262 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6263 {
6264 hi2c->Mode = HAL_I2C_MODE_NONE;
6265
6266 /* Process Unlocked */
6267 __HAL_UNLOCK(hi2c);
6268
6269 /* Call the corresponding callback to inform upper layer of End of Transfer */
6270 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6271 hi2c->MemRxCpltCallback(hi2c);
6272 #else
6273 HAL_I2C_MemRxCpltCallback(hi2c);
6274 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6275 }
6276 else
6277 {
6278 hi2c->Mode = HAL_I2C_MODE_NONE;
6279
6280 /* Process Unlocked */
6281 __HAL_UNLOCK(hi2c);
6282
6283 /* Call the corresponding callback to inform upper layer of End of Transfer */
6284 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6285 hi2c->MasterRxCpltCallback(hi2c);
6286 #else
6287 HAL_I2C_MasterRxCpltCallback(hi2c);
6288 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6289 }
6290 }
6291 else
6292 {
6293 /* Nothing to do */
6294 }
6295 }
6296
6297 /**
6298 * @brief I2C Slave complete process.
6299 * @param hi2c I2C handle.
6300 * @param ITFlags Interrupt flags to handle.
6301 * @retval None
6302 */
I2C_ITSlaveCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6303 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6304 {
6305 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6306 uint32_t tmpITFlags = ITFlags;
6307 uint32_t tmpoptions = hi2c->XferOptions;
6308 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6309
6310 /* Clear STOP Flag */
6311 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6312
6313 /* Disable Interrupts and Store Previous state */
6314 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6315 {
6316 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
6317 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6318 }
6319 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6320 {
6321 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
6322 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6323 }
6324 else if (tmpstate == HAL_I2C_STATE_LISTEN)
6325 {
6326 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
6327 hi2c->PreviousState = I2C_STATE_NONE;
6328 }
6329 else
6330 {
6331 /* Do nothing */
6332 }
6333
6334 /* Disable Address Acknowledge */
6335 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6336
6337 /* Clear Configuration Register 2 */
6338 I2C_RESET_CR2(hi2c);
6339
6340 /* Flush TX register */
6341 I2C_Flush_TXDR(hi2c);
6342
6343 /* If a DMA is ongoing, Update handle size context */
6344 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6345 {
6346 /* Disable DMA Request */
6347 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6348
6349 if (hi2c->hdmatx != NULL)
6350 {
6351 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
6352 }
6353 }
6354 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6355 {
6356 /* Disable DMA Request */
6357 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6358
6359 if (hi2c->hdmarx != NULL)
6360 {
6361 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
6362 }
6363 }
6364 else
6365 {
6366 /* Do nothing */
6367 }
6368
6369 /* Store Last receive data if any */
6370 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
6371 {
6372 /* Remove RXNE flag on temporary variable as read done */
6373 tmpITFlags &= ~I2C_FLAG_RXNE;
6374
6375 /* Read data from RXDR */
6376 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6377
6378 /* Increment Buffer pointer */
6379 hi2c->pBuffPtr++;
6380
6381 if ((hi2c->XferSize > 0U))
6382 {
6383 hi2c->XferSize--;
6384 hi2c->XferCount--;
6385 }
6386 }
6387
6388 /* All data are not transferred, so set error code accordingly */
6389 if (hi2c->XferCount != 0U)
6390 {
6391 /* Set ErrorCode corresponding to a Non-Acknowledge */
6392 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6393 }
6394
6395 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
6396 (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
6397 {
6398 /* Check that I2C transfer finished */
6399 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
6400 /* Mean XferCount == 0*/
6401 /* So clear Flag NACKF only */
6402 if (hi2c->XferCount == 0U)
6403 {
6404 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
6405 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
6406 Warning[Pa134]: left and right operands are identical */
6407 {
6408 /* Call I2C Listen complete process */
6409 I2C_ITListenCplt(hi2c, tmpITFlags);
6410 }
6411 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
6412 {
6413 /* Clear NACK Flag */
6414 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6415
6416 /* Flush TX register */
6417 I2C_Flush_TXDR(hi2c);
6418
6419 /* Last Byte is Transmitted */
6420 /* Call I2C Slave Sequential complete process */
6421 I2C_ITSlaveSeqCplt(hi2c);
6422 }
6423 else
6424 {
6425 /* Clear NACK Flag */
6426 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6427 }
6428 }
6429 else
6430 {
6431 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
6432 /* Clear NACK Flag */
6433 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6434
6435 /* Set ErrorCode corresponding to a Non-Acknowledge */
6436 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6437
6438 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
6439 {
6440 /* Call the corresponding callback to inform upper layer of End of Transfer */
6441 I2C_ITError(hi2c, hi2c->ErrorCode);
6442 }
6443 }
6444 }
6445
6446 hi2c->Mode = HAL_I2C_MODE_NONE;
6447 hi2c->XferISR = NULL;
6448
6449 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6450 {
6451 /* Call the corresponding callback to inform upper layer of End of Transfer */
6452 I2C_ITError(hi2c, hi2c->ErrorCode);
6453
6454 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6455 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6456 {
6457 /* Call I2C Listen complete process */
6458 I2C_ITListenCplt(hi2c, tmpITFlags);
6459 }
6460 }
6461 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
6462 {
6463 /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
6464 I2C_ITSlaveSeqCplt(hi2c);
6465
6466 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6467 hi2c->State = HAL_I2C_STATE_READY;
6468 hi2c->PreviousState = I2C_STATE_NONE;
6469
6470 /* Process Unlocked */
6471 __HAL_UNLOCK(hi2c);
6472
6473 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6474 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6475 hi2c->ListenCpltCallback(hi2c);
6476 #else
6477 HAL_I2C_ListenCpltCallback(hi2c);
6478 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6479 }
6480 /* Call the corresponding callback to inform upper layer of End of Transfer */
6481 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6482 {
6483 hi2c->State = HAL_I2C_STATE_READY;
6484 hi2c->PreviousState = I2C_STATE_NONE;
6485
6486 /* Process Unlocked */
6487 __HAL_UNLOCK(hi2c);
6488
6489 /* Call the corresponding callback to inform upper layer of End of Transfer */
6490 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6491 hi2c->SlaveRxCpltCallback(hi2c);
6492 #else
6493 HAL_I2C_SlaveRxCpltCallback(hi2c);
6494 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6495 }
6496 else
6497 {
6498 hi2c->State = HAL_I2C_STATE_READY;
6499 hi2c->PreviousState = I2C_STATE_NONE;
6500
6501 /* Process Unlocked */
6502 __HAL_UNLOCK(hi2c);
6503
6504 /* Call the corresponding callback to inform upper layer of End of Transfer */
6505 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6506 hi2c->SlaveTxCpltCallback(hi2c);
6507 #else
6508 HAL_I2C_SlaveTxCpltCallback(hi2c);
6509 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6510 }
6511 }
6512
6513 /**
6514 * @brief I2C Listen complete process.
6515 * @param hi2c I2C handle.
6516 * @param ITFlags Interrupt flags to handle.
6517 * @retval None
6518 */
I2C_ITListenCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6519 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6520 {
6521 /* Reset handle parameters */
6522 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6523 hi2c->PreviousState = I2C_STATE_NONE;
6524 hi2c->State = HAL_I2C_STATE_READY;
6525 hi2c->Mode = HAL_I2C_MODE_NONE;
6526 hi2c->XferISR = NULL;
6527
6528 /* Store Last receive data if any */
6529 if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
6530 {
6531 /* Read data from RXDR */
6532 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6533
6534 /* Increment Buffer pointer */
6535 hi2c->pBuffPtr++;
6536
6537 if ((hi2c->XferSize > 0U))
6538 {
6539 hi2c->XferSize--;
6540 hi2c->XferCount--;
6541
6542 /* Set ErrorCode corresponding to a Non-Acknowledge */
6543 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6544 }
6545 }
6546
6547 /* Disable all Interrupts*/
6548 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6549
6550 /* Clear NACK Flag */
6551 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6552
6553 /* Process Unlocked */
6554 __HAL_UNLOCK(hi2c);
6555
6556 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6557 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6558 hi2c->ListenCpltCallback(hi2c);
6559 #else
6560 HAL_I2C_ListenCpltCallback(hi2c);
6561 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6562 }
6563
6564 /**
6565 * @brief I2C interrupts error process.
6566 * @param hi2c I2C handle.
6567 * @param ErrorCode Error code to handle.
6568 * @retval None
6569 */
I2C_ITError(I2C_HandleTypeDef * hi2c,uint32_t ErrorCode)6570 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
6571 {
6572 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6573
6574 uint32_t tmppreviousstate;
6575
6576 /* Reset handle parameters */
6577 hi2c->Mode = HAL_I2C_MODE_NONE;
6578 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6579 hi2c->XferCount = 0U;
6580
6581 /* Set new error code */
6582 hi2c->ErrorCode |= ErrorCode;
6583
6584 /* Disable Interrupts */
6585 if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
6586 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
6587 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6588 {
6589 /* Disable all interrupts, except interrupts related to LISTEN state */
6590 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6591
6592 /* keep HAL_I2C_STATE_LISTEN if set */
6593 hi2c->State = HAL_I2C_STATE_LISTEN;
6594 hi2c->XferISR = I2C_Slave_ISR_IT;
6595 }
6596 else
6597 {
6598 /* Disable all interrupts */
6599 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6600
6601 /* Flush TX register */
6602 I2C_Flush_TXDR(hi2c);
6603
6604 /* If state is an abort treatment on going, don't change state */
6605 /* This change will be do later */
6606 if (hi2c->State != HAL_I2C_STATE_ABORT)
6607 {
6608 /* Set HAL_I2C_STATE_READY */
6609 hi2c->State = HAL_I2C_STATE_READY;
6610
6611 /* Check if a STOPF is detected */
6612 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6613 {
6614 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6615 {
6616 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6617 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6618 }
6619
6620 /* Clear STOP Flag */
6621 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6622 }
6623
6624 }
6625 hi2c->XferISR = NULL;
6626 }
6627
6628 /* Abort DMA TX transfer if any */
6629 tmppreviousstate = hi2c->PreviousState;
6630
6631 if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
6632 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
6633 {
6634 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
6635 {
6636 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6637 }
6638
6639 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6640 {
6641 /* Set the I2C DMA Abort callback :
6642 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6643 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6644
6645 /* Process Unlocked */
6646 __HAL_UNLOCK(hi2c);
6647
6648 /* Abort DMA TX */
6649 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6650 {
6651 /* Call Directly XferAbortCallback function in case of error */
6652 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6653 }
6654 }
6655 else
6656 {
6657 I2C_TreatErrorCallback(hi2c);
6658 }
6659 }
6660 /* Abort DMA RX transfer if any */
6661 else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
6662 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
6663 {
6664 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
6665 {
6666 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6667 }
6668
6669 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6670 {
6671 /* Set the I2C DMA Abort callback :
6672 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6673 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6674
6675 /* Process Unlocked */
6676 __HAL_UNLOCK(hi2c);
6677
6678 /* Abort DMA RX */
6679 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6680 {
6681 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6682 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6683 }
6684 }
6685 else
6686 {
6687 I2C_TreatErrorCallback(hi2c);
6688 }
6689 }
6690 else
6691 {
6692 I2C_TreatErrorCallback(hi2c);
6693 }
6694 }
6695
6696 /**
6697 * @brief I2C Error callback treatment.
6698 * @param hi2c I2C handle.
6699 * @retval None
6700 */
I2C_TreatErrorCallback(I2C_HandleTypeDef * hi2c)6701 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
6702 {
6703 if (hi2c->State == HAL_I2C_STATE_ABORT)
6704 {
6705 hi2c->State = HAL_I2C_STATE_READY;
6706 hi2c->PreviousState = I2C_STATE_NONE;
6707
6708 /* Process Unlocked */
6709 __HAL_UNLOCK(hi2c);
6710
6711 /* Call the corresponding callback to inform upper layer of End of Transfer */
6712 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6713 hi2c->AbortCpltCallback(hi2c);
6714 #else
6715 HAL_I2C_AbortCpltCallback(hi2c);
6716 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6717 }
6718 else
6719 {
6720 hi2c->PreviousState = I2C_STATE_NONE;
6721
6722 /* Process Unlocked */
6723 __HAL_UNLOCK(hi2c);
6724
6725 /* Call the corresponding callback to inform upper layer of End of Transfer */
6726 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6727 hi2c->ErrorCallback(hi2c);
6728 #else
6729 HAL_I2C_ErrorCallback(hi2c);
6730 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6731 }
6732 }
6733
6734 /**
6735 * @brief I2C Tx data register flush process.
6736 * @param hi2c I2C handle.
6737 * @retval None
6738 */
I2C_Flush_TXDR(I2C_HandleTypeDef * hi2c)6739 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
6740 {
6741 /* If a pending TXIS flag is set */
6742 /* Write a dummy data in TXDR to clear it */
6743 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
6744 {
6745 hi2c->Instance->TXDR = 0x00U;
6746 }
6747
6748 /* Flush TX register if not empty */
6749 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
6750 {
6751 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
6752 }
6753 }
6754
6755 /**
6756 * @brief DMA I2C master transmit process complete callback.
6757 * @param hdma DMA handle
6758 * @retval None
6759 */
I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef * hdma)6760 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
6761 {
6762 /* Derogation MISRAC2012-Rule-11.5 */
6763 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6764
6765 /* Disable DMA Request */
6766 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6767
6768 /* If last transfer, enable STOP interrupt */
6769 if (hi2c->XferCount == 0U)
6770 {
6771 /* Enable STOP interrupt */
6772 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6773 }
6774 /* else prepare a new DMA transfer and enable TCReload interrupt */
6775 else
6776 {
6777 /* Update Buffer pointer */
6778 hi2c->pBuffPtr += hi2c->XferSize;
6779
6780 /* Set the XferSize to transfer */
6781 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6782 {
6783 hi2c->XferSize = MAX_NBYTE_SIZE;
6784 }
6785 else
6786 {
6787 hi2c->XferSize = hi2c->XferCount;
6788 }
6789
6790 /* Enable the DMA stream or channel depends on Instance */
6791 if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
6792 hi2c->XferSize) != HAL_OK)
6793 {
6794 /* Call the corresponding callback to inform upper layer of End of Transfer */
6795 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6796 }
6797 else
6798 {
6799 /* Enable TC interrupts */
6800 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6801 }
6802 }
6803 }
6804
6805
6806 /**
6807 * @brief DMA I2C slave transmit process complete callback.
6808 * @param hdma DMA handle
6809 * @retval None
6810 */
I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef * hdma)6811 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
6812 {
6813 /* Derogation MISRAC2012-Rule-11.5 */
6814 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6815 uint32_t tmpoptions = hi2c->XferOptions;
6816
6817 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
6818 {
6819 /* Disable DMA Request */
6820 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6821
6822 /* Last Byte is Transmitted */
6823 /* Call I2C Slave Sequential complete process */
6824 I2C_ITSlaveSeqCplt(hi2c);
6825 }
6826 else
6827 {
6828 /* No specific action, Master fully manage the generation of STOP condition */
6829 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6830 /* So STOP condition should be manage through Interrupt treatment */
6831 }
6832 }
6833
6834
6835 /**
6836 * @brief DMA I2C master receive process complete callback.
6837 * @param hdma DMA handle
6838 * @retval None
6839 */
I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef * hdma)6840 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
6841 {
6842 /* Derogation MISRAC2012-Rule-11.5 */
6843 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6844
6845 /* Disable DMA Request */
6846 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6847
6848 /* If last transfer, enable STOP interrupt */
6849 if (hi2c->XferCount == 0U)
6850 {
6851 /* Enable STOP interrupt */
6852 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6853 }
6854 /* else prepare a new DMA transfer and enable TCReload interrupt */
6855 else
6856 {
6857 /* Update Buffer pointer */
6858 hi2c->pBuffPtr += hi2c->XferSize;
6859
6860 /* Set the XferSize to transfer */
6861 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6862 {
6863 hi2c->XferSize = MAX_NBYTE_SIZE;
6864 }
6865 else
6866 {
6867 hi2c->XferSize = hi2c->XferCount;
6868 }
6869
6870 /* Enable the DMA stream or channel depends on Instance */
6871 if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
6872 hi2c->XferSize) != HAL_OK)
6873 {
6874 /* Call the corresponding callback to inform upper layer of End of Transfer */
6875 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6876 }
6877 else
6878 {
6879 /* Enable TC interrupts */
6880 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6881 }
6882 }
6883 }
6884
6885
6886 /**
6887 * @brief DMA I2C slave receive process complete callback.
6888 * @param hdma DMA handle
6889 * @retval None
6890 */
I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef * hdma)6891 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
6892 {
6893 /* Derogation MISRAC2012-Rule-11.5 */
6894 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6895 uint32_t tmpoptions = hi2c->XferOptions;
6896
6897 if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
6898 (tmpoptions != I2C_NO_OPTION_FRAME))
6899 {
6900 /* Disable DMA Request */
6901 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6902
6903 /* Call I2C Slave Sequential complete process */
6904 I2C_ITSlaveSeqCplt(hi2c);
6905 }
6906 else
6907 {
6908 /* No specific action, Master fully manage the generation of STOP condition */
6909 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6910 /* So STOP condition should be manage through Interrupt treatment */
6911 }
6912 }
6913
6914
6915 /**
6916 * @brief DMA I2C communication error callback.
6917 * @param hdma DMA handle
6918 * @retval None
6919 */
I2C_DMAError(DMA_HandleTypeDef * hdma)6920 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
6921 {
6922 uint32_t treatdmaerror = 0U;
6923 /* Derogation MISRAC2012-Rule-11.5 */
6924 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6925
6926 if (hi2c->hdmatx != NULL)
6927 {
6928 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
6929 {
6930 treatdmaerror = 1U;
6931 }
6932 }
6933
6934 if (hi2c->hdmarx != NULL)
6935 {
6936 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
6937 {
6938 treatdmaerror = 1U;
6939 }
6940 }
6941
6942 /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */
6943 if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U))
6944 {
6945 /* Disable Acknowledge */
6946 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6947
6948 /* Call the corresponding callback to inform upper layer of End of Transfer */
6949 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6950 }
6951 }
6952
6953
6954 /**
6955 * @brief DMA I2C communication abort callback
6956 * (To be called at end of DMA Abort procedure).
6957 * @param hdma DMA handle.
6958 * @retval None
6959 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)6960 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
6961 {
6962 /* Derogation MISRAC2012-Rule-11.5 */
6963 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6964
6965 /* Reset AbortCpltCallback */
6966 if (hi2c->hdmatx != NULL)
6967 {
6968 hi2c->hdmatx->XferAbortCallback = NULL;
6969 }
6970 if (hi2c->hdmarx != NULL)
6971 {
6972 hi2c->hdmarx->XferAbortCallback = NULL;
6973 }
6974
6975 I2C_TreatErrorCallback(hi2c);
6976 }
6977
6978
6979 /**
6980 * @brief This function handles I2C Communication Timeout. It waits
6981 * until a flag is no longer in the specified status.
6982 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6983 * the configuration information for the specified I2C.
6984 * @param Flag Specifies the I2C flag to check.
6985 * @param Status The actual Flag status (SET or RESET).
6986 * @param Timeout Timeout duration
6987 * @param Tickstart Tick start value
6988 * @retval HAL status
6989 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)6990 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
6991 uint32_t Timeout, uint32_t Tickstart)
6992 {
6993 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
6994 {
6995 /* Check if an error is detected */
6996 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6997 {
6998 return HAL_ERROR;
6999 }
7000
7001 /* Check for the Timeout */
7002 if (Timeout != HAL_MAX_DELAY)
7003 {
7004 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7005 {
7006 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
7007 {
7008 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7009 hi2c->State = HAL_I2C_STATE_READY;
7010 hi2c->Mode = HAL_I2C_MODE_NONE;
7011
7012 /* Process Unlocked */
7013 __HAL_UNLOCK(hi2c);
7014 return HAL_ERROR;
7015 }
7016 }
7017 }
7018 }
7019 return HAL_OK;
7020 }
7021
7022 /**
7023 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
7024 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7025 * the configuration information for the specified I2C.
7026 * @param Timeout Timeout duration
7027 * @param Tickstart Tick start value
7028 * @retval HAL status
7029 */
I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7030 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7031 uint32_t Tickstart)
7032 {
7033 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
7034 {
7035 /* Check if an error is detected */
7036 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7037 {
7038 return HAL_ERROR;
7039 }
7040
7041 /* Check for the Timeout */
7042 if (Timeout != HAL_MAX_DELAY)
7043 {
7044 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7045 {
7046 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
7047 {
7048 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7049 hi2c->State = HAL_I2C_STATE_READY;
7050 hi2c->Mode = HAL_I2C_MODE_NONE;
7051
7052 /* Process Unlocked */
7053 __HAL_UNLOCK(hi2c);
7054
7055 return HAL_ERROR;
7056 }
7057 }
7058 }
7059 }
7060 return HAL_OK;
7061 }
7062
7063 /**
7064 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
7065 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7066 * the configuration information for the specified I2C.
7067 * @param Timeout Timeout duration
7068 * @param Tickstart Tick start value
7069 * @retval HAL status
7070 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7071 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7072 uint32_t Tickstart)
7073 {
7074 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7075 {
7076 /* Check if an error is detected */
7077 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7078 {
7079 return HAL_ERROR;
7080 }
7081
7082 /* Check for the Timeout */
7083 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7084 {
7085 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
7086 {
7087 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7088 hi2c->State = HAL_I2C_STATE_READY;
7089 hi2c->Mode = HAL_I2C_MODE_NONE;
7090
7091 /* Process Unlocked */
7092 __HAL_UNLOCK(hi2c);
7093
7094 return HAL_ERROR;
7095 }
7096 }
7097 }
7098 return HAL_OK;
7099 }
7100
7101 /**
7102 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
7103 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7104 * the configuration information for the specified I2C.
7105 * @param Timeout Timeout duration
7106 * @param Tickstart Tick start value
7107 * @retval HAL status
7108 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7109 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7110 uint32_t Tickstart)
7111 {
7112 HAL_StatusTypeDef status = HAL_OK;
7113
7114 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
7115 {
7116 /* Check if an error is detected */
7117 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7118 {
7119 status = HAL_ERROR;
7120 }
7121
7122 /* Check if a STOPF is detected */
7123 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
7124 {
7125 /* Check if an RXNE is pending */
7126 /* Store Last receive data if any */
7127 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
7128 {
7129 /* Return HAL_OK */
7130 /* The Reading of data from RXDR will be done in caller function */
7131 status = HAL_OK;
7132 }
7133
7134 /* Check a no-acknowledge have been detected */
7135 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7136 {
7137 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7138 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
7139
7140 /* Clear STOP Flag */
7141 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7142
7143 /* Clear Configuration Register 2 */
7144 I2C_RESET_CR2(hi2c);
7145
7146 hi2c->State = HAL_I2C_STATE_READY;
7147 hi2c->Mode = HAL_I2C_MODE_NONE;
7148
7149 /* Process Unlocked */
7150 __HAL_UNLOCK(hi2c);
7151
7152 status = HAL_ERROR;
7153 }
7154 else
7155 {
7156 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
7157 }
7158 }
7159
7160 /* Check for the Timeout */
7161 if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
7162 {
7163 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
7164 {
7165 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7166 hi2c->State = HAL_I2C_STATE_READY;
7167
7168 /* Process Unlocked */
7169 __HAL_UNLOCK(hi2c);
7170
7171 status = HAL_ERROR;
7172 }
7173 }
7174 }
7175 return status;
7176 }
7177
7178 /**
7179 * @brief This function handles errors detection during an I2C Communication.
7180 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7181 * the configuration information for the specified I2C.
7182 * @param Timeout Timeout duration
7183 * @param Tickstart Tick start value
7184 * @retval HAL status
7185 */
I2C_IsErrorOccurred(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7186 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7187 {
7188 HAL_StatusTypeDef status = HAL_OK;
7189 uint32_t itflag = hi2c->Instance->ISR;
7190 uint32_t error_code = 0;
7191 uint32_t tickstart = Tickstart;
7192 uint32_t tmp1;
7193 HAL_I2C_ModeTypeDef tmp2;
7194
7195 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
7196 {
7197 /* Clear NACKF Flag */
7198 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7199
7200 /* Wait until STOP Flag is set or timeout occurred */
7201 /* AutoEnd should be initiate after AF */
7202 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
7203 {
7204 /* Check for the Timeout */
7205 if (Timeout != HAL_MAX_DELAY)
7206 {
7207 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7208 {
7209 tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
7210 tmp2 = hi2c->Mode;
7211
7212 /* In case of I2C still busy, try to regenerate a STOP manually */
7213 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
7214 (tmp1 != I2C_CR2_STOP) && \
7215 (tmp2 != HAL_I2C_MODE_SLAVE))
7216 {
7217 /* Generate Stop */
7218 hi2c->Instance->CR2 |= I2C_CR2_STOP;
7219
7220 /* Update Tick with new reference */
7221 tickstart = HAL_GetTick();
7222 }
7223
7224 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7225 {
7226 /* Check for the Timeout */
7227 if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
7228 {
7229 error_code |= HAL_I2C_ERROR_TIMEOUT;
7230
7231 status = HAL_ERROR;
7232
7233 break;
7234 }
7235 }
7236 }
7237 }
7238 }
7239
7240 /* In case STOP Flag is detected, clear it */
7241 if (status == HAL_OK)
7242 {
7243 /* Clear STOP Flag */
7244 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7245 }
7246
7247 error_code |= HAL_I2C_ERROR_AF;
7248
7249 status = HAL_ERROR;
7250 }
7251
7252 /* Refresh Content of Status register */
7253 itflag = hi2c->Instance->ISR;
7254
7255 /* Then verify if an additional errors occurs */
7256 /* Check if a Bus error occurred */
7257 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
7258 {
7259 error_code |= HAL_I2C_ERROR_BERR;
7260
7261 /* Clear BERR flag */
7262 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
7263
7264 status = HAL_ERROR;
7265 }
7266
7267 /* Check if an Over-Run/Under-Run error occurred */
7268 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
7269 {
7270 error_code |= HAL_I2C_ERROR_OVR;
7271
7272 /* Clear OVR flag */
7273 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
7274
7275 status = HAL_ERROR;
7276 }
7277
7278 /* Check if an Arbitration Loss error occurred */
7279 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
7280 {
7281 error_code |= HAL_I2C_ERROR_ARLO;
7282
7283 /* Clear ARLO flag */
7284 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
7285
7286 status = HAL_ERROR;
7287 }
7288
7289 if (status != HAL_OK)
7290 {
7291 /* Flush TX register */
7292 I2C_Flush_TXDR(hi2c);
7293
7294 /* Clear Configuration Register 2 */
7295 I2C_RESET_CR2(hi2c);
7296
7297 hi2c->ErrorCode |= error_code;
7298 hi2c->State = HAL_I2C_STATE_READY;
7299 hi2c->Mode = HAL_I2C_MODE_NONE;
7300
7301 /* Process Unlocked */
7302 __HAL_UNLOCK(hi2c);
7303 }
7304
7305 return status;
7306 }
7307
7308 /**
7309 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
7310 * @param hi2c I2C handle.
7311 * @param DevAddress Specifies the slave address to be programmed.
7312 * @param Size Specifies the number of bytes to be programmed.
7313 * This parameter must be a value between 0 and 255.
7314 * @param Mode New state of the I2C START condition generation.
7315 * This parameter can be one of the following values:
7316 * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
7317 * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
7318 * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
7319 * @param Request New state of the I2C START condition generation.
7320 * This parameter can be one of the following values:
7321 * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
7322 * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
7323 * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
7324 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
7325 * @retval None
7326 */
I2C_TransferConfig(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t Size,uint32_t Mode,uint32_t Request)7327 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
7328 uint32_t Request)
7329 {
7330 uint32_t tmp;
7331
7332 /* Check the parameters */
7333 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
7334 assert_param(IS_TRANSFER_MODE(Mode));
7335 assert_param(IS_TRANSFER_REQUEST(Request));
7336
7337 /* Declaration of tmp to prevent undefined behavior of volatile usage */
7338 tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
7339 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
7340 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
7341
7342 /* update CR2 register */
7343 MODIFY_REG(hi2c->Instance->CR2, \
7344 ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
7345 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
7346 I2C_CR2_START | I2C_CR2_STOP)), tmp);
7347 }
7348
7349 /**
7350 * @brief Manage the enabling of Interrupts.
7351 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7352 * the configuration information for the specified I2C.
7353 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7354 * @retval None
7355 */
I2C_Enable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7356 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7357 {
7358 uint32_t tmpisr = 0U;
7359
7360 if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
7361 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
7362 (hi2c->XferISR != I2C_Mem_ISR_DMA))
7363 {
7364 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7365 {
7366 /* Enable ERR, STOP, NACK and ADDR interrupts */
7367 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7368 }
7369
7370 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7371 {
7372 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7373 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7374 }
7375
7376 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7377 {
7378 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7379 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7380 }
7381
7382 if (InterruptRequest == I2C_XFER_ERROR_IT)
7383 {
7384 /* Enable ERR and NACK interrupts */
7385 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7386 }
7387
7388 if (InterruptRequest == I2C_XFER_CPLT_IT)
7389 {
7390 /* Enable STOP interrupts */
7391 tmpisr |= I2C_IT_STOPI;
7392 }
7393 }
7394
7395 else
7396 {
7397 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7398 {
7399 /* Enable ERR, STOP, NACK and ADDR interrupts */
7400 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7401 }
7402
7403 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7404 {
7405 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7406 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7407 }
7408
7409 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7410 {
7411 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7412 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7413 }
7414
7415 if (InterruptRequest == I2C_XFER_ERROR_IT)
7416 {
7417 /* Enable ERR and NACK interrupts */
7418 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7419 }
7420
7421 if (InterruptRequest == I2C_XFER_CPLT_IT)
7422 {
7423 /* Enable STOP interrupts */
7424 tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
7425 }
7426
7427 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7428 {
7429 /* Enable TC interrupts */
7430 tmpisr |= I2C_IT_TCI;
7431 }
7432 }
7433
7434 /* Enable interrupts only at the end */
7435 /* to avoid the risk of I2C interrupt handle execution before */
7436 /* all interrupts requested done */
7437 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
7438 }
7439
7440 /**
7441 * @brief Manage the disabling of Interrupts.
7442 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7443 * the configuration information for the specified I2C.
7444 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7445 * @retval None
7446 */
I2C_Disable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7447 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7448 {
7449 uint32_t tmpisr = 0U;
7450
7451 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7452 {
7453 /* Disable TC and TXI interrupts */
7454 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
7455
7456 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7457 {
7458 /* Disable NACK and STOP interrupts */
7459 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7460 }
7461 }
7462
7463 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7464 {
7465 /* Disable TC and RXI interrupts */
7466 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
7467
7468 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7469 {
7470 /* Disable NACK and STOP interrupts */
7471 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7472 }
7473 }
7474
7475 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7476 {
7477 /* Disable ADDR, NACK and STOP interrupts */
7478 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7479 }
7480
7481 if (InterruptRequest == I2C_XFER_ERROR_IT)
7482 {
7483 /* Enable ERR and NACK interrupts */
7484 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7485 }
7486
7487 if (InterruptRequest == I2C_XFER_CPLT_IT)
7488 {
7489 /* Enable STOP interrupts */
7490 tmpisr |= I2C_IT_STOPI;
7491 }
7492
7493 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7494 {
7495 /* Enable TC interrupts */
7496 tmpisr |= I2C_IT_TCI;
7497 }
7498
7499 /* Disable interrupts only at the end */
7500 /* to avoid a breaking situation like at "t" time */
7501 /* all disable interrupts request are not done */
7502 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
7503 }
7504
7505 /**
7506 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7507 * @param hi2c I2C handle.
7508 * @retval None
7509 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7510 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7511 {
7512 /* if user set XferOptions to I2C_OTHER_FRAME */
7513 /* it request implicitly to generate a restart condition */
7514 /* set XferOptions to I2C_FIRST_FRAME */
7515 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7516 {
7517 hi2c->XferOptions = I2C_FIRST_FRAME;
7518 }
7519 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7520 /* it request implicitly to generate a restart condition */
7521 /* then generate a stop condition at the end of transfer */
7522 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7523 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7524 {
7525 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7526 }
7527 else
7528 {
7529 /* Nothing to do */
7530 }
7531 }
7532
7533 /**
7534 * @}
7535 */
7536
7537 #endif /* HAL_I2C_MODULE_ENABLED */
7538 /**
7539 * @}
7540 */
7541
7542 /**
7543 * @}
7544 */
7545
