1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_hrtim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the High Resolution Timer (HRTIM) peripheral:
8 * + HRTIM Initialization
9 * + Timer Time Base Unit Configuration
10 * + Simple Time Base Start/Stop
11 * + Simple Time Base Start/Stop Interrupt
12 * + Simple Time Base Start/Stop DMA Request
13 * + Simple Output Compare/PWM Channel Configuration
14 * + Simple Output Compare/PWM Channel Start/Stop Interrupt
15 * + Simple Output Compare/PWM Channel Start/Stop DMA Request
16 * + Simple Input Capture Channel Configuration
17 * + Simple Input Capture Channel Start/Stop Interrupt
18 * + Simple Input Capture Channel Start/Stop DMA Request
19 * + Simple One Pulse Channel Configuration
20 * + Simple One Pulse Channel Start/Stop Interrupt
21 * + HRTIM External Synchronization Configuration
22 * + HRTIM Burst Mode Controller Configuration
23 * + HRTIM Burst Mode Controller Enabling
24 * + HRTIM External Events Conditioning Configuration
25 * + HRTIM Faults Conditioning Configuration
26 * + HRTIM Faults Enabling
27 * + HRTIM ADC trigger Configuration
28 * + Waveform Timer Configuration
29 * + Waveform Event Filtering Configuration
30 * + Waveform Dead Time Insertion Configuration
31 * + Waveform Chopper Mode Configuration
32 * + Waveform Compare Unit Configuration
33 * + Waveform Capture Unit Configuration
34 * + Waveform Output Configuration
35 * + Waveform Counter Start/Stop
36 * + Waveform Counter Start/Stop Interrupt
37 * + Waveform Counter Start/Stop DMA Request
38 * + Waveform Output Enabling
39 * + Waveform Output Level Set/Get
40 * + Waveform Output State Get
41 * + Waveform Burst DMA Operation Configuration
42 * + Waveform Burst DMA Operation Start
43 * + Waveform Timer Counter Software Reset
44 * + Waveform Capture Software Trigger
45 * + Waveform Burst Mode Controller Software Trigger
46 * + Waveform Timer Pre-loadable Registers Update Enabling
47 * + Waveform Timer Pre-loadable Registers Software Update
48 * + Waveform Timer Delayed Protection Status Get
49 * + Waveform Timer Burst Status Get
50 * + Waveform Timer Push-Pull Status Get
51 * + Peripheral State Get
52 *
53 ******************************************************************************
54 * @attention
55 *
56 * Copyright (c) 2017 STMicroelectronics.
57 * All rights reserved.
58 *
59 * This software is licensed under terms that can be found in the LICENSE file
60 * in the root directory of this software component.
61 * If no LICENSE file comes with this software, it is provided AS-IS.
62 *
63 ******************************************************************************
64 @verbatim
65 ==============================================================================
66 ##### Simple mode v.s. waveform mode #####
67 ==============================================================================
68 [..] The HRTIM HAL API is split into 2 categories:
69 (#)Simple functions: these functions allow for using a HRTIM timer as a
70 general purpose timer with high resolution capabilities.
71 HRTIM simple modes are managed through the set of functions named
72 HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
73 to the one defined for the TIM peripheral. When a HRTIM timer operates in
74 simple mode, only a very limited set of HRTIM features are used.
75 Following simple modes are proposed:
76 (++)Output compare mode,
77 (++)PWM output mode,
78 (++)Input capture mode,
79 (++)One pulse mode.
80 (#)Waveform functions: These functions allow taking advantage of the HRTIM
81 flexibility to produce numerous types of control signal. When a HRTIM timer
82 operates in waveform mode, all the HRTIM features are accessible without
83 any restriction. HRTIM waveform modes are managed through the set of
84 functions named HAL_HRTIM_Waveform<Function>
85
86 ##### How to use this driver #####
87 ==============================================================================
88 [..]
89 (#)Initialize the HRTIM low level resources by implementing the
90 HAL_HRTIM_MspInit() function:
91 (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
92 (##)Connect HRTIM pins to MCU I/Os
93 (+++) Enable the clock for the HRTIM GPIOs using the following
94 function: __HAL_RCC_GPIOx_CLK_ENABLE()
95 (+++) Configure these GPIO pins in Alternate Function mode using
96 HAL_GPIO_Init()
97 (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
98 (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
99 (+++)Initialize the DMA handle
100 (+++)Associate the initialized DMA handle to the appropriate DMA
101 handle of the HRTIM handle using __HAL_LINKDMA()
102 (+++)Initialize the DMA channel using HAL_DMA_Init()
103 (+++)Configure the priority and enable the NVIC for the transfer
104 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
105 and HAL_NVIC_EnableIRQ()
106 (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
107 (+++)Configure the priority and enable the NVIC for the concerned
108 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
109
110 (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
111 structure (field of the HRTIM handle) specifies which global interrupt of
112 whole HRTIM must be enabled (Burst mode period, System fault, Faults).
113 It also contains the HRTIM external synchronization configuration. HRTIM
114 can act as a master (generating a synchronization signal) or as a slave
115 (waiting for a trigger to be synchronized).
116
117 (#) Configure HRTIM resources shared by all HRTIM timers
118 (##)Burst Mode Controller:
119 (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
120 controller: operating mode (continuous or one-shot mode), clock
121 (source, prescaler) , trigger(s), period, idle duration.
122 (##)External Events Conditioning:
123 (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
124 external event channel: source, polarity, edge-sensitivity.
125 External event can be used as triggers (timer reset, input
126 capture, burst mode, ADC triggers, delayed protection)
127 They can also be used to set or reset timer outputs. Up to
128 10 event channels are available.
129 (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
130 event sampling clock (used for digital filtering).
131 (##)Fault Conditioning:
132 (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
133 fault channel: source, polarity, edge-sensitivity. Fault
134 channels are used to disable the outputs in case of an
135 abnormal operation. Up to 5 fault channels are available.
136 (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
137 sampling clock (used for digital filtering).
138 (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
139 circuitry. By default all fault inputs are disabled.
140 (##)ADC trigger:
141 (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
142 the update of the ADC trigger register and the ADC trigger.
143 4 independent triggers are available to start both the regular
144 and the injected sequencers of the 2 ADCs
145
146 (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
147 function must be called whatever the HRTIM timer operating mode is
148 (simple v.s. waveform). It configures mainly:
149 (##)The HRTIM timer counter operating mode (continuous v.s. one shot)
150 (##)The HRTIM timer clock prescaler
151 (##)The HRTIM timer period
152 (##)The HRTIM timer repetition counter
153
154 *** If the HRTIM timer operates in simple mode ***
155 ===================================================
156 [..]
157 (#) Start or Stop simple timers
158 (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
159 HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
160 HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
161 (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
162 HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
163 HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
164 HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
165 (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
166 HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
167 HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
168 HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
169 (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
170 HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
171 HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
172 HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
173 (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
174 HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
175 HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
176
177 *** If the HRTIM timer operates in waveform mode ***
178 ====================================================
179 [..]
180 (#) Completes waveform timer configuration
181 (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
182 operating in wave form mode mainly consists in:
183 (+++)Enabling the HRTIM timer interrupts and DMA requests.
184 (+++)Enabling the half mode for the HRTIM timer.
185 (+++)Defining how the HRTIM timer reacts to external synchronization input.
186 (+++)Enabling the push-pull mode for the HRTIM timer.
187 (+++)Enabling the fault channels for the HRTIM timer.
188 (+++)Enabling the dead-time insertion for the HRTIM timer.
189 (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
190 on which the delayed protection are applied).
191 (+++)Specifying the HRTIM timer update and reset triggers.
192 (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
193 (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
194 event blanking and windowing circuitry of a HRTIM timer:
195 (+++)Blanking: to mask external events during a defined time period a defined time period
196 (+++)Windowing, to enable external events only during a defined time period
197 (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
198 unit for a HRTIM timer. Allows to generate a couple of
199 complementary signals from a single reference waveform,
200 with programmable delays between active state.
201 (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
202 the high-frequency carrier signal added on top of the timing
203 unit output. Chopper mode can be enabled or disabled for each
204 timer output separately (see HAL_HRTIM_WaveformOutputConfig()).
205 (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
206 controller. Allows having multiple HRTIM registers updated
207 with a single DMA request. The burst DMA operation is started
208 by calling HAL_HRTIM_BurstDMATransfer().
209 (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
210 of a HRTIM timer. This operation consists in setting the
211 compare value and possibly specifying the auto delayed mode
212 for compare units 2 and 4 (allows to have compare events
213 generated relatively to capture events). Note that when auto
214 delayed mode is needed, the capture unit associated to the
215 compare unit must be configured separately.
216 (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
217 of a HRTIM timer. This operation consists in specifying the
218 source(s) triggering the capture (timer register update event,
219 external event, timer output set/reset event, other HRTIM
220 timer related events).
221 (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
222 output mainly consists in:
223 (+++)Setting the output polarity (active high or active low),
224 (+++)Defining the set/reset crossbar for the output,
225 (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
226
227 (#) Set waveform timer output(s) level
228 (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
229 active or inactive level. For example, when deadtime insertion
230 is enabled it is necessary to force the output level by software
231 to have the outputs in a complementary state as soon as the RUN mode is entered.
232
233 (#) Enable or Disable waveform timer output(s)
234 (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
235
236 (#) Start or Stop waveform HRTIM timer(s).
237 (++)HAL_HRTIM_WaveformCountStart(),HAL_HRTIM_WaveformCountStop(),
238 (++)HAL_HRTIM_WaveformCountStart_IT(),HAL_HRTIM_WaveformCountStop_IT(),
239 (++)HAL_HRTIM_WaveformCountStart_DMA(),HAL_HRTIM_WaveformCountStop_DMA(),
240 (#) Burst mode controller enabling:
241 (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
242 burst mode controller.
243
244 (#) Some HRTIM operations can be triggered by software:
245 (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
246 trigs the burst operation.
247 (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
248 capture of the HRTIM timer counter.
249 (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
250 update of the pre-loadable registers of the HRTIM timer
251 (++)HAL_HRTIM_SoftwareReset():calling this function resets the
252 HRTIM timer counter.
253
254 (#) Some functions can be used any time to retrieve HRTIM timer related
255 information
256 (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
257 capture register of the designated capture unit.
258 (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
259 (ACTIVE/INACTIVE) of the designated timer output.
260 (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
261 (IDLE/RUN/FAULT) of the designated timer output.
262 (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
263 (ACTIVE/INACTIVE) of the designated output when the delayed
264 protection was triggered.
265 (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
266 (ACTIVE/INACTIVE) of the burst mode controller.
267 (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
268 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
269 the push-pull status indicates on which output the signal is currently
270 active (e.g signal applied on output 1 and output 2 forced
271 inactive or vice versa).
272 (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
273 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
274 the idle push-pull status indicates during which period the
275 delayed protection request occurred (e.g. protection occurred
276 when the output 1 was active and output 2 forced inactive or
277 vice versa).
278
279 (#) Some functions can be used any time to retrieve actual HRTIM status
280 (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
281
282 *** Callback registration ***
283 =============================
284 [..]
285 The compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS when set to 1
286 allows the user to configure dynamically the driver callbacks.
287 Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
288 to register an interrupt callback.
289
290 [..]
291 Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
292 (+) Fault1Callback : Fault 1 interrupt callback function
293 (+) Fault2Callback : Fault 2 interrupt callback function
294 (+) Fault3Callback : Fault 3 interrupt callback function
295 (+) Fault4Callback : Fault 4 interrupt callback function
296 (+) Fault5Callback : Fault 5 interrupt callback function
297 (+) SystemFaultCallback : System fault interrupt callback function
298 (+) BurstModePeriodCallback : Burst mode period interrupt callback function
299 (+) SynchronizationEventCallback : Sync Input interrupt callback function
300 (+) ErrorCallback : DMA error callback function
301 (+) MspInitCallback : HRTIM MspInit callback function
302 (+) MspDeInitCallback : HRTIM MspInit callback function
303
304 [..]
305 Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
306 (+) RegistersUpdateCallback : Timer x Update interrupt callback function
307 (+) RepetitionEventCallback : Timer x Repetition interrupt callback function
308 (+) Compare1EventCallback : Timer x Compare 1 match interrupt callback function
309 (+) Compare2EventCallback : Timer x Compare 2 match interrupt callback function
310 (+) Compare3EventCallback : Timer x Compare 3 match interrupt callback function
311 (+) Compare4EventCallback : Timer x Compare 4 match interrupt callback function
312 (+) Capture1EventCallback : Timer x Capture 1 interrupts callback function
313 (+) Capture2EventCallback : Timer x Capture 2 interrupts callback function
314 (+) DelayedProtectionCallback : Timer x Delayed protection interrupt callback function
315 (+) CounterResetCallback : Timer x counter reset/roll-over interrupt callback function
316 (+) Output1SetCallback : Timer x output 1 set interrupt callback function
317 (+) Output1ResetCallback : Timer x output 1 reset interrupt callback function
318 (+) Output2SetCallback : Timer x output 2 set interrupt callback function
319 (+) Output2ResetCallback : Timer x output 2 reset interrupt callback function
320 (+) BurstDMATransferCallback : Timer x Burst DMA completed interrupt callback function
321
322 [..]
323 Both functions take as parameters the HAL peripheral handle, the Callback ID
324 and a pointer to the user callback function.
325
326 [..]
327 Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
328 to reset a callback to the default weak function. Both functions take as parameters
329 the HAL peripheral handle and the Callback ID.
330
331 [..]
332 By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
333 all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
334 Exception done for MspInit and MspDeInit functions that are reset to the legacy
335 weak functions in the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() only when these
336 callbacks are null (not registered beforehand). If MspInit or MspDeInit are
337 not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
338 MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
339
340 [..]
341 Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
342 Exception done MspInit/MspDeInit functions that can be registered/unregistered
343 in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
344 (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
345 Then, the user first registers the MspInit/MspDeInit user callbacks
346 using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
347 or HAL_HRTIM_Init() function.
348
349 [..]
350 When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
351 not defined, the callback registration feature is not available and all
352 callbacks are set to the corresponding weak functions.
353
354 @endverbatim
355 ******************************************************************************
356 */
357
358 /* Includes ------------------------------------------------------------------*/
359 #include "stm32h7xx_hal.h"
360
361 /** @addtogroup STM32H7xx_HAL_Driver
362 * @{
363 */
364
365 #ifdef HAL_HRTIM_MODULE_ENABLED
366
367 #if defined(HRTIM1)
368
369 /** @defgroup HRTIM HRTIM
370 * @brief HRTIM HAL module driver
371 * @{
372 */
373
374 /* Private typedef -----------------------------------------------------------*/
375 /* Private define ------------------------------------------------------------*/
376 /** @defgroup HRTIM_Private_Defines HRTIM Private Define
377 * @{
378 */
379 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
380 HRTIM_FLTR_FLT2EN |\
381 HRTIM_FLTR_FLT3EN |\
382 HRTIM_FLTR_FLT4EN | \
383 HRTIM_FLTR_FLT5EN)
384
385 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
386 HRTIM_TIMUPDATETRIGGER_TIMER_A |\
387 HRTIM_TIMUPDATETRIGGER_TIMER_B |\
388 HRTIM_TIMUPDATETRIGGER_TIMER_C |\
389 HRTIM_TIMUPDATETRIGGER_TIMER_D |\
390 HRTIM_TIMUPDATETRIGGER_TIMER_E)
391
392 #define HRTIM_FLTINR1_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
393 (HRTIM_FAULTLOCK_READONLY << 8U) | \
394 (HRTIM_FAULTLOCK_READONLY << 16U) | \
395 (HRTIM_FAULTLOCK_READONLY << 24U))
396
397 #define HRTIM_FLTINR2_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
398 (HRTIM_FAULTLOCK_READONLY << 8U))
399 /**
400 * @}
401 */
402
403 /* Private macro -------------------------------------------------------------*/
404 /* Private variables ---------------------------------------------------------*/
405 /** @defgroup HRTIM_Private_Variables HRTIM Private Variables
406 * @{
407 */
408 static uint32_t TimerIdxToTimerId[] =
409 {
410 HRTIM_TIMERID_TIMER_A,
411 HRTIM_TIMERID_TIMER_B,
412 HRTIM_TIMERID_TIMER_C,
413 HRTIM_TIMERID_TIMER_D,
414 HRTIM_TIMERID_TIMER_E,
415 HRTIM_TIMERID_MASTER,
416 };
417 /**
418 * @}
419 */
420
421 /* Private function prototypes -----------------------------------------------*/
422 /** @defgroup HRTIM_Private_Functions HRTIM Private Functions
423 * @{
424 */
425 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim,
426 const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg);
427
428 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim,
429 uint32_t TimerIdx,
430 const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg);
431
432 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim,
433 const HRTIM_TimerCfgTypeDef *pTimerCfg);
434
435 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim,
436 uint32_t TimerIdx,
437 const HRTIM_TimerCfgTypeDef *pTimerCfg);
438
439
440 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim,
441 uint32_t TimerIdx,
442 uint32_t CaptureUnit,
443 uint32_t Event);
444
445 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim,
446 uint32_t TimerIdx,
447 uint32_t Output,
448 const HRTIM_OutputCfgTypeDef *pOutputCfg);
449
450 static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
451 uint32_t Event,
452 const HRTIM_EventCfgTypeDef *pEventCfg);
453
454 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim,
455 uint32_t TimerIdx,
456 uint32_t Event);
457
458 static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim,
459 uint32_t TimerIdx,
460 uint32_t OCChannel);
461
462 static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim,
463 uint32_t TimerIdx,
464 uint32_t OCChannel);
465
466 static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim,
467 uint32_t TimerIdx);
468
469 static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim,
470 const DMA_HandleTypeDef *hdma);
471
472 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim,
473 uint32_t TimerIdx);
474
475 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim);
476
477 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim);
478
479 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim,
480 uint32_t TimerIdx);
481
482 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
483
484 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
485
486 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
487
488 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
489 /**
490 * @}
491 */
492
493 /* Exported functions ---------------------------------------------------------*/
494 /** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
495 * @{
496 */
497
498 /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
499 * @brief Initialization and Configuration functions
500 @verbatim
501 ===============================================================================
502 ##### Initialization and Time Base Configuration functions #####
503 ===============================================================================
504 [..] This section provides functions allowing to:
505 (+) Initialize a HRTIM instance
506 (+) De-initialize a HRTIM instance
507 (+) Initialize the HRTIM MSP
508 (+) De-initialize the HRTIM MSP
509 (+) Configure the time base unit of a HRTIM timer
510
511 @endverbatim
512 * @{
513 */
514
515 /**
516 * @brief Initialize a HRTIM instance
517 * @param hhrtim pointer to HAL HRTIM handle
518 * @retval HAL status
519 */
HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)520 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim)
521 {
522 uint8_t timer_idx;
523 uint32_t hrtim_mcr;
524
525 /* Check the HRTIM handle allocation */
526 if (hhrtim == NULL)
527 {
528 return HAL_ERROR;
529 }
530
531 /* Check the parameters */
532 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
533 assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptRequests));
534
535 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
536 if (hhrtim->State == HAL_HRTIM_STATE_RESET)
537 {
538 /* Initialize callback function pointers to their default values */
539 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
540 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
541 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
542 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
543 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
544 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
545 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
546 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
547 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
548 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
549 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
550 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
551 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
552 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
553 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
554 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
555 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
556 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
557 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
558 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
559 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
560 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
561 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
562 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
563
564 if (hhrtim->MspInitCallback == NULL)
565 {
566 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
567 }
568 }
569 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
570
571 /* Set the HRTIM state */
572 hhrtim->State = HAL_HRTIM_STATE_BUSY;
573
574 /* Initialize the DMA handles */
575 hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
576 hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
577 hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
578 hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
579 hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
580 hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
581
582 /* HRTIM output synchronization configuration (if required) */
583 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != (uint32_t)RESET)
584 {
585 /* Check parameters */
586 assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
587 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
588
589 /* The synchronization output initialization procedure must be done prior
590 to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
591 */
592 if (hhrtim->Instance == HRTIM1)
593 {
594 /* Enable the HRTIM peripheral clock */
595 __HAL_RCC_HRTIM1_CLK_ENABLE();
596 }
597
598 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
599
600 /* Set the event to be sent on the synchronization output */
601 hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
602 hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
603
604 /* Set the polarity of the synchronization output */
605 hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
606 hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
607
608 /* Update the HRTIM registers */
609 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
610 }
611
612 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
613 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
614 hhrtim->MspInitCallback(hhrtim);
615 #else
616 HAL_HRTIM_MspInit(hhrtim);
617 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
618
619 /* HRTIM input synchronization configuration (if required) */
620 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != (uint32_t)RESET)
621 {
622 /* Check parameters */
623 assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
624
625 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
626
627 /* Set the synchronization input source */
628 hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
629 hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
630
631 /* Update the HRTIM registers */
632 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
633 }
634
635 /* Initialize the HRTIM state*/
636 hhrtim->State = HAL_HRTIM_STATE_READY;
637
638 /* Initialize the lock status of the HRTIM HAL API */
639 __HAL_UNLOCK(hhrtim);
640
641 /* Initialize timer related parameters */
642 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
643 timer_idx <= HRTIM_TIMERINDEX_MASTER ;
644 timer_idx++)
645 {
646 hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
647 hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
648 hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
649 hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
650 hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
651 hhrtim->TimerParam[timer_idx].DMASize = 0U;
652 }
653
654 return HAL_OK;
655 }
656
657 /**
658 * @brief De-initialize a HRTIM instance
659 * @param hhrtim pointer to HAL HRTIM handle
660 * @retval HAL status
661 */
HAL_HRTIM_DeInit(HRTIM_HandleTypeDef * hhrtim)662 HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim)
663 {
664 /* Check the HRTIM handle allocation */
665 if (hhrtim == NULL)
666 {
667 return HAL_ERROR;
668 }
669
670 /* Check the parameters */
671 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
672
673 /* Set the HRTIM state */
674 hhrtim->State = HAL_HRTIM_STATE_BUSY;
675
676 /* DeInit the low level hardware */
677 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
678 if (hhrtim->MspDeInitCallback == NULL)
679 {
680 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
681 }
682
683 hhrtim->MspDeInitCallback(hhrtim);
684 #else
685 HAL_HRTIM_MspDeInit(hhrtim);
686 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
687
688 hhrtim->State = HAL_HRTIM_STATE_READY;
689
690 return HAL_OK;
691 }
692
693 /**
694 * @brief MSP initialization for a HRTIM instance
695 * @param hhrtim pointer to HAL HRTIM handle
696 * @retval None
697 */
HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)698 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim)
699 {
700 /* Prevent unused argument(s) compilation warning */
701 UNUSED(hhrtim);
702
703 /* NOTE: This function should not be modified, when the callback is needed,
704 the HAL_HRTIM_MspInit could be implemented in the user file
705 */
706 }
707
708 /**
709 * @brief MSP de-initialization of a HRTIM instance
710 * @param hhrtim pointer to HAL HRTIM handle
711 * @retval None
712 */
HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)713 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim)
714 {
715 /* Prevent unused argument(s) compilation warning */
716 UNUSED(hhrtim);
717
718 /* NOTE: This function should not be modified, when the callback is needed,
719 the HAL_HRTIM_MspDeInit could be implemented in the user file
720 */
721 }
722
723 /**
724 * @brief Configure the time base unit of a timer
725 * @param hhrtim pointer to HAL HRTIM handle
726 * @param TimerIdx Timer index
727 * This parameter can be one of the following values:
728 * @arg HRTIM_TIMERINDEX_MASTER for master timer
729 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
730 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
731 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
732 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
733 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
734 * @param pTimeBaseCfg pointer to the time base configuration structure
735 * @note This function must be called prior starting the timer
736 * @note The time-base unit initialization parameters specify:
737 * The timer counter operating mode (continuous, one shot),
738 * The timer clock prescaler,
739 * The timer period,
740 * The timer repetition counter.
741 * @retval HAL status
742 */
HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)743 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
744 uint32_t TimerIdx,
745 const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
746 {
747 /* Check the parameters */
748 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
749 assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
750 assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
751
752 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
753 {
754 return HAL_BUSY;
755 }
756
757 /* Set the HRTIM state */
758 hhrtim->State = HAL_HRTIM_STATE_BUSY;
759
760 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
761 {
762 /* Configure master timer time base unit */
763 HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
764 }
765 else
766 {
767 /* Configure timing unit time base unit */
768 HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
769 }
770
771 /* Set HRTIM state */
772 hhrtim->State = HAL_HRTIM_STATE_READY;
773
774 return HAL_OK;
775 }
776
777 /**
778 * @}
779 */
780
781 /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
782 * @brief Simple time base mode functions.
783 @verbatim
784 ===============================================================================
785 ##### Simple time base mode functions #####
786 ===============================================================================
787 [..] This section provides functions allowing to:
788 (+) Start simple time base
789 (+) Stop simple time base
790 (+) Start simple time base and enable interrupt
791 (+) Stop simple time base and disable interrupt
792 (+) Start simple time base and enable DMA transfer
793 (+) Stop simple time base and disable DMA transfer
794 -@- When a HRTIM timer operates in simple time base mode, the timer
795 counter counts from 0 to the period value.
796
797 @endverbatim
798 * @{
799 */
800
801 /**
802 * @brief Start the counter of a timer operating in simple time base mode.
803 * @param hhrtim pointer to HAL HRTIM handle
804 * @param TimerIdx Timer index.
805 * This parameter can be one of the following values:
806 * @arg HRTIM_TIMERINDEX_MASTER for master timer
807 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
808 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
809 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
810 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
811 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
812 * @retval HAL status
813 */
HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)814 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
815 uint32_t TimerIdx)
816 {
817 /* Check the parameters */
818 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
819
820 /* Process Locked */
821 __HAL_LOCK(hhrtim);
822
823 hhrtim->State = HAL_HRTIM_STATE_BUSY;
824
825 /* Enable the timer counter */
826 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
827
828 hhrtim->State = HAL_HRTIM_STATE_READY;
829
830 /* Process Unlocked */
831 __HAL_UNLOCK(hhrtim);
832
833 return HAL_OK;
834 }
835
836 /**
837 * @brief Stop the counter of a timer operating in simple time base mode.
838 * @param hhrtim pointer to HAL HRTIM handle
839 * @param TimerIdx Timer index.
840 * This parameter can be one of the following values:
841 * @arg HRTIM_TIMERINDEX_MASTER for master timer
842 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
843 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
844 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
845 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
846 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
847 * @retval HAL status
848 */
HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)849 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
850 uint32_t TimerIdx)
851 {
852 /* Check the parameters */
853 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
854
855 /* Process Locked */
856 __HAL_LOCK(hhrtim);
857
858 hhrtim->State = HAL_HRTIM_STATE_BUSY;
859
860 /* Disable the timer counter */
861 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
862
863 hhrtim->State = HAL_HRTIM_STATE_READY;
864
865 /* Process Unlocked */
866 __HAL_UNLOCK(hhrtim);
867
868 return HAL_OK;
869 }
870
871 /**
872 * @brief Start the counter of a timer operating in simple time base mode
873 * (Timer repetition interrupt is enabled).
874 * @param hhrtim pointer to HAL HRTIM handle
875 * @param TimerIdx Timer index.
876 * This parameter can be one of the following values:
877 * @arg HRTIM_TIMERINDEX_MASTER for master timer
878 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
879 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
880 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
881 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
882 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
883 * @retval HAL status
884 */
HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)885 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
886 uint32_t TimerIdx)
887 {
888 /* Check the parameters */
889 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
890
891 /* Process Locked */
892 __HAL_LOCK(hhrtim);
893
894 hhrtim->State = HAL_HRTIM_STATE_BUSY;
895
896 /* Enable the repetition interrupt */
897 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
898 {
899 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
900 }
901 else
902 {
903 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
904 }
905
906 /* Enable the timer counter */
907 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
908
909 hhrtim->State = HAL_HRTIM_STATE_READY;
910
911 /* Process Unlocked */
912 __HAL_UNLOCK(hhrtim);
913
914 return HAL_OK;
915 }
916
917 /**
918 * @brief Stop the counter of a timer operating in simple time base mode
919 * (Timer repetition interrupt is disabled).
920 * @param hhrtim pointer to HAL HRTIM handle
921 * @param TimerIdx Timer index.
922 * This parameter can be one of the following values:
923 * @arg HRTIM_TIMERINDEX_MASTER for master timer
924 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
925 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
926 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
927 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
928 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
929 * @retval HAL status
930 */
HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)931 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
932 uint32_t TimerIdx)
933 {
934 /* Check the parameters */
935 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
936
937 /* Process Locked */
938 __HAL_LOCK(hhrtim);
939
940 hhrtim->State = HAL_HRTIM_STATE_BUSY;
941
942 /* Disable the repetition interrupt */
943 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
944 {
945 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
946 }
947 else
948 {
949 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
950 }
951
952 /* Disable the timer counter */
953 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
954
955 hhrtim->State = HAL_HRTIM_STATE_READY;
956
957 /* Process Unlocked */
958 __HAL_UNLOCK(hhrtim);
959
960 return HAL_OK;
961 }
962
963 /**
964 * @brief Start the counter of a timer operating in simple time base mode
965 * (Timer repetition DMA request is enabled).
966 * @param hhrtim pointer to HAL HRTIM handle
967 * @param TimerIdx Timer index.
968 * This parameter can be one of the following values:
969 * @arg HRTIM_TIMERINDEX_MASTER for master timer
970 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
971 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
972 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
973 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
974 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
975 * @param SrcAddr DMA transfer source address
976 * @param DestAddr DMA transfer destination address
977 * @param Length The length of data items (data size) to be transferred
978 * from source to destination
979 */
HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)980 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
981 uint32_t TimerIdx,
982 uint32_t SrcAddr,
983 uint32_t DestAddr,
984 uint32_t Length)
985 {
986 DMA_HandleTypeDef *hdma;
987
988 /* Check the parameters */
989 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
990
991 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
992 {
993 return HAL_BUSY;
994 }
995 if (hhrtim->State == HAL_HRTIM_STATE_READY)
996 {
997 if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U))
998 {
999 return HAL_ERROR;
1000 }
1001 else
1002 {
1003 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1004 }
1005 }
1006
1007 /* Process Locked */
1008 __HAL_LOCK(hhrtim);
1009
1010 /* Get the timer DMA handler */
1011 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1012
1013 if (hdma == NULL)
1014 {
1015 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1016
1017 /* Process Unlocked */
1018 __HAL_UNLOCK(hhrtim);
1019
1020 return HAL_ERROR;
1021 }
1022
1023 /* Set the DMA transfer completed callback */
1024 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1025 {
1026 hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
1027 }
1028 else
1029 {
1030 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1031 }
1032
1033 /* Set the DMA error callback */
1034 hdma->XferErrorCallback = HRTIM_DMAError ;
1035
1036 /* Enable the DMA channel */
1037 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1038 {
1039 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1040
1041 /* Process Unlocked */
1042 __HAL_UNLOCK(hhrtim);
1043
1044 return HAL_ERROR;
1045 }
1046
1047 /* Enable the timer repetition DMA request */
1048 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1049 {
1050 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1051 }
1052 else
1053 {
1054 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1055 }
1056
1057 /* Enable the timer counter */
1058 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1059
1060 hhrtim->State = HAL_HRTIM_STATE_READY;
1061
1062 /* Process Unlocked */
1063 __HAL_UNLOCK(hhrtim);
1064
1065 return HAL_OK;
1066 }
1067
1068 /**
1069 * @brief Stop the counter of a timer operating in simple time base mode
1070 * (Timer repetition DMA request is disabled).
1071 * @param hhrtim pointer to HAL HRTIM handle
1072 * @param TimerIdx Timer index.
1073 * This parameter can be one of the following values:
1074 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1075 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1076 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1077 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1078 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1079 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1080 * @retval HAL status
1081 */
HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1082 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
1083 uint32_t TimerIdx)
1084 {
1085 DMA_HandleTypeDef *hdma;
1086
1087 /* Check the parameters */
1088 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1089
1090 /* Process Locked */
1091 __HAL_LOCK(hhrtim);
1092
1093 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1094 {
1095 hhrtim->State = HAL_HRTIM_STATE_READY;
1096
1097 /* Disable the DMA */
1098 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
1099 {
1100 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1101 }
1102 /* Disable the timer repetition DMA request */
1103 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1104 }
1105 else
1106 {
1107 /* Get the timer DMA handler */
1108 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1109
1110 if (hdma == NULL)
1111 {
1112 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1113 }
1114 else
1115 {
1116 hhrtim->State = HAL_HRTIM_STATE_READY;
1117
1118 /* Disable the DMA */
1119 if (HAL_DMA_Abort(hdma) != HAL_OK)
1120 {
1121 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1122 }
1123
1124 /* Disable the timer repetition DMA request */
1125 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1126 }
1127 }
1128
1129 /* Disable the timer counter */
1130 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1131
1132 /* Process Unlocked */
1133 __HAL_UNLOCK(hhrtim);
1134
1135 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
1136 {
1137 return HAL_ERROR;
1138 }
1139 else
1140 {
1141 return HAL_OK;
1142 }
1143 }
1144
1145 /**
1146 * @}
1147 */
1148
1149 /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
1150 * @brief Simple output compare functions
1151 @verbatim
1152 ===============================================================================
1153 ##### Simple output compare functions #####
1154 ===============================================================================
1155 [..] This section provides functions allowing to:
1156 (+) Configure simple output channel
1157 (+) Start simple output compare
1158 (+) Stop simple output compare
1159 (+) Start simple output compare and enable interrupt
1160 (+) Stop simple output compare and disable interrupt
1161 (+) Start simple output compare and enable DMA transfer
1162 (+) Stop simple output compare and disable DMA transfer
1163 -@- When a HRTIM timer operates in simple output compare mode
1164 the output level is set to a programmable value when a match
1165 is found between the compare register and the counter.
1166 Compare unit 1 is automatically associated to output 1
1167 Compare unit 2 is automatically associated to output 2
1168 @endverbatim
1169 * @{
1170 */
1171
1172 /**
1173 * @brief Configure an output in simple output compare mode
1174 * @param hhrtim pointer to HAL HRTIM handle
1175 * @param TimerIdx Timer index
1176 * This parameter can be one of the following values:
1177 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1178 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1179 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1180 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1181 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1182 * @param OCChannel Timer output
1183 * This parameter can be one of the following values:
1184 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1185 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1186 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1187 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1188 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1189 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1190 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1191 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1192 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1193 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1194 * @param pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
1195 * @note When the timer operates in simple output compare mode:
1196 * Output 1 is implicitly controlled by the compare unit 1
1197 * Output 2 is implicitly controlled by the compare unit 2
1198 * Output Set/Reset crossbar is set according to the selected output compare mode:
1199 * Toggle: SETxyR = RSTxyR = CMPy
1200 * Active: SETxyR = CMPy, RSTxyR = 0
1201 * Inactive: SETxy =0, RSTxy = CMPy
1202 * @retval HAL status
1203 */
HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel,const HRTIM_SimpleOCChannelCfgTypeDef * pSimpleOCChannelCfg)1204 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
1205 uint32_t TimerIdx,
1206 uint32_t OCChannel,
1207 const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg)
1208 {
1209 uint32_t CompareUnit = (uint32_t)RESET;
1210 HRTIM_OutputCfgTypeDef OutputCfg;
1211
1212 /* Check parameters */
1213 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1214 assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
1215 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOCChannelCfg->Pulse));
1216 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
1217 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
1218
1219 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
1220 {
1221 return HAL_BUSY;
1222 }
1223
1224 /* Process Locked */
1225 __HAL_LOCK(hhrtim);
1226
1227 /* Set HRTIM state */
1228 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1229
1230 /* Configure timer compare unit */
1231 switch (OCChannel)
1232 {
1233 case HRTIM_OUTPUT_TA1:
1234 case HRTIM_OUTPUT_TB1:
1235 case HRTIM_OUTPUT_TC1:
1236 case HRTIM_OUTPUT_TD1:
1237 case HRTIM_OUTPUT_TE1:
1238 {
1239 CompareUnit = HRTIM_COMPAREUNIT_1;
1240 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse;
1241 break;
1242 }
1243 case HRTIM_OUTPUT_TA2:
1244 case HRTIM_OUTPUT_TB2:
1245 case HRTIM_OUTPUT_TC2:
1246 case HRTIM_OUTPUT_TD2:
1247 case HRTIM_OUTPUT_TE2:
1248 {
1249 CompareUnit = HRTIM_COMPAREUNIT_2;
1250 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse;
1251 break;
1252 }
1253 default:
1254 {
1255 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1256
1257 /* Process Unlocked */
1258 __HAL_UNLOCK(hhrtim);
1259
1260 break;
1261 }
1262 }
1263
1264 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
1265 {
1266 return HAL_ERROR;
1267 }
1268
1269 /* Configure timer output */
1270 OutputCfg.Polarity = (pSimpleOCChannelCfg->Polarity & HRTIM_OUTR_POL1);
1271 OutputCfg.IdleLevel = (pSimpleOCChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
1272 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1273 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1274 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1275 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1276
1277 switch (pSimpleOCChannelCfg->Mode)
1278 {
1279 case HRTIM_BASICOCMODE_TOGGLE:
1280 {
1281 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1282 {
1283 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1284 }
1285 else
1286 {
1287 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1288 }
1289 OutputCfg.ResetSource = OutputCfg.SetSource;
1290 break;
1291 }
1292
1293 case HRTIM_BASICOCMODE_ACTIVE:
1294 {
1295 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1296 {
1297 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1298 }
1299 else
1300 {
1301 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1302 }
1303 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1304 break;
1305 }
1306
1307 case HRTIM_BASICOCMODE_INACTIVE:
1308 {
1309 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1310 {
1311 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
1312 }
1313 else
1314 {
1315 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
1316 }
1317 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1318 break;
1319 }
1320
1321 default:
1322 {
1323 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1324 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1325
1326 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1327
1328 /* Process Unlocked */
1329 __HAL_UNLOCK(hhrtim);
1330
1331 break;
1332 }
1333 }
1334
1335 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
1336 {
1337 return HAL_ERROR;
1338 }
1339
1340 HRTIM_OutputConfig(hhrtim,
1341 TimerIdx,
1342 OCChannel,
1343 &OutputCfg);
1344
1345 /* Set HRTIM state */
1346 hhrtim->State = HAL_HRTIM_STATE_READY;
1347
1348 /* Process Unlocked */
1349 __HAL_UNLOCK(hhrtim);
1350
1351 return HAL_OK;
1352 }
1353
1354 /**
1355 * @brief Start the output compare signal generation on the designed timer output
1356 * @param hhrtim pointer to HAL HRTIM handle
1357 * @param TimerIdx Timer index
1358 * This parameter can be one of the following values:
1359 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1360 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1361 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1362 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1363 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1364 * @param OCChannel Timer output
1365 * This parameter can be one of the following values:
1366 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1367 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1368 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1369 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1370 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1371 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1372 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1373 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1374 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1375 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1376 * @retval HAL status
1377 */
HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1378 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
1379 uint32_t TimerIdx,
1380 uint32_t OCChannel)
1381 {
1382 /* Check the parameters */
1383 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1384
1385 /* Process Locked */
1386 __HAL_LOCK(hhrtim);
1387
1388 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1389
1390 /* Enable the timer output */
1391 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1392
1393 /* Enable the timer counter */
1394 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1395
1396 hhrtim->State = HAL_HRTIM_STATE_READY;
1397
1398 /* Process Unlocked */
1399 __HAL_UNLOCK(hhrtim);
1400
1401 return HAL_OK;
1402 }
1403
1404 /**
1405 * @brief Stop the output compare signal generation on the designed timer output
1406 * @param hhrtim pointer to HAL HRTIM handle
1407 * @param TimerIdx Timer index
1408 * This parameter can be one of the following values:
1409 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1410 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1411 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1412 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1413 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1414 * @param OCChannel Timer output
1415 * This parameter can be one of the following values:
1416 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1417 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1418 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1419 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1420 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1421 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1422 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1423 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1424 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1425 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1426 * @retval HAL status
1427 */
HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1428 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
1429 uint32_t TimerIdx,
1430 uint32_t OCChannel)
1431 {
1432 /* Check the parameters */
1433 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1434
1435 /* Process Locked */
1436 __HAL_LOCK(hhrtim);
1437
1438 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1439
1440 /* Disable the timer output */
1441 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1442
1443 /* Disable the timer counter */
1444 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1445
1446 hhrtim->State = HAL_HRTIM_STATE_READY;
1447
1448 /* Process Unlocked */
1449 __HAL_UNLOCK(hhrtim);
1450
1451 return HAL_OK;
1452 }
1453
1454 /**
1455 * @brief Start the output compare signal generation on the designed timer output
1456 * (Interrupt is enabled (see note note below)).
1457 * @param hhrtim pointer to HAL HRTIM handle
1458 * @param TimerIdx Timer index
1459 * This parameter can be one of the following values:
1460 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1461 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1462 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1463 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1464 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1465 * @param OCChannel Timer output
1466 * This parameter can be one of the following values:
1467 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1468 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1469 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1470 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1471 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1472 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1473 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1474 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1475 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1476 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1477 * @note Interrupt enabling depends on the chosen output compare mode
1478 * Output toggle: compare match interrupt is enabled
1479 * Output set active: output set interrupt is enabled
1480 * Output set inactive: output reset interrupt is enabled
1481 * @retval HAL status
1482 */
HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1483 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
1484 uint32_t TimerIdx,
1485 uint32_t OCChannel)
1486 {
1487 uint32_t interrupt;
1488
1489 /* Check the parameters */
1490 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1491
1492 /* Process Locked */
1493 __HAL_LOCK(hhrtim);
1494
1495 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1496
1497 /* Get the interrupt to enable (depends on the output compare mode) */
1498 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1499
1500 /* Enable the timer output */
1501 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1502
1503 /* Enable the timer interrupt (depends on the output compare mode) */
1504 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
1505
1506 /* Enable the timer counter */
1507 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1508
1509 hhrtim->State = HAL_HRTIM_STATE_READY;
1510
1511 /* Process Unlocked */
1512 __HAL_UNLOCK(hhrtim);
1513
1514 return HAL_OK;
1515 }
1516
1517 /**
1518 * @brief Stop the output compare signal generation on the designed timer output
1519 * (Interrupt is disabled).
1520 * @param hhrtim pointer to HAL HRTIM handle
1521 * @param TimerIdx Timer index
1522 * This parameter can be one of the following values:
1523 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1524 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1525 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1526 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1527 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1528 * @param OCChannel Timer output
1529 * This parameter can be one of the following values:
1530 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1531 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1532 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1533 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1534 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1535 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1536 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1537 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1538 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1539 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1540 * @retval HAL status
1541 */
HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1542 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
1543 uint32_t TimerIdx,
1544 uint32_t OCChannel)
1545 {
1546 uint32_t interrupt;
1547
1548 /* Check the parameters */
1549 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1550
1551 /* Process Locked */
1552 __HAL_LOCK(hhrtim);
1553
1554 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1555
1556 /* Disable the timer output */
1557 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1558
1559 /* Get the interrupt to disable (depends on the output compare mode) */
1560 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1561
1562 /* Disable the timer interrupt */
1563 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
1564
1565 /* Disable the timer counter */
1566 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1567
1568 hhrtim->State = HAL_HRTIM_STATE_READY;
1569
1570 /* Process Unlocked */
1571 __HAL_UNLOCK(hhrtim);
1572
1573 return HAL_OK;
1574 }
1575
1576 /**
1577 * @brief Start the output compare signal generation on the designed timer output
1578 * (DMA request is enabled (see note below)).
1579 * @param hhrtim pointer to HAL HRTIM handle
1580 * @param TimerIdx Timer index
1581 * This parameter can be one of the following values:
1582 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1583 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1584 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1585 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1586 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1587 * @param OCChannel Timer output
1588 * This parameter can be one of the following values:
1589 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1590 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1591 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1592 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1593 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1594 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1595 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1596 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1597 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1598 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1599 * @param SrcAddr DMA transfer source address
1600 * @param DestAddr DMA transfer destination address
1601 * @param Length The length of data items (data size) to be transferred
1602 * from source to destination
1603 * @note DMA request enabling depends on the chosen output compare mode
1604 * Output toggle: compare match DMA request is enabled
1605 * Output set active: output set DMA request is enabled
1606 * Output set inactive: output reset DMA request is enabled
1607 * @retval HAL status
1608 */
HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)1609 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
1610 uint32_t TimerIdx,
1611 uint32_t OCChannel,
1612 uint32_t SrcAddr,
1613 uint32_t DestAddr,
1614 uint32_t Length)
1615 {
1616 DMA_HandleTypeDef *hdma;
1617 uint32_t dma_request;
1618
1619 /* Check the parameters */
1620 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1621
1622 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
1623 {
1624 return HAL_BUSY;
1625 }
1626 if (hhrtim->State == HAL_HRTIM_STATE_READY)
1627 {
1628 if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U))
1629 {
1630 return HAL_ERROR;
1631 }
1632 else
1633 {
1634 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1635 }
1636 }
1637
1638 /* Process Locked */
1639 __HAL_LOCK(hhrtim);
1640
1641 /* Enable the timer output */
1642 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1643
1644 /* Get the DMA request to enable */
1645 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1646
1647 /* Get the timer DMA handler */
1648 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1649
1650 if (hdma == NULL)
1651 {
1652 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1653
1654 /* Process Unlocked */
1655 __HAL_UNLOCK(hhrtim);
1656
1657 return HAL_ERROR;
1658 }
1659
1660 /* Set the DMA error callback */
1661 hdma->XferErrorCallback = HRTIM_DMAError ;
1662
1663 /* Set the DMA transfer completed callback */
1664 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1665
1666 /* Enable the DMA channel */
1667 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1668 {
1669 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1670
1671 /* Process Unlocked */
1672 __HAL_UNLOCK(hhrtim);
1673
1674 return HAL_ERROR;
1675 }
1676
1677 /* Enable the timer DMA request */
1678 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
1679
1680 /* Enable the timer counter */
1681 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1682
1683 hhrtim->State = HAL_HRTIM_STATE_READY;
1684
1685 /* Process Unlocked */
1686 __HAL_UNLOCK(hhrtim);
1687
1688 return HAL_OK;
1689 }
1690
1691 /**
1692 * @brief Stop the output compare signal generation on the designed timer output
1693 * (DMA request is disabled).
1694 * @param hhrtim pointer to HAL HRTIM handle
1695 * @param TimerIdx Timer index
1696 * This parameter can be one of the following values:
1697 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1698 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1699 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1700 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1701 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1702 * @param OCChannel Timer output
1703 * This parameter can be one of the following values:
1704 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1705 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1706 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1707 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1708 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1709 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1710 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1711 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1712 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1713 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1714 * @retval HAL status
1715 */
HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1716 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
1717 uint32_t TimerIdx,
1718 uint32_t OCChannel)
1719 {
1720 uint32_t dma_request;
1721
1722 /* Check the parameters */
1723 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1724
1725 /* Process Locked */
1726 __HAL_LOCK(hhrtim);
1727
1728 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1729
1730 /* Disable the timer output */
1731 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1732
1733 /* Get the timer DMA handler */
1734 /* Disable the DMA */
1735 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
1736 {
1737 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1738
1739 /* Process Unlocked */
1740 __HAL_UNLOCK(hhrtim);
1741
1742 return HAL_ERROR;
1743 }
1744
1745 /* Get the DMA request to disable */
1746 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1747
1748 /* Disable the timer DMA request */
1749 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
1750
1751 /* Disable the timer counter */
1752 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1753
1754 hhrtim->State = HAL_HRTIM_STATE_READY;
1755
1756 /* Process Unlocked */
1757 __HAL_UNLOCK(hhrtim);
1758
1759 return HAL_OK;
1760 }
1761
1762 /**
1763 * @}
1764 */
1765
1766 /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
1767 * @brief Simple PWM output functions
1768 @verbatim
1769 ===============================================================================
1770 ##### Simple PWM output functions #####
1771 ===============================================================================
1772 [..] This section provides functions allowing to:
1773 (+) Configure simple PWM output channel
1774 (+) Start simple PWM output
1775 (+) Stop simple PWM output
1776 (+) Start simple PWM output and enable interrupt
1777 (+) Stop simple PWM output and disable interrupt
1778 (+) Start simple PWM output and enable DMA transfer
1779 (+) Stop simple PWM output and disable DMA transfer
1780 -@- When a HRTIM timer operates in simple PWM output mode
1781 the output level is set to a programmable value when a match is
1782 found between the compare register and the counter and reset when
1783 the timer period is reached. Duty cycle is determined by the
1784 comparison value.
1785 Compare unit 1 is automatically associated to output 1
1786 Compare unit 2 is automatically associated to output 2
1787 @endverbatim
1788 * @{
1789 */
1790
1791 /**
1792 * @brief Configure an output in simple PWM mode
1793 * @param hhrtim pointer to HAL HRTIM handle
1794 * @param TimerIdx Timer index
1795 * This parameter can be one of the following values:
1796 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1797 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1798 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1799 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1800 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1801 * @param PWMChannel Timer output
1802 * This parameter can be one of the following values:
1803 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1804 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1805 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1806 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1807 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1808 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1809 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1810 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1811 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1812 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1813 * @param pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
1814 * @note When the timer operates in simple PWM output mode:
1815 * Output 1 is implicitly controlled by the compare unit 1
1816 * Output 2 is implicitly controlled by the compare unit 2
1817 * Output Set/Reset crossbar is set as follows:
1818 * Output 1: SETx1R = CMP1, RSTx1R = PER
1819 * Output 2: SETx2R = CMP2, RST2R = PER
1820 * @note When Simple PWM mode is used the registers preload mechanism is
1821 * enabled (otherwise the behavior is not guaranteed).
1822 * @retval HAL status
1823 */
HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel,const HRTIM_SimplePWMChannelCfgTypeDef * pSimplePWMChannelCfg)1824 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
1825 uint32_t TimerIdx,
1826 uint32_t PWMChannel,
1827 const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg)
1828 {
1829 HRTIM_OutputCfgTypeDef OutputCfg;
1830 uint32_t hrtim_timcr;
1831
1832 /* Check parameters */
1833 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1834 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
1835 assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse));
1836 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
1837
1838 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
1839 {
1840 return HAL_BUSY;
1841 }
1842
1843 /* Process Locked */
1844 __HAL_LOCK(hhrtim);
1845
1846 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1847
1848 /* Configure timer compare unit */
1849 switch (PWMChannel)
1850 {
1851 case HRTIM_OUTPUT_TA1:
1852 case HRTIM_OUTPUT_TB1:
1853 case HRTIM_OUTPUT_TC1:
1854 case HRTIM_OUTPUT_TD1:
1855 case HRTIM_OUTPUT_TE1:
1856 {
1857 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse;
1858 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1859 break;
1860 }
1861
1862 case HRTIM_OUTPUT_TA2:
1863 case HRTIM_OUTPUT_TB2:
1864 case HRTIM_OUTPUT_TC2:
1865 case HRTIM_OUTPUT_TD2:
1866 case HRTIM_OUTPUT_TE2:
1867 {
1868 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse;
1869 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1870 break;
1871 }
1872 default:
1873 {
1874 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1875 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1876
1877 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1878
1879 /* Process Unlocked */
1880 __HAL_UNLOCK(hhrtim);
1881
1882 break;
1883 }
1884 }
1885
1886 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
1887 {
1888 return HAL_ERROR;
1889 }
1890
1891 /* Configure timer output */
1892 OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1);
1893 OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
1894 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1895 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1896 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1897 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1898 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
1899
1900 HRTIM_OutputConfig(hhrtim,
1901 TimerIdx,
1902 PWMChannel,
1903 &OutputCfg);
1904
1905 /* Enable the registers preload mechanism */
1906 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
1907 hrtim_timcr |= HRTIM_TIMCR_PREEN;
1908 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
1909
1910 hhrtim->State = HAL_HRTIM_STATE_READY;
1911
1912 /* Process Unlocked */
1913 __HAL_UNLOCK(hhrtim);
1914
1915 return HAL_OK;
1916 }
1917
1918 /**
1919 * @brief Start the PWM output signal generation on the designed timer output
1920 * @param hhrtim pointer to HAL HRTIM handle
1921 * @param TimerIdx Timer index
1922 * This parameter can be one of the following values:
1923 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1924 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1925 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1926 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1927 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1928 * @param PWMChannel Timer output
1929 * This parameter can be one of the following values:
1930 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1931 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1932 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1933 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1934 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1935 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1936 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1937 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1938 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1939 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1940 * @retval HAL status
1941 */
HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)1942 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
1943 uint32_t TimerIdx,
1944 uint32_t PWMChannel)
1945 {
1946 /* Check the parameters */
1947 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1948
1949 /* Process Locked */
1950 __HAL_LOCK(hhrtim);
1951
1952 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1953
1954 /* Enable the timer output */
1955 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
1956
1957 /* Enable the timer counter */
1958 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1959
1960 hhrtim->State = HAL_HRTIM_STATE_READY;
1961
1962 /* Process Unlocked */
1963 __HAL_UNLOCK(hhrtim);
1964
1965 return HAL_OK;
1966 }
1967
1968 /**
1969 * @brief Stop the PWM output signal generation on the designed timer output
1970 * @param hhrtim pointer to HAL HRTIM handle
1971 * @param TimerIdx Timer index
1972 * This parameter can be one of the following values:
1973 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1974 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1975 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1976 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1977 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1978 * @param PWMChannel Timer output
1979 * This parameter can be one of the following values:
1980 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1981 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1982 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1983 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1984 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1985 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1986 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1987 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1988 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1989 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1990 * @retval HAL status
1991 */
HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)1992 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
1993 uint32_t TimerIdx,
1994 uint32_t PWMChannel)
1995 {
1996 /* Check the parameters */
1997 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1998
1999 /* Process Locked */
2000 __HAL_LOCK(hhrtim);
2001
2002 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2003
2004 /* Disable the timer output */
2005 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2006
2007 /* Disable the timer counter */
2008 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2009
2010 hhrtim->State = HAL_HRTIM_STATE_READY;
2011
2012 /* Process Unlocked */
2013 __HAL_UNLOCK(hhrtim);
2014
2015 return HAL_OK;
2016 }
2017
2018 /**
2019 * @brief Start the PWM output signal generation on the designed timer output
2020 * (The compare interrupt is enabled).
2021 * @param hhrtim pointer to HAL HRTIM handle
2022 * @param TimerIdx Timer index
2023 * This parameter can be one of the following values:
2024 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2025 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2026 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2027 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2028 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2029 * @param PWMChannel Timer output
2030 * This parameter can be one of the following values:
2031 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2032 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2033 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2034 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2035 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2036 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2037 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2038 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2039 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2040 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2041 * @retval HAL status
2042 */
HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2043 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
2044 uint32_t TimerIdx,
2045 uint32_t PWMChannel)
2046 {
2047 /* Check the parameters */
2048 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2049
2050 /* Process Locked */
2051 __HAL_LOCK(hhrtim);
2052
2053 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2054
2055 /* Enable the timer output */
2056 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2057
2058 /* Enable the timer interrupt (depends on the PWM output) */
2059 switch (PWMChannel)
2060 {
2061 case HRTIM_OUTPUT_TA1:
2062 case HRTIM_OUTPUT_TB1:
2063 case HRTIM_OUTPUT_TC1:
2064 case HRTIM_OUTPUT_TD1:
2065 case HRTIM_OUTPUT_TE1:
2066 {
2067 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2068 break;
2069 }
2070
2071 case HRTIM_OUTPUT_TA2:
2072 case HRTIM_OUTPUT_TB2:
2073 case HRTIM_OUTPUT_TC2:
2074 case HRTIM_OUTPUT_TD2:
2075 case HRTIM_OUTPUT_TE2:
2076 {
2077 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2078 break;
2079 }
2080
2081 default:
2082 {
2083 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2084
2085 /* Process Unlocked */
2086 __HAL_UNLOCK(hhrtim);
2087
2088 break;
2089 }
2090 }
2091
2092 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2093 {
2094 return HAL_ERROR;
2095 }
2096
2097 /* Enable the timer counter */
2098 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2099
2100 hhrtim->State = HAL_HRTIM_STATE_READY;
2101
2102 /* Process Unlocked */
2103 __HAL_UNLOCK(hhrtim);
2104
2105 return HAL_OK;
2106 }
2107
2108 /**
2109 * @brief Stop the PWM output signal generation on the designed timer output
2110 * (The compare interrupt is disabled).
2111 * @param hhrtim pointer to HAL HRTIM handle
2112 * @param TimerIdx Timer index
2113 * This parameter can be one of the following values:
2114 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2115 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2116 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2117 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2118 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2119 * @param PWMChannel Timer output
2120 * This parameter can be one of the following values:
2121 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2122 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2123 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2124 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2125 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2126 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2127 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2128 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2129 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2130 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2131 * @retval HAL status
2132 */
HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2133 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
2134 uint32_t TimerIdx,
2135 uint32_t PWMChannel)
2136 {
2137 /* Check the parameters */
2138 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2139
2140 /* Process Locked */
2141 __HAL_LOCK(hhrtim);
2142
2143 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2144
2145 /* Disable the timer output */
2146 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2147
2148 /* Disable the timer interrupt (depends on the PWM output) */
2149 switch (PWMChannel)
2150 {
2151 case HRTIM_OUTPUT_TA1:
2152 case HRTIM_OUTPUT_TB1:
2153 case HRTIM_OUTPUT_TC1:
2154 case HRTIM_OUTPUT_TD1:
2155 case HRTIM_OUTPUT_TE1:
2156 {
2157 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2158 break;
2159 }
2160
2161 case HRTIM_OUTPUT_TA2:
2162 case HRTIM_OUTPUT_TB2:
2163 case HRTIM_OUTPUT_TC2:
2164 case HRTIM_OUTPUT_TD2:
2165 case HRTIM_OUTPUT_TE2:
2166 {
2167 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2168 break;
2169 }
2170
2171 default:
2172 {
2173 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2174
2175 /* Process Unlocked */
2176 __HAL_UNLOCK(hhrtim);
2177
2178 break;
2179 }
2180 }
2181
2182 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2183 {
2184 return HAL_ERROR;
2185 }
2186
2187 /* Disable the timer counter */
2188 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2189
2190 hhrtim->State = HAL_HRTIM_STATE_READY;
2191
2192 /* Process Unlocked */
2193 __HAL_UNLOCK(hhrtim);
2194
2195 return HAL_OK;
2196 }
2197
2198 /**
2199 * @brief Start the PWM output signal generation on the designed timer output
2200 * (The compare DMA request is enabled).
2201 * @param hhrtim pointer to HAL HRTIM handle
2202 * @param TimerIdx Timer index
2203 * This parameter can be one of the following values:
2204 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2205 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2206 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2207 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2208 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2209 * @param PWMChannel Timer output
2210 * This parameter can be one of the following values:
2211 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2212 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2213 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2214 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2215 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2216 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2217 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2218 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2219 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2220 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2221 * @param SrcAddr DMA transfer source address
2222 * @param DestAddr DMA transfer destination address
2223 * @param Length The length of data items (data size) to be transferred
2224 * from source to destination
2225 * @retval HAL status
2226 */
HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)2227 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
2228 uint32_t TimerIdx,
2229 uint32_t PWMChannel,
2230 uint32_t SrcAddr,
2231 uint32_t DestAddr,
2232 uint32_t Length)
2233 {
2234 DMA_HandleTypeDef *hdma;
2235
2236 /* Check the parameters */
2237 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2238
2239 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
2240 {
2241 return HAL_BUSY;
2242 }
2243 if (hhrtim->State == HAL_HRTIM_STATE_READY)
2244 {
2245 if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U))
2246 {
2247 return HAL_ERROR;
2248 }
2249 else
2250 {
2251 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2252 }
2253 }
2254
2255 /* Process Locked */
2256 __HAL_LOCK(hhrtim);
2257
2258 /* Enable the timer output */
2259 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2260
2261 /* Get the timer DMA handler */
2262 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2263
2264 if (hdma == NULL)
2265 {
2266 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2267
2268 /* Process Unlocked */
2269 __HAL_UNLOCK(hhrtim);
2270
2271 return HAL_ERROR;
2272 }
2273
2274 /* Set the DMA error callback */
2275 hdma->XferErrorCallback = HRTIM_DMAError ;
2276
2277 /* Set the DMA transfer completed callback */
2278 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2279
2280 /* Enable the DMA channel */
2281 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
2282 {
2283 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2284
2285 /* Process Unlocked */
2286 __HAL_UNLOCK(hhrtim);
2287
2288 return HAL_ERROR;
2289 }
2290
2291 /* Enable the timer DMA request */
2292 switch (PWMChannel)
2293 {
2294 case HRTIM_OUTPUT_TA1:
2295 case HRTIM_OUTPUT_TB1:
2296 case HRTIM_OUTPUT_TC1:
2297 case HRTIM_OUTPUT_TD1:
2298 case HRTIM_OUTPUT_TE1:
2299 {
2300 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2301 break;
2302 }
2303
2304 case HRTIM_OUTPUT_TA2:
2305 case HRTIM_OUTPUT_TB2:
2306 case HRTIM_OUTPUT_TC2:
2307 case HRTIM_OUTPUT_TD2:
2308 case HRTIM_OUTPUT_TE2:
2309 {
2310 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2311 break;
2312 }
2313
2314 default:
2315 {
2316 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2317
2318 /* Process Unlocked */
2319 __HAL_UNLOCK(hhrtim);
2320
2321 break;
2322 }
2323 }
2324
2325 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2326 {
2327 return HAL_ERROR;
2328 }
2329
2330 /* Enable the timer counter */
2331 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2332
2333 hhrtim->State = HAL_HRTIM_STATE_READY;
2334
2335 /* Process Unlocked */
2336 __HAL_UNLOCK(hhrtim);
2337
2338 return HAL_OK;
2339 }
2340
2341 /**
2342 * @brief Stop the PWM output signal generation on the designed timer output
2343 * (The compare DMA request is disabled).
2344 * @param hhrtim pointer to HAL HRTIM handle
2345 * @param TimerIdx Timer index
2346 * This parameter can be one of the following values:
2347 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2348 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2349 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2350 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2351 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2352 * @param PWMChannel Timer output
2353 * This parameter can be one of the following values:
2354 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2355 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2356 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2357 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2358 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2359 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2360 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2361 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2362 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2363 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2364 * @retval HAL status
2365 */
HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2366 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
2367 uint32_t TimerIdx,
2368 uint32_t PWMChannel)
2369 {
2370 /* Check the parameters */
2371 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2372
2373 /* Process Locked */
2374 __HAL_LOCK(hhrtim);
2375
2376 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2377
2378 /* Disable the timer output */
2379 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2380
2381 /* Get the timer DMA handler */
2382 /* Disable the DMA */
2383 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
2384 {
2385 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2386
2387 /* Process Unlocked */
2388 __HAL_UNLOCK(hhrtim);
2389
2390 return HAL_ERROR;
2391 }
2392
2393 /* Disable the timer DMA request */
2394 switch (PWMChannel)
2395 {
2396 case HRTIM_OUTPUT_TA1:
2397 case HRTIM_OUTPUT_TB1:
2398 case HRTIM_OUTPUT_TC1:
2399 case HRTIM_OUTPUT_TD1:
2400 case HRTIM_OUTPUT_TE1:
2401 {
2402 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2403 break;
2404 }
2405
2406 case HRTIM_OUTPUT_TA2:
2407 case HRTIM_OUTPUT_TB2:
2408 case HRTIM_OUTPUT_TC2:
2409 case HRTIM_OUTPUT_TD2:
2410 case HRTIM_OUTPUT_TE2:
2411 {
2412 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2413 break;
2414 }
2415
2416 default:
2417 {
2418 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2419
2420 /* Process Unlocked */
2421 __HAL_UNLOCK(hhrtim);
2422
2423 break;
2424 }
2425 }
2426
2427 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2428 {
2429 return HAL_ERROR;
2430 }
2431
2432 /* Disable the timer counter */
2433 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2434
2435 hhrtim->State = HAL_HRTIM_STATE_READY;
2436
2437 /* Process Unlocked */
2438 __HAL_UNLOCK(hhrtim);
2439
2440 return HAL_OK;
2441 }
2442
2443 /**
2444 * @}
2445 */
2446
2447 /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
2448 * @brief Simple input capture functions
2449 @verbatim
2450 ===============================================================================
2451 ##### Simple input capture functions #####
2452 ===============================================================================
2453 [..] This section provides functions allowing to:
2454 (+) Configure simple input capture channel
2455 (+) Start simple input capture
2456 (+) Stop simple input capture
2457 (+) Start simple input capture and enable interrupt
2458 (+) Stop simple input capture and disable interrupt
2459 (+) Start simple input capture and enable DMA transfer
2460 (+) Stop simple input capture and disable DMA transfer
2461 -@- When a HRTIM timer operates in simple input capture mode
2462 the Capture Register (HRTIM_CPT1/2xR) is used to latch the
2463 value of the timer counter counter after a transition detected
2464 on a given external event input.
2465 @endverbatim
2466 * @{
2467 */
2468
2469 /**
2470 * @brief Configure a simple capture
2471 * @param hhrtim pointer to HAL HRTIM handle
2472 * @param TimerIdx Timer index
2473 * This parameter can be one of the following values:
2474 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2475 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2476 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2477 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2478 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2479 * @param CaptureChannel Capture unit
2480 * This parameter can be one of the following values:
2481 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2482 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2483 * @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
2484 * @note When the timer operates in simple capture mode the capture is triggered
2485 * by the designated external event and GPIO input is implicitly used as event source.
2486 * The cature can be triggered by a rising edge, a falling edge or both
2487 * edges on event channel.
2488 * @retval HAL status
2489 */
HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel,const HRTIM_SimpleCaptureChannelCfgTypeDef * pSimpleCaptureChannelCfg)2490 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
2491 uint32_t TimerIdx,
2492 uint32_t CaptureChannel,
2493 const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg)
2494 {
2495 HRTIM_EventCfgTypeDef EventCfg;
2496
2497 /* Check parameters */
2498 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2499 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2500 assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
2501 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
2502 pSimpleCaptureChannelCfg->EventPolarity));
2503 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
2504 assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
2505 pSimpleCaptureChannelCfg->EventFilter));
2506
2507 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
2508 {
2509 return HAL_BUSY;
2510 }
2511
2512 /* Process Locked */
2513 __HAL_LOCK(hhrtim);
2514
2515 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2516
2517 /* Configure external event channel */
2518 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
2519 EventCfg.Filter = (pSimpleCaptureChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
2520 EventCfg.Polarity = (pSimpleCaptureChannelCfg->EventPolarity & HRTIM_EECR1_EE1POL);
2521 EventCfg.Sensitivity = (pSimpleCaptureChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
2522 EventCfg.Source = HRTIM_EVENTSRC_1;
2523
2524 HRTIM_EventConfig(hhrtim,
2525 pSimpleCaptureChannelCfg->Event,
2526 &EventCfg);
2527
2528 /* Memorize capture trigger (will be configured when the capture is started */
2529 HRTIM_CaptureUnitConfig(hhrtim,
2530 TimerIdx,
2531 CaptureChannel,
2532 pSimpleCaptureChannelCfg->Event);
2533
2534 hhrtim->State = HAL_HRTIM_STATE_READY;
2535
2536 /* Process Unlocked */
2537 __HAL_UNLOCK(hhrtim);
2538
2539 return HAL_OK;
2540 }
2541
2542 /**
2543 * @brief Enable a simple capture on the designed capture unit
2544 * @param hhrtim pointer to HAL HRTIM handle
2545 * @param TimerIdx Timer index
2546 * This parameter can be one of the following values:
2547 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2548 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2549 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2550 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2551 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2552 * @param CaptureChannel Timer output
2553 * This parameter can be one of the following values:
2554 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2555 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2556 * @retval HAL status
2557 * @note The external event triggering the capture is available for all timing
2558 * units. It can be used directly and is active as soon as the timing
2559 * unit counter is enabled.
2560 */
HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2561 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
2562 uint32_t TimerIdx,
2563 uint32_t CaptureChannel)
2564 {
2565 /* Check the parameters */
2566 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2567 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2568
2569 /* Process Locked */
2570 __HAL_LOCK(hhrtim);
2571
2572 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2573
2574 /* Set the capture unit trigger */
2575 switch (CaptureChannel)
2576 {
2577 case HRTIM_CAPTUREUNIT_1:
2578 {
2579 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2580 break;
2581 }
2582
2583 case HRTIM_CAPTUREUNIT_2:
2584 {
2585 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2586 break;
2587 }
2588
2589 default:
2590 {
2591 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2592
2593 /* Process Unlocked */
2594 __HAL_UNLOCK(hhrtim);
2595
2596 break;
2597 }
2598 }
2599
2600 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2601 {
2602 return HAL_ERROR;
2603 }
2604
2605 /* Enable the timer counter */
2606 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2607
2608 hhrtim->State = HAL_HRTIM_STATE_READY;
2609
2610 /* Process Unlocked */
2611 __HAL_UNLOCK(hhrtim);
2612
2613 return HAL_OK;
2614 }
2615
2616 /**
2617 * @brief Disable a simple capture on the designed capture unit
2618 * @param hhrtim pointer to HAL HRTIM handle
2619 * @param TimerIdx Timer index
2620 * This parameter can be one of the following values:
2621 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2622 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2623 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2624 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2625 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2626 * @param CaptureChannel Timer output
2627 * This parameter can be one of the following values:
2628 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2629 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2630 * @retval HAL status
2631 */
HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2632 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
2633 uint32_t TimerIdx,
2634 uint32_t CaptureChannel)
2635 {
2636 uint32_t hrtim_cpt1cr;
2637 uint32_t hrtim_cpt2cr;
2638
2639 /* Check the parameters */
2640 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2641 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2642
2643 /* Process Locked */
2644 __HAL_LOCK(hhrtim);
2645
2646 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2647
2648 /* Set the capture unit trigger */
2649 switch (CaptureChannel)
2650 {
2651 case HRTIM_CAPTUREUNIT_1:
2652 {
2653 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2654 break;
2655 }
2656
2657 case HRTIM_CAPTUREUNIT_2:
2658 {
2659 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2660 break;
2661 }
2662
2663 default:
2664 {
2665 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2666
2667 /* Process Unlocked */
2668 __HAL_UNLOCK(hhrtim);
2669
2670 break;
2671 }
2672 }
2673
2674 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2675 {
2676 return HAL_ERROR;
2677 }
2678
2679 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
2680 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
2681
2682 /* Disable the timer counter */
2683 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
2684 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
2685 {
2686 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2687 }
2688
2689 hhrtim->State = HAL_HRTIM_STATE_READY;
2690
2691 /* Process Unlocked */
2692 __HAL_UNLOCK(hhrtim);
2693
2694 return HAL_OK;
2695 }
2696
2697 /**
2698 * @brief Enable a simple capture on the designed capture unit
2699 * (Capture interrupt is enabled).
2700 * @param hhrtim pointer to HAL HRTIM handle
2701 * @param TimerIdx Timer index
2702 * This parameter can be one of the following values:
2703 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2704 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2705 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2706 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2707 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2708 * @param CaptureChannel Timer output
2709 * This parameter can be one of the following values:
2710 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2711 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2712 * @retval HAL status
2713 */
HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2714 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
2715 uint32_t TimerIdx,
2716 uint32_t CaptureChannel)
2717 {
2718 /* Check the parameters */
2719 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2720 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2721
2722 /* Process Locked */
2723 __HAL_LOCK(hhrtim);
2724
2725 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2726
2727 /* Set the capture unit trigger */
2728 switch (CaptureChannel)
2729 {
2730 case HRTIM_CAPTUREUNIT_1:
2731 {
2732 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2733
2734 /* Enable the capture unit 1 interrupt */
2735 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2736 break;
2737 }
2738
2739 case HRTIM_CAPTUREUNIT_2:
2740 {
2741 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2742
2743 /* Enable the capture unit 2 interrupt */
2744 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2745 break;
2746 }
2747
2748 default:
2749 {
2750 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2751
2752 /* Process Unlocked */
2753 __HAL_UNLOCK(hhrtim);
2754
2755 break;
2756 }
2757 }
2758
2759 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2760 {
2761 return HAL_ERROR;
2762 }
2763
2764 /* Enable the timer counter */
2765 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2766
2767 hhrtim->State = HAL_HRTIM_STATE_READY;
2768
2769 /* Process Unlocked */
2770 __HAL_UNLOCK(hhrtim);
2771
2772 return HAL_OK;
2773 }
2774
2775 /**
2776 * @brief Disable a simple capture on the designed capture unit
2777 * (Capture interrupt is disabled).
2778 * @param hhrtim pointer to HAL HRTIM handle
2779 * @param TimerIdx Timer index
2780 * This parameter can be one of the following values:
2781 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2782 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2783 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2784 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2785 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2786 * @param CaptureChannel Timer output
2787 * This parameter can be one of the following values:
2788 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2789 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2790 * @retval HAL status
2791 */
HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2792 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
2793 uint32_t TimerIdx,
2794 uint32_t CaptureChannel)
2795 {
2796
2797 uint32_t hrtim_cpt1cr;
2798 uint32_t hrtim_cpt2cr;
2799
2800 /* Check the parameters */
2801 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2802 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2803
2804 /* Process Locked */
2805 __HAL_LOCK(hhrtim);
2806
2807 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2808
2809 /* Set the capture unit trigger */
2810 switch (CaptureChannel)
2811 {
2812 case HRTIM_CAPTUREUNIT_1:
2813 {
2814 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2815
2816 /* Disable the capture unit 1 interrupt */
2817 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2818 break;
2819 }
2820
2821 case HRTIM_CAPTUREUNIT_2:
2822 {
2823 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2824
2825 /* Disable the capture unit 2 interrupt */
2826 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2827 break;
2828 }
2829
2830 default:
2831 {
2832 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2833
2834 /* Process Unlocked */
2835 __HAL_UNLOCK(hhrtim);
2836
2837 break;
2838 }
2839 }
2840
2841 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2842 {
2843 return HAL_ERROR;
2844 }
2845
2846 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
2847 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
2848
2849 /* Disable the timer counter */
2850 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
2851 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
2852 {
2853 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2854 }
2855
2856 hhrtim->State = HAL_HRTIM_STATE_READY;
2857
2858 /* Process Unlocked */
2859 __HAL_UNLOCK(hhrtim);
2860
2861 return HAL_OK;
2862 }
2863
2864 /**
2865 * @brief Enable a simple capture on the designed capture unit
2866 * (Capture DMA request is enabled).
2867 * @param hhrtim pointer to HAL HRTIM handle
2868 * @param TimerIdx Timer index
2869 * This parameter can be one of the following values:
2870 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2871 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2872 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2873 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2874 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2875 * @param CaptureChannel Timer output
2876 * This parameter can be one of the following values:
2877 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2878 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2879 * @param SrcAddr DMA transfer source address
2880 * @param DestAddr DMA transfer destination address
2881 * @param Length The length of data items (data size) to be transferred
2882 * from source to destination
2883 * @retval HAL status
2884 */
HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)2885 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
2886 uint32_t TimerIdx,
2887 uint32_t CaptureChannel,
2888 uint32_t SrcAddr,
2889 uint32_t DestAddr,
2890 uint32_t Length)
2891 {
2892 DMA_HandleTypeDef *hdma;
2893
2894 /* Check the parameters */
2895 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2896 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2897
2898 /* Process Locked */
2899 __HAL_LOCK(hhrtim);
2900
2901 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2902
2903 /* Get the timer DMA handler */
2904 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2905
2906 if (hdma == NULL)
2907 {
2908 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2909
2910 /* Process Unlocked */
2911 __HAL_UNLOCK(hhrtim);
2912
2913 return HAL_ERROR;
2914 }
2915
2916 /* Set the DMA error callback */
2917 hdma->XferErrorCallback = HRTIM_DMAError ;
2918
2919 /* Set the DMA transfer completed callback */
2920 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2921
2922 /* Enable the DMA channel */
2923 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
2924 {
2925 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2926
2927 /* Process Unlocked */
2928 __HAL_UNLOCK(hhrtim);
2929
2930 return HAL_ERROR;
2931 }
2932
2933 switch (CaptureChannel)
2934 {
2935 case HRTIM_CAPTUREUNIT_1:
2936 {
2937 /* Set the capture unit trigger */
2938 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2939
2940 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
2941 break;
2942 }
2943
2944 case HRTIM_CAPTUREUNIT_2:
2945 {
2946 /* Set the capture unit trigger */
2947 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2948
2949 /* Enable the timer DMA request */
2950 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
2951 break;
2952 }
2953
2954 default:
2955 {
2956 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2957
2958 /* Process Unlocked */
2959 __HAL_UNLOCK(hhrtim);
2960
2961 break;
2962 }
2963 }
2964
2965 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2966 {
2967 return HAL_ERROR;
2968 }
2969
2970 /* Enable the timer counter */
2971 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2972
2973 hhrtim->State = HAL_HRTIM_STATE_READY;
2974
2975 /* Process Unlocked */
2976 __HAL_UNLOCK(hhrtim);
2977
2978 return HAL_OK;
2979 }
2980
2981 /**
2982 * @brief Disable a simple capture on the designed capture unit
2983 * (Capture DMA request is disabled).
2984 * @param hhrtim pointer to HAL HRTIM handle
2985 * @param TimerIdx Timer index
2986 * This parameter can be one of the following values:
2987 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2988 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2989 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2990 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2991 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2992 * @param CaptureChannel Timer output
2993 * This parameter can be one of the following values:
2994 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2995 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2996 * @retval HAL status
2997 */
HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2998 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
2999 uint32_t TimerIdx,
3000 uint32_t CaptureChannel)
3001 {
3002
3003 uint32_t hrtim_cpt1cr;
3004 uint32_t hrtim_cpt2cr;
3005
3006 /* Check the parameters */
3007 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3008 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3009
3010 /* Process Locked */
3011 __HAL_LOCK(hhrtim);
3012
3013 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3014
3015 /* Get the timer DMA handler */
3016 /* Disable the DMA */
3017 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
3018 {
3019 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3020
3021 /* Process Unlocked */
3022 __HAL_UNLOCK(hhrtim);
3023
3024 return HAL_ERROR;
3025 }
3026
3027 switch (CaptureChannel)
3028 {
3029 case HRTIM_CAPTUREUNIT_1:
3030 {
3031 /* Reset the capture unit trigger */
3032 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
3033
3034 /* Disable the capture unit 1 DMA request */
3035 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
3036 break;
3037 }
3038
3039 case HRTIM_CAPTUREUNIT_2:
3040 {
3041 /* Reset the capture unit trigger */
3042 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
3043
3044 /* Disable the capture unit 2 DMA request */
3045 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
3046 break;
3047 }
3048
3049 default:
3050 {
3051 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3052
3053 /* Process Unlocked */
3054 __HAL_UNLOCK(hhrtim);
3055
3056 break;
3057 }
3058 }
3059
3060 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
3061 {
3062 return HAL_ERROR;
3063 }
3064
3065 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
3066 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
3067
3068 /* Disable the timer counter */
3069 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
3070 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
3071 {
3072 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3073 }
3074
3075 hhrtim->State = HAL_HRTIM_STATE_READY;
3076
3077 /* Process Unlocked */
3078 __HAL_UNLOCK(hhrtim);
3079
3080 return HAL_OK;
3081 }
3082
3083 /**
3084 * @}
3085 */
3086
3087 /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
3088 * @brief Simple one pulse functions
3089 @verbatim
3090 ===============================================================================
3091 ##### Simple one pulse functions #####
3092 ===============================================================================
3093 [..] This section provides functions allowing to:
3094 (+) Configure one pulse channel
3095 (+) Start one pulse generation
3096 (+) Stop one pulse generation
3097 (+) Start one pulse generation and enable interrupt
3098 (+) Stop one pulse generation and disable interrupt
3099 -@- When a HRTIM timer operates in simple one pulse mode
3100 the timer counter is started in response to transition detected
3101 on a given external event input to generate a pulse with a
3102 programmable length after a programmable delay.
3103 @endverbatim
3104 * @{
3105 */
3106
3107 /**
3108 * @brief Configure an output simple one pulse mode
3109 * @param hhrtim pointer to HAL HRTIM handle
3110 * @param TimerIdx Timer index
3111 * This parameter can be one of the following values:
3112 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3113 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3114 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3115 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3116 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3117 * @param OnePulseChannel Timer output
3118 * This parameter can be one of the following values:
3119 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3120 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3121 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3122 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3123 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3124 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3125 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3126 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3127 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3128 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3129 * @param pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
3130 * @note When the timer operates in simple one pulse mode:
3131 * the timer counter is implicitly started by the reset event,
3132 * the reset of the timer counter is triggered by the designated external event
3133 * GPIO input is implicitly used as event source,
3134 * Output 1 is implicitly controlled by the compare unit 1,
3135 * Output 2 is implicitly controlled by the compare unit 2.
3136 * Output Set/Reset crossbar is set as follows:
3137 * Output 1: SETx1R = CMP1, RSTx1R = PER
3138 * Output 2: SETx2R = CMP2, RST2R = PER
3139 * @retval HAL status
3140 * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
3141 * outputs, the reset event related configuration data provided in the
3142 * second call will override the reset event related configuration data
3143 * provided in the first call.
3144 */
HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel,const HRTIM_SimpleOnePulseChannelCfgTypeDef * pSimpleOnePulseChannelCfg)3145 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
3146 uint32_t TimerIdx,
3147 uint32_t OnePulseChannel,
3148 const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg)
3149 {
3150 HRTIM_OutputCfgTypeDef OutputCfg;
3151 HRTIM_EventCfgTypeDef EventCfg;
3152
3153 /* Check parameters */
3154 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3155 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOnePulseChannelCfg->Pulse));
3156 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
3157 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
3158 assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
3159 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
3160 pSimpleOnePulseChannelCfg->EventPolarity));
3161 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
3162 assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
3163 pSimpleOnePulseChannelCfg->EventFilter));
3164
3165 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
3166 {
3167 return HAL_BUSY;
3168 }
3169
3170 /* Process Locked */
3171 __HAL_LOCK(hhrtim);
3172
3173 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3174
3175 /* Configure timer compare unit */
3176 switch (OnePulseChannel)
3177 {
3178 case HRTIM_OUTPUT_TA1:
3179 case HRTIM_OUTPUT_TB1:
3180 case HRTIM_OUTPUT_TC1:
3181 case HRTIM_OUTPUT_TD1:
3182 case HRTIM_OUTPUT_TE1:
3183 {
3184 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse;
3185 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
3186 break;
3187 }
3188
3189 case HRTIM_OUTPUT_TA2:
3190 case HRTIM_OUTPUT_TB2:
3191 case HRTIM_OUTPUT_TC2:
3192 case HRTIM_OUTPUT_TD2:
3193 case HRTIM_OUTPUT_TE2:
3194 {
3195 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse;
3196 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
3197 break;
3198 }
3199
3200 default:
3201 {
3202 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
3203 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
3204
3205 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3206
3207 /* Process Unlocked */
3208 __HAL_UNLOCK(hhrtim);
3209
3210 break;
3211 }
3212 }
3213
3214 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
3215 {
3216 return HAL_ERROR;
3217 }
3218
3219 /* Configure timer output */
3220 OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1);
3221 OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1);
3222 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
3223 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
3224 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
3225 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
3226 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
3227
3228 HRTIM_OutputConfig(hhrtim,
3229 TimerIdx,
3230 OnePulseChannel,
3231 &OutputCfg);
3232
3233 /* Configure external event channel */
3234 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
3235 EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
3236 EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1);
3237 EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
3238 EventCfg.Source = HRTIM_EVENTSRC_1;
3239
3240 HRTIM_EventConfig(hhrtim,
3241 pSimpleOnePulseChannelCfg->Event,
3242 &EventCfg);
3243
3244 /* Configure the timer reset register */
3245 HRTIM_TIM_ResetConfig(hhrtim,
3246 TimerIdx,
3247 pSimpleOnePulseChannelCfg->Event);
3248
3249 hhrtim->State = HAL_HRTIM_STATE_READY;
3250
3251 /* Process Unlocked */
3252 __HAL_UNLOCK(hhrtim);
3253
3254 return HAL_OK;
3255 }
3256
3257 /**
3258 * @brief Enable the simple one pulse signal generation on the designed output
3259 * @param hhrtim pointer to HAL HRTIM handle
3260 * @param TimerIdx Timer index
3261 * This parameter can be one of the following values:
3262 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3263 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3264 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3265 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3266 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3267 * @param OnePulseChannel Timer output
3268 * This parameter can be one of the following values:
3269 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3270 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3271 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3272 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3273 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3274 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3275 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3276 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3277 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3278 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3279 * @retval HAL status
3280 */
HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3281 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
3282 uint32_t TimerIdx,
3283 uint32_t OnePulseChannel)
3284 {
3285 /* Check the parameters */
3286 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3287
3288 /* Process Locked */
3289 __HAL_LOCK(hhrtim);
3290
3291 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3292
3293 /* Enable the timer output */
3294 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3295
3296 /* Enable the timer counter */
3297 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3298
3299 hhrtim->State = HAL_HRTIM_STATE_READY;
3300
3301 /* Process Unlocked */
3302 __HAL_UNLOCK(hhrtim);
3303
3304 return HAL_OK;
3305 }
3306
3307 /**
3308 * @brief Disable the simple one pulse signal generation on the designed output
3309 * @param hhrtim pointer to HAL HRTIM handle
3310 * @param TimerIdx Timer index
3311 * This parameter can be one of the following values:
3312 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3313 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3314 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3315 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3316 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3317 * @param OnePulseChannel Timer output
3318 * This parameter can be one of the following values:
3319 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3320 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3321 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3322 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3323 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3324 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3325 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3326 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3327 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3328 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3329 * @retval HAL status
3330 */
HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3331 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
3332 uint32_t TimerIdx,
3333 uint32_t OnePulseChannel)
3334 {
3335 /* Check the parameters */
3336 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3337
3338 /* Process Locked */
3339 __HAL_LOCK(hhrtim);
3340
3341 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3342
3343 /* Disable the timer output */
3344 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3345
3346 /* Disable the timer counter */
3347 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3348
3349 hhrtim->State = HAL_HRTIM_STATE_READY;
3350
3351 /* Process Unlocked */
3352 __HAL_UNLOCK(hhrtim);
3353
3354 return HAL_OK;
3355 }
3356
3357 /**
3358 * @brief Enable the simple one pulse signal generation on the designed output
3359 * (The compare interrupt is enabled (pulse start)).
3360 * @param hhrtim pointer to HAL HRTIM handle
3361 * @param TimerIdx Timer index
3362 * This parameter can be one of the following values:
3363 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3364 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3365 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3366 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3367 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3368 * @param OnePulseChannel Timer output
3369 * This parameter can be one of the following values:
3370 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3371 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3372 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3373 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3374 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3375 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3376 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3377 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3378 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3379 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3380 * @retval HAL status
3381 */
HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3382 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
3383 uint32_t TimerIdx,
3384 uint32_t OnePulseChannel)
3385 {
3386 /* Check the parameters */
3387 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3388
3389 /* Process Locked */
3390 __HAL_LOCK(hhrtim);
3391
3392 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3393
3394 /* Enable the timer output */
3395 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3396
3397 /* Enable the timer interrupt (depends on the OnePulse output) */
3398 switch (OnePulseChannel)
3399 {
3400 case HRTIM_OUTPUT_TA1:
3401 case HRTIM_OUTPUT_TB1:
3402 case HRTIM_OUTPUT_TC1:
3403 case HRTIM_OUTPUT_TD1:
3404 case HRTIM_OUTPUT_TE1:
3405 {
3406 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3407 break;
3408 }
3409
3410 case HRTIM_OUTPUT_TA2:
3411 case HRTIM_OUTPUT_TB2:
3412 case HRTIM_OUTPUT_TC2:
3413 case HRTIM_OUTPUT_TD2:
3414 case HRTIM_OUTPUT_TE2:
3415 {
3416 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3417 break;
3418 }
3419
3420 default:
3421 {
3422 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3423
3424 /* Process Unlocked */
3425 __HAL_UNLOCK(hhrtim);
3426
3427 break;
3428 }
3429 }
3430
3431 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
3432 {
3433 return HAL_ERROR;
3434 }
3435
3436 /* Enable the timer counter */
3437 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3438
3439 hhrtim->State = HAL_HRTIM_STATE_READY;
3440
3441 /* Process Unlocked */
3442 __HAL_UNLOCK(hhrtim);
3443
3444 return HAL_OK;
3445 }
3446
3447 /**
3448 * @brief Disable the simple one pulse signal generation on the designed output
3449 * (The compare interrupt is disabled).
3450 * @param hhrtim pointer to HAL HRTIM handle
3451 * @param TimerIdx Timer index
3452 * This parameter can be one of the following values:
3453 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3454 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3455 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3456 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3457 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3458 * @param OnePulseChannel Timer output
3459 * This parameter can be one of the following values:
3460 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3461 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3462 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3463 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3464 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3465 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3466 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3467 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3468 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3469 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3470 * @retval HAL status
3471 */
HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3472 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
3473 uint32_t TimerIdx,
3474 uint32_t OnePulseChannel)
3475 {
3476 /* Check the parameters */
3477 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3478
3479 /* Process Locked */
3480 __HAL_LOCK(hhrtim);
3481
3482 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3483
3484 /* Disable the timer output */
3485 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3486
3487 /* Disable the timer interrupt (depends on the OnePulse output) */
3488 switch (OnePulseChannel)
3489 {
3490 case HRTIM_OUTPUT_TA1:
3491 case HRTIM_OUTPUT_TB1:
3492 case HRTIM_OUTPUT_TC1:
3493 case HRTIM_OUTPUT_TD1:
3494 case HRTIM_OUTPUT_TE1:
3495 {
3496 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3497 break;
3498 }
3499
3500 case HRTIM_OUTPUT_TA2:
3501 case HRTIM_OUTPUT_TB2:
3502 case HRTIM_OUTPUT_TC2:
3503 case HRTIM_OUTPUT_TD2:
3504 case HRTIM_OUTPUT_TE2:
3505 {
3506 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3507 break;
3508 }
3509
3510 default:
3511 {
3512 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3513
3514 /* Process Unlocked */
3515 __HAL_UNLOCK(hhrtim);
3516
3517 break;
3518 }
3519 }
3520
3521 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
3522 {
3523 return HAL_ERROR;
3524 }
3525
3526 /* Disable the timer counter */
3527 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3528
3529 hhrtim->State = HAL_HRTIM_STATE_READY;
3530
3531 /* Process Unlocked */
3532 __HAL_UNLOCK(hhrtim);
3533
3534 return HAL_OK;
3535 }
3536
3537 /**
3538 * @}
3539 */
3540
3541 /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
3542 * @brief HRTIM configuration functions
3543 @verbatim
3544 ===============================================================================
3545 ##### HRTIM configuration functions #####
3546 ===============================================================================
3547 [..] This section provides functions allowing to configure the HRTIM
3548 resources shared by all the HRTIM timers operating in waveform mode:
3549 (+) Configure the burst mode controller
3550 (+) Configure an external event conditioning
3551 (+) Configure the external events sampling clock
3552 (+) Configure a fault conditioning
3553 (+) Enable or disable fault inputs
3554 (+) Configure the faults sampling clock
3555 (+) Configure an ADC trigger
3556
3557 @endverbatim
3558 * @{
3559 */
3560
3561 /**
3562 * @brief Configure the burst mode feature of the HRTIM
3563 * @param hhrtim pointer to HAL HRTIM handle
3564 * @param pBurstModeCfg pointer to the burst mode configuration structure
3565 * @retval HAL status
3566 * @note This function must be called before starting the burst mode
3567 * controller
3568 */
HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,const HRTIM_BurstModeCfgTypeDef * pBurstModeCfg)3569 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
3570 const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg)
3571 {
3572 uint32_t hrtim_bmcr;
3573
3574 /* Check parameters */
3575 assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
3576 assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
3577 assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
3578 assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
3579 assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
3580
3581 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
3582 {
3583 return HAL_BUSY;
3584 }
3585
3586 /* Process Locked */
3587 __HAL_LOCK(hhrtim);
3588
3589 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3590
3591 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
3592
3593 /* Set the burst mode operating mode */
3594 hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
3595 hrtim_bmcr |= (pBurstModeCfg->Mode & HRTIM_BMCR_BMOM);
3596
3597 /* Set the burst mode clock source */
3598 hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
3599 hrtim_bmcr |= (pBurstModeCfg->ClockSource & HRTIM_BMCR_BMCLK);
3600
3601 /* Set the burst mode prescaler */
3602 hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
3603 hrtim_bmcr |= pBurstModeCfg->Prescaler;
3604
3605 /* Enable/disable burst mode registers preload */
3606 hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
3607 hrtim_bmcr |= (pBurstModeCfg->PreloadEnable & HRTIM_BMCR_BMPREN);
3608
3609 /* Set the burst mode trigger */
3610 hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
3611
3612 /* Set the burst mode compare value */
3613 hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
3614
3615 /* Set the burst mode period */
3616 hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
3617
3618 /* Update the HRTIM registers */
3619 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
3620
3621 hhrtim->State = HAL_HRTIM_STATE_READY;
3622
3623 /* Process Unlocked */
3624 __HAL_UNLOCK(hhrtim);
3625
3626 return HAL_OK;
3627 }
3628
3629 /**
3630 * @brief Configure the conditioning of an external event
3631 * @param hhrtim pointer to HAL HRTIM handle
3632 * @param Event external event to configure
3633 * This parameter can be one of the following values:
3634 * @arg HRTIM_EVENT_NONE: no external Event
3635 * @arg HRTIM_EVENT_1: External event 1
3636 * @arg HRTIM_EVENT_2: External event 2
3637 * @arg HRTIM_EVENT_3: External event 3
3638 * @arg HRTIM_EVENT_4: External event 4
3639 * @arg HRTIM_EVENT_5: External event 5
3640 * @arg HRTIM_EVENT_6: External event 6
3641 * @arg HRTIM_EVENT_7: External event 7
3642 * @arg HRTIM_EVENT_8: External event 8
3643 * @arg HRTIM_EVENT_9: External event 9
3644 * @arg HRTIM_EVENT_10: External event 10
3645 * @param pEventCfg pointer to the event conditioning configuration structure
3646 * @note This function must be called before starting the timer
3647 * @retval HAL status
3648 */
HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Event,const HRTIM_EventCfgTypeDef * pEventCfg)3649 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
3650 uint32_t Event,
3651 const HRTIM_EventCfgTypeDef *pEventCfg)
3652 {
3653 /* Check parameters */
3654 assert_param(IS_HRTIM_EVENT(Event));
3655 assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
3656 assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
3657 assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
3658 assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
3659 assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
3660
3661 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
3662 {
3663 return HAL_BUSY;
3664 }
3665
3666 /* Process Locked */
3667 __HAL_LOCK(hhrtim);
3668
3669 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3670
3671 /* Configure the event channel */
3672 HRTIM_EventConfig(hhrtim, Event, pEventCfg);
3673
3674 hhrtim->State = HAL_HRTIM_STATE_READY;
3675
3676 /* Process Unlocked */
3677 __HAL_UNLOCK(hhrtim);
3678
3679 return HAL_OK;
3680 }
3681
3682 /**
3683 * @brief Configure the external event conditioning block prescaler
3684 * @param hhrtim pointer to HAL HRTIM handle
3685 * @param Prescaler Prescaler value
3686 * This parameter can be one of the following values:
3687 * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
3688 * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
3689 * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
3690 * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
3691 * @note This function must be called before starting the timer
3692 * @retval HAL status
3693 */
HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Prescaler)3694 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
3695 uint32_t Prescaler)
3696 {
3697 /* Check parameters */
3698 assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
3699
3700 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
3701 {
3702 return HAL_BUSY;
3703 }
3704
3705 /* Process Locked */
3706 __HAL_LOCK(hhrtim);
3707
3708 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3709
3710 /* Set the external event prescaler */
3711 MODIFY_REG(hhrtim->Instance->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, (Prescaler & HRTIM_EECR3_EEVSD));
3712
3713 hhrtim->State = HAL_HRTIM_STATE_READY;
3714
3715 /* Process Unlocked */
3716 __HAL_UNLOCK(hhrtim);
3717
3718 return HAL_OK;
3719 }
3720
3721 /**
3722 * @brief Configure the conditioning of fault input
3723 * @param hhrtim pointer to HAL HRTIM handle
3724 * @param Fault fault input to configure
3725 * This parameter can be one of the following values:
3726 * @arg HRTIM_FAULT_1: Fault input 1
3727 * @arg HRTIM_FAULT_2: Fault input 2
3728 * @arg HRTIM_FAULT_3: Fault input 3
3729 * @arg HRTIM_FAULT_4: Fault input 4
3730 * @arg HRTIM_FAULT_5: Fault input 5
3731 * @param pFaultCfg pointer to the fault conditioning configuration structure
3732 * @note This function must be called before starting the timer and before
3733 * enabling faults inputs
3734 * @retval HAL status
3735 */
HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Fault,const HRTIM_FaultCfgTypeDef * pFaultCfg)3736 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
3737 uint32_t Fault,
3738 const HRTIM_FaultCfgTypeDef *pFaultCfg)
3739 {
3740 uint32_t hrtim_fltinr1;
3741 uint32_t hrtim_fltinr2;
3742
3743 /* Check parameters */
3744 assert_param(IS_HRTIM_FAULT(Fault));
3745 assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
3746 assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
3747 assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
3748 assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
3749
3750 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
3751 {
3752 return HAL_BUSY;
3753 }
3754
3755 /* Process Locked */
3756 __HAL_LOCK(hhrtim);
3757
3758 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3759
3760 /* Configure fault channel */
3761 hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
3762 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
3763
3764 switch (Fault)
3765 {
3766 case HRTIM_FAULT_1:
3767 {
3768 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
3769 hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P);
3770 hrtim_fltinr1 |= (pFaultCfg->Source & HRTIM_FLTINR1_FLT1SRC);
3771 hrtim_fltinr1 |= (pFaultCfg->Filter & HRTIM_FLTINR1_FLT1F);
3772 hrtim_fltinr1 |= (pFaultCfg->Lock & HRTIM_FLTINR1_FLT1LCK);
3773 break;
3774 }
3775
3776 case HRTIM_FAULT_2:
3777 {
3778 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
3779 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P);
3780 hrtim_fltinr1 |= ((pFaultCfg->Source << 8U) & HRTIM_FLTINR1_FLT2SRC);
3781 hrtim_fltinr1 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR1_FLT2F);
3782 hrtim_fltinr1 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR1_FLT2LCK);
3783 break;
3784 }
3785
3786 case HRTIM_FAULT_3:
3787 {
3788 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
3789 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P);
3790 hrtim_fltinr1 |= ((pFaultCfg->Source << 16U) & HRTIM_FLTINR1_FLT3SRC);
3791 hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F);
3792 hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK);
3793 break;
3794 }
3795
3796 case HRTIM_FAULT_4:
3797 {
3798 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
3799 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P);
3800 hrtim_fltinr1 |= ((pFaultCfg->Source << 24U) & HRTIM_FLTINR1_FLT4SRC);
3801 hrtim_fltinr1 |= ((pFaultCfg->Filter << 24U) & HRTIM_FLTINR1_FLT4F);
3802 hrtim_fltinr1 |= ((pFaultCfg->Lock << 24U) & HRTIM_FLTINR1_FLT4LCK);
3803 break;
3804 }
3805
3806 case HRTIM_FAULT_5:
3807 {
3808 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
3809 hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P);
3810 hrtim_fltinr2 |= (pFaultCfg->Source & HRTIM_FLTINR2_FLT5SRC);
3811 hrtim_fltinr2 |= (pFaultCfg->Filter & HRTIM_FLTINR2_FLT5F);
3812 hrtim_fltinr2 |= (pFaultCfg->Lock & HRTIM_FLTINR2_FLT5LCK);
3813 break;
3814 }
3815
3816 default:
3817 {
3818 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3819
3820 /* Process Unlocked */
3821 __HAL_UNLOCK(hhrtim);
3822
3823 break;
3824 }
3825 }
3826
3827 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
3828 {
3829 return HAL_ERROR;
3830 }
3831
3832 /* Update the HRTIM registers except LOCK bit */
3833 hhrtim->Instance->sCommonRegs.FLTINR1 = (hrtim_fltinr1 & (~(HRTIM_FLTINR1_FLTxLCK)));
3834 hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK)));
3835
3836 /* Update the HRTIM registers LOCK bit */
3837 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1, (hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK));
3838 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2, (hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK));
3839
3840 hhrtim->State = HAL_HRTIM_STATE_READY;
3841
3842 /* Process Unlocked */
3843 __HAL_UNLOCK(hhrtim);
3844
3845 return HAL_OK;
3846 }
3847
3848 /**
3849 * @brief Configure the fault conditioning block prescaler
3850 * @param hhrtim pointer to HAL HRTIM handle
3851 * @param Prescaler Prescaler value
3852 * This parameter can be one of the following values:
3853 * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
3854 * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
3855 * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
3856 * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
3857 * @retval HAL status
3858 * @note This function must be called before starting the timer and before
3859 * enabling faults inputs
3860 */
HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Prescaler)3861 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
3862 uint32_t Prescaler)
3863 {
3864 /* Check parameters */
3865 assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
3866
3867 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
3868 {
3869 return HAL_BUSY;
3870 }
3871
3872 /* Process Locked */
3873 __HAL_LOCK(hhrtim);
3874
3875 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3876
3877 /* Set the external event prescaler */
3878 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, (Prescaler & HRTIM_FLTINR2_FLTSD));
3879
3880 hhrtim->State = HAL_HRTIM_STATE_READY;
3881
3882 /* Process Unlocked */
3883 __HAL_UNLOCK(hhrtim);
3884
3885 return HAL_OK;
3886 }
3887
3888 /**
3889 * @brief Enable or disables the HRTIMx Fault mode.
3890 * @param hhrtim pointer to HAL HRTIM handle
3891 * @param Faults fault input(s) to enable or disable
3892 * This parameter can be any combination of the following values:
3893 * @arg HRTIM_FAULT_1: Fault input 1
3894 * @arg HRTIM_FAULT_2: Fault input 2
3895 * @arg HRTIM_FAULT_3: Fault input 3
3896 * @arg HRTIM_FAULT_4: Fault input 4
3897 * @arg HRTIM_FAULT_5: Fault input 5
3898 * @param Enable Fault(s) enabling
3899 * This parameter can be one of the following values:
3900 * @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
3901 * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
3902 * @retval None
3903 */
HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,uint32_t Faults,uint32_t Enable)3904 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim,
3905 uint32_t Faults,
3906 uint32_t Enable)
3907 {
3908 /* Check parameters */
3909 assert_param(IS_HRTIM_FAULT(Faults));
3910 assert_param(IS_HRTIM_FAULTMODECTL(Enable));
3911
3912 if ((Faults & HRTIM_FAULT_1) != (uint32_t)RESET)
3913 {
3914 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT1E, (Enable & HRTIM_FLTINR1_FLT1E));
3915 }
3916 if ((Faults & HRTIM_FAULT_2) != (uint32_t)RESET)
3917 {
3918 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT2E, ((Enable << 8U) & HRTIM_FLTINR1_FLT2E));
3919 }
3920 if ((Faults & HRTIM_FAULT_3) != (uint32_t)RESET)
3921 {
3922 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT3E, ((Enable << 16U) & HRTIM_FLTINR1_FLT3E));
3923 }
3924 if ((Faults & HRTIM_FAULT_4) != (uint32_t)RESET)
3925 {
3926 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT4E, ((Enable << 24U) & HRTIM_FLTINR1_FLT4E));
3927 }
3928 if ((Faults & HRTIM_FAULT_5) != (uint32_t)RESET)
3929 {
3930 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT5E, ((Enable) & HRTIM_FLTINR2_FLT5E));
3931 }
3932 }
3933
3934 /**
3935 * @brief Configure both the ADC trigger register update source and the ADC
3936 * trigger source.
3937 * @param hhrtim pointer to HAL HRTIM handle
3938 * @param ADCTrigger ADC trigger to configure
3939 * This parameter can be one of the following values:
3940 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
3941 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
3942 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
3943 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
3944 * @param pADCTriggerCfg pointer to the ADC trigger configuration structure
3945 * @retval HAL status
3946 * @note This function must be called before starting the timer
3947 */
HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t ADCTrigger,const HRTIM_ADCTriggerCfgTypeDef * pADCTriggerCfg)3948 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
3949 uint32_t ADCTrigger,
3950 const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg)
3951 {
3952 uint32_t hrtim_cr1;
3953
3954 /* Check parameters */
3955 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
3956 assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
3957
3958 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
3959 {
3960 return HAL_BUSY;
3961 }
3962
3963 /* Process Locked */
3964 __HAL_LOCK(hhrtim);
3965
3966 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3967
3968 /* Set the ADC trigger update source */
3969 hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
3970
3971 switch (ADCTrigger)
3972 {
3973 case HRTIM_ADCTRIGGER_1:
3974 {
3975 hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
3976 hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
3977
3978 /* Set the ADC trigger 1 source */
3979 hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
3980 break;
3981 }
3982
3983 case HRTIM_ADCTRIGGER_2:
3984 {
3985 hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
3986 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
3987
3988 /* Set the ADC trigger 2 source */
3989 hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
3990 break;
3991 }
3992
3993 case HRTIM_ADCTRIGGER_3:
3994 {
3995 hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
3996 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
3997
3998 /* Set the ADC trigger 3 source */
3999 hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
4000 break;
4001 }
4002
4003 case HRTIM_ADCTRIGGER_4:
4004 {
4005 hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
4006 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
4007
4008 /* Set the ADC trigger 4 source */
4009 hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
4010 break;
4011 }
4012
4013 default:
4014 {
4015 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4016
4017 /* Process Unlocked */
4018 __HAL_UNLOCK(hhrtim);
4019
4020 break;
4021 }
4022 }
4023
4024 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
4025 {
4026 return HAL_ERROR;
4027 }
4028
4029 /* Update the HRTIM registers */
4030 hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
4031
4032 hhrtim->State = HAL_HRTIM_STATE_READY;
4033
4034 /* Process Unlocked */
4035 __HAL_UNLOCK(hhrtim);
4036
4037 return HAL_OK;
4038 }
4039
4040
4041 /**
4042 * @}
4043 */
4044
4045 /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
4046 * @brief HRTIM timer configuration and control functions
4047 @verbatim
4048 ===============================================================================
4049 ##### HRTIM timer configuration and control functions #####
4050 ===============================================================================
4051 [..] This section provides functions used to configure and control a
4052 HRTIM timer operating in waveform mode:
4053 (+) Configure HRTIM timer general behavior
4054 (+) Configure HRTIM timer event filtering
4055 (+) Configure HRTIM timer deadtime insertion
4056 (+) Configure HRTIM timer chopper mode
4057 (+) Configure HRTIM timer burst DMA
4058 (+) Configure HRTIM timer compare unit
4059 (+) Configure HRTIM timer capture unit
4060 (+) Configure HRTIM timer output
4061 (+) Set HRTIM timer output level
4062 (+) Enable HRTIM timer output
4063 (+) Disable HRTIM timer output
4064 (+) Start HRTIM timer
4065 (+) Stop HRTIM timer
4066 (+) Start HRTIM timer and enable interrupt
4067 (+) Stop HRTIM timer and disable interrupt
4068 (+) Start HRTIM timer and enable DMA transfer
4069 (+) Stop HRTIM timer and disable DMA transfer
4070 (+) Enable or disable the burst mode controller
4071 (+) Start the burst mode controller (by software)
4072 (+) Trigger a Capture (by software)
4073 (+) Update the HRTIM timer preloadable registers (by software)
4074 (+) Reset the HRTIM timer counter (by software)
4075 (+) Start a burst DMA transfer
4076 (+) Enable timer register update
4077 (+) Disable timer register update
4078
4079 @endverbatim
4080 * @{
4081 */
4082
4083 /**
4084 * @brief Configure the general behavior of a timer operating in waveform mode
4085 * @param hhrtim pointer to HAL HRTIM handle
4086 * @param TimerIdx Timer index
4087 * This parameter can be one of the following values:
4088 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4089 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4090 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4091 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4092 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4093 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4094 * @param pTimerCfg pointer to the timer configuration structure
4095 * @note When the timer operates in waveform mode, all the features supported by
4096 * the HRTIM are available without any limitation.
4097 * @retval HAL status
4098 * @note This function must be called before starting the timer
4099 */
HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimerCfgTypeDef * pTimerCfg)4100 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
4101 uint32_t TimerIdx,
4102 const HRTIM_TimerCfgTypeDef *pTimerCfg)
4103 {
4104 /* Check parameters */
4105 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4106
4107 /* Relevant for all HRTIM timers, including the master */
4108 assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
4109 assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
4110 assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
4111 assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro));
4112 assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
4113 assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
4114 assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
4115
4116 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4117 {
4118 return HAL_BUSY;
4119 }
4120
4121 /* Process Locked */
4122 __HAL_LOCK(hhrtim);
4123
4124 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4125
4126 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4127 {
4128 /* Check parameters */
4129 assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
4130 assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
4131 assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
4132
4133 /* Configure master timer */
4134 HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
4135 }
4136 else
4137 {
4138 /* Check parameters */
4139 assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
4140 assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
4141 assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
4142 assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
4143 assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
4144 assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
4145 assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
4146 pTimerCfg->DeadTimeInsertion));
4147 assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
4148 pTimerCfg->DelayedProtectionMode));
4149 assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
4150 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
4151 assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
4152
4153 /* Configure timing unit */
4154 HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
4155 }
4156
4157 /* Update timer parameters */
4158 hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
4159 hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
4160 hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
4161 hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
4162 hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
4163
4164 /* Force a software update */
4165 HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
4166
4167 hhrtim->State = HAL_HRTIM_STATE_READY;
4168
4169 /* Process Unlocked */
4170 __HAL_UNLOCK(hhrtim);
4171
4172 return HAL_OK;
4173 }
4174
4175 /**
4176 * @brief Configure the event filtering capabilities of a timer (blanking, windowing)
4177 * @param hhrtim pointer to HAL HRTIM handle
4178 * @param TimerIdx Timer index
4179 * This parameter can be one of the following values:
4180 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4181 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4182 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4183 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4184 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4185 * @param Event external event for which timer event filtering must be configured
4186 * This parameter can be one of the following values:
4187 * @arg HRTIM_EVENT_1: External event 1
4188 * @arg HRTIM_EVENT_2: External event 2
4189 * @arg HRTIM_EVENT_3: External event 3
4190 * @arg HRTIM_EVENT_4: External event 4
4191 * @arg HRTIM_EVENT_5: External event 5
4192 * @arg HRTIM_EVENT_6: External event 6
4193 * @arg HRTIM_EVENT_7: External event 7
4194 * @arg HRTIM_EVENT_8: External event 8
4195 * @arg HRTIM_EVENT_9: External event 9
4196 * @arg HRTIM_EVENT_10: External event 10
4197 * @param pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
4198 * @note This function must be called before starting the timer
4199 * @retval HAL status
4200 */
HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Event,const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg)4201 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
4202 uint32_t TimerIdx,
4203 uint32_t Event,
4204 const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg)
4205 {
4206 /* Check parameters */
4207 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4208 assert_param(IS_HRTIM_EVENT(Event));
4209 assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
4210
4211 assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
4212
4213 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4214 {
4215 return HAL_BUSY;
4216 }
4217
4218 /* Process Locked */
4219 __HAL_LOCK(hhrtim);
4220
4221 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4222
4223 /* Configure timer event filtering capabilities */
4224 switch (Event)
4225 {
4226 case HRTIM_EVENT_NONE:
4227 {
4228 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1);
4229 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2);
4230 break;
4231 }
4232
4233 case HRTIM_EVENT_1:
4234 {
4235 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH),
4236 (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
4237 break;
4238 }
4239
4240 case HRTIM_EVENT_2:
4241 {
4242 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH),
4243 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U));
4244 break;
4245 }
4246
4247 case HRTIM_EVENT_3:
4248 {
4249 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH),
4250 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U));
4251 break;
4252 }
4253
4254 case HRTIM_EVENT_4:
4255 {
4256 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH),
4257 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U));
4258 break;
4259 }
4260
4261 case HRTIM_EVENT_5:
4262 {
4263 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH),
4264 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U));
4265 break;
4266 }
4267
4268 case HRTIM_EVENT_6:
4269 {
4270 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH),
4271 (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
4272 break;
4273 }
4274
4275 case HRTIM_EVENT_7:
4276 {
4277 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH),
4278 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U));
4279 break;
4280 }
4281
4282 case HRTIM_EVENT_8:
4283 {
4284 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH),
4285 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U));
4286 break;
4287 }
4288
4289 case HRTIM_EVENT_9:
4290 {
4291 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH),
4292 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U));
4293 break;
4294 }
4295
4296 case HRTIM_EVENT_10:
4297 {
4298 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH),
4299 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U));
4300 break;
4301 }
4302
4303 default:
4304 {
4305 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4306
4307 /* Process Unlocked */
4308 __HAL_UNLOCK(hhrtim);
4309
4310 break;
4311 }
4312 }
4313
4314 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
4315 {
4316 return HAL_ERROR;
4317 }
4318
4319 hhrtim->State = HAL_HRTIM_STATE_READY;
4320
4321 /* Process Unlocked */
4322 __HAL_UNLOCK(hhrtim);
4323
4324 return HAL_OK;
4325 }
4326
4327 /**
4328 * @brief Configure the dead-time insertion feature for a timer
4329 * @param hhrtim pointer to HAL HRTIM handle
4330 * @param TimerIdx Timer index
4331 * This parameter can be one of the following values:
4332 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4333 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4334 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4335 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4336 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4337 * @param pDeadTimeCfg pointer to the deadtime insertion configuration structure
4338 * @retval HAL status
4339 * @note This function must be called before starting the timer
4340 */
HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_DeadTimeCfgTypeDef * pDeadTimeCfg)4341 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
4342 uint32_t TimerIdx,
4343 const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg)
4344 {
4345 uint32_t hrtim_dtr;
4346
4347 /* Check parameters */
4348 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4349 assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
4350 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
4351 assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
4352 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
4353 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
4354 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
4355 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
4356
4357 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4358 {
4359 return HAL_BUSY;
4360 }
4361
4362 /* Process Locked */
4363 __HAL_LOCK(hhrtim);
4364
4365 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4366
4367 /* Set timer deadtime configuration */
4368 hrtim_dtr = (pDeadTimeCfg->Prescaler & HRTIM_DTR_DTPRSC);
4369 hrtim_dtr |= (pDeadTimeCfg->RisingValue & HRTIM_DTR_DTR);
4370 hrtim_dtr |= (pDeadTimeCfg->RisingSign & HRTIM_DTR_SDTR);
4371 hrtim_dtr |= (pDeadTimeCfg->RisingSignLock & HRTIM_DTR_DTRSLK);
4372 hrtim_dtr |= (pDeadTimeCfg->RisingLock & HRTIM_DTR_DTRLK);
4373 hrtim_dtr |= ((pDeadTimeCfg->FallingValue << 16U) & HRTIM_DTR_DTF);
4374 hrtim_dtr |= (pDeadTimeCfg->FallingSign & HRTIM_DTR_SDTF);
4375 hrtim_dtr |= (pDeadTimeCfg->FallingSignLock & HRTIM_DTR_DTFSLK);
4376 hrtim_dtr |= (pDeadTimeCfg->FallingLock & HRTIM_DTR_DTFLK);
4377
4378 /* Update the HRTIM registers */
4379 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, (
4380 HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
4381 HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
4382 HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr);
4383
4384 hhrtim->State = HAL_HRTIM_STATE_READY;
4385
4386 /* Process Unlocked */
4387 __HAL_UNLOCK(hhrtim);
4388
4389 return HAL_OK;
4390 }
4391
4392 /**
4393 * @brief Configure the chopper mode feature for a timer
4394 * @param hhrtim pointer to HAL HRTIM handle
4395 * @param TimerIdx Timer index
4396 * This parameter can be one of the following values:
4397 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4398 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4399 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4400 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4401 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4402 * @param pChopperModeCfg pointer to the chopper mode configuration structure
4403 * @retval HAL status
4404 * @note This function must be called before configuring the timer output(s)
4405 */
HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_ChopperModeCfgTypeDef * pChopperModeCfg)4406 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
4407 uint32_t TimerIdx,
4408 const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg)
4409 {
4410 uint32_t hrtim_chpr;
4411
4412 /* Check parameters */
4413 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4414 assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
4415 assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
4416 assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
4417
4418 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4419 {
4420 return HAL_BUSY;
4421 }
4422
4423 /* Process Locked */
4424 __HAL_LOCK(hhrtim);
4425
4426 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4427
4428 /* Set timer choppe mode configuration */
4429 hrtim_chpr = (pChopperModeCfg->CarrierFreq & HRTIM_CHPR_CARFRQ);
4430 hrtim_chpr |= (pChopperModeCfg->DutyCycle & HRTIM_CHPR_CARDTY);
4431 hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW);
4432
4433 /* Update the HRTIM registers */
4434 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR,
4435 (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW),
4436 hrtim_chpr);
4437
4438 hhrtim->State = HAL_HRTIM_STATE_READY;
4439
4440 /* Process Unlocked */
4441 __HAL_UNLOCK(hhrtim);
4442
4443 return HAL_OK;
4444 }
4445
4446 /**
4447 * @brief Configure the burst DMA controller for a timer
4448 * @param hhrtim pointer to HAL HRTIM handle
4449 * @param TimerIdx Timer index
4450 * This parameter can be one of the following values:
4451 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4452 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4453 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4454 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4455 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4456 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4457 * @param RegistersToUpdate registers to be written by DMA
4458 * This parameter can be any combination of the following values:
4459 * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
4460 * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
4461 * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
4462 * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
4463 * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
4464 * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
4465 * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
4466 * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
4467 * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
4468 * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
4469 * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
4470 * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
4471 * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
4472 * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
4473 * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
4474 * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
4475 * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
4476 * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
4477 * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
4478 * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
4479 * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
4480 * @retval HAL status
4481 * @note This function must be called before starting the timer
4482 */
HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t RegistersToUpdate)4483 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
4484 uint32_t TimerIdx,
4485 uint32_t RegistersToUpdate)
4486 {
4487 /* Check parameters */
4488 assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
4489
4490 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4491 {
4492 return HAL_BUSY;
4493 }
4494
4495 /* Process Locked */
4496 __HAL_LOCK(hhrtim);
4497
4498 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4499
4500 /* Set the burst DMA timer update register */
4501 switch (TimerIdx)
4502 {
4503 case HRTIM_TIMERINDEX_TIMER_A:
4504 {
4505 hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
4506 break;
4507 }
4508
4509 case HRTIM_TIMERINDEX_TIMER_B:
4510 {
4511 hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
4512 break;
4513 }
4514
4515 case HRTIM_TIMERINDEX_TIMER_C:
4516 {
4517 hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
4518 break;
4519 }
4520
4521 case HRTIM_TIMERINDEX_TIMER_D:
4522 {
4523 hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
4524 break;
4525 }
4526
4527 case HRTIM_TIMERINDEX_TIMER_E:
4528 {
4529 hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
4530 break;
4531 }
4532
4533 case HRTIM_TIMERINDEX_MASTER:
4534 {
4535 hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
4536 break;
4537 }
4538
4539 default:
4540 {
4541 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4542
4543 /* Process Unlocked */
4544 __HAL_UNLOCK(hhrtim);
4545
4546 break;
4547 }
4548 }
4549
4550 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
4551 {
4552 return HAL_ERROR;
4553 }
4554
4555 hhrtim->State = HAL_HRTIM_STATE_READY;
4556
4557 /* Process Unlocked */
4558 __HAL_UNLOCK(hhrtim);
4559
4560 return HAL_OK;
4561 }
4562
4563 /**
4564 * @brief Configure the compare unit of a timer operating in waveform mode
4565 * @param hhrtim pointer to HAL HRTIM handle
4566 * @param TimerIdx Timer index
4567 * This parameter can be one of the following values:
4568 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4569 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4570 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4571 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4572 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4573 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4574 * @param CompareUnit Compare unit to configure
4575 * This parameter can be one of the following values:
4576 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
4577 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
4578 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
4579 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
4580 * @param pCompareCfg pointer to the compare unit configuration structure
4581 * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
4582 * application has to configure separately the capture unit. Capture unit
4583 * to configure in that case depends on the compare unit auto delayed mode
4584 * is applied to (see below):
4585 * Auto delayed on output compare 2: capture unit 1 must be configured
4586 * Auto delayed on output compare 4: capture unit 2 must be configured
4587 * @retval HAL status
4588 * @note This function must be called before starting the timer
4589 */
HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CompareUnit,const HRTIM_CompareCfgTypeDef * pCompareCfg)4590 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
4591 uint32_t TimerIdx,
4592 uint32_t CompareUnit,
4593 const HRTIM_CompareCfgTypeDef *pCompareCfg)
4594 {
4595 /* Check parameters */
4596 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4597
4598 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4599 {
4600 return HAL_BUSY;
4601 }
4602
4603 /* Process Locked */
4604 __HAL_LOCK(hhrtim);
4605
4606 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4607
4608 /* Configure the compare unit */
4609 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4610 {
4611 switch (CompareUnit)
4612 {
4613 case HRTIM_COMPAREUNIT_1:
4614 {
4615 hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
4616 break;
4617 }
4618
4619 case HRTIM_COMPAREUNIT_2:
4620 {
4621 hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
4622 break;
4623 }
4624
4625 case HRTIM_COMPAREUNIT_3:
4626 {
4627 hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
4628 break;
4629 }
4630
4631 case HRTIM_COMPAREUNIT_4:
4632 {
4633 hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
4634 break;
4635 }
4636
4637 default:
4638 {
4639 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4640
4641 /* Process Unlocked */
4642 __HAL_UNLOCK(hhrtim);
4643
4644 break;
4645 }
4646 }
4647
4648 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
4649 {
4650 return HAL_ERROR;
4651 }
4652
4653 }
4654 else
4655 {
4656 switch (CompareUnit)
4657 {
4658 case HRTIM_COMPAREUNIT_1:
4659 {
4660 /* Set the compare value */
4661 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
4662 break;
4663 }
4664
4665 case HRTIM_COMPAREUNIT_2:
4666 {
4667 /* Check parameters */
4668 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4669
4670 /* Set the compare value */
4671 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
4672
4673 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4674 {
4675 /* Configure auto-delayed mode */
4676 /* DELCMP2 bitfield must be reset when reprogrammed from one value */
4677 /* to the other to reinitialize properly the auto-delayed mechanism */
4678 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
4679 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
4680
4681 /* Set the compare value for timeout compare unit (if any) */
4682 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4683 {
4684 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4685 }
4686 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4687 {
4688 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4689 }
4690 else
4691 {
4692 /* nothing to do */
4693 }
4694 }
4695 else
4696 {
4697 /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */
4698 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
4699 }
4700 break;
4701 }
4702
4703 case HRTIM_COMPAREUNIT_3:
4704 {
4705 /* Set the compare value */
4706 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
4707 break;
4708 }
4709
4710 case HRTIM_COMPAREUNIT_4:
4711 {
4712 /* Check parameters */
4713 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4714
4715 /* Set the compare value */
4716 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
4717
4718 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4719 {
4720 /* Configure auto-delayed mode */
4721 /* DELCMP4 bitfield must be reset when reprogrammed from one value */
4722 /* to the other to reinitialize properly the auto-delayed mechanism */
4723 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
4724 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
4725
4726 /* Set the compare value for timeout compare unit (if any) */
4727 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4728 {
4729 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4730 }
4731 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4732 {
4733 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4734 }
4735 else
4736 {
4737 /* nothing to do */
4738 }
4739 }
4740 else
4741 {
4742 /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */
4743 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
4744 }
4745 break;
4746 }
4747
4748 default:
4749 {
4750 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4751
4752 /* Process Unlocked */
4753 __HAL_UNLOCK(hhrtim);
4754
4755 break;
4756 }
4757 }
4758
4759 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
4760 {
4761 return HAL_ERROR;
4762 }
4763
4764 }
4765 hhrtim->State = HAL_HRTIM_STATE_READY;
4766
4767 /* Process Unlocked */
4768 __HAL_UNLOCK(hhrtim);
4769
4770 return HAL_OK;
4771 }
4772
4773 /**
4774 * @brief Configure the capture unit of a timer operating in waveform mode
4775 * @param hhrtim pointer to HAL HRTIM handle
4776 * @param TimerIdx Timer index
4777 * This parameter can be one of the following values:
4778 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4779 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4780 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4781 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4782 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4783 * @param CaptureUnit Capture unit to configure
4784 * This parameter can be one of the following values:
4785 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
4786 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
4787 * @param pCaptureCfg pointer to the compare unit configuration structure
4788 * @retval HAL status
4789 * @note This function must be called before starting the timer
4790 */
HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit,const HRTIM_CaptureCfgTypeDef * pCaptureCfg)4791 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
4792 uint32_t TimerIdx,
4793 uint32_t CaptureUnit,
4794 const HRTIM_CaptureCfgTypeDef *pCaptureCfg)
4795 {
4796 /* Check parameters */
4797 assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
4798
4799
4800 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4801 {
4802 return HAL_BUSY;
4803 }
4804
4805 /* Process Locked */
4806 __HAL_LOCK(hhrtim);
4807
4808 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4809
4810 /* Configure the capture unit */
4811 switch (CaptureUnit)
4812 {
4813 case HRTIM_CAPTUREUNIT_1:
4814 {
4815 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, pCaptureCfg->Trigger);
4816 break;
4817 }
4818
4819 case HRTIM_CAPTUREUNIT_2:
4820 {
4821 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, pCaptureCfg->Trigger);
4822 break;
4823 }
4824
4825 default:
4826 {
4827 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4828
4829 /* Process Unlocked */
4830 __HAL_UNLOCK(hhrtim);
4831
4832 break;
4833 }
4834 }
4835
4836 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
4837 {
4838 return HAL_ERROR;
4839 }
4840
4841
4842 hhrtim->State = HAL_HRTIM_STATE_READY;
4843
4844 /* Process Unlocked */
4845 __HAL_UNLOCK(hhrtim);
4846
4847 return HAL_OK;
4848 }
4849
4850 /**
4851 * @brief Configure the output of a timer operating in waveform mode
4852 * @param hhrtim pointer to HAL HRTIM handle
4853 * @param TimerIdx Timer index
4854 * This parameter can be one of the following values:
4855 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4856 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4857 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4858 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4859 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4860 * @param Output Timer output
4861 * This parameter can be one of the following values:
4862 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
4863 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
4864 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
4865 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
4866 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
4867 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
4868 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
4869 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
4870 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
4871 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
4872 * @param pOutputCfg pointer to the timer output configuration structure
4873 * @retval HAL status
4874 * @note This function must be called before configuring the timer and after
4875 * configuring the deadtime insertion feature (if required).
4876 */
HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,const HRTIM_OutputCfgTypeDef * pOutputCfg)4877 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
4878 uint32_t TimerIdx,
4879 uint32_t Output,
4880 const HRTIM_OutputCfgTypeDef *pOutputCfg)
4881 {
4882 /* Check parameters */
4883 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
4884 assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
4885 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
4886 assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
4887 assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
4888 assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
4889 assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
4890
4891 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4892 {
4893 return HAL_BUSY;
4894 }
4895
4896 /* Process Locked */
4897 __HAL_LOCK(hhrtim);
4898
4899 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4900
4901 /* Configure the timer output */
4902 HRTIM_OutputConfig(hhrtim,
4903 TimerIdx,
4904 Output,
4905 pOutputCfg);
4906
4907 hhrtim->State = HAL_HRTIM_STATE_READY;
4908
4909 /* Process Unlocked */
4910 __HAL_UNLOCK(hhrtim);
4911
4912 return HAL_OK;
4913 }
4914
4915 /**
4916 * @brief Force the timer output to its active or inactive state
4917 * @param hhrtim pointer to HAL HRTIM handle
4918 * @param TimerIdx Timer index
4919 * This parameter can be one of the following values:
4920 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4921 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4922 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4923 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4924 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4925 * @param Output Timer output
4926 * This parameter can be one of the following values:
4927 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
4928 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
4929 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
4930 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
4931 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
4932 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
4933 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
4934 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
4935 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
4936 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
4937 * @param OutputLevel indicates whether the output is forced to its active or inactive level
4938 * This parameter can be one of the following values:
4939 * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
4940 * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
4941 * @retval HAL status
4942 * @note The 'software set/reset trigger' bit in the output set/reset registers
4943 * is automatically reset by hardware
4944 */
HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,uint32_t OutputLevel)4945 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
4946 uint32_t TimerIdx,
4947 uint32_t Output,
4948 uint32_t OutputLevel)
4949 {
4950 /* Check parameters */
4951 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
4952 assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
4953
4954 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4955 {
4956 return HAL_BUSY;
4957 }
4958
4959 /* Process Locked */
4960 __HAL_LOCK(hhrtim);
4961
4962 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4963
4964 /* Force timer output level */
4965 switch (Output)
4966 {
4967 case HRTIM_OUTPUT_TA1:
4968 case HRTIM_OUTPUT_TB1:
4969 case HRTIM_OUTPUT_TC1:
4970 case HRTIM_OUTPUT_TD1:
4971 case HRTIM_OUTPUT_TE1:
4972 {
4973 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
4974 {
4975 /* Force output to its active state */
4976 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R, HRTIM_SET1R_SST);
4977 }
4978 else
4979 {
4980 /* Force output to its inactive state */
4981 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R, HRTIM_RST1R_SRT);
4982 }
4983 break;
4984 }
4985
4986 case HRTIM_OUTPUT_TA2:
4987 case HRTIM_OUTPUT_TB2:
4988 case HRTIM_OUTPUT_TC2:
4989 case HRTIM_OUTPUT_TD2:
4990 case HRTIM_OUTPUT_TE2:
4991 {
4992 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
4993 {
4994 /* Force output to its active state */
4995 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R, HRTIM_SET2R_SST);
4996 }
4997 else
4998 {
4999 /* Force output to its inactive state */
5000 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R, HRTIM_RST2R_SRT);
5001 }
5002 break;
5003 }
5004
5005 default:
5006 {
5007 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5008
5009 /* Process Unlocked */
5010 __HAL_UNLOCK(hhrtim);
5011
5012 break;
5013 }
5014 }
5015
5016 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
5017 {
5018 return HAL_ERROR;
5019 }
5020
5021 hhrtim->State = HAL_HRTIM_STATE_READY;
5022
5023 /* Process Unlocked */
5024 __HAL_UNLOCK(hhrtim);
5025
5026 return HAL_OK;
5027 }
5028
5029 /**
5030 * @brief Enable the generation of the waveform signal on the designated output(s)
5031 * Outputs can be combined (ORed) to allow for simultaneous output enabling.
5032 * @param hhrtim pointer to HAL HRTIM handle
5033 * @param OutputsToStart Timer output(s) to enable
5034 * This parameter can be any combination of the following values:
5035 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5036 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5037 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5038 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5039 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5040 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5041 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5042 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5043 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5044 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5045 * @retval HAL status
5046 */
HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,uint32_t OutputsToStart)5047 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
5048 uint32_t OutputsToStart)
5049 {
5050 /* Check the parameters */
5051 assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
5052
5053 /* Process Locked */
5054 __HAL_LOCK(hhrtim);
5055
5056 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5057
5058 /* Enable the HRTIM outputs */
5059 hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
5060
5061 hhrtim->State = HAL_HRTIM_STATE_READY;
5062
5063 /* Process Unlocked */
5064 __HAL_UNLOCK(hhrtim);
5065
5066 return HAL_OK;
5067 }
5068
5069 /**
5070 * @brief Disable the generation of the waveform signal on the designated output(s)
5071 * Outputs can be combined (ORed) to allow for simultaneous output disabling.
5072 * @param hhrtim pointer to HAL HRTIM handle
5073 * @param OutputsToStop Timer output(s) to disable
5074 * This parameter can be any combination of the following values:
5075 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5076 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5077 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5078 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5079 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5080 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5081 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5082 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5083 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5084 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5085 * @retval HAL status
5086 */
HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,uint32_t OutputsToStop)5087 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
5088 uint32_t OutputsToStop)
5089 {
5090 /* Check the parameters */
5091 assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
5092
5093 /* Process Locked */
5094 __HAL_LOCK(hhrtim);
5095
5096 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5097
5098 /* Enable the HRTIM outputs */
5099 hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
5100
5101 hhrtim->State = HAL_HRTIM_STATE_READY;
5102
5103 /* Process Unlocked */
5104 __HAL_UNLOCK(hhrtim);
5105
5106 return HAL_OK;
5107 }
5108
5109 /**
5110 * @brief Start the counter of the designated timer(s) operating in waveform mode
5111 * Timers can be combined (ORed) to allow for simultaneous counter start.
5112 * @param hhrtim pointer to HAL HRTIM handle
5113 * @param Timers Timer counter(s) to start
5114 * This parameter can be any combination of the following values:
5115 * @arg HRTIM_TIMERID_MASTER
5116 * @arg HRTIM_TIMERID_TIMER_A
5117 * @arg HRTIM_TIMERID_TIMER_B
5118 * @arg HRTIM_TIMERID_TIMER_C
5119 * @arg HRTIM_TIMERID_TIMER_D
5120 * @arg HRTIM_TIMERID_TIMER_E
5121 * @retval HAL status
5122 */
HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5123 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim,
5124 uint32_t Timers)
5125 {
5126 /* Check the parameters */
5127 assert_param(IS_HRTIM_TIMERID(Timers));
5128
5129 /* Process Locked */
5130 __HAL_LOCK(hhrtim);
5131
5132 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5133
5134 /* Enable timer(s) counter */
5135 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
5136
5137 hhrtim->State = HAL_HRTIM_STATE_READY;
5138
5139 /* Process Unlocked */
5140 __HAL_UNLOCK(hhrtim);
5141
5142 return HAL_OK;
5143 }
5144
5145 /**
5146 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5147 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5148 * @param hhrtim pointer to HAL HRTIM handle
5149 * @param Timers Timer counter(s) to stop
5150 * This parameter can be any combination of the following values:
5151 * @arg HRTIM_TIMERID_MASTER
5152 * @arg HRTIM_TIMERID_TIMER_A
5153 * @arg HRTIM_TIMERID_TIMER_B
5154 * @arg HRTIM_TIMERID_TIMER_C
5155 * @arg HRTIM_TIMERID_TIMER_D
5156 * @arg HRTIM_TIMERID_TIMER_E
5157 * @retval HAL status
5158 * @note The counter of a timer is stopped only if all timer outputs are disabled
5159 */
HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5160 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim,
5161 uint32_t Timers)
5162 {
5163 /* Check the parameters */
5164 assert_param(IS_HRTIM_TIMERID(Timers));
5165
5166 /* Process Locked */
5167 __HAL_LOCK(hhrtim);
5168
5169 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5170
5171 /* Disable timer(s) counter */
5172 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
5173
5174 hhrtim->State = HAL_HRTIM_STATE_READY;
5175
5176 /* Process Unlocked */
5177 __HAL_UNLOCK(hhrtim);
5178
5179 return HAL_OK;
5180 }
5181
5182 /**
5183 * @brief Start the counter of the designated timer(s) operating in waveform mode
5184 * Timers can be combined (ORed) to allow for simultaneous counter start.
5185 * @param hhrtim pointer to HAL HRTIM handle
5186 * @param Timers Timer counter(s) to start
5187 * This parameter can be any combination of the following values:
5188 * @arg HRTIM_TIMERID_MASTER
5189 * @arg HRTIM_TIMERID_TIMER_A
5190 * @arg HRTIM_TIMERID_TIMER_B
5191 * @arg HRTIM_TIMERID_TIMER_C
5192 * @arg HRTIM_TIMERID_TIMER_D
5193 * @arg HRTIM_TIMERID_TIMER_E
5194 * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
5195 * to the timers to start are enabled within this function.
5196 * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
5197 * function.
5198 * @retval HAL status
5199 */
HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5200 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim,
5201 uint32_t Timers)
5202 {
5203 uint8_t timer_idx;
5204
5205 /* Check the parameters */
5206 assert_param(IS_HRTIM_TIMERID(Timers));
5207
5208 /* Process Locked */
5209 __HAL_LOCK(hhrtim);
5210
5211 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5212
5213 /* Enable HRTIM interrupts (if required) */
5214 __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests);
5215
5216 /* Enable master timer related interrupts (if required) */
5217 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
5218 {
5219 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
5220 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
5221 }
5222
5223 /* Enable timing unit related interrupts (if required) */
5224 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5225 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5226 timer_idx++)
5227 {
5228 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
5229 {
5230 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
5231 timer_idx,
5232 hhrtim->TimerParam[timer_idx].InterruptRequests);
5233 }
5234 }
5235
5236 /* Enable timer(s) counter */
5237 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
5238
5239 hhrtim->State = HAL_HRTIM_STATE_READY;
5240
5241 /* Process Unlocked */
5242 __HAL_UNLOCK(hhrtim);
5243
5244 return HAL_OK;
5245 }
5246
5247 /**
5248 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5249 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5250 * @param hhrtim pointer to HAL HRTIM handle
5251 * @param Timers Timer counter(s) to stop
5252 * This parameter can be any combination of the following values:
5253 * @arg HRTIM_TIMERID_MASTER
5254 * @arg HRTIM_TIMERID_TIMER_A
5255 * @arg HRTIM_TIMERID_TIMER_B
5256 * @arg HRTIM_TIMERID_TIMER_C
5257 * @arg HRTIM_TIMERID_TIMER_D
5258 * @arg HRTIM_TIMERID_TIMER_E
5259 * @retval HAL status
5260 * @note The counter of a timer is stopped only if all timer outputs are disabled
5261 * @note All enabled timer related interrupts are disabled.
5262 */
HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5263 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim,
5264 uint32_t Timers)
5265 {
5266 /* ++ WA */
5267 __IO uint32_t delai = (uint32_t)(0x17FU);
5268 /* -- WA */
5269
5270 uint8_t timer_idx;
5271
5272 /* Check the parameters */
5273 assert_param(IS_HRTIM_TIMERID(Timers));
5274
5275 /* Process Locked */
5276 __HAL_LOCK(hhrtim);
5277
5278 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5279
5280 /* Disable HRTIM interrupts (if required) */
5281 __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests);
5282
5283 /* Disable master timer related interrupts (if required) */
5284 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
5285 {
5286 /* Interrupts enable flag must be cleared one by one */
5287 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
5288 }
5289
5290 /* Disable timing unit related interrupts (if required) */
5291 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5292 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5293 timer_idx++)
5294 {
5295 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
5296 {
5297 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
5298 }
5299 }
5300
5301 /* ++ WA */
5302 do { delai--; } while (delai != 0U);
5303 /* -- WA */
5304
5305 /* Disable timer(s) counter */
5306 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
5307
5308 hhrtim->State = HAL_HRTIM_STATE_READY;
5309
5310 /* Process Unlocked */
5311 __HAL_UNLOCK(hhrtim);
5312
5313 return HAL_OK;
5314 }
5315
5316 /**
5317 * @brief Start the counter of the designated timer(s) operating in waveform mode
5318 * Timers can be combined (ORed) to allow for simultaneous counter start.
5319 * @param hhrtim pointer to HAL HRTIM handle
5320 * @param Timers Timer counter(s) to start
5321 * This parameter can be any combination of the following values:
5322 * @arg HRTIM_TIMERID_MASTER
5323 * @arg HRTIM_TIMERID_TIMER_A
5324 * @arg HRTIM_TIMERID_TIMER_B
5325 * @arg HRTIM_TIMERID_TIMER_C
5326 * @arg HRTIM_TIMERID_TIMER_D
5327 * @arg HRTIM_TIMERID_TIMER_E
5328 * @retval HAL status
5329 * @note This function enables the dma request(s) mentioned in the timer
5330 * configuration data structure for every timers to start.
5331 * @note The source memory address, the destination memory address and the
5332 * size of each DMA transfer are specified at timer configuration time
5333 * (see HAL_HRTIM_WaveformTimerConfig)
5334 */
HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5335 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim,
5336 uint32_t Timers)
5337 {
5338 uint8_t timer_idx;
5339 DMA_HandleTypeDef *hdma;
5340
5341 /* Check the parameters */
5342 assert_param(IS_HRTIM_TIMERID(Timers));
5343
5344 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5345 {
5346 return HAL_BUSY;
5347 }
5348
5349 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5350
5351 /* Process Locked */
5352 __HAL_LOCK(hhrtim);
5353
5354 if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) &&
5355 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
5356 {
5357 /* Set the DMA error callback */
5358 hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
5359
5360 /* Set the DMA transfer completed callback */
5361 hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
5362
5363 /* Enable the DMA channel */
5364 if (HAL_DMA_Start_IT(hhrtim->hdmaMaster,
5365 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
5366 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
5367 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK)
5368 {
5369 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5370
5371 /* Process Unlocked */
5372 __HAL_UNLOCK(hhrtim);
5373
5374 return HAL_ERROR;
5375 }
5376
5377 /* Enable the timer DMA request */
5378 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
5379 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5380 }
5381
5382 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5383 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5384 timer_idx++)
5385 {
5386 if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) &&
5387 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
5388 {
5389 /* Get the timer DMA handler */
5390 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
5391
5392 if (hdma == NULL)
5393 {
5394 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5395
5396 /* Process Unlocked */
5397 __HAL_UNLOCK(hhrtim);
5398
5399 return HAL_ERROR;
5400 }
5401
5402 /* Set the DMA error callback */
5403 hdma->XferErrorCallback = HRTIM_DMAError ;
5404
5405 /* Set the DMA transfer completed callback */
5406 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
5407
5408 /* Enable the DMA channel */
5409 if (HAL_DMA_Start_IT(hdma,
5410 hhrtim->TimerParam[timer_idx].DMASrcAddress,
5411 hhrtim->TimerParam[timer_idx].DMADstAddress,
5412 hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK)
5413 {
5414 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5415
5416 /* Process Unlocked */
5417 __HAL_UNLOCK(hhrtim);
5418
5419 return HAL_ERROR;
5420 }
5421
5422 /* Enable the timer DMA request */
5423 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
5424 timer_idx,
5425 hhrtim->TimerParam[timer_idx].DMARequests);
5426 }
5427 }
5428
5429 /* Enable the timer counter */
5430 __HAL_HRTIM_ENABLE(hhrtim, Timers);
5431
5432 hhrtim->State = HAL_HRTIM_STATE_READY;
5433
5434 /* Process Unlocked */
5435 __HAL_UNLOCK(hhrtim);
5436
5437 return HAL_OK;
5438 }
5439
5440 /**
5441 * @brief Stop the counter of the designated timer(s) operating in waveform mode
5442 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5443 * @param hhrtim pointer to HAL HRTIM handle
5444 * @param Timers Timer counter(s) to stop
5445 * This parameter can be any combination of the following values:
5446 * @arg HRTIM_TIMERID_MASTER
5447 * @arg HRTIM_TIMERID_TIMER_A
5448 * @arg HRTIM_TIMERID_TIMER_B
5449 * @arg HRTIM_TIMERID_TIMER_C
5450 * @arg HRTIM_TIMERID_TIMER_D
5451 * @arg HRTIM_TIMERID_TIMER_E
5452 * @retval HAL status
5453 * @note The counter of a timer is stopped only if all timer outputs are disabled
5454 * @note All enabled timer related DMA requests are disabled.
5455 */
HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5456 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim,
5457 uint32_t Timers)
5458 {
5459 uint8_t timer_idx;
5460
5461 /* Check the parameters */
5462 assert_param(IS_HRTIM_TIMERID(Timers));
5463
5464 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5465
5466 if (((Timers & HRTIM_TIMERID_MASTER) != 0U) &&
5467 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
5468 {
5469 /* Disable the DMA */
5470 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
5471 {
5472 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5473 }
5474 else
5475 {
5476 hhrtim->State = HAL_HRTIM_STATE_READY;
5477 /* Disable the DMA request(s) */
5478 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
5479 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5480 }
5481 }
5482
5483 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5484 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5485 timer_idx++)
5486 {
5487 if (((Timers & TimerIdxToTimerId[timer_idx]) != 0U) &&
5488 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
5489 {
5490 /* Get the timer DMA handler */
5491 /* Disable the DMA */
5492 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx)) != HAL_OK)
5493 {
5494 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5495 }
5496 else
5497 {
5498 hhrtim->State = HAL_HRTIM_STATE_READY;
5499
5500 /* Disable the DMA request(s) */
5501 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
5502 timer_idx,
5503 hhrtim->TimerParam[timer_idx].DMARequests);
5504 }
5505 }
5506 }
5507
5508 /* Disable the timer counter */
5509 __HAL_HRTIM_DISABLE(hhrtim, Timers);
5510
5511 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
5512 {
5513 return HAL_ERROR;
5514 }
5515 else
5516 {
5517 return HAL_OK;
5518 }
5519 }
5520
5521 /**
5522 * @brief Enable or disables the HRTIM burst mode controller.
5523 * @param hhrtim pointer to HAL HRTIM handle
5524 * @param Enable Burst mode controller enabling
5525 * This parameter can be one of the following values:
5526 * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
5527 * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
5528 * @retval HAL status
5529 * @note This function must be called after starting the timer(s)
5530 */
HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,uint32_t Enable)5531 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
5532 uint32_t Enable)
5533 {
5534 /* Check parameters */
5535 assert_param(IS_HRTIM_BURSTMODECTL(Enable));
5536
5537 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5538 {
5539 return HAL_BUSY;
5540 }
5541
5542 /* Process Locked */
5543 __HAL_LOCK(hhrtim);
5544
5545 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5546
5547 /* Enable/Disable the burst mode controller */
5548 MODIFY_REG(hhrtim->Instance->sCommonRegs.BMCR, HRTIM_BMCR_BME, Enable);
5549
5550 hhrtim->State = HAL_HRTIM_STATE_READY;
5551
5552 /* Process Unlocked */
5553 __HAL_UNLOCK(hhrtim);
5554
5555 return HAL_OK;
5556 }
5557
5558 /**
5559 * @brief Trig the burst mode operation.
5560 * @param hhrtim pointer to HAL HRTIM handle
5561 * @retval HAL status
5562 */
HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef * hhrtim)5563 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
5564 {
5565 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5566 {
5567 return HAL_BUSY;
5568 }
5569
5570 /* Process Locked */
5571 __HAL_LOCK(hhrtim);
5572
5573 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5574
5575 /* Software trigger of the burst mode controller */
5576 SET_BIT(hhrtim->Instance->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
5577
5578 hhrtim->State = HAL_HRTIM_STATE_READY;
5579
5580 /* Process Unlocked */
5581 __HAL_UNLOCK(hhrtim);
5582
5583 return HAL_OK;
5584 }
5585
5586 /**
5587 * @brief Trig a software capture on the designed capture unit
5588 * @param hhrtim pointer to HAL HRTIM handle
5589 * @param TimerIdx Timer index
5590 * This parameter can be one of the following values:
5591 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5592 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5593 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5594 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5595 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5596 * @param CaptureUnit Capture unit to trig
5597 * This parameter can be one of the following values:
5598 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
5599 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
5600 * @retval HAL status
5601 * @note The 'software capture' bit in the capure configuration register is
5602 * automatically reset by hardware
5603 */
HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)5604 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
5605 uint32_t TimerIdx,
5606 uint32_t CaptureUnit)
5607 {
5608 /* Check parameters */
5609 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5610 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
5611
5612 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5613 {
5614 return HAL_BUSY;
5615 }
5616
5617 /* Process Locked */
5618 __HAL_LOCK(hhrtim);
5619
5620 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5621
5622 /* Force a software capture on concerned capture unit */
5623 switch (CaptureUnit)
5624 {
5625 case HRTIM_CAPTUREUNIT_1:
5626 {
5627 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT);
5628 break;
5629 }
5630
5631 case HRTIM_CAPTUREUNIT_2:
5632 {
5633 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT);
5634 break;
5635 }
5636
5637 default:
5638 {
5639 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5640
5641 /* Process Unlocked */
5642 __HAL_UNLOCK(hhrtim);
5643
5644 break;
5645 }
5646 }
5647
5648 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
5649 {
5650 return HAL_ERROR;
5651 }
5652
5653 hhrtim->State = HAL_HRTIM_STATE_READY;
5654
5655 /* Process Unlocked */
5656 __HAL_UNLOCK(hhrtim);
5657
5658 return HAL_OK;
5659 }
5660
5661 /**
5662 * @brief Trig the update of the registers of one or several timers
5663 * @param hhrtim pointer to HAL HRTIM handle
5664 * @param Timers timers concerned with the software register update
5665 * This parameter can be any combination of the following values:
5666 * @arg HRTIM_TIMERUPDATE_MASTER
5667 * @arg HRTIM_TIMERUPDATE_A
5668 * @arg HRTIM_TIMERUPDATE_B
5669 * @arg HRTIM_TIMERUPDATE_C
5670 * @arg HRTIM_TIMERUPDATE_D
5671 * @arg HRTIM_TIMERUPDATE_E
5672 * @retval HAL status
5673 * @note The 'software update' bits in the HRTIM control register 2 register are
5674 * automatically reset by hardware
5675 */
HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5676 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
5677 uint32_t Timers)
5678 {
5679 /* Check parameters */
5680 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5681
5682 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5683 {
5684 return HAL_BUSY;
5685 }
5686
5687 /* Process Locked */
5688 __HAL_LOCK(hhrtim);
5689
5690 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5691
5692 /* Force timer(s) registers update */
5693 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
5694
5695 hhrtim->State = HAL_HRTIM_STATE_READY;
5696
5697 /* Process Unlocked */
5698 __HAL_UNLOCK(hhrtim);
5699
5700 return HAL_OK;
5701 }
5702
5703 /**
5704 * @brief Trig the reset of one or several timers
5705 * @param hhrtim pointer to HAL HRTIM handle
5706 * @param Timers timers concerned with the software counter reset
5707 * This parameter can be any combination of the following values:
5708 * @arg HRTIM_TIMERRESET_MASTER
5709 * @arg HRTIM_TIMERRESET_TIMER_A
5710 * @arg HRTIM_TIMERRESET_TIMER_B
5711 * @arg HRTIM_TIMERRESET_TIMER_C
5712 * @arg HRTIM_TIMERRESET_TIMER_D
5713 * @arg HRTIM_TIMERRESET_TIMER_E
5714 * @retval HAL status
5715 * @note The 'software reset' bits in the HRTIM control register 2 are
5716 * automatically reset by hardware
5717 */
HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5718 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
5719 uint32_t Timers)
5720 {
5721 /* Check parameters */
5722 assert_param(IS_HRTIM_TIMERRESET(Timers));
5723
5724 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5725 {
5726 return HAL_BUSY;
5727 }
5728
5729 /* Process Locked */
5730 __HAL_LOCK(hhrtim);
5731
5732 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5733
5734 /* Force timer(s) registers reset */
5735 hhrtim->Instance->sCommonRegs.CR2 = Timers;
5736
5737 hhrtim->State = HAL_HRTIM_STATE_READY;
5738
5739 /* Process Unlocked */
5740 __HAL_UNLOCK(hhrtim);
5741
5742 return HAL_OK;
5743 }
5744
5745 /**
5746 * @brief Start a burst DMA operation to update HRTIM control registers content
5747 * @param hhrtim pointer to HAL HRTIM handle
5748 * @param TimerIdx Timer index
5749 * This parameter can be one of the following values:
5750 * @arg HRTIM_TIMERINDEX_MASTER for master timer
5751 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5752 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5753 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5754 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5755 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5756 * @param BurstBufferAddress address of the buffer the HRTIM control registers
5757 * content will be updated from.
5758 * @param BurstBufferLength size (in WORDS) of the burst buffer.
5759 * @retval HAL status
5760 * @note The TimerIdx parameter determines the dma channel to be used by the
5761 * DMA burst controller (see below)
5762 * HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
5763 * HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
5764 * HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
5765 * HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
5766 * HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
5767 * HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
5768 */
HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t BurstBufferAddress,uint32_t BurstBufferLength)5769 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
5770 uint32_t TimerIdx,
5771 uint32_t BurstBufferAddress,
5772 uint32_t BurstBufferLength)
5773 {
5774 DMA_HandleTypeDef *hdma;
5775
5776 /* Check the parameters */
5777 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
5778
5779 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5780 {
5781 return HAL_BUSY;
5782 }
5783 if (hhrtim->State == HAL_HRTIM_STATE_READY)
5784 {
5785 if ((BurstBufferAddress == 0U) || (BurstBufferLength == 0U))
5786 {
5787 return HAL_ERROR;
5788 }
5789 else
5790 {
5791 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5792 }
5793 }
5794
5795 /* Process Locked */
5796 __HAL_LOCK(hhrtim);
5797
5798 /* Get the timer DMA handler */
5799 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
5800
5801 if (hdma == NULL)
5802 {
5803 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5804
5805 /* Process Unlocked */
5806 __HAL_UNLOCK(hhrtim);
5807
5808 return HAL_ERROR;
5809 }
5810
5811 /* Set the DMA transfer completed callback */
5812 hdma->XferCpltCallback = HRTIM_BurstDMACplt;
5813
5814 /* Set the DMA error callback */
5815 hdma->XferErrorCallback = HRTIM_DMAError ;
5816
5817 /* Enable the DMA channel */
5818 if (HAL_DMA_Start_IT(hdma,
5819 BurstBufferAddress,
5820 (uint32_t) &(hhrtim->Instance->sCommonRegs.BDMADR),
5821 BurstBufferLength) != HAL_OK)
5822 {
5823 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5824
5825 /* Process Unlocked */
5826 __HAL_UNLOCK(hhrtim);
5827
5828 return HAL_ERROR;
5829 }
5830
5831 hhrtim->State = HAL_HRTIM_STATE_READY;
5832
5833 /* Process Unlocked */
5834 __HAL_UNLOCK(hhrtim);
5835
5836 return HAL_OK;
5837 }
5838
5839 /**
5840 * @brief Enable the transfer from preload to active registers for one
5841 * or several timing units (including master timer).
5842 * @param hhrtim pointer to HAL HRTIM handle
5843 * @param Timers Timer(s) concerned by the register preload enabling command
5844 * This parameter can be any combination of the following values:
5845 * @arg HRTIM_TIMERUPDATE_MASTER
5846 * @arg HRTIM_TIMERUPDATE_A
5847 * @arg HRTIM_TIMERUPDATE_B
5848 * @arg HRTIM_TIMERUPDATE_C
5849 * @arg HRTIM_TIMERUPDATE_D
5850 * @arg HRTIM_TIMERUPDATE_E
5851 * @retval HAL status
5852 */
HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5853 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
5854 uint32_t Timers)
5855 {
5856 /* Check the parameters */
5857 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5858
5859 /* Process Locked */
5860 __HAL_LOCK(hhrtim);
5861
5862 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5863
5864 /* Enable timer(s) registers update */
5865 hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
5866
5867 hhrtim->State = HAL_HRTIM_STATE_READY;
5868
5869 /* Process Unlocked */
5870 __HAL_UNLOCK(hhrtim);
5871
5872 return HAL_OK;
5873 }
5874
5875 /**
5876 * @brief Disable the transfer from preload to active registers for one
5877 * or several timing units (including master timer).
5878 * @param hhrtim pointer to HAL HRTIM handle
5879 * @param Timers Timer(s) concerned by the register preload disabling command
5880 * This parameter can be any combination of the following values:
5881 * @arg HRTIM_TIMERUPDATE_MASTER
5882 * @arg HRTIM_TIMERUPDATE_A
5883 * @arg HRTIM_TIMERUPDATE_B
5884 * @arg HRTIM_TIMERUPDATE_C
5885 * @arg HRTIM_TIMERUPDATE_D
5886 * @arg HRTIM_TIMERUPDATE_E
5887 * @retval HAL status
5888 */
HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)5889 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
5890 uint32_t Timers)
5891 {
5892 /* Check the parameters */
5893 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5894
5895 /* Process Locked */
5896 __HAL_LOCK(hhrtim);
5897
5898 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5899
5900 /* Enable timer(s) registers update */
5901 hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
5902
5903 hhrtim->State = HAL_HRTIM_STATE_READY;
5904
5905 /* Process Unlocked */
5906 __HAL_UNLOCK(hhrtim);
5907
5908 return HAL_OK;
5909 }
5910
5911 /**
5912 * @}
5913 */
5914
5915 /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
5916 * @brief Peripheral State functions
5917 @verbatim
5918 ===============================================================================
5919 ##### Peripheral State functions #####
5920 ===============================================================================
5921 [..] This section provides functions used to get HRTIM or HRTIM timer
5922 specific information:
5923 (+) Get HRTIM HAL state
5924 (+) Get captured value
5925 (+) Get HRTIM timer output level
5926 (+) Get HRTIM timer output state
5927 (+) Get delayed protection status
5928 (+) Get burst status
5929 (+) Get current push-pull status
5930 (+) Get idle push-pull status
5931
5932 @endverbatim
5933 * @{
5934 */
5935
5936 /**
5937 * @brief Return the HRTIM HAL state
5938 * @param hhrtim pointer to HAL HRTIM handle
5939 * @retval HAL state
5940 */
HAL_HRTIM_GetState(const HRTIM_HandleTypeDef * hhrtim)5941 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim)
5942 {
5943 /* Return HRTIM state */
5944 return hhrtim->State;
5945 }
5946
5947 /**
5948 * @brief Return actual value of the capture register of the designated capture unit
5949 * @param hhrtim pointer to HAL HRTIM handle
5950 * @param TimerIdx Timer index
5951 * This parameter can be one of the following values:
5952 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5953 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5954 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5955 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5956 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5957 * @param CaptureUnit Capture unit to trig
5958 * This parameter can be one of the following values:
5959 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
5960 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
5961 * @retval Captured value
5962 */
HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)5963 uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim,
5964 uint32_t TimerIdx,
5965 uint32_t CaptureUnit)
5966 {
5967 uint32_t captured_value;
5968
5969 /* Check parameters */
5970 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5971 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
5972
5973 /* Read captured value */
5974 switch (CaptureUnit)
5975 {
5976 case HRTIM_CAPTUREUNIT_1:
5977 {
5978 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
5979 break;
5980 }
5981
5982 case HRTIM_CAPTUREUNIT_2:
5983 {
5984 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
5985 break;
5986 }
5987
5988 default:
5989 {
5990 captured_value = 0xFFFFFFFFUL;
5991 break;
5992 }
5993
5994 }
5995
5996 return captured_value;
5997 }
5998
5999
6000 /**
6001 * @brief Return actual level (active or inactive) of the designated output
6002 * @param hhrtim pointer to HAL HRTIM handle
6003 * @param TimerIdx Timer index
6004 * This parameter can be one of the following values:
6005 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6006 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6007 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6008 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6009 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6010 * @param Output Timer output
6011 * This parameter can be one of the following values:
6012 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6013 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6014 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6015 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6016 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6017 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6018 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6019 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6020 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6021 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6022 * @retval Output level
6023 * @note Returned output level is taken before the output stage (chopper,
6024 * polarity).
6025 */
HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)6026 uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim,
6027 uint32_t TimerIdx,
6028 uint32_t Output)
6029 {
6030 uint32_t output_level;
6031
6032 /* Check parameters */
6033 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6034
6035 /* Read the output level */
6036 switch (Output)
6037 {
6038 case HRTIM_OUTPUT_TA1:
6039 case HRTIM_OUTPUT_TB1:
6040 case HRTIM_OUTPUT_TC1:
6041 case HRTIM_OUTPUT_TD1:
6042 case HRTIM_OUTPUT_TE1:
6043 {
6044 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET)
6045 {
6046 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
6047 }
6048 else
6049 {
6050 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
6051 }
6052 break;
6053 }
6054
6055 case HRTIM_OUTPUT_TA2:
6056 case HRTIM_OUTPUT_TB2:
6057 case HRTIM_OUTPUT_TC2:
6058 case HRTIM_OUTPUT_TD2:
6059 case HRTIM_OUTPUT_TE2:
6060 {
6061 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET)
6062 {
6063 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
6064 }
6065 else
6066 {
6067 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
6068 }
6069 break;
6070 }
6071
6072 default:
6073 {
6074 output_level = 0xFFFFFFFFUL;
6075 break;
6076 }
6077 }
6078
6079 return output_level;
6080 }
6081
6082 /**
6083 * @brief Return actual state (RUN, IDLE, FAULT) of the designated output
6084 * @param hhrtim pointer to HAL HRTIM handle
6085 * @param TimerIdx Timer index
6086 * This parameter can be one of the following values:
6087 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6088 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6089 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6090 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6091 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6092 * @param Output Timer output
6093 * This parameter can be one of the following values:
6094 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6095 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6096 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6097 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6098 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6099 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6100 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6101 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6102 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6103 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6104 * @retval Output state
6105 */
HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)6106 uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim,
6107 uint32_t TimerIdx,
6108 uint32_t Output)
6109 {
6110 uint32_t output_bit;
6111 uint32_t output_state;
6112
6113 /* Check parameters */
6114 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6115
6116 /* Prevent unused argument(s) compilation warning */
6117 UNUSED(TimerIdx);
6118
6119 /* Set output state according to output control status and output disable status */
6120 switch (Output)
6121 {
6122 case HRTIM_OUTPUT_TA1:
6123 {
6124 output_bit = HRTIM_OENR_TA1OEN;
6125 break;
6126 }
6127
6128 case HRTIM_OUTPUT_TA2:
6129 {
6130 output_bit = HRTIM_OENR_TA2OEN;
6131 break;
6132 }
6133
6134 case HRTIM_OUTPUT_TB1:
6135 {
6136 output_bit = HRTIM_OENR_TB1OEN;
6137 break;
6138 }
6139
6140 case HRTIM_OUTPUT_TB2:
6141 {
6142 output_bit = HRTIM_OENR_TB2OEN;
6143 break;
6144 }
6145
6146 case HRTIM_OUTPUT_TC1:
6147 {
6148 output_bit = HRTIM_OENR_TC1OEN;
6149 break;
6150 }
6151
6152 case HRTIM_OUTPUT_TC2:
6153 {
6154 output_bit = HRTIM_OENR_TC2OEN;
6155 break;
6156 }
6157
6158 case HRTIM_OUTPUT_TD1:
6159 {
6160 output_bit = HRTIM_OENR_TD1OEN;
6161 break;
6162 }
6163
6164 case HRTIM_OUTPUT_TD2:
6165 {
6166 output_bit = HRTIM_OENR_TD2OEN;
6167 break;
6168 }
6169
6170 case HRTIM_OUTPUT_TE1:
6171 {
6172 output_bit = HRTIM_OENR_TE1OEN;
6173 break;
6174 }
6175
6176 case HRTIM_OUTPUT_TE2:
6177 {
6178 output_bit = HRTIM_OENR_TE2OEN;
6179 break;
6180 }
6181
6182 default:
6183 {
6184 output_bit = 0UL;
6185 break;
6186 }
6187 }
6188
6189 if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET)
6190 {
6191 /* Output is enabled: output in RUN state (whatever output disable status is)*/
6192 output_state = HRTIM_OUTPUTSTATE_RUN;
6193 }
6194 else
6195 {
6196 if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != (uint32_t)RESET)
6197 {
6198 /* Output is disabled: output in FAULT state */
6199 output_state = HRTIM_OUTPUTSTATE_FAULT;
6200 }
6201 else
6202 {
6203 /* Output is disabled: output in IDLE state */
6204 output_state = HRTIM_OUTPUTSTATE_IDLE;
6205 }
6206 }
6207
6208 return (output_state);
6209 }
6210
6211 /**
6212 * @brief Return the level (active or inactive) of the designated output
6213 * when the delayed protection was triggered.
6214 * @param hhrtim pointer to HAL HRTIM handle
6215 * @param TimerIdx Timer index
6216 * This parameter can be one of the following values:
6217 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6218 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6219 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6220 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6221 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6222 * @param Output Timer output
6223 * This parameter can be one of the following values:
6224 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6225 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6226 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6227 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6228 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6229 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6230 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6231 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6232 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6233 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6234 * @retval Delayed protection status
6235 */
HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)6236 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim,
6237 uint32_t TimerIdx,
6238 uint32_t Output)
6239 {
6240 uint32_t delayed_protection_status;
6241
6242 /* Check parameters */
6243 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6244
6245 /* Read the delayed protection status */
6246 switch (Output)
6247 {
6248 case HRTIM_OUTPUT_TA1:
6249 case HRTIM_OUTPUT_TB1:
6250 case HRTIM_OUTPUT_TC1:
6251 case HRTIM_OUTPUT_TD1:
6252 case HRTIM_OUTPUT_TE1:
6253 {
6254 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET)
6255 {
6256 /* Output 1 was active when the delayed idle protection was triggered */
6257 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
6258 }
6259 else
6260 {
6261 /* Output 1 was inactive when the delayed idle protection was triggered */
6262 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
6263 }
6264 break;
6265 }
6266
6267 case HRTIM_OUTPUT_TA2:
6268 case HRTIM_OUTPUT_TB2:
6269 case HRTIM_OUTPUT_TC2:
6270 case HRTIM_OUTPUT_TD2:
6271 case HRTIM_OUTPUT_TE2:
6272 {
6273 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET)
6274 {
6275 /* Output 2 was active when the delayed idle protection was triggered */
6276 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
6277 }
6278 else
6279 {
6280 /* Output 2 was inactive when the delayed idle protection was triggered */
6281 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
6282 }
6283 break;
6284 }
6285
6286 default:
6287 {
6288 delayed_protection_status = 0xFFFFFFFFUL;
6289 break;
6290 }
6291 }
6292
6293 return delayed_protection_status;
6294 }
6295
6296 /**
6297 * @brief Return the actual status (active or inactive) of the burst mode controller
6298 * @param hhrtim pointer to HAL HRTIM handle
6299 * @retval Burst mode controller status
6300 */
HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim)6301 uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim)
6302 {
6303 uint32_t burst_mode_status;
6304
6305 /* Read burst mode status */
6306 burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
6307
6308 return burst_mode_status;
6309 }
6310
6311 /**
6312 * @brief Indicate on which output the signal is currently active (when the
6313 * push pull mode is enabled).
6314 * @param hhrtim pointer to HAL HRTIM handle
6315 * @param TimerIdx Timer index
6316 * This parameter can be one of the following values:
6317 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6318 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6319 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6320 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6321 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6322 * @retval Burst mode controller status
6323 */
HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6324 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim,
6325 uint32_t TimerIdx)
6326 {
6327 uint32_t current_pushpull_status;
6328
6329 /* Check the parameters */
6330 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6331
6332 /* Read current push pull status */
6333 current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
6334
6335 return current_pushpull_status;
6336 }
6337
6338
6339 /**
6340 * @brief Indicate on which output the signal was applied, in push-pull mode,
6341 balanced fault mode or delayed idle mode, when the protection was triggered.
6342 * @param hhrtim pointer to HAL HRTIM handle
6343 * @param TimerIdx Timer index
6344 * This parameter can be one of the following values:
6345 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6346 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6347 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6348 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6349 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6350 * @retval Idle Push Pull Status
6351 */
HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6352 uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim,
6353 uint32_t TimerIdx)
6354 {
6355 uint32_t idle_pushpull_status;
6356
6357 /* Check the parameters */
6358 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6359
6360 /* Read current push pull status */
6361 idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
6362
6363 return idle_pushpull_status;
6364 }
6365
6366 /**
6367 * @}
6368 */
6369
6370 /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
6371 * @brief Functions called when HRTIM generates an interrupt
6372 * 7 interrupts can be generated by the master timer:
6373 * - Master timer registers update
6374 * - Synchronization event received
6375 * - Master timer repetition event
6376 * - Master Compare 1 to 4 event
6377 * 14 interrupts can be generated by each timing unit:
6378 * - Delayed protection triggered
6379 * - Counter reset or roll-over event
6380 * - Output 1 and output 2 reset (transition active to inactive)
6381 * - Output 1 and output 2 set (transition inactive to active)
6382 * - Capture 1 and 2 events
6383 * - Timing unit registers update
6384 * - Repetition event
6385 * - Compare 1 to 4 event
6386 * 7 global interrupts are generated for the whole HRTIM:
6387 * - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
6388 * - Burst mode period completed
6389 @verbatim
6390 ===============================================================================
6391 ##### HRTIM interrupts handling #####
6392 ===============================================================================
6393 [..]
6394 This subsection provides a set of functions allowing to manage the HRTIM
6395 interrupts:
6396 (+) HRTIM interrupt handler
6397 (+) Callback function called when Fault1 interrupt occurs
6398 (+) Callback function called when Fault2 interrupt occurs
6399 (+) Callback function called when Fault3 interrupt occurs
6400 (+) Callback function called when Fault4 interrupt occurs
6401 (+) Callback function called when Fault5 interrupt occurs
6402 (+) Callback function called when system Fault interrupt occurs
6403 (+) Callback function called when burst mode period interrupt occurs
6404 (+) Callback function called when synchronization input interrupt occurs
6405 (+) Callback function called when a timer register update interrupt occurs
6406 (+) Callback function called when a timer repetition interrupt occurs
6407 (+) Callback function called when a compare 1 match interrupt occurs
6408 (+) Callback function called when a compare 2 match interrupt occurs
6409 (+) Callback function called when a compare 3 match interrupt occurs
6410 (+) Callback function called when a compare 4 match interrupt occurs
6411 (+) Callback function called when a capture 1 interrupt occurs
6412 (+) Callback function called when a capture 2 interrupt occurs
6413 (+) Callback function called when a delayed protection interrupt occurs
6414 (+) Callback function called when a timer counter reset interrupt occurs
6415 (+) Callback function called when a timer output 1 set interrupt occurs
6416 (+) Callback function called when a timer output 1 reset interrupt occurs
6417 (+) Callback function called when a timer output 2 set interrupt occurs
6418 (+) Callback function called when a timer output 2 reset interrupt occurs
6419 (+) Callback function called when a timer output 2 reset interrupt occurs
6420 (+) Callback function called upon completion of a burst DMA transfer
6421 (+) HRTIM callback function registration
6422 (+) HRTIM callback function unregistration
6423 (+) HRTIM Timer x callback function registration
6424 (+) HRTIM Timer x callback function unregistration
6425
6426 @endverbatim
6427 * @{
6428 */
6429
6430 /**
6431 * @brief This function handles HRTIM interrupt request.
6432 * @param hhrtim pointer to HAL HRTIM handle
6433 * @param TimerIdx Timer index
6434 * This parameter can be any value of HRTIM_Timer_Index
6435 * @retval None
6436 */
HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6437 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
6438 uint32_t TimerIdx)
6439 {
6440 /* HRTIM interrupts handling */
6441 if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
6442 {
6443 HRTIM_HRTIM_ISR(hhrtim);
6444 }
6445 else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
6446 {
6447 /* Master related interrupts handling */
6448 HRTIM_Master_ISR(hhrtim);
6449 }
6450 else
6451 {
6452 /* Timing unit related interrupts handling */
6453 HRTIM_Timer_ISR(hhrtim, TimerIdx);
6454 }
6455
6456 }
6457
6458 /**
6459 * @brief Callback function invoked when a fault 1 interrupt occurred
6460 * @param hhrtim pointer to HAL HRTIM handle * @retval None
6461 * @retval None
6462 */
HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)6463 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim)
6464 {
6465 /* Prevent unused argument(s) compilation warning */
6466 UNUSED(hhrtim);
6467
6468 /* NOTE : This function should not be modified, when the callback is needed,
6469 the HAL_HRTIM_Fault1Callback could be implemented in the user file
6470 */
6471 }
6472
6473 /**
6474 * @brief Callback function invoked when a fault 2 interrupt occurred
6475 * @param hhrtim pointer to HAL HRTIM handle
6476 * @retval None
6477 */
HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)6478 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim)
6479 {
6480 /* Prevent unused argument(s) compilation warning */
6481 UNUSED(hhrtim);
6482
6483 /* NOTE : This function should not be modified, when the callback is needed,
6484 the HAL_HRTIM_Fault2Callback could be implemented in the user file
6485 */
6486 }
6487
6488 /**
6489 * @brief Callback function invoked when a fault 3 interrupt occurred
6490 * @param hhrtim pointer to HAL HRTIM handle
6491 * @retval None
6492 */
HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)6493 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim)
6494 {
6495 /* Prevent unused argument(s) compilation warning */
6496 UNUSED(hhrtim);
6497
6498 /* NOTE : This function should not be modified, when the callback is needed,
6499 the HAL_HRTIM_Fault3Callback could be implemented in the user file
6500 */
6501 }
6502
6503 /**
6504 * @brief Callback function invoked when a fault 4 interrupt occurred
6505 * @param hhrtim pointer to HAL HRTIM handle
6506 * @retval None
6507 */
HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)6508 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim)
6509 {
6510 /* Prevent unused argument(s) compilation warning */
6511 UNUSED(hhrtim);
6512
6513 /* NOTE : This function should not be modified, when the callback is needed,
6514 the HAL_HRTIM_Fault4Callback could be implemented in the user file
6515 */
6516 }
6517
6518 /**
6519 * @brief Callback function invoked when a fault 5 interrupt occurred
6520 * @param hhrtim pointer to HAL HRTIM handle
6521 * @retval None
6522 */
HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)6523 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim)
6524 {
6525 /* Prevent unused argument(s) compilation warning */
6526 UNUSED(hhrtim);
6527
6528 /* NOTE : This function should not be modified, when the callback is needed,
6529 the HAL_HRTIM_Fault5Callback could be implemented in the user file
6530 */
6531 }
6532
6533 /**
6534 * @brief Callback function invoked when a system fault interrupt occurred
6535 * @param hhrtim pointer to HAL HRTIM handle
6536 * @retval None
6537 */
HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)6538 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim)
6539 {
6540 /* Prevent unused argument(s) compilation warning */
6541 UNUSED(hhrtim);
6542
6543 /* NOTE : This function should not be modified, when the callback is needed,
6544 the HAL_HRTIM_SystemFaultCallback could be implemented in the user file
6545 */
6546 }
6547
6548 /**
6549 * @brief Callback function invoked when the end of the burst mode period is reached
6550 * @param hhrtim pointer to HAL HRTIM handle
6551 * @retval None
6552 */
HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)6553 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim)
6554 {
6555 /* Prevent unused argument(s) compilation warning */
6556 UNUSED(hhrtim);
6557
6558 /* NOTE : This function should not be modified, when the callback is needed,
6559 the HAL_HRTIM_BurstModeCallback could be implemented in the user file
6560 */
6561 }
6562
6563 /**
6564 * @brief Callback function invoked when a synchronization input event is received
6565 * @param hhrtim pointer to HAL HRTIM handle
6566 * @retval None
6567 */
HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)6568 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim)
6569 {
6570 /* Prevent unused argument(s) compilation warning */
6571 UNUSED(hhrtim);
6572
6573 /* NOTE : This function should not be modified, when the callback is needed,
6574 the HAL_HRTIM_SynchronizationEventCallback could be implemented in the user file
6575 */
6576 }
6577
6578 /**
6579 * @brief Callback function invoked when timer registers are updated
6580 * @param hhrtim pointer to HAL HRTIM handle
6581 * @param TimerIdx Timer index
6582 * This parameter can be one of the following values:
6583 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6584 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6585 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6586 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6587 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6588 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6589 * @retval None
6590 */
HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6591 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
6592 uint32_t TimerIdx)
6593 {
6594 /* Prevent unused argument(s) compilation warning */
6595 UNUSED(hhrtim);
6596 UNUSED(TimerIdx);
6597
6598 /* NOTE : This function should not be modified, when the callback is needed,
6599 the HAL_HRTIM_Master_RegistersUpdateCallback could be implemented in the user file
6600 */
6601 }
6602
6603 /**
6604 * @brief Callback function invoked when timer repetition period has elapsed
6605 * @param hhrtim pointer to HAL HRTIM handle
6606 * @param TimerIdx Timer index
6607 * This parameter can be one of the following values:
6608 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6609 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6610 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6611 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6612 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6613 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6614 * @retval None
6615 */
HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6616 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
6617 uint32_t TimerIdx)
6618 {
6619 /* Prevent unused argument(s) compilation warning */
6620 UNUSED(hhrtim);
6621 UNUSED(TimerIdx);
6622
6623 /* NOTE : This function should not be modified, when the callback is needed,
6624 the HAL_HRTIM_Master_RepetitionEventCallback could be implemented in the user file
6625 */
6626 }
6627
6628 /**
6629 * @brief Callback function invoked when the timer counter matches the value
6630 * programmed in the compare 1 register
6631 * @param hhrtim pointer to HAL HRTIM handle
6632 * @param TimerIdx Timer index
6633 * This parameter can be one of the following values:
6634 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6635 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6636 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6637 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6638 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6639 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6640 * @retval None
6641 */
HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6642 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
6643 uint32_t TimerIdx)
6644 {
6645 /* Prevent unused argument(s) compilation warning */
6646 UNUSED(hhrtim);
6647 UNUSED(TimerIdx);
6648
6649 /* NOTE : This function should not be modified, when the callback is needed,
6650 the HAL_HRTIM_Master_Compare1EventCallback could be implemented in the user file
6651 */
6652 }
6653
6654 /**
6655 * @brief Callback function invoked when the timer counter matches the value
6656 * programmed in the compare 2 register
6657 * @param hhrtim pointer to HAL HRTIM handle
6658 * @retval None
6659 * @param TimerIdx Timer index
6660 * This parameter can be one of the following values:
6661 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6662 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6663 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6664 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6665 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6666 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6667 */
HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6668 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
6669 uint32_t TimerIdx)
6670 {
6671 /* Prevent unused argument(s) compilation warning */
6672 UNUSED(hhrtim);
6673 UNUSED(TimerIdx);
6674
6675 /* NOTE : This function should not be modified, when the callback is needed,
6676 the HAL_HRTIM_Master_Compare2EventCallback could be implemented in the user file
6677 */
6678 }
6679
6680 /**
6681 * @brief Callback function invoked when the timer counter matches the value
6682 * programmed in the compare 3 register
6683 * @param hhrtim pointer to HAL HRTIM handle
6684 * @param TimerIdx Timer index
6685 * This parameter can be one of the following values:
6686 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6687 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6688 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6689 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6690 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6691 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6692 * @retval None
6693 */
HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6694 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
6695 uint32_t TimerIdx)
6696 {
6697 /* Prevent unused argument(s) compilation warning */
6698 UNUSED(hhrtim);
6699 UNUSED(TimerIdx);
6700
6701 /* NOTE : This function should not be modified, when the callback is needed,
6702 the HAL_HRTIM_Master_Compare3EventCallback could be implemented in the user file
6703 */
6704 }
6705
6706 /**
6707 * @brief Callback function invoked when the timer counter matches the value
6708 * programmed in the compare 4 register.
6709 * @param hhrtim pointer to HAL HRTIM handle
6710 * @param TimerIdx Timer index
6711 * This parameter can be one of the following values:
6712 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6713 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6714 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6715 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6716 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6717 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6718 * @retval None
6719 */
HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6720 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
6721 uint32_t TimerIdx)
6722 {
6723 /* Prevent unused argument(s) compilation warning */
6724 UNUSED(hhrtim);
6725 UNUSED(TimerIdx);
6726
6727 /* NOTE : This function should not be modified, when the callback is needed,
6728 the HAL_HRTIM_Master_Compare4EventCallback could be implemented in the user file
6729 */
6730 }
6731
6732 /**
6733 * @brief Callback function invoked when the timer x capture 1 event occurs
6734 * @param hhrtim pointer to HAL HRTIM handle
6735 * @param TimerIdx Timer index
6736 * This parameter can be one of the following values:
6737 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6738 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6739 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6740 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6741 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6742 * @retval None
6743 */
HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6744 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
6745 uint32_t TimerIdx)
6746 {
6747 /* Prevent unused argument(s) compilation warning */
6748 UNUSED(hhrtim);
6749 UNUSED(TimerIdx);
6750
6751 /* NOTE : This function should not be modified, when the callback is needed,
6752 the HAL_HRTIM_Timer_Capture1EventCallback could be implemented in the user file
6753 */
6754 }
6755
6756 /**
6757 * @brief Callback function invoked when the timer x capture 2 event occurs
6758 * @param hhrtim pointer to HAL HRTIM handle
6759 * @param TimerIdx Timer index
6760 * This parameter can be one of the following values:
6761 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6762 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6763 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6764 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6765 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6766 * @retval None
6767 */
HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6768 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
6769 uint32_t TimerIdx)
6770 {
6771 /* Prevent unused argument(s) compilation warning */
6772 UNUSED(hhrtim);
6773 UNUSED(TimerIdx);
6774
6775 /* NOTE : This function should not be modified, when the callback is needed,
6776 the HAL_HRTIM_Timer_Capture2EventCallback could be implemented in the user file
6777 */
6778 }
6779
6780 /**
6781 * @brief Callback function invoked when the delayed idle or balanced idle mode is
6782 * entered.
6783 * @param hhrtim pointer to HAL HRTIM handle
6784 * @param TimerIdx Timer index
6785 * This parameter can be one of the following values:
6786 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6787 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6788 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6789 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6790 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6791 * @retval None
6792 */
HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6793 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
6794 uint32_t TimerIdx)
6795 {
6796 /* Prevent unused argument(s) compilation warning */
6797 UNUSED(hhrtim);
6798 UNUSED(TimerIdx);
6799
6800 /* NOTE : This function should not be modified, when the callback is needed,
6801 the HAL_HRTIM_Timer_DelayedProtectionCallback could be implemented in the user file
6802 */
6803 }
6804
6805 /**
6806 * @brief Callback function invoked when the timer x counter reset/roll-over
6807 * event occurs.
6808 * @param hhrtim pointer to HAL HRTIM handle
6809 * @param TimerIdx Timer index
6810 * This parameter can be one of the following values:
6811 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6812 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6813 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6814 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6815 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6816 * @retval None
6817 */
HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6818 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
6819 uint32_t TimerIdx)
6820 {
6821 /* Prevent unused argument(s) compilation warning */
6822 UNUSED(hhrtim);
6823 UNUSED(TimerIdx);
6824
6825 /* NOTE : This function should not be modified, when the callback is needed,
6826 the HAL_HRTIM_Timer_CounterResetCallback could be implemented in the user file
6827 */
6828 }
6829
6830 /**
6831 * @brief Callback function invoked when the timer x output 1 is set
6832 * @param hhrtim pointer to HAL HRTIM handle
6833 * @param TimerIdx Timer index
6834 * This parameter can be one of the following values:
6835 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6836 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6837 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6838 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6839 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6840 * @retval None
6841 */
HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6842 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
6843 uint32_t TimerIdx)
6844 {
6845 /* Prevent unused argument(s) compilation warning */
6846 UNUSED(hhrtim);
6847 UNUSED(TimerIdx);
6848
6849 /* NOTE : This function should not be modified, when the callback is needed,
6850 the HAL_HRTIM_Timer_Output1SetCallback could be implemented in the user file
6851 */
6852 }
6853
6854 /**
6855 * @brief Callback function invoked when the timer x output 1 is reset
6856 * @param hhrtim pointer to HAL HRTIM handle
6857 * @param TimerIdx Timer index
6858 * This parameter can be one of the following values:
6859 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6860 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6861 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6862 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6863 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6864 * @retval None
6865 */
HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6866 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
6867 uint32_t TimerIdx)
6868 {
6869 /* Prevent unused argument(s) compilation warning */
6870 UNUSED(hhrtim);
6871 UNUSED(TimerIdx);
6872
6873 /* NOTE : This function should not be modified, when the callback is needed,
6874 the HAL_HRTIM_Timer_Output1ResetCallback could be implemented in the user file
6875 */
6876 }
6877
6878 /**
6879 * @brief Callback function invoked when the timer x output 2 is set
6880 * @param hhrtim pointer to HAL HRTIM handle
6881 * @param TimerIdx Timer index
6882 * This parameter can be one of the following values:
6883 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6884 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6885 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6886 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6887 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6888 * @retval None
6889 */
HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6890 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
6891 uint32_t TimerIdx)
6892 {
6893 /* Prevent unused argument(s) compilation warning */
6894 UNUSED(hhrtim);
6895 UNUSED(TimerIdx);
6896
6897 /* NOTE : This function should not be modified, when the callback is needed,
6898 the HAL_HRTIM_Timer_Output2SetCallback could be implemented in the user file
6899 */
6900 }
6901
6902 /**
6903 * @brief Callback function invoked when the timer x output 2 is reset
6904 * @param hhrtim pointer to HAL HRTIM handle
6905 * @param TimerIdx Timer index
6906 * This parameter can be one of the following values:
6907 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6908 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6909 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6910 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6911 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6912 * @retval None
6913 */
HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6914 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
6915 uint32_t TimerIdx)
6916 {
6917 /* Prevent unused argument(s) compilation warning */
6918 UNUSED(hhrtim);
6919 UNUSED(TimerIdx);
6920
6921 /* NOTE : This function should not be modified, when the callback is needed,
6922 the HAL_HRTIM_Timer_Output2ResetCallback could be implemented in the user file
6923 */
6924 }
6925
6926 /**
6927 * @brief Callback function invoked when a DMA burst transfer is completed
6928 * @param hhrtim pointer to HAL HRTIM handle
6929 * @param TimerIdx Timer index
6930 * This parameter can be one of the following values:
6931 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6932 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6933 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6934 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6935 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6936 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6937 * @retval None
6938 */
HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)6939 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
6940 uint32_t TimerIdx)
6941 {
6942 /* Prevent unused argument(s) compilation warning */
6943 UNUSED(hhrtim);
6944 UNUSED(TimerIdx);
6945
6946 /* NOTE : This function should not be modified, when the callback is needed,
6947 the HAL_HRTIM_BurstDMATransferCallback could be implemented in the user file
6948 */
6949 }
6950
6951 /**
6952 * @brief Callback function invoked when a DMA error occurs
6953 * @param hhrtim pointer to HAL HRTIM handle
6954 * @retval None
6955 */
HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef * hhrtim)6956 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
6957 {
6958 /* Prevent unused argument(s) compilation warning */
6959 UNUSED(hhrtim);
6960
6961 /* NOTE : This function should not be modified, when the callback is needed,
6962 the HAL_HRTIM_ErrorCallback could be implemented in the user file
6963 */
6964 }
6965
6966 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
6967 /**
6968 * @brief HRTIM callback function registration
6969 * @param hhrtim pointer to HAL HRTIM handle
6970 * @param CallbackID ID of the HRTIM callback function to register
6971 * This parameter can be one of the following values:
6972 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
6973 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
6974 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
6975 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
6976 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
6977 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
6978 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
6979 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
6980 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
6981 * @arg HAL_HRTIM_MSPINIT_CB_ID
6982 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
6983 * @param pCallback Callback function pointer
6984 * @retval HAL status
6985 */
HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID,pHRTIM_CallbackTypeDef pCallback)6986 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim,
6987 HAL_HRTIM_CallbackIDTypeDef CallbackID,
6988 pHRTIM_CallbackTypeDef pCallback)
6989 {
6990 HAL_StatusTypeDef status = HAL_OK;
6991
6992 if (pCallback == NULL)
6993 {
6994 /* Update the state */
6995 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
6996
6997 return HAL_ERROR;
6998 }
6999
7000 /* Process locked */
7001 __HAL_LOCK(hhrtim);
7002
7003 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7004 {
7005 switch (CallbackID)
7006 {
7007 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
7008 hhrtim->Fault1Callback = pCallback;
7009 break;
7010
7011 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
7012 hhrtim->Fault2Callback = pCallback;
7013 break;
7014
7015 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
7016 hhrtim->Fault3Callback = pCallback;
7017 break;
7018
7019 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
7020 hhrtim->Fault4Callback = pCallback;
7021 break;
7022
7023 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
7024 hhrtim->Fault5Callback = pCallback;
7025 break;
7026
7027 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
7028 hhrtim->SystemFaultCallback = pCallback;
7029 break;
7030
7031
7032 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
7033 hhrtim->BurstModePeriodCallback = pCallback;
7034 break;
7035
7036 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
7037 hhrtim->SynchronizationEventCallback = pCallback;
7038 break;
7039
7040 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
7041 hhrtim->ErrorCallback = pCallback;
7042 break;
7043
7044 case HAL_HRTIM_MSPINIT_CB_ID :
7045 hhrtim->MspInitCallback = pCallback;
7046 break;
7047
7048 case HAL_HRTIM_MSPDEINIT_CB_ID :
7049 hhrtim->MspDeInitCallback = pCallback;
7050 break;
7051
7052 default :
7053 /* Update the state */
7054 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7055
7056 /* Return error status */
7057 status = HAL_ERROR;
7058 break;
7059 }
7060 }
7061 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
7062 {
7063 switch (CallbackID)
7064 {
7065 case HAL_HRTIM_MSPINIT_CB_ID :
7066 hhrtim->MspInitCallback = pCallback;
7067 break;
7068
7069 case HAL_HRTIM_MSPDEINIT_CB_ID :
7070 hhrtim->MspDeInitCallback = pCallback;
7071 break;
7072
7073 default :
7074 /* Update the state */
7075 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7076
7077 /* Return error status */
7078 status = HAL_ERROR;
7079 break;
7080 }
7081 }
7082 else
7083 {
7084 /* Update the state */
7085 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7086
7087 /* Return error status */
7088 status = HAL_ERROR;
7089 }
7090
7091 /* Release Lock */
7092 __HAL_UNLOCK(hhrtim);
7093
7094 return status;
7095 }
7096
7097 /**
7098 * @brief HRTIM callback function un-registration
7099 * @param hhrtim pointer to HAL HRTIM handle
7100 * @param CallbackID ID of the HRTIM callback function to unregister
7101 * This parameter can be one of the following values:
7102 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
7103 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
7104 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
7105 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
7106 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
7107 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
7108 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
7109 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
7110 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
7111 * @arg HAL_HRTIM_MSPINIT_CB_ID
7112 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
7113 * @retval HAL status
7114 */
HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID)7115 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim,
7116 HAL_HRTIM_CallbackIDTypeDef CallbackID)
7117 {
7118 HAL_StatusTypeDef status = HAL_OK;
7119
7120 /* Process locked */
7121 __HAL_LOCK(hhrtim);
7122
7123 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7124 {
7125 switch (CallbackID)
7126 {
7127 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
7128 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
7129 break;
7130
7131 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
7132 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
7133 break;
7134
7135 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
7136 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
7137 break;
7138
7139 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
7140 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
7141 break;
7142
7143 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
7144 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
7145 break;
7146
7147 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
7148 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
7149 break;
7150
7151
7152 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
7153 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
7154 break;
7155
7156 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
7157 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
7158 break;
7159
7160 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
7161 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
7162 break;
7163
7164 case HAL_HRTIM_MSPINIT_CB_ID :
7165 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
7166 break;
7167
7168 case HAL_HRTIM_MSPDEINIT_CB_ID :
7169 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
7170 break;
7171
7172 default :
7173 /* Update the state */
7174 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7175
7176 /* Return error status */
7177 status = HAL_ERROR;
7178 break;
7179 }
7180 }
7181 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
7182 {
7183 switch (CallbackID)
7184 {
7185 case HAL_HRTIM_MSPINIT_CB_ID :
7186 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
7187 break;
7188
7189 case HAL_HRTIM_MSPDEINIT_CB_ID :
7190 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
7191 break;
7192
7193 default :
7194 /* Update the state */
7195 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7196
7197 /* Return error status */
7198 status = HAL_ERROR;
7199 break;
7200 }
7201 }
7202 else
7203 {
7204 /* Update the state */
7205 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7206
7207 /* Return error status */
7208 status = HAL_ERROR;
7209 }
7210
7211 /* Release Lock */
7212 __HAL_UNLOCK(hhrtim);
7213
7214 return status;
7215 }
7216
7217 /**
7218 * @brief HRTIM Timer x callback function registration
7219 * @param hhrtim pointer to HAL HRTIM handle
7220 * @param CallbackID ID of the HRTIM Timer x callback function to register
7221 * This parameter can be one of the following values:
7222 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
7223 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
7224 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
7225 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
7226 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
7227 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
7228 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
7229 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
7230 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
7231 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
7232 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
7233 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
7234 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
7235 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
7236 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
7237 * @param pCallback Callback function pointer
7238 * @retval HAL status
7239 */
HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID,pHRTIM_TIMxCallbackTypeDef pCallback)7240 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim,
7241 HAL_HRTIM_CallbackIDTypeDef CallbackID,
7242 pHRTIM_TIMxCallbackTypeDef pCallback)
7243 {
7244 HAL_StatusTypeDef status = HAL_OK;
7245
7246 if (pCallback == NULL)
7247 {
7248 /* Update the state */
7249 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7250
7251 return HAL_ERROR;
7252 }
7253
7254 /* Process locked */
7255 __HAL_LOCK(hhrtim);
7256
7257 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7258 {
7259 switch (CallbackID)
7260 {
7261 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
7262 hhrtim->RegistersUpdateCallback = pCallback;
7263 break;
7264
7265 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
7266 hhrtim->RepetitionEventCallback = pCallback;
7267 break;
7268
7269 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
7270 hhrtim->Compare1EventCallback = pCallback;
7271 break;
7272
7273 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
7274 hhrtim->Compare2EventCallback = pCallback;
7275 break;
7276
7277 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
7278 hhrtim->Compare3EventCallback = pCallback;
7279 break;
7280
7281 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
7282 hhrtim->Compare4EventCallback = pCallback;
7283 break;
7284
7285 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
7286 hhrtim->Capture1EventCallback = pCallback;
7287 break;
7288
7289 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
7290 hhrtim->Capture2EventCallback = pCallback;
7291 break;
7292
7293 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
7294 hhrtim->DelayedProtectionCallback = pCallback;
7295 break;
7296
7297 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
7298 hhrtim->CounterResetCallback = pCallback;
7299 break;
7300
7301 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
7302 hhrtim->Output1SetCallback = pCallback;
7303 break;
7304
7305 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
7306 hhrtim->Output1ResetCallback = pCallback;
7307 break;
7308
7309 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
7310 hhrtim->Output2SetCallback = pCallback;
7311 break;
7312
7313 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
7314 hhrtim->Output2ResetCallback = pCallback;
7315 break;
7316
7317 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
7318 hhrtim->BurstDMATransferCallback = pCallback;
7319 break;
7320
7321 default :
7322 /* Update the state */
7323 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7324
7325 /* Return error status */
7326 status = HAL_ERROR;
7327 break;
7328 }
7329 }
7330 else
7331 {
7332 /* Update the state */
7333 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7334
7335 /* Return error status */
7336 status = HAL_ERROR;
7337 }
7338
7339 /* Release Lock */
7340 __HAL_UNLOCK(hhrtim);
7341
7342 return status;
7343 }
7344
7345 /**
7346 * @brief HRTIM Timer x callback function un-registration
7347 * @param hhrtim pointer to HAL HRTIM handle
7348 * @param CallbackID ID of the HRTIM callback Timer x function to unregister
7349 * This parameter can be one of the following values:
7350 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
7351 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
7352 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
7353 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
7354 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
7355 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
7356 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
7357 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
7358 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
7359 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
7360 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
7361 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
7362 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
7363 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
7364 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
7365 * @retval HAL status
7366 */
HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID)7367 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim,
7368 HAL_HRTIM_CallbackIDTypeDef CallbackID)
7369 {
7370 HAL_StatusTypeDef status = HAL_OK;
7371
7372 /* Process locked */
7373 __HAL_LOCK(hhrtim);
7374
7375 if (HAL_HRTIM_STATE_READY == hhrtim->State)
7376 {
7377 switch (CallbackID)
7378 {
7379 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
7380 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
7381 break;
7382
7383 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
7384 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
7385 break;
7386
7387 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
7388 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
7389 break;
7390
7391 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
7392 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
7393 break;
7394
7395 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
7396 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
7397 break;
7398
7399 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
7400 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
7401 break;
7402
7403 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
7404 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
7405 break;
7406
7407 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
7408 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
7409 break;
7410
7411 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
7412 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
7413 break;
7414
7415 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
7416 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
7417 break;
7418
7419 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
7420 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
7421 break;
7422
7423 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
7424 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
7425 break;
7426
7427 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
7428 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
7429 break;
7430
7431 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
7432 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
7433 break;
7434
7435 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
7436 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
7437 break;
7438
7439 default :
7440 /* Update the state */
7441 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7442
7443 /* Return error status */
7444 status = HAL_ERROR;
7445 break;
7446 }
7447 }
7448 else
7449 {
7450 /* Update the state */
7451 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
7452
7453 /* Return error status */
7454 status = HAL_ERROR;
7455 }
7456
7457 /* Release Lock */
7458 __HAL_UNLOCK(hhrtim);
7459
7460 return status;
7461 }
7462 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
7463 /**
7464 * @}
7465 */
7466
7467 /**
7468 * @}
7469 */
7470
7471 /** @addtogroup HRTIM_Private_Functions
7472 * @{
7473 */
7474
7475 /**
7476 * @brief Configure the master timer time base
7477 * @param hhrtim pointer to HAL HRTIM handle
7478 * @param pTimeBaseCfg pointer to the time base configuration structure
7479 * @retval None
7480 */
HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)7481 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim,
7482 const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
7483 {
7484 uint32_t hrtim_mcr;
7485
7486 /* Configure master timer */
7487 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
7488
7489 /* Set the prescaler ratio */
7490 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
7491 hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
7492
7493 /* Set the operating mode */
7494 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
7495 hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
7496
7497 /* Update the HRTIM registers */
7498 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
7499 hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
7500 hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
7501 }
7502
7503 /**
7504 * @brief Configure timing unit (Timer A to Timer E) time base
7505 * @param hhrtim pointer to HAL HRTIM handle
7506 * @param TimerIdx Timer index
7507 * @param pTimeBaseCfg pointer to the time base configuration structure
7508 * @retval None
7509 */
HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)7510 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim,
7511 uint32_t TimerIdx,
7512 const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
7513 {
7514 uint32_t hrtim_timcr;
7515
7516 /* Configure master timing unit */
7517 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
7518
7519 /* Set the prescaler ratio */
7520 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
7521 hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
7522
7523 /* Set the operating mode */
7524 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
7525 hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
7526
7527 /* Update the HRTIM registers */
7528 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
7529 hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
7530 hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
7531 }
7532
7533 /**
7534 * @brief Configure the master timer in waveform mode
7535 * @param hhrtim pointer to HAL HRTIM handle
7536 * @param pTimerCfg pointer to the timer configuration data structure
7537 * @retval None
7538 */
HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,const HRTIM_TimerCfgTypeDef * pTimerCfg)7539 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim,
7540 const HRTIM_TimerCfgTypeDef *pTimerCfg)
7541 {
7542 uint32_t hrtim_mcr;
7543 uint32_t hrtim_bmcr;
7544
7545 /* Configure master timer */
7546 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
7547 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
7548
7549 /* Enable/Disable the half mode */
7550 hrtim_mcr &= ~(HRTIM_MCR_HALF);
7551 hrtim_mcr |= pTimerCfg->HalfModeEnable;
7552
7553 /* Enable/Disable the timer start upon synchronization event reception */
7554 hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
7555 hrtim_mcr |= pTimerCfg->StartOnSync;
7556
7557 /* Enable/Disable the timer reset upon synchronization event reception */
7558 hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
7559 hrtim_mcr |= pTimerCfg->ResetOnSync;
7560
7561 /* Enable/Disable the DAC synchronization event generation */
7562 hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
7563 hrtim_mcr |= pTimerCfg->DACSynchro;
7564
7565 /* Enable/Disable preload mechanism for timer registers */
7566 hrtim_mcr &= ~(HRTIM_MCR_PREEN);
7567 hrtim_mcr |= pTimerCfg->PreloadEnable;
7568
7569 /* Master timer registers update handling */
7570 hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
7571 hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
7572
7573 /* Enable/Disable registers update on repetition */
7574 hrtim_mcr &= ~(HRTIM_MCR_MREPU);
7575 hrtim_mcr |= pTimerCfg->RepetitionUpdate;
7576
7577 /* Set the timer burst mode */
7578 hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
7579 hrtim_bmcr |= pTimerCfg->BurstMode;
7580
7581 /* Update the HRTIM registers */
7582 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
7583 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
7584 }
7585
7586 /**
7587 * @brief Configure timing unit (Timer A to Timer E) in waveform mode
7588 * @param hhrtim pointer to HAL HRTIM handle
7589 * @param TimerIdx Timer index
7590 * @param pTimerCfg pointer to the timer configuration data structure
7591 * @retval None
7592 */
HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimerCfgTypeDef * pTimerCfg)7593 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim,
7594 uint32_t TimerIdx,
7595 const HRTIM_TimerCfgTypeDef *pTimerCfg)
7596 {
7597 uint32_t hrtim_timcr;
7598 uint32_t hrtim_timfltr;
7599 uint32_t hrtim_timoutr;
7600 uint32_t hrtim_timrstr;
7601 uint32_t hrtim_bmcr;
7602
7603 /* UPDGAT bitfield must be reset before programming a new value */
7604 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
7605
7606 /* Configure timing unit (Timer A to Timer E) */
7607 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
7608 hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
7609 hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
7610 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
7611
7612 /* Enable/Disable the half mode */
7613 hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
7614 hrtim_timcr |= pTimerCfg->HalfModeEnable;
7615
7616 /* Enable/Disable the timer start upon synchronization event reception */
7617 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
7618 hrtim_timcr |= pTimerCfg->StartOnSync;
7619
7620 /* Enable/Disable the timer reset upon synchronization event reception */
7621 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
7622 hrtim_timcr |= pTimerCfg->ResetOnSync;
7623
7624 /* Enable/Disable the DAC synchronization event generation */
7625 hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
7626 hrtim_timcr |= pTimerCfg->DACSynchro;
7627
7628 /* Enable/Disable preload mechanism for timer registers */
7629 hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
7630 hrtim_timcr |= pTimerCfg->PreloadEnable;
7631
7632 /* Timing unit registers update handling */
7633 hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
7634 hrtim_timcr |= pTimerCfg->UpdateGating;
7635
7636 /* Enable/Disable registers update on repetition */
7637 hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
7638 if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
7639 {
7640 hrtim_timcr |= HRTIM_TIMCR_TREPU;
7641 }
7642
7643 /* Set the push-pull mode */
7644 hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
7645 hrtim_timcr |= pTimerCfg->PushPull;
7646
7647 /* Enable/Disable registers update on timer counter reset */
7648 hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
7649 hrtim_timcr |= pTimerCfg->ResetUpdate;
7650
7651 /* Set the timer update trigger */
7652 hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
7653 hrtim_timcr |= pTimerCfg->UpdateTrigger;
7654
7655 /* Enable/Disable the fault channel at timer level */
7656 hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
7657 hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
7658
7659 /* Lock/Unlock fault sources at timer level */
7660 hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
7661 hrtim_timfltr |= pTimerCfg->FaultLock;
7662
7663 /* The deadtime cannot be used simultaneously with the push-pull mode */
7664 if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
7665 {
7666 /* Enable/Disable dead time insertion at timer level */
7667 hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
7668 hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
7669 }
7670
7671 /* Enable/Disable delayed protection at timer level
7672 Delayed Idle is available whatever the timer operating mode (regular, push-pull)
7673 Balanced Idle is only available in push-pull mode
7674 */
7675 if (((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
7676 && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
7677 || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
7678 {
7679 hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT | HRTIM_OUTR_DLYPRTEN);
7680 hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
7681 }
7682
7683 /* Set the timer counter reset trigger */
7684 hrtim_timrstr = pTimerCfg->ResetTrigger;
7685
7686 /* Set the timer burst mode */
7687 switch (TimerIdx)
7688 {
7689 case HRTIM_TIMERINDEX_TIMER_A:
7690 {
7691 hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
7692 hrtim_bmcr |= (pTimerCfg->BurstMode << 1U);
7693 break;
7694 }
7695
7696 case HRTIM_TIMERINDEX_TIMER_B:
7697 {
7698 hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
7699 hrtim_bmcr |= (pTimerCfg->BurstMode << 2U);
7700 break;
7701 }
7702
7703 case HRTIM_TIMERINDEX_TIMER_C:
7704 {
7705 hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
7706 hrtim_bmcr |= (pTimerCfg->BurstMode << 3U);
7707 break;
7708 }
7709
7710 case HRTIM_TIMERINDEX_TIMER_D:
7711 {
7712 hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
7713 hrtim_bmcr |= (pTimerCfg->BurstMode << 4U);
7714 break;
7715 }
7716
7717 case HRTIM_TIMERINDEX_TIMER_E:
7718 {
7719 hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
7720 hrtim_bmcr |= (pTimerCfg->BurstMode << 5U);
7721 break;
7722 }
7723
7724 default:
7725 break;
7726 }
7727
7728 /* Update the HRTIM registers */
7729 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
7730 hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
7731 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
7732 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
7733 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
7734 }
7735
7736 /**
7737 * @brief Configure a capture unit
7738 * @param hhrtim pointer to HAL HRTIM handle
7739 * @param TimerIdx Timer index
7740 * @param CaptureUnit Capture unit identifier
7741 * @param Event Event reference
7742 * @retval None
7743 */
HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit,uint32_t Event)7744 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim,
7745 uint32_t TimerIdx,
7746 uint32_t CaptureUnit,
7747 uint32_t Event)
7748 {
7749 uint32_t CaptureTrigger = 0xFFFFFFFFU;
7750
7751 switch (Event)
7752 {
7753 case HRTIM_EVENT_1:
7754 {
7755 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
7756 break;
7757 }
7758
7759 case HRTIM_EVENT_2:
7760 {
7761 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
7762 break;
7763 }
7764
7765 case HRTIM_EVENT_3:
7766 {
7767 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
7768 break;
7769 }
7770
7771 case HRTIM_EVENT_4:
7772 {
7773 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
7774 break;
7775 }
7776
7777 case HRTIM_EVENT_5:
7778 {
7779 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
7780 break;
7781 }
7782
7783 case HRTIM_EVENT_6:
7784 {
7785 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
7786 break;
7787 }
7788
7789 case HRTIM_EVENT_7:
7790 {
7791 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
7792 break;
7793 }
7794
7795 case HRTIM_EVENT_8:
7796 {
7797 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
7798 break;
7799 }
7800
7801 case HRTIM_EVENT_9:
7802 {
7803 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
7804 break;
7805 }
7806
7807 case HRTIM_EVENT_10:
7808 {
7809 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
7810 break;
7811 }
7812
7813 default:
7814 break;
7815 }
7816
7817 switch (CaptureUnit)
7818 {
7819 case HRTIM_CAPTUREUNIT_1:
7820 {
7821 hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
7822 break;
7823 }
7824
7825 case HRTIM_CAPTUREUNIT_2:
7826 {
7827 hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
7828 break;
7829 }
7830
7831 default:
7832 break;
7833 }
7834 }
7835
7836 /**
7837 * @brief Configure the output of a timing unit
7838 * @param hhrtim pointer to HAL HRTIM handle
7839 * @param TimerIdx Timer index
7840 * @param Output timing unit output identifier
7841 * @param pOutputCfg pointer to the output configuration data structure
7842 * @retval None
7843 */
HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,const HRTIM_OutputCfgTypeDef * pOutputCfg)7844 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim,
7845 uint32_t TimerIdx,
7846 uint32_t Output,
7847 const HRTIM_OutputCfgTypeDef *pOutputCfg)
7848 {
7849 uint32_t hrtim_outr;
7850 uint32_t hrtim_dtr;
7851
7852 uint32_t shift = 0U;
7853
7854 hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
7855 hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
7856
7857 switch (Output)
7858 {
7859 case HRTIM_OUTPUT_TA1:
7860 case HRTIM_OUTPUT_TB1:
7861 case HRTIM_OUTPUT_TC1:
7862 case HRTIM_OUTPUT_TD1:
7863 case HRTIM_OUTPUT_TE1:
7864 {
7865 /* Set the output set/reset crossbar */
7866 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
7867 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
7868 break;
7869 }
7870
7871 case HRTIM_OUTPUT_TA2:
7872 case HRTIM_OUTPUT_TB2:
7873 case HRTIM_OUTPUT_TC2:
7874 case HRTIM_OUTPUT_TD2:
7875 case HRTIM_OUTPUT_TE2:
7876 {
7877 /* Set the output set/reset crossbar */
7878 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
7879 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
7880 shift = 16U;
7881 break;
7882 }
7883
7884 default:
7885 break;
7886 }
7887
7888 /* Clear output config */
7889 hrtim_outr &= ~((HRTIM_OUTR_POL1 |
7890 HRTIM_OUTR_IDLM1 |
7891 HRTIM_OUTR_IDLES1 |
7892 HRTIM_OUTR_FAULT1 |
7893 HRTIM_OUTR_CHP1 |
7894 HRTIM_OUTR_DIDL1) << shift);
7895
7896 /* Set the polarity */
7897 hrtim_outr |= (pOutputCfg->Polarity << shift);
7898
7899 /* Set the IDLE mode */
7900 hrtim_outr |= (pOutputCfg->IdleMode << shift);
7901
7902 /* Set the IDLE state */
7903 hrtim_outr |= (pOutputCfg->IdleLevel << shift);
7904
7905 /* Set the FAULT state */
7906 hrtim_outr |= (pOutputCfg->FaultLevel << shift);
7907
7908 /* Set the chopper mode */
7909 hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
7910
7911 /* Set the burst mode entry mode : deadtime insertion when entering the idle
7912 state during a burst mode operation is allowed only under the following
7913 conditions:
7914 - the outputs is active during the burst mode (IDLES=1U)
7915 - positive deadtimes (SDTR/SDTF set to 0U)
7916 */
7917 if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
7918 ((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) &&
7919 ((hrtim_dtr & HRTIM_DTR_SDTF) == (uint32_t)RESET))
7920 {
7921 hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
7922 }
7923
7924 /* Update HRTIM register */
7925 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
7926 }
7927
7928 /**
7929 * @brief Configure an external event channel
7930 * @param hhrtim pointer to HAL HRTIM handle
7931 * @param Event Event channel identifier
7932 * @param pEventCfg pointer to the event channel configuration data structure
7933 * @retval None
7934 */
HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Event,const HRTIM_EventCfgTypeDef * pEventCfg)7935 static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
7936 uint32_t Event,
7937 const HRTIM_EventCfgTypeDef *pEventCfg)
7938 {
7939 uint32_t hrtim_eecr1;
7940 uint32_t hrtim_eecr2;
7941 uint32_t hrtim_eecr3;
7942
7943 /* Configure external event channel */
7944 hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
7945 hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
7946 hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
7947
7948 switch (Event)
7949 {
7950 case HRTIM_EVENT_NONE:
7951 {
7952 /* Update the HRTIM registers */
7953 hhrtim->Instance->sCommonRegs.EECR1 = 0U;
7954 hhrtim->Instance->sCommonRegs.EECR2 = 0U;
7955 hhrtim->Instance->sCommonRegs.EECR3 = 0U;
7956 break;
7957 }
7958
7959 case HRTIM_EVENT_1:
7960 {
7961 hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
7962 hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC);
7963 hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
7964 hrtim_eecr1 |= (pEventCfg->Sensitivity & HRTIM_EECR1_EE1SNS);
7965 /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
7966 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7967 /* Update the HRTIM registers (EE1FAST bit) */
7968 hrtim_eecr1 |= (pEventCfg->FastMode & HRTIM_EECR1_EE1FAST);
7969 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7970 break;
7971 }
7972
7973 case HRTIM_EVENT_2:
7974 {
7975 hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
7976 hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC);
7977 hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR1_EE2POL);
7978 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR1_EE2SNS);
7979 /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
7980 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7981 /* Update the HRTIM registers (EE2FAST bit) */
7982 hrtim_eecr1 |= ((pEventCfg->FastMode << 6U) & HRTIM_EECR1_EE2FAST);
7983 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7984 break;
7985 }
7986
7987 case HRTIM_EVENT_3:
7988 {
7989 hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
7990 hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC);
7991 hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR1_EE3POL);
7992 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR1_EE3SNS);
7993 /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
7994 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7995 /* Update the HRTIM registers (EE3FAST bit) */
7996 hrtim_eecr1 |= ((pEventCfg->FastMode << 12U) & HRTIM_EECR1_EE3FAST);
7997 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7998 break;
7999 }
8000
8001 case HRTIM_EVENT_4:
8002 {
8003 hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
8004 hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC);
8005 hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR1_EE4POL);
8006 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR1_EE4SNS);
8007 /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
8008 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8009 /* Update the HRTIM registers (EE4FAST bit) */
8010 hrtim_eecr1 |= ((pEventCfg->FastMode << 18U) & HRTIM_EECR1_EE4FAST);
8011 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8012 break;
8013 }
8014
8015 case HRTIM_EVENT_5:
8016 {
8017 hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
8018 hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC);
8019 hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR1_EE5POL);
8020 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR1_EE5SNS);
8021 /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
8022 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8023 /* Update the HRTIM registers (EE5FAST bit) */
8024 hrtim_eecr1 |= ((pEventCfg->FastMode << 24U) & HRTIM_EECR1_EE5FAST);
8025 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8026 break;
8027 }
8028
8029 case HRTIM_EVENT_6:
8030 {
8031 hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
8032 hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC);
8033 hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
8034 hrtim_eecr2 |= (pEventCfg->Sensitivity & HRTIM_EECR2_EE6SNS);
8035 hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
8036 hrtim_eecr3 |= (pEventCfg->Filter & HRTIM_EECR3_EE6F);
8037 /* Update the HRTIM registers */
8038 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8039 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8040 break;
8041 }
8042
8043 case HRTIM_EVENT_7:
8044 {
8045 hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
8046 hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC);
8047 hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR2_EE7POL);
8048 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR2_EE7SNS);
8049 hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
8050 hrtim_eecr3 |= ((pEventCfg->Filter << 6U) & HRTIM_EECR3_EE7F);
8051 /* Update the HRTIM registers */
8052 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8053 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8054 break;
8055 }
8056
8057 case HRTIM_EVENT_8:
8058 {
8059 hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
8060 hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC);
8061 hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL);
8062 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS);
8063 hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
8064 hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F);
8065 /* Update the HRTIM registers */
8066 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8067 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8068 break;
8069 }
8070
8071 case HRTIM_EVENT_9:
8072 {
8073 hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
8074 hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC);
8075 hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR2_EE9POL);
8076 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR2_EE9SNS);
8077 hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
8078 hrtim_eecr3 |= ((pEventCfg->Filter << 18U) & HRTIM_EECR3_EE9F);
8079 /* Update the HRTIM registers */
8080 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8081 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8082 break;
8083 }
8084
8085 case HRTIM_EVENT_10:
8086 {
8087 hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
8088 hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC);
8089 hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR2_EE10POL);
8090 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR2_EE10SNS);
8091 hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
8092 hrtim_eecr3 |= ((pEventCfg->Filter << 24U) & HRTIM_EECR3_EE10F);
8093 /* Update the HRTIM registers */
8094 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8095 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8096 break;
8097 }
8098
8099 default:
8100 break;
8101 }
8102 }
8103
8104 /**
8105 * @brief Configure the timer counter reset
8106 * @param hhrtim pointer to HAL HRTIM handle
8107 * @param TimerIdx Timer index
8108 * @param Event Event channel identifier
8109 * @retval None
8110 */
HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Event)8111 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim,
8112 uint32_t TimerIdx,
8113 uint32_t Event)
8114 {
8115 switch (Event)
8116 {
8117 case HRTIM_EVENT_1:
8118 {
8119 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
8120 break;
8121 }
8122
8123 case HRTIM_EVENT_2:
8124 {
8125 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
8126 break;
8127 }
8128
8129 case HRTIM_EVENT_3:
8130 {
8131 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
8132 break;
8133 }
8134
8135 case HRTIM_EVENT_4:
8136 {
8137 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
8138 break;
8139 }
8140
8141 case HRTIM_EVENT_5:
8142 {
8143 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
8144 break;
8145 }
8146
8147 case HRTIM_EVENT_6:
8148 {
8149 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
8150 break;
8151 }
8152
8153 case HRTIM_EVENT_7:
8154 {
8155 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
8156 break;
8157 }
8158
8159 case HRTIM_EVENT_8:
8160 {
8161 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
8162 break;
8163 }
8164
8165 case HRTIM_EVENT_9:
8166 {
8167 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
8168 break;
8169 }
8170
8171 case HRTIM_EVENT_10:
8172 {
8173 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
8174 break;
8175 }
8176
8177 default:
8178 break;
8179 }
8180 }
8181
8182 /**
8183 * @brief Return the interrupt to enable or disable according to the
8184 * OC mode.
8185 * @param hhrtim pointer to HAL HRTIM handle
8186 * @param TimerIdx Timer index
8187 * @param OCChannel Timer output
8188 * This parameter can be one of the following values:
8189 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
8190 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
8191 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
8192 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
8193 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
8194 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
8195 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
8196 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
8197 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
8198 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
8199 * @retval Interrupt to enable or disable
8200 */
HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)8201 static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim,
8202 uint32_t TimerIdx,
8203 uint32_t OCChannel)
8204 {
8205 uint32_t hrtim_set;
8206 uint32_t hrtim_reset;
8207 uint32_t interrupt = 0U;
8208
8209 switch (OCChannel)
8210 {
8211 case HRTIM_OUTPUT_TA1:
8212 case HRTIM_OUTPUT_TB1:
8213 case HRTIM_OUTPUT_TC1:
8214 case HRTIM_OUTPUT_TD1:
8215 case HRTIM_OUTPUT_TE1:
8216 {
8217 /* Retrieves actual OC mode and set interrupt accordingly */
8218 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
8219 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
8220
8221 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8222 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8223 {
8224 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8225 interrupt = HRTIM_TIM_IT_CMP1;
8226 }
8227 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8228 (hrtim_reset == 0U))
8229 {
8230 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8231 interrupt = HRTIM_TIM_IT_SET1;
8232 }
8233 else if ((hrtim_set == 0U) &&
8234 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8235 {
8236 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8237 interrupt = HRTIM_TIM_IT_RST1;
8238 }
8239 else
8240 {
8241 /* nothing to do */
8242 }
8243 break;
8244 }
8245
8246 case HRTIM_OUTPUT_TA2:
8247 case HRTIM_OUTPUT_TB2:
8248 case HRTIM_OUTPUT_TC2:
8249 case HRTIM_OUTPUT_TD2:
8250 case HRTIM_OUTPUT_TE2:
8251 {
8252 /* Retrieves actual OC mode and set interrupt accordingly */
8253 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
8254 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
8255
8256 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8257 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8258 {
8259 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8260 interrupt = HRTIM_TIM_IT_CMP2;
8261 }
8262 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8263 (hrtim_reset == 0U))
8264 {
8265 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8266 interrupt = HRTIM_TIM_IT_SET2;
8267 }
8268 else if ((hrtim_set == 0U) &&
8269 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8270 {
8271 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8272 interrupt = HRTIM_TIM_IT_RST2;
8273 }
8274 else
8275 {
8276 /* nothing to do */
8277 }
8278 break;
8279 }
8280
8281 default:
8282 break;
8283 }
8284
8285 return interrupt;
8286 }
8287
8288 /**
8289 * @brief Return the DMA request to enable or disable according to the
8290 * OC mode.
8291 * @param hhrtim pointer to HAL HRTIM handle
8292 * @param TimerIdx Timer index
8293 * @param OCChannel Timer output
8294 * This parameter can be one of the following values:
8295 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
8296 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
8297 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
8298 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
8299 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
8300 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
8301 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
8302 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
8303 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
8304 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
8305 * @retval DMA request to enable or disable
8306 */
HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)8307 static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim,
8308 uint32_t TimerIdx,
8309 uint32_t OCChannel)
8310 {
8311 uint32_t hrtim_set;
8312 uint32_t hrtim_reset;
8313 uint32_t dma_request = 0U;
8314
8315 switch (OCChannel)
8316 {
8317 case HRTIM_OUTPUT_TA1:
8318 case HRTIM_OUTPUT_TB1:
8319 case HRTIM_OUTPUT_TC1:
8320 case HRTIM_OUTPUT_TD1:
8321 case HRTIM_OUTPUT_TE1:
8322 {
8323 /* Retrieves actual OC mode and set dma_request accordingly */
8324 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
8325 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
8326
8327 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8328 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8329 {
8330 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8331 dma_request = HRTIM_TIM_DMA_CMP1;
8332 }
8333 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
8334 (hrtim_reset == 0U))
8335 {
8336 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8337 dma_request = HRTIM_TIM_DMA_SET1;
8338 }
8339 else if ((hrtim_set == 0U) &&
8340 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
8341 {
8342 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8343 dma_request = HRTIM_TIM_DMA_RST1;
8344 }
8345 else
8346 {
8347 /* nothing to do */
8348 }
8349 break;
8350 }
8351
8352 case HRTIM_OUTPUT_TA2:
8353 case HRTIM_OUTPUT_TB2:
8354 case HRTIM_OUTPUT_TC2:
8355 case HRTIM_OUTPUT_TD2:
8356 case HRTIM_OUTPUT_TE2:
8357 {
8358 /* Retrieves actual OC mode and set dma_request accordingly */
8359 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
8360 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
8361
8362 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8363 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8364 {
8365 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
8366 dma_request = HRTIM_TIM_DMA_CMP2;
8367 }
8368 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
8369 (hrtim_reset == 0U))
8370 {
8371 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
8372 dma_request = HRTIM_TIM_DMA_SET2;
8373 }
8374 else if ((hrtim_set == 0U) &&
8375 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
8376 {
8377 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
8378 dma_request = HRTIM_TIM_DMA_RST2;
8379 }
8380 else
8381 {
8382 /* nothing to do */
8383 }
8384 break;
8385 }
8386
8387 default:
8388 break;
8389 }
8390
8391 return dma_request;
8392 }
8393
HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8394 static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim,
8395 uint32_t TimerIdx)
8396 {
8397 DMA_HandleTypeDef *hdma = (DMA_HandleTypeDef *)NULL;
8398
8399 switch (TimerIdx)
8400 {
8401 case HRTIM_TIMERINDEX_MASTER:
8402 {
8403 hdma = hhrtim->hdmaMaster;
8404 break;
8405 }
8406
8407 case HRTIM_TIMERINDEX_TIMER_A:
8408 {
8409 hdma = hhrtim->hdmaTimerA;
8410 break;
8411 }
8412
8413 case HRTIM_TIMERINDEX_TIMER_B:
8414 {
8415 hdma = hhrtim->hdmaTimerB;
8416 break;
8417 }
8418
8419 case HRTIM_TIMERINDEX_TIMER_C:
8420 {
8421 hdma = hhrtim->hdmaTimerC;
8422 break;
8423 }
8424
8425 case HRTIM_TIMERINDEX_TIMER_D:
8426 {
8427 hdma = hhrtim->hdmaTimerD;
8428 break;
8429 }
8430
8431 case HRTIM_TIMERINDEX_TIMER_E:
8432 {
8433 hdma = hhrtim->hdmaTimerE;
8434 break;
8435 }
8436
8437 default:
8438 break;
8439 }
8440
8441 return hdma;
8442 }
8443
GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,const DMA_HandleTypeDef * hdma)8444 static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim,
8445 const DMA_HandleTypeDef *hdma)
8446 {
8447 uint32_t timed_idx = 0xFFFFFFFFU;
8448
8449 if (hdma == hhrtim->hdmaMaster)
8450 {
8451 timed_idx = HRTIM_TIMERINDEX_MASTER;
8452 }
8453 else if (hdma == hhrtim->hdmaTimerA)
8454 {
8455 timed_idx = HRTIM_TIMERINDEX_TIMER_A;
8456 }
8457 else if (hdma == hhrtim->hdmaTimerB)
8458 {
8459 timed_idx = HRTIM_TIMERINDEX_TIMER_B;
8460 }
8461 else if (hdma == hhrtim->hdmaTimerC)
8462 {
8463 timed_idx = HRTIM_TIMERINDEX_TIMER_C;
8464 }
8465 else if (hdma == hhrtim->hdmaTimerD)
8466 {
8467 timed_idx = HRTIM_TIMERINDEX_TIMER_D;
8468 }
8469 else if (hdma == hhrtim->hdmaTimerE)
8470 {
8471 timed_idx = HRTIM_TIMERINDEX_TIMER_E;
8472 }
8473 else
8474 {
8475 /* nothing to do */
8476 }
8477 return timed_idx;
8478 }
8479
8480 /**
8481 * @brief Force an immediate transfer from the preload to the active
8482 * registers.
8483 * @param hhrtim pointer to HAL HRTIM handle
8484 * @param TimerIdx Timer index
8485 * @retval None
8486 */
HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8487 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim,
8488 uint32_t TimerIdx)
8489 {
8490 switch (TimerIdx)
8491 {
8492 case HRTIM_TIMERINDEX_MASTER:
8493 {
8494 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
8495 break;
8496 }
8497
8498 case HRTIM_TIMERINDEX_TIMER_A:
8499 {
8500 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
8501 break;
8502 }
8503
8504 case HRTIM_TIMERINDEX_TIMER_B:
8505 {
8506 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
8507 break;
8508 }
8509
8510 case HRTIM_TIMERINDEX_TIMER_C:
8511 {
8512 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
8513 break;
8514 }
8515
8516 case HRTIM_TIMERINDEX_TIMER_D:
8517 {
8518 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
8519 break;
8520 }
8521
8522 case HRTIM_TIMERINDEX_TIMER_E:
8523 {
8524 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
8525 break;
8526 }
8527
8528 default:
8529 break;
8530 }
8531 }
8532
8533
8534 /**
8535 * @brief HRTIM interrupts service routine
8536 * @param hhrtim pointer to HAL HRTIM handle
8537 * @retval None
8538 */
HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)8539 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim)
8540 {
8541 uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
8542 uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
8543
8544 /* Fault 1 event */
8545 if ((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET)
8546 {
8547 if ((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET)
8548 {
8549 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
8550
8551 /* Invoke Fault 1 event callback */
8552 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8553 hhrtim->Fault1Callback(hhrtim);
8554 #else
8555 HAL_HRTIM_Fault1Callback(hhrtim);
8556 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8557 }
8558 }
8559
8560 /* Fault 2 event */
8561 if ((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET)
8562 {
8563 if ((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET)
8564 {
8565 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
8566
8567 /* Invoke Fault 2 event callback */
8568 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8569 hhrtim->Fault2Callback(hhrtim);
8570 #else
8571 HAL_HRTIM_Fault2Callback(hhrtim);
8572 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8573 }
8574 }
8575
8576 /* Fault 3 event */
8577 if ((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET)
8578 {
8579 if ((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET)
8580 {
8581 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
8582
8583 /* Invoke Fault 3 event callback */
8584 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8585 hhrtim->Fault3Callback(hhrtim);
8586 #else
8587 HAL_HRTIM_Fault3Callback(hhrtim);
8588 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8589 }
8590 }
8591
8592 /* Fault 4 event */
8593 if ((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET)
8594 {
8595 if ((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET)
8596 {
8597 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
8598
8599 /* Invoke Fault 4 event callback */
8600 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8601 hhrtim->Fault4Callback(hhrtim);
8602 #else
8603 HAL_HRTIM_Fault4Callback(hhrtim);
8604 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8605 }
8606 }
8607
8608 /* Fault 5 event */
8609 if ((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET)
8610 {
8611 if ((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET)
8612 {
8613 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
8614
8615 /* Invoke Fault 5 event callback */
8616 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8617 hhrtim->Fault5Callback(hhrtim);
8618 #else
8619 HAL_HRTIM_Fault5Callback(hhrtim);
8620 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8621 }
8622 }
8623
8624 /* System fault event */
8625 if ((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
8626 {
8627 if ((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET)
8628 {
8629 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
8630
8631 /* Invoke System fault event callback */
8632 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8633 hhrtim->SystemFaultCallback(hhrtim);
8634 #else
8635 HAL_HRTIM_SystemFaultCallback(hhrtim);
8636 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8637 }
8638 }
8639 }
8640
8641 /**
8642 * @brief Master timer interrupts service routine
8643 * @param hhrtim pointer to HAL HRTIM handle
8644 * @retval None
8645 */
HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)8646 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim)
8647 {
8648 uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
8649 uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
8650 uint32_t misrflags = READ_REG(hhrtim->Instance->sMasterRegs.MISR);
8651 uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER);
8652
8653 /* Burst mode period event */
8654 if ((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET)
8655 {
8656 if ((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET)
8657 {
8658 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
8659
8660 /* Invoke Burst mode period event callback */
8661 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8662 hhrtim->BurstModePeriodCallback(hhrtim);
8663 #else
8664 HAL_HRTIM_BurstModePeriodCallback(hhrtim);
8665 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8666 }
8667 }
8668
8669 /* Master timer compare 1 event */
8670 if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
8671 {
8672 if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET)
8673 {
8674 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
8675
8676 /* Invoke compare 1 event callback */
8677 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8678 hhrtim->Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8679 #else
8680 HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8681 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8682 }
8683 }
8684
8685 /* Master timer compare 2 event */
8686 if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
8687 {
8688 if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET)
8689 {
8690 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
8691
8692 /* Invoke compare 2 event callback */
8693 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8694 hhrtim->Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8695 #else
8696 HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8697 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8698 }
8699 }
8700
8701 /* Master timer compare 3 event */
8702 if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
8703 {
8704 if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET)
8705 {
8706 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
8707
8708 /* Invoke compare 3 event callback */
8709 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8710 hhrtim->Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8711 #else
8712 HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8713 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8714 }
8715 }
8716
8717 /* Master timer compare 4 event */
8718 if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
8719 {
8720 if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET)
8721 {
8722 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
8723
8724 /* Invoke compare 4 event callback */
8725 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8726 hhrtim->Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8727 #else
8728 HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8729 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8730 }
8731 }
8732
8733 /* Master timer repetition event */
8734 if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
8735 {
8736 if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET)
8737 {
8738 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
8739
8740 /* Invoke repetition event callback */
8741 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8742 hhrtim->RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8743 #else
8744 HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8745 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8746 }
8747 }
8748
8749 /* Synchronization input event */
8750 if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
8751 {
8752 if ((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET)
8753 {
8754 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
8755
8756 /* Invoke synchronization event callback */
8757 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8758 hhrtim->SynchronizationEventCallback(hhrtim);
8759 #else
8760 HAL_HRTIM_SynchronizationEventCallback(hhrtim);
8761 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8762 }
8763 }
8764
8765 /* Master timer registers update event */
8766 if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
8767 {
8768 if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET)
8769 {
8770 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
8771
8772 /* Invoke registers update event callback */
8773 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8774 hhrtim->RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8775 #else
8776 HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
8777 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8778 }
8779 }
8780 }
8781
8782 /**
8783 * @brief Timer interrupts service routine
8784 * @param hhrtim pointer to HAL HRTIM handle
8785 * @param TimerIdx Timer index
8786 * This parameter can be one of the following values:
8787 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8788 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8789 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8790 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8791 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8792 * @retval None
8793 */
HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8794 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim,
8795 uint32_t TimerIdx)
8796 {
8797 uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR);
8798 uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER);
8799
8800 /* Timer compare 1 event */
8801 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
8802 {
8803 if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET)
8804 {
8805 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
8806
8807 /* Invoke compare 1 event callback */
8808 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8809 hhrtim->Compare1EventCallback(hhrtim, TimerIdx);
8810 #else
8811 HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
8812 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8813 }
8814 }
8815
8816 /* Timer compare 2 event */
8817 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
8818 {
8819 if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET)
8820 {
8821 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
8822
8823 /* Invoke compare 2 event callback */
8824 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8825 hhrtim->Compare2EventCallback(hhrtim, TimerIdx);
8826 #else
8827 HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
8828 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8829 }
8830 }
8831
8832 /* Timer compare 3 event */
8833 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
8834 {
8835 if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET)
8836 {
8837 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
8838
8839 /* Invoke compare 3 event callback */
8840 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8841 hhrtim->Compare3EventCallback(hhrtim, TimerIdx);
8842 #else
8843 HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
8844 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8845 }
8846 }
8847
8848 /* Timer compare 4 event */
8849 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
8850 {
8851 if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET)
8852 {
8853 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
8854
8855 /* Invoke compare 4 event callback */
8856 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8857 hhrtim->Compare4EventCallback(hhrtim, TimerIdx);
8858 #else
8859 HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
8860 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8861 }
8862 }
8863
8864 /* Timer repetition event */
8865 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
8866 {
8867 if ((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET)
8868 {
8869 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
8870
8871 /* Invoke repetition event callback */
8872 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8873 hhrtim->RepetitionEventCallback(hhrtim, TimerIdx);
8874 #else
8875 HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
8876 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8877 }
8878 }
8879
8880 /* Timer registers update event */
8881 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
8882 {
8883 if ((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET)
8884 {
8885 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
8886
8887 /* Invoke registers update event callback */
8888 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8889 hhrtim->RegistersUpdateCallback(hhrtim, TimerIdx);
8890 #else
8891 HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
8892 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8893 }
8894 }
8895
8896 /* Timer capture 1 event */
8897 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
8898 {
8899 if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET)
8900 {
8901 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
8902
8903 /* Invoke capture 1 event callback */
8904 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8905 hhrtim->Capture1EventCallback(hhrtim, TimerIdx);
8906 #else
8907 HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
8908 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8909 }
8910 }
8911
8912 /* Timer capture 2 event */
8913 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
8914 {
8915 if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET)
8916 {
8917 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
8918
8919 /* Invoke capture 2 event callback */
8920 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8921 hhrtim->Capture2EventCallback(hhrtim, TimerIdx);
8922 #else
8923 HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
8924 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8925 }
8926 }
8927
8928 /* Timer output 1 set event */
8929 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
8930 {
8931 if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET)
8932 {
8933 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
8934
8935 /* Invoke output 1 set event callback */
8936 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8937 hhrtim->Output1SetCallback(hhrtim, TimerIdx);
8938 #else
8939 HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
8940 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8941 }
8942 }
8943
8944 /* Timer output 1 reset event */
8945 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
8946 {
8947 if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET)
8948 {
8949 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
8950
8951 /* Invoke output 1 reset event callback */
8952 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8953 hhrtim->Output1ResetCallback(hhrtim, TimerIdx);
8954 #else
8955 HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
8956 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8957 }
8958 }
8959
8960 /* Timer output 2 set event */
8961 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
8962 {
8963 if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET)
8964 {
8965 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
8966
8967 /* Invoke output 2 set event callback */
8968 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8969 hhrtim->Output2SetCallback(hhrtim, TimerIdx);
8970 #else
8971 HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
8972 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8973 }
8974 }
8975
8976 /* Timer output 2 reset event */
8977 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
8978 {
8979 if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET)
8980 {
8981 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
8982
8983 /* Invoke output 2 reset event callback */
8984 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8985 hhrtim->Output2ResetCallback(hhrtim, TimerIdx);
8986 #else
8987 HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
8988 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
8989 }
8990 }
8991
8992 /* Timer reset event */
8993 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
8994 {
8995 if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET)
8996 {
8997 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
8998
8999 /* Invoke timer reset callback */
9000 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9001 hhrtim->CounterResetCallback(hhrtim, TimerIdx);
9002 #else
9003 HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
9004 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9005 }
9006 }
9007
9008 /* Delayed protection event */
9009 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
9010 {
9011 if ((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET)
9012 {
9013 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
9014
9015 /* Invoke delayed protection callback */
9016 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9017 hhrtim->DelayedProtectionCallback(hhrtim, TimerIdx);
9018 #else
9019 HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
9020 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9021 }
9022 }
9023 }
9024
9025 /**
9026 * @brief DMA callback invoked upon master timer related DMA request completion
9027 * @param hdma pointer to DMA handle.
9028 * @retval None
9029 */
HRTIM_DMAMasterCplt(DMA_HandleTypeDef * hdma)9030 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
9031 {
9032 HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
9033
9034 if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET)
9035 {
9036 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9037 hrtim->Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9038 #else
9039 HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9040 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9041 }
9042 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET)
9043 {
9044 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9045 hrtim->Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9046 #else
9047 HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9048 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9049 }
9050 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET)
9051 {
9052 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9053 hrtim->Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9054 #else
9055 HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9056 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9057 }
9058 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET)
9059 {
9060 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9061 hrtim->Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9062 #else
9063 HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9064 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9065 }
9066 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET)
9067 {
9068 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9069 hrtim->SynchronizationEventCallback(hrtim);
9070 #else
9071 HAL_HRTIM_SynchronizationEventCallback(hrtim);
9072 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9073 }
9074 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET)
9075 {
9076 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9077 hrtim->RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9078 #else
9079 HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9080 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9081 }
9082 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET)
9083 {
9084 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9085 hrtim->RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9086 #else
9087 HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
9088 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9089 }
9090 else
9091 {
9092 /* nothing to do */
9093 }
9094 }
9095
9096 /**
9097 * @brief DMA callback invoked upon timer A..E related DMA request completion
9098 * @param hdma pointer to DMA handle.
9099 * @retval None
9100 */
HRTIM_DMATimerxCplt(DMA_HandleTypeDef * hdma)9101 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
9102 {
9103 uint8_t timer_idx;
9104
9105 HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
9106
9107 timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma);
9108
9109 if (!IS_HRTIM_TIMING_UNIT(timer_idx)) {return;}
9110
9111 if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET)
9112 {
9113 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9114 hrtim->Compare1EventCallback(hrtim, timer_idx);
9115 #else
9116 HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
9117 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9118 }
9119 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != (uint32_t)RESET)
9120 {
9121 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9122 hrtim->Compare2EventCallback(hrtim, timer_idx);
9123 #else
9124 HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
9125 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9126 }
9127 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != (uint32_t)RESET)
9128 {
9129 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9130 hrtim->Compare3EventCallback(hrtim, timer_idx);
9131 #else
9132 HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
9133 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9134 }
9135 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != (uint32_t)RESET)
9136 {
9137 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9138 hrtim->Compare4EventCallback(hrtim, timer_idx);
9139 #else
9140 HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
9141 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9142 }
9143 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != (uint32_t)RESET)
9144 {
9145 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9146 hrtim->RegistersUpdateCallback(hrtim, timer_idx);
9147 #else
9148 HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
9149 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9150 }
9151 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != (uint32_t)RESET)
9152 {
9153 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9154 hrtim->Capture1EventCallback(hrtim, timer_idx);
9155 #else
9156 HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
9157 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9158 }
9159 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != (uint32_t)RESET)
9160 {
9161 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9162 hrtim->Capture2EventCallback(hrtim, timer_idx);
9163 #else
9164 HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
9165 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9166 }
9167 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != (uint32_t)RESET)
9168 {
9169 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9170 hrtim->Output1SetCallback(hrtim, timer_idx);
9171 #else
9172 HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
9173 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9174 }
9175 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != (uint32_t)RESET)
9176 {
9177 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9178 hrtim->Output1ResetCallback(hrtim, timer_idx);
9179 #else
9180 HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
9181 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9182 }
9183 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != (uint32_t)RESET)
9184 {
9185 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9186 hrtim->Output2SetCallback(hrtim, timer_idx);
9187 #else
9188 HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
9189 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9190 }
9191 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != (uint32_t)RESET)
9192 {
9193 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9194 hrtim->Output2ResetCallback(hrtim, timer_idx);
9195 #else
9196 HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
9197 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9198 }
9199 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != (uint32_t)RESET)
9200 {
9201 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9202 hrtim->CounterResetCallback(hrtim, timer_idx);
9203 #else
9204 HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
9205 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9206 }
9207 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != (uint32_t)RESET)
9208 {
9209 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9210 hrtim->DelayedProtectionCallback(hrtim, timer_idx);
9211 #else
9212 HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
9213 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9214 }
9215 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != (uint32_t)RESET)
9216 {
9217 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9218 hrtim->RepetitionEventCallback(hrtim, timer_idx);
9219 #else
9220 HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
9221 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9222 }
9223 else
9224 {
9225 /* nothing to do */
9226 }
9227 }
9228
9229 /**
9230 * @brief DMA error callback
9231 * @param hdma pointer to DMA handle.
9232 * @retval None
9233 */
HRTIM_DMAError(DMA_HandleTypeDef * hdma)9234 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
9235 {
9236 HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
9237
9238 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9239 hrtim->ErrorCallback(hrtim);
9240 #else
9241 HAL_HRTIM_ErrorCallback(hrtim);
9242 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9243 }
9244
9245 /**
9246 * @brief DMA callback invoked upon burst DMA transfer completion
9247 * @param hdma pointer to DMA handle.
9248 * @retval None
9249 */
HRTIM_BurstDMACplt(DMA_HandleTypeDef * hdma)9250 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
9251 {
9252 HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
9253
9254 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
9255 hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
9256 #else
9257 HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
9258 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9259 }
9260
9261 /**
9262 * @}
9263 */
9264
9265 /**
9266 * @}
9267 */
9268
9269 #endif /* HRTIM1 */
9270
9271 #endif /* HAL_HRTIM_MODULE_ENABLED */
9272
9273 /**
9274 * @}
9275 */
9276
