1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_flash_ex.c
4 * @author MCD Application Team
5 * @brief Extended FLASH HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the FLASH extension peripheral:
8 * + Extended programming operations functions
9 *
10 @verbatim
11 ==============================================================================
12 ##### Flash Extension features #####
13 ==============================================================================
14
15 [..] Comparing to other previous devices, the FLASH interface for STM32H7xx
16 devices contains the following additional features
17
18 (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
19 capability (RWW)
20 (+) Dual bank memory organization
21 (+) PCROP protection for all banks
22 (+) Global readout protection (RDP)
23 (+) Write protection
24 (+) Secure access only protection
25 (+) Bank / register swapping (when Dual-Bank)
26 (+) Cyclic Redundancy Check (CRC)
27
28 ##### How to use this driver #####
29 ==============================================================================
30 [..] This driver provides functions to configure and program the FLASH memory
31 of all STM32H7xx devices. It includes
32 (#) FLASH Memory Erase functions:
33 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
34 HAL_FLASH_Lock() functions
35 (++) Erase function: Sector erase, bank erase and dual-bank mass erase
36 (++) There are two modes of erase :
37 (+++) Polling Mode using HAL_FLASHEx_Erase()
38 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
39
40 (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to:
41 (++) Set/Reset the write protection per bank
42 (++) Set the Read protection Level
43 (++) Set the BOR level
44 (++) Program the user Option Bytes
45 (++) PCROP protection configuration and control per bank
46 (++) Secure area configuration and control per bank
47 (++) Core Boot address configuration
48 (++) TCM / AXI shared RAM configuration
49 (++) CPU Frequency Boost configuration
50
51 (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1(),
52 HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions
53
54 (#) FLASH CRC computation function: Use HAL_FLASHEx_ComputeCRC() to:
55 (++) Enable CRC feature
56 (++) Program the desired burst size
57 (++) Define the user Flash Area on which the CRC has be computed
58 (++) Perform the CRC computation
59 (++) Disable CRC feature
60
61 (#) Error correction code error functions:
62 (++) Use the HAL_FLASHEx_EnableEccCorrectionInterrupt() and HAL_FLASHEx_DisableEccCorrectionInterrupt()
63 functions to enable and disable the FLASH ECC correction interruption.
64 (++) Use the HAL_FLASHEx_EnableEccDetectionInterrupt() and HAL_FLASHEx_DisableEccDetectionInterrupt()
65 functions to enable and disable the FLASH ECC Detection interruption.
66 (++) Handle ECCD interrupt by calling HAL_FLASHEx_BusFault_IRQHandler()
67 (++) Use HAL_FLASHEx_BusFault_IRQHandler() function called under BusFault_IRQHandler() interrupt subroutine
68 to handle the ECCD interrupt.
69 (++) Use HAL_FLASHEx_GetEccInfo() function to get the flash ECC fail information.
70
71 @endverbatim
72 ******************************************************************************
73 * @attention
74 *
75 * Copyright (c) 2017 STMicroelectronics.
76 * All rights reserved.
77 *
78 * This software is licensed under terms that can be found in the LICENSE file in
79 * the root directory of this software component.
80 * If no LICENSE file comes with this software, it is provided AS-IS.
81 ******************************************************************************
82 */
83
84 /* Includes ------------------------------------------------------------------*/
85 #include "stm32h7xx_hal.h"
86
87 /** @addtogroup STM32H7xx_HAL_Driver
88 * @{
89 */
90
91 /** @defgroup FLASHEx FLASHEx
92 * @brief FLASH HAL Extension module driver
93 * @{
94 */
95
96 #ifdef HAL_FLASH_MODULE_ENABLED
97
98 /* Private typedef -----------------------------------------------------------*/
99 /* Private define ------------------------------------------------------------*/
100 /** @addtogroup FLASHEx_Private_Constants
101 * @{
102 */
103 #define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
104
105 /**
106 * @}
107 */
108 /* Private macro -------------------------------------------------------------*/
109 /* Private variables ---------------------------------------------------------*/
110 /* Private function prototypes -----------------------------------------------*/
111 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
112 * @{
113 */
114 static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks);
115 static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
116 static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank);
117 static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank);
118 static void FLASH_OB_RDPConfig(uint32_t RDPLevel);
119 static uint32_t FLASH_OB_GetRDP(void);
120 static void FLASH_OB_PCROPConfig(uint32_t PCROConfigRDP, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks);
121 static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank);
122 static void FLASH_OB_BOR_LevelConfig(uint32_t Level);
123 static uint32_t FLASH_OB_GetBOR(void);
124 static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
125 static uint32_t FLASH_OB_GetUser(void);
126 static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
127 static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
128 static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks);
129 static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank);
130 static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank);
131 static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank);
132
133 #if defined (DUAL_CORE)
134 static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
135 static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
136 #endif /*DUAL_CORE*/
137
138 #if defined (FLASH_OTPBL_LOCKBL)
139 static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block);
140 static uint32_t FLASH_OB_OTP_GetLock(void);
141 #endif /* FLASH_OTPBL_LOCKBL */
142
143 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
144 static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig);
145 static uint32_t FLASH_OB_SharedRAM_GetConfig(void);
146 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
147
148 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
149 static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost);
150 static uint32_t FLASH_OB_CPUFreq_GetBoost(void);
151 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
152 /**
153 * @}
154 */
155
156 /* Exported functions ---------------------------------------------------------*/
157 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
158 * @{
159 */
160
161 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
162 * @brief Extended IO operation functions
163 *
164 @verbatim
165 ===============================================================================
166 ##### Extended programming operation functions #####
167 ===============================================================================
168 [..]
169 This subsection provides a set of functions allowing to manage the Extension FLASH
170 programming operations Operations.
171
172 @endverbatim
173 * @{
174 */
175 /**
176 * @brief Perform a mass erase or erase the specified FLASH memory sectors
177 * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
178 * contains the configuration information for the erasing.
179 *
180 * @param[out] SectorError pointer to variable that contains the configuration
181 * information on faulty sector in case of error (0xFFFFFFFF means that all
182 * the sectors have been correctly erased)
183 *
184 * @retval HAL Status
185 */
HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef * pEraseInit,uint32_t * SectorError)186 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
187 {
188 HAL_StatusTypeDef status = HAL_OK;
189 uint32_t sector_index;
190
191 /* Check the parameters */
192 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
193 assert_param(IS_FLASH_BANK(pEraseInit->Banks));
194
195 /* Process Locked */
196 __HAL_LOCK(&pFlash);
197
198 /* Reset error code */
199 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
200
201 /* Wait for last operation to be completed on Bank1 */
202 if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
203 {
204 if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
205 {
206 status = HAL_ERROR;
207 }
208 }
209
210 #if defined (DUAL_BANK)
211 /* Wait for last operation to be completed on Bank2 */
212 if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
213 {
214 if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
215 {
216 status = HAL_ERROR;
217 }
218 }
219 #endif /* DUAL_BANK */
220
221 if(status == HAL_OK)
222 {
223 if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
224 {
225 /* Mass erase to be done */
226 FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
227
228 /* Wait for last operation to be completed on Bank 1 */
229 if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
230 {
231 if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
232 {
233 status = HAL_ERROR;
234 }
235 /* if the erase operation is completed, disable the Bank1 BER Bit */
236 FLASH->CR1 &= (~FLASH_CR_BER);
237 }
238 #if defined (DUAL_BANK)
239 /* Wait for last operation to be completed on Bank 2 */
240 if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
241 {
242 if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
243 {
244 status = HAL_ERROR;
245 }
246 /* if the erase operation is completed, disable the Bank2 BER Bit */
247 FLASH->CR2 &= (~FLASH_CR_BER);
248 }
249 #endif /* DUAL_BANK */
250 }
251 else
252 {
253 /*Initialization of SectorError variable*/
254 *SectorError = 0xFFFFFFFFU;
255
256 /* Erase by sector by sector to be done*/
257 for(sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Sector); sector_index++)
258 {
259 FLASH_Erase_Sector(sector_index, pEraseInit->Banks, pEraseInit->VoltageRange);
260
261 if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
262 {
263 /* Wait for last operation to be completed */
264 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
265
266 /* If the erase operation is completed, disable the SER Bit */
267 FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
268 }
269 #if defined (DUAL_BANK)
270 if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
271 {
272 /* Wait for last operation to be completed */
273 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
274
275 /* If the erase operation is completed, disable the SER Bit */
276 FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB));
277 }
278 #endif /* DUAL_BANK */
279
280 if(status != HAL_OK)
281 {
282 /* In case of error, stop erase procedure and return the faulty sector */
283 *SectorError = sector_index;
284 break;
285 }
286 }
287 }
288 }
289
290 /* Process Unlocked */
291 __HAL_UNLOCK(&pFlash);
292
293 return status;
294 }
295
296 /**
297 * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
298 * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
299 * contains the configuration information for the erasing.
300 *
301 * @retval HAL Status
302 */
HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef * pEraseInit)303 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
304 {
305 HAL_StatusTypeDef status = HAL_OK;
306
307 /* Check the parameters */
308 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
309 assert_param(IS_FLASH_BANK(pEraseInit->Banks));
310
311 /* Process Locked */
312 __HAL_LOCK(&pFlash);
313
314 /* Reset error code */
315 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
316
317 /* Wait for last operation to be completed on Bank 1 */
318 if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
319 {
320 if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
321 {
322 status = HAL_ERROR;
323 }
324 }
325
326 #if defined (DUAL_BANK)
327 /* Wait for last operation to be completed on Bank 2 */
328 if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
329 {
330 if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
331 {
332 status = HAL_ERROR;
333 }
334 }
335 #endif /* DUAL_BANK */
336
337 if (status != HAL_OK)
338 {
339 /* Process Unlocked */
340 __HAL_UNLOCK(&pFlash);
341 }
342 else
343 {
344 if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1)
345 {
346 /* Enable End of Operation and Error interrupts for Bank 1 */
347 #if defined (FLASH_CR_OPERRIE)
348 __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
349 FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1);
350 #else
351 __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \
352 FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1);
353 #endif /* FLASH_CR_OPERRIE */
354 }
355 #if defined (DUAL_BANK)
356 if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2)
357 {
358 /* Enable End of Operation and Error interrupts for Bank 2 */
359 #if defined (FLASH_CR_OPERRIE)
360 __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
361 FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2);
362 #else
363 __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \
364 FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2);
365 #endif /* FLASH_CR_OPERRIE */
366 }
367 #endif /* DUAL_BANK */
368
369 if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
370 {
371 /*Mass erase to be done*/
372 if(pEraseInit->Banks == FLASH_BANK_1)
373 {
374 pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1;
375 }
376 #if defined (DUAL_BANK)
377 else if(pEraseInit->Banks == FLASH_BANK_2)
378 {
379 pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2;
380 }
381 #endif /* DUAL_BANK */
382 else
383 {
384 pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE;
385 }
386
387 FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks);
388 }
389 else
390 {
391 /* Erase by sector to be done */
392 #if defined (DUAL_BANK)
393 if(pEraseInit->Banks == FLASH_BANK_1)
394 {
395 pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
396 }
397 else
398 {
399 pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2;
400 }
401 #else
402 pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1;
403 #endif /* DUAL_BANK */
404
405 pFlash.NbSectorsToErase = pEraseInit->NbSectors;
406 pFlash.Sector = pEraseInit->Sector;
407 pFlash.VoltageForErase = pEraseInit->VoltageRange;
408
409 /* Erase first sector and wait for IT */
410 FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks, pEraseInit->VoltageRange);
411 }
412 }
413
414 return status;
415 }
416
417 /**
418 * @brief Program option bytes
419 * @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that
420 * contains the configuration information for the programming.
421 *
422 * @retval HAL Status
423 */
HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef * pOBInit)424 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
425 {
426 HAL_StatusTypeDef status;
427
428 /* Check the parameters */
429 assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
430
431 /* Process Locked */
432 __HAL_LOCK(&pFlash);
433
434 /* Reset Error Code */
435 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
436
437 /* Wait for last operation to be completed */
438 if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK)
439 {
440 status = HAL_ERROR;
441 }
442 #if defined (DUAL_BANK)
443 else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK)
444 {
445 status = HAL_ERROR;
446 }
447 #endif /* DUAL_BANK */
448 else
449 {
450 status = HAL_OK;
451 }
452
453 if(status == HAL_OK)
454 {
455 /*Write protection configuration*/
456 if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
457 {
458 assert_param(IS_WRPSTATE(pOBInit->WRPState));
459
460 if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
461 {
462 /*Enable of Write protection on the selected Sector*/
463 FLASH_OB_EnableWRP(pOBInit->WRPSector,pOBInit->Banks);
464 }
465 else
466 {
467 /*Disable of Write protection on the selected Sector*/
468 FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
469 }
470 }
471
472 /* Read protection configuration */
473 if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
474 {
475 /* Configure the Read protection level */
476 FLASH_OB_RDPConfig(pOBInit->RDPLevel);
477 }
478
479 /* User Configuration */
480 if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
481 {
482 /* Configure the user option bytes */
483 FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
484 }
485
486 /* PCROP Configuration */
487 if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)
488 {
489 assert_param(IS_FLASH_BANK(pOBInit->Banks));
490
491 /*Configure the Proprietary code readout protection */
492 FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr, pOBInit->Banks);
493 }
494
495 /* BOR Level configuration */
496 if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
497 {
498 FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
499 }
500
501 #if defined(DUAL_CORE)
502 /* CM7 Boot Address configuration */
503 if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD)
504 {
505 FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
506 }
507
508 /* CM4 Boot Address configuration */
509 if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD)
510 {
511 FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr1);
512 }
513 #else /* Single Core*/
514 /* Boot Address configuration */
515 if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD)
516 {
517 FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
518 }
519 #endif /*DUAL_CORE*/
520
521 /* Secure area configuration */
522 if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA)
523 {
524 FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks);
525 }
526
527 #if defined(FLASH_OTPBL_LOCKBL)
528 /* OTP Block Lock configuration */
529 if((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) == OPTIONBYTE_OTP_LOCK)
530 {
531 FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock);
532 }
533 #endif /* FLASH_OTPBL_LOCKBL */
534
535 #if defined(FLASH_OPTSR2_TCM_AXI_SHARED)
536 /* TCM / AXI Shared RAM configuration */
537 if((pOBInit->OptionType & OPTIONBYTE_SHARED_RAM) == OPTIONBYTE_SHARED_RAM)
538 {
539 FLASH_OB_SharedRAM_Config(pOBInit->SharedRamConfig);
540 }
541 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
542
543 #if defined(FLASH_OPTSR2_CPUFREQ_BOOST)
544 /* CPU Frequency Boost configuration */
545 if((pOBInit->OptionType & OPTIONBYTE_FREQ_BOOST) == OPTIONBYTE_FREQ_BOOST)
546 {
547 FLASH_OB_CPUFreq_BoostConfig(pOBInit->FreqBoostState);
548 }
549 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
550 }
551
552 /* Process Unlocked */
553 __HAL_UNLOCK(&pFlash);
554
555 return status;
556 }
557
558 /**
559 * @brief Get the Option byte configuration
560 * @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that
561 * contains the configuration information for the programming.
562 * @note The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2,
563 * as this parameter is use to get the given Bank WRP, PCROP and secured area configuration.
564 *
565 * @retval None
566 */
HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef * pOBInit)567 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
568 {
569 pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_RDP | OPTIONBYTE_BOR);
570
571 /* Get Read protection level */
572 pOBInit->RDPLevel = FLASH_OB_GetRDP();
573
574 /* Get the user option bytes */
575 pOBInit->USERConfig = FLASH_OB_GetUser();
576
577 /*Get BOR Level*/
578 pOBInit->BORLevel = FLASH_OB_GetBOR();
579
580 #if defined (DUAL_BANK)
581 if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2))
582 #else
583 if (pOBInit->Banks == FLASH_BANK_1)
584 #endif /* DUAL_BANK */
585 {
586 pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA);
587
588 /* Get write protection on the selected area */
589 FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector), pOBInit->Banks);
590
591 /* Get the Proprietary code readout protection */
592 FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr), pOBInit->Banks);
593
594 /*Get Bank Secure area*/
595 FLASH_OB_GetSecureArea(&(pOBInit->SecureAreaConfig), &(pOBInit->SecureAreaStartAddr), &(pOBInit->SecureAreaEndAddr), pOBInit->Banks);
596 }
597
598 /*Get Boot Address*/
599 FLASH_OB_GetBootAdd(&(pOBInit->BootAddr0), &(pOBInit->BootAddr1));
600 #if defined(DUAL_CORE)
601 pOBInit->OptionType |= OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD;
602
603 /*Get CM4 Boot Address*/
604 FLASH_OB_GetCM4BootAdd(&(pOBInit->CM4BootAddr0), &(pOBInit->CM4BootAddr1));
605 #else
606 pOBInit->OptionType |= OPTIONBYTE_BOOTADD;
607 #endif /*DUAL_CORE*/
608
609 #if defined (FLASH_OTPBL_LOCKBL)
610 pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK;
611
612 /* Get OTP Block Lock */
613 pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock();
614 #endif /* FLASH_OTPBL_LOCKBL */
615
616 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
617 pOBInit->OptionType |= OPTIONBYTE_SHARED_RAM;
618
619 /* Get TCM / AXI Shared RAM */
620 pOBInit->SharedRamConfig = FLASH_OB_SharedRAM_GetConfig();
621 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
622
623 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
624 pOBInit->OptionType |= OPTIONBYTE_FREQ_BOOST;
625
626 /* Get CPU Frequency Boost */
627 pOBInit->FreqBoostState = FLASH_OB_CPUFreq_GetBoost();
628 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
629 }
630
631 /**
632 * @brief Unlock the FLASH Bank1 control registers access
633 * @retval HAL Status
634 */
HAL_FLASHEx_Unlock_Bank1(void)635 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void)
636 {
637 if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
638 {
639 /* Authorize the FLASH Bank1 Registers access */
640 WRITE_REG(FLASH->KEYR1, FLASH_KEY1);
641 WRITE_REG(FLASH->KEYR1, FLASH_KEY2);
642
643 /* Verify Flash Bank1 is unlocked */
644 if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U)
645 {
646 return HAL_ERROR;
647 }
648 }
649
650 return HAL_OK;
651 }
652
653 /**
654 * @brief Locks the FLASH Bank1 control registers access
655 * @retval HAL Status
656 */
HAL_FLASHEx_Lock_Bank1(void)657 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void)
658 {
659 /* Set the LOCK Bit to lock the FLASH Bank1 Registers access */
660 SET_BIT(FLASH->CR1, FLASH_CR_LOCK);
661 return HAL_OK;
662 }
663
664 #if defined (DUAL_BANK)
665 /**
666 * @brief Unlock the FLASH Bank2 control registers access
667 * @retval HAL Status
668 */
HAL_FLASHEx_Unlock_Bank2(void)669 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void)
670 {
671 if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
672 {
673 /* Authorize the FLASH Bank2 Registers access */
674 WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
675 WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
676
677 /* Verify Flash Bank1 is unlocked */
678 if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U)
679 {
680 return HAL_ERROR;
681 }
682 }
683
684 return HAL_OK;
685 }
686
687 /**
688 * @brief Locks the FLASH Bank2 control registers access
689 * @retval HAL Status
690 */
HAL_FLASHEx_Lock_Bank2(void)691 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void)
692 {
693 /* Set the LOCK Bit to lock the FLASH Bank2 Registers access */
694 SET_BIT(FLASH->CR2, FLASH_CR_LOCK);
695 return HAL_OK;
696 }
697 #endif /* DUAL_BANK */
698
699 /*
700 * @brief Perform a CRC computation on the specified FLASH memory area
701 * @param pCRCInit pointer to an FLASH_CRCInitTypeDef structure that
702 * contains the configuration information for the CRC computation.
703 * @note CRC computation uses CRC-32 (Ethernet) polynomial 0x4C11DB7
704 * @note The application should avoid running a CRC on PCROP or secure-only
705 * user Flash memory area since it may alter the expected CRC value.
706 * A special error flag (CRC read error: CRCRDERR) can be used to
707 * detect such a case.
708 * @retval HAL Status
709 */
HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef * pCRCInit,uint32_t * CRC_Result)710 HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result)
711 {
712 HAL_StatusTypeDef status;
713 uint32_t sector_index;
714
715 /* Check the parameters */
716 assert_param(IS_FLASH_BANK_EXCLUSIVE(pCRCInit->Bank));
717 assert_param(IS_FLASH_TYPECRC(pCRCInit->TypeCRC));
718
719 /* Wait for OB change operation to be completed */
720 status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
721
722 if (status == HAL_OK)
723 {
724 if (pCRCInit->Bank == FLASH_BANK_1)
725 {
726 /* Enable CRC feature */
727 FLASH->CR1 |= FLASH_CR_CRC_EN;
728
729 /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */
730 FLASH->CCR1 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR);
731
732 /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */
733 FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC;
734
735 if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS)
736 {
737 /* Clear sectors list */
738 FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_SECT;
739
740 /* Select CRC sectors */
741 for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++)
742 {
743 FLASH_CRC_AddSector(sector_index, FLASH_BANK_1);
744 }
745 }
746 else if (pCRCInit->TypeCRC == FLASH_CRC_BANK)
747 {
748 /* Enable Bank 1 CRC select bit */
749 FLASH->CRCCR1 |= FLASH_CRCCR_ALL_BANK;
750 }
751 else
752 {
753 /* Select CRC start and end addresses */
754 FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_1);
755 }
756
757 /* Start the CRC calculation */
758 FLASH->CRCCR1 |= FLASH_CRCCR_START_CRC;
759
760 /* Wait on CRC busy flag */
761 status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1);
762
763 /* Return CRC result */
764 (*CRC_Result) = FLASH->CRCDATA;
765
766 /* Disable CRC feature */
767 FLASH->CR1 &= (~FLASH_CR_CRC_EN);
768
769 /* Clear CRC flags */
770 __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1);
771 }
772 #if defined (DUAL_BANK)
773 else
774 {
775 /* Enable CRC feature */
776 FLASH->CR2 |= FLASH_CR_CRC_EN;
777
778 /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */
779 FLASH->CCR2 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR);
780
781 /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */
782 FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC;
783
784 if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS)
785 {
786 /* Clear sectors list */
787 FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_SECT;
788
789 /* Add CRC sectors */
790 for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++)
791 {
792 FLASH_CRC_AddSector(sector_index, FLASH_BANK_2);
793 }
794 }
795 else if (pCRCInit->TypeCRC == FLASH_CRC_BANK)
796 {
797 /* Enable Bank 2 CRC select bit */
798 FLASH->CRCCR2 |= FLASH_CRCCR_ALL_BANK;
799 }
800 else
801 {
802 /* Select CRC start and end addresses */
803 FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_2);
804 }
805
806 /* Start the CRC calculation */
807 FLASH->CRCCR2 |= FLASH_CRCCR_START_CRC;
808
809 /* Wait on CRC busy flag */
810 status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2);
811
812 /* Return CRC result */
813 (*CRC_Result) = FLASH->CRCDATA;
814
815 /* Disable CRC feature */
816 FLASH->CR2 &= (~FLASH_CR_CRC_EN);
817
818 /* Clear CRC flags */
819 __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2);
820 }
821 #endif /* DUAL_BANK */
822 }
823
824 return status;
825 }
826
827 /**
828 * @}
829 */
830
831 #if (USE_FLASH_ECC == 1U)
832 /** @defgroup FLASHEx_Exported_Functions_Group2 Extended ECC operation functions
833 * @brief Extended ECC operation functions
834 *
835 @verbatim
836 ===============================================================================
837 ##### Extended ECC operation functions #####
838 ===============================================================================
839 [..]
840 This subsection provides a set of functions allowing to manage the Extended FLASH
841 ECC Operations.
842
843 @endverbatim
844 * @{
845 */
846
847 /**
848 * @brief Enable ECC correction interrupts on FLASH BANK1 and BANK2.
849 * @param None
850 * @retval None
851 */
HAL_FLASHEx_EnableEccCorrectionInterrupt(void)852 void HAL_FLASHEx_EnableEccCorrectionInterrupt(void)
853 {
854 __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK1);
855
856 #if defined (DUAL_BANK)
857 __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK2);
858 #endif /* DUAL_BANK */
859 }
860
861 /**
862 * @brief Disable ECC correction interrupts on FLASH BANK1 and BANK2.
863 * @param None
864 * @retval None
865 */
HAL_FLASHEx_DisableEccCorrectionInterrupt(void)866 void HAL_FLASHEx_DisableEccCorrectionInterrupt(void)
867 {
868 __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK1);
869
870 #if defined (DUAL_BANK)
871 __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK2);
872 #endif /* DUAL_BANK */
873 }
874
875 /**
876 * @brief Enable ECC correction interrupt on FLASH BANK1.
877 * @param None
878 * @retval None
879 */
HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void)880 void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void)
881 {
882 __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK1);
883 }
884
885 /**
886 * @brief Disable ECC correction interrupt on FLASH BANK1.
887 * @param None
888 * @retval None
889 */
HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void)890 void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void)
891 {
892 __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK1);
893 }
894
895 #if defined (DUAL_BANK)
896 /**
897 * @brief Enable ECC correction interrupt on FLASH BANK2.
898 * @param None
899 * @retval None
900 */
HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void)901 void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void)
902 {
903 __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK2);
904 }
905
906 /**
907 * @brief Disable ECC correction interrupt on FLASH BANK2.
908 * @param None
909 * @retval None
910 */
HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void)911 void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void)
912 {
913 __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK2);
914 }
915 #endif /* DUAL_BANK */
916
917 /**
918 * @brief Enable ECC Detection interrupts on FLASH BANK1 and BANK2.
919 * @param None
920 * @retval None
921 */
HAL_FLASHEx_EnableEccDetectionInterrupt(void)922 void HAL_FLASHEx_EnableEccDetectionInterrupt(void)
923 {
924 __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK1);
925
926 #if defined (DUAL_BANK)
927 __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK2);
928 #endif /* DUAL_BANK */
929 }
930
931 /**
932 * @brief Disable ECC Detection interrupts on FLASH BANK1 and BANK2.
933 * @param None
934 * @retval None
935 */
HAL_FLASHEx_DisableEccDetectionInterrupt(void)936 void HAL_FLASHEx_DisableEccDetectionInterrupt(void)
937 {
938 __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK1);
939
940 #if defined (DUAL_BANK)
941 __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK2);
942 #endif /* DUAL_BANK */
943 }
944
945 /**
946 * @brief Enable ECC Detection interrupt on FLASH BANK1.
947 * @param None
948 * @retval None
949 */
HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void)950 void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void)
951 {
952 __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK1);
953 }
954
955 /**
956 * @brief Disable ECC correction interrupt on FLASH BANK1.
957 * @param None
958 * @retval None
959 */
HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void)960 void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void)
961 {
962 __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK1);
963 }
964
965 #if defined (DUAL_BANK)
966 /**
967 * @brief Enable ECC Detection interrupt on FLASH BANK2.
968 * @param None
969 * @retval None
970 */
HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void)971 void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void)
972 {
973 __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK2);
974 }
975
976 /**
977 * @brief Disable ECC Detection interrupt on FLASH BANK2.
978 * @param None
979 * @retval None
980 */
HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void)981 void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void)
982 {
983 __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK2);
984 }
985 #endif /* DUAL_BANK */
986
987 /**
988 * @brief Get the ECC error information.
989 * @param pData Pointer to an FLASH_EccInfoTypeDef structure that contains the
990 * ECC error information.
991 * @note This function should be called before ECC bit is cleared
992 * (in callback function)
993 * @retval None
994 */
HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef * pData)995 void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData)
996 {
997 uint32_t errorflag;
998
999 /* Check FLASH Bank1 ECC single correction and double detection error flags */
1000 errorflag = FLASH->SR1 & (FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1);
1001 if(errorflag != 0U)
1002 {
1003 pData->Area = FLASH_ECC_AREA_USER_BANK1;
1004 pData->Address = ((((FLASH->ECC_FA1 & FLASH_ECC_FA_FAIL_ECC_ADDR))* FLASH_NB_32BITWORD_IN_FLASHWORD * 4) + FLASH_BANK1_BASE);
1005 }
1006 #if defined (DUAL_BANK)
1007 /* Check FLASH Bank2 ECC single correction and double detection error flags */
1008 errorflag = FLASH->SR2 & (FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2);
1009 if(errorflag != 0U)
1010 {
1011 pData->Area = FLASH_ECC_AREA_USER_BANK2;
1012 pData->Address = ((((FLASH->ECC_FA2 & FLASH_ECC_FA_FAIL_ECC_ADDR))* FLASH_NB_32BITWORD_IN_FLASHWORD * 4) + FLASH_BANK2_BASE);
1013 }
1014 #endif /* DUAL_BANK */
1015 }
1016
1017 /**
1018 * @brief Handle Flash ECC Detection interrupt request.
1019 * @retval None
1020 */
HAL_FLASHEx_BusFault_IRQHandler(void)1021 void HAL_FLASHEx_BusFault_IRQHandler(void)
1022 {
1023 /* Check if the ECC double error occurred*/
1024 if ((FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1) != 0)
1025 {
1026 /* FLASH ECC detection user callback */
1027 HAL_FLASHEx_EccDetectionCallback();
1028
1029 /* Clear Bank 1 ECC double detection error flag
1030 note : this step will clear all the information related to the flash ECC detection
1031 */
1032 __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_DBECCERR_BANK1);
1033 }
1034 #if defined (DUAL_BANK)
1035 /* Check if the ECC double error occurred*/
1036 if ((FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2) != 0)
1037 {
1038 /* FLASH ECC detection user callback */
1039 HAL_FLASHEx_EccDetectionCallback();
1040
1041 /* Clear Bank 2 ECC double detection error flag
1042 note : this step will clear all the information related to the flash ECC detection
1043 */
1044 __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_DBECCERR_BANK2);
1045 }
1046 #endif /* DUAL_BANK */
1047 }
1048
1049 /**
1050 * @brief FLASH ECC Correction interrupt callback.
1051 * @retval None
1052 */
HAL_FLASHEx_EccCorrectionCallback(void)1053 __weak void HAL_FLASHEx_EccCorrectionCallback(void)
1054 {
1055 /* NOTE : This function should not be modified, when the callback is needed,
1056 the HAL_FLASHEx_EccCorrectionCallback could be implemented in the user file
1057 */
1058 }
1059
1060 /**
1061 * @brief FLASH ECC Detection interrupt callback.
1062 * @retval None
1063 */
HAL_FLASHEx_EccDetectionCallback(void)1064 __weak void HAL_FLASHEx_EccDetectionCallback(void)
1065 {
1066 /* NOTE : This function should not be modified, when the callback is needed,
1067 the HAL_FLASHEx_EccDetectionCallback could be implemented in the user file
1068 */
1069 }
1070
1071 /**
1072 * @}
1073 */
1074 #endif /* USE_FLASH_ECC */
1075
1076 /**
1077 * @}
1078 */
1079
1080 /* Private functions ---------------------------------------------------------*/
1081
1082 /** @addtogroup FLASHEx_Private_Functions
1083 * @{
1084 */
1085
1086 /**
1087 * @brief Mass erase of FLASH memory
1088 * @param VoltageRange The device program/erase parallelism.
1089 * This parameter can be one of the following values:
1090 * @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
1091 * @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
1092 * @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
1093 * @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
1094 *
1095 * @param Banks Banks to be erased
1096 * This parameter can be one of the following values:
1097 * @arg FLASH_BANK_1: Bank1 to be erased
1098 * @arg FLASH_BANK_2: Bank2 to be erased
1099 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
1100 *
1101 * @retval HAL Status
1102 */
FLASH_MassErase(uint32_t VoltageRange,uint32_t Banks)1103 static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks)
1104 {
1105 /* Check the parameters */
1106 #if defined (FLASH_CR_PSIZE)
1107 assert_param(IS_VOLTAGERANGE(VoltageRange));
1108 #else
1109 UNUSED(VoltageRange);
1110 #endif /* FLASH_CR_PSIZE */
1111 assert_param(IS_FLASH_BANK(Banks));
1112
1113 #if defined (DUAL_BANK)
1114 /* Flash Mass Erase */
1115 if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH)
1116 {
1117 #if defined (FLASH_CR_PSIZE)
1118 /* Reset Program/erase VoltageRange for Bank1 and Bank2 */
1119 FLASH->CR1 &= (~FLASH_CR_PSIZE);
1120 FLASH->CR2 &= (~FLASH_CR_PSIZE);
1121
1122 /* Set voltage range */
1123 FLASH->CR1 |= VoltageRange;
1124 FLASH->CR2 |= VoltageRange;
1125 #endif /* FLASH_CR_PSIZE */
1126
1127 /* Set Mass Erase Bit */
1128 FLASH->OPTCR |= FLASH_OPTCR_MER;
1129 }
1130 else
1131 #endif /* DUAL_BANK */
1132 {
1133 /* Proceed to erase Flash Bank */
1134 if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
1135 {
1136 #if defined (FLASH_CR_PSIZE)
1137 /* Set Program/erase VoltageRange for Bank1 */
1138 FLASH->CR1 &= (~FLASH_CR_PSIZE);
1139 FLASH->CR1 |= VoltageRange;
1140 #endif /* FLASH_CR_PSIZE */
1141
1142 /* Erase Bank1 */
1143 FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START);
1144 }
1145
1146 #if defined (DUAL_BANK)
1147 if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
1148 {
1149 #if defined (FLASH_CR_PSIZE)
1150 /* Set Program/erase VoltageRange for Bank2 */
1151 FLASH->CR2 &= (~FLASH_CR_PSIZE);
1152 FLASH->CR2 |= VoltageRange;
1153 #endif /* FLASH_CR_PSIZE */
1154
1155 /* Erase Bank2 */
1156 FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START);
1157 }
1158 #endif /* DUAL_BANK */
1159 }
1160 }
1161
1162 /**
1163 * @brief Erase the specified FLASH memory sector
1164 * @param Sector FLASH sector to erase
1165 * This parameter can be a value of @ref FLASH_Sectors
1166 * @param Banks Banks to be erased
1167 * This parameter can be one of the following values:
1168 * @arg FLASH_BANK_1: Bank1 to be erased
1169 * @arg FLASH_BANK_2: Bank2 to be erased
1170 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
1171 * @param VoltageRange The device program/erase parallelism.
1172 * This parameter can be one of the following values:
1173 * @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits
1174 * @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits
1175 * @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits
1176 * @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits
1177 *
1178 * @retval None
1179 */
FLASH_Erase_Sector(uint32_t Sector,uint32_t Banks,uint32_t VoltageRange)1180 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
1181 {
1182 assert_param(IS_FLASH_SECTOR(Sector));
1183 assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
1184 #if defined (FLASH_CR_PSIZE)
1185 assert_param(IS_VOLTAGERANGE(VoltageRange));
1186 #else
1187 UNUSED(VoltageRange);
1188 #endif /* FLASH_CR_PSIZE */
1189
1190 if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
1191 {
1192 #if defined (FLASH_CR_PSIZE)
1193 /* Reset Program/erase VoltageRange and Sector Number for Bank1 */
1194 FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
1195
1196 FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
1197 #else
1198 /* Reset Sector Number for Bank1 */
1199 FLASH->CR1 &= ~(FLASH_CR_SNB);
1200
1201 FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
1202 #endif /* FLASH_CR_PSIZE */
1203 }
1204
1205 #if defined (DUAL_BANK)
1206 if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
1207 {
1208 #if defined (FLASH_CR_PSIZE)
1209 /* Reset Program/erase VoltageRange and Sector Number for Bank2 */
1210 FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB);
1211
1212 FLASH->CR2 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
1213 #else
1214 /* Reset Sector Number for Bank2 */
1215 FLASH->CR2 &= ~(FLASH_CR_SNB);
1216
1217 FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START);
1218 #endif /* FLASH_CR_PSIZE */
1219 }
1220 #endif /* DUAL_BANK */
1221 }
1222
1223 /**
1224 * @brief Enable the write protection of the desired bank1 or bank 2 sectors
1225 * @param WRPSector specifies the sector(s) to be write protected.
1226 * This parameter can be one of the following values:
1227 * @arg WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_ALL
1228 *
1229 * @param Banks the specific bank to apply WRP sectors
1230 * This parameter can be one of the following values:
1231 * @arg FLASH_BANK_1: enable WRP on specified bank1 sectors
1232 * @arg FLASH_BANK_2: enable WRP on specified bank2 sectors
1233 * @arg FLASH_BANK_BOTH: enable WRP on both bank1 and bank2 specified sectors
1234 *
1235 * @retval HAL FLASH State
1236 */
FLASH_OB_EnableWRP(uint32_t WRPSector,uint32_t Banks)1237 static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
1238 {
1239 /* Check the parameters */
1240 assert_param(IS_OB_WRP_SECTOR(WRPSector));
1241 assert_param(IS_FLASH_BANK(Banks));
1242
1243 if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
1244 {
1245 /* Enable Write Protection for bank 1 */
1246 FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN));
1247 }
1248
1249 #if defined (DUAL_BANK)
1250 if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
1251 {
1252 /* Enable Write Protection for bank 2 */
1253 FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN));
1254 }
1255 #endif /* DUAL_BANK */
1256 }
1257
1258 /**
1259 * @brief Disable the write protection of the desired bank1 or bank 2 sectors
1260 * @param WRPSector specifies the sector(s) to disable write protection.
1261 * This parameter can be one of the following values:
1262 * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL
1263 *
1264 * @param Banks the specific bank to apply WRP sectors
1265 * This parameter can be one of the following values:
1266 * @arg FLASH_BANK_1: disable WRP on specified bank1 sectors
1267 * @arg FLASH_BANK_2: disable WRP on specified bank2 sectors
1268 * @arg FLASH_BANK_BOTH: disable WRP on both bank1 and bank2 specified sectors
1269 *
1270 * @retval HAL FLASH State
1271 */
FLASH_OB_DisableWRP(uint32_t WRPSector,uint32_t Banks)1272 static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
1273 {
1274 /* Check the parameters */
1275 assert_param(IS_OB_WRP_SECTOR(WRPSector));
1276 assert_param(IS_FLASH_BANK(Banks));
1277
1278 if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
1279 {
1280 /* Disable Write Protection for bank 1 */
1281 FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN);
1282 }
1283
1284 #if defined (DUAL_BANK)
1285 if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
1286 {
1287 /* Disable Write Protection for bank 2 */
1288 FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN);
1289 }
1290 #endif /* DUAL_BANK */
1291 }
1292
1293 /**
1294 * @brief Get the write protection of the given bank 1 or bank 2 sectors
1295 * @param WRPState gives the write protection state on the given bank.
1296 * This parameter can be one of the following values:
1297 * @arg WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE
1298
1299 * @param WRPSector gives the write protected sector(s) on the given bank .
1300 * This parameter can be one of the following values:
1301 * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL
1302 *
1303 * @param Bank the specific bank to apply WRP sectors
1304 * This parameter can be exclusively one of the following values:
1305 * @arg FLASH_BANK_1: Get bank1 WRP sectors
1306 * @arg FLASH_BANK_2: Get bank2 WRP sectors
1307 * @arg FLASH_BANK_BOTH: note allowed in this functions
1308 *
1309 * @retval HAL FLASH State
1310 */
FLASH_OB_GetWRP(uint32_t * WRPState,uint32_t * WRPSector,uint32_t Bank)1311 static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank)
1312 {
1313 uint32_t regvalue = 0U;
1314
1315 if(Bank == FLASH_BANK_1)
1316 {
1317 regvalue = FLASH->WPSN_CUR1;
1318 }
1319
1320 #if defined (DUAL_BANK)
1321 if(Bank == FLASH_BANK_2)
1322 {
1323 regvalue = FLASH->WPSN_CUR2;
1324 }
1325 #endif /* DUAL_BANK */
1326
1327 (*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN;
1328
1329 if(*WRPSector == 0U)
1330 {
1331 (*WRPState) = OB_WRPSTATE_DISABLE;
1332 }
1333 else
1334 {
1335 (*WRPState) = OB_WRPSTATE_ENABLE;
1336 }
1337 }
1338
1339 /**
1340 * @brief Set the read protection level.
1341 *
1342 * @note To configure the RDP level, the option lock bit OPTLOCK must be
1343 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
1344 * @note To validate the RDP level, the option bytes must be reloaded
1345 * through the call of the HAL_FLASH_OB_Launch() function.
1346 * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
1347 * to go back to level 1 or 0 !!!
1348 *
1349 * @param RDPLevel specifies the read protection level.
1350 * This parameter can be one of the following values:
1351 * @arg OB_RDP_LEVEL_0: No protection
1352 * @arg OB_RDP_LEVEL_1: Read protection of the memory
1353 * @arg OB_RDP_LEVEL_2: Full chip protection
1354 *
1355 * @retval HAL status
1356 */
FLASH_OB_RDPConfig(uint32_t RDPLevel)1357 static void FLASH_OB_RDPConfig(uint32_t RDPLevel)
1358 {
1359 /* Check the parameters */
1360 assert_param(IS_OB_RDP_LEVEL(RDPLevel));
1361
1362 /* Configure the RDP level in the option bytes register */
1363 MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_RDP, RDPLevel);
1364 }
1365
1366 /**
1367 * @brief Get the read protection level.
1368 * @retval RDPLevel specifies the read protection level.
1369 * This return value can be one of the following values:
1370 * @arg OB_RDP_LEVEL_0: No protection
1371 * @arg OB_RDP_LEVEL_1: Read protection of the memory
1372 * @arg OB_RDP_LEVEL_2: Full chip protection
1373 */
FLASH_OB_GetRDP(void)1374 static uint32_t FLASH_OB_GetRDP(void)
1375 {
1376 uint32_t rdp_level = READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_RDP);
1377
1378 if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
1379 {
1380 return (OB_RDP_LEVEL_1);
1381 }
1382 else
1383 {
1384 return rdp_level;
1385 }
1386 }
1387
1388 #if defined(DUAL_CORE)
1389 /**
1390 * @brief Program the FLASH User Option Byte.
1391 *
1392 * @note To configure the user option bytes, the option lock bit OPTLOCK must
1393 * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
1394 *
1395 * @note To validate the user option bytes, the option bytes must be reloaded
1396 * through the call of the HAL_FLASH_OB_Launch() function.
1397 *
1398 * @param UserType The FLASH User Option Bytes to be modified :
1399 * a combination of @ref FLASHEx_OB_USER_Type
1400 *
1401 * @param UserConfig The FLASH User Option Bytes values:
1402 * IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
1403 * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
1404 * SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24),
1405 * nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
1406 *
1407 * @retval HAL status
1408 */
1409 #else
1410 /**
1411 * @brief Program the FLASH User Option Byte.
1412 *
1413 * @note To configure the user option bytes, the option lock bit OPTLOCK must
1414 * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
1415 *
1416 * @note To validate the user option bytes, the option bytes must be reloaded
1417 * through the call of the HAL_FLASH_OB_Launch() function.
1418 *
1419 * @param UserType The FLASH User Option Bytes to be modified :
1420 * a combination of @arg FLASHEx_OB_USER_Type
1421 *
1422 * @param UserConfig The FLASH User Option Bytes values:
1423 * IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
1424 * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
1425 * SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
1426 *
1427 * @retval HAL status
1428 */
1429 #endif /*DUAL_CORE*/
FLASH_OB_UserConfig(uint32_t UserType,uint32_t UserConfig)1430 static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
1431 {
1432 uint32_t optr_reg_val = 0;
1433 uint32_t optr_reg_mask = 0;
1434
1435 /* Check the parameters */
1436 assert_param(IS_OB_USER_TYPE(UserType));
1437
1438 if((UserType & OB_USER_IWDG1_SW) != 0U)
1439 {
1440 /* IWDG_HW option byte should be modified */
1441 assert_param(IS_OB_IWDG1_SOURCE(UserConfig & FLASH_OPTSR_IWDG1_SW));
1442
1443 /* Set value and mask for IWDG_HW option byte */
1444 optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG1_SW);
1445 optr_reg_mask |= FLASH_OPTSR_IWDG1_SW;
1446 }
1447 #if defined(DUAL_CORE)
1448 if((UserType & OB_USER_IWDG2_SW) != 0U)
1449 {
1450 /* IWDG2_SW option byte should be modified */
1451 assert_param(IS_OB_IWDG2_SOURCE(UserConfig & FLASH_OPTSR_IWDG2_SW));
1452
1453 /* Set value and mask for IWDG2_SW option byte */
1454 optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG2_SW);
1455 optr_reg_mask |= FLASH_OPTSR_IWDG2_SW;
1456 }
1457 #endif /*DUAL_CORE*/
1458 if((UserType & OB_USER_NRST_STOP_D1) != 0U)
1459 {
1460 /* NRST_STOP option byte should be modified */
1461 assert_param(IS_OB_STOP_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D1));
1462
1463 /* Set value and mask for NRST_STOP option byte */
1464 optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D1);
1465 optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D1;
1466 }
1467
1468 if((UserType & OB_USER_NRST_STDBY_D1) != 0U)
1469 {
1470 /* NRST_STDBY option byte should be modified */
1471 assert_param(IS_OB_STDBY_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D1));
1472
1473 /* Set value and mask for NRST_STDBY option byte */
1474 optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D1);
1475 optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D1;
1476 }
1477
1478 if((UserType & OB_USER_IWDG_STOP) != 0U)
1479 {
1480 /* IWDG_STOP option byte should be modified */
1481 assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTSR_FZ_IWDG_STOP));
1482
1483 /* Set value and mask for IWDG_STOP option byte */
1484 optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_STOP);
1485 optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_STOP;
1486 }
1487
1488 if((UserType & OB_USER_IWDG_STDBY) != 0U)
1489 {
1490 /* IWDG_STDBY option byte should be modified */
1491 assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY));
1492
1493 /* Set value and mask for IWDG_STDBY option byte */
1494 optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY);
1495 optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_SDBY;
1496 }
1497
1498 if((UserType & OB_USER_ST_RAM_SIZE) != 0U)
1499 {
1500 /* ST_RAM_SIZE option byte should be modified */
1501 assert_param(IS_OB_USER_ST_RAM_SIZE(UserConfig & FLASH_OPTSR_ST_RAM_SIZE));
1502
1503 /* Set value and mask for ST_RAM_SIZE option byte */
1504 optr_reg_val |= (UserConfig & FLASH_OPTSR_ST_RAM_SIZE);
1505 optr_reg_mask |= FLASH_OPTSR_ST_RAM_SIZE;
1506 }
1507
1508 if((UserType & OB_USER_SECURITY) != 0U)
1509 {
1510 /* SECURITY option byte should be modified */
1511 assert_param(IS_OB_USER_SECURITY(UserConfig & FLASH_OPTSR_SECURITY));
1512
1513 /* Set value and mask for SECURITY option byte */
1514 optr_reg_val |= (UserConfig & FLASH_OPTSR_SECURITY);
1515 optr_reg_mask |= FLASH_OPTSR_SECURITY;
1516 }
1517
1518 #if defined(DUAL_CORE)
1519 if((UserType & OB_USER_BCM4) != 0U)
1520 {
1521 /* BCM4 option byte should be modified */
1522 assert_param(IS_OB_USER_BCM4(UserConfig & FLASH_OPTSR_BCM4));
1523
1524 /* Set value and mask for BCM4 option byte */
1525 optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM4);
1526 optr_reg_mask |= FLASH_OPTSR_BCM4;
1527 }
1528
1529 if((UserType & OB_USER_BCM7) != 0U)
1530 {
1531 /* BCM7 option byte should be modified */
1532 assert_param(IS_OB_USER_BCM7(UserConfig & FLASH_OPTSR_BCM7));
1533
1534 /* Set value and mask for BCM7 option byte */
1535 optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7);
1536 optr_reg_mask |= FLASH_OPTSR_BCM7;
1537 }
1538 #endif /* DUAL_CORE */
1539
1540 #if defined (FLASH_OPTSR_NRST_STOP_D2)
1541 if((UserType & OB_USER_NRST_STOP_D2) != 0U)
1542 {
1543 /* NRST_STOP option byte should be modified */
1544 assert_param(IS_OB_STOP_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D2));
1545
1546 /* Set value and mask for NRST_STOP option byte */
1547 optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D2);
1548 optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D2;
1549 }
1550
1551 if((UserType & OB_USER_NRST_STDBY_D2) != 0U)
1552 {
1553 /* NRST_STDBY option byte should be modified */
1554 assert_param(IS_OB_STDBY_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D2));
1555
1556 /* Set value and mask for NRST_STDBY option byte */
1557 optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2);
1558 optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2;
1559 }
1560 #endif /* FLASH_OPTSR_NRST_STOP_D2 */
1561
1562 #if defined (DUAL_BANK)
1563 if((UserType & OB_USER_SWAP_BANK) != 0U)
1564 {
1565 /* SWAP_BANK_OPT option byte should be modified */
1566 assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTSR_SWAP_BANK_OPT));
1567
1568 /* Set value and mask for SWAP_BANK_OPT option byte */
1569 optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT);
1570 optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT;
1571 }
1572 #endif /* DUAL_BANK */
1573
1574 if((UserType & OB_USER_IOHSLV) != 0U)
1575 {
1576 /* IOHSLV_OPT option byte should be modified */
1577 assert_param(IS_OB_USER_IOHSLV(UserConfig & FLASH_OPTSR_IO_HSLV));
1578
1579 /* Set value and mask for IOHSLV_OPT option byte */
1580 optr_reg_val |= (UserConfig & FLASH_OPTSR_IO_HSLV);
1581 optr_reg_mask |= FLASH_OPTSR_IO_HSLV;
1582 }
1583
1584 #if defined (FLASH_OPTSR_VDDMMC_HSLV)
1585 if((UserType & OB_USER_VDDMMC_HSLV) != 0U)
1586 {
1587 /* VDDMMC_HSLV option byte should be modified */
1588 assert_param(IS_OB_USER_VDDMMC_HSLV(UserConfig & FLASH_OPTSR_VDDMMC_HSLV));
1589
1590 /* Set value and mask for VDDMMC_HSLV option byte */
1591 optr_reg_val |= (UserConfig & FLASH_OPTSR_VDDMMC_HSLV);
1592 optr_reg_mask |= FLASH_OPTSR_VDDMMC_HSLV;
1593 }
1594 #endif /* FLASH_OPTSR_VDDMMC_HSLV */
1595
1596 /* Configure the option bytes register */
1597 MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val);
1598 }
1599
1600 #if defined(DUAL_CORE)
1601 /**
1602 * @brief Return the FLASH User Option Byte value.
1603 * @retval The FLASH User Option Bytes values
1604 * IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
1605 * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
1606 * SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24),
1607 * nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
1608 */
1609 #else
1610 /**
1611 * @brief Return the FLASH User Option Byte value.
1612 * @retval The FLASH User Option Bytes values
1613 * IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
1614 * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
1615 * SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
1616 */
1617 #endif /*DUAL_CORE*/
FLASH_OB_GetUser(void)1618 static uint32_t FLASH_OB_GetUser(void)
1619 {
1620 uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR);
1621 userConfig &= (~(FLASH_OPTSR_BOR_LEV | FLASH_OPTSR_RDP));
1622
1623 return userConfig;
1624 }
1625
1626 /**
1627 * @brief Configure the Proprietary code readout protection of the desired addresses
1628 *
1629 * @note To configure the PCROP options, the option lock bit OPTLOCK must be
1630 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
1631 * @note To validate the PCROP options, the option bytes must be reloaded
1632 * through the call of the HAL_FLASH_OB_Launch() function.
1633 *
1634 * @param PCROPConfig specifies if the PCROP area for the given Bank shall be erased or not
1635 * when RDP level decreased from Level 1 to Level 0, or after a bank erase with protection removal
1636 * This parameter must be a value of @arg FLASHEx_OB_PCROP_RDP enumeration
1637 *
1638 * @param PCROPStartAddr specifies the start address of the Proprietary code readout protection
1639 * This parameter can be an address between begin and end of the bank
1640 *
1641 * @param PCROPEndAddr specifies the end address of the Proprietary code readout protection
1642 * This parameter can be an address between PCROPStartAddr and end of the bank
1643 *
1644 * @param Banks the specific bank to apply PCROP protection
1645 * This parameter can be one of the following values:
1646 * @arg FLASH_BANK_1: PCROP on specified bank1 area
1647 * @arg FLASH_BANK_2: PCROP on specified bank2 area
1648 * @arg FLASH_BANK_BOTH: PCROP on specified bank1 and bank2 area (same config will be applied on both banks)
1649 *
1650 * @retval None
1651 */
FLASH_OB_PCROPConfig(uint32_t PCROPConfig,uint32_t PCROPStartAddr,uint32_t PCROPEndAddr,uint32_t Banks)1652 static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks)
1653 {
1654 /* Check the parameters */
1655 assert_param(IS_FLASH_BANK(Banks));
1656 assert_param(IS_OB_PCROP_RDP(PCROPConfig));
1657
1658 if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
1659 {
1660 assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPStartAddr));
1661 assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPEndAddr));
1662
1663 /* Configure the Proprietary code readout protection */
1664 FLASH->PRAR_PRG1 = ((PCROPStartAddr - FLASH_BANK1_BASE) >> 8) | \
1665 (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
1666 PCROPConfig;
1667 }
1668
1669 #if defined (DUAL_BANK)
1670 if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
1671 {
1672 assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr));
1673 assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPEndAddr));
1674
1675 /* Configure the Proprietary code readout protection */
1676 FLASH->PRAR_PRG2 = ((PCROPStartAddr - FLASH_BANK2_BASE) >> 8) | \
1677 (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \
1678 PCROPConfig;
1679 }
1680 #endif /* DUAL_BANK */
1681 }
1682
1683 /**
1684 * @brief Get the Proprietary code readout protection configuration on a given Bank
1685 *
1686 * @param PCROPConfig indicates if the PCROP area for the given Bank shall be erased or not
1687 * when RDP level decreased from Level 1 to Level 0 or after a bank erase with protection removal
1688 *
1689 * @param PCROPStartAddr gives the start address of the Proprietary code readout protection of the bank
1690 *
1691 * @param PCROPEndAddr gives the end address of the Proprietary code readout protection of the bank
1692 *
1693 * @param Bank the specific bank to apply PCROP protection
1694 * This parameter can be exclusively one of the following values:
1695 * @arg FLASH_BANK_1: PCROP on specified bank1 area
1696 * @arg FLASH_BANK_2: PCROP on specified bank2 area
1697 * @arg FLASH_BANK_BOTH: is not allowed here
1698 *
1699 * @retval None
1700 */
FLASH_OB_GetPCROP(uint32_t * PCROPConfig,uint32_t * PCROPStartAddr,uint32_t * PCROPEndAddr,uint32_t Bank)1701 static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr, uint32_t Bank)
1702 {
1703 uint32_t regvalue = 0;
1704 uint32_t bankBase = 0;
1705
1706 if(Bank == FLASH_BANK_1)
1707 {
1708 regvalue = FLASH->PRAR_CUR1;
1709 bankBase = FLASH_BANK1_BASE;
1710 }
1711
1712 #if defined (DUAL_BANK)
1713 if(Bank == FLASH_BANK_2)
1714 {
1715 regvalue = FLASH->PRAR_CUR2;
1716 bankBase = FLASH_BANK2_BASE;
1717 }
1718 #endif /* DUAL_BANK */
1719
1720 (*PCROPConfig) = (regvalue & FLASH_PRAR_DMEP);
1721
1722 (*PCROPStartAddr) = ((regvalue & FLASH_PRAR_PROT_AREA_START) << 8) + bankBase;
1723 (*PCROPEndAddr) = (regvalue & FLASH_PRAR_PROT_AREA_END) >> FLASH_PRAR_PROT_AREA_END_Pos;
1724 (*PCROPEndAddr) = ((*PCROPEndAddr) << 8) + bankBase;
1725 }
1726
1727 /**
1728 * @brief Set the BOR Level.
1729 * @param Level specifies the Option Bytes BOR Reset Level.
1730 * This parameter can be one of the following values:
1731 * @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V
1732 * @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V
1733 * @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V
1734 * @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V
1735 * @retval None
1736 */
FLASH_OB_BOR_LevelConfig(uint32_t Level)1737 static void FLASH_OB_BOR_LevelConfig(uint32_t Level)
1738 {
1739 assert_param(IS_OB_BOR_LEVEL(Level));
1740
1741 /* Configure BOR_LEV option byte */
1742 MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_BOR_LEV, Level);
1743 }
1744
1745 /**
1746 * @brief Get the BOR Level.
1747 * @retval The Option Bytes BOR Reset Level.
1748 * This parameter can be one of the following values:
1749 * @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V
1750 * @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V
1751 * @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V
1752 * @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V
1753 */
FLASH_OB_GetBOR(void)1754 static uint32_t FLASH_OB_GetBOR(void)
1755 {
1756 return (FLASH->OPTSR_CUR & FLASH_OPTSR_BOR_LEV);
1757 }
1758
1759 /**
1760 * @brief Set Boot address
1761 * @param BootOption Boot address option byte to be programmed,
1762 * This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
1763 (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
1764 *
1765 * @param BootAddress0 Specifies the Boot Address 0
1766 * @param BootAddress1 Specifies the Boot Address 1
1767 * @retval HAL Status
1768 */
FLASH_OB_BootAddConfig(uint32_t BootOption,uint32_t BootAddress0,uint32_t BootAddress1)1769 static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
1770 {
1771 /* Check the parameters */
1772 assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
1773
1774 if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
1775 {
1776 /* Check the parameters */
1777 assert_param(IS_BOOT_ADDRESS(BootAddress0));
1778
1779 /* Configure CM7 BOOT ADD0 */
1780 #if defined(DUAL_CORE)
1781 MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD0, (BootAddress0 >> 16));
1782 #else /* Single Core*/
1783 MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD0, (BootAddress0 >> 16));
1784 #endif /* DUAL_CORE */
1785 }
1786
1787 if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
1788 {
1789 /* Check the parameters */
1790 assert_param(IS_BOOT_ADDRESS(BootAddress1));
1791
1792 /* Configure CM7 BOOT ADD1 */
1793 #if defined(DUAL_CORE)
1794 MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD1, BootAddress1);
1795 #else /* Single Core*/
1796 MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD1, BootAddress1);
1797 #endif /* DUAL_CORE */
1798 }
1799 }
1800
1801 /**
1802 * @brief Get Boot address
1803 * @param BootAddress0 Specifies the Boot Address 0.
1804 * @param BootAddress1 Specifies the Boot Address 1.
1805 * @retval HAL Status
1806 */
FLASH_OB_GetBootAdd(uint32_t * BootAddress0,uint32_t * BootAddress1)1807 static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
1808 {
1809 uint32_t regvalue;
1810
1811 #if defined(DUAL_CORE)
1812 regvalue = FLASH->BOOT7_CUR;
1813
1814 (*BootAddress0) = (regvalue & FLASH_BOOT7_BCM7_ADD0) << 16;
1815 (*BootAddress1) = (regvalue & FLASH_BOOT7_BCM7_ADD1);
1816 #else /* Single Core */
1817 regvalue = FLASH->BOOT_CUR;
1818
1819 (*BootAddress0) = (regvalue & FLASH_BOOT_ADD0) << 16;
1820 (*BootAddress1) = (regvalue & FLASH_BOOT_ADD1);
1821 #endif /* DUAL_CORE */
1822 }
1823
1824 #if defined(DUAL_CORE)
1825 /**
1826 * @brief Set CM4 Boot address
1827 * @param BootOption Boot address option byte to be programmed,
1828 * This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
1829 (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
1830 *
1831 * @param BootAddress0 Specifies the CM4 Boot Address 0.
1832 * @param BootAddress1 Specifies the CM4 Boot Address 1.
1833 * @retval HAL Status
1834 */
FLASH_OB_CM4BootAddConfig(uint32_t BootOption,uint32_t BootAddress0,uint32_t BootAddress1)1835 static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
1836 {
1837 /* Check the parameters */
1838 assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
1839
1840 if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
1841 {
1842 /* Check the parameters */
1843 assert_param(IS_BOOT_ADDRESS(BootAddress0));
1844
1845 /* Configure CM4 BOOT ADD0 */
1846 MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD0, (BootAddress0 >> 16));
1847
1848 }
1849
1850 if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
1851 {
1852 /* Check the parameters */
1853 assert_param(IS_BOOT_ADDRESS(BootAddress1));
1854
1855 /* Configure CM4 BOOT ADD1 */
1856 MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD1, BootAddress1);
1857 }
1858 }
1859
1860 /**
1861 * @brief Get CM4 Boot address
1862 * @param BootAddress0 Specifies the CM4 Boot Address 0.
1863 * @param BootAddress1 Specifies the CM4 Boot Address 1.
1864 * @retval HAL Status
1865 */
FLASH_OB_GetCM4BootAdd(uint32_t * BootAddress0,uint32_t * BootAddress1)1866 static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
1867 {
1868 uint32_t regvalue;
1869
1870 regvalue = FLASH->BOOT4_CUR;
1871
1872 (*BootAddress0) = (regvalue & FLASH_BOOT4_BCM4_ADD0) << 16;
1873 (*BootAddress1) = (regvalue & FLASH_BOOT4_BCM4_ADD1);
1874 }
1875 #endif /*DUAL_CORE*/
1876
1877 /**
1878 * @brief Set secure area configuration
1879 * @param SecureAreaConfig specify if the secure area will be deleted or not
1880 * when RDP level decreased from Level 1 to Level 0 or during a mass erase.
1881 *
1882 * @param SecureAreaStartAddr Specifies the secure area start address
1883 * @param SecureAreaEndAddr Specifies the secure area end address
1884 * @param Banks the specific bank to apply Security protection
1885 * This parameter can be one of the following values:
1886 * @arg FLASH_BANK_1: Secure area on specified bank1 area
1887 * @arg FLASH_BANK_2: Secure area on specified bank2 area
1888 * @arg FLASH_BANK_BOTH: Secure area on specified bank1 and bank2 area (same config will be applied on both banks)
1889 * @retval None
1890 */
FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig,uint32_t SecureAreaStartAddr,uint32_t SecureAreaEndAddr,uint32_t Banks)1891 static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks)
1892 {
1893 /* Check the parameters */
1894 assert_param(IS_FLASH_BANK(Banks));
1895 assert_param(IS_OB_SECURE_RDP(SecureAreaConfig));
1896
1897 if((Banks & FLASH_BANK_1) == FLASH_BANK_1)
1898 {
1899 /* Check the parameters */
1900 assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaStartAddr));
1901 assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaEndAddr));
1902
1903 /* Configure the secure area */
1904 FLASH->SCAR_PRG1 = ((SecureAreaStartAddr - FLASH_BANK1_BASE) >> 8) | \
1905 (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
1906 (SecureAreaConfig & FLASH_SCAR_DMES);
1907 }
1908
1909 #if defined (DUAL_BANK)
1910 if((Banks & FLASH_BANK_2) == FLASH_BANK_2)
1911 {
1912 /* Check the parameters */
1913 assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaStartAddr));
1914 assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaEndAddr));
1915
1916 /* Configure the secure area */
1917 FLASH->SCAR_PRG2 = ((SecureAreaStartAddr - FLASH_BANK2_BASE) >> 8) | \
1918 (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \
1919 (SecureAreaConfig & FLASH_SCAR_DMES);
1920 }
1921 #endif /* DUAL_BANK */
1922 }
1923
1924 /**
1925 * @brief Get secure area configuration
1926 * @param SecureAreaConfig indicates if the secure area will be deleted or not
1927 * when RDP level decreased from Level 1 to Level 0 or during a mass erase.
1928 * @param SecureAreaStartAddr gives the secure area start address
1929 * @param SecureAreaEndAddr gives the secure area end address
1930 * @param Bank Specifies the Bank
1931 * @retval None
1932 */
FLASH_OB_GetSecureArea(uint32_t * SecureAreaConfig,uint32_t * SecureAreaStartAddr,uint32_t * SecureAreaEndAddr,uint32_t Bank)1933 static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank)
1934 {
1935 uint32_t regvalue = 0;
1936 uint32_t bankBase = 0;
1937
1938 /* Check Bank parameter value */
1939 if(Bank == FLASH_BANK_1)
1940 {
1941 regvalue = FLASH->SCAR_CUR1;
1942 bankBase = FLASH_BANK1_BASE;
1943 }
1944
1945 #if defined (DUAL_BANK)
1946 if(Bank == FLASH_BANK_2)
1947 {
1948 regvalue = FLASH->SCAR_CUR2;
1949 bankBase = FLASH_BANK2_BASE;
1950 }
1951 #endif /* DUAL_BANK */
1952
1953 /* Get the secure area settings */
1954 (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES);
1955 (*SecureAreaStartAddr) = ((regvalue & FLASH_SCAR_SEC_AREA_START) << 8) + bankBase;
1956 (*SecureAreaEndAddr) = (regvalue & FLASH_SCAR_SEC_AREA_END) >> FLASH_SCAR_SEC_AREA_END_Pos;
1957 (*SecureAreaEndAddr) = ((*SecureAreaEndAddr) << 8) + bankBase;
1958 }
1959
1960 /**
1961 * @brief Add a CRC sector to the list of sectors on which the CRC will be calculated
1962 * @param Sector Specifies the CRC sector number
1963 * @param Bank Specifies the Bank
1964 * @retval None
1965 */
FLASH_CRC_AddSector(uint32_t Sector,uint32_t Bank)1966 static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank)
1967 {
1968 /* Check the parameters */
1969 assert_param(IS_FLASH_SECTOR(Sector));
1970
1971 if (Bank == FLASH_BANK_1)
1972 {
1973 /* Clear CRC sector */
1974 FLASH->CRCCR1 &= (~FLASH_CRCCR_CRC_SECT);
1975
1976 /* Select CRC Sector and activate ADD_SECT bit */
1977 FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT;
1978 }
1979 #if defined (DUAL_BANK)
1980 else
1981 {
1982 /* Clear CRC sector */
1983 FLASH->CRCCR2 &= (~FLASH_CRCCR_CRC_SECT);
1984
1985 /* Select CRC Sector and activate ADD_SECT bit */
1986 FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT;
1987 }
1988 #endif /* DUAL_BANK */
1989 }
1990
1991 /**
1992 * @brief Select CRC start and end memory addresses on which the CRC will be calculated
1993 * @param CRCStartAddr Specifies the CRC start address
1994 * @param CRCEndAddr Specifies the CRC end address
1995 * @param Bank Specifies the Bank
1996 * @retval None
1997 */
FLASH_CRC_SelectAddress(uint32_t CRCStartAddr,uint32_t CRCEndAddr,uint32_t Bank)1998 static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank)
1999 {
2000 if (Bank == FLASH_BANK_1)
2001 {
2002 assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCStartAddr));
2003 assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCEndAddr));
2004
2005 /* Write CRC Start and End addresses */
2006 FLASH->CRCSADD1 = CRCStartAddr;
2007 FLASH->CRCEADD1 = CRCEndAddr;
2008 }
2009 #if defined (DUAL_BANK)
2010 else
2011 {
2012 assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr));
2013 assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCEndAddr));
2014
2015 /* Write CRC Start and End addresses */
2016 FLASH->CRCSADD2 = CRCStartAddr;
2017 FLASH->CRCEADD2 = CRCEndAddr;
2018 }
2019 #endif /* DUAL_BANK */
2020 }
2021 /**
2022 * @}
2023 */
2024
2025 #if defined (FLASH_OTPBL_LOCKBL)
2026 /**
2027 * @brief Configure the OTP Block Lock.
2028 * @param OTP_Block specifies the OTP Block to lock.
2029 * This parameter can be a value of @ref FLASHEx_OTP_Blocks
2030 * @retval None
2031 */
FLASH_OB_OTP_LockConfig(uint32_t OTP_Block)2032 static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block)
2033 {
2034 /* Check the parameters */
2035 assert_param(IS_OTP_BLOCK(OTP_Block));
2036
2037 /* Configure the OTP Block lock in the option bytes register */
2038 FLASH->OTPBL_PRG |= (OTP_Block & FLASH_OTPBL_LOCKBL);
2039 }
2040
2041 /**
2042 * @brief Get the OTP Block Lock.
2043 * @retval OTP_Block specifies the OTP Block to lock.
2044 * This return value can be a value of @ref FLASHEx_OTP_Blocks
2045 */
FLASH_OB_OTP_GetLock(void)2046 static uint32_t FLASH_OB_OTP_GetLock(void)
2047 {
2048 return (FLASH->OTPBL_CUR);
2049 }
2050 #endif /* FLASH_OTPBL_LOCKBL */
2051
2052 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
2053 /**
2054 * @brief Configure the TCM / AXI Shared RAM.
2055 * @param SharedRamConfig specifies the Shared RAM configuration.
2056 * This parameter can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED
2057 * @retval None
2058 */
FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig)2059 static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig)
2060 {
2061 /* Check the parameters */
2062 assert_param(IS_OB_USER_TCM_AXI_SHARED(SharedRamConfig));
2063
2064 /* Configure the TCM / AXI Shared RAM in the option bytes register */
2065 MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_TCM_AXI_SHARED, SharedRamConfig);
2066 }
2067
2068 /**
2069 * @brief Get the TCM / AXI Shared RAM configuration.
2070 * @retval SharedRamConfig returns the TCM / AXI Shared RAM configuration.
2071 * This return value can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED
2072 */
FLASH_OB_SharedRAM_GetConfig(void)2073 static uint32_t FLASH_OB_SharedRAM_GetConfig(void)
2074 {
2075 return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED);
2076 }
2077 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
2078
2079 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
2080 /**
2081 * @brief Configure the CPU Frequency Boost.
2082 * @param FreqBoost specifies the CPU Frequency Boost state.
2083 * This parameter can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST
2084 * @retval None
2085 */
FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost)2086 static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost)
2087 {
2088 /* Check the parameters */
2089 assert_param(IS_OB_USER_CPUFREQ_BOOST(FreqBoost));
2090
2091 /* Configure the CPU Frequency Boost in the option bytes register */
2092 MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_CPUFREQ_BOOST, FreqBoost);
2093 }
2094
2095 /**
2096 * @brief Get the CPU Frequency Boost state.
2097 * @retval FreqBoost returns the CPU Frequency Boost state.
2098 * This return value can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST
2099 */
FLASH_OB_CPUFreq_GetBoost(void)2100 static uint32_t FLASH_OB_CPUFreq_GetBoost(void)
2101 {
2102 return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST);
2103 }
2104 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
2105
2106 #endif /* HAL_FLASH_MODULE_ENABLED */
2107
2108 /**
2109 * @}
2110 */
2111
2112 /**
2113 * @}
2114 */
2115
2116
