1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
15
16 [..]
17 *** How to configure Interrupts using CORTEX HAL driver ***
18 ===========================================================
19 [..]
20 This section provides functions allowing to configure the NVIC interrupts (IRQ).
21 The Cortex-M exceptions are managed by CMSIS functions.
22
23 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
24 function according to the following table.
25 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
26 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
27 (#) please refer to programming manual for details in how to configure priority.
28
29 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
30 The pending IRQ priority will be managed only by the sub priority.
31
32 -@- IRQ priority order (sorted by highest to lowest priority):
33 (+@) Lowest preemption priority
34 (+@) Lowest sub priority
35 (+@) Lowest hardware priority (IRQ number)
36
37 [..]
38 *** How to configure Systick using CORTEX HAL driver ***
39 ========================================================
40 [..]
41 Setup SysTick Timer for time base.
42
43 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
44 is a CMSIS function that:
45 (++) Configures the SysTick Reload register with value passed as function parameter.
46 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
47 (++) Resets the SysTick Counter register.
48 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
49 (++) Enables the SysTick Interrupt.
50 (++) Starts the SysTick Counter.
51
52 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
53 HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
54 HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
55 inside the stm32h7xx_hal_cortex.h file.
56
57 (+) You can change the SysTick IRQ priority by calling the
58 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
59 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
60
61 (+) To adjust the SysTick time base, use the following formula:
62
63 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
64 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
65 (++) Reload Value should not exceed 0xFFFFFF
66
67 @endverbatim
68 ******************************************************************************
69 * @attention
70 *
71 * Copyright (c) 2017 STMicroelectronics.
72 * All rights reserved.
73 *
74 * This software is licensed under terms that can be found in the LICENSE file in
75 * the root directory of this software component.
76 * If no LICENSE file comes with this software, it is provided AS-IS.
77 *
78 ******************************************************************************
79 */
80
81 /* Includes ------------------------------------------------------------------*/
82 #include "stm32h7xx_hal.h"
83
84 /** @addtogroup STM32H7xx_HAL_Driver
85 * @{
86 */
87
88 /** @defgroup CORTEX CORTEX
89 * @brief CORTEX HAL module driver
90 * @{
91 */
92
93 #ifdef HAL_CORTEX_MODULE_ENABLED
94
95 /* Private types -------------------------------------------------------------*/
96 /* Private variables ---------------------------------------------------------*/
97 /* Private constants ---------------------------------------------------------*/
98 /* Private macros ------------------------------------------------------------*/
99 /* Private functions ---------------------------------------------------------*/
100 /* Exported functions --------------------------------------------------------*/
101
102 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
103 * @{
104 */
105
106
107 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
108 * @brief Initialization and Configuration functions
109 *
110 @verbatim
111 ==============================================================================
112 ##### Initialization and de-initialization functions #####
113 ==============================================================================
114 [..]
115 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
116 Systick functionalities
117
118 @endverbatim
119 * @{
120 */
121
122
123 /**
124 * @brief Sets the priority grouping field (preemption priority and subpriority)
125 * using the required unlock sequence.
126 * @param PriorityGroup The priority grouping bits length.
127 * This parameter can be one of the following values:
128 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
129 * 4 bits for subpriority
130 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
131 * 3 bits for subpriority
132 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
133 * 2 bits for subpriority
134 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
135 * 1 bits for subpriority
136 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
137 * 0 bits for subpriority
138 * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
139 * The pending IRQ priority will be managed only by the subpriority.
140 * @retval None
141 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)142 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
143 {
144 /* Check the parameters */
145 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
146
147 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
148 NVIC_SetPriorityGrouping(PriorityGroup);
149 }
150
151 /**
152 * @brief Sets the priority of an interrupt.
153 * @param IRQn External interrupt number.
154 * This parameter can be an enumerator of IRQn_Type enumeration
155 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
156 * @param PreemptPriority The preemption priority for the IRQn channel.
157 * This parameter can be a value between 0 and 15
158 * A lower priority value indicates a higher priority
159 * @param SubPriority the subpriority level for the IRQ channel.
160 * This parameter can be a value between 0 and 15
161 * A lower priority value indicates a higher priority.
162 * @retval None
163 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)164 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
165 {
166 uint32_t prioritygroup;
167
168 /* Check the parameters */
169 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
170 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
171
172 prioritygroup = NVIC_GetPriorityGrouping();
173
174 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
175 }
176
177 /**
178 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
179 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
180 * function should be called before.
181 * @param IRQn External interrupt number.
182 * This parameter can be an enumerator of IRQn_Type enumeration
183 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
184 * @retval None
185 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)186 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
187 {
188 /* Check the parameters */
189 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
190
191 /* Enable interrupt */
192 NVIC_EnableIRQ(IRQn);
193 }
194
195 /**
196 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
197 * @param IRQn External interrupt number.
198 * This parameter can be an enumerator of IRQn_Type enumeration
199 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
200 * @retval None
201 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)202 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
203 {
204 /* Check the parameters */
205 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
206
207 /* Disable interrupt */
208 NVIC_DisableIRQ(IRQn);
209 }
210
211 /**
212 * @brief Initiates a system reset request to reset the MCU.
213 * @retval None
214 */
HAL_NVIC_SystemReset(void)215 void HAL_NVIC_SystemReset(void)
216 {
217 /* System Reset */
218 NVIC_SystemReset();
219 }
220
221 /**
222 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
223 * Counter is in free running mode to generate periodic interrupts.
224 * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
225 * @retval status - 0 Function succeeded.
226 * - 1 Function failed.
227 */
HAL_SYSTICK_Config(uint32_t TicksNumb)228 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
229 {
230 return SysTick_Config(TicksNumb);
231 }
232 /**
233 * @}
234 */
235
236 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
237 * @brief Cortex control functions
238 *
239 @verbatim
240 ==============================================================================
241 ##### Peripheral Control functions #####
242 ==============================================================================
243 [..]
244 This subsection provides a set of functions allowing to control the CORTEX
245 (NVIC, SYSTICK, MPU) functionalities.
246
247
248 @endverbatim
249 * @{
250 */
251 #if (__MPU_PRESENT == 1)
252 /**
253 * @brief Disables the MPU
254 * @retval None
255 */
HAL_MPU_Disable(void)256 void HAL_MPU_Disable(void)
257 {
258 /* Make sure outstanding transfers are done */
259 __DMB();
260
261 /* Disable fault exceptions */
262 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
263
264 /* Disable the MPU and clear the control register*/
265 MPU->CTRL = 0;
266 }
267
268 /**
269 * @brief Enables the MPU
270 * @param MPU_Control Specifies the control mode of the MPU during hard fault,
271 * NMI, FAULTMASK and privileged access to the default memory
272 * This parameter can be one of the following values:
273 * @arg MPU_HFNMI_PRIVDEF_NONE
274 * @arg MPU_HARDFAULT_NMI
275 * @arg MPU_PRIVILEGED_DEFAULT
276 * @arg MPU_HFNMI_PRIVDEF
277 * @retval None
278 */
HAL_MPU_Enable(uint32_t MPU_Control)279 void HAL_MPU_Enable(uint32_t MPU_Control)
280 {
281 /* Enable the MPU */
282 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
283
284 /* Enable fault exceptions */
285 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
286
287 /* Ensure MPU setting take effects */
288 __DSB();
289 __ISB();
290 }
291
292 /**
293 * @brief Enables the MPU Region.
294 * @retval None
295 */
HAL_MPU_EnableRegion(uint32_t RegionNumber)296 void HAL_MPU_EnableRegion(uint32_t RegionNumber)
297 {
298 /* Check the parameters */
299 assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
300
301 /* Set the Region number */
302 MPU->RNR = RegionNumber;
303
304 /* Enable the Region */
305 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
306 }
307
308 /**
309 * @brief Disables the MPU Region.
310 * @retval None
311 */
HAL_MPU_DisableRegion(uint32_t RegionNumber)312 void HAL_MPU_DisableRegion(uint32_t RegionNumber)
313 {
314 /* Check the parameters */
315 assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
316
317 /* Set the Region number */
318 MPU->RNR = RegionNumber;
319
320 /* Disable the Region */
321 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
322 }
323
324 /**
325 * @brief Initializes and configures the Region and the memory to be protected.
326 * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
327 * the initialization and configuration information.
328 * @retval None
329 */
HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef * MPU_Init)330 void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init)
331 {
332 /* Check the parameters */
333 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
334 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
335 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
336 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
337 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
338 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
339 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
340 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
341 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
342 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
343
344 /* Set the Region number */
345 MPU->RNR = MPU_Init->Number;
346
347 /* Disable the Region */
348 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
349
350 /* Apply configuration */
351 MPU->RBAR = MPU_Init->BaseAddress;
352 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
353 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
354 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
355 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
356 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
357 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
358 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
359 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
360 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
361 }
362 #endif /* __MPU_PRESENT */
363
364 /**
365 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
366 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
367 */
HAL_NVIC_GetPriorityGrouping(void)368 uint32_t HAL_NVIC_GetPriorityGrouping(void)
369 {
370 /* Get the PRIGROUP[10:8] field value */
371 return NVIC_GetPriorityGrouping();
372 }
373
374 /**
375 * @brief Gets the priority of an interrupt.
376 * @param IRQn External interrupt number.
377 * This parameter can be an enumerator of IRQn_Type enumeration
378 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
379 * @param PriorityGroup the priority grouping bits length.
380 * This parameter can be one of the following values:
381 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
382 * 4 bits for subpriority
383 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
384 * 3 bits for subpriority
385 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
386 * 2 bits for subpriority
387 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
388 * 1 bits for subpriority
389 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
390 * 0 bits for subpriority
391 * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
392 * @param pSubPriority Pointer on the Subpriority value (starting from 0).
393 * @retval None
394 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)395 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
396 {
397 /* Check the parameters */
398 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
399 /* Get priority for Cortex-M system or device specific interrupts */
400 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
401 }
402
403 /**
404 * @brief Sets Pending bit of an external interrupt.
405 * @param IRQn External interrupt number
406 * This parameter can be an enumerator of IRQn_Type enumeration
407 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
408 * @retval None
409 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)410 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
411 {
412 /* Check the parameters */
413 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
414
415 /* Set interrupt pending */
416 NVIC_SetPendingIRQ(IRQn);
417 }
418
419 /**
420 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
421 * and returns the pending bit for the specified interrupt).
422 * @param IRQn External interrupt number.
423 * This parameter can be an enumerator of IRQn_Type enumeration
424 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
425 * @retval status - 0 Interrupt status is not pending.
426 * - 1 Interrupt status is pending.
427 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)428 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
429 {
430 /* Check the parameters */
431 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
432
433 /* Return 1 if pending else 0 */
434 return NVIC_GetPendingIRQ(IRQn);
435 }
436
437 /**
438 * @brief Clears the pending bit of an external interrupt.
439 * @param IRQn External interrupt number.
440 * This parameter can be an enumerator of IRQn_Type enumeration
441 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
442 * @retval None
443 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)444 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
445 {
446 /* Check the parameters */
447 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
448
449 /* Clear pending interrupt */
450 NVIC_ClearPendingIRQ(IRQn);
451 }
452
453 /**
454 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
455 * @param IRQn External interrupt number
456 * This parameter can be an enumerator of IRQn_Type enumeration
457 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
458 * @retval status - 0 Interrupt status is not pending.
459 * - 1 Interrupt status is pending.
460 */
HAL_NVIC_GetActive(IRQn_Type IRQn)461 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
462 {
463 /* Check the parameters */
464 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
465
466 /* Return 1 if active else 0 */
467 return NVIC_GetActive(IRQn);
468 }
469
470 /**
471 * @brief Configures the SysTick clock source.
472 * @param CLKSource specifies the SysTick clock source.
473 * This parameter can be one of the following values:
474 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
475 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
476 * @retval None
477 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)478 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
479 {
480 /* Check the parameters */
481 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
482 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
483 {
484 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
485 }
486 else
487 {
488 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
489 }
490 }
491
492 /**
493 * @brief This function handles SYSTICK interrupt request.
494 * @retval None
495 */
HAL_SYSTICK_IRQHandler(void)496 void HAL_SYSTICK_IRQHandler(void)
497 {
498 HAL_SYSTICK_Callback();
499 }
500
501 /**
502 * @brief SYSTICK callback.
503 * @retval None
504 */
HAL_SYSTICK_Callback(void)505 __weak void HAL_SYSTICK_Callback(void)
506 {
507 /* NOTE : This function Should not be modified, when the callback is needed,
508 the HAL_SYSTICK_Callback could be implemented in the user file
509 */
510 }
511
512 #if defined(DUAL_CORE)
513
514 /**
515 * @brief Returns the current CPU ID.
516 * @retval CPU identifier
517 */
HAL_GetCurrentCPUID(void)518 uint32_t HAL_GetCurrentCPUID(void)
519 {
520 if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U)
521 {
522 return CM7_CPUID;
523 }
524 else
525 {
526 return CM4_CPUID;
527 }
528 }
529
530 #else
531
532 /**
533 * @brief Returns the current CPU ID.
534 * @retval CPU identifier
535 */
HAL_GetCurrentCPUID(void)536 uint32_t HAL_GetCurrentCPUID(void)
537 {
538 return CM7_CPUID;
539 }
540
541 #endif /*DUAL_CORE*/
542 /**
543 * @}
544 */
545
546 /**
547 * @}
548 */
549
550 #endif /* HAL_CORTEX_MODULE_ENABLED */
551 /**
552 * @}
553 */
554
555 /**
556 * @}
557 */
558
559
