1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_adc_ex.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Converter (ADC)
7 * peripheral:
8 * + Peripheral Control functions
9 * Other functions (generic functions) are available in file
10 * "stm32h7xx_hal_adc.c".
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2017 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 [..]
25 (@) Sections "ADC peripheral features" and "How to use this driver" are
26 available in file of generic functions "stm32h7xx_hal_adc.c".
27 [..]
28 @endverbatim
29 ******************************************************************************
30 */
31
32 /* Includes ------------------------------------------------------------------*/
33 #include "stm32h7xx_hal.h"
34
35 /** @addtogroup STM32H7xx_HAL_Driver
36 * @{
37 */
38
39 /** @defgroup ADCEx ADCEx
40 * @brief ADC Extended HAL module driver
41 * @{
42 */
43
44 #ifdef HAL_ADC_MODULE_ENABLED
45
46 /* Private typedef -----------------------------------------------------------*/
47 /* Private define ------------------------------------------------------------*/
48
49 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
50 * @{
51 */
52
53 #define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
54 ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
55 ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
56 once the ADC is enabled */
57
58 /* Fixed timeout value for ADC calibration. */
59 /* Fixed timeout value for ADC calibration. */
60 /* Values defined to be higher than worst cases: low clock frequency, */
61 /* maximum prescalers. */
62 /* Ex of profile low frequency : f_ADC at 0.125 Mhz (minimum value */
63 /* according to Data sheet), calibration_time MAX = 165010 / f_ADC */
64 /* 165010 / 125000 = 1.32s */
65 /* At maximum CPU speed (480 MHz), this means */
66 /* 1.32 * 480 MHz = 633600000 CPU cycles */
67 #define ADC_CALIBRATION_TIMEOUT (633600000U) /*!< ADC calibration time-out value */
68
69
70 /**
71 * @}
72 */
73
74 /* Private macro -------------------------------------------------------------*/
75 /* Private variables ---------------------------------------------------------*/
76 /* Private function prototypes -----------------------------------------------*/
77 /* Exported functions --------------------------------------------------------*/
78
79 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
80 * @{
81 */
82
83 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
84 * @brief Extended IO operation functions
85 *
86 @verbatim
87 ===============================================================================
88 ##### IO operation functions #####
89 ===============================================================================
90 [..] This section provides functions allowing to:
91
92 (+) Perform the ADC self-calibration for single or differential ending.
93 (+) Get calibration factors for single or differential ending.
94 (+) Set calibration factors for single or differential ending.
95
96 (+) Start conversion of ADC group injected.
97 (+) Stop conversion of ADC group injected.
98 (+) Poll for conversion complete on ADC group injected.
99 (+) Get result of ADC group injected channel conversion.
100 (+) Start conversion of ADC group injected and enable interruptions.
101 (+) Stop conversion of ADC group injected and disable interruptions.
102
103 (+) When multimode feature is available, start multimode and enable DMA transfer.
104 (+) Stop multimode and disable ADC DMA transfer.
105 (+) Get result of multimode conversion.
106
107 @endverbatim
108 * @{
109 */
110
111 /**
112 * @brief Perform an ADC automatic self-calibration
113 * Calibration prerequisite: ADC must be disabled (execute this
114 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
115 * @param hadc ADC handle
116 * @param CalibrationMode Selection of calibration offset or
117 * linear calibration offset.
118 * @arg ADC_CALIB_OFFSET Channel in mode calibration offset
119 * @arg ADC_CALIB_OFFSET_LINEARITY Channel in mode linear calibration offset
120 * @param SingleDiff Selection of single-ended or differential input
121 * This parameter can be one of the following values:
122 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
123 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
124 * @retval HAL status
125 */
HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef * hadc,uint32_t CalibrationMode,uint32_t SingleDiff)126 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
127 {
128 HAL_StatusTypeDef tmp_hal_status;
129 __IO uint32_t wait_loop_index = 0UL;
130
131 /* Check the parameters */
132 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
133 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
134
135 /* Process locked */
136 __HAL_LOCK(hadc);
137
138 /* Calibration prerequisite: ADC must be disabled. */
139
140 /* Disable the ADC (if not already disabled) */
141 tmp_hal_status = ADC_Disable(hadc);
142
143 /* Check if ADC is effectively disabled */
144 if (tmp_hal_status == HAL_OK)
145 {
146 /* Set ADC state */
147 ADC_STATE_CLR_SET(hadc->State,
148 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
149 HAL_ADC_STATE_BUSY_INTERNAL);
150
151 /* Start ADC calibration in mode single-ended or differential */
152 LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff);
153
154 /* Wait for calibration completion */
155 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
156 {
157 wait_loop_index++;
158 if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
159 {
160 /* Update ADC state machine to error */
161 ADC_STATE_CLR_SET(hadc->State,
162 HAL_ADC_STATE_BUSY_INTERNAL,
163 HAL_ADC_STATE_ERROR_INTERNAL);
164
165 /* Process unlocked */
166 __HAL_UNLOCK(hadc);
167
168 return HAL_ERROR;
169 }
170 }
171
172 /* Set ADC state */
173 ADC_STATE_CLR_SET(hadc->State,
174 HAL_ADC_STATE_BUSY_INTERNAL,
175 HAL_ADC_STATE_READY);
176 }
177 else
178 {
179 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
180
181 /* Note: No need to update variable "tmp_hal_status" here: already set */
182 /* to state "HAL_ERROR" by function disabling the ADC. */
183 }
184
185 /* Process unlocked */
186 __HAL_UNLOCK(hadc);
187
188 /* Return function status */
189 return tmp_hal_status;
190 }
191
192 /**
193 * @brief Get the calibration factor.
194 * @param hadc ADC handle.
195 * @param SingleDiff This parameter can be only:
196 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
197 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
198 * @retval Calibration value.
199 */
HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef * hadc,uint32_t SingleDiff)200 uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
201 {
202 /* Check the parameters */
203 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
204 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
205
206 /* Return the selected ADC calibration value */
207 return LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff);
208 }
209
210 /**
211 * @brief Get the calibration factor from automatic conversion result
212 * @param hadc ADC handle
213 * @param LinearCalib_Buffer: Linear calibration factor
214 * @retval HAL state
215 */
HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef * hadc,uint32_t * LinearCalib_Buffer)216 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
217 {
218 uint32_t cnt;
219 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
220 uint32_t temp_REG_IsConversionOngoing = 0UL;
221
222 /* Check the parameters */
223 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
224
225 /* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */
226 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
227 {
228 tmp_hal_status = ADC_Enable(hadc);
229 }
230
231 if (tmp_hal_status == HAL_OK)
232 {
233 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
234 {
235 LL_ADC_REG_StopConversion(hadc->Instance);
236 temp_REG_IsConversionOngoing = 1UL;
237 }
238 for (cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL; cnt--)
239 {
240 LinearCalib_Buffer[cnt - 1U] = LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT - cnt));
241 }
242 if (temp_REG_IsConversionOngoing != 0UL)
243 {
244 LL_ADC_REG_StartConversion(hadc->Instance);
245 }
246 }
247
248 return tmp_hal_status;
249 }
250
251 /**
252 * @brief Set the calibration factor to overwrite automatic conversion result.
253 * ADC must be enabled and no conversion is ongoing.
254 * @param hadc ADC handle
255 * @param SingleDiff This parameter can be only:
256 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
257 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
258 * @param CalibrationFactor Calibration factor On devices STM32H72xx and STM32H73xx this parameter is coded on 11 bits
259 * maximum for ADC1/2 and on 7 bits for ADC3.
260 * On devices STM32H74xx and STM32H75xx this parameter is coded on 11 bits.
261 * @retval HAL state
262 */
HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef * hadc,uint32_t SingleDiff,uint32_t CalibrationFactor)263 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
264 {
265 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
266 uint32_t tmp_adc_is_conversion_on_going_regular;
267 uint32_t tmp_adc_is_conversion_on_going_injected;
268
269 /* Check the parameters */
270 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
271 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
272
273 #if defined(ADC_VER_V5_V90)
274 if (hadc->Instance == ADC3)
275 {
276 assert_param(IS_ADC_CALFACT_ADC3(CalibrationFactor));
277 }
278 else
279 {
280 assert_param(IS_ADC_CALFACT(CalibrationFactor));
281 }
282 #else
283 assert_param(IS_ADC_CALFACT(CalibrationFactor));
284 #endif
285
286 /* Process locked */
287 __HAL_LOCK(hadc);
288
289 /* Verification of hardware constraints before modifying the calibration */
290 /* factors register: ADC must be enabled, no conversion on going. */
291 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
292 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
293
294 if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
295 && (tmp_adc_is_conversion_on_going_regular == 0UL)
296 && (tmp_adc_is_conversion_on_going_injected == 0UL)
297 )
298 {
299 /* Set the selected ADC calibration value */
300 LL_ADC_SetCalibrationOffsetFactor(hadc->Instance, SingleDiff, CalibrationFactor);
301 }
302 else
303 {
304 /* Update ADC state machine */
305 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
306 /* Update ADC error code */
307 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
308
309 /* Update ADC state machine to error */
310 tmp_hal_status = HAL_ERROR;
311 }
312
313 /* Process unlocked */
314 __HAL_UNLOCK(hadc);
315
316 /* Return function status */
317 return tmp_hal_status;
318 }
319
320 /**
321 * @brief Set the linear calibration factor
322 * @param hadc ADC handle
323 * @param LinearCalib_Buffer: Linear calibration factor
324 * @retval HAL state
325 */
HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef * hadc,uint32_t * LinearCalib_Buffer)326 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer)
327 {
328 uint32_t cnt;
329 __IO uint32_t wait_loop_index = 0;
330 uint32_t temp_REG_IsConversionOngoing = 0UL;
331
332 /* Check the parameters */
333 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
334
335 /* - Exit from deep-power-down mode and ADC voltage regulator enable */
336 /* Exit deep power down mode if still in that state */
337 if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
338 {
339 /* Exit deep power down mode */
340 CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
341
342 /* System was in deep power down mode, calibration must
343 be relaunched or a previously saved calibration factor
344 re-applied once the ADC voltage regulator is enabled */
345 }
346
347
348 if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
349 {
350 /* Enable ADC internal voltage regulator */
351 SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
352 /* Delay for ADC stabilization time */
353 /* Wait loop initialization and execution */
354 /* Note: Variable divided by 2 to compensate partially */
355 /* CPU processing cycles. */
356 wait_loop_index = ((ADC_STAB_DELAY_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
357 while (wait_loop_index != 0UL)
358 {
359 wait_loop_index--;
360 }
361 }
362
363
364 /* Verification that ADC voltage regulator is correctly enabled, whether */
365 /* or not ADC is coming from state reset (if any potential problem of */
366 /* clocking, voltage regulator would not be enabled). */
367 if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
368 {
369 /* Update ADC state machine to error */
370 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
371
372 /* Set ADC error code to ADC peripheral internal error */
373 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
374
375 return HAL_ERROR;
376 }
377 /* Enable the ADC peripheral */
378 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) /* Enable the ADC if it is disabled */
379 {
380 if (ADC_Enable(hadc) != HAL_OK)
381 {
382 return HAL_ERROR;
383 }
384 else
385 {
386 for (cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL ; cnt--)
387 {
388 LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT - cnt), LinearCalib_Buffer[cnt - 1U]);
389 }
390 (void)ADC_Disable(hadc);
391 }
392 }
393 else /* ADC is already enabled, so no need to enable it but need to stop conversion */
394 {
395 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
396 {
397 LL_ADC_REG_StopConversion(hadc->Instance);
398 temp_REG_IsConversionOngoing = 1UL;
399 }
400 for (cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL ; cnt--)
401 {
402 LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT - cnt), LinearCalib_Buffer[cnt - 1U]);
403 }
404 if (temp_REG_IsConversionOngoing != 0UL)
405 {
406 LL_ADC_REG_StartConversion(hadc->Instance);
407 }
408 }
409 return HAL_OK;
410 }
411
412 /**
413 * @brief Load the calibration factor from engi bytes
414 * @param hadc ADC handle
415 * @retval HAL state
416 */
HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef * hadc)417 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc)
418 {
419 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
420 uint32_t cnt, FactorOffset;
421 uint32_t LinearCalib_Buffer[ADC_LINEAR_CALIB_REG_COUNT];
422
423 /* Linearity calibration is retrieved from engi bytes
424 read values from registers and put them to the CALFACT2 register */
425 /* If needed linearity calibration can be done in runtime using
426 LL_ADC_GetCalibrationLinearFactor() */
427 if (hadc->Instance == ADC1)
428 {
429 FactorOffset = 0UL;
430 }
431 else if (hadc->Instance == ADC2)
432 {
433 FactorOffset = 8UL;
434 }
435 else /*Case ADC3*/
436 {
437 FactorOffset = 16UL;
438 }
439
440 for (cnt = 0UL; cnt < ADC_LINEAR_CALIB_REG_COUNT; cnt++)
441 {
442 LinearCalib_Buffer[cnt] = *(uint32_t *)(ADC_LINEAR_CALIB_REG_1_ADDR + FactorOffset + cnt);
443 }
444 if (HAL_ADCEx_LinearCalibration_SetValue(hadc, (uint32_t *)LinearCalib_Buffer) != HAL_OK)
445 {
446 tmp_hal_status = HAL_ERROR;
447 }
448
449 return tmp_hal_status;
450 }
451
452 /**
453 * @brief Enable ADC, start conversion of injected group.
454 * @note Interruptions enabled in this function: None.
455 * @note Case of multimode enabled when multimode feature is available:
456 * HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
457 * then for ADC master.
458 * For ADC slave, ADC is enabled only (conversion is not started).
459 * For ADC master, ADC is enabled and multimode conversion is started.
460 * @param hadc ADC handle.
461 * @retval HAL status
462 */
HAL_ADCEx_InjectedStart(ADC_HandleTypeDef * hadc)463 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
464 {
465 HAL_StatusTypeDef tmp_hal_status;
466 uint32_t tmp_config_injected_queue;
467 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
468
469 /* Check the parameters */
470 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
471
472 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
473 {
474 return HAL_BUSY;
475 }
476 else
477 {
478 /* In case of software trigger detection enabled, JQDIS must be set
479 (which can be done only if ADSTART and JADSTART are both cleared).
480 If JQDIS is not set at that point, returns an error
481 - since software trigger detection is disabled. User needs to
482 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
483 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
484 the queue is empty */
485 tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
486
487 if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
488 && (tmp_config_injected_queue == 0UL)
489 )
490 {
491 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
492 return HAL_ERROR;
493 }
494
495 /* Process locked */
496 __HAL_LOCK(hadc);
497
498 /* Enable the ADC peripheral */
499 tmp_hal_status = ADC_Enable(hadc);
500
501 /* Start conversion if ADC is effectively enabled */
502 if (tmp_hal_status == HAL_OK)
503 {
504 /* Check if a regular conversion is ongoing */
505 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
506 {
507 /* Reset ADC error code field related to injected conversions only */
508 CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
509 }
510 else
511 {
512 /* Set ADC error code to none */
513 ADC_CLEAR_ERRORCODE(hadc);
514 }
515
516 /* Set ADC state */
517 /* - Clear state bitfield related to injected group conversion results */
518 /* - Set state bitfield related to injected operation */
519 ADC_STATE_CLR_SET(hadc->State,
520 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
521 HAL_ADC_STATE_INJ_BUSY);
522
523 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
524 - if ADC instance is master or if multimode feature is not available
525 - if multimode setting is disabled (ADC instance slave in independent mode) */
526 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
527 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
528 )
529 {
530 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
531 }
532
533 /* Clear ADC group injected group conversion flag */
534 /* (To ensure of no unknown state from potential previous ADC operations) */
535 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
536
537 /* Process unlocked */
538 /* Unlock before starting ADC conversions: in case of potential */
539 /* interruption, to let the process to ADC IRQ Handler. */
540 __HAL_UNLOCK(hadc);
541
542 /* Enable conversion of injected group, if automatic injected conversion */
543 /* is disabled. */
544 /* If software start has been selected, conversion starts immediately. */
545 /* If external trigger has been selected, conversion will start at next */
546 /* trigger event. */
547 /* Case of multimode enabled (when multimode feature is available): */
548 /* if ADC is slave, */
549 /* - ADC is enabled only (conversion is not started), */
550 /* - if multimode only concerns regular conversion, ADC is enabled */
551 /* and conversion is started. */
552 /* If ADC is master or independent, */
553 /* - ADC is enabled and conversion is started. */
554 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
555 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
556 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
557 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
558 )
559 {
560 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
561 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
562 {
563 LL_ADC_INJ_StartConversion(hadc->Instance);
564 }
565 }
566 else
567 {
568 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
569 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
570 }
571
572 }
573 else
574 {
575 /* Process unlocked */
576 __HAL_UNLOCK(hadc);
577 }
578
579 /* Return function status */
580 return tmp_hal_status;
581 }
582 }
583
584 /**
585 * @brief Stop conversion of injected channels. Disable ADC peripheral if
586 * no regular conversion is on going.
587 * @note If ADC must be disabled and if conversion is on going on
588 * regular group, function HAL_ADC_Stop must be used to stop both
589 * injected and regular groups, and disable the ADC.
590 * @note If injected group mode auto-injection is enabled,
591 * function HAL_ADC_Stop must be used.
592 * @note In case of multimode enabled (when multimode feature is available),
593 * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
594 * For ADC master, conversion is stopped and ADC is disabled.
595 * For ADC slave, ADC is disabled only (conversion stop of ADC master
596 * has already stopped conversion of ADC slave).
597 * @param hadc ADC handle.
598 * @retval HAL status
599 */
HAL_ADCEx_InjectedStop(ADC_HandleTypeDef * hadc)600 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
601 {
602 HAL_StatusTypeDef tmp_hal_status;
603
604 /* Check the parameters */
605 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
606
607 /* Process locked */
608 __HAL_LOCK(hadc);
609
610 /* 1. Stop potential conversion on going on injected group only. */
611 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
612
613 /* Disable ADC peripheral if injected conversions are effectively stopped */
614 /* and if no conversion on regular group is on-going */
615 if (tmp_hal_status == HAL_OK)
616 {
617 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
618 {
619 /* 2. Disable the ADC peripheral */
620 tmp_hal_status = ADC_Disable(hadc);
621
622 /* Check if ADC is effectively disabled */
623 if (tmp_hal_status == HAL_OK)
624 {
625 /* Set ADC state */
626 ADC_STATE_CLR_SET(hadc->State,
627 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
628 HAL_ADC_STATE_READY);
629 }
630 }
631 /* Conversion on injected group is stopped, but ADC not disabled since */
632 /* conversion on regular group is still running. */
633 else
634 {
635 /* Set ADC state */
636 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
637 }
638 }
639
640 /* Process unlocked */
641 __HAL_UNLOCK(hadc);
642
643 /* Return function status */
644 return tmp_hal_status;
645 }
646
647 /**
648 * @brief Wait for injected group conversion to be completed.
649 * @param hadc ADC handle
650 * @param Timeout Timeout value in millisecond.
651 * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
652 * checked and cleared depending on AUTDLY bit status.
653 * @retval HAL status
654 */
HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)655 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
656 {
657 uint32_t tickstart;
658 uint32_t tmp_Flag_End;
659 uint32_t tmp_adc_inj_is_trigger_source_sw_start;
660 uint32_t tmp_adc_reg_is_trigger_source_sw_start;
661 uint32_t tmp_cfgr;
662 const ADC_TypeDef *tmpADC_Master;
663 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
664
665 /* Check the parameters */
666 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
667
668 /* If end of sequence selected */
669 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
670 {
671 tmp_Flag_End = ADC_FLAG_JEOS;
672 }
673 else /* end of conversion selected */
674 {
675 tmp_Flag_End = ADC_FLAG_JEOC;
676 }
677
678 /* Get timeout */
679 tickstart = HAL_GetTick();
680
681 /* Wait until End of Conversion or Sequence flag is raised */
682 while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
683 {
684 /* Check if timeout is disabled (set to infinite wait) */
685 if (Timeout != HAL_MAX_DELAY)
686 {
687 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
688 {
689 if((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
690 {
691 /* Update ADC state machine to timeout */
692 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
693
694 /* Process unlocked */
695 __HAL_UNLOCK(hadc);
696
697 return HAL_TIMEOUT;
698 }
699 }
700 }
701 }
702
703 /* Retrieve ADC configuration */
704 tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
705 tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
706 /* Get relevant register CFGR in ADC instance of ADC master or slave */
707 /* in function of multimode state (for devices with multimode */
708 /* available). */
709 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
710 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
711 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
712 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
713 )
714 {
715 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
716 }
717 else
718 {
719 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
720 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
721 }
722
723 /* Update ADC state machine */
724 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
725
726 /* Determine whether any further conversion upcoming on group injected */
727 /* by external trigger or by automatic injected conversion */
728 /* from group regular. */
729 if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
730 ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
731 ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
732 (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
733 {
734 /* Check whether end of sequence is reached */
735 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
736 {
737 /* Particular case if injected contexts queue is enabled: */
738 /* when the last context has been fully processed, JSQR is reset */
739 /* by the hardware. Even if no injected conversion is planned to come */
740 /* (queue empty, triggers are ignored), it can start again */
741 /* immediately after setting a new context (JADSTART is still set). */
742 /* Therefore, state of HAL ADC injected group is kept to busy. */
743 if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
744 {
745 /* Set ADC state */
746 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
747
748 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
749 {
750 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
751 }
752 }
753 }
754 }
755
756 /* Clear polled flag */
757 if (tmp_Flag_End == ADC_FLAG_JEOS)
758 {
759 /* Clear end of sequence JEOS flag of injected group if low power feature */
760 /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
761 /* For injected groups, no new conversion will start before JEOS is */
762 /* cleared. */
763 if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
764 {
765 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
766 }
767 }
768 else
769 {
770 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
771 }
772
773 /* Return API HAL status */
774 return HAL_OK;
775 }
776
777 /**
778 * @brief Enable ADC, start conversion of injected group with interruption.
779 * @note Interruptions enabled in this function according to initialization
780 * setting : JEOC (end of conversion) or JEOS (end of sequence)
781 * @note Case of multimode enabled (when multimode feature is enabled):
782 * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
783 * then for ADC master.
784 * For ADC slave, ADC is enabled only (conversion is not started).
785 * For ADC master, ADC is enabled and multimode conversion is started.
786 * @param hadc ADC handle.
787 * @retval HAL status.
788 */
HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef * hadc)789 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
790 {
791 HAL_StatusTypeDef tmp_hal_status;
792 uint32_t tmp_config_injected_queue;
793 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
794
795 /* Check the parameters */
796 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
797
798 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
799 {
800 return HAL_BUSY;
801 }
802 else
803 {
804 /* In case of software trigger detection enabled, JQDIS must be set
805 (which can be done only if ADSTART and JADSTART are both cleared).
806 If JQDIS is not set at that point, returns an error
807 - since software trigger detection is disabled. User needs to
808 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
809 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
810 the queue is empty */
811 tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
812
813 if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
814 && (tmp_config_injected_queue == 0UL)
815 )
816 {
817 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
818 return HAL_ERROR;
819 }
820
821 /* Process locked */
822 __HAL_LOCK(hadc);
823
824 /* Enable the ADC peripheral */
825 tmp_hal_status = ADC_Enable(hadc);
826
827 /* Start conversion if ADC is effectively enabled */
828 if (tmp_hal_status == HAL_OK)
829 {
830 /* Check if a regular conversion is ongoing */
831 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
832 {
833 /* Reset ADC error code field related to injected conversions only */
834 CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
835 }
836 else
837 {
838 /* Set ADC error code to none */
839 ADC_CLEAR_ERRORCODE(hadc);
840 }
841
842 /* Set ADC state */
843 /* - Clear state bitfield related to injected group conversion results */
844 /* - Set state bitfield related to injected operation */
845 ADC_STATE_CLR_SET(hadc->State,
846 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
847 HAL_ADC_STATE_INJ_BUSY);
848
849 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
850 - if ADC instance is master or if multimode feature is not available
851 - if multimode setting is disabled (ADC instance slave in independent mode) */
852 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
853 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
854 )
855 {
856 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
857 }
858
859 /* Clear ADC group injected group conversion flag */
860 /* (To ensure of no unknown state from potential previous ADC operations) */
861 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
862
863 /* Process unlocked */
864 /* Unlock before starting ADC conversions: in case of potential */
865 /* interruption, to let the process to ADC IRQ Handler. */
866 __HAL_UNLOCK(hadc);
867
868 /* Enable ADC Injected context queue overflow interrupt if this feature */
869 /* is enabled. */
870 if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL)
871 {
872 __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
873 }
874
875 /* Enable ADC end of conversion interrupt */
876 switch (hadc->Init.EOCSelection)
877 {
878 case ADC_EOC_SEQ_CONV:
879 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
880 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
881 break;
882 /* case ADC_EOC_SINGLE_CONV */
883 default:
884 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
885 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
886 break;
887 }
888
889 /* Enable conversion of injected group, if automatic injected conversion */
890 /* is disabled. */
891 /* If software start has been selected, conversion starts immediately. */
892 /* If external trigger has been selected, conversion will start at next */
893 /* trigger event. */
894 /* Case of multimode enabled (when multimode feature is available): */
895 /* if ADC is slave, */
896 /* - ADC is enabled only (conversion is not started), */
897 /* - if multimode only concerns regular conversion, ADC is enabled */
898 /* and conversion is started. */
899 /* If ADC is master or independent, */
900 /* - ADC is enabled and conversion is started. */
901 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
902 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
903 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
904 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
905 )
906 {
907 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
908 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
909 {
910 LL_ADC_INJ_StartConversion(hadc->Instance);
911 }
912 }
913 else
914 {
915 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
916 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
917 }
918
919 }
920 else
921 {
922 /* Process unlocked */
923 __HAL_UNLOCK(hadc);
924 }
925
926 /* Return function status */
927 return tmp_hal_status;
928 }
929 }
930
931 /**
932 * @brief Stop conversion of injected channels, disable interruption of
933 * end-of-conversion. Disable ADC peripheral if no regular conversion
934 * is on going.
935 * @note If ADC must be disabled and if conversion is on going on
936 * regular group, function HAL_ADC_Stop must be used to stop both
937 * injected and regular groups, and disable the ADC.
938 * @note If injected group mode auto-injection is enabled,
939 * function HAL_ADC_Stop must be used.
940 * @note Case of multimode enabled (when multimode feature is available):
941 * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
942 * then for ADC slave.
943 * For ADC master, conversion is stopped and ADC is disabled.
944 * For ADC slave, ADC is disabled only (conversion stop of ADC master
945 * has already stopped conversion of ADC slave).
946 * @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
947 * @param hadc ADC handle
948 * @retval HAL status
949 */
HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef * hadc)950 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
951 {
952 HAL_StatusTypeDef tmp_hal_status;
953
954 /* Check the parameters */
955 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
956
957 /* Process locked */
958 __HAL_LOCK(hadc);
959
960 /* 1. Stop potential conversion on going on injected group only. */
961 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
962
963 /* Disable ADC peripheral if injected conversions are effectively stopped */
964 /* and if no conversion on the other group (regular group) is intended to */
965 /* continue. */
966 if (tmp_hal_status == HAL_OK)
967 {
968 /* Disable ADC end of conversion interrupt for injected channels */
969 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
970
971 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
972 {
973 /* 2. Disable the ADC peripheral */
974 tmp_hal_status = ADC_Disable(hadc);
975
976 /* Check if ADC is effectively disabled */
977 if (tmp_hal_status == HAL_OK)
978 {
979 /* Set ADC state */
980 ADC_STATE_CLR_SET(hadc->State,
981 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
982 HAL_ADC_STATE_READY);
983 }
984 }
985 /* Conversion on injected group is stopped, but ADC not disabled since */
986 /* conversion on regular group is still running. */
987 else
988 {
989 /* Set ADC state */
990 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
991 }
992 }
993
994 /* Process unlocked */
995 __HAL_UNLOCK(hadc);
996
997 /* Return function status */
998 return tmp_hal_status;
999 }
1000
1001 /**
1002 * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
1003 * @note Multimode must have been previously configured using
1004 * HAL_ADCEx_MultiModeConfigChannel() function.
1005 * Interruptions enabled in this function:
1006 * overrun, DMA half transfer, DMA transfer complete.
1007 * Each of these interruptions has its dedicated callback function.
1008 * @note Case of ADC slave using its own DMA channel (typical case being both ADC instances using DMA channel
1009 * of ADC master with data concatenated): multimode must be configured without data packing and
1010 * this function must be called first with handle of ADC slave, then with handle of ADC master.
1011 * @note State field of Slave ADC handle is not updated in this configuration:
1012 * user should not rely on it for information related to Slave regular
1013 * conversions.
1014 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
1015 * @param pData Destination Buffer address.
1016 * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
1017 * @retval HAL status
1018 */
HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef * hadc,const uint32_t * pData,uint32_t Length)1019 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length)
1020 {
1021 HAL_StatusTypeDef tmp_hal_status;
1022 ADC_HandleTypeDef tmphadcSlave;
1023 ADC_Common_TypeDef *tmpADC_Common;
1024
1025 /* Check the parameters */
1026 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1027 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
1028 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
1029
1030 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
1031 {
1032 return HAL_BUSY;
1033 }
1034 else
1035 {
1036 /* Process locked */
1037 __HAL_LOCK(hadc);
1038
1039 /* Case of ADC slave using its own DMA channel: check whether handle selected
1040 corresponds to ADC master or slave instance */
1041 if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance)
1042 {
1043 /* Case of ADC slave selected: enable ADC instance */
1044 tmp_hal_status = ADC_Enable(hadc);
1045 }
1046 else
1047 {
1048 tmphadcSlave.State = HAL_ADC_STATE_RESET;
1049 tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
1050 /* Set a temporary handle of the ADC slave associated to the ADC master */
1051 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
1052
1053 if (tmphadcSlave.Instance == NULL)
1054 {
1055 /* Set ADC state */
1056 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1057
1058 /* Process unlocked */
1059 __HAL_UNLOCK(hadc);
1060
1061 return HAL_ERROR;
1062 }
1063
1064 /* Enable the ADC peripherals: master and slave (in case if not already */
1065 /* enabled previously) */
1066 tmp_hal_status = ADC_Enable(hadc);
1067 if (tmp_hal_status == HAL_OK)
1068 {
1069 tmp_hal_status = ADC_Enable(&tmphadcSlave);
1070 }
1071 }
1072
1073 /* Start multimode conversion of ADCs pair */
1074 if (tmp_hal_status == HAL_OK)
1075 {
1076 /* Set ADC state */
1077 ADC_STATE_CLR_SET(hadc->State,
1078 (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
1079 HAL_ADC_STATE_REG_BUSY);
1080
1081 /* Set ADC error code to none */
1082 ADC_CLEAR_ERRORCODE(hadc);
1083
1084 /* Set the DMA transfer complete callback */
1085 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
1086
1087 /* Set the DMA half transfer complete callback */
1088 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
1089
1090 /* Set the DMA error callback */
1091 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
1092
1093 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
1094 /* start (in case of SW start): */
1095
1096 /* Clear regular group conversion flag and overrun flag */
1097 /* (To ensure of no unknown state from potential previous ADC operations) */
1098 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1099
1100 /* Process unlocked */
1101 /* Unlock before starting ADC conversions: in case of potential */
1102 /* interruption, to let the process to ADC IRQ Handler. */
1103 __HAL_UNLOCK(hadc);
1104
1105 /* Enable ADC overrun interrupt */
1106 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1107
1108 /* Case of ADC slave using its own DMA channel: check whether handle selected
1109 corresponds to ADC master or slave instance */
1110 if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance)
1111 {
1112 /* Case of ADC slave selected: Start the DMA channel. */
1113 /* Note: Data transfer will start upon next call of this function using handle of ADC master */
1114 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
1115 }
1116 else
1117 {
1118 /* Pointer to the common control register */
1119 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
1120
1121 /* Start the DMA channel */
1122 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
1123
1124 /* Enable conversion of regular group. */
1125 /* If software start has been selected, conversion starts immediately. */
1126 /* If external trigger has been selected, conversion will start at next */
1127 /* trigger event. */
1128 /* Start ADC group regular conversion */
1129 LL_ADC_REG_StartConversion(hadc->Instance);
1130 }
1131 }
1132 else
1133 {
1134 /* Process unlocked */
1135 __HAL_UNLOCK(hadc);
1136 }
1137
1138 /* Return function status */
1139 return tmp_hal_status;
1140 }
1141 }
1142
1143 /**
1144 * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
1145 * @note Multimode is kept enabled after this function. MultiMode DMA bits
1146 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
1147 * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
1148 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
1149 * resort to HAL_ADCEx_DisableMultiMode() API.
1150 * @note In case of DMA configured in circular mode, function
1151 * HAL_ADC_Stop_DMA() must be called after this function with handle of
1152 * ADC slave, to properly disable the DMA channel.
1153 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
1154 * @retval HAL status
1155 */
HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef * hadc)1156 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
1157 {
1158 HAL_StatusTypeDef tmp_hal_status;
1159 uint32_t tickstart;
1160 ADC_HandleTypeDef tmphadcSlave;
1161 uint32_t tmphadcSlave_conversion_on_going;
1162 HAL_StatusTypeDef tmphadcSlave_disable_status;
1163
1164 /* Check the parameters */
1165 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1166
1167 /* Process locked */
1168 __HAL_LOCK(hadc);
1169
1170
1171 /* 1. Stop potential multimode conversion on going, on regular and injected groups */
1172 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1173
1174 /* Disable ADC peripheral if conversions are effectively stopped */
1175 if (tmp_hal_status == HAL_OK)
1176 {
1177 tmphadcSlave.State = HAL_ADC_STATE_RESET;
1178 tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
1179
1180 /* Set a temporary handle of the ADC slave associated to the ADC master */
1181 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
1182
1183 if (tmphadcSlave.Instance == NULL)
1184 {
1185 /* Update ADC state machine to error */
1186 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1187
1188 /* Process unlocked */
1189 __HAL_UNLOCK(hadc);
1190
1191 return HAL_ERROR;
1192 }
1193
1194 /* Procedure to disable the ADC peripheral: wait for conversions */
1195 /* effectively stopped (ADC master and ADC slave), then disable ADC */
1196
1197 /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
1198 tickstart = HAL_GetTick();
1199
1200 tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
1201 while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1202 || (tmphadcSlave_conversion_on_going == 1UL)
1203 )
1204 {
1205 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
1206 {
1207 /* New check to avoid false timeout detection in case of preemption */
1208 tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
1209
1210 if((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1211 || (tmphadcSlave_conversion_on_going == 1UL)
1212 )
1213 {
1214 /* Update ADC state machine to error */
1215 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1216
1217 /* Process unlocked */
1218 __HAL_UNLOCK(hadc);
1219
1220 return HAL_ERROR;
1221 }
1222 }
1223
1224 tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
1225 }
1226
1227 /* Disable the DMA channel (in case of DMA in circular mode or stop */
1228 /* while DMA transfer is on going) */
1229 /* Note: DMA channel of ADC slave should be stopped after this function */
1230 /* with HAL_ADC_Stop_DMA() API. */
1231 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1232
1233 /* Check if DMA channel effectively disabled */
1234 if (tmp_hal_status == HAL_ERROR)
1235 {
1236 /* Update ADC state machine to error */
1237 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1238 }
1239
1240 /* Disable ADC overrun interrupt */
1241 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1242
1243 /* 2. Disable the ADC peripherals: master and slave */
1244 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
1245 /* memory a potential failing status. */
1246 if (tmp_hal_status == HAL_OK)
1247 {
1248 tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave);
1249 if ((ADC_Disable(hadc) == HAL_OK) &&
1250 (tmphadcSlave_disable_status == HAL_OK))
1251 {
1252 tmp_hal_status = HAL_OK;
1253 }
1254 }
1255 else
1256 {
1257 /* In case of error, attempt to disable ADC master and slave without status assert */
1258 (void) ADC_Disable(hadc);
1259 (void) ADC_Disable(&tmphadcSlave);
1260 }
1261
1262 /* Set ADC state (ADC master) */
1263 ADC_STATE_CLR_SET(hadc->State,
1264 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1265 HAL_ADC_STATE_READY);
1266 }
1267
1268 /* Process unlocked */
1269 __HAL_UNLOCK(hadc);
1270
1271 /* Return function status */
1272 return tmp_hal_status;
1273 }
1274
1275 /**
1276 * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
1277 * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
1278 * @retval The converted data values.
1279 */
HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef * hadc)1280 uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc)
1281 {
1282 const ADC_Common_TypeDef *tmpADC_Common;
1283
1284 /* Check the parameters */
1285 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1286
1287 /* Prevent unused argument(s) compilation warning if no assert_param check */
1288 /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
1289 UNUSED(hadc);
1290
1291 /* Pointer to the common control register */
1292 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
1293
1294 /* Return the multi mode conversion value */
1295 return tmpADC_Common->CDR;
1296 }
1297
1298 /**
1299 * @brief Get ADC injected group conversion result.
1300 * @note Reading register JDRx automatically clears ADC flag JEOC
1301 * (ADC group injected end of unitary conversion).
1302 * @note This function does not clear ADC flag JEOS
1303 * (ADC group injected end of sequence conversion)
1304 * Occurrence of flag JEOS rising:
1305 * - If sequencer is composed of 1 rank, flag JEOS is equivalent
1306 * to flag JEOC.
1307 * - If sequencer is composed of several ranks, during the scan
1308 * sequence flag JEOC only is raised, at the end of the scan sequence
1309 * both flags JEOC and EOS are raised.
1310 * Flag JEOS must not be cleared by this function because
1311 * it would not be compliant with low power features
1312 * (feature low power auto-wait, not available on all STM32 families).
1313 * To clear this flag, either use function:
1314 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
1315 * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
1316 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
1317 * @param hadc ADC handle
1318 * @param InjectedRank the converted ADC injected rank.
1319 * This parameter can be one of the following values:
1320 * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
1321 * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
1322 * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
1323 * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
1324 * @retval ADC group injected conversion data
1325 */
HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef * hadc,uint32_t InjectedRank)1326 uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
1327 {
1328 uint32_t tmp_jdr;
1329
1330 /* Check the parameters */
1331 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1332 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
1333
1334 /* Get ADC converted value */
1335 switch (InjectedRank)
1336 {
1337 case ADC_INJECTED_RANK_4:
1338 tmp_jdr = hadc->Instance->JDR4;
1339 break;
1340 case ADC_INJECTED_RANK_3:
1341 tmp_jdr = hadc->Instance->JDR3;
1342 break;
1343 case ADC_INJECTED_RANK_2:
1344 tmp_jdr = hadc->Instance->JDR2;
1345 break;
1346 case ADC_INJECTED_RANK_1:
1347 default:
1348 tmp_jdr = hadc->Instance->JDR1;
1349 break;
1350 }
1351
1352 /* Return ADC converted value */
1353 return tmp_jdr;
1354 }
1355
1356 /**
1357 * @brief Injected conversion complete callback in non-blocking mode.
1358 * @param hadc ADC handle
1359 * @retval None
1360 */
HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef * hadc)1361 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
1362 {
1363 /* Prevent unused argument(s) compilation warning */
1364 UNUSED(hadc);
1365
1366 /* NOTE : This function should not be modified. When the callback is needed,
1367 function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
1368 */
1369 }
1370
1371 /**
1372 * @brief Injected context queue overflow callback.
1373 * @note This callback is called if injected context queue is enabled
1374 (parameter "QueueInjectedContext" in injected channel configuration)
1375 and if a new injected context is set when queue is full (maximum 2
1376 contexts).
1377 * @param hadc ADC handle
1378 * @retval None
1379 */
HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef * hadc)1380 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
1381 {
1382 /* Prevent unused argument(s) compilation warning */
1383 UNUSED(hadc);
1384
1385 /* NOTE : This function should not be modified. When the callback is needed,
1386 function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
1387 */
1388 }
1389
1390 /**
1391 * @brief Analog watchdog 2 callback in non-blocking mode.
1392 * @param hadc ADC handle
1393 * @retval None
1394 */
HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef * hadc)1395 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
1396 {
1397 /* Prevent unused argument(s) compilation warning */
1398 UNUSED(hadc);
1399
1400 /* NOTE : This function should not be modified. When the callback is needed,
1401 function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
1402 */
1403 }
1404
1405 /**
1406 * @brief Analog watchdog 3 callback in non-blocking mode.
1407 * @param hadc ADC handle
1408 * @retval None
1409 */
HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef * hadc)1410 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
1411 {
1412 /* Prevent unused argument(s) compilation warning */
1413 UNUSED(hadc);
1414
1415 /* NOTE : This function should not be modified. When the callback is needed,
1416 function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
1417 */
1418 }
1419
1420
1421 /**
1422 * @brief End Of Sampling callback in non-blocking mode.
1423 * @param hadc ADC handle
1424 * @retval None
1425 */
HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef * hadc)1426 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
1427 {
1428 /* Prevent unused argument(s) compilation warning */
1429 UNUSED(hadc);
1430
1431 /* NOTE : This function should not be modified. When the callback is needed,
1432 function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
1433 */
1434 }
1435
1436 /**
1437 * @brief Stop ADC conversion of regular group (and injected channels in
1438 * case of auto_injection mode), disable ADC peripheral if no
1439 * conversion is on going on injected group.
1440 * @param hadc ADC handle
1441 * @retval HAL status.
1442 */
HAL_ADCEx_RegularStop(ADC_HandleTypeDef * hadc)1443 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
1444 {
1445 HAL_StatusTypeDef tmp_hal_status;
1446
1447 /* Check the parameters */
1448 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1449
1450 /* Process locked */
1451 __HAL_LOCK(hadc);
1452
1453 /* 1. Stop potential regular conversion on going */
1454 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1455
1456 /* Disable ADC peripheral if regular conversions are effectively stopped
1457 and if no injected conversions are on-going */
1458 if (tmp_hal_status == HAL_OK)
1459 {
1460 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1461 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1462
1463 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1464 {
1465 /* 2. Disable the ADC peripheral */
1466 tmp_hal_status = ADC_Disable(hadc);
1467
1468 /* Check if ADC is effectively disabled */
1469 if (tmp_hal_status == HAL_OK)
1470 {
1471 /* Set ADC state */
1472 ADC_STATE_CLR_SET(hadc->State,
1473 HAL_ADC_STATE_INJ_BUSY,
1474 HAL_ADC_STATE_READY);
1475 }
1476 }
1477 /* Conversion on injected group is stopped, but ADC not disabled since */
1478 /* conversion on regular group is still running. */
1479 else
1480 {
1481 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1482 }
1483 }
1484
1485 /* Process unlocked */
1486 __HAL_UNLOCK(hadc);
1487
1488 /* Return function status */
1489 return tmp_hal_status;
1490 }
1491
1492
1493 /**
1494 * @brief Stop ADC conversion of ADC groups regular and injected,
1495 * disable interrution of end-of-conversion,
1496 * disable ADC peripheral if no conversion is on going
1497 * on injected group.
1498 * @param hadc ADC handle
1499 * @retval HAL status.
1500 */
HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef * hadc)1501 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
1502 {
1503 HAL_StatusTypeDef tmp_hal_status;
1504
1505 /* Check the parameters */
1506 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1507
1508 /* Process locked */
1509 __HAL_LOCK(hadc);
1510
1511 /* 1. Stop potential regular conversion on going */
1512 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1513
1514 /* Disable ADC peripheral if conversions are effectively stopped
1515 and if no injected conversion is on-going */
1516 if (tmp_hal_status == HAL_OK)
1517 {
1518 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1519 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1520
1521 /* Disable all regular-related interrupts */
1522 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1523
1524 /* 2. Disable ADC peripheral if no injected conversions are on-going */
1525 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1526 {
1527 tmp_hal_status = ADC_Disable(hadc);
1528 /* if no issue reported */
1529 if (tmp_hal_status == HAL_OK)
1530 {
1531 /* Set ADC state */
1532 ADC_STATE_CLR_SET(hadc->State,
1533 HAL_ADC_STATE_INJ_BUSY,
1534 HAL_ADC_STATE_READY);
1535 }
1536 }
1537 else
1538 {
1539 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1540 }
1541 }
1542
1543 /* Process unlocked */
1544 __HAL_UNLOCK(hadc);
1545
1546 /* Return function status */
1547 return tmp_hal_status;
1548 }
1549
1550 /**
1551 * @brief Stop ADC conversion of regular group (and injected group in
1552 * case of auto_injection mode), disable ADC DMA transfer, disable
1553 * ADC peripheral if no conversion is on going
1554 * on injected group.
1555 * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
1556 * For multimode (when multimode feature is available),
1557 * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
1558 * @param hadc ADC handle
1559 * @retval HAL status.
1560 */
HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef * hadc)1561 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
1562 {
1563 HAL_StatusTypeDef tmp_hal_status;
1564
1565 /* Check the parameters */
1566 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1567
1568 /* Process locked */
1569 __HAL_LOCK(hadc);
1570
1571 /* 1. Stop potential regular conversion on going */
1572 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1573
1574 /* Disable ADC peripheral if conversions are effectively stopped
1575 and if no injected conversion is on-going */
1576 if (tmp_hal_status == HAL_OK)
1577 {
1578 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1579 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1580
1581 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
1582 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1, 0UL);
1583
1584 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
1585 /* while DMA transfer is on going) */
1586 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1587
1588 /* Check if DMA channel effectively disabled */
1589 if (tmp_hal_status != HAL_OK)
1590 {
1591 /* Update ADC state machine to error */
1592 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1593 }
1594
1595 /* Disable ADC overrun interrupt */
1596 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1597
1598 /* 2. Disable the ADC peripheral */
1599 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
1600 /* to keep in memory a potential failing status. */
1601 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1602 {
1603 if (tmp_hal_status == HAL_OK)
1604 {
1605 tmp_hal_status = ADC_Disable(hadc);
1606 }
1607 else
1608 {
1609 (void)ADC_Disable(hadc);
1610 }
1611
1612 /* Check if ADC is effectively disabled */
1613 if (tmp_hal_status == HAL_OK)
1614 {
1615 /* Set ADC state */
1616 ADC_STATE_CLR_SET(hadc->State,
1617 HAL_ADC_STATE_INJ_BUSY,
1618 HAL_ADC_STATE_READY);
1619 }
1620 }
1621 else
1622 {
1623 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1624 }
1625 }
1626
1627 /* Process unlocked */
1628 __HAL_UNLOCK(hadc);
1629
1630 /* Return function status */
1631 return tmp_hal_status;
1632 }
1633
1634 /**
1635 * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
1636 * @note Multimode is kept enabled after this function. Multimode DMA bits
1637 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
1638 * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
1639 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
1640 * resort to HAL_ADCEx_DisableMultiMode() API.
1641 * @note In case of DMA configured in circular mode, function
1642 * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
1643 * ADC slave, to properly disable the DMA channel.
1644 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
1645 * @retval HAL status
1646 */
HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef * hadc)1647 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
1648 {
1649 HAL_StatusTypeDef tmp_hal_status;
1650 uint32_t tickstart;
1651 ADC_HandleTypeDef tmphadcSlave;
1652 uint32_t tmphadcSlave_conversion_on_going;
1653
1654 /* Check the parameters */
1655 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1656
1657 /* Process locked */
1658 __HAL_LOCK(hadc);
1659
1660
1661 /* 1. Stop potential multimode conversion on going, on regular groups */
1662 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1663
1664 /* Disable ADC peripheral if conversions are effectively stopped */
1665 if (tmp_hal_status == HAL_OK)
1666 {
1667 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1668 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1669
1670 tmphadcSlave.State = HAL_ADC_STATE_RESET;
1671 tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
1672
1673 /* Set a temporary handle of the ADC slave associated to the ADC master */
1674 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
1675
1676 if (tmphadcSlave.Instance == NULL)
1677 {
1678 /* Update ADC state machine to error */
1679 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1680
1681 /* Process unlocked */
1682 __HAL_UNLOCK(hadc);
1683
1684 return HAL_ERROR;
1685 }
1686
1687 /* Procedure to disable the ADC peripheral: wait for conversions */
1688 /* effectively stopped (ADC master and ADC slave), then disable ADC */
1689
1690 /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
1691 tickstart = HAL_GetTick();
1692
1693 tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
1694 while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1695 || (tmphadcSlave_conversion_on_going == 1UL)
1696 )
1697 {
1698 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
1699 {
1700 /* New check to avoid false timeout detection in case of preemption */
1701 tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
1702
1703 if((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1704 || (tmphadcSlave_conversion_on_going == 1UL)
1705 )
1706 {
1707 /* Update ADC state machine to error */
1708 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1709
1710 /* Process unlocked */
1711 __HAL_UNLOCK(hadc);
1712
1713 return HAL_ERROR;
1714 }
1715 }
1716
1717 tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
1718 }
1719
1720 /* Disable the DMA channel (in case of DMA in circular mode or stop */
1721 /* while DMA transfer is on going) */
1722 /* Note: DMA channel of ADC slave should be stopped after this function */
1723 /* with HAL_ADCEx_RegularStop_DMA() API. */
1724 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1725
1726 /* Check if DMA channel effectively disabled */
1727 if (tmp_hal_status != HAL_OK)
1728 {
1729 /* Update ADC state machine to error */
1730 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1731 }
1732
1733 /* Disable ADC overrun interrupt */
1734 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1735
1736 /* 2. Disable the ADC peripherals: master and slave if no injected */
1737 /* conversion is on-going. */
1738 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
1739 /* memory a potential failing status. */
1740 if (tmp_hal_status == HAL_OK)
1741 {
1742 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1743 {
1744 tmp_hal_status = ADC_Disable(hadc);
1745 if (tmp_hal_status == HAL_OK)
1746 {
1747 if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL)
1748 {
1749 tmp_hal_status = ADC_Disable(&tmphadcSlave);
1750 }
1751 }
1752 }
1753
1754 if (tmp_hal_status == HAL_OK)
1755 {
1756 /* Both Master and Slave ADC's could be disabled. Update Master State */
1757 /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
1758 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
1759 }
1760 else
1761 {
1762 /* injected (Master or Slave) conversions are still on-going,
1763 no Master State change */
1764 }
1765 }
1766 }
1767
1768 /* Process unlocked */
1769 __HAL_UNLOCK(hadc);
1770
1771 /* Return function status */
1772 return tmp_hal_status;
1773 }
1774
1775 /**
1776 * @}
1777 */
1778
1779 /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
1780 * @brief ADC Extended Peripheral Control functions
1781 *
1782 @verbatim
1783 ===============================================================================
1784 ##### Peripheral Control functions #####
1785 ===============================================================================
1786 [..] This section provides functions allowing to:
1787 (+) Configure channels on injected group
1788 (+) Configure multimode when multimode feature is available
1789 (+) Enable or Disable Injected Queue
1790 (+) Disable ADC voltage regulator
1791 (+) Enter ADC deep-power-down mode
1792
1793 @endverbatim
1794 * @{
1795 */
1796
1797 /**
1798 * @brief Configure a channel to be assigned to ADC group injected.
1799 * @note Possibility to update parameters on the fly:
1800 * This function initializes injected group, following calls to this
1801 * function can be used to reconfigure some parameters of structure
1802 * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
1803 * The setting of these parameters is conditioned to ADC state:
1804 * Refer to comments of structure "ADC_InjectionConfTypeDef".
1805 * @note In case of usage of internal measurement channels:
1806 * Vbat/VrefInt/TempSensor.
1807 * These internal paths can be disabled using function
1808 * HAL_ADC_DeInit().
1809 * @note Caution: For Injected Context Queue use, a context must be fully
1810 * defined before start of injected conversion. All channels are configured
1811 * consecutively for the same ADC instance. Therefore, the number of calls to
1812 * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
1813 * InjectedNbrOfConversion for each context.
1814 * - Example 1: If 1 context is intended to be used (or if there is no use of the
1815 * Injected Queue Context feature) and if the context contains 3 injected ranks
1816 * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
1817 * called once for each channel (i.e. 3 times) before starting a conversion.
1818 * This function must not be called to configure a 4th injected channel:
1819 * it would start a new context into context queue.
1820 * - Example 2: If 2 contexts are intended to be used and each of them contains
1821 * 3 injected ranks (InjectedNbrOfConversion = 3),
1822 * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
1823 * for each context (3 channels x 2 contexts = 6 calls). Conversion can
1824 * start once the 1st context is set, that is after the first three
1825 * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
1826 * @param hadc ADC handle
1827 * @param sConfigInjected Structure of ADC injected group and ADC channel for
1828 * injected group.
1829 * @retval HAL status
1830 */
HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef * hadc,ADC_InjectionConfTypeDef * sConfigInjected)1831 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
1832 {
1833 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1834 uint32_t tmpOffsetShifted;
1835 uint32_t tmp_config_internal_channel;
1836 uint32_t tmp_adc_is_conversion_on_going_regular;
1837 uint32_t tmp_adc_is_conversion_on_going_injected;
1838 __IO uint32_t wait_loop_index = 0;
1839
1840 uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
1841
1842 /* Check the parameters */
1843 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1844 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
1845 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
1846 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
1847 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
1848 assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
1849 assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
1850 assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
1851 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
1852 #if defined(ADC_VER_V5_V90)
1853 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedOffsetSaturation));
1854 if (hadc->Instance == ADC3)
1855 {
1856 assert_param(IS_ADC3_OFFSET_SIGN(sConfigInjected->InjectedOffsetSign));
1857 assert_param(IS_ADC3_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
1858 }
1859 else
1860 #endif /* ADC_VER_V5_V90 */
1861 {
1862 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
1863 }
1864
1865 if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
1866 {
1867 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
1868 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
1869 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
1870 }
1871
1872 /* Check offset range according to oversampling setting */
1873 if (hadc->Init.OversamplingMode == ENABLE)
1874 {
1875 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset / (hadc->Init.Oversampling.Ratio + 1U)));
1876 }
1877 else
1878 {
1879 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
1880 }
1881 #if defined(ADC_VER_V5_V90)
1882 /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
1883 ignored (considered as reset) */
1884 if (hadc->Instance == ADC3)
1885 {
1886 assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE)));
1887 }
1888 #endif /* ADC_VER_V5_V90 */
1889 /* JDISCEN and JAUTO bits can't be set at the same time */
1890 assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
1891
1892 /* DISCEN and JAUTO bits can't be set at the same time */
1893 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
1894
1895 /* Verification of channel number */
1896 if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
1897 {
1898 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
1899 }
1900 else
1901 {
1902 if (hadc->Instance == ADC1)
1903 {
1904 assert_param(IS_ADC1_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
1905 }
1906 if (hadc->Instance == ADC2)
1907 {
1908 assert_param(IS_ADC2_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
1909 }
1910 #if defined (ADC3)
1911 if (hadc->Instance == ADC3)
1912 {
1913 assert_param(IS_ADC3_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
1914 }
1915 #endif
1916 }
1917
1918 /* Process locked */
1919 __HAL_LOCK(hadc);
1920
1921 /* Configuration of injected group sequencer: */
1922 /* Hardware constraint: Must fully define injected context register JSQR */
1923 /* before make it entering into injected sequencer queue. */
1924 /* */
1925 /* - if scan mode is disabled: */
1926 /* * Injected channels sequence length is set to 0x00: 1 channel */
1927 /* converted (channel on injected rank 1) */
1928 /* Parameter "InjectedNbrOfConversion" is discarded. */
1929 /* * Injected context register JSQR setting is simple: register is fully */
1930 /* defined on one call of this function (for injected rank 1) and can */
1931 /* be entered into queue directly. */
1932 /* - if scan mode is enabled: */
1933 /* * Injected channels sequence length is set to parameter */
1934 /* "InjectedNbrOfConversion". */
1935 /* * Injected context register JSQR setting more complex: register is */
1936 /* fully defined over successive calls of this function, for each */
1937 /* injected channel rank. It is entered into queue only when all */
1938 /* injected ranks have been set. */
1939 /* Note: Scan mode is not present by hardware on this device, but used */
1940 /* by software for alignment over all STM32 devices. */
1941
1942 if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
1943 (sConfigInjected->InjectedNbrOfConversion == 1U))
1944 {
1945 /* Configuration of context register JSQR: */
1946 /* - number of ranks in injected group sequencer: fixed to 1st rank */
1947 /* (scan mode disabled, only rank 1 used) */
1948 /* - external trigger to start conversion */
1949 /* - external trigger polarity */
1950 /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
1951
1952 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
1953 {
1954 /* Enable external trigger if trigger selection is different of */
1955 /* software start. */
1956 /* Note: This configuration keeps the hardware feature of parameter */
1957 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
1958 /* software start. */
1959 if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
1960 {
1961 tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
1962 | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
1963 | sConfigInjected->ExternalTrigInjecConvEdge
1964 );
1965 }
1966 else
1967 {
1968 tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
1969 }
1970
1971 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
1972 /* For debug and informative reasons, hadc handle saves JSQR setting */
1973 hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
1974
1975 }
1976 }
1977 else
1978 {
1979 /* Case of scan mode enabled, several channels to set into injected group */
1980 /* sequencer. */
1981 /* */
1982 /* Procedure to define injected context register JSQR over successive */
1983 /* calls of this function, for each injected channel rank: */
1984 /* 1. Start new context and set parameters related to all injected */
1985 /* channels: injected sequence length and trigger. */
1986
1987 /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
1988 /* call of the context under setting */
1989 if (hadc->InjectionConfig.ChannelCount == 0U)
1990 {
1991 /* Initialize number of channels that will be configured on the context */
1992 /* being built */
1993 hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
1994 /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
1995 call, this context will be written in JSQR register at the last call.
1996 At this point, the context is merely reset */
1997 hadc->InjectionConfig.ContextQueue = 0x00000000U;
1998
1999 /* Configuration of context register JSQR: */
2000 /* - number of ranks in injected group sequencer */
2001 /* - external trigger to start conversion */
2002 /* - external trigger polarity */
2003
2004 /* Enable external trigger if trigger selection is different of */
2005 /* software start. */
2006 /* Note: This configuration keeps the hardware feature of parameter */
2007 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
2008 /* software start. */
2009 if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
2010 {
2011 tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)
2012 | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
2013 | sConfigInjected->ExternalTrigInjecConvEdge
2014 );
2015 }
2016 else
2017 {
2018 tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U));
2019 }
2020
2021 }
2022
2023 /* 2. Continue setting of context under definition with parameter */
2024 /* related to each channel: channel rank sequence */
2025 /* Clear the old JSQx bits for the selected rank */
2026 tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
2027
2028 /* Set the JSQx bits for the selected rank */
2029 tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
2030
2031 /* Decrease channel count */
2032 hadc->InjectionConfig.ChannelCount--;
2033
2034 /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
2035 call, aggregate the setting to those already built during the previous
2036 HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
2037 hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
2038
2039 /* 4. End of context setting: if this is the last channel set, then write context
2040 into register JSQR and make it enter into queue */
2041 if (hadc->InjectionConfig.ChannelCount == 0U)
2042 {
2043 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
2044 }
2045 }
2046
2047 /* Parameters update conditioned to ADC state: */
2048 /* Parameters that can be updated when ADC is disabled or enabled without */
2049 /* conversion on going on injected group: */
2050 /* - Injected context queue: Queue disable (active context is kept) or */
2051 /* enable (context decremented, up to 2 contexts queued) */
2052 /* - Injected discontinuous mode: can be enabled only if auto-injected */
2053 /* mode is disabled. */
2054 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
2055 {
2056 if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel)))
2057 {
2058 #if defined(ADC_VER_V5_V90)
2059 if (hadc->Instance != ADC3)
2060 {
2061 /* ADC channels preselection */
2062 hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
2063 }
2064 #else
2065 /* ADC channels preselection */
2066 hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
2067 #endif /* ADC_VER_V5_V90 */
2068 }
2069
2070 /* If auto-injected mode is disabled: no constraint */
2071 if (sConfigInjected->AutoInjectedConv == DISABLE)
2072 {
2073 MODIFY_REG(hadc->Instance->CFGR,
2074 ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
2075 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) |
2076 ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode));
2077 }
2078 /* If auto-injected mode is enabled: Injected discontinuous setting is */
2079 /* discarded. */
2080 else
2081 {
2082 MODIFY_REG(hadc->Instance->CFGR,
2083 ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
2084 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext));
2085 }
2086
2087 }
2088
2089 /* Parameters update conditioned to ADC state: */
2090 /* Parameters that can be updated when ADC is disabled or enabled without */
2091 /* conversion on going on regular and injected groups: */
2092 /* - Automatic injected conversion: can be enabled if injected group */
2093 /* external triggers are disabled. */
2094 /* - Channel sampling time */
2095 /* - Channel offset */
2096 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2097 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2098
2099 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2100 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2101 )
2102 {
2103 /* If injected group external triggers are disabled (set to injected */
2104 /* software start): no constraint */
2105 if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
2106 || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
2107 {
2108 if (sConfigInjected->AutoInjectedConv == ENABLE)
2109 {
2110 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
2111 }
2112 else
2113 {
2114 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
2115 }
2116 }
2117 /* If Automatic injected conversion was intended to be set and could not */
2118 /* due to injected group external triggers enabled, error is reported. */
2119 else
2120 {
2121 if (sConfigInjected->AutoInjectedConv == ENABLE)
2122 {
2123 /* Update ADC state machine to error */
2124 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2125
2126 tmp_hal_status = HAL_ERROR;
2127 }
2128 else
2129 {
2130 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
2131 }
2132 }
2133
2134 if (sConfigInjected->InjecOversamplingMode == ENABLE)
2135 {
2136 #if defined(ADC_VER_V5_V90)
2137 if (hadc->Instance == ADC3)
2138 {
2139 assert_param(IS_ADC_OVERSAMPLING_RATIO_ADC3(sConfigInjected->InjecOversampling.Ratio));
2140 }
2141 else
2142 {
2143 assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
2144 }
2145 #else
2146 assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
2147 #endif
2148 assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
2149
2150 /* JOVSE must be reset in case of triggered regular mode */
2151 assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
2152
2153 /* Configuration of Injected Oversampler: */
2154 /* - Oversampling Ratio */
2155 /* - Right bit shift */
2156
2157 /* Enable OverSampling mode */
2158 #if defined(ADC_VER_V5_V90)
2159 if (hadc->Instance != ADC3)
2160 {
2161 MODIFY_REG(hadc->Instance->CFGR2,
2162 ADC_CFGR2_JOVSE |
2163 ADC_CFGR2_OVSR |
2164 ADC_CFGR2_OVSS,
2165 ADC_CFGR2_JOVSE |
2166 ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
2167 sConfigInjected->InjecOversampling.RightBitShift
2168 );
2169 }
2170 else
2171 {
2172 MODIFY_REG(hadc->Instance->CFGR2,
2173 ADC_CFGR2_JOVSE |
2174 ADC3_CFGR2_OVSR |
2175 ADC_CFGR2_OVSS,
2176 ADC_CFGR2_JOVSE |
2177 (sConfigInjected->InjecOversampling.Ratio) |
2178 sConfigInjected->InjecOversampling.RightBitShift
2179 );
2180 }
2181 #else
2182 MODIFY_REG(hadc->Instance->CFGR2,
2183 ADC_CFGR2_JOVSE |
2184 ADC_CFGR2_OVSR |
2185 ADC_CFGR2_OVSS,
2186 ADC_CFGR2_JOVSE |
2187 ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
2188 sConfigInjected->InjecOversampling.RightBitShift
2189 );
2190 #endif
2191 }
2192 else
2193 {
2194 /* Disable Regular OverSampling */
2195 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
2196 }
2197
2198 /* Set sampling time of the selected ADC channel */
2199 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
2200
2201 /* Configure the offset: offset enable/disable, channel, offset value */
2202
2203 /* Shift the offset with respect to the selected ADC resolution. */
2204 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
2205 #if defined(ADC_VER_V5_V90)
2206 if (hadc->Instance == ADC3)
2207 {
2208 tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
2209 }
2210 else
2211 #endif /* ADC_VER_V5_V90 */
2212 {
2213 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
2214 }
2215
2216 if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
2217 {
2218 /* Set ADC selected offset number */
2219 LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, tmpOffsetShifted);
2220
2221 #if defined(ADC_VER_V5_V90)
2222 if (hadc->Instance == ADC3)
2223 {
2224 /* Set ADC selected offset sign & saturation */
2225 LL_ADC_SetOffsetSign(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedOffsetSign);
2226 LL_ADC_SetOffsetSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
2227 }
2228 else
2229 #endif /* ADC_VER_V5_V90 */
2230 {
2231 /* Set ADC selected offset signed saturation */
2232 LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
2233 }
2234
2235 }
2236 else
2237 {
2238 #if defined(ADC_VER_V5_V90)
2239 if (hadc->Instance == ADC3)
2240 {
2241 /* Scan each offset register to check if the selected channel is targeted. */
2242 /* If this is the case, the corresponding offset number is disabled. */
2243 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
2244 {
2245 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
2246 }
2247 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
2248 {
2249 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
2250 }
2251 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
2252 {
2253 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
2254 }
2255 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
2256 {
2257 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
2258 }
2259 }
2260 else
2261 #endif /* ADC_VER_V5_V90 */
2262 {
2263 /* Scan each offset register to check if the selected channel is targeted. */
2264 /* If this is the case, the corresponding offset number is disabled. */
2265 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
2266 {
2267 LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
2268 }
2269 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
2270 {
2271 LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
2272 }
2273 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
2274 {
2275 LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
2276 }
2277 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
2278 {
2279 LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
2280 }
2281 }
2282 }
2283
2284 }
2285
2286 /* Parameters update conditioned to ADC state: */
2287 /* Parameters that can be updated only when ADC is disabled: */
2288 /* - Single or differential mode */
2289 /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
2290 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2291 {
2292 /* Set mode single-ended or differential input of the selected ADC channel */
2293 LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff);
2294
2295 /* Configuration of differential mode */
2296 /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
2297 if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
2298 {
2299 /* Set ADC channel preselection of corresponding negative channel */
2300 LL_ADC_SetChannelPreselection(hadc->Instance, ADC_CHANNEL_DIFF_NEG_INPUT(hadc, sConfigInjected->InjectedChannel));
2301 }
2302
2303 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
2304 /* internal measurement paths enable: If internal channel selected, */
2305 /* enable dedicated internal buffers and path. */
2306 /* Note: these internal measurement paths can be disabled using */
2307 /* HAL_ADC_DeInit(). */
2308
2309 if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
2310 {
2311 /* Configuration of common ADC parameters (continuation) */
2312 /* Software is allowed to change common parameters only when all ADCs */
2313 /* of the common group are disabled. */
2314 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2315 {
2316 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2317
2318 /* If the requested internal measurement path has already been enabled, */
2319 /* bypass the configuration processing. */
2320 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
2321 {
2322 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
2323 {
2324 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
2325
2326 /* Delay for temperature sensor stabilization time */
2327 /* Wait loop initialization and execution */
2328 /* Note: Variable divided by 2 to compensate partially */
2329 /* CPU processing cycles, scaling in us split to not */
2330 /* exceed 32 bits register capacity and handle low frequency. */
2331 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
2332 while (wait_loop_index != 0UL)
2333 {
2334 wait_loop_index--;
2335 }
2336 }
2337 }
2338 else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
2339 {
2340 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
2341 {
2342 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
2343 }
2344 }
2345 else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
2346 {
2347 if (ADC_VREFINT_INSTANCE(hadc))
2348 {
2349 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
2350 }
2351 }
2352 else
2353 {
2354 /* nothing to do */
2355 }
2356 }
2357 /* If the requested internal measurement path has already been enabled */
2358 /* and other ADC of the common group are enabled, internal */
2359 /* measurement paths cannot be enabled. */
2360 else
2361 {
2362 /* Update ADC state machine to error */
2363 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2364
2365 tmp_hal_status = HAL_ERROR;
2366 }
2367 }
2368
2369 }
2370
2371 /* Process unlocked */
2372 __HAL_UNLOCK(hadc);
2373
2374 /* Return function status */
2375 return tmp_hal_status;
2376 }
2377
2378 /**
2379 * @brief Enable ADC multimode and configure multimode parameters
2380 * @note Possibility to update parameters on the fly:
2381 * This function initializes multimode parameters, following
2382 * calls to this function can be used to reconfigure some parameters
2383 * of structure "ADC_MultiModeTypeDef" on the fly, without resetting
2384 * the ADCs.
2385 * The setting of these parameters is conditioned to ADC state.
2386 * For parameters constraints, see comments of structure
2387 * "ADC_MultiModeTypeDef".
2388 * @note To move back configuration from multimode to single mode, ADC must
2389 * be reset (using function HAL_ADC_Init() ).
2390 * @param hadc Master ADC handle
2391 * @param multimode Structure of ADC multimode configuration
2392 * @retval HAL status
2393 */
HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef * hadc,ADC_MultiModeTypeDef * multimode)2394 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
2395 {
2396 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2397 ADC_Common_TypeDef *tmpADC_Common;
2398 ADC_HandleTypeDef tmphadcSlave;
2399 uint32_t tmphadcSlave_conversion_on_going;
2400
2401 /* Check the parameters */
2402 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
2403 assert_param(IS_ADC_MULTIMODE(multimode->Mode));
2404 if (multimode->Mode != ADC_MODE_INDEPENDENT)
2405 {
2406 assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData));
2407 assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
2408 }
2409
2410 /* Process locked */
2411 __HAL_LOCK(hadc);
2412
2413 tmphadcSlave.State = HAL_ADC_STATE_RESET;
2414 tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
2415
2416 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
2417
2418 if (tmphadcSlave.Instance == NULL)
2419 {
2420 /* Update ADC state machine to error */
2421 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2422
2423 /* Process unlocked */
2424 __HAL_UNLOCK(hadc);
2425
2426 return HAL_ERROR;
2427 }
2428
2429 /* Parameters update conditioned to ADC state: */
2430 /* Parameters that can be updated when ADC is disabled or enabled without */
2431 /* conversion on going on regular group: */
2432 /* - Multimode DATA Format configuration */
2433 tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
2434 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2435 && (tmphadcSlave_conversion_on_going == 0UL))
2436 {
2437 /* Pointer to the common control register */
2438 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
2439
2440 /* If multimode is selected, configure all multimode parameters. */
2441 /* Otherwise, reset multimode parameters (can be used in case of */
2442 /* transition from multimode to independent mode). */
2443 if (multimode->Mode != ADC_MODE_INDEPENDENT)
2444 {
2445 MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
2446
2447 /* Parameters that can be updated only when ADC is disabled: */
2448 /* - Multimode mode selection */
2449 /* - Multimode delay */
2450 /* Note: Delay range depends on selected resolution: */
2451 /* from 1 to 9 clock cycles for 16 bits */
2452 /* from 1 to 9 clock cycles for 14 bits, */
2453 /* from 1 to 8 clock cycles for 12 bits */
2454 /* from 1 to 6 clock cycles for 10 and 8 bits */
2455 /* If a higher delay is selected, it will be clipped to maximum delay */
2456 /* range */
2457
2458 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2459 {
2460 MODIFY_REG(tmpADC_Common->CCR,
2461 ADC_CCR_DUAL |
2462 ADC_CCR_DELAY,
2463 multimode->Mode |
2464 multimode->TwoSamplingDelay
2465 );
2466 }
2467 }
2468 else /* ADC_MODE_INDEPENDENT */
2469 {
2470 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF);
2471
2472 /* Parameters that can be updated only when ADC is disabled: */
2473 /* - Multimode mode selection */
2474 /* - Multimode delay */
2475 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2476 {
2477 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
2478 }
2479 }
2480 }
2481 /* If one of the ADC sharing the same common group is enabled, no update */
2482 /* could be done on neither of the multimode structure parameters. */
2483 else
2484 {
2485 /* Update ADC state machine to error */
2486 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2487
2488 tmp_hal_status = HAL_ERROR;
2489 }
2490
2491 /* Process unlocked */
2492 __HAL_UNLOCK(hadc);
2493
2494 /* Return function status */
2495 return tmp_hal_status;
2496 }
2497
2498 /**
2499 * @brief Enable Injected Queue
2500 * @note This function resets CFGR register JQDIS bit in order to enable the
2501 * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
2502 * are both equal to 0 to ensure that no regular nor injected
2503 * conversion is ongoing.
2504 * @param hadc ADC handle
2505 * @retval HAL status
2506 */
HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef * hadc)2507 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
2508 {
2509 HAL_StatusTypeDef tmp_hal_status;
2510 uint32_t tmp_adc_is_conversion_on_going_regular;
2511 uint32_t tmp_adc_is_conversion_on_going_injected;
2512
2513 /* Check the parameters */
2514 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2515
2516 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2517 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2518
2519 /* Parameter can be set only if no conversion is on-going */
2520 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2521 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2522 )
2523 {
2524 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
2525
2526 /* Update state, clear previous result related to injected queue overflow */
2527 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
2528
2529 tmp_hal_status = HAL_OK;
2530 }
2531 else
2532 {
2533 tmp_hal_status = HAL_ERROR;
2534 }
2535
2536 return tmp_hal_status;
2537 }
2538
2539 /**
2540 * @brief Disable Injected Queue
2541 * @note This function sets CFGR register JQDIS bit in order to disable the
2542 * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
2543 * are both equal to 0 to ensure that no regular nor injected
2544 * conversion is ongoing.
2545 * @param hadc ADC handle
2546 * @retval HAL status
2547 */
HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef * hadc)2548 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
2549 {
2550 HAL_StatusTypeDef tmp_hal_status;
2551 uint32_t tmp_adc_is_conversion_on_going_regular;
2552 uint32_t tmp_adc_is_conversion_on_going_injected;
2553
2554 /* Check the parameters */
2555 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2556
2557 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2558 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2559
2560 /* Parameter can be set only if no conversion is on-going */
2561 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2562 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2563 )
2564 {
2565 LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
2566 tmp_hal_status = HAL_OK;
2567 }
2568 else
2569 {
2570 tmp_hal_status = HAL_ERROR;
2571 }
2572
2573 return tmp_hal_status;
2574 }
2575
2576 /**
2577 * @brief Disable ADC voltage regulator.
2578 * @note Disabling voltage regulator allows to save power. This operation can
2579 * be carried out only when ADC is disabled.
2580 * @note To enable again the voltage regulator, the user is expected to
2581 * resort to HAL_ADC_Init() API.
2582 * @param hadc ADC handle
2583 * @retval HAL status
2584 */
HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef * hadc)2585 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
2586 {
2587 HAL_StatusTypeDef tmp_hal_status;
2588
2589 /* Check the parameters */
2590 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2591
2592 /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
2593 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2594 {
2595 LL_ADC_DisableInternalRegulator(hadc->Instance);
2596 tmp_hal_status = HAL_OK;
2597 }
2598 else
2599 {
2600 tmp_hal_status = HAL_ERROR;
2601 }
2602
2603 return tmp_hal_status;
2604 }
2605
2606 /**
2607 * @brief Enter ADC deep-power-down mode
2608 * @note This mode is achieved in setting DEEPPWD bit and allows to save power
2609 * in reducing leakage currents. It is particularly interesting before
2610 * entering stop modes.
2611 * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
2612 * ADC voltage regulator. This means that this API encompasses
2613 * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
2614 * calibration is lost.
2615 * @note To exit the ADC deep-power-down mode, the user is expected to
2616 * resort to HAL_ADC_Init() API as well as to relaunch a calibration
2617 * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
2618 * saved calibration factor.
2619 * @param hadc ADC handle
2620 * @retval HAL status
2621 */
HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef * hadc)2622 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
2623 {
2624 HAL_StatusTypeDef tmp_hal_status;
2625
2626 /* Check the parameters */
2627 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2628
2629 /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
2630 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2631 {
2632 LL_ADC_EnableDeepPowerDown(hadc->Instance);
2633 tmp_hal_status = HAL_OK;
2634 }
2635 else
2636 {
2637 tmp_hal_status = HAL_ERROR;
2638 }
2639
2640 return tmp_hal_status;
2641 }
2642
2643 /**
2644 * @}
2645 */
2646
2647 /**
2648 * @}
2649 */
2650
2651 #endif /* HAL_ADC_MODULE_ENABLED */
2652 /**
2653 * @}
2654 */
2655
2656 /**
2657 * @}
2658 */
2659
2660
