1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_fmc.c
4 * @author MCD Application Team
5 * @brief FMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2022 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### FMC peripheral features #####
27 ==============================================================================
28 [..] The Flexible memory controller (FMC) includes following memory controllers:
29 (+) The NOR/PSRAM memory controller
30 (+) The NAND memory controller
31 (+) The Synchronous DRAM (SDRAM) controller
32
33 [..] The FMC functional block makes the interface with synchronous and asynchronous static
34 memories and SDRAM memories. Its main purposes are:
35 (+) to translate AHB transactions into the appropriate external device protocol
36 (+) to meet the access time requirements of the external memory devices
37
38 [..] All external memories share the addresses, data and control signals with the controller.
39 Each external device is accessed by means of a unique Chip Select. The FMC performs
40 only one access at a time to an external device.
41 The main features of the FMC controller are the following:
42 (+) Interface with static-memory mapped devices including:
43 (++) Static random access memory (SRAM)
44 (++) Read-only memory (ROM)
45 (++) NOR Flash memory/OneNAND Flash memory
46 (++) PSRAM (4 memory banks)
47 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
48 data
49 (+) Interface with synchronous DRAM (SDRAM) memories
50 (+) Independent Chip Select control for each memory bank
51 (+) Independent configuration for each memory bank
52
53 @endverbatim
54 ******************************************************************************
55 */
56
57 /* Includes ------------------------------------------------------------------*/
58 #include "stm32h7rsxx_hal.h"
59
60 /** @addtogroup STM32H7RSxx_HAL_Driver
61 * @{
62 */
63 #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\
64 || defined(HAL_SRAM_MODULE_ENABLED)
65
66 /** @defgroup FMC_LL FMC Low Layer
67 * @brief FMC driver modules
68 * @{
69 */
70
71 /* Private typedef -----------------------------------------------------------*/
72 /* Private define ------------------------------------------------------------*/
73
74 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
75 * @{
76 */
77
78 /* ----------------------- FMC registers bit mask --------------------------- */
79
80 /* --- BCR Register ---*/
81 /* BCR register clear mask */
82
83 /* --- BTR Register ---*/
84 /* BTR register clear mask */
85 #define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
86 FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
87 FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
88 FMC_BTRx_ACCMOD))
89
90 /* --- BWTR Register ---*/
91 /* BWTR register clear mask */
92 #if defined(FMC_BWTRx_BUSTURN)
93 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
94 FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
95 FMC_BWTRx_ACCMOD))
96 #else
97 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
98 FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD))
99 #endif /* FMC_BWTRx_BUSTURN */
100
101 /* --- PCR Register ---*/
102 /* PCR register clear mask */
103 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
104 FMC_PCR_PWID | FMC_PCR_ECCEN | \
105 FMC_PCR_TCLR | FMC_PCR_TAR | \
106 FMC_PCR_ECCPS))
107 /* --- PMEM Register ---*/
108 /* PMEM register clear mask */
109 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\
110 FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ))
111
112 /* --- PATT Register ---*/
113 /* PATT register clear mask */
114 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\
115 FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ))
116
117
118 /* --- SDCR Register ---*/
119 /* SDCR register clear mask */
120 #define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCRx_NC | FMC_SDCRx_NR | \
121 FMC_SDCRx_MWID | FMC_SDCRx_NB | \
122 FMC_SDCRx_CAS | FMC_SDCRx_WP | \
123 FMC_SDCRx_SDCLK | FMC_SDCRx_RBURST | \
124 FMC_SDCRx_RPIPE))
125
126 /* --- SDTR Register ---*/
127 /* SDTR register clear mask */
128 #define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTRx_TMRD | FMC_SDTRx_TXSR | \
129 FMC_SDTRx_TRAS | FMC_SDTRx_TRC | \
130 FMC_SDTRx_TWR | FMC_SDTRx_TRP | \
131 FMC_SDTRx_TRCD))
132
133 /**
134 * @}
135 */
136
137 /* Private macro -------------------------------------------------------------*/
138 /* Private variables ---------------------------------------------------------*/
139 /* Private function prototypes -----------------------------------------------*/
140 /* Exported functions --------------------------------------------------------*/
141
142 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
143 * @{
144 */
145
146
147 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
148 * @brief NORSRAM Controller functions
149 *
150 @verbatim
151 ==============================================================================
152 ##### How to use NORSRAM device driver #####
153 ==============================================================================
154
155 [..]
156 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
157 to run the NORSRAM external devices.
158
159 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
160 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
161 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
162 (+) FMC NORSRAM bank extended timing configuration using the function
163 FMC_NORSRAM_Extended_Timing_Init()
164 (+) FMC NORSRAM bank enable/disable write operation using the functions
165 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
166
167 @endverbatim
168 * @{
169 */
170
171 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
172 * @brief Initialization and Configuration functions
173 *
174 @verbatim
175 ==============================================================================
176 ##### Initialization and de_initialization functions #####
177 ==============================================================================
178 [..]
179 This section provides functions allowing to:
180 (+) Initialize and configure the FMC NORSRAM interface
181 (+) De-initialize the FMC NORSRAM interface
182 (+) Configure the FMC clock and associated GPIOs
183
184 @endverbatim
185 * @{
186 */
187
188 /**
189 * @brief Initialize the FMC_NORSRAM device according to the specified
190 * control parameters in the FMC_NORSRAM_InitTypeDef
191 * @param Device Pointer to NORSRAM device instance
192 * @param Init Pointer to NORSRAM Initialization structure
193 * @retval HAL status
194 */
FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef * Device,const FMC_NORSRAM_InitTypeDef * Init)195 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
196 const FMC_NORSRAM_InitTypeDef *Init)
197 {
198 uint32_t flashaccess;
199 uint32_t btcr_reg;
200 uint32_t mask;
201
202 /* Check the parameters */
203 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
204 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
205 assert_param(IS_FMC_MUX(Init->DataAddressMux));
206 assert_param(IS_FMC_MEMORY(Init->MemoryType));
207 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
208 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
209 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
210 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
211 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
212 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
213 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
214 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
215 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
216 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
217 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
218 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
219
220 /* Disable NORSRAM Device */
221 __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
222
223 /* Set NORSRAM device control parameters */
224 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
225 {
226 flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
227 }
228 else
229 {
230 flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
231 }
232
233 btcr_reg = (flashaccess | \
234 Init->DataAddressMux | \
235 Init->MemoryType | \
236 Init->MemoryDataWidth | \
237 Init->BurstAccessMode | \
238 Init->WaitSignalPolarity | \
239 Init->WaitSignalActive | \
240 Init->WriteOperation | \
241 Init->WaitSignal | \
242 Init->ExtendedMode | \
243 Init->AsynchronousWait | \
244 Init->WriteBurst);
245
246 btcr_reg |= Init->ContinuousClock;
247 btcr_reg |= Init->WriteFifo;
248 btcr_reg |= Init->PageSize;
249
250 mask = (FMC_BCRx_MBKEN |
251 FMC_BCRx_MUXEN |
252 FMC_BCRx_MTYP |
253 FMC_BCRx_MWID |
254 FMC_BCRx_FACCEN |
255 FMC_BCRx_BURSTEN |
256 FMC_BCRx_WAITPOL |
257 FMC_BCRx_WAITCFG |
258 FMC_BCRx_WREN |
259 FMC_BCRx_WAITEN |
260 FMC_BCRx_EXTMOD |
261 FMC_BCRx_ASYNCWAIT |
262 FMC_BCRx_CBURSTRW);
263
264 mask |= FMC_BCR1_CCLKEN;
265 mask |= FMC_BCR1_WFDIS;
266 mask |= FMC_BCRx_CPSIZE;
267
268 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
269
270 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
271 if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
272 {
273 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
274 }
275
276 if (Init->NSBank != FMC_NORSRAM_BANK1)
277 {
278 /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
279 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
280 }
281
282 return HAL_OK;
283 }
284
285 /**
286 * @brief DeInitialize the FMC_NORSRAM peripheral
287 * @param Device Pointer to NORSRAM device instance
288 * @param ExDevice Pointer to NORSRAM extended mode device instance
289 * @param Bank NORSRAM bank number
290 * @retval HAL status
291 */
FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)292 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
293 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
294 {
295 /* Check the parameters */
296 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
297 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
298 assert_param(IS_FMC_NORSRAM_BANK(Bank));
299
300 /* Disable the FMC_NORSRAM device */
301 __FMC_NORSRAM_DISABLE(Device, Bank);
302
303 /* De-initialize the FMC_NORSRAM device */
304 /* FMC_NORSRAM_BANK1 */
305 if (Bank == FMC_NORSRAM_BANK1)
306 {
307 Device->BTCR[Bank] = 0x000030DBU;
308 }
309 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
310 else
311 {
312 Device->BTCR[Bank] = 0x000030D2U;
313 }
314
315 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
316 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
317
318 return HAL_OK;
319 }
320
321 /**
322 * @brief Initialize the FMC_NORSRAM Timing according to the specified
323 * parameters in the FMC_NORSRAM_TimingTypeDef
324 * @param Device Pointer to NORSRAM device instance
325 * @param Timing Pointer to NORSRAM Timing structure
326 * @param Bank NORSRAM bank number
327 * @retval HAL status
328 */
FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef * Device,const FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)329 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
330 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
331 {
332 uint32_t tmpr;
333
334 /* Check the parameters */
335 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
336 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
337 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
338 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
339 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
340 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
341 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
342 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
343 assert_param(IS_FMC_NORSRAM_BANK(Bank));
344
345 /* Set FMC_NORSRAM device timing parameters */
346 Device->BTCR[Bank + 1U] =
347 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) |
348 (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) |
349 (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) |
350 (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) |
351 ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) |
352 ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) |
353 Timing->AccessMode;
354
355 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
356 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
357 {
358 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));
359 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos);
360 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);
361 }
362
363 return HAL_OK;
364 }
365
366 /**
367 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
368 * parameters in the FMC_NORSRAM_TimingTypeDef
369 * @param Device Pointer to NORSRAM device instance
370 * @param Timing Pointer to NORSRAM Timing structure
371 * @param Bank NORSRAM bank number
372 * @param ExtendedMode FMC Extended Mode
373 * This parameter can be one of the following values:
374 * @arg FMC_EXTENDED_MODE_DISABLE
375 * @arg FMC_EXTENDED_MODE_ENABLE
376 * @retval HAL status
377 */
FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef * Device,const FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)378 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
379 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
380 uint32_t ExtendedMode)
381 {
382 /* Check the parameters */
383 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
384
385 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
386 if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
387 {
388 /* Check the parameters */
389 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
390 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
391 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
392 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
393 #if defined(FMC_BWTRx_BUSTURN)
394 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
395 #endif /* FMC_BWTRx_BUSTURN */
396 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
397 assert_param(IS_FMC_NORSRAM_BANK(Bank));
398
399 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
400 #if defined(FMC_BWTRx_BUSTURN)
401 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
402 ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) |
403 ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) |
404 Timing->AccessMode |
405 ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos)));
406 #else /* FMC_BWTRx_BUSTURN */
407 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
408 ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) |
409 ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) |
410 Timing->AccessMode));
411 #endif /* FMC_BWTRx_BUSTURN */
412 }
413 else
414 {
415 Device->BWTR[Bank] = 0x0FFFFFFFU;
416 }
417
418 return HAL_OK;
419 }
420 /**
421 * @}
422 */
423
424 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
425 * @brief management functions
426 *
427 @verbatim
428 ==============================================================================
429 ##### FMC_NORSRAM Control functions #####
430 ==============================================================================
431 [..]
432 This subsection provides a set of functions allowing to control dynamically
433 the FMC NORSRAM interface.
434
435 @endverbatim
436 * @{
437 */
438
439 /**
440 * @brief Enables dynamically FMC_NORSRAM write operation.
441 * @param Device Pointer to NORSRAM device instance
442 * @param Bank NORSRAM bank number
443 * @retval HAL status
444 */
FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)445 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
446 {
447 /* Check the parameters */
448 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
449 assert_param(IS_FMC_NORSRAM_BANK(Bank));
450
451 /* Enable write operation */
452 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
453
454 return HAL_OK;
455 }
456
457 /**
458 * @brief Disables dynamically FMC_NORSRAM write operation.
459 * @param Device Pointer to NORSRAM device instance
460 * @param Bank NORSRAM bank number
461 * @retval HAL status
462 */
FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)463 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
464 {
465 /* Check the parameters */
466 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
467 assert_param(IS_FMC_NORSRAM_BANK(Bank));
468
469 /* Disable write operation */
470 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
471
472 return HAL_OK;
473 }
474
475 /**
476 * @}
477 */
478
479 /**
480 * @}
481 */
482
483
484 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
485 * @brief NAND Controller functions
486 *
487 @verbatim
488 ==============================================================================
489 ##### How to use NAND device driver #####
490 ==============================================================================
491 [..]
492 This driver contains a set of APIs to interface with the FMC NAND banks in order
493 to run the NAND external devices.
494
495 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
496 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
497 (+) FMC NAND bank common space timing configuration using the function
498 FMC_NAND_CommonSpace_Timing_Init()
499 (+) FMC NAND bank attribute space timing configuration using the function
500 FMC_NAND_AttributeSpace_Timing_Init()
501 (+) FMC NAND bank enable/disable ECC correction feature using the functions
502 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
503 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
504
505 @endverbatim
506 * @{
507 */
508
509 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
510 * @brief Initialization and Configuration functions
511 *
512 @verbatim
513 ==============================================================================
514 ##### Initialization and de_initialization functions #####
515 ==============================================================================
516 [..]
517 This section provides functions allowing to:
518 (+) Initialize and configure the FMC NAND interface
519 (+) De-initialize the FMC NAND interface
520 (+) Configure the FMC clock and associated GPIOs
521
522 @endverbatim
523 * @{
524 */
525
526 /**
527 * @brief Initializes the FMC_NAND device according to the specified
528 * control parameters in the FMC_NAND_HandleTypeDef
529 * @param Device Pointer to NAND device instance
530 * @param Init Pointer to NAND Initialization structure
531 * @retval HAL status
532 */
FMC_NAND_Init(FMC_NAND_TypeDef * Device,const FMC_NAND_InitTypeDef * Init)533 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init)
534 {
535 /* Check the parameters */
536 assert_param(IS_FMC_NAND_DEVICE(Device));
537 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
538 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
539 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
540 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
541 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
542 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
543 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
544
545 /* NAND bank 3 registers configuration */
546 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |
547 FMC_PCR_MEMORY_TYPE_NAND |
548 Init->MemoryDataWidth |
549 Init->EccComputation |
550 Init->ECCPageSize |
551 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) |
552 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos)));
553
554 return HAL_OK;
555 }
556
557 /**
558 * @brief Initializes the FMC_NAND Common space Timing according to the specified
559 * parameters in the FMC_NAND_PCC_TimingTypeDef
560 * @param Device Pointer to NAND device instance
561 * @param Timing Pointer to NAND timing structure
562 * @param Bank NAND bank number
563 * @retval HAL status
564 */
FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef * Device,const FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)565 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
566 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
567 {
568 /* Check the parameters */
569 assert_param(IS_FMC_NAND_DEVICE(Device));
570 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
571 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
572 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
573 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
574 assert_param(IS_FMC_NAND_BANK(Bank));
575
576 /* Prevent unused argument(s) compilation warning if no assert_param check */
577 UNUSED(Bank);
578
579 /* NAND bank 3 registers configuration */
580 Device->PMEM = (Timing->SetupTime |
581 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
582 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
583 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos));
584
585 return HAL_OK;
586 }
587
588 /**
589 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
590 * parameters in the FMC_NAND_PCC_TimingTypeDef
591 * @param Device Pointer to NAND device instance
592 * @param Timing Pointer to NAND timing structure
593 * @param Bank NAND bank number
594 * @retval HAL status
595 */
FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef * Device,const FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)596 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
597 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
598 {
599 /* Check the parameters */
600 assert_param(IS_FMC_NAND_DEVICE(Device));
601 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
602 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
603 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
604 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
605 assert_param(IS_FMC_NAND_BANK(Bank));
606
607 /* Prevent unused argument(s) compilation warning if no assert_param check */
608 UNUSED(Bank);
609
610 /* NAND bank 3 registers configuration */
611 Device->PATT = (Timing->SetupTime |
612 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
613 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
614 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos));
615
616 return HAL_OK;
617 }
618
619 /**
620 * @brief DeInitializes the FMC_NAND device
621 * @param Device Pointer to NAND device instance
622 * @param Bank NAND bank number
623 * @retval HAL status
624 */
FMC_NAND_DeInit(FMC_NAND_TypeDef * Device,uint32_t Bank)625 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
626 {
627 /* Check the parameters */
628 assert_param(IS_FMC_NAND_DEVICE(Device));
629 assert_param(IS_FMC_NAND_BANK(Bank));
630
631 /* Disable the NAND Bank */
632 __FMC_NAND_DISABLE(Device, Bank);
633
634 /* De-initialize the NAND Bank */
635 /* Prevent unused argument(s) compilation warning if no assert_param check */
636 UNUSED(Bank);
637
638 /* Set the FMC_NAND_BANK3 registers to their reset values */
639 WRITE_REG(Device->PCR, 0x00000018U);
640 WRITE_REG(Device->SR, 0x00000040U);
641 WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
642 WRITE_REG(Device->PATT, 0xFCFCFCFCU);
643
644 return HAL_OK;
645 }
646
647 /**
648 * @}
649 */
650
651 /** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
652 * @brief management functions
653 *
654 @verbatim
655 ==============================================================================
656 ##### FMC_NAND Control functions #####
657 ==============================================================================
658 [..]
659 This subsection provides a set of functions allowing to control dynamically
660 the FMC NAND interface.
661
662 @endverbatim
663 * @{
664 */
665
666
667 /**
668 * @brief Enables dynamically FMC_NAND ECC feature.
669 * @param Device Pointer to NAND device instance
670 * @param Bank NAND bank number
671 * @retval HAL status
672 */
FMC_NAND_ECC_Enable(FMC_NAND_TypeDef * Device,uint32_t Bank)673 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
674 {
675 /* Check the parameters */
676 assert_param(IS_FMC_NAND_DEVICE(Device));
677 assert_param(IS_FMC_NAND_BANK(Bank));
678
679 /* Enable ECC feature */
680 /* Prevent unused argument(s) compilation warning if no assert_param check */
681 UNUSED(Bank);
682
683 SET_BIT(Device->PCR, FMC_PCR_ECCEN);
684
685 return HAL_OK;
686 }
687
688
689 /**
690 * @brief Disables dynamically FMC_NAND ECC feature.
691 * @param Device Pointer to NAND device instance
692 * @param Bank NAND bank number
693 * @retval HAL status
694 */
FMC_NAND_ECC_Disable(FMC_NAND_TypeDef * Device,uint32_t Bank)695 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
696 {
697 /* Check the parameters */
698 assert_param(IS_FMC_NAND_DEVICE(Device));
699 assert_param(IS_FMC_NAND_BANK(Bank));
700
701 /* Disable ECC feature */
702 /* Prevent unused argument(s) compilation warning if no assert_param check */
703 UNUSED(Bank);
704
705 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
706
707 return HAL_OK;
708 }
709
710 /**
711 * @brief Disables dynamically FMC_NAND ECC feature.
712 * @param Device Pointer to NAND device instance
713 * @param ECCval Pointer to ECC value
714 * @param Bank NAND bank number
715 * @param Timeout Timeout wait value
716 * @retval HAL status
717 */
FMC_NAND_GetECC(const FMC_NAND_TypeDef * Device,uint32_t * ECCval,uint32_t Bank,uint32_t Timeout)718 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
719 uint32_t Timeout)
720 {
721 uint32_t tickstart;
722
723 /* Check the parameters */
724 assert_param(IS_FMC_NAND_DEVICE(Device));
725 assert_param(IS_FMC_NAND_BANK(Bank));
726
727 /* Get tick */
728 tickstart = HAL_GetTick();
729
730 /* Wait until FIFO is empty */
731 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
732 {
733 /* Check for the Timeout */
734 if (Timeout != HAL_MAX_DELAY)
735 {
736 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
737 {
738 return HAL_TIMEOUT;
739 }
740 }
741 }
742
743 /* Prevent unused argument(s) compilation warning if no assert_param check */
744 UNUSED(Bank);
745
746 /* Get the ECCR register value */
747 *ECCval = (uint32_t)Device->ECCR;
748
749 return HAL_OK;
750 }
751
752 /**
753 * @}
754 */
755
756
757 /** @defgroup FMC_LL_SDRAM
758 * @brief SDRAM Controller functions
759 *
760 @verbatim
761 ==============================================================================
762 ##### How to use SDRAM device driver #####
763 ==============================================================================
764 [..]
765 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
766 to run the SDRAM external devices.
767
768 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
769 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
770 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
771 (+) FMC SDRAM bank enable/disable write operation using the functions
772 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
773 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
774
775 @endverbatim
776 * @{
777 */
778
779 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
780 * @brief Initialization and Configuration functions
781 *
782 @verbatim
783 ==============================================================================
784 ##### Initialization and de_initialization functions #####
785 ==============================================================================
786 [..]
787 This section provides functions allowing to:
788 (+) Initialize and configure the FMC SDRAM interface
789 (+) De-initialize the FMC SDRAM interface
790 (+) Configure the FMC clock and associated GPIOs
791
792 @endverbatim
793 * @{
794 */
795
796 /**
797 * @brief Initializes the FMC_SDRAM device according to the specified
798 * control parameters in the FMC_SDRAM_InitTypeDef
799 * @param Device Pointer to SDRAM device instance
800 * @param Init Pointer to SDRAM Initialization structure
801 * @retval HAL status
802 */
FMC_SDRAM_Init(FMC_SDRAM_TypeDef * Device,const FMC_SDRAM_InitTypeDef * Init)803 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init)
804 {
805 /* Check the parameters */
806 assert_param(IS_FMC_SDRAM_DEVICE(Device));
807 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
808 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
809 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
810 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
811 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
812 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
813 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
814 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
815 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
816 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
817
818 /* Set SDRAM bank configuration parameters */
819 if (Init->SDBank == FMC_SDRAM_BANK1)
820 {
821 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
822 SDCR_CLEAR_MASK,
823 (Init->ColumnBitsNumber |
824 Init->RowBitsNumber |
825 Init->MemoryDataWidth |
826 Init->InternalBankNumber |
827 Init->CASLatency |
828 Init->WriteProtection |
829 Init->SDClockPeriod |
830 Init->ReadBurst |
831 Init->ReadPipeDelay));
832 }
833 else /* FMC_Bank2_SDRAM */
834 {
835 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
836 FMC_SDCRx_SDCLK |
837 FMC_SDCRx_RBURST |
838 FMC_SDCRx_RPIPE,
839 (Init->SDClockPeriod |
840 Init->ReadBurst |
841 Init->ReadPipeDelay));
842
843 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
844 SDCR_CLEAR_MASK,
845 (Init->ColumnBitsNumber |
846 Init->RowBitsNumber |
847 Init->MemoryDataWidth |
848 Init->InternalBankNumber |
849 Init->CASLatency |
850 Init->WriteProtection));
851 }
852
853 return HAL_OK;
854 }
855
856
857 /**
858 * @brief Initializes the FMC_SDRAM device timing according to the specified
859 * parameters in the FMC_SDRAM_TimingTypeDef
860 * @param Device Pointer to SDRAM device instance
861 * @param Timing Pointer to SDRAM Timing structure
862 * @param Bank SDRAM bank number
863 * @retval HAL status
864 */
FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef * Device,const FMC_SDRAM_TimingTypeDef * Timing,uint32_t Bank)865 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
866 const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
867 {
868 /* Check the parameters */
869 assert_param(IS_FMC_SDRAM_DEVICE(Device));
870 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
871 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
872 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
873 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
874 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
875 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
876 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
877 assert_param(IS_FMC_SDRAM_BANK(Bank));
878
879 /* Set SDRAM device timing parameters */
880 if (Bank == FMC_SDRAM_BANK1)
881 {
882 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
883 SDTR_CLEAR_MASK,
884 (((Timing->LoadToActiveDelay) - 1U) |
885 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) |
886 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) |
887 (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) |
888 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) |
889 (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos) |
890 (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos)));
891 }
892 else /* FMC_Bank2_SDRAM */
893 {
894 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
895 FMC_SDTRx_TRC |
896 FMC_SDTRx_TRP,
897 (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) |
898 (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos));
899
900 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
901 SDTR_CLEAR_MASK,
902 (((Timing->LoadToActiveDelay) - 1U) |
903 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) |
904 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) |
905 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) |
906 (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos)));
907 }
908
909 return HAL_OK;
910 }
911
912 /**
913 * @brief DeInitializes the FMC_SDRAM peripheral
914 * @param Device Pointer to SDRAM device instance
915 * @retval HAL status
916 */
FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef * Device,uint32_t Bank)917 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
918 {
919 /* Check the parameters */
920 assert_param(IS_FMC_SDRAM_DEVICE(Device));
921 assert_param(IS_FMC_SDRAM_BANK(Bank));
922
923 /* De-initialize the SDRAM device */
924 Device->SDCR[Bank] = 0x000002D0U;
925 Device->SDTR[Bank] = 0x0FFFFFFFU;
926 Device->SDCMR = 0x00000000U;
927 Device->SDRTR = 0x00000000U;
928 Device->SDSR = 0x00000000U;
929
930 return HAL_OK;
931 }
932
933 /**
934 * @}
935 */
936
937 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
938 * @brief management functions
939 *
940 @verbatim
941 ==============================================================================
942 ##### FMC_SDRAM Control functions #####
943 ==============================================================================
944 [..]
945 This subsection provides a set of functions allowing to control dynamically
946 the FMC SDRAM interface.
947
948 @endverbatim
949 * @{
950 */
951
952 /**
953 * @brief Enables dynamically FMC_SDRAM write protection.
954 * @param Device Pointer to SDRAM device instance
955 * @param Bank SDRAM bank number
956 * @retval HAL status
957 */
FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)958 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
959 {
960 /* Check the parameters */
961 assert_param(IS_FMC_SDRAM_DEVICE(Device));
962 assert_param(IS_FMC_SDRAM_BANK(Bank));
963
964 /* Enable write protection */
965 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
966
967 return HAL_OK;
968 }
969
970 /**
971 * @brief Disables dynamically FMC_SDRAM write protection.
972 * @param hsdram FMC_SDRAM handle
973 * @retval HAL status
974 */
FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)975 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
976 {
977 /* Check the parameters */
978 assert_param(IS_FMC_SDRAM_DEVICE(Device));
979 assert_param(IS_FMC_SDRAM_BANK(Bank));
980
981 /* Disable write protection */
982 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
983
984 return HAL_OK;
985 }
986
987 /**
988 * @brief Send Command to the FMC SDRAM bank
989 * @param Device Pointer to SDRAM device instance
990 * @param Command Pointer to SDRAM command structure
991 * @param Timing Pointer to SDRAM Timing structure
992 * @param Timeout Timeout wait value
993 * @retval HAL state
994 */
FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef * Device,const FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)995 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
996 const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
997 {
998 /* Check the parameters */
999 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1000 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
1001 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
1002 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
1003 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
1004
1005 /* Set command register */
1006 MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
1007 ((Command->CommandMode) | (Command->CommandTarget) |
1008 (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
1009 ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
1010 /* Prevent unused argument(s) compilation warning */
1011 UNUSED(Timeout);
1012 return HAL_OK;
1013 }
1014
1015 /**
1016 * @brief Program the SDRAM Memory Refresh rate.
1017 * @param Device Pointer to SDRAM device instance
1018 * @param RefreshRate The SDRAM refresh rate value.
1019 * @retval HAL state
1020 */
FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef * Device,uint32_t RefreshRate)1021 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1022 {
1023 /* Check the parameters */
1024 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1025 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1026
1027 /* Set the refresh rate in command register */
1028 MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));
1029
1030 return HAL_OK;
1031 }
1032
1033 /**
1034 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
1035 * @param Device Pointer to SDRAM device instance
1036 * @param AutoRefreshNumber Specifies the auto Refresh number.
1037 * @retval None
1038 */
FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef * Device,uint32_t AutoRefreshNumber)1039 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
1040 uint32_t AutoRefreshNumber)
1041 {
1042 /* Check the parameters */
1043 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1044 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1045
1046 /* Set the Auto-refresh number in command register */
1047 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
1048
1049 return HAL_OK;
1050 }
1051
1052 /**
1053 * @brief Returns the indicated FMC SDRAM bank mode status.
1054 * @param Device Pointer to SDRAM device instance
1055 * @param Bank Defines the FMC SDRAM bank. This parameter can be
1056 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1057 * @retval The FMC SDRAM bank mode status, could be on of the following values:
1058 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1059 * FMC_SDRAM_POWER_DOWN_MODE.
1060 */
FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef * Device,uint32_t Bank)1061 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1062 {
1063 uint32_t tmpreg;
1064
1065 /* Check the parameters */
1066 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1067 assert_param(IS_FMC_SDRAM_BANK(Bank));
1068
1069 /* Get the corresponding bank mode */
1070 if (Bank == FMC_SDRAM_BANK1)
1071 {
1072 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1073 }
1074 else
1075 {
1076 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
1077 }
1078
1079 /* Return the mode status */
1080 return tmpreg;
1081 }
1082
1083 /**
1084 * @}
1085 */
1086
1087 /**
1088 * @}
1089 */
1090
1091
1092 /**
1093 * @}
1094 */
1095
1096 /**
1097 * @}
1098 */
1099
1100 #endif /* HAL_NOR_MODULE_ENABLED */
1101 /**
1102 * @}
1103 */
1104 /**
1105 * @}
1106 */
1107
