1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### LL DMA driver acronyms #####
20 ==============================================================================
21 [..] Acronyms table :
22 =========================================
23 || Acronym || ||
24 =========================================
25 || SRC || Source ||
26 || DEST || Destination ||
27 || ADDR || Address ||
28 || ADDRS || Addresses ||
29 || INC || Increment / Incremented ||
30 || DEC || Decrement / Decremented ||
31 || BLK || Block ||
32 || RPT || Repeat / Repeated ||
33 || TRIG || Trigger ||
34 =========================================
35 @endverbatim
36 ******************************************************************************
37 */
38
39 #if defined (USE_FULL_LL_DRIVER)
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32h7rsxx_ll_dma.h"
43 #include "stm32h7rsxx_ll_bus.h"
44 #ifdef USE_FULL_ASSERT
45 #include "stm32_assert.h"
46 #else
47 #define assert_param(expr) ((void)0U)
48 #endif /* USE_FULL_ASSERT */
49
50 /** @addtogroup STM32H7RSxx_LL_Driver
51 * @{
52 */
53
54 #if (defined (GPDMA1) || defined (HPDMA1))
55
56 /** @addtogroup DMA_LL
57 * @{
58 */
59
60 /* Private types -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62 /* Private constants ---------------------------------------------------------*/
63 /* Private macros ------------------------------------------------------------*/
64
65 /** @addtogroup DMA_LL_Private_Macros
66 * @{
67 */
68 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == HPDMA1) && \
69 (((Channel) == LL_DMA_CHANNEL_0) || \
70 ((Channel) == LL_DMA_CHANNEL_1) || \
71 ((Channel) == LL_DMA_CHANNEL_2) || \
72 ((Channel) == LL_DMA_CHANNEL_3) || \
73 ((Channel) == LL_DMA_CHANNEL_4) || \
74 ((Channel) == LL_DMA_CHANNEL_5) || \
75 ((Channel) == LL_DMA_CHANNEL_6) || \
76 ((Channel) == LL_DMA_CHANNEL_7) || \
77 ((Channel) == LL_DMA_CHANNEL_8) || \
78 ((Channel) == LL_DMA_CHANNEL_9) || \
79 ((Channel) == LL_DMA_CHANNEL_10) || \
80 ((Channel) == LL_DMA_CHANNEL_11) || \
81 ((Channel) == LL_DMA_CHANNEL_12) || \
82 ((Channel) == LL_DMA_CHANNEL_13) || \
83 ((Channel) == LL_DMA_CHANNEL_14) || \
84 ((Channel) == LL_DMA_CHANNEL_15) || \
85 ((Channel) == LL_DMA_CHANNEL_ALL))) || \
86 (((INSTANCE) == GPDMA1) && \
87 (((Channel) == LL_DMA_CHANNEL_0) || \
88 ((Channel) == LL_DMA_CHANNEL_1) || \
89 ((Channel) == LL_DMA_CHANNEL_2) || \
90 ((Channel) == LL_DMA_CHANNEL_3) || \
91 ((Channel) == LL_DMA_CHANNEL_4) || \
92 ((Channel) == LL_DMA_CHANNEL_5) || \
93 ((Channel) == LL_DMA_CHANNEL_6) || \
94 ((Channel) == LL_DMA_CHANNEL_7) || \
95 ((Channel) == LL_DMA_CHANNEL_8) || \
96 ((Channel) == LL_DMA_CHANNEL_9) || \
97 ((Channel) == LL_DMA_CHANNEL_10) || \
98 ((Channel) == LL_DMA_CHANNEL_11) || \
99 ((Channel) == LL_DMA_CHANNEL_12) || \
100 ((Channel) == LL_DMA_CHANNEL_13) || \
101 ((Channel) == LL_DMA_CHANNEL_14) || \
102 ((Channel) == LL_DMA_CHANNEL_15) || \
103 ((Channel) == LL_DMA_CHANNEL_ALL))))
104
105 #define IS_LL_HPDMA_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == HPDMA1) && \
106 (((Channel) == LL_DMA_CHANNEL_0) || \
107 ((Channel) == LL_DMA_CHANNEL_1) || \
108 ((Channel) == LL_DMA_CHANNEL_2) || \
109 ((Channel) == LL_DMA_CHANNEL_3) || \
110 ((Channel) == LL_DMA_CHANNEL_4) || \
111 ((Channel) == LL_DMA_CHANNEL_5) || \
112 ((Channel) == LL_DMA_CHANNEL_6) || \
113 ((Channel) == LL_DMA_CHANNEL_7) || \
114 ((Channel) == LL_DMA_CHANNEL_8) || \
115 ((Channel) == LL_DMA_CHANNEL_9) || \
116 ((Channel) == LL_DMA_CHANNEL_10) || \
117 ((Channel) == LL_DMA_CHANNEL_11) || \
118 ((Channel) == LL_DMA_CHANNEL_12) || \
119 ((Channel) == LL_DMA_CHANNEL_13) || \
120 ((Channel) == LL_DMA_CHANNEL_14) || \
121 ((Channel) == LL_DMA_CHANNEL_15)))
122
123 #define IS_LL_GPDMA_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \
124 (((Channel) == LL_DMA_CHANNEL_0) || \
125 ((Channel) == LL_DMA_CHANNEL_1) || \
126 ((Channel) == LL_DMA_CHANNEL_2) || \
127 ((Channel) == LL_DMA_CHANNEL_3) || \
128 ((Channel) == LL_DMA_CHANNEL_4) || \
129 ((Channel) == LL_DMA_CHANNEL_5) || \
130 ((Channel) == LL_DMA_CHANNEL_6) || \
131 ((Channel) == LL_DMA_CHANNEL_7) || \
132 ((Channel) == LL_DMA_CHANNEL_8) || \
133 ((Channel) == LL_DMA_CHANNEL_9) || \
134 ((Channel) == LL_DMA_CHANNEL_10) || \
135 ((Channel) == LL_DMA_CHANNEL_11) || \
136 ((Channel) == LL_DMA_CHANNEL_12) || \
137 ((Channel) == LL_DMA_CHANNEL_13) || \
138 ((Channel) == LL_DMA_CHANNEL_14) || \
139 ((Channel) == LL_DMA_CHANNEL_15)))
140
141 #define IS_LL_DMA_2D_CHANNEL_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == HPDMA1) && \
142 (((Channel) == LL_DMA_CHANNEL_12) || \
143 ((Channel) == LL_DMA_CHANNEL_13) || \
144 ((Channel) == LL_DMA_CHANNEL_14) || \
145 ((Channel) == LL_DMA_CHANNEL_15))) || \
146 (((INSTANCE) == GPDMA1) && \
147 (((Channel) == LL_DMA_CHANNEL_12) || \
148 ((Channel) == LL_DMA_CHANNEL_13) || \
149 ((Channel) == LL_DMA_CHANNEL_14) || \
150 ((Channel) == LL_DMA_CHANNEL_15))))
151
152 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_NORMAL) || \
153 ((__VALUE__) == LL_DMA_PFCTRL))
154
155 #define IS_LL_DMA_PFREQ_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == HPDMA1) && \
156 (((Channel) == LL_DMA_CHANNEL_15))) || \
157 (((INSTANCE) == GPDMA1) && \
158 (((Channel) == LL_DMA_CHANNEL_0) || \
159 ((Channel) == LL_DMA_CHANNEL_15))))
160
161 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) || \
162 ((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
163 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH))
164
165 #define IS_LL_DMA_DATA_ALIGNMENT(__VALUE__) (((__VALUE__) == LL_DMA_DATA_ALIGN_ZEROPADD) || \
166 ((__VALUE__) == LL_DMA_DATA_ALIGN_SIGNEXTPADD) || \
167 ((__VALUE__) == LL_DMA_DATA_PACK_UNPACK))
168
169 #define IS_LL_DMA_BURST_LENGTH(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= 64U))
170
171 #define IS_LL_DMA_SRC_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_SRC_DATAWIDTH_BYTE) || \
172 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_HALFWORD) || \
173 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_WORD) || \
174 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_DOUBLEWORD))
175
176 #define IS_LL_DMA_DEST_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_DEST_DATAWIDTH_BYTE) || \
177 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_HALFWORD) || \
178 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_WORD) || \
179 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_DOUBLEWORD))
180
181 #define IS_LL_DMA_SRC_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_FIXED) || \
182 ((__VALUE__) == LL_DMA_SRC_INCREMENT))
183
184 #define IS_LL_DMA_DEST_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_FIXED) || \
185 ((__VALUE__) == LL_DMA_DEST_INCREMENT))
186
187 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_LOW_PRIORITY_LOW_WEIGHT) || \
188 ((__VALUE__) == LL_DMA_LOW_PRIORITY_MID_WEIGHT) || \
189 ((__VALUE__) == LL_DMA_LOW_PRIORITY_HIGH_WEIGHT) || \
190 ((__VALUE__) == LL_DMA_HIGH_PRIORITY))
191
192 #define IS_LL_DMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0xFFFFU)
193
194 #define IS_LL_DMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x0EFFU)
195
196 #define IS_LL_DMA_TRIGGER_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TRIGM_BLK_TRANSFER) || \
197 ((__VALUE__) == LL_DMA_TRIGM_RPT_BLK_TRANSFER) || \
198 ((__VALUE__) == LL_DMA_TRIGM_LLI_LINK_TRANSFER) || \
199 ((__VALUE__) == LL_DMA_TRIGM_SINGLBURST_TRANSFER ))
200
201 #define IS_LL_DMA_TRIGGER_POLARITY(__VALUE__) (((__VALUE__) == LL_DMA_TRIG_POLARITY_MASKED) || \
202 ((__VALUE__) == LL_DMA_TRIG_POLARITY_RISING) || \
203 ((__VALUE__) == LL_DMA_TRIG_POLARITY_FALLING))
204
205 #define IS_LL_DMA_BLKHW_REQUEST(__VALUE__) (((__VALUE__) == LL_DMA_HWREQUEST_SINGLEBURST) || \
206 ((__VALUE__) == LL_DMA_HWREQUEST_BLK))
207
208 #define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_TIM15_TRGO)
209
210 #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_I3C1_RS)
211
212 #define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER) || \
213 ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER) || \
214 ((__VALUE__) == LL_DMA_TCEM_EACH_LLITEM_TRANSFER) || \
215 ((__VALUE__) == LL_DMA_TCEM_LAST_LLITEM_TRANSFER))
216
217 #define IS_LL_DMA_DEST_WORD_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_WORD_PRESERVE) || \
218 ((__VALUE__) == LL_DMA_DEST_WORD_EXCHANGE))
219
220 #define IS_LL_DMA_DEST_HALFWORD_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_HALFWORD_PRESERVE) || \
221 ((__VALUE__) == LL_DMA_DEST_HALFWORD_EXCHANGE))
222
223 #define IS_LL_DMA_DEST_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_BYTE_PRESERVE) || \
224 ((__VALUE__) == LL_DMA_DEST_BYTE_EXCHANGE))
225
226 #define IS_LL_DMA_SRC_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_BYTE_PRESERVE) || \
227 ((__VALUE__) == LL_DMA_SRC_BYTE_EXCHANGE))
228
229 #define IS_LL_DMA_LINK_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT0) || \
230 ((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT1))
231
232 #define IS_LL_DMA_SRC_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT0) || \
233 ((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT1))
234
235 #define IS_LL_DMA_DEST_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT0) || \
236 ((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT1))
237
238 #define IS_LL_DMA_LINK_STEP_MODE(__VALUE__) (((__VALUE__) == LL_DMA_LSM_FULL_EXECUTION) || \
239 ((__VALUE__) == LL_DMA_LSM_1LINK_EXECUTION))
240
241 #define IS_LL_DMA_BURST_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_SRC_ADDR_INCREMENT) || \
242 ((__VALUE__) == LL_DMA_BURST_SRC_ADDR_DECREMENT))
243
244 #define IS_LL_DMA_BURST_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_DEST_ADDR_INCREMENT) || \
245 ((__VALUE__) == LL_DMA_BURST_DEST_ADDR_DECREMENT))
246
247 #define IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
248
249 #define IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_INCREMENT) || \
250 ((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_DECREMENT))
251
252 #define IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_INCREMENT) || \
253 ((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_DECREMENT))
254
255 #define IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0xFFFFU)
256
257 #define IS_LL_DMA_LINK_BASEADDR(__VALUE__) (((__VALUE__) & 0xFFFFU) == 0U)
258
259 #define IS_LL_DMA_LINK_ADDR_OFFSET(__VALUE__) (((__VALUE__) & 0x03U) == 0U)
260
261 #define IS_LL_DMA_LINK_UPDATE_REGISTERS(__VALUE__) ((((__VALUE__) & 0x01FE0000U) == 0U) && ((__VALUE__) != 0U))
262
263 #define IS_LL_DMA_LINK_NODETYPE(__VALUE__) (((__VALUE__) == LL_DMA_HPDMA_2D_NODE) || \
264 ((__VALUE__) == LL_DMA_HPDMA_LINEAR_NODE) || \
265 ((__VALUE__) == LL_DMA_GPDMA_2D_NODE) || \
266 ((__VALUE__) == LL_DMA_GPDMA_LINEAR_NODE))
267
268 /**
269 * @}
270 */
271
272 /* Private function prototypes -----------------------------------------------*/
273 /* Exported functions --------------------------------------------------------*/
274
275 /** @addtogroup DMA_LL_Exported_Functions
276 * @{
277 */
278
279 /** @addtogroup DMA_LL_EF_Init
280 * @{
281 */
282
283 /**
284 * @brief De-initialize the DMA registers to their default reset values.
285 * @note This API is used for all available DMA channels.
286 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
287 * helper macros :
288 * @arg @ref LL_DMA_GET_INSTANCE
289 * @arg @ref LL_DMA_GET_CHANNEL
290 * @param DMAx DMAx Instance
291 * @param Channel This parameter can be one of the following values:
292 * @arg @ref LL_DMA_CHANNEL_0
293 * @arg @ref LL_DMA_CHANNEL_1
294 * @arg @ref LL_DMA_CHANNEL_2
295 * @arg @ref LL_DMA_CHANNEL_3
296 * @arg @ref LL_DMA_CHANNEL_4
297 * @arg @ref LL_DMA_CHANNEL_5
298 * @arg @ref LL_DMA_CHANNEL_6
299 * @arg @ref LL_DMA_CHANNEL_7
300 * @arg @ref LL_DMA_CHANNEL_8
301 * @arg @ref LL_DMA_CHANNEL_9
302 * @arg @ref LL_DMA_CHANNEL_10
303 * @arg @ref LL_DMA_CHANNEL_11
304 * @arg @ref LL_DMA_CHANNEL_12
305 * @arg @ref LL_DMA_CHANNEL_13
306 * @arg @ref LL_DMA_CHANNEL_14
307 * @arg @ref LL_DMA_CHANNEL_15
308 * @retval An ErrorStatus enumeration value:
309 * - SUCCESS : DMA registers are de-initialized.
310 * - ERROR : DMA registers are not de-initialized.
311 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)312 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
313 {
314 DMA_Channel_TypeDef *tmp;
315 ErrorStatus status = SUCCESS;
316
317 /* Check the DMA Instance DMAx and Channel parameters */
318 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
319
320 if (Channel == LL_DMA_CHANNEL_ALL)
321 {
322 if (DMAx == GPDMA1)
323 {
324 /* Force reset of DMA clock */
325 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
326
327 /* Release reset of DMA clock */
328 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
329 }
330 else
331 {
332 /* Force reset of DMA clock */
333 LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_HPDMA1);
334
335 /* Release reset of DMA clock */
336 LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_HPDMA1);
337 }
338 }
339 else
340 {
341 /* Get the DMA Channel Instance */
342 tmp = (DMA_Channel_TypeDef *)(LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
343
344 /* Suspend DMA channel */
345 LL_DMA_SuspendChannel(DMAx, Channel);
346
347 /* Disable the selected Channel */
348 LL_DMA_ResetChannel(DMAx, Channel);
349
350 /* Reset DMAx_Channely control register */
351 LL_DMA_WriteReg(tmp, CLBAR, 0U);
352
353 /* Reset DMAx_Channely control register */
354 LL_DMA_WriteReg(tmp, CCR, 0U);
355
356 /* Reset DMAx_Channely Configuration register */
357 LL_DMA_WriteReg(tmp, CTR1, 0U);
358
359 /* Reset DMAx_Channely transfer register 2 */
360 LL_DMA_WriteReg(tmp, CTR2, 0U);
361
362 /* Reset DMAx_Channely block number of data register */
363 LL_DMA_WriteReg(tmp, CBR1, 0U);
364
365 /* Reset DMAx_Channely source address register */
366 LL_DMA_WriteReg(tmp, CSAR, 0U);
367
368 /* Reset DMAx_Channely destination address register */
369 LL_DMA_WriteReg(tmp, CDAR, 0U);
370
371 /* Check DMA channel */
372 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
373 {
374 /* Reset DMAx_Channely transfer register 3 */
375 LL_DMA_WriteReg(tmp, CTR3, 0U);
376
377 /* Reset DMAx_Channely Block register 2 */
378 LL_DMA_WriteReg(tmp, CBR2, 0U);
379 }
380
381 /* Reset DMAx_Channely Linked list address register */
382 LL_DMA_WriteReg(tmp, CLLR, 0U);
383
384 /* Reset DMAx_Channely pending flags */
385 LL_DMA_WriteReg(tmp, CFCR, 0x00003F00U);
386
387 /* Reset DMAx_Channely attribute */
388 LL_DMA_DisableChannelPrivilege(DMAx, Channel);
389
390 }
391
392 return (uint32_t)status;
393 }
394
395 /**
396 * @brief Initialize the DMA registers according to the specified parameters
397 * in DMA_InitStruct.
398 * @note This API is used for all available DMA channels.
399 * @note A software request transfer can be done once programming the direction
400 * field in memory to memory value.
401 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
402 * helper macros :
403 * @arg @ref LL_DMA_GET_INSTANCE
404 * @arg @ref LL_DMA_GET_CHANNEL
405 * @param DMAx DMAx Instance
406 * @param Channel This parameter can be one of the following values:
407 * @arg @ref LL_DMA_CHANNEL_0
408 * @arg @ref LL_DMA_CHANNEL_1
409 * @arg @ref LL_DMA_CHANNEL_2
410 * @arg @ref LL_DMA_CHANNEL_3
411 * @arg @ref LL_DMA_CHANNEL_4
412 * @arg @ref LL_DMA_CHANNEL_5
413 * @arg @ref LL_DMA_CHANNEL_6
414 * @arg @ref LL_DMA_CHANNEL_7
415 * @arg @ref LL_DMA_CHANNEL_8
416 * @arg @ref LL_DMA_CHANNEL_9
417 * @arg @ref LL_DMA_CHANNEL_10
418 * @arg @ref LL_DMA_CHANNEL_11
419 * @arg @ref LL_DMA_CHANNEL_12
420 * @arg @ref LL_DMA_CHANNEL_13
421 * @arg @ref LL_DMA_CHANNEL_14
422 * @arg @ref LL_DMA_CHANNEL_15
423 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
424 * @retval An ErrorStatus enumeration value:
425 * - SUCCESS : DMA registers are initialized.
426 * - ERROR : Not applicable.
427 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitTypeDef * DMA_InitStruct)428 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
429 {
430 /* Check the DMA Instance DMAx and Channel parameters*/
431 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
432
433 /* Check the DMA parameters from DMA_InitStruct */
434 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
435
436 /* Check direction */
437 if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
438 {
439 assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitStruct->Request));
440 }
441
442 assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitStruct->DataAlignment));
443 assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitStruct->SrcDataWidth));
444 assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitStruct->DestDataWidth));
445 assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitStruct->SrcIncMode));
446 assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitStruct->DestIncMode));
447 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
448 assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitStruct->BlkDataLength));
449 assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitStruct->TriggerPolarity));
450 assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitStruct->BlkHWRequest));
451 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitStruct->TransferEventMode));
452 assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitStruct->LinkStepMode));
453 assert_param(IS_LL_DMA_LINK_BASEADDR(DMA_InitStruct->LinkedListBaseAddr));
454 assert_param(IS_LL_DMA_LINK_ADDR_OFFSET(DMA_InitStruct->LinkedListAddrOffset));
455 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
456 if (DMA_InitStruct->Mode == LL_DMA_PFCTRL)
457 {
458 assert_param(IS_LL_DMA_PFREQ_INSTANCE(DMAx, Channel));
459 }
460
461 /* Check DMA instance */
462 if ((IS_LL_HPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) || (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U))
463 {
464 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->SrcBurstLength));
465 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->DestBurstLength));
466 assert_param(IS_LL_DMA_DEST_WORD_EXCHANGE(DMA_InitStruct->DestWordExchange));
467 assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitStruct->DestHWordExchange));
468 assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitStruct->DestByteExchange));
469 assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitStruct->SrcByteExchange));
470 assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitStruct->LinkAllocatedPort));
471 assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitStruct->SrcAllocatedPort));
472 assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitStruct->DestAllocatedPort));
473 }
474
475 /* Check trigger polarity */
476 if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
477 {
478 assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitStruct->TriggerMode));
479 assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitStruct->TriggerSelection));
480 }
481
482 /* Check DMA channel */
483 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
484 {
485 assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitStruct->BlkRptCount));
486 assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitStruct->SrcAddrUpdateMode));
487 assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitStruct->DestAddrUpdateMode));
488 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->SrcAddrOffset));
489 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->DestAddrOffset));
490 assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitStruct->BlkRptSrcAddrUpdateMode));
491 assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitStruct->BlkRptDestAddrUpdateMode));
492 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptSrcAddrOffset));
493 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptDestAddrOffset));
494 }
495
496 /*-------------------------- DMAx CLBAR Configuration ------------------------
497 * Configure the Transfer linked list address with parameter :
498 * - LinkedListBaseAdd: DMA_CLBAR_LBA[31:16] bits
499 */
500 LL_DMA_SetLinkedListBaseAddr(DMAx, Channel, DMA_InitStruct->LinkedListBaseAddr);
501
502 /*-------------------------- DMAx CCR Configuration --------------------------
503 * Configure the control parameter :
504 * - LinkAllocatedPort: DMA_CCR_LAP bit
505 * - LinkStepMode: DMA_CCR_LSM bit
506 * - Priority: DMA_CCR_PRIO [23:22] bits
507 */
508 LL_DMA_ConfigControl(DMAx, Channel, DMA_InitStruct->Priority | \
509 DMA_InitStruct->LinkAllocatedPort | \
510 DMA_InitStruct->LinkStepMode);
511
512 /*-------------------------- DMAx CTR1 Configuration -------------------------
513 * Configure the Data transfer parameter :
514 * - DestAllocatedPort: DMA_CTR1_DAP bit
515 * - DestWordExchange: DMA_CTR1_DWX bit
516 * - DestHWordExchange: DMA_CTR1_DHX bit
517 * - DestByteExchange: DMA_CTR1_DBX bit
518 * - DestIncMode: DMA_CTR1_DINC bit
519 * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
520 * - SrcAllocatedPort: DMA_CTR1_SAP bit
521 * - SrcByteExchange: DMA_CTR1_SBX bit
522 * - DataAlignment: DMA_CTR1_PAM [12:11] bits
523 * - SrcIncMode: DMA_CTR1_SINC bit
524 * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
525 * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
526 * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
527 */
528 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->DestAllocatedPort | \
529 DMA_InitStruct->DestWordExchange | \
530 DMA_InitStruct->DestHWordExchange | \
531 DMA_InitStruct->DestByteExchange | \
532 DMA_InitStruct->DestIncMode | \
533 DMA_InitStruct->DestDataWidth | \
534 DMA_InitStruct->SrcAllocatedPort | \
535 DMA_InitStruct->SrcByteExchange | \
536 DMA_InitStruct->DataAlignment | \
537 DMA_InitStruct->SrcIncMode | \
538 DMA_InitStruct->SrcDataWidth);
539 /* Check DMA instance */
540 if ((IS_LL_HPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) || (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U))
541 {
542 LL_DMA_ConfigBurstLength(DMAx, Channel, DMA_InitStruct->SrcBurstLength,
543 DMA_InitStruct->DestBurstLength);
544 }
545
546 /*-------------------------- DMAx CTR2 Configuration -------------------------
547 * Configure the channel transfer parameter :
548 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
549 * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
550 * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
551 * - BlkHWRequest: DMA_CTR2_BREQ bit
552 * - Mode: DMA_CTR2_PFREQ bit
553 * - Direction: DMA_CTR2_DREQ bit
554 * - Direction: DMA_CTR2_SWREQ bit
555 * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
556 * - Request: DMA_CTR2_REQSEL [6:0] bits
557 */
558 LL_DMA_ConfigChannelTransfer(DMAx, Channel, DMA_InitStruct->TransferEventMode | \
559 DMA_InitStruct->TriggerPolarity | \
560 DMA_InitStruct->BlkHWRequest | \
561 DMA_InitStruct->Mode | \
562 DMA_InitStruct->Direction);
563
564 /* Check direction */
565 if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
566 {
567 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->Request);
568 }
569
570 /* Check trigger polarity */
571 if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
572 {
573 LL_DMA_SetHWTrigger(DMAx, Channel, DMA_InitStruct->TriggerSelection);
574 LL_DMA_SetTriggerMode(DMAx, Channel, DMA_InitStruct->TriggerMode);
575 }
576
577 /*-------------------------- DMAx CBR1 Configuration -------------------------
578 * Configure the Transfer Block counters and update mode with parameter :
579 * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
580 * - BlkRptCount: DMA_CBR1_BRC[26:16] bits
581 * BlkRptCount field is supported only by 2D addressing channels.
582 * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit
583 * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels.
584 * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit
585 * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels.
586 * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit
587 * SrcAddrUpdateMode field is supported only by 2D addressing channels.
588 * - DestAddrUpdateMode: DMA_CBR1_DDEC bit
589 * DestAddrUpdateMode field is supported only by 2D addressing channels.
590 */
591 LL_DMA_SetBlkDataLength(DMAx, Channel, DMA_InitStruct->BlkDataLength);
592
593 /* Check DMA channel */
594 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
595 {
596 LL_DMA_SetBlkRptCount(DMAx, Channel, DMA_InitStruct->BlkRptCount);
597 LL_DMA_ConfigBlkRptAddrUpdate(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrUpdateMode | \
598 DMA_InitStruct->BlkRptDestAddrUpdateMode | \
599 DMA_InitStruct->SrcAddrUpdateMode | \
600 DMA_InitStruct->DestAddrUpdateMode);
601 }
602
603 /*-------------------------- DMAx CSAR and CDAR Configuration ----------------
604 * Configure the Transfer source address with parameter :
605 * - SrcAddress: DMA_CSAR_SA[31:0] bits
606 * - DestAddress: DMA_CDAR_DA[31:0] bits
607 */
608 LL_DMA_ConfigAddresses(DMAx, Channel, DMA_InitStruct->SrcAddress, DMA_InitStruct->DestAddress);
609
610 /* Check DMA channel */
611 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
612 {
613 /*------------------------ DMAx CTR3 Configuration -------------------------
614 * Configure the Transfer Block counters and update mode with parameter :
615 * - SrcAddrOffset: DMA_CTR3_SAO[28:16] bits
616 * SrcAddrOffset field is supported only by 2D addressing channels.
617 * - DestAddrOffset: DMA_CTR3_DAO[12:0] bits
618 * DestAddrOffset field is supported only by 2D addressing channels.
619 */
620 LL_DMA_ConfigAddrUpdateValue(DMAx, Channel, DMA_InitStruct->SrcAddrOffset, DMA_InitStruct->DestAddrOffset);
621
622 /*------------------------ DMAx CBR2 Configuration -----------------------
623 * Configure the Transfer Block counters and update mode with parameter :
624 * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits
625 * BlkRptSrcAddrOffset field is supported only by 2D addressing channels.
626 * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits
627 * BlkRptDestAddrOffset field is supported only by 2D addressing channels.
628 */
629 LL_DMA_ConfigBlkRptAddrUpdateValue(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrOffset,
630 DMA_InitStruct->BlkRptDestAddrOffset);
631 }
632
633 /*-------------------------- DMAx CLLR Configuration -------------------------
634 * Configure the Transfer linked list address with parameter :
635 * - DestAddrOffset: DMA_CLLR_LA[15:2] bits
636 */
637 LL_DMA_SetLinkedListAddrOffset(DMAx, Channel, DMA_InitStruct->LinkedListAddrOffset);
638
639 return (uint32_t)SUCCESS;
640 }
641
642 /**
643 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
644 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
645 * @retval None.
646 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)647 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
648 {
649 /* Set DMA_InitStruct fields to default values */
650 DMA_InitStruct->SrcAddress = 0x00000000U;
651 DMA_InitStruct->DestAddress = 0x00000000U;
652 DMA_InitStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
653 DMA_InitStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
654 DMA_InitStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
655 DMA_InitStruct->SrcBurstLength = 1U;
656 DMA_InitStruct->DestBurstLength = 1U;
657 DMA_InitStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
658 DMA_InitStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
659 DMA_InitStruct->SrcIncMode = LL_DMA_SRC_FIXED;
660 DMA_InitStruct->DestIncMode = LL_DMA_DEST_FIXED;
661 DMA_InitStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
662 DMA_InitStruct->BlkDataLength = 0x00000000U;
663 DMA_InitStruct->Mode = LL_DMA_NORMAL;
664 DMA_InitStruct->BlkRptCount = 0x00000000U;
665 DMA_InitStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
666 DMA_InitStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
667 DMA_InitStruct->TriggerSelection = 0x00000000U;
668 DMA_InitStruct->Request = 0x00000000U;
669 DMA_InitStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
670 DMA_InitStruct->DestWordExchange = LL_DMA_DEST_WORD_PRESERVE;
671 DMA_InitStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
672 DMA_InitStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
673 DMA_InitStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
674 DMA_InitStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
675 DMA_InitStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
676 DMA_InitStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
677 DMA_InitStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
678 DMA_InitStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT;
679 DMA_InitStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT;
680 DMA_InitStruct->SrcAddrOffset = 0x00000000U;
681 DMA_InitStruct->DestAddrOffset = 0x00000000U;
682 DMA_InitStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
683 DMA_InitStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
684 DMA_InitStruct->BlkRptSrcAddrOffset = 0x00000000U;
685 DMA_InitStruct->BlkRptDestAddrOffset = 0x00000000U;
686 DMA_InitStruct->LinkedListBaseAddr = 0x00000000U;
687 DMA_InitStruct->LinkedListAddrOffset = 0x00000000U;
688 }
689
690 /**
691 * @brief Set each @ref LL_DMA_InitLinkedListTypeDef field to default value.
692 * @param DMA_InitLinkedListStruct Pointer to
693 * a @ref LL_DMA_InitLinkedListTypeDef structure.
694 * @retval None.
695 */
LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef * DMA_InitLinkedListStruct)696 void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
697 {
698 /* Set LL_DMA_InitLinkedListTypeDef fields to default values */
699 DMA_InitLinkedListStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
700 DMA_InitLinkedListStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
701 DMA_InitLinkedListStruct->TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER;
702 DMA_InitLinkedListStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
703 }
704
705 /**
706 * @brief De-initialize the DMA linked list.
707 * @note This API is used for all available DMA channels.
708 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
709 * helper macros :
710 * @arg @ref LL_DMA_GET_INSTANCE
711 * @arg @ref LL_DMA_GET_CHANNEL
712 * @param DMAx DMAx Instance
713 * @param Channel This parameter can be one of the following values:
714 * @arg @ref LL_DMA_CHANNEL_0
715 * @arg @ref LL_DMA_CHANNEL_1
716 * @arg @ref LL_DMA_CHANNEL_2
717 * @arg @ref LL_DMA_CHANNEL_3
718 * @arg @ref LL_DMA_CHANNEL_4
719 * @arg @ref LL_DMA_CHANNEL_5
720 * @arg @ref LL_DMA_CHANNEL_6
721 * @arg @ref LL_DMA_CHANNEL_7
722 * @arg @ref LL_DMA_CHANNEL_8
723 * @arg @ref LL_DMA_CHANNEL_9
724 * @arg @ref LL_DMA_CHANNEL_10
725 * @arg @ref LL_DMA_CHANNEL_11
726 * @arg @ref LL_DMA_CHANNEL_12
727 * @arg @ref LL_DMA_CHANNEL_13
728 * @arg @ref LL_DMA_CHANNEL_14
729 * @arg @ref LL_DMA_CHANNEL_15
730 * @retval An ErrorStatus enumeration value:
731 * - SUCCESS : DMA registers are de-initialized.
732 * - ERROR : DMA registers are not de-initialized.
733 */
LL_DMA_List_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)734 uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
735 {
736 return LL_DMA_DeInit(DMAx, Channel);
737 }
738
739 /**
740 * @brief Initialize the DMA linked list according to the specified parameters
741 * in LL_DMA_InitLinkedListTypeDef.
742 * @note This API is used for all available DMA channels.
743 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
744 * helper macros :
745 * @arg @ref LL_DMA_GET_INSTANCE
746 * @arg @ref LL_DMA_GET_CHANNEL
747 * @param DMAx DMAx Instance
748 * @param Channel This parameter can be one of the following values:
749 * @arg @ref LL_DMA_CHANNEL_0
750 * @arg @ref LL_DMA_CHANNEL_1
751 * @arg @ref LL_DMA_CHANNEL_2
752 * @arg @ref LL_DMA_CHANNEL_3
753 * @arg @ref LL_DMA_CHANNEL_4
754 * @arg @ref LL_DMA_CHANNEL_5
755 * @arg @ref LL_DMA_CHANNEL_6
756 * @arg @ref LL_DMA_CHANNEL_7
757 * @arg @ref LL_DMA_CHANNEL_8
758 * @arg @ref LL_DMA_CHANNEL_9
759 * @arg @ref LL_DMA_CHANNEL_10
760 * @arg @ref LL_DMA_CHANNEL_11
761 * @arg @ref LL_DMA_CHANNEL_12
762 * @arg @ref LL_DMA_CHANNEL_13
763 * @arg @ref LL_DMA_CHANNEL_14
764 * @arg @ref LL_DMA_CHANNEL_15
765 * @param DMA_InitLinkedListStruct pointer to
766 * a @ref LL_DMA_InitLinkedListTypeDef structure.
767 * @retval An ErrorStatus enumeration value:
768 * - SUCCESS : DMA registers are initialized.
769 * - ERROR : Not applicable.
770 */
LL_DMA_List_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitLinkedListTypeDef * DMA_InitLinkedListStruct)771 uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
772 {
773 /* Check the DMA Instance DMAx and Channel parameters*/
774 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
775
776 /* Check the DMA parameters from DMA_InitLinkedListStruct */
777 assert_param(IS_LL_DMA_PRIORITY(DMA_InitLinkedListStruct->Priority));
778 assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitLinkedListStruct->LinkStepMode));
779 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitLinkedListStruct->TransferEventMode));
780 /* Check DMA instance */
781 if ((IS_LL_HPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) || (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U))
782 {
783 assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitLinkedListStruct->LinkAllocatedPort));
784 }
785
786 /*-------------------------- DMAx CCR Configuration --------------------------
787 * Configure the control parameter :
788 * - LinkAllocatedPort: DMA_CCR_LAP bit
789 * LinkAllocatedPort field is supported only by GPDMA channels.
790 * - LinkStepMode: DMA_CCR_LSM bit
791 * - Priority: DMA_CCR_PRIO [23:22] bits
792 */
793 LL_DMA_ConfigControl(DMAx, Channel, DMA_InitLinkedListStruct->Priority | \
794 DMA_InitLinkedListStruct->LinkAllocatedPort | \
795 DMA_InitLinkedListStruct->LinkStepMode);
796
797 /*-------------------------- DMAx CTR2 Configuration -------------------------
798 * Configure the channel transfer parameter :
799 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
800 */
801 LL_DMA_SetTransferEventMode(DMAx, Channel, DMA_InitLinkedListStruct->TransferEventMode);
802
803 return (uint32_t)SUCCESS;
804 }
805
806 /**
807 * @brief Set each @ref LL_DMA_InitNodeTypeDef field to default value.
808 * @param DMA_InitNodeStruct Pointer to a @ref LL_DMA_InitNodeTypeDef
809 * structure.
810 * @retval None.
811 */
LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef * DMA_InitNodeStruct)812 void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct)
813 {
814 /* Set DMA_InitNodeStruct fields to default values */
815 DMA_InitNodeStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
816 DMA_InitNodeStruct->DestWordExchange = LL_DMA_DEST_WORD_PRESERVE;
817 DMA_InitNodeStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
818 DMA_InitNodeStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
819 DMA_InitNodeStruct->DestBurstLength = 1U;
820 DMA_InitNodeStruct->DestIncMode = LL_DMA_DEST_FIXED;
821 DMA_InitNodeStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
822 DMA_InitNodeStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
823 DMA_InitNodeStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
824 DMA_InitNodeStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
825 DMA_InitNodeStruct->SrcBurstLength = 1U;
826 DMA_InitNodeStruct->SrcIncMode = LL_DMA_SRC_FIXED;
827 DMA_InitNodeStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
828 DMA_InitNodeStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
829 DMA_InitNodeStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
830 DMA_InitNodeStruct->TriggerSelection = 0x00000000U;
831 DMA_InitNodeStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
832 DMA_InitNodeStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
833 DMA_InitNodeStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
834 DMA_InitNodeStruct->Request = 0x00000000U;
835 DMA_InitNodeStruct->Mode = LL_DMA_NORMAL;
836 DMA_InitNodeStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
837 DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
838 DMA_InitNodeStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT;
839 DMA_InitNodeStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT;
840 DMA_InitNodeStruct->BlkRptCount = 0x00000000U;
841 DMA_InitNodeStruct->BlkDataLength = 0x00000000U;
842 DMA_InitNodeStruct->SrcAddress = 0x00000000U;
843 DMA_InitNodeStruct->DestAddress = 0x00000000U;
844 DMA_InitNodeStruct->DestAddrOffset = 0x00000000U;
845 DMA_InitNodeStruct->SrcAddrOffset = 0x00000000U;
846 DMA_InitNodeStruct->BlkRptDestAddrOffset = 0x00000000U;
847 DMA_InitNodeStruct->BlkRptSrcAddrOffset = 0x00000000U;
848 DMA_InitNodeStruct->UpdateRegisters = (LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 | \
849 LL_DMA_UPDATE_CBR1 | LL_DMA_UPDATE_CSAR | \
850 LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CTR3 | \
851 LL_DMA_UPDATE_CBR2 | LL_DMA_UPDATE_CLLR);
852 DMA_InitNodeStruct->NodeType = LL_DMA_GPDMA_LINEAR_NODE;
853 }
854
855 /**
856 * @brief Initializes DMA linked list node according to the specified
857 * parameters in the DMA_InitNodeStruct.
858 * @param DMA_InitNodeStruct Pointer to a LL_DMA_InitNodeTypeDef structure
859 * that contains linked list node
860 * registers configurations.
861 * @param pNode Pointer to linked list node to fill according to
862 * LL_DMA_LinkNodeTypeDef parameters.
863 * @retval None
864 */
LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef * DMA_InitNodeStruct,LL_DMA_LinkNodeTypeDef * pNode)865 uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode)
866 {
867 uint32_t reg_counter = 0U;
868
869 /* Check the DMA Node type */
870 assert_param(IS_LL_DMA_LINK_NODETYPE(DMA_InitNodeStruct->NodeType));
871
872 /* Check the DMA parameters from DMA_InitNodeStruct */
873 assert_param(IS_LL_DMA_DIRECTION(DMA_InitNodeStruct->Direction));
874
875 /* Check direction */
876 if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
877 {
878 assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitNodeStruct->Request));
879 }
880
881 assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitNodeStruct->DataAlignment));
882 assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitNodeStruct->SrcDataWidth));
883 assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitNodeStruct->DestDataWidth));
884 assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitNodeStruct->SrcIncMode));
885 assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitNodeStruct->DestIncMode));
886 assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitNodeStruct->BlkDataLength));
887 assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitNodeStruct->TriggerPolarity));
888 assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitNodeStruct->BlkHWRequest));
889 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitNodeStruct->TransferEventMode));
890 assert_param(IS_LL_DMA_LINK_UPDATE_REGISTERS(DMA_InitNodeStruct->UpdateRegisters));
891 assert_param(IS_LL_DMA_MODE(DMA_InitNodeStruct->Mode));
892
893 /* Check trigger polarity */
894 if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
895 {
896 assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode));
897 assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection));
898 }
899
900 /* Check node type */
901 if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_LINEAR_NODE) || \
902 (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_LINEAR_NODE))
903 {
904 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength));
905 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength));
906 assert_param(IS_LL_DMA_DEST_WORD_EXCHANGE(DMA_InitNodeStruct->DestWordExchange));
907 assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitNodeStruct->DestHWordExchange));
908 assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitNodeStruct->DestByteExchange));
909 assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitNodeStruct->SrcByteExchange));
910 assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitNodeStruct->SrcAllocatedPort));
911 assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitNodeStruct->DestAllocatedPort));
912 }
913
914 /* Check DMA channel */
915 if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || \
916 (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
917 {
918 assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitNodeStruct->BlkRptCount));
919 assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitNodeStruct->SrcAddrUpdateMode));
920 assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitNodeStruct->DestAddrUpdateMode));
921 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->SrcAddrOffset));
922 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->DestAddrOffset));
923 assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode));
924 assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptDestAddrUpdateMode));
925 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptSrcAddrOffset));
926 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptDestAddrOffset));
927 }
928
929 /* Check if CTR1 register update is enabled */
930 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR1) == LL_DMA_UPDATE_CTR1)
931 {
932 /*-------------------------- DMAx CTR1 Configuration -----------------------
933 * Configure the Data transfer parameter :
934 * - DestAllocatedPort: DMA_CTR1_DAP bit
935 * - DestWordExchange: DMA_CTR1_DWX bit
936 * - DestHWordExchange: DMA_CTR1_DHX bit
937 * - DestByteExchange: DMA_CTR1_DBX bit
938 * - DestIncMode: DMA_CTR1_DINC bit
939 * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
940 * - SrcAllocatedPort: DMA_CTR1_SAP bit
941 * - SrcByteExchange: DMA_CTR1_SBX bit
942 * - DataAlignment: DMA_CTR1_PAM [12:11] bits
943 * - SrcIncMode: DMA_CTR1_SINC bit
944 * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
945 * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
946 * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
947 */
948
949 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->DestIncMode | \
950 DMA_InitNodeStruct->DestDataWidth | \
951 DMA_InitNodeStruct->DataAlignment | \
952 DMA_InitNodeStruct->SrcIncMode | \
953 DMA_InitNodeStruct->SrcDataWidth);
954
955 /* Update CTR1 register fields */
956 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort | \
957 DMA_InitNodeStruct->DestWordExchange | \
958 DMA_InitNodeStruct->DestHWordExchange | \
959 DMA_InitNodeStruct->DestByteExchange | \
960 ((DMA_InitNodeStruct->DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) | \
961 DMA_InitNodeStruct->SrcAllocatedPort | \
962 DMA_InitNodeStruct->SrcByteExchange | \
963 ((DMA_InitNodeStruct->SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos));
964
965 /* Increment counter for the next register */
966 reg_counter++;
967 }
968
969
970 /* Check if CTR2 register update is enabled */
971 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR2) == LL_DMA_UPDATE_CTR2)
972 {
973 /*-------------------------- DMAx CTR2 Configuration -----------------------
974 * Configure the channel transfer parameter :
975 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
976 * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
977 * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
978 * - Mode: DMA_CTR2_PFREQ bit
979 * - BlkHWRequest: DMA_CTR2_BREQ bit
980 * - Direction: DMA_CTR2_DREQ bit
981 * - Direction: DMA_CTR2_SWREQ bit
982 * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
983 * - Request: DMA_CTR2_REQSEL [6:0] bits
984 */
985 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->TransferEventMode | \
986 DMA_InitNodeStruct->TriggerPolarity | \
987 DMA_InitNodeStruct->BlkHWRequest | \
988 DMA_InitNodeStruct->Mode | \
989 DMA_InitNodeStruct->Direction);
990
991 /* Check direction */
992 if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
993 {
994 pNode->LinkRegisters[reg_counter] |= DMA_InitNodeStruct->Request & DMA_CTR2_REQSEL;
995 }
996
997 /* Check trigger polarity */
998 if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
999 {
1000 pNode->LinkRegisters[reg_counter] |= (((DMA_InitNodeStruct->TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & \
1001 DMA_CTR2_TRIGSEL) | DMA_InitNodeStruct->TriggerMode);
1002 }
1003
1004
1005 /* Increment counter for the next register */
1006 reg_counter++;
1007 }
1008
1009 /* Check if CBR1 register update is enabled */
1010 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR1) == LL_DMA_UPDATE_CBR1)
1011 {
1012 /*-------------------------- DMAx CBR1 Configuration -----------------------
1013 * Configure the Transfer Block counters and update mode with parameter :
1014 * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
1015 * - BlkRptCount: DMA_CBR1_BRC[26:16] bits
1016 * BlkRptCount field is supported only by 2D addressing channels.
1017 * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit
1018 * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels.
1019 * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit
1020 * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels.
1021 * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit
1022 * SrcAddrUpdateMode field is supported only by 2D addressing channels.
1023 * - DestAddrUpdateMode: DMA_CBR1_DDEC bit
1024 * DestAddrUpdateMode field is supported only by 2D addressing channels.
1025 */
1026 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->BlkDataLength;
1027
1028 /* Update CBR1 register fields for 2D addressing channels */
1029 if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || \
1030 (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
1031 {
1032 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->BlkRptDestAddrUpdateMode | \
1033 DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode | \
1034 DMA_InitNodeStruct->DestAddrUpdateMode | \
1035 DMA_InitNodeStruct->SrcAddrUpdateMode | \
1036 ((DMA_InitNodeStruct->BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC));
1037 }
1038
1039 /* Increment counter for the next register */
1040 reg_counter++;
1041 }
1042
1043 /* Check if CSAR register update is enabled */
1044 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CSAR) == LL_DMA_UPDATE_CSAR)
1045 {
1046 /*-------------------------- DMAx CSAR Configuration -----------------------
1047 * Configure the Transfer Block counters and update mode with parameter :
1048 * - SrcAddress: DMA_CSAR_SA[31:0] bits
1049 */
1050 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->SrcAddress;
1051
1052 /* Increment counter for the next register */
1053 reg_counter++;
1054 }
1055
1056
1057 /* Check if CDAR register update is enabled */
1058 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CDAR) == LL_DMA_UPDATE_CDAR)
1059 {
1060 /*-------------------------- DMAx CDAR Configuration -----------------------
1061 * Configure the Transfer Block counters and update mode with parameter :
1062 * - DestAddress: DMA_CDAR_DA[31:0] bits
1063 */
1064 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->DestAddress;
1065
1066 /* Increment counter for the next register */
1067 reg_counter++;
1068 }
1069
1070
1071 /* Update CTR3 register fields for 2D addressing channels */
1072 if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
1073 {
1074 /* Check if CTR3 register update is enabled */
1075 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR3) == LL_DMA_UPDATE_CTR3)
1076 {
1077 /*-------------------------- DMAx CTR3 Configuration ---------------------
1078 * Configure the Block counters and update mode with parameter :
1079 * - DestAddressOffset: DMA_CTR3_DAO[12:0] bits
1080 * DestAddressOffset field is supported only by 2D addressing channels.
1081 * - SrcAddressOffset: DMA_CTR3_SAO[12:0] bits
1082 * SrcAddressOffset field is supported only by 2D addressing channels.
1083 */
1084 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->SrcAddrOffset | \
1085 ((DMA_InitNodeStruct->DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
1086
1087 /* Increment counter for the next register */
1088 reg_counter++;
1089 }
1090 }
1091
1092
1093 /* Update CBR2 register fields for 2D addressing channels */
1094 if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
1095 {
1096 /* Check if CBR2 register update is enabled */
1097 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR2) == LL_DMA_UPDATE_CBR2)
1098 {
1099 /*-------------------------- DMAx CBR2 Configuration ---------------------
1100 * Configure the Block counters and update mode with parameter :
1101 * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits
1102 * BlkRptDestAddrOffset field is supported only by 2D addressing channels.
1103 * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits
1104 * BlkRptSrcAddrOffset field is supported only by 2D addressing channels.
1105 */
1106 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->BlkRptSrcAddrOffset | \
1107 ((DMA_InitNodeStruct->BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & \
1108 DMA_CBR2_BRDAO));
1109
1110 /* Increment counter for the next register */
1111 reg_counter++;
1112 }
1113 }
1114
1115 /* Check if CLLR register update is enabled */
1116 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CLLR) == LL_DMA_UPDATE_CLLR)
1117 {
1118 /*-------------------------- DMAx CLLR Configuration -----------------------
1119 * Configure the Transfer Block counters and update mode with parameter :
1120 * - UpdateRegisters DMA_CLLR_UT1 bit
1121 * - UpdateRegisters DMA_CLLR_UT2 bit
1122 * - UpdateRegisters DMA_CLLR_UB1 bit
1123 * - UpdateRegisters DMA_CLLR_USA bit
1124 * - UpdateRegisters DMA_CLLR_UDA bit
1125 * - UpdateRegisters DMA_CLLR_UT3 bit
1126 * DMA_CLLR_UT3 bit is discarded for linear addressing channels.
1127 * - UpdateRegisters DMA_CLLR_UB2 bit
1128 * DMA_CLLR_UB2 bit is discarded for linear addressing channels.
1129 * - UpdateRegisters DMA_CLLR_ULL bit
1130 */
1131 pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CLLR_UT2 | \
1132 DMA_CLLR_UB1 | DMA_CLLR_USA | \
1133 DMA_CLLR_UDA | DMA_CLLR_ULL)));
1134
1135 /* Update CLLR register fields for 2D addressing channels */
1136 if ((DMA_InitNodeStruct->NodeType == LL_DMA_HPDMA_2D_NODE) || \
1137 (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE))
1138 {
1139 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CLLR_UB2));
1140 }
1141 }
1142
1143 return (uint32_t)SUCCESS;
1144 }
1145
1146 /**
1147 * @brief Connect Linked list Nodes.
1148 * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Linked list node.
1149 * @param PrevNodeCLLRIdx Offset of Previous Node CLLR register.
1150 * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
1151 * @param pNewLinkNode Pointer to new Linked list.
1152 * @param NewNodeCLLRIdx Offset of New Node CLLR register.
1153 * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
1154 * @retval None
1155 */
LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef * pPrevLinkNode,uint32_t PrevNodeCLLRIdx,LL_DMA_LinkNodeTypeDef * pNewLinkNode,uint32_t NewNodeCLLRIdx)1156 void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
1157 LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx)
1158 {
1159 pPrevLinkNode->LinkRegisters[PrevNodeCLLRIdx] = (((uint32_t)pNewLinkNode & DMA_CLLR_LA) | \
1160 (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \
1161 DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \
1162 DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL)));
1163 }
1164
1165 /**
1166 * @brief Disconnect the next linked list node.
1167 * @param pLinkNode Pointer to linked list node to be disconnected from the next one.
1168 * @param LinkNodeCLLRIdx Offset of Link Node CLLR register.
1169 * @retval None.
1170 */
LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef * pLinkNode,uint32_t LinkNodeCLLRIdx)1171 void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx)
1172 {
1173 pLinkNode->LinkRegisters[LinkNodeCLLRIdx] = 0;
1174 }
1175
1176 /**
1177 * @}
1178 */
1179
1180 /**
1181 * @}
1182 */
1183
1184 /**
1185 * @}
1186 */
1187
1188 #endif /* GPDMA1 || HPDMA1 */
1189
1190 /**
1191 * @}
1192 */
1193
1194 #endif /* USE_FULL_LL_DRIVER */
1195
