1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32h7rsxx_ll_adc.h"
22 #include "stm32h7rsxx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32H7RSxx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* ADC prescaler 4. */
62 /* Ratio max = 512 *4 = 2048 */
63 /* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */
64 /* Highest CPU clock PLL (PLLR). */
65 /* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */
66 /* = 3968 */
67 /* Unit: CPU cycles. */
68 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL)
69 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
70 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
71
72 /**
73 * @}
74 */
75
76 /* Private macros ------------------------------------------------------------*/
77
78 /** @addtogroup ADC_LL_Private_Macros
79 * @{
80 */
81
82 /* Check of parameters for configuration of ADC hierarchical scope: */
83 /* common to several ADC instances. */
84 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
85 (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
86 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
98 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
99 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
100 )
101
102 /* Check of parameters for configuration of ADC hierarchical scope: */
103 /* ADC instance. */
104 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
105 (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
106 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
107 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
108 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
109 )
110
111 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
112 (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
113 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
114 )
115
116 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
117 (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
118 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
119 )
120
121 /* Check of parameters for configuration of ADC hierarchical scope: */
122 /* ADC group regular */
123 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
124 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
125 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
126 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
127 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
128 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
129 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
130 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
131 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
132 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM12_TRGO) \
133 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_TRGO) \
134 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
135 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
136 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) \
144 )
145
146 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
147 (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
148 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
149 )
150
151 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
152 (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
153 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
154 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
155 )
156
157 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
158 (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
159 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
160 )
161
162 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
163 (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
164 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
165 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
166 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
167 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
168 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
169 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
170 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
171 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
172 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
173 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
174 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
175 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
176 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
177 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
178 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
179 )
180
181 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
182 (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
183 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
184 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
185 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
186 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
187 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
188 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
189 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
190 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
191 )
192
193 /* Check of parameters for configuration of ADC hierarchical scope: */
194 /* ADC group injected */
195 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
196 (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
197 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
198 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
199 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
200 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
201 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
202 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
203 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
204 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
205 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_TRGO) \
206 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_CH1) \
207 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
208 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
209 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
210 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
211 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM12_TRGO) \
212 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
213 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2) \
214 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2) \
215 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1) \
216 )
217
218 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
219 (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
220 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
221 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
222 )
223
224 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
225 (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
226 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
227 )
228
229 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
230 (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
231 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
232 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
233 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
234 )
235
236 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
237 (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
238 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
239 )
240
241 #if defined(ADC_MULTIMODE_SUPPORT)
242 /* Check of parameters for configuration of ADC hierarchical scope: */
243 /* multimode. */
244 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
245 (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
246 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
247 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
248 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
249 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
250 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
251 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
252 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
253 )
254
255 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
256 (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
257 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
258 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
259 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
260 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \
261 )
262
263 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
264 (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
265 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
266 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
267 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
268 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
269 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
270 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
271 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
272 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
273 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
274 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
275 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
276 )
277
278 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
279 (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
280 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
281 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
282 )
283
284 #endif /* ADC_MULTIMODE_SUPPORT */
285 /**
286 * @}
287 */
288
289
290 /* Private function prototypes -----------------------------------------------*/
291
292 /* Exported functions --------------------------------------------------------*/
293 /** @addtogroup ADC_LL_Exported_Functions
294 * @{
295 */
296
297 /** @addtogroup ADC_LL_EF_Init
298 * @{
299 */
300
301 /**
302 * @brief De-initialize registers of all ADC instances belonging to
303 * the same ADC common instance to their default reset values.
304 * @note This function is performing a hard reset, using high level
305 * clock source RCC ADC reset.
306 * Caution: On this STM32 series, if several ADC instances are available
307 * on the selected device, RCC ADC reset will reset
308 * all ADC instances belonging to the common ADC instance.
309 * To de-initialize only 1 ADC instance, use
310 * function @ref LL_ADC_DeInit().
311 * @param ADCxy_COMMON ADC common instance
312 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
313 * @retval An ErrorStatus enumeration value:
314 * - SUCCESS: ADC common registers are de-initialized
315 * - ERROR: not applicable
316 */
LL_ADC_CommonDeInit(const ADC_Common_TypeDef * ADCxy_COMMON)317 ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON)
318 {
319 /* Check the parameters */
320 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
321
322 /* Prevent unused argument compilation warning */
323 (void)(ADCxy_COMMON);
324
325 /* Force reset of ADC clock (core clock) */
326 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ADC12);
327
328 /* Release reset of ADC clock (core clock) */
329 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
330
331 return SUCCESS;
332 }
333
334 /**
335 * @brief Initialize some features of ADC common parameters
336 * (all ADC instances belonging to the same ADC common instance)
337 * and multimode (for devices with several ADC instances available).
338 * @note The setting of ADC common parameters is conditioned to
339 * ADC instances state:
340 * All ADC instances belonging to the same ADC common instance
341 * must be disabled.
342 * @param ADCxy_COMMON ADC common instance
343 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
344 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
345 * @retval An ErrorStatus enumeration value:
346 * - SUCCESS: ADC common registers are initialized
347 * - ERROR: ADC common registers are not initialized
348 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,const LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)349 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
350 {
351 ErrorStatus status = SUCCESS;
352
353 /* Check the parameters */
354 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
355 assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
356
357 #if defined(ADC_MULTIMODE_SUPPORT)
358 assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode));
359 if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
360 {
361 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(pADC_CommonInitStruct->MultiDMATransfer));
362 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay));
363 }
364 #endif /* ADC_MULTIMODE_SUPPORT */
365
366 /* Note: Hardware constraint (refer to description of functions */
367 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
368 /* On this STM32 series, setting of these features is conditioned to */
369 /* ADC state: */
370 /* All ADC instances of the ADC common group must be disabled. */
371 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
372 {
373 /* Configuration of ADC hierarchical scope: */
374 /* - common to several ADC */
375 /* (all ADC instances belonging to the same ADC common instance) */
376 /* - Set ADC clock (conversion clock) */
377 /* - multimode (if several ADC instances available on the */
378 /* selected device) */
379 /* - Set ADC multimode configuration */
380 /* - Set ADC multimode DMA transfer */
381 /* - Set ADC multimode: delay between 2 sampling phases */
382 #if defined(ADC_MULTIMODE_SUPPORT)
383 if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
384 {
385 MODIFY_REG(ADCxy_COMMON->CCR,
386 ADC_CCR_CKMODE
387 | ADC_CCR_PRESC
388 | ADC_CCR_DUAL
389 | ADC_CCR_MDMA
390 | ADC_CCR_DELAY
391 ,
392 pADC_CommonInitStruct->CommonClock
393 | pADC_CommonInitStruct->Multimode
394 | pADC_CommonInitStruct->MultiDMATransfer
395 | pADC_CommonInitStruct->MultiTwoSamplingDelay
396 );
397 }
398 else
399 {
400 MODIFY_REG(ADCxy_COMMON->CCR,
401 ADC_CCR_CKMODE
402 | ADC_CCR_PRESC
403 | ADC_CCR_DUAL
404 | ADC_CCR_MDMA
405 | ADC_CCR_DELAY
406 ,
407 pADC_CommonInitStruct->CommonClock
408 | LL_ADC_MULTI_INDEPENDENT
409 );
410 }
411 #else
412 LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
413 #endif /* ADC_MULTIMODE_SUPPORT */
414 }
415 else
416 {
417 /* Initialization error: One or several ADC instances belonging to */
418 /* the same ADC common instance are not disabled. */
419 status = ERROR;
420 }
421
422 return status;
423 }
424
425 /**
426 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
427 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
428 * whose fields will be set to default values.
429 * @retval None
430 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)431 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
432 {
433 /* Set pADC_CommonInitStruct fields to default values */
434 /* Set fields of ADC common */
435 /* (all ADC instances belonging to the same ADC common instance) */
436 pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
437
438 #if defined(ADC_MULTIMODE_SUPPORT)
439 /* Set fields of ADC multimode */
440 pADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
441 pADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
442 pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
443 #endif /* ADC_MULTIMODE_SUPPORT */
444 }
445
446 /**
447 * @brief De-initialize registers of the selected ADC instance
448 * to their default reset values.
449 * @note To reset all ADC instances quickly (perform a hard reset),
450 * use function @ref LL_ADC_CommonDeInit().
451 * @note If this functions returns error status, it means that ADC instance
452 * is in an unknown state.
453 * In this case, perform a hard reset using high level
454 * clock source RCC ADC reset.
455 * Caution: On this STM32 series, if several ADC instances are available
456 * on the selected device, RCC ADC reset will reset
457 * all ADC instances belonging to the common ADC instance.
458 * Refer to function @ref LL_ADC_CommonDeInit().
459 * @param ADCx ADC instance
460 * @retval An ErrorStatus enumeration value:
461 * - SUCCESS: ADC registers are de-initialized
462 * - ERROR: ADC registers are not de-initialized
463 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)464 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
465 {
466 ErrorStatus status = SUCCESS;
467
468 __IO uint32_t timeout_cpu_cycles = 0UL;
469
470 /* Check the parameters */
471 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
472
473 /* Disable ADC instance if not already disabled. */
474 if (LL_ADC_IsEnabled(ADCx) == 1UL)
475 {
476 /* Stop potential ADC conversion on going on ADC group regular. */
477 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
478 {
479 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
480 {
481 LL_ADC_REG_StopConversion(ADCx);
482 }
483 }
484
485 /* Stop potential ADC conversion on going on ADC group injected. */
486 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
487 {
488 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
489 {
490 LL_ADC_INJ_StopConversion(ADCx);
491 }
492 }
493
494 /* Wait for ADC conversions are effectively stopped */
495 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
496 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
497 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
498 {
499 timeout_cpu_cycles--;
500 if (timeout_cpu_cycles == 0UL)
501 {
502 /* Time-out error */
503 status = ERROR;
504 break;
505 }
506 }
507
508 /* Flush group injected contexts queue (register JSQR): */
509 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
510 /* contexts queue is maintained with the last active context). */
511 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
512
513 /* Disable the ADC instance */
514 LL_ADC_Disable(ADCx);
515
516 /* Wait for ADC instance is effectively disabled */
517 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
518 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
519 {
520 timeout_cpu_cycles--;
521 if (timeout_cpu_cycles == 0UL)
522 {
523 /* Time-out error */
524 status = ERROR;
525 break;
526 }
527 }
528 }
529
530 /* Check whether ADC state is compliant with expected state */
531 if (READ_BIT(ADCx->CR,
532 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
533 | ADC_CR_ADDIS | ADC_CR_ADEN)
534 )
535 == 0UL)
536 {
537 /* ========== Reset ADC registers ========== */
538 /* Reset register IER */
539 CLEAR_BIT(ADCx->IER,
540 (LL_ADC_IT_ADRDY
541 | LL_ADC_IT_EOC
542 | LL_ADC_IT_EOS
543 | LL_ADC_IT_OVR
544 | LL_ADC_IT_EOSMP
545 | LL_ADC_IT_JEOC
546 | LL_ADC_IT_JEOS
547 | LL_ADC_IT_JQOVF
548 | LL_ADC_IT_AWD1
549 | LL_ADC_IT_AWD2
550 | LL_ADC_IT_AWD3
551 )
552 );
553
554 /* Reset register ISR */
555 SET_BIT(ADCx->ISR,
556 (LL_ADC_FLAG_ADRDY
557 | LL_ADC_FLAG_EOC
558 | LL_ADC_FLAG_EOS
559 | LL_ADC_FLAG_OVR
560 | LL_ADC_FLAG_EOSMP
561 | LL_ADC_FLAG_JEOC
562 | LL_ADC_FLAG_JEOS
563 | LL_ADC_FLAG_JQOVF
564 | LL_ADC_FLAG_AWD1
565 | LL_ADC_FLAG_AWD2
566 | LL_ADC_FLAG_AWD3
567 )
568 );
569
570 /* Reset register CR */
571 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
572 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
573 /* access mode "read-set": no direct reset applicable. */
574 /* - Reset Calibration mode to default setting (single ended). */
575 /* - Disable ADC internal voltage regulator. */
576 /* - Enable ADC deep power down. */
577 /* Note: ADC internal voltage regulator disable and ADC deep power */
578 /* down enable are conditioned to ADC state disabled: */
579 /* already done above. */
580 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
581 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
582
583 /* Reset register CFGR */
584 MODIFY_REG(ADCx->CFGR,
585 (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
586 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
587 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
588 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
589 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
590 | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN),
591 ADC_CFGR_JQDIS
592 );
593
594 /* Reset register CFGR2 */
595 CLEAR_BIT(ADCx->CFGR2,
596 (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
597 | ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG
598 | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
599 );
600
601 /* Reset register SMPR1 */
602 CLEAR_BIT(ADCx->SMPR1,
603 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
604 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
605 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
606 );
607
608 /* Reset register SMPR2 */
609 CLEAR_BIT(ADCx->SMPR2,
610 (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
611 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
612 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
613 );
614
615 /* Reset register TR1 */
616 MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT | ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
617
618 /* Reset register TR2 */
619 MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
620
621 /* Reset register TR3 */
622 MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
623
624 /* Reset register SQR1 */
625 CLEAR_BIT(ADCx->SQR1,
626 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
627 | ADC_SQR1_SQ1 | ADC_SQR1_L)
628 );
629
630 /* Reset register SQR2 */
631 CLEAR_BIT(ADCx->SQR2,
632 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
633 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
634 );
635
636 /* Reset register SQR3 */
637 CLEAR_BIT(ADCx->SQR3,
638 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
639 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
640 );
641
642 /* Reset register SQR4 */
643 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
644
645 /* Reset register JSQR */
646 CLEAR_BIT(ADCx->JSQR,
647 (ADC_JSQR_JL
648 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
649 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
650 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
651 );
652
653 /* Reset register DR */
654 /* Note: bits in access mode read only, no direct reset applicable */
655
656 /* Reset register OFR1 */
657 CLEAR_BIT(ADCx->OFR1,
658 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN | ADC_OFR1_OFFSETPOS);
659 /* Reset register OFR2 */
660 CLEAR_BIT(ADCx->OFR2,
661 ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN | ADC_OFR2_OFFSETPOS);
662 /* Reset register OFR3 */
663 CLEAR_BIT(ADCx->OFR3,
664 ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS);
665 /* Reset register OFR4 */
666 CLEAR_BIT(ADCx->OFR4,
667 ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS);
668
669 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
670 /* Note: bits in access mode read only, no direct reset applicable */
671
672 /* Reset register AWD2CR */
673 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
674
675 /* Reset register AWD3CR */
676 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
677
678 /* Reset register DIFSEL */
679 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
680
681 /* Reset register CALFACT */
682 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
683 }
684 else
685 {
686 /* ADC instance is in an unknown state */
687 /* Need to performing a hard reset of ADC instance, using high level */
688 /* clock source RCC ADC reset. */
689 /* Caution: On this STM32 series, if several ADC instances are available */
690 /* on the selected device, RCC ADC reset will reset */
691 /* all ADC instances belonging to the common ADC instance. */
692 /* Caution: On this STM32 series, if several ADC instances are available */
693 /* on the selected device, RCC ADC reset will reset */
694 /* all ADC instances belonging to the common ADC instance. */
695 status = ERROR;
696 }
697
698 return status;
699 }
700
701 /**
702 * @brief Initialize some features of ADC instance.
703 * @note These parameters have an impact on ADC scope: ADC instance.
704 * Affects both group regular and group injected (availability
705 * of ADC group injected depends on STM32 series).
706 * Refer to corresponding unitary functions into
707 * @ref ADC_LL_EF_Configuration_ADC_Instance .
708 * @note The setting of these parameters by function @ref LL_ADC_Init()
709 * is conditioned to ADC state:
710 * ADC instance must be disabled.
711 * This condition is applied to all ADC features, for efficiency
712 * and compatibility over all STM32 series. However, the different
713 * features can be set under different ADC state conditions
714 * (setting possible with ADC enabled without conversion on going,
715 * ADC enabled with conversion on going, ...)
716 * Each feature can be updated afterwards with a unitary function
717 * and potentially with ADC in a different state than disabled,
718 * refer to description of each function for setting
719 * conditioned to ADC state.
720 * @note After using this function, some other features must be configured
721 * using LL unitary functions.
722 * The minimum configuration remaining to be done is:
723 * - Set ADC group regular or group injected sequencer:
724 * map channel on the selected sequencer rank.
725 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
726 * - Set ADC channel sampling time
727 * Refer to function LL_ADC_SetChannelSamplingTime();
728 * @param ADCx ADC instance
729 * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
730 * @retval An ErrorStatus enumeration value:
731 * - SUCCESS: ADC registers are initialized
732 * - ERROR: ADC registers are not initialized
733 */
LL_ADC_Init(ADC_TypeDef * ADCx,const LL_ADC_InitTypeDef * pADC_InitStruct)734 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct)
735 {
736 ErrorStatus status = SUCCESS;
737
738 /* Check the parameters */
739 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
740
741 assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
742 assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
743 assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
744
745 /* Note: Hardware constraint (refer to description of this function): */
746 /* ADC instance must be disabled. */
747 if (LL_ADC_IsEnabled(ADCx) == 0UL)
748 {
749 /* Configuration of ADC hierarchical scope: */
750 /* - ADC instance */
751 /* - Set ADC data resolution */
752 /* - Set ADC conversion data alignment */
753 /* - Set ADC low power mode */
754 MODIFY_REG(ADCx->CFGR,
755 ADC_CFGR_RES
756 | ADC_CFGR_ALIGN
757 | ADC_CFGR_AUTDLY
758 ,
759 pADC_InitStruct->Resolution
760 | pADC_InitStruct->DataAlignment
761 | pADC_InitStruct->LowPowerMode
762 );
763
764 }
765 else
766 {
767 /* Initialization error: ADC instance is not disabled. */
768 status = ERROR;
769 }
770
771 return status;
772 }
773
774 /**
775 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
776 * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
777 * whose fields will be set to default values.
778 * @retval None
779 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * pADC_InitStruct)780 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
781 {
782 /* Set pADC_InitStruct fields to default values */
783 /* Set fields of ADC instance */
784 pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
785 pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
786 pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
787
788 }
789
790 /**
791 * @brief Initialize some features of ADC group regular.
792 * @note These parameters have an impact on ADC scope: ADC group regular.
793 * Refer to corresponding unitary functions into
794 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
795 * (functions with prefix "REG").
796 * @note The setting of these parameters by function @ref LL_ADC_Init()
797 * is conditioned to ADC state:
798 * ADC instance must be disabled.
799 * This condition is applied to all ADC features, for efficiency
800 * and compatibility over all STM32 series. However, the different
801 * features can be set under different ADC state conditions
802 * (setting possible with ADC enabled without conversion on going,
803 * ADC enabled with conversion on going, ...)
804 * Each feature can be updated afterwards with a unitary function
805 * and potentially with ADC in a different state than disabled,
806 * refer to description of each function for setting
807 * conditioned to ADC state.
808 * @note After using this function, other features must be configured
809 * using LL unitary functions.
810 * The minimum configuration remaining to be done is:
811 * - Set ADC group regular or group injected sequencer:
812 * map channel on the selected sequencer rank.
813 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
814 * - Set ADC channel sampling time
815 * Refer to function LL_ADC_SetChannelSamplingTime();
816 * @param ADCx ADC instance
817 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
818 * @retval An ErrorStatus enumeration value:
819 * - SUCCESS: ADC registers are initialized
820 * - ERROR: ADC registers are not initialized
821 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,const LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)822 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
823 {
824 ErrorStatus status = SUCCESS;
825
826 /* Check the parameters */
827 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
828 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
829 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
830 if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
831 {
832 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
833
834 /* ADC group regular continuous mode and discontinuous mode */
835 /* can not be enabled simultenaeously */
836 assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
837 || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
838 }
839 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
840 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
841 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
842
843 /* Note: Hardware constraint (refer to description of this function): */
844 /* ADC instance must be disabled. */
845 if (LL_ADC_IsEnabled(ADCx) == 0UL)
846 {
847 /* Configuration of ADC hierarchical scope: */
848 /* - ADC group regular */
849 /* - Set ADC group regular trigger source */
850 /* - Set ADC group regular sequencer length */
851 /* - Set ADC group regular sequencer discontinuous mode */
852 /* - Set ADC group regular continuous mode */
853 /* - Set ADC group regular conversion data transfer: no transfer or */
854 /* transfer by DMA, and DMA requests mode */
855 /* - Set ADC group regular overrun behavior */
856 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
857 /* setting of trigger source to SW start. */
858 if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
859 {
860 MODIFY_REG(ADCx->CFGR,
861 ADC_CFGR_EXTSEL
862 | ADC_CFGR_EXTEN
863 | ADC_CFGR_DISCEN
864 | ADC_CFGR_DISCNUM
865 | ADC_CFGR_CONT
866 | ADC_CFGR_ADFCFG
867 | ADC_CFGR_DMAEN
868 | ADC_CFGR_DMACFG
869 | ADC_CFGR_OVRMOD
870 ,
871 pADC_RegInitStruct->TriggerSource
872 | pADC_RegInitStruct->SequencerDiscont
873 | pADC_RegInitStruct->ContinuousMode
874 | pADC_RegInitStruct->DMATransfer
875 | pADC_RegInitStruct->Overrun
876 );
877 }
878 else
879 {
880 MODIFY_REG(ADCx->CFGR,
881 ADC_CFGR_EXTSEL
882 | ADC_CFGR_EXTEN
883 | ADC_CFGR_DISCEN
884 | ADC_CFGR_DISCNUM
885 | ADC_CFGR_CONT
886 | ADC_CFGR_ADFCFG
887 | ADC_CFGR_DMAEN
888 | ADC_CFGR_DMACFG
889 | ADC_CFGR_OVRMOD
890 ,
891 pADC_RegInitStruct->TriggerSource
892 | LL_ADC_REG_SEQ_DISCONT_DISABLE
893 | pADC_RegInitStruct->ContinuousMode
894 | pADC_RegInitStruct->DMATransfer
895 | pADC_RegInitStruct->Overrun
896 );
897 }
898
899 /* Set ADC group regular sequencer length and scan direction */
900 LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
901 }
902 else
903 {
904 /* Initialization error: ADC instance is not disabled. */
905 status = ERROR;
906 }
907 return status;
908 }
909
910 /**
911 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
912 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
913 * whose fields will be set to default values.
914 * @retval None
915 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)916 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
917 {
918 /* Set pADC_RegInitStruct fields to default values */
919 /* Set fields of ADC group regular */
920 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
921 /* setting of trigger source to SW start. */
922 pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
923 pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
924 pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
925 pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
926 pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
927 pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
928 }
929
930 /**
931 * @brief Initialize some features of ADC group injected.
932 * @note These parameters have an impact on ADC scope: ADC group injected.
933 * Refer to corresponding unitary functions into
934 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
935 * (functions with prefix "INJ").
936 * @note The setting of these parameters by function @ref LL_ADC_Init()
937 * is conditioned to ADC state:
938 * ADC instance must be disabled.
939 * This condition is applied to all ADC features, for efficiency
940 * and compatibility over all STM32 series. However, the different
941 * features can be set under different ADC state conditions
942 * (setting possible with ADC enabled without conversion on going,
943 * ADC enabled with conversion on going, ...)
944 * Each feature can be updated afterwards with a unitary function
945 * and potentially with ADC in a different state than disabled,
946 * refer to description of each function for setting
947 * conditioned to ADC state.
948 * @note After using this function, other features must be configured
949 * using LL unitary functions.
950 * The minimum configuration remaining to be done is:
951 * - Set ADC group injected sequencer:
952 * map channel on the selected sequencer rank.
953 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
954 * - Set ADC channel sampling time
955 * Refer to function LL_ADC_SetChannelSamplingTime();
956 * @note Caution if feature ADC group injected contexts queue is enabled
957 * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
958 * using successively several times this function will appear as
959 * having no effect.
960 * To set several features of ADC group injected, use
961 * function @ref LL_ADC_INJ_ConfigQueueContext().
962 * @param ADCx ADC instance
963 * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
964 * @retval An ErrorStatus enumeration value:
965 * - SUCCESS: ADC registers are initialized
966 * - ERROR: ADC registers are not initialized
967 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,const LL_ADC_INJ_InitTypeDef * pADC_InjInitStruct)968 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
969 {
970 ErrorStatus status = SUCCESS;
971
972 /* Check the parameters */
973 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
974 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(pADC_InjInitStruct->TriggerSource));
975 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_InjInitStruct->SequencerLength));
976 if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
977 {
978 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_InjInitStruct->SequencerDiscont));
979 }
980 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_InjInitStruct->TrigAuto));
981
982 /* Note: Hardware constraint (refer to description of this function): */
983 /* ADC instance must be disabled. */
984 if (LL_ADC_IsEnabled(ADCx) == 0UL)
985 {
986 /* Configuration of ADC hierarchical scope: */
987 /* - ADC group injected */
988 /* - Set ADC group injected trigger source */
989 /* - Set ADC group injected sequencer length */
990 /* - Set ADC group injected sequencer discontinuous mode */
991 /* - Set ADC group injected conversion trigger: independent or */
992 /* from ADC group regular */
993 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
994 /* setting of trigger source to SW start. */
995 if (pADC_InjInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
996 {
997 MODIFY_REG(ADCx->CFGR,
998 ADC_CFGR_JDISCEN
999 | ADC_CFGR_JAUTO
1000 ,
1001 pADC_InjInitStruct->SequencerDiscont
1002 | pADC_InjInitStruct->TrigAuto
1003 );
1004 }
1005 else
1006 {
1007 MODIFY_REG(ADCx->CFGR,
1008 ADC_CFGR_JDISCEN
1009 | ADC_CFGR_JAUTO
1010 ,
1011 LL_ADC_REG_SEQ_DISCONT_DISABLE
1012 | pADC_InjInitStruct->TrigAuto
1013 );
1014 }
1015
1016 MODIFY_REG(ADCx->JSQR,
1017 ADC_JSQR_JEXTSEL
1018 | ADC_JSQR_JEXTEN
1019 | ADC_JSQR_JL
1020 ,
1021 pADC_InjInitStruct->TriggerSource
1022 | pADC_InjInitStruct->SequencerLength
1023 );
1024 }
1025 else
1026 {
1027 /* Initialization error: ADC instance is not disabled. */
1028 status = ERROR;
1029 }
1030 return status;
1031 }
1032
1033 /**
1034 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1035 * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1036 * whose fields will be set to default values.
1037 * @retval None
1038 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * pADC_InjInitStruct)1039 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
1040 {
1041 /* Set pADC_InjInitStruct fields to default values */
1042 /* Set fields of ADC group injected */
1043 pADC_InjInitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1044 pADC_InjInitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1045 pADC_InjInitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1046 pADC_InjInitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1047 }
1048
1049 /**
1050 * @}
1051 */
1052
1053 /**
1054 * @}
1055 */
1056
1057 /**
1058 * @}
1059 */
1060
1061 #endif /* ADC1 || ADC2 */
1062
1063 /**
1064 * @}
1065 */
1066
1067 #endif /* USE_FULL_LL_DRIVER */
1068
