1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2022 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare:
88 to use the Timer to generate an Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function HAL_TIM_RegisterCallback() to register a callback.
118 HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
142 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
143 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
144 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
145 (+) TriggerCallback : TIM Trigger Callback.
146 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
147 (+) IC_CaptureCallback : TIM Input Capture Callback.
148 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
149 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
150 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
151 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
152 (+) ErrorCallback : TIM Error Callback.
153 (+) CommutationCallback : TIM Commutation Callback.
154 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
155 (+) BreakCallback : TIM Break Callback.
156 (+) Break2Callback : TIM Break2 Callback.
157 (+) EncoderIndexCallback : TIM Encoder Index Callback.
158 (+) DirectionChangeCallback : TIM Direction Change Callback
159 (+) IndexErrorCallback : TIM Index Error Callback.
160 (+) TransitionErrorCallback : TIM Transition Error Callback
161
162 [..]
163 By default, after the Init and when the state is HAL_TIM_STATE_RESET
164 all interrupt callbacks are set to the corresponding weak functions:
165 examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
166
167 [..]
168 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
169 functionalities in the Init / DeInit only when these callbacks are null
170 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
171 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
172
173 [..]
174 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
175 Exception done MspInit / MspDeInit that can be registered / unregistered
176 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
177 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
178 In that case first register the MspInit/MspDeInit user callbacks
179 using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
180
181 [..]
182 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
183 not defined, the callback registration feature is not available and all callbacks
184 are set to the corresponding weak functions.
185
186 @endverbatim
187 ******************************************************************************
188 */
189
190 /* Includes ------------------------------------------------------------------*/
191 #include "stm32h7rsxx_hal.h"
192
193 /** @addtogroup STM32H7RSxx_HAL_Driver
194 * @{
195 */
196
197 /** @defgroup TIM TIM
198 * @brief TIM HAL module driver
199 * @{
200 */
201
202 #ifdef HAL_TIM_MODULE_ENABLED
203
204 /* Private typedef -----------------------------------------------------------*/
205 /* Private define ------------------------------------------------------------*/
206 /* Private macros ------------------------------------------------------------*/
207 /* Private variables ---------------------------------------------------------*/
208 /* Private function prototypes -----------------------------------------------*/
209 /** @addtogroup TIM_Private_Functions
210 * @{
211 */
212 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
213 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
214 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
215 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
216 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
217 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
218 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
219 uint32_t TIM_ICFilter);
220 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
221 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
222 uint32_t TIM_ICFilter);
223 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
224 uint32_t TIM_ICFilter);
225 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
226 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
227 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
228 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
229 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
230 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
231 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
232 const TIM_SlaveConfigTypeDef *sSlaveConfig);
233 /**
234 * @}
235 */
236 /* Exported functions --------------------------------------------------------*/
237
238 /** @defgroup TIM_Exported_Functions TIM Exported Functions
239 * @{
240 */
241
242 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
243 * @brief Time Base functions
244 *
245 @verbatim
246 ==============================================================================
247 ##### Time Base functions #####
248 ==============================================================================
249 [..]
250 This section provides functions allowing to:
251 (+) Initialize and configure the TIM base.
252 (+) De-initialize the TIM base.
253 (+) Start the Time Base.
254 (+) Stop the Time Base.
255 (+) Start the Time Base and enable interrupt.
256 (+) Stop the Time Base and disable interrupt.
257 (+) Start the Time Base and enable DMA transfer.
258 (+) Stop the Time Base and disable DMA transfer.
259
260 @endverbatim
261 * @{
262 */
263 /**
264 * @brief Initializes the TIM Time base Unit according to the specified
265 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
266 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
267 * requires a timer reset to avoid unexpected direction
268 * due to DIR bit readonly in center aligned mode.
269 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
270 * @param htim TIM Base handle
271 * @retval HAL status
272 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)273 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
274 {
275 /* Check the TIM handle allocation */
276 if (htim == NULL)
277 {
278 return HAL_ERROR;
279 }
280
281 /* Check the parameters */
282 assert_param(IS_TIM_INSTANCE(htim->Instance));
283 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
284 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
285 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
286 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
287
288 if (htim->State == HAL_TIM_STATE_RESET)
289 {
290 /* Allocate lock resource and initialize it */
291 htim->Lock = HAL_UNLOCKED;
292
293 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
294 /* Reset interrupt callbacks to legacy weak callbacks */
295 TIM_ResetCallback(htim);
296
297 if (htim->Base_MspInitCallback == NULL)
298 {
299 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
300 }
301 /* Init the low level hardware : GPIO, CLOCK, NVIC */
302 htim->Base_MspInitCallback(htim);
303 #else
304 /* Init the low level hardware : GPIO, CLOCK, NVIC */
305 HAL_TIM_Base_MspInit(htim);
306 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
307 }
308
309 /* Set the TIM state */
310 htim->State = HAL_TIM_STATE_BUSY;
311
312 /* Set the Time Base configuration */
313 TIM_Base_SetConfig(htim->Instance, &htim->Init);
314
315 /* Initialize the DMA burst operation state */
316 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
317
318 /* Initialize the TIM channels state */
319 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
320 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
321
322 /* Initialize the TIM state*/
323 htim->State = HAL_TIM_STATE_READY;
324
325 return HAL_OK;
326 }
327
328 /**
329 * @brief DeInitializes the TIM Base peripheral
330 * @param htim TIM Base handle
331 * @retval HAL status
332 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)333 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
334 {
335 /* Check the parameters */
336 assert_param(IS_TIM_INSTANCE(htim->Instance));
337
338 htim->State = HAL_TIM_STATE_BUSY;
339
340 /* Disable the TIM Peripheral Clock */
341 __HAL_TIM_DISABLE(htim);
342
343 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
344 if (htim->Base_MspDeInitCallback == NULL)
345 {
346 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
347 }
348 /* DeInit the low level hardware */
349 htim->Base_MspDeInitCallback(htim);
350 #else
351 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
352 HAL_TIM_Base_MspDeInit(htim);
353 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
354
355 /* Change the DMA burst operation state */
356 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
357
358 /* Change the TIM channels state */
359 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
360 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
361
362 /* Change TIM state */
363 htim->State = HAL_TIM_STATE_RESET;
364
365 /* Release Lock */
366 __HAL_UNLOCK(htim);
367
368 return HAL_OK;
369 }
370
371 /**
372 * @brief Initializes the TIM Base MSP.
373 * @param htim TIM Base handle
374 * @retval None
375 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)376 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
377 {
378 /* Prevent unused argument(s) compilation warning */
379 UNUSED(htim);
380
381 /* NOTE : This function should not be modified, when the callback is needed,
382 the HAL_TIM_Base_MspInit could be implemented in the user file
383 */
384 }
385
386 /**
387 * @brief DeInitializes TIM Base MSP.
388 * @param htim TIM Base handle
389 * @retval None
390 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)391 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
392 {
393 /* Prevent unused argument(s) compilation warning */
394 UNUSED(htim);
395
396 /* NOTE : This function should not be modified, when the callback is needed,
397 the HAL_TIM_Base_MspDeInit could be implemented in the user file
398 */
399 }
400
401
402 /**
403 * @brief Starts the TIM Base generation.
404 * @param htim TIM Base handle
405 * @retval HAL status
406 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)407 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
408 {
409 uint32_t tmpsmcr;
410
411 /* Check the parameters */
412 assert_param(IS_TIM_INSTANCE(htim->Instance));
413
414 /* Check the TIM state */
415 if (htim->State != HAL_TIM_STATE_READY)
416 {
417 return HAL_ERROR;
418 }
419
420 /* Set the TIM state */
421 htim->State = HAL_TIM_STATE_BUSY;
422
423 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
424 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
425 {
426 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
427 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
428 {
429 __HAL_TIM_ENABLE(htim);
430 }
431 }
432 else
433 {
434 __HAL_TIM_ENABLE(htim);
435 }
436
437 /* Return function status */
438 return HAL_OK;
439 }
440
441 /**
442 * @brief Stops the TIM Base generation.
443 * @param htim TIM Base handle
444 * @retval HAL status
445 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)446 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
447 {
448 /* Check the parameters */
449 assert_param(IS_TIM_INSTANCE(htim->Instance));
450
451 /* Disable the Peripheral */
452 __HAL_TIM_DISABLE(htim);
453
454 /* Set the TIM state */
455 htim->State = HAL_TIM_STATE_READY;
456
457 /* Return function status */
458 return HAL_OK;
459 }
460
461 /**
462 * @brief Starts the TIM Base generation in interrupt mode.
463 * @param htim TIM Base handle
464 * @retval HAL status
465 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)466 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
467 {
468 uint32_t tmpsmcr;
469
470 /* Check the parameters */
471 assert_param(IS_TIM_INSTANCE(htim->Instance));
472
473 /* Check the TIM state */
474 if (htim->State != HAL_TIM_STATE_READY)
475 {
476 return HAL_ERROR;
477 }
478
479 /* Set the TIM state */
480 htim->State = HAL_TIM_STATE_BUSY;
481
482 /* Enable the TIM Update interrupt */
483 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
484
485 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
486 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
487 {
488 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
489 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
490 {
491 __HAL_TIM_ENABLE(htim);
492 }
493 }
494 else
495 {
496 __HAL_TIM_ENABLE(htim);
497 }
498
499 /* Return function status */
500 return HAL_OK;
501 }
502
503 /**
504 * @brief Stops the TIM Base generation in interrupt mode.
505 * @param htim TIM Base handle
506 * @retval HAL status
507 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)508 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
509 {
510 /* Check the parameters */
511 assert_param(IS_TIM_INSTANCE(htim->Instance));
512
513 /* Disable the TIM Update interrupt */
514 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
515
516 /* Disable the Peripheral */
517 __HAL_TIM_DISABLE(htim);
518
519 /* Set the TIM state */
520 htim->State = HAL_TIM_STATE_READY;
521
522 /* Return function status */
523 return HAL_OK;
524 }
525
526 /**
527 * @brief Starts the TIM Base generation in DMA mode.
528 * @param htim TIM Base handle
529 * @param pData The source Buffer address.
530 * @param Length The length of data to be transferred from memory to peripheral.
531 * @retval HAL status
532 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,const uint32_t * pData,uint16_t Length)533 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
534 {
535 uint32_t tmpsmcr;
536
537 /* Check the parameters */
538 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
539
540 /* Set the TIM state */
541 if (htim->State == HAL_TIM_STATE_BUSY)
542 {
543 return HAL_BUSY;
544 }
545 else if (htim->State == HAL_TIM_STATE_READY)
546 {
547 if ((pData == NULL) || (Length == 0U))
548 {
549 return HAL_ERROR;
550 }
551 else
552 {
553 htim->State = HAL_TIM_STATE_BUSY;
554 }
555 }
556 else
557 {
558 return HAL_ERROR;
559 }
560
561 /* Set the DMA Period elapsed callbacks */
562 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
563 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
564
565 /* Set the DMA error callback */
566 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
567
568 /* Enable the DMA channel */
569 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
570 Length) != HAL_OK)
571 {
572 /* Return error status */
573 return HAL_ERROR;
574 }
575
576 /* Enable the TIM Update DMA request */
577 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
578
579 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
580 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
581 {
582 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
583 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
584 {
585 __HAL_TIM_ENABLE(htim);
586 }
587 }
588 else
589 {
590 __HAL_TIM_ENABLE(htim);
591 }
592
593 /* Return function status */
594 return HAL_OK;
595 }
596
597 /**
598 * @brief Stops the TIM Base generation in DMA mode.
599 * @param htim TIM Base handle
600 * @retval HAL status
601 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)602 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
603 {
604 /* Check the parameters */
605 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
606
607 /* Disable the TIM Update DMA request */
608 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
609
610 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
611
612 /* Disable the Peripheral */
613 __HAL_TIM_DISABLE(htim);
614
615 /* Set the TIM state */
616 htim->State = HAL_TIM_STATE_READY;
617
618 /* Return function status */
619 return HAL_OK;
620 }
621
622 /**
623 * @}
624 */
625
626 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
627 * @brief TIM Output Compare functions
628 *
629 @verbatim
630 ==============================================================================
631 ##### TIM Output Compare functions #####
632 ==============================================================================
633 [..]
634 This section provides functions allowing to:
635 (+) Initialize and configure the TIM Output Compare.
636 (+) De-initialize the TIM Output Compare.
637 (+) Start the TIM Output Compare.
638 (+) Stop the TIM Output Compare.
639 (+) Start the TIM Output Compare and enable interrupt.
640 (+) Stop the TIM Output Compare and disable interrupt.
641 (+) Start the TIM Output Compare and enable DMA transfer.
642 (+) Stop the TIM Output Compare and disable DMA transfer.
643
644 @endverbatim
645 * @{
646 */
647 /**
648 * @brief Initializes the TIM Output Compare according to the specified
649 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
650 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
651 * requires a timer reset to avoid unexpected direction
652 * due to DIR bit readonly in center aligned mode.
653 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
654 * @param htim TIM Output Compare handle
655 * @retval HAL status
656 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)657 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
658 {
659 /* Check the TIM handle allocation */
660 if (htim == NULL)
661 {
662 return HAL_ERROR;
663 }
664
665 /* Check the parameters */
666 assert_param(IS_TIM_INSTANCE(htim->Instance));
667 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
668 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
669 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
670 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
671
672 if (htim->State == HAL_TIM_STATE_RESET)
673 {
674 /* Allocate lock resource and initialize it */
675 htim->Lock = HAL_UNLOCKED;
676
677 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
678 /* Reset interrupt callbacks to legacy weak callbacks */
679 TIM_ResetCallback(htim);
680
681 if (htim->OC_MspInitCallback == NULL)
682 {
683 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
684 }
685 /* Init the low level hardware : GPIO, CLOCK, NVIC */
686 htim->OC_MspInitCallback(htim);
687 #else
688 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
689 HAL_TIM_OC_MspInit(htim);
690 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
691 }
692
693 /* Set the TIM state */
694 htim->State = HAL_TIM_STATE_BUSY;
695
696 /* Init the base time for the Output Compare */
697 TIM_Base_SetConfig(htim->Instance, &htim->Init);
698
699 /* Initialize the DMA burst operation state */
700 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
701
702 /* Initialize the TIM channels state */
703 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
704 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
705
706 /* Initialize the TIM state*/
707 htim->State = HAL_TIM_STATE_READY;
708
709 return HAL_OK;
710 }
711
712 /**
713 * @brief DeInitializes the TIM peripheral
714 * @param htim TIM Output Compare handle
715 * @retval HAL status
716 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)717 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
718 {
719 /* Check the parameters */
720 assert_param(IS_TIM_INSTANCE(htim->Instance));
721
722 htim->State = HAL_TIM_STATE_BUSY;
723
724 /* Disable the TIM Peripheral Clock */
725 __HAL_TIM_DISABLE(htim);
726
727 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
728 if (htim->OC_MspDeInitCallback == NULL)
729 {
730 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
731 }
732 /* DeInit the low level hardware */
733 htim->OC_MspDeInitCallback(htim);
734 #else
735 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
736 HAL_TIM_OC_MspDeInit(htim);
737 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
738
739 /* Change the DMA burst operation state */
740 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
741
742 /* Change the TIM channels state */
743 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
744 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
745
746 /* Change TIM state */
747 htim->State = HAL_TIM_STATE_RESET;
748
749 /* Release Lock */
750 __HAL_UNLOCK(htim);
751
752 return HAL_OK;
753 }
754
755 /**
756 * @brief Initializes the TIM Output Compare MSP.
757 * @param htim TIM Output Compare handle
758 * @retval None
759 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)760 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
761 {
762 /* Prevent unused argument(s) compilation warning */
763 UNUSED(htim);
764
765 /* NOTE : This function should not be modified, when the callback is needed,
766 the HAL_TIM_OC_MspInit could be implemented in the user file
767 */
768 }
769
770 /**
771 * @brief DeInitializes TIM Output Compare MSP.
772 * @param htim TIM Output Compare handle
773 * @retval None
774 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)775 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
776 {
777 /* Prevent unused argument(s) compilation warning */
778 UNUSED(htim);
779
780 /* NOTE : This function should not be modified, when the callback is needed,
781 the HAL_TIM_OC_MspDeInit could be implemented in the user file
782 */
783 }
784
785 /**
786 * @brief Starts the TIM Output Compare signal generation.
787 * @param htim TIM Output Compare handle
788 * @param Channel TIM Channel to be enabled
789 * This parameter can be one of the following values:
790 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
791 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
792 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
793 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
794 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
795 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
796 * @retval HAL status
797 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)798 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
799 {
800 uint32_t tmpsmcr;
801
802 /* Check the parameters */
803 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
804
805 /* Check the TIM channel state */
806 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
807 {
808 return HAL_ERROR;
809 }
810
811 /* Set the TIM channel state */
812 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
813
814 /* Enable the Output compare channel */
815 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
816
817 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
818 {
819 /* Enable the main output */
820 __HAL_TIM_MOE_ENABLE(htim);
821 }
822
823 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
824 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
825 {
826 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
827 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
828 {
829 __HAL_TIM_ENABLE(htim);
830 }
831 }
832 else
833 {
834 __HAL_TIM_ENABLE(htim);
835 }
836
837 /* Return function status */
838 return HAL_OK;
839 }
840
841 /**
842 * @brief Stops the TIM Output Compare signal generation.
843 * @param htim TIM Output Compare handle
844 * @param Channel TIM Channel to be disabled
845 * This parameter can be one of the following values:
846 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
847 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
848 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
849 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
850 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
851 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
852 * @retval HAL status
853 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)854 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
855 {
856 /* Check the parameters */
857 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
858
859 /* Disable the Output compare channel */
860 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
861
862 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
863 {
864 /* Disable the Main Output */
865 __HAL_TIM_MOE_DISABLE(htim);
866 }
867
868 /* Disable the Peripheral */
869 __HAL_TIM_DISABLE(htim);
870
871 /* Set the TIM channel state */
872 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
873
874 /* Return function status */
875 return HAL_OK;
876 }
877
878 /**
879 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
880 * @param htim TIM Output Compare handle
881 * @param Channel TIM Channel to be enabled
882 * This parameter can be one of the following values:
883 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
884 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
885 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
886 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
887 * @retval HAL status
888 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)889 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
890 {
891 HAL_StatusTypeDef status = HAL_OK;
892 uint32_t tmpsmcr;
893
894 /* Check the parameters */
895 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
896
897 /* Check the TIM channel state */
898 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
899 {
900 return HAL_ERROR;
901 }
902
903 /* Set the TIM channel state */
904 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
905
906 switch (Channel)
907 {
908 case TIM_CHANNEL_1:
909 {
910 /* Enable the TIM Capture/Compare 1 interrupt */
911 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
912 break;
913 }
914
915 case TIM_CHANNEL_2:
916 {
917 /* Enable the TIM Capture/Compare 2 interrupt */
918 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
919 break;
920 }
921
922 case TIM_CHANNEL_3:
923 {
924 /* Enable the TIM Capture/Compare 3 interrupt */
925 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
926 break;
927 }
928
929 case TIM_CHANNEL_4:
930 {
931 /* Enable the TIM Capture/Compare 4 interrupt */
932 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
933 break;
934 }
935
936 default:
937 status = HAL_ERROR;
938 break;
939 }
940
941 if (status == HAL_OK)
942 {
943 /* Enable the Output compare channel */
944 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
945
946 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
947 {
948 /* Enable the main output */
949 __HAL_TIM_MOE_ENABLE(htim);
950 }
951
952 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
953 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
954 {
955 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
956 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
957 {
958 __HAL_TIM_ENABLE(htim);
959 }
960 }
961 else
962 {
963 __HAL_TIM_ENABLE(htim);
964 }
965 }
966
967 /* Return function status */
968 return status;
969 }
970
971 /**
972 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
973 * @param htim TIM Output Compare handle
974 * @param Channel TIM Channel to be disabled
975 * This parameter can be one of the following values:
976 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
977 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
978 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
979 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
980 * @retval HAL status
981 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)982 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
983 {
984 HAL_StatusTypeDef status = HAL_OK;
985
986 /* Check the parameters */
987 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
988
989 switch (Channel)
990 {
991 case TIM_CHANNEL_1:
992 {
993 /* Disable the TIM Capture/Compare 1 interrupt */
994 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
995 break;
996 }
997
998 case TIM_CHANNEL_2:
999 {
1000 /* Disable the TIM Capture/Compare 2 interrupt */
1001 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1002 break;
1003 }
1004
1005 case TIM_CHANNEL_3:
1006 {
1007 /* Disable the TIM Capture/Compare 3 interrupt */
1008 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1009 break;
1010 }
1011
1012 case TIM_CHANNEL_4:
1013 {
1014 /* Disable the TIM Capture/Compare 4 interrupt */
1015 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1016 break;
1017 }
1018
1019 default:
1020 status = HAL_ERROR;
1021 break;
1022 }
1023
1024 if (status == HAL_OK)
1025 {
1026 /* Disable the Output compare channel */
1027 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1028
1029 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1030 {
1031 /* Disable the Main Output */
1032 __HAL_TIM_MOE_DISABLE(htim);
1033 }
1034
1035 /* Disable the Peripheral */
1036 __HAL_TIM_DISABLE(htim);
1037
1038 /* Set the TIM channel state */
1039 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1040 }
1041
1042 /* Return function status */
1043 return status;
1044 }
1045
1046 /**
1047 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1048 * @param htim TIM Output Compare handle
1049 * @param Channel TIM Channel to be enabled
1050 * This parameter can be one of the following values:
1051 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1052 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1053 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1054 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1055 * @param pData The source Buffer address.
1056 * @param Length The length of data to be transferred from memory to TIM peripheral
1057 * @retval HAL status
1058 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1059 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1060 uint16_t Length)
1061 {
1062 HAL_StatusTypeDef status = HAL_OK;
1063 uint32_t tmpsmcr;
1064
1065 /* Check the parameters */
1066 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1067
1068 /* Set the TIM channel state */
1069 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1070 {
1071 return HAL_BUSY;
1072 }
1073 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1074 {
1075 if ((pData == NULL) || (Length == 0U))
1076 {
1077 return HAL_ERROR;
1078 }
1079 else
1080 {
1081 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1082 }
1083 }
1084 else
1085 {
1086 return HAL_ERROR;
1087 }
1088
1089 switch (Channel)
1090 {
1091 case TIM_CHANNEL_1:
1092 {
1093 /* Set the DMA compare callbacks */
1094 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1095 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1096
1097 /* Set the DMA error callback */
1098 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1099
1100 /* Enable the DMA channel */
1101 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1102 Length) != HAL_OK)
1103 {
1104 /* Return error status */
1105 return HAL_ERROR;
1106 }
1107
1108 /* Enable the TIM Capture/Compare 1 DMA request */
1109 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1110 break;
1111 }
1112
1113 case TIM_CHANNEL_2:
1114 {
1115 /* Set the DMA compare callbacks */
1116 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1117 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1118
1119 /* Set the DMA error callback */
1120 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1121
1122 /* Enable the DMA channel */
1123 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1124 Length) != HAL_OK)
1125 {
1126 /* Return error status */
1127 return HAL_ERROR;
1128 }
1129
1130 /* Enable the TIM Capture/Compare 2 DMA request */
1131 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1132 break;
1133 }
1134
1135 case TIM_CHANNEL_3:
1136 {
1137 /* Set the DMA compare callbacks */
1138 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1139 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1140
1141 /* Set the DMA error callback */
1142 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1143
1144 /* Enable the DMA channel */
1145 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1146 Length) != HAL_OK)
1147 {
1148 /* Return error status */
1149 return HAL_ERROR;
1150 }
1151 /* Enable the TIM Capture/Compare 3 DMA request */
1152 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1153 break;
1154 }
1155
1156 case TIM_CHANNEL_4:
1157 {
1158 /* Set the DMA compare callbacks */
1159 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1160 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1161
1162 /* Set the DMA error callback */
1163 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1164
1165 /* Enable the DMA channel */
1166 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1167 Length) != HAL_OK)
1168 {
1169 /* Return error status */
1170 return HAL_ERROR;
1171 }
1172 /* Enable the TIM Capture/Compare 4 DMA request */
1173 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1174 break;
1175 }
1176
1177 default:
1178 status = HAL_ERROR;
1179 break;
1180 }
1181
1182 if (status == HAL_OK)
1183 {
1184 /* Enable the Output compare channel */
1185 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1186
1187 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1188 {
1189 /* Enable the main output */
1190 __HAL_TIM_MOE_ENABLE(htim);
1191 }
1192
1193 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1194 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1195 {
1196 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1197 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1198 {
1199 __HAL_TIM_ENABLE(htim);
1200 }
1201 }
1202 else
1203 {
1204 __HAL_TIM_ENABLE(htim);
1205 }
1206 }
1207
1208 /* Return function status */
1209 return status;
1210 }
1211
1212 /**
1213 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1214 * @param htim TIM Output Compare handle
1215 * @param Channel TIM Channel to be disabled
1216 * This parameter can be one of the following values:
1217 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1218 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1219 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1220 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1221 * @retval HAL status
1222 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1223 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1224 {
1225 HAL_StatusTypeDef status = HAL_OK;
1226
1227 /* Check the parameters */
1228 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1229
1230 switch (Channel)
1231 {
1232 case TIM_CHANNEL_1:
1233 {
1234 /* Disable the TIM Capture/Compare 1 DMA request */
1235 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1236 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1237 break;
1238 }
1239
1240 case TIM_CHANNEL_2:
1241 {
1242 /* Disable the TIM Capture/Compare 2 DMA request */
1243 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1244 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1245 break;
1246 }
1247
1248 case TIM_CHANNEL_3:
1249 {
1250 /* Disable the TIM Capture/Compare 3 DMA request */
1251 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1252 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1253 break;
1254 }
1255
1256 case TIM_CHANNEL_4:
1257 {
1258 /* Disable the TIM Capture/Compare 4 interrupt */
1259 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1260 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1261 break;
1262 }
1263
1264 default:
1265 status = HAL_ERROR;
1266 break;
1267 }
1268
1269 if (status == HAL_OK)
1270 {
1271 /* Disable the Output compare channel */
1272 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1273
1274 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1275 {
1276 /* Disable the Main Output */
1277 __HAL_TIM_MOE_DISABLE(htim);
1278 }
1279
1280 /* Disable the Peripheral */
1281 __HAL_TIM_DISABLE(htim);
1282
1283 /* Set the TIM channel state */
1284 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1285 }
1286
1287 /* Return function status */
1288 return status;
1289 }
1290
1291 /**
1292 * @}
1293 */
1294
1295 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1296 * @brief TIM PWM functions
1297 *
1298 @verbatim
1299 ==============================================================================
1300 ##### TIM PWM functions #####
1301 ==============================================================================
1302 [..]
1303 This section provides functions allowing to:
1304 (+) Initialize and configure the TIM PWM.
1305 (+) De-initialize the TIM PWM.
1306 (+) Start the TIM PWM.
1307 (+) Stop the TIM PWM.
1308 (+) Start the TIM PWM and enable interrupt.
1309 (+) Stop the TIM PWM and disable interrupt.
1310 (+) Start the TIM PWM and enable DMA transfer.
1311 (+) Stop the TIM PWM and disable DMA transfer.
1312
1313 @endverbatim
1314 * @{
1315 */
1316 /**
1317 * @brief Initializes the TIM PWM Time Base according to the specified
1318 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1319 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1320 * requires a timer reset to avoid unexpected direction
1321 * due to DIR bit readonly in center aligned mode.
1322 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1323 * @param htim TIM PWM handle
1324 * @retval HAL status
1325 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1326 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1327 {
1328 /* Check the TIM handle allocation */
1329 if (htim == NULL)
1330 {
1331 return HAL_ERROR;
1332 }
1333
1334 /* Check the parameters */
1335 assert_param(IS_TIM_INSTANCE(htim->Instance));
1336 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1337 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1338 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
1339 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1340
1341 if (htim->State == HAL_TIM_STATE_RESET)
1342 {
1343 /* Allocate lock resource and initialize it */
1344 htim->Lock = HAL_UNLOCKED;
1345
1346 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1347 /* Reset interrupt callbacks to legacy weak callbacks */
1348 TIM_ResetCallback(htim);
1349
1350 if (htim->PWM_MspInitCallback == NULL)
1351 {
1352 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1353 }
1354 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1355 htim->PWM_MspInitCallback(htim);
1356 #else
1357 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1358 HAL_TIM_PWM_MspInit(htim);
1359 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1360 }
1361
1362 /* Set the TIM state */
1363 htim->State = HAL_TIM_STATE_BUSY;
1364
1365 /* Init the base time for the PWM */
1366 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1367
1368 /* Initialize the DMA burst operation state */
1369 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1370
1371 /* Initialize the TIM channels state */
1372 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1373 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1374
1375 /* Initialize the TIM state*/
1376 htim->State = HAL_TIM_STATE_READY;
1377
1378 return HAL_OK;
1379 }
1380
1381 /**
1382 * @brief DeInitializes the TIM peripheral
1383 * @param htim TIM PWM handle
1384 * @retval HAL status
1385 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1386 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1387 {
1388 /* Check the parameters */
1389 assert_param(IS_TIM_INSTANCE(htim->Instance));
1390
1391 htim->State = HAL_TIM_STATE_BUSY;
1392
1393 /* Disable the TIM Peripheral Clock */
1394 __HAL_TIM_DISABLE(htim);
1395
1396 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1397 if (htim->PWM_MspDeInitCallback == NULL)
1398 {
1399 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1400 }
1401 /* DeInit the low level hardware */
1402 htim->PWM_MspDeInitCallback(htim);
1403 #else
1404 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1405 HAL_TIM_PWM_MspDeInit(htim);
1406 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1407
1408 /* Change the DMA burst operation state */
1409 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1410
1411 /* Change the TIM channels state */
1412 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1413 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1414
1415 /* Change TIM state */
1416 htim->State = HAL_TIM_STATE_RESET;
1417
1418 /* Release Lock */
1419 __HAL_UNLOCK(htim);
1420
1421 return HAL_OK;
1422 }
1423
1424 /**
1425 * @brief Initializes the TIM PWM MSP.
1426 * @param htim TIM PWM handle
1427 * @retval None
1428 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1429 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1430 {
1431 /* Prevent unused argument(s) compilation warning */
1432 UNUSED(htim);
1433
1434 /* NOTE : This function should not be modified, when the callback is needed,
1435 the HAL_TIM_PWM_MspInit could be implemented in the user file
1436 */
1437 }
1438
1439 /**
1440 * @brief DeInitializes TIM PWM MSP.
1441 * @param htim TIM PWM handle
1442 * @retval None
1443 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1444 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1445 {
1446 /* Prevent unused argument(s) compilation warning */
1447 UNUSED(htim);
1448
1449 /* NOTE : This function should not be modified, when the callback is needed,
1450 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1451 */
1452 }
1453
1454 /**
1455 * @brief Starts the PWM signal generation.
1456 * @param htim TIM handle
1457 * @param Channel TIM Channels to be enabled
1458 * This parameter can be one of the following values:
1459 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1460 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1461 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1462 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1463 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1464 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1465 * @retval HAL status
1466 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1467 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1468 {
1469 uint32_t tmpsmcr;
1470
1471 /* Check the parameters */
1472 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1473
1474 /* Check the TIM channel state */
1475 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1476 {
1477 return HAL_ERROR;
1478 }
1479
1480 /* Set the TIM channel state */
1481 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1482
1483 /* Enable the Capture compare channel */
1484 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1485
1486 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1487 {
1488 /* Enable the main output */
1489 __HAL_TIM_MOE_ENABLE(htim);
1490 }
1491
1492 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1493 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1494 {
1495 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1496 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1497 {
1498 __HAL_TIM_ENABLE(htim);
1499 }
1500 }
1501 else
1502 {
1503 __HAL_TIM_ENABLE(htim);
1504 }
1505
1506 /* Return function status */
1507 return HAL_OK;
1508 }
1509
1510 /**
1511 * @brief Stops the PWM signal generation.
1512 * @param htim TIM PWM handle
1513 * @param Channel TIM Channels to be disabled
1514 * This parameter can be one of the following values:
1515 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1516 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1517 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1518 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1519 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1520 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1521 * @retval HAL status
1522 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1523 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1524 {
1525 /* Check the parameters */
1526 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1527
1528 /* Disable the Capture compare channel */
1529 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1530
1531 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1532 {
1533 /* Disable the Main Output */
1534 __HAL_TIM_MOE_DISABLE(htim);
1535 }
1536
1537 /* Disable the Peripheral */
1538 __HAL_TIM_DISABLE(htim);
1539
1540 /* Set the TIM channel state */
1541 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1542
1543 /* Return function status */
1544 return HAL_OK;
1545 }
1546
1547 /**
1548 * @brief Starts the PWM signal generation in interrupt mode.
1549 * @param htim TIM PWM handle
1550 * @param Channel TIM Channel to be enabled
1551 * This parameter can be one of the following values:
1552 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1553 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1554 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1555 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1556 * @retval HAL status
1557 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1558 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1559 {
1560 HAL_StatusTypeDef status = HAL_OK;
1561 uint32_t tmpsmcr;
1562
1563 /* Check the parameters */
1564 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1565
1566 /* Check the TIM channel state */
1567 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1568 {
1569 return HAL_ERROR;
1570 }
1571
1572 /* Set the TIM channel state */
1573 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1574
1575 switch (Channel)
1576 {
1577 case TIM_CHANNEL_1:
1578 {
1579 /* Enable the TIM Capture/Compare 1 interrupt */
1580 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1581 break;
1582 }
1583
1584 case TIM_CHANNEL_2:
1585 {
1586 /* Enable the TIM Capture/Compare 2 interrupt */
1587 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1588 break;
1589 }
1590
1591 case TIM_CHANNEL_3:
1592 {
1593 /* Enable the TIM Capture/Compare 3 interrupt */
1594 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1595 break;
1596 }
1597
1598 case TIM_CHANNEL_4:
1599 {
1600 /* Enable the TIM Capture/Compare 4 interrupt */
1601 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1602 break;
1603 }
1604
1605 default:
1606 status = HAL_ERROR;
1607 break;
1608 }
1609
1610 if (status == HAL_OK)
1611 {
1612 /* Enable the Capture compare channel */
1613 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1614
1615 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1616 {
1617 /* Enable the main output */
1618 __HAL_TIM_MOE_ENABLE(htim);
1619 }
1620
1621 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1622 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1623 {
1624 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1625 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1626 {
1627 __HAL_TIM_ENABLE(htim);
1628 }
1629 }
1630 else
1631 {
1632 __HAL_TIM_ENABLE(htim);
1633 }
1634 }
1635
1636 /* Return function status */
1637 return status;
1638 }
1639
1640 /**
1641 * @brief Stops the PWM signal generation in interrupt mode.
1642 * @param htim TIM PWM handle
1643 * @param Channel TIM Channels to be disabled
1644 * This parameter can be one of the following values:
1645 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1646 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1647 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1648 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1649 * @retval HAL status
1650 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1651 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1652 {
1653 HAL_StatusTypeDef status = HAL_OK;
1654
1655 /* Check the parameters */
1656 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1657
1658 switch (Channel)
1659 {
1660 case TIM_CHANNEL_1:
1661 {
1662 /* Disable the TIM Capture/Compare 1 interrupt */
1663 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1664 break;
1665 }
1666
1667 case TIM_CHANNEL_2:
1668 {
1669 /* Disable the TIM Capture/Compare 2 interrupt */
1670 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1671 break;
1672 }
1673
1674 case TIM_CHANNEL_3:
1675 {
1676 /* Disable the TIM Capture/Compare 3 interrupt */
1677 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1678 break;
1679 }
1680
1681 case TIM_CHANNEL_4:
1682 {
1683 /* Disable the TIM Capture/Compare 4 interrupt */
1684 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1685 break;
1686 }
1687
1688 default:
1689 status = HAL_ERROR;
1690 break;
1691 }
1692
1693 if (status == HAL_OK)
1694 {
1695 /* Disable the Capture compare channel */
1696 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1697
1698 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1699 {
1700 /* Disable the Main Output */
1701 __HAL_TIM_MOE_DISABLE(htim);
1702 }
1703
1704 /* Disable the Peripheral */
1705 __HAL_TIM_DISABLE(htim);
1706
1707 /* Set the TIM channel state */
1708 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1709 }
1710
1711 /* Return function status */
1712 return status;
1713 }
1714
1715 /**
1716 * @brief Starts the TIM PWM signal generation in DMA mode.
1717 * @param htim TIM PWM handle
1718 * @param Channel TIM Channels to be enabled
1719 * This parameter can be one of the following values:
1720 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1721 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1722 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1723 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1724 * @param pData The source Buffer address.
1725 * @param Length The length of data to be transferred from memory to TIM peripheral
1726 * @retval HAL status
1727 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1728 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1729 uint16_t Length)
1730 {
1731 HAL_StatusTypeDef status = HAL_OK;
1732 uint32_t tmpsmcr;
1733
1734 /* Check the parameters */
1735 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1736
1737 /* Set the TIM channel state */
1738 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1739 {
1740 return HAL_BUSY;
1741 }
1742 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1743 {
1744 if ((pData == NULL) || (Length == 0U))
1745 {
1746 return HAL_ERROR;
1747 }
1748 else
1749 {
1750 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1751 }
1752 }
1753 else
1754 {
1755 return HAL_ERROR;
1756 }
1757
1758 switch (Channel)
1759 {
1760 case TIM_CHANNEL_1:
1761 {
1762 /* Set the DMA compare callbacks */
1763 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1764 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1765
1766 /* Set the DMA error callback */
1767 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1768
1769 /* Enable the DMA channel */
1770 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1771 Length) != HAL_OK)
1772 {
1773 /* Return error status */
1774 return HAL_ERROR;
1775 }
1776
1777 /* Enable the TIM Capture/Compare 1 DMA request */
1778 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1779 break;
1780 }
1781
1782 case TIM_CHANNEL_2:
1783 {
1784 /* Set the DMA compare callbacks */
1785 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1786 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1787
1788 /* Set the DMA error callback */
1789 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1790
1791 /* Enable the DMA channel */
1792 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1793 Length) != HAL_OK)
1794 {
1795 /* Return error status */
1796 return HAL_ERROR;
1797 }
1798 /* Enable the TIM Capture/Compare 2 DMA request */
1799 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1800 break;
1801 }
1802
1803 case TIM_CHANNEL_3:
1804 {
1805 /* Set the DMA compare callbacks */
1806 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1807 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1808
1809 /* Set the DMA error callback */
1810 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1811
1812 /* Enable the DMA channel */
1813 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1814 Length) != HAL_OK)
1815 {
1816 /* Return error status */
1817 return HAL_ERROR;
1818 }
1819 /* Enable the TIM Output Capture/Compare 3 request */
1820 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1821 break;
1822 }
1823
1824 case TIM_CHANNEL_4:
1825 {
1826 /* Set the DMA compare callbacks */
1827 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1828 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1829
1830 /* Set the DMA error callback */
1831 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1832
1833 /* Enable the DMA channel */
1834 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1835 Length) != HAL_OK)
1836 {
1837 /* Return error status */
1838 return HAL_ERROR;
1839 }
1840 /* Enable the TIM Capture/Compare 4 DMA request */
1841 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1842 break;
1843 }
1844
1845 default:
1846 status = HAL_ERROR;
1847 break;
1848 }
1849
1850 if (status == HAL_OK)
1851 {
1852 /* Enable the Capture compare channel */
1853 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1854
1855 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1856 {
1857 /* Enable the main output */
1858 __HAL_TIM_MOE_ENABLE(htim);
1859 }
1860
1861 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1862 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1863 {
1864 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1865 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1866 {
1867 __HAL_TIM_ENABLE(htim);
1868 }
1869 }
1870 else
1871 {
1872 __HAL_TIM_ENABLE(htim);
1873 }
1874 }
1875
1876 /* Return function status */
1877 return status;
1878 }
1879
1880 /**
1881 * @brief Stops the TIM PWM signal generation in DMA mode.
1882 * @param htim TIM PWM handle
1883 * @param Channel TIM Channels to be disabled
1884 * This parameter can be one of the following values:
1885 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1886 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1887 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1888 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1889 * @retval HAL status
1890 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1891 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1892 {
1893 HAL_StatusTypeDef status = HAL_OK;
1894
1895 /* Check the parameters */
1896 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
1897
1898 switch (Channel)
1899 {
1900 case TIM_CHANNEL_1:
1901 {
1902 /* Disable the TIM Capture/Compare 1 DMA request */
1903 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1904 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1905 break;
1906 }
1907
1908 case TIM_CHANNEL_2:
1909 {
1910 /* Disable the TIM Capture/Compare 2 DMA request */
1911 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1912 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1913 break;
1914 }
1915
1916 case TIM_CHANNEL_3:
1917 {
1918 /* Disable the TIM Capture/Compare 3 DMA request */
1919 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1920 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1921 break;
1922 }
1923
1924 case TIM_CHANNEL_4:
1925 {
1926 /* Disable the TIM Capture/Compare 4 interrupt */
1927 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1928 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1929 break;
1930 }
1931
1932 default:
1933 status = HAL_ERROR;
1934 break;
1935 }
1936
1937 if (status == HAL_OK)
1938 {
1939 /* Disable the Capture compare channel */
1940 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1941
1942 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1943 {
1944 /* Disable the Main Output */
1945 __HAL_TIM_MOE_DISABLE(htim);
1946 }
1947
1948 /* Disable the Peripheral */
1949 __HAL_TIM_DISABLE(htim);
1950
1951 /* Set the TIM channel state */
1952 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1953 }
1954
1955 /* Return function status */
1956 return status;
1957 }
1958
1959 /**
1960 * @}
1961 */
1962
1963 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1964 * @brief TIM Input Capture functions
1965 *
1966 @verbatim
1967 ==============================================================================
1968 ##### TIM Input Capture functions #####
1969 ==============================================================================
1970 [..]
1971 This section provides functions allowing to:
1972 (+) Initialize and configure the TIM Input Capture.
1973 (+) De-initialize the TIM Input Capture.
1974 (+) Start the TIM Input Capture.
1975 (+) Stop the TIM Input Capture.
1976 (+) Start the TIM Input Capture and enable interrupt.
1977 (+) Stop the TIM Input Capture and disable interrupt.
1978 (+) Start the TIM Input Capture and enable DMA transfer.
1979 (+) Stop the TIM Input Capture and disable DMA transfer.
1980
1981 @endverbatim
1982 * @{
1983 */
1984 /**
1985 * @brief Initializes the TIM Input Capture Time base according to the specified
1986 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1987 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1988 * requires a timer reset to avoid unexpected direction
1989 * due to DIR bit readonly in center aligned mode.
1990 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1991 * @param htim TIM Input Capture handle
1992 * @retval HAL status
1993 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1994 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1995 {
1996 /* Check the TIM handle allocation */
1997 if (htim == NULL)
1998 {
1999 return HAL_ERROR;
2000 }
2001
2002 /* Check the parameters */
2003 assert_param(IS_TIM_INSTANCE(htim->Instance));
2004 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2005 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2006 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2007 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2008
2009 if (htim->State == HAL_TIM_STATE_RESET)
2010 {
2011 /* Allocate lock resource and initialize it */
2012 htim->Lock = HAL_UNLOCKED;
2013
2014 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2015 /* Reset interrupt callbacks to legacy weak callbacks */
2016 TIM_ResetCallback(htim);
2017
2018 if (htim->IC_MspInitCallback == NULL)
2019 {
2020 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
2021 }
2022 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2023 htim->IC_MspInitCallback(htim);
2024 #else
2025 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2026 HAL_TIM_IC_MspInit(htim);
2027 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2028 }
2029
2030 /* Set the TIM state */
2031 htim->State = HAL_TIM_STATE_BUSY;
2032
2033 /* Init the base time for the input capture */
2034 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2035
2036 /* Initialize the DMA burst operation state */
2037 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2038
2039 /* Initialize the TIM channels state */
2040 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2041 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
2042
2043 /* Initialize the TIM state*/
2044 htim->State = HAL_TIM_STATE_READY;
2045
2046 return HAL_OK;
2047 }
2048
2049 /**
2050 * @brief DeInitializes the TIM peripheral
2051 * @param htim TIM Input Capture handle
2052 * @retval HAL status
2053 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)2054 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
2055 {
2056 /* Check the parameters */
2057 assert_param(IS_TIM_INSTANCE(htim->Instance));
2058
2059 htim->State = HAL_TIM_STATE_BUSY;
2060
2061 /* Disable the TIM Peripheral Clock */
2062 __HAL_TIM_DISABLE(htim);
2063
2064 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2065 if (htim->IC_MspDeInitCallback == NULL)
2066 {
2067 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
2068 }
2069 /* DeInit the low level hardware */
2070 htim->IC_MspDeInitCallback(htim);
2071 #else
2072 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
2073 HAL_TIM_IC_MspDeInit(htim);
2074 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2075
2076 /* Change the DMA burst operation state */
2077 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2078
2079 /* Change the TIM channels state */
2080 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2081 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
2082
2083 /* Change TIM state */
2084 htim->State = HAL_TIM_STATE_RESET;
2085
2086 /* Release Lock */
2087 __HAL_UNLOCK(htim);
2088
2089 return HAL_OK;
2090 }
2091
2092 /**
2093 * @brief Initializes the TIM Input Capture MSP.
2094 * @param htim TIM Input Capture handle
2095 * @retval None
2096 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)2097 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
2098 {
2099 /* Prevent unused argument(s) compilation warning */
2100 UNUSED(htim);
2101
2102 /* NOTE : This function should not be modified, when the callback is needed,
2103 the HAL_TIM_IC_MspInit could be implemented in the user file
2104 */
2105 }
2106
2107 /**
2108 * @brief DeInitializes TIM Input Capture MSP.
2109 * @param htim TIM handle
2110 * @retval None
2111 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)2112 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
2113 {
2114 /* Prevent unused argument(s) compilation warning */
2115 UNUSED(htim);
2116
2117 /* NOTE : This function should not be modified, when the callback is needed,
2118 the HAL_TIM_IC_MspDeInit could be implemented in the user file
2119 */
2120 }
2121
2122 /**
2123 * @brief Starts the TIM Input Capture measurement.
2124 * @param htim TIM Input Capture handle
2125 * @param Channel TIM Channels to be enabled
2126 * This parameter can be one of the following values:
2127 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2128 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2129 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2130 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2131 * @retval HAL status
2132 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2133 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2134 {
2135 uint32_t tmpsmcr;
2136 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2137 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2138
2139 /* Check the parameters */
2140 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2141
2142 /* Check the TIM channel state */
2143 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2144 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2145 {
2146 return HAL_ERROR;
2147 }
2148
2149 /* Set the TIM channel state */
2150 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2151 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2152
2153 /* Enable the Input Capture channel */
2154 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2155
2156 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2157 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2158 {
2159 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2160 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2161 {
2162 __HAL_TIM_ENABLE(htim);
2163 }
2164 }
2165 else
2166 {
2167 __HAL_TIM_ENABLE(htim);
2168 }
2169
2170 /* Return function status */
2171 return HAL_OK;
2172 }
2173
2174 /**
2175 * @brief Stops the TIM Input Capture measurement.
2176 * @param htim TIM Input Capture handle
2177 * @param Channel TIM Channels to be disabled
2178 * This parameter can be one of the following values:
2179 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2180 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2181 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2182 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2183 * @retval HAL status
2184 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2185 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2186 {
2187 /* Check the parameters */
2188 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2189
2190 /* Disable the Input Capture channel */
2191 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2192
2193 /* Disable the Peripheral */
2194 __HAL_TIM_DISABLE(htim);
2195
2196 /* Set the TIM channel state */
2197 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2198 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2199
2200 /* Return function status */
2201 return HAL_OK;
2202 }
2203
2204 /**
2205 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2206 * @param htim TIM Input Capture handle
2207 * @param Channel TIM Channels to be enabled
2208 * This parameter can be one of the following values:
2209 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2210 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2211 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2212 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2213 * @retval HAL status
2214 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2215 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2216 {
2217 HAL_StatusTypeDef status = HAL_OK;
2218 uint32_t tmpsmcr;
2219
2220 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2221 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2222
2223 /* Check the parameters */
2224 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2225
2226 /* Check the TIM channel state */
2227 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2228 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2229 {
2230 return HAL_ERROR;
2231 }
2232
2233 /* Set the TIM channel state */
2234 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2235 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2236
2237 switch (Channel)
2238 {
2239 case TIM_CHANNEL_1:
2240 {
2241 /* Enable the TIM Capture/Compare 1 interrupt */
2242 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2243 break;
2244 }
2245
2246 case TIM_CHANNEL_2:
2247 {
2248 /* Enable the TIM Capture/Compare 2 interrupt */
2249 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2250 break;
2251 }
2252
2253 case TIM_CHANNEL_3:
2254 {
2255 /* Enable the TIM Capture/Compare 3 interrupt */
2256 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2257 break;
2258 }
2259
2260 case TIM_CHANNEL_4:
2261 {
2262 /* Enable the TIM Capture/Compare 4 interrupt */
2263 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2264 break;
2265 }
2266
2267 default:
2268 status = HAL_ERROR;
2269 break;
2270 }
2271
2272 if (status == HAL_OK)
2273 {
2274 /* Enable the Input Capture channel */
2275 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2276
2277 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2278 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2279 {
2280 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2281 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2282 {
2283 __HAL_TIM_ENABLE(htim);
2284 }
2285 }
2286 else
2287 {
2288 __HAL_TIM_ENABLE(htim);
2289 }
2290 }
2291
2292 /* Return function status */
2293 return status;
2294 }
2295
2296 /**
2297 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2298 * @param htim TIM Input Capture handle
2299 * @param Channel TIM Channels to be disabled
2300 * This parameter can be one of the following values:
2301 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2302 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2303 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2304 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2305 * @retval HAL status
2306 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2307 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2308 {
2309 HAL_StatusTypeDef status = HAL_OK;
2310
2311 /* Check the parameters */
2312 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2313
2314 switch (Channel)
2315 {
2316 case TIM_CHANNEL_1:
2317 {
2318 /* Disable the TIM Capture/Compare 1 interrupt */
2319 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2320 break;
2321 }
2322
2323 case TIM_CHANNEL_2:
2324 {
2325 /* Disable the TIM Capture/Compare 2 interrupt */
2326 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2327 break;
2328 }
2329
2330 case TIM_CHANNEL_3:
2331 {
2332 /* Disable the TIM Capture/Compare 3 interrupt */
2333 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2334 break;
2335 }
2336
2337 case TIM_CHANNEL_4:
2338 {
2339 /* Disable the TIM Capture/Compare 4 interrupt */
2340 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2341 break;
2342 }
2343
2344 default:
2345 status = HAL_ERROR;
2346 break;
2347 }
2348
2349 if (status == HAL_OK)
2350 {
2351 /* Disable the Input Capture channel */
2352 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2353
2354 /* Disable the Peripheral */
2355 __HAL_TIM_DISABLE(htim);
2356
2357 /* Set the TIM channel state */
2358 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2359 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2360 }
2361
2362 /* Return function status */
2363 return status;
2364 }
2365
2366 /**
2367 * @brief Starts the TIM Input Capture measurement in DMA mode.
2368 * @param htim TIM Input Capture handle
2369 * @param Channel TIM Channels to be enabled
2370 * This parameter can be one of the following values:
2371 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2372 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2373 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2374 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2375 * @param pData The destination Buffer address.
2376 * @param Length The length of data to be transferred from TIM peripheral to memory.
2377 * @retval HAL status
2378 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2379 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2380 {
2381 HAL_StatusTypeDef status = HAL_OK;
2382 uint32_t tmpsmcr;
2383
2384 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2385 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2386
2387 /* Check the parameters */
2388 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2389 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2390
2391 /* Set the TIM channel state */
2392 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2393 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2394 {
2395 return HAL_BUSY;
2396 }
2397 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2398 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2399 {
2400 if ((pData == NULL) || (Length == 0U))
2401 {
2402 return HAL_ERROR;
2403 }
2404 else
2405 {
2406 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2407 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2408 }
2409 }
2410 else
2411 {
2412 return HAL_ERROR;
2413 }
2414
2415 /* Enable the Input Capture channel */
2416 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2417
2418 switch (Channel)
2419 {
2420 case TIM_CHANNEL_1:
2421 {
2422 /* Set the DMA capture callbacks */
2423 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2424 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2425
2426 /* Set the DMA error callback */
2427 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2428
2429 /* Enable the DMA channel */
2430 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
2431 Length) != HAL_OK)
2432 {
2433 /* Return error status */
2434 return HAL_ERROR;
2435 }
2436 /* Enable the TIM Capture/Compare 1 DMA request */
2437 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2438 break;
2439 }
2440
2441 case TIM_CHANNEL_2:
2442 {
2443 /* Set the DMA capture callbacks */
2444 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2445 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2446
2447 /* Set the DMA error callback */
2448 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2449
2450 /* Enable the DMA channel */
2451 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
2452 Length) != HAL_OK)
2453 {
2454 /* Return error status */
2455 return HAL_ERROR;
2456 }
2457 /* Enable the TIM Capture/Compare 2 DMA request */
2458 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2459 break;
2460 }
2461
2462 case TIM_CHANNEL_3:
2463 {
2464 /* Set the DMA capture callbacks */
2465 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2466 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2467
2468 /* Set the DMA error callback */
2469 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2470
2471 /* Enable the DMA channel */
2472 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
2473 Length) != HAL_OK)
2474 {
2475 /* Return error status */
2476 return HAL_ERROR;
2477 }
2478 /* Enable the TIM Capture/Compare 3 DMA request */
2479 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2480 break;
2481 }
2482
2483 case TIM_CHANNEL_4:
2484 {
2485 /* Set the DMA capture callbacks */
2486 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2487 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2488
2489 /* Set the DMA error callback */
2490 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2491
2492 /* Enable the DMA channel */
2493 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
2494 Length) != HAL_OK)
2495 {
2496 /* Return error status */
2497 return HAL_ERROR;
2498 }
2499 /* Enable the TIM Capture/Compare 4 DMA request */
2500 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2501 break;
2502 }
2503
2504 default:
2505 status = HAL_ERROR;
2506 break;
2507 }
2508
2509 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2510 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2511 {
2512 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2513 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2514 {
2515 __HAL_TIM_ENABLE(htim);
2516 }
2517 }
2518 else
2519 {
2520 __HAL_TIM_ENABLE(htim);
2521 }
2522
2523 /* Return function status */
2524 return status;
2525 }
2526
2527 /**
2528 * @brief Stops the TIM Input Capture measurement in DMA mode.
2529 * @param htim TIM Input Capture handle
2530 * @param Channel TIM Channels to be disabled
2531 * This parameter can be one of the following values:
2532 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2533 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2534 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2535 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2536 * @retval HAL status
2537 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2538 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2539 {
2540 HAL_StatusTypeDef status = HAL_OK;
2541
2542 /* Check the parameters */
2543 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
2544 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2545
2546 /* Disable the Input Capture channel */
2547 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2548
2549 switch (Channel)
2550 {
2551 case TIM_CHANNEL_1:
2552 {
2553 /* Disable the TIM Capture/Compare 1 DMA request */
2554 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2555 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2556 break;
2557 }
2558
2559 case TIM_CHANNEL_2:
2560 {
2561 /* Disable the TIM Capture/Compare 2 DMA request */
2562 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2563 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2564 break;
2565 }
2566
2567 case TIM_CHANNEL_3:
2568 {
2569 /* Disable the TIM Capture/Compare 3 DMA request */
2570 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2571 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2572 break;
2573 }
2574
2575 case TIM_CHANNEL_4:
2576 {
2577 /* Disable the TIM Capture/Compare 4 DMA request */
2578 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2579 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2580 break;
2581 }
2582
2583 default:
2584 status = HAL_ERROR;
2585 break;
2586 }
2587
2588 if (status == HAL_OK)
2589 {
2590 /* Disable the Peripheral */
2591 __HAL_TIM_DISABLE(htim);
2592
2593 /* Set the TIM channel state */
2594 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2595 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2596 }
2597
2598 /* Return function status */
2599 return status;
2600 }
2601 /**
2602 * @}
2603 */
2604
2605 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2606 * @brief TIM One Pulse functions
2607 *
2608 @verbatim
2609 ==============================================================================
2610 ##### TIM One Pulse functions #####
2611 ==============================================================================
2612 [..]
2613 This section provides functions allowing to:
2614 (+) Initialize and configure the TIM One Pulse.
2615 (+) De-initialize the TIM One Pulse.
2616 (+) Start the TIM One Pulse.
2617 (+) Stop the TIM One Pulse.
2618 (+) Start the TIM One Pulse and enable interrupt.
2619 (+) Stop the TIM One Pulse and disable interrupt.
2620 (+) Start the TIM One Pulse and enable DMA transfer.
2621 (+) Stop the TIM One Pulse and disable DMA transfer.
2622
2623 @endverbatim
2624 * @{
2625 */
2626 /**
2627 * @brief Initializes the TIM One Pulse Time Base according to the specified
2628 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2629 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2630 * requires a timer reset to avoid unexpected direction
2631 * due to DIR bit readonly in center aligned mode.
2632 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2633 * @note When the timer instance is initialized in One Pulse mode, timer
2634 * channels 1 and channel 2 are reserved and cannot be used for other
2635 * purpose.
2636 * @param htim TIM One Pulse handle
2637 * @param OnePulseMode Select the One pulse mode.
2638 * This parameter can be one of the following values:
2639 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2640 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2641 * @retval HAL status
2642 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2643 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2644 {
2645 /* Check the TIM handle allocation */
2646 if (htim == NULL)
2647 {
2648 return HAL_ERROR;
2649 }
2650
2651 /* Check the parameters */
2652 assert_param(IS_TIM_INSTANCE(htim->Instance));
2653 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2654 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2655 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2656 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
2657 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2658
2659 if (htim->State == HAL_TIM_STATE_RESET)
2660 {
2661 /* Allocate lock resource and initialize it */
2662 htim->Lock = HAL_UNLOCKED;
2663
2664 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2665 /* Reset interrupt callbacks to legacy weak callbacks */
2666 TIM_ResetCallback(htim);
2667
2668 if (htim->OnePulse_MspInitCallback == NULL)
2669 {
2670 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2671 }
2672 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2673 htim->OnePulse_MspInitCallback(htim);
2674 #else
2675 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2676 HAL_TIM_OnePulse_MspInit(htim);
2677 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2678 }
2679
2680 /* Set the TIM state */
2681 htim->State = HAL_TIM_STATE_BUSY;
2682
2683 /* Configure the Time base in the One Pulse Mode */
2684 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2685
2686 /* Reset the OPM Bit */
2687 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2688
2689 /* Configure the OPM Mode */
2690 htim->Instance->CR1 |= OnePulseMode;
2691
2692 /* Initialize the DMA burst operation state */
2693 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2694
2695 /* Initialize the TIM channels state */
2696 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2697 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2698 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2699 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2700
2701 /* Initialize the TIM state*/
2702 htim->State = HAL_TIM_STATE_READY;
2703
2704 return HAL_OK;
2705 }
2706
2707 /**
2708 * @brief DeInitializes the TIM One Pulse
2709 * @param htim TIM One Pulse handle
2710 * @retval HAL status
2711 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2712 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2713 {
2714 /* Check the parameters */
2715 assert_param(IS_TIM_INSTANCE(htim->Instance));
2716
2717 htim->State = HAL_TIM_STATE_BUSY;
2718
2719 /* Disable the TIM Peripheral Clock */
2720 __HAL_TIM_DISABLE(htim);
2721
2722 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2723 if (htim->OnePulse_MspDeInitCallback == NULL)
2724 {
2725 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2726 }
2727 /* DeInit the low level hardware */
2728 htim->OnePulse_MspDeInitCallback(htim);
2729 #else
2730 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2731 HAL_TIM_OnePulse_MspDeInit(htim);
2732 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2733
2734 /* Change the DMA burst operation state */
2735 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2736
2737 /* Set the TIM channel state */
2738 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2739 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2740 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2741 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2742
2743 /* Change TIM state */
2744 htim->State = HAL_TIM_STATE_RESET;
2745
2746 /* Release Lock */
2747 __HAL_UNLOCK(htim);
2748
2749 return HAL_OK;
2750 }
2751
2752 /**
2753 * @brief Initializes the TIM One Pulse MSP.
2754 * @param htim TIM One Pulse handle
2755 * @retval None
2756 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2757 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2758 {
2759 /* Prevent unused argument(s) compilation warning */
2760 UNUSED(htim);
2761
2762 /* NOTE : This function should not be modified, when the callback is needed,
2763 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2764 */
2765 }
2766
2767 /**
2768 * @brief DeInitializes TIM One Pulse MSP.
2769 * @param htim TIM One Pulse handle
2770 * @retval None
2771 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2772 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2773 {
2774 /* Prevent unused argument(s) compilation warning */
2775 UNUSED(htim);
2776
2777 /* NOTE : This function should not be modified, when the callback is needed,
2778 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2779 */
2780 }
2781
2782 /**
2783 * @brief Starts the TIM One Pulse signal generation.
2784 * @note Though OutputChannel parameter is deprecated and ignored by the function
2785 * it has been kept to avoid HAL_TIM API compatibility break.
2786 * @note The pulse output channel is determined when calling
2787 * @ref HAL_TIM_OnePulse_ConfigChannel().
2788 * @param htim TIM One Pulse handle
2789 * @param OutputChannel See note above
2790 * @retval HAL status
2791 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2792 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2793 {
2794 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2795 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2796 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2797 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2798
2799 /* Prevent unused argument(s) compilation warning */
2800 UNUSED(OutputChannel);
2801
2802 /* Check the TIM channels state */
2803 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2804 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2805 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2806 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2807 {
2808 return HAL_ERROR;
2809 }
2810
2811 /* Set the TIM channels state */
2812 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2813 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2814 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2815 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2816
2817 /* Enable the Capture compare and the Input Capture channels
2818 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2819 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2820 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2821 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2822
2823 No need to enable the counter, it's enabled automatically by hardware
2824 (the counter starts in response to a stimulus and generate a pulse */
2825
2826 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2827 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2828
2829 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2830 {
2831 /* Enable the main output */
2832 __HAL_TIM_MOE_ENABLE(htim);
2833 }
2834
2835 /* Return function status */
2836 return HAL_OK;
2837 }
2838
2839 /**
2840 * @brief Stops the TIM One Pulse signal generation.
2841 * @note Though OutputChannel parameter is deprecated and ignored by the function
2842 * it has been kept to avoid HAL_TIM API compatibility break.
2843 * @note The pulse output channel is determined when calling
2844 * @ref HAL_TIM_OnePulse_ConfigChannel().
2845 * @param htim TIM One Pulse handle
2846 * @param OutputChannel See note above
2847 * @retval HAL status
2848 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2849 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2850 {
2851 /* Prevent unused argument(s) compilation warning */
2852 UNUSED(OutputChannel);
2853
2854 /* Disable the Capture compare and the Input Capture channels
2855 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2856 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2857 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2858 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2859
2860 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2861 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2862
2863 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2864 {
2865 /* Disable the Main Output */
2866 __HAL_TIM_MOE_DISABLE(htim);
2867 }
2868
2869 /* Disable the Peripheral */
2870 __HAL_TIM_DISABLE(htim);
2871
2872 /* Set the TIM channels state */
2873 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2874 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2875 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2876 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2877
2878 /* Return function status */
2879 return HAL_OK;
2880 }
2881
2882 /**
2883 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2884 * @note Though OutputChannel parameter is deprecated and ignored by the function
2885 * it has been kept to avoid HAL_TIM API compatibility break.
2886 * @note The pulse output channel is determined when calling
2887 * @ref HAL_TIM_OnePulse_ConfigChannel().
2888 * @param htim TIM One Pulse handle
2889 * @param OutputChannel See note above
2890 * @retval HAL status
2891 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2892 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2893 {
2894 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2895 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2896 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2897 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2898
2899 /* Prevent unused argument(s) compilation warning */
2900 UNUSED(OutputChannel);
2901
2902 /* Check the TIM channels state */
2903 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2904 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2905 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2906 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2907 {
2908 return HAL_ERROR;
2909 }
2910
2911 /* Set the TIM channels state */
2912 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2913 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2914 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2915 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2916
2917 /* Enable the Capture compare and the Input Capture channels
2918 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2919 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2920 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2921 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2922
2923 No need to enable the counter, it's enabled automatically by hardware
2924 (the counter starts in response to a stimulus and generate a pulse */
2925
2926 /* Enable the TIM Capture/Compare 1 interrupt */
2927 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2928
2929 /* Enable the TIM Capture/Compare 2 interrupt */
2930 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2931
2932 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2933 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2934
2935 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2936 {
2937 /* Enable the main output */
2938 __HAL_TIM_MOE_ENABLE(htim);
2939 }
2940
2941 /* Return function status */
2942 return HAL_OK;
2943 }
2944
2945 /**
2946 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2947 * @note Though OutputChannel parameter is deprecated and ignored by the function
2948 * it has been kept to avoid HAL_TIM API compatibility break.
2949 * @note The pulse output channel is determined when calling
2950 * @ref HAL_TIM_OnePulse_ConfigChannel().
2951 * @param htim TIM One Pulse handle
2952 * @param OutputChannel See note above
2953 * @retval HAL status
2954 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2955 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2956 {
2957 /* Prevent unused argument(s) compilation warning */
2958 UNUSED(OutputChannel);
2959
2960 /* Disable the TIM Capture/Compare 1 interrupt */
2961 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2962
2963 /* Disable the TIM Capture/Compare 2 interrupt */
2964 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2965
2966 /* Disable the Capture compare and the Input Capture channels
2967 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2968 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2969 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2970 whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2971 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2972 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2973
2974 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2975 {
2976 /* Disable the Main Output */
2977 __HAL_TIM_MOE_DISABLE(htim);
2978 }
2979
2980 /* Disable the Peripheral */
2981 __HAL_TIM_DISABLE(htim);
2982
2983 /* Set the TIM channels state */
2984 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2985 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2986 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2987 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2988
2989 /* Return function status */
2990 return HAL_OK;
2991 }
2992
2993 /**
2994 * @}
2995 */
2996
2997 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2998 * @brief TIM Encoder functions
2999 *
3000 @verbatim
3001 ==============================================================================
3002 ##### TIM Encoder functions #####
3003 ==============================================================================
3004 [..]
3005 This section provides functions allowing to:
3006 (+) Initialize and configure the TIM Encoder.
3007 (+) De-initialize the TIM Encoder.
3008 (+) Start the TIM Encoder.
3009 (+) Stop the TIM Encoder.
3010 (+) Start the TIM Encoder and enable interrupt.
3011 (+) Stop the TIM Encoder and disable interrupt.
3012 (+) Start the TIM Encoder and enable DMA transfer.
3013 (+) Stop the TIM Encoder and disable DMA transfer.
3014
3015 @endverbatim
3016 * @{
3017 */
3018 /**
3019 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
3020 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
3021 * requires a timer reset to avoid unexpected direction
3022 * due to DIR bit readonly in center aligned mode.
3023 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
3024 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
3025 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
3026 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
3027 * @note When the timer instance is initialized in Encoder mode, timer
3028 * channels 1 and channel 2 are reserved and cannot be used for other
3029 * purpose.
3030 * @param htim TIM Encoder Interface handle
3031 * @param sConfig TIM Encoder Interface configuration structure
3032 * @retval HAL status
3033 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,const TIM_Encoder_InitTypeDef * sConfig)3034 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
3035 {
3036 uint32_t tmpsmcr;
3037 uint32_t tmpccmr1;
3038 uint32_t tmpccer;
3039
3040 /* Check the TIM handle allocation */
3041 if (htim == NULL)
3042 {
3043 return HAL_ERROR;
3044 }
3045
3046 /* Check the parameters */
3047 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3048 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
3049 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
3050 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
3051 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
3052 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
3053 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
3054 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
3055 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
3056 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
3057 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
3058 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
3059 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
3060 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
3061
3062 if (htim->State == HAL_TIM_STATE_RESET)
3063 {
3064 /* Allocate lock resource and initialize it */
3065 htim->Lock = HAL_UNLOCKED;
3066
3067 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3068 /* Reset interrupt callbacks to legacy weak callbacks */
3069 TIM_ResetCallback(htim);
3070
3071 if (htim->Encoder_MspInitCallback == NULL)
3072 {
3073 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
3074 }
3075 /* Init the low level hardware : GPIO, CLOCK, NVIC */
3076 htim->Encoder_MspInitCallback(htim);
3077 #else
3078 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
3079 HAL_TIM_Encoder_MspInit(htim);
3080 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3081 }
3082
3083 /* Set the TIM state */
3084 htim->State = HAL_TIM_STATE_BUSY;
3085
3086 /* Reset the SMS and ECE bits */
3087 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
3088
3089 /* Configure the Time base in the Encoder Mode */
3090 TIM_Base_SetConfig(htim->Instance, &htim->Init);
3091
3092 /* Get the TIMx SMCR register value */
3093 tmpsmcr = htim->Instance->SMCR;
3094
3095 /* Get the TIMx CCMR1 register value */
3096 tmpccmr1 = htim->Instance->CCMR1;
3097
3098 /* Get the TIMx CCER register value */
3099 tmpccer = htim->Instance->CCER;
3100
3101 /* Set the encoder Mode */
3102 tmpsmcr |= sConfig->EncoderMode;
3103
3104 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3105 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
3106 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
3107
3108 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
3109 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
3110 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
3111 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
3112 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
3113
3114 /* Set the TI1 and the TI2 Polarities */
3115 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
3116 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
3117 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
3118
3119 /* Write to TIMx SMCR */
3120 htim->Instance->SMCR = tmpsmcr;
3121
3122 /* Write to TIMx CCMR1 */
3123 htim->Instance->CCMR1 = tmpccmr1;
3124
3125 /* Write to TIMx CCER */
3126 htim->Instance->CCER = tmpccer;
3127
3128 /* Initialize the DMA burst operation state */
3129 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
3130
3131 /* Set the TIM channels state */
3132 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3133 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3134 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3135 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3136
3137 /* Initialize the TIM state*/
3138 htim->State = HAL_TIM_STATE_READY;
3139
3140 return HAL_OK;
3141 }
3142
3143
3144 /**
3145 * @brief DeInitializes the TIM Encoder interface
3146 * @param htim TIM Encoder Interface handle
3147 * @retval HAL status
3148 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)3149 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
3150 {
3151 /* Check the parameters */
3152 assert_param(IS_TIM_INSTANCE(htim->Instance));
3153
3154 htim->State = HAL_TIM_STATE_BUSY;
3155
3156 /* Disable the TIM Peripheral Clock */
3157 __HAL_TIM_DISABLE(htim);
3158
3159 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3160 if (htim->Encoder_MspDeInitCallback == NULL)
3161 {
3162 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
3163 }
3164 /* DeInit the low level hardware */
3165 htim->Encoder_MspDeInitCallback(htim);
3166 #else
3167 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
3168 HAL_TIM_Encoder_MspDeInit(htim);
3169 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3170
3171 /* Change the DMA burst operation state */
3172 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
3173
3174 /* Set the TIM channels state */
3175 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3176 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3177 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
3178 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
3179
3180 /* Change TIM state */
3181 htim->State = HAL_TIM_STATE_RESET;
3182
3183 /* Release Lock */
3184 __HAL_UNLOCK(htim);
3185
3186 return HAL_OK;
3187 }
3188
3189 /**
3190 * @brief Initializes the TIM Encoder Interface MSP.
3191 * @param htim TIM Encoder Interface handle
3192 * @retval None
3193 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3194 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3195 {
3196 /* Prevent unused argument(s) compilation warning */
3197 UNUSED(htim);
3198
3199 /* NOTE : This function should not be modified, when the callback is needed,
3200 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3201 */
3202 }
3203
3204 /**
3205 * @brief DeInitializes TIM Encoder Interface MSP.
3206 * @param htim TIM Encoder Interface handle
3207 * @retval None
3208 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3209 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3210 {
3211 /* Prevent unused argument(s) compilation warning */
3212 UNUSED(htim);
3213
3214 /* NOTE : This function should not be modified, when the callback is needed,
3215 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3216 */
3217 }
3218
3219 /**
3220 * @brief Starts the TIM Encoder Interface.
3221 * @param htim TIM Encoder Interface handle
3222 * @param Channel TIM Channels to be enabled
3223 * This parameter can be one of the following values:
3224 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3225 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3226 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3227 * @retval HAL status
3228 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3229 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3230 {
3231 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3232 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3233 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3234 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3235
3236 /* Check the parameters */
3237 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3238
3239 /* Set the TIM channel(s) state */
3240 if (Channel == TIM_CHANNEL_1)
3241 {
3242 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3243 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3244 {
3245 return HAL_ERROR;
3246 }
3247 else
3248 {
3249 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3250 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3251 }
3252 }
3253 else if (Channel == TIM_CHANNEL_2)
3254 {
3255 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3256 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3257 {
3258 return HAL_ERROR;
3259 }
3260 else
3261 {
3262 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3263 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3264 }
3265 }
3266 else
3267 {
3268 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3269 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3270 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3271 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3272 {
3273 return HAL_ERROR;
3274 }
3275 else
3276 {
3277 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3278 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3279 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3280 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3281 }
3282 }
3283
3284 /* Enable the encoder interface channels */
3285 switch (Channel)
3286 {
3287 case TIM_CHANNEL_1:
3288 {
3289 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3290 break;
3291 }
3292
3293 case TIM_CHANNEL_2:
3294 {
3295 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3296 break;
3297 }
3298
3299 default :
3300 {
3301 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3302 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3303 break;
3304 }
3305 }
3306 /* Enable the Peripheral */
3307 __HAL_TIM_ENABLE(htim);
3308
3309 /* Return function status */
3310 return HAL_OK;
3311 }
3312
3313 /**
3314 * @brief Stops the TIM Encoder Interface.
3315 * @param htim TIM Encoder Interface handle
3316 * @param Channel TIM Channels to be disabled
3317 * This parameter can be one of the following values:
3318 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3319 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3320 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3321 * @retval HAL status
3322 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3323 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3324 {
3325 /* Check the parameters */
3326 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3327
3328 /* Disable the Input Capture channels 1 and 2
3329 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3330 switch (Channel)
3331 {
3332 case TIM_CHANNEL_1:
3333 {
3334 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3335 break;
3336 }
3337
3338 case TIM_CHANNEL_2:
3339 {
3340 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3341 break;
3342 }
3343
3344 default :
3345 {
3346 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3347 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3348 break;
3349 }
3350 }
3351
3352 /* Disable the Peripheral */
3353 __HAL_TIM_DISABLE(htim);
3354
3355 /* Set the TIM channel(s) state */
3356 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3357 {
3358 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3359 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3360 }
3361 else
3362 {
3363 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3364 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3365 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3366 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3367 }
3368
3369 /* Return function status */
3370 return HAL_OK;
3371 }
3372
3373 /**
3374 * @brief Starts the TIM Encoder Interface in interrupt mode.
3375 * @param htim TIM Encoder Interface handle
3376 * @param Channel TIM Channels to be enabled
3377 * This parameter can be one of the following values:
3378 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3379 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3380 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3381 * @retval HAL status
3382 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3383 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3384 {
3385 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3386 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3387 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3388 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3389
3390 /* Check the parameters */
3391 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3392
3393 /* Set the TIM channel(s) state */
3394 if (Channel == TIM_CHANNEL_1)
3395 {
3396 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3397 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3398 {
3399 return HAL_ERROR;
3400 }
3401 else
3402 {
3403 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3404 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3405 }
3406 }
3407 else if (Channel == TIM_CHANNEL_2)
3408 {
3409 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3410 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3411 {
3412 return HAL_ERROR;
3413 }
3414 else
3415 {
3416 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3417 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3418 }
3419 }
3420 else
3421 {
3422 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3423 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3424 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3425 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3426 {
3427 return HAL_ERROR;
3428 }
3429 else
3430 {
3431 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3432 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3433 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3434 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3435 }
3436 }
3437
3438 /* Enable the encoder interface channels */
3439 /* Enable the capture compare Interrupts 1 and/or 2 */
3440 switch (Channel)
3441 {
3442 case TIM_CHANNEL_1:
3443 {
3444 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3445 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3446 break;
3447 }
3448
3449 case TIM_CHANNEL_2:
3450 {
3451 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3452 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3453 break;
3454 }
3455
3456 default :
3457 {
3458 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3459 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3460 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3461 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3462 break;
3463 }
3464 }
3465
3466 /* Enable the Peripheral */
3467 __HAL_TIM_ENABLE(htim);
3468
3469 /* Return function status */
3470 return HAL_OK;
3471 }
3472
3473 /**
3474 * @brief Stops the TIM Encoder Interface in interrupt mode.
3475 * @param htim TIM Encoder Interface handle
3476 * @param Channel TIM Channels to be disabled
3477 * This parameter can be one of the following values:
3478 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3479 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3480 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3481 * @retval HAL status
3482 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3483 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3484 {
3485 /* Check the parameters */
3486 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3487
3488 /* Disable the Input Capture channels 1 and 2
3489 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3490 if (Channel == TIM_CHANNEL_1)
3491 {
3492 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3493
3494 /* Disable the capture compare Interrupts 1 */
3495 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3496 }
3497 else if (Channel == TIM_CHANNEL_2)
3498 {
3499 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3500
3501 /* Disable the capture compare Interrupts 2 */
3502 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3503 }
3504 else
3505 {
3506 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3507 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3508
3509 /* Disable the capture compare Interrupts 1 and 2 */
3510 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3511 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3512 }
3513
3514 /* Disable the Peripheral */
3515 __HAL_TIM_DISABLE(htim);
3516
3517 /* Set the TIM channel(s) state */
3518 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3519 {
3520 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3521 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3522 }
3523 else
3524 {
3525 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3526 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3527 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3528 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3529 }
3530
3531 /* Return function status */
3532 return HAL_OK;
3533 }
3534
3535 /**
3536 * @brief Starts the TIM Encoder Interface in DMA mode.
3537 * @param htim TIM Encoder Interface handle
3538 * @param Channel TIM Channels to be enabled
3539 * This parameter can be one of the following values:
3540 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3541 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3542 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3543 * @param pData1 The destination Buffer address for IC1.
3544 * @param pData2 The destination Buffer address for IC2.
3545 * @param Length The length of data to be transferred from TIM peripheral to memory.
3546 * @retval HAL status
3547 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3548 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3549 uint32_t *pData2, uint16_t Length)
3550 {
3551 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3552 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3553 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3554 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3555
3556 /* Check the parameters */
3557 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3558
3559 /* Set the TIM channel(s) state */
3560 if (Channel == TIM_CHANNEL_1)
3561 {
3562 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3563 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3564 {
3565 return HAL_BUSY;
3566 }
3567 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3568 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3569 {
3570 if ((pData1 == NULL) || (Length == 0U))
3571 {
3572 return HAL_ERROR;
3573 }
3574 else
3575 {
3576 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3577 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3578 }
3579 }
3580 else
3581 {
3582 return HAL_ERROR;
3583 }
3584 }
3585 else if (Channel == TIM_CHANNEL_2)
3586 {
3587 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3588 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3589 {
3590 return HAL_BUSY;
3591 }
3592 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3593 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3594 {
3595 if ((pData2 == NULL) || (Length == 0U))
3596 {
3597 return HAL_ERROR;
3598 }
3599 else
3600 {
3601 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3602 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3603 }
3604 }
3605 else
3606 {
3607 return HAL_ERROR;
3608 }
3609 }
3610 else
3611 {
3612 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3613 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3614 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3615 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3616 {
3617 return HAL_BUSY;
3618 }
3619 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3620 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3621 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3622 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3623 {
3624 if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
3625 {
3626 return HAL_ERROR;
3627 }
3628 else
3629 {
3630 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3631 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3632 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3633 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3634 }
3635 }
3636 else
3637 {
3638 return HAL_ERROR;
3639 }
3640 }
3641
3642 switch (Channel)
3643 {
3644 case TIM_CHANNEL_1:
3645 {
3646 /* Set the DMA capture callbacks */
3647 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3648 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3649
3650 /* Set the DMA error callback */
3651 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3652
3653 /* Enable the DMA channel */
3654 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3655 Length) != HAL_OK)
3656 {
3657 /* Return error status */
3658 return HAL_ERROR;
3659 }
3660 /* Enable the TIM Input Capture DMA request */
3661 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3662
3663 /* Enable the Capture compare channel */
3664 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3665
3666 /* Enable the Peripheral */
3667 __HAL_TIM_ENABLE(htim);
3668
3669 break;
3670 }
3671
3672 case TIM_CHANNEL_2:
3673 {
3674 /* Set the DMA capture callbacks */
3675 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3676 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3677
3678 /* Set the DMA error callback */
3679 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3680 /* Enable the DMA channel */
3681 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3682 Length) != HAL_OK)
3683 {
3684 /* Return error status */
3685 return HAL_ERROR;
3686 }
3687 /* Enable the TIM Input Capture DMA request */
3688 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3689
3690 /* Enable the Capture compare channel */
3691 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3692
3693 /* Enable the Peripheral */
3694 __HAL_TIM_ENABLE(htim);
3695
3696 break;
3697 }
3698
3699 default:
3700 {
3701 /* Set the DMA capture callbacks */
3702 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3703 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3704
3705 /* Set the DMA error callback */
3706 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3707
3708 /* Enable the DMA channel */
3709 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
3710 Length) != HAL_OK)
3711 {
3712 /* Return error status */
3713 return HAL_ERROR;
3714 }
3715
3716 /* Set the DMA capture callbacks */
3717 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3718 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3719
3720 /* Set the DMA error callback */
3721 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3722
3723 /* Enable the DMA channel */
3724 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
3725 Length) != HAL_OK)
3726 {
3727 /* Return error status */
3728 return HAL_ERROR;
3729 }
3730
3731 /* Enable the TIM Input Capture DMA request */
3732 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3733 /* Enable the TIM Input Capture DMA request */
3734 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3735
3736 /* Enable the Capture compare channel */
3737 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3738 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3739
3740 /* Enable the Peripheral */
3741 __HAL_TIM_ENABLE(htim);
3742
3743 break;
3744 }
3745 }
3746
3747 /* Return function status */
3748 return HAL_OK;
3749 }
3750
3751 /**
3752 * @brief Stops the TIM Encoder Interface in DMA mode.
3753 * @param htim TIM Encoder Interface handle
3754 * @param Channel TIM Channels to be enabled
3755 * This parameter can be one of the following values:
3756 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3757 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3758 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3759 * @retval HAL status
3760 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3761 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3762 {
3763 /* Check the parameters */
3764 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3765
3766 /* Disable the Input Capture channels 1 and 2
3767 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3768 if (Channel == TIM_CHANNEL_1)
3769 {
3770 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3771
3772 /* Disable the capture compare DMA Request 1 */
3773 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3774 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3775 }
3776 else if (Channel == TIM_CHANNEL_2)
3777 {
3778 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3779
3780 /* Disable the capture compare DMA Request 2 */
3781 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3782 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3783 }
3784 else
3785 {
3786 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3787 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3788
3789 /* Disable the capture compare DMA Request 1 and 2 */
3790 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3791 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3792 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3793 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3794 }
3795
3796 /* Disable the Peripheral */
3797 __HAL_TIM_DISABLE(htim);
3798
3799 /* Set the TIM channel(s) state */
3800 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3801 {
3802 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3803 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3804 }
3805 else
3806 {
3807 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3808 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3809 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3810 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3811 }
3812
3813 /* Return function status */
3814 return HAL_OK;
3815 }
3816
3817 /**
3818 * @}
3819 */
3820 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3821 * @brief TIM IRQ handler management
3822 *
3823 @verbatim
3824 ==============================================================================
3825 ##### IRQ handler management #####
3826 ==============================================================================
3827 [..]
3828 This section provides Timer IRQ handler function.
3829
3830 @endverbatim
3831 * @{
3832 */
3833 /**
3834 * @brief This function handles TIM interrupts requests.
3835 * @param htim TIM handle
3836 * @retval None
3837 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3838 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3839 {
3840 uint32_t itsource = htim->Instance->DIER;
3841 uint32_t itflag = htim->Instance->SR;
3842
3843 /* Capture compare 1 event */
3844 if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
3845 {
3846 if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
3847 {
3848 {
3849 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
3850 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3851
3852 /* Input capture event */
3853 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3854 {
3855 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3856 htim->IC_CaptureCallback(htim);
3857 #else
3858 HAL_TIM_IC_CaptureCallback(htim);
3859 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3860 }
3861 /* Output compare event */
3862 else
3863 {
3864 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3865 htim->OC_DelayElapsedCallback(htim);
3866 htim->PWM_PulseFinishedCallback(htim);
3867 #else
3868 HAL_TIM_OC_DelayElapsedCallback(htim);
3869 HAL_TIM_PWM_PulseFinishedCallback(htim);
3870 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3871 }
3872 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3873 }
3874 }
3875 }
3876 /* Capture compare 2 event */
3877 if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
3878 {
3879 if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
3880 {
3881 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
3882 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3883 /* Input capture event */
3884 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3885 {
3886 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3887 htim->IC_CaptureCallback(htim);
3888 #else
3889 HAL_TIM_IC_CaptureCallback(htim);
3890 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3891 }
3892 /* Output compare event */
3893 else
3894 {
3895 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3896 htim->OC_DelayElapsedCallback(htim);
3897 htim->PWM_PulseFinishedCallback(htim);
3898 #else
3899 HAL_TIM_OC_DelayElapsedCallback(htim);
3900 HAL_TIM_PWM_PulseFinishedCallback(htim);
3901 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3902 }
3903 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3904 }
3905 }
3906 /* Capture compare 3 event */
3907 if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
3908 {
3909 if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
3910 {
3911 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
3912 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3913 /* Input capture event */
3914 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3915 {
3916 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3917 htim->IC_CaptureCallback(htim);
3918 #else
3919 HAL_TIM_IC_CaptureCallback(htim);
3920 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3921 }
3922 /* Output compare event */
3923 else
3924 {
3925 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3926 htim->OC_DelayElapsedCallback(htim);
3927 htim->PWM_PulseFinishedCallback(htim);
3928 #else
3929 HAL_TIM_OC_DelayElapsedCallback(htim);
3930 HAL_TIM_PWM_PulseFinishedCallback(htim);
3931 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3932 }
3933 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3934 }
3935 }
3936 /* Capture compare 4 event */
3937 if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
3938 {
3939 if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
3940 {
3941 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
3942 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3943 /* Input capture event */
3944 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3945 {
3946 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3947 htim->IC_CaptureCallback(htim);
3948 #else
3949 HAL_TIM_IC_CaptureCallback(htim);
3950 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3951 }
3952 /* Output compare event */
3953 else
3954 {
3955 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3956 htim->OC_DelayElapsedCallback(htim);
3957 htim->PWM_PulseFinishedCallback(htim);
3958 #else
3959 HAL_TIM_OC_DelayElapsedCallback(htim);
3960 HAL_TIM_PWM_PulseFinishedCallback(htim);
3961 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3962 }
3963 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3964 }
3965 }
3966 /* TIM Update event */
3967 if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
3968 {
3969 if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
3970 {
3971 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
3972 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3973 htim->PeriodElapsedCallback(htim);
3974 #else
3975 HAL_TIM_PeriodElapsedCallback(htim);
3976 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3977 }
3978 }
3979 /* TIM Break input event */
3980 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
3981 ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
3982 {
3983 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
3984 {
3985 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
3986 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3987 htim->BreakCallback(htim);
3988 #else
3989 HAL_TIMEx_BreakCallback(htim);
3990 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3991 }
3992 }
3993 /* TIM Break2 input event */
3994 if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
3995 {
3996 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
3997 {
3998 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
3999 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4000 htim->Break2Callback(htim);
4001 #else
4002 HAL_TIMEx_Break2Callback(htim);
4003 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4004 }
4005 }
4006 /* TIM Trigger detection event */
4007 if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
4008 {
4009 if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
4010 {
4011 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
4012 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4013 htim->TriggerCallback(htim);
4014 #else
4015 HAL_TIM_TriggerCallback(htim);
4016 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4017 }
4018 }
4019 /* TIM commutation event */
4020 if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
4021 {
4022 if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
4023 {
4024 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
4025 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4026 htim->CommutationCallback(htim);
4027 #else
4028 HAL_TIMEx_CommutCallback(htim);
4029 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4030 }
4031 }
4032 /* TIM Encoder index event */
4033 if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX))
4034 {
4035 if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX))
4036 {
4037 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX);
4038 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4039 htim->EncoderIndexCallback(htim);
4040 #else
4041 HAL_TIMEx_EncoderIndexCallback(htim);
4042 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4043 }
4044 }
4045 /* TIM Direction change event */
4046 if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR))
4047 {
4048 if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR))
4049 {
4050 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR);
4051 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4052 htim->DirectionChangeCallback(htim);
4053 #else
4054 HAL_TIMEx_DirectionChangeCallback(htim);
4055 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4056 }
4057 }
4058 /* TIM Index error event */
4059 if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR))
4060 {
4061 if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR))
4062 {
4063 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR);
4064 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4065 htim->IndexErrorCallback(htim);
4066 #else
4067 HAL_TIMEx_IndexErrorCallback(htim);
4068 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4069 }
4070 }
4071 /* TIM Transition error event */
4072 if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR))
4073 {
4074 if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR))
4075 {
4076 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR);
4077 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
4078 htim->TransitionErrorCallback(htim);
4079 #else
4080 HAL_TIMEx_TransitionErrorCallback(htim);
4081 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
4082 }
4083 }
4084 }
4085
4086 /**
4087 * @}
4088 */
4089
4090 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
4091 * @brief TIM Peripheral Control functions
4092 *
4093 @verbatim
4094 ==============================================================================
4095 ##### Peripheral Control functions #####
4096 ==============================================================================
4097 [..]
4098 This section provides functions allowing to:
4099 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
4100 (+) Configure External Clock source.
4101 (+) Configure Complementary channels, break features and dead time.
4102 (+) Configure Master and the Slave synchronization.
4103 (+) Configure the DMA Burst Mode.
4104
4105 @endverbatim
4106 * @{
4107 */
4108
4109 /**
4110 * @brief Initializes the TIM Output Compare Channels according to the specified
4111 * parameters in the TIM_OC_InitTypeDef.
4112 * @param htim TIM Output Compare handle
4113 * @param sConfig TIM Output Compare configuration structure
4114 * @param Channel TIM Channels to configure
4115 * This parameter can be one of the following values:
4116 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4117 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4118 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4119 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4120 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
4121 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
4122 * @retval HAL status
4123 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4124 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
4125 const TIM_OC_InitTypeDef *sConfig,
4126 uint32_t Channel)
4127 {
4128 HAL_StatusTypeDef status = HAL_OK;
4129
4130 /* Check the parameters */
4131 assert_param(IS_TIM_CHANNELS(Channel));
4132 assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
4133 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4134
4135 /* Process Locked */
4136 __HAL_LOCK(htim);
4137
4138 switch (Channel)
4139 {
4140 case TIM_CHANNEL_1:
4141 {
4142 /* Check the parameters */
4143 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4144
4145 /* Configure the TIM Channel 1 in Output Compare */
4146 TIM_OC1_SetConfig(htim->Instance, sConfig);
4147 break;
4148 }
4149
4150 case TIM_CHANNEL_2:
4151 {
4152 /* Check the parameters */
4153 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4154
4155 /* Configure the TIM Channel 2 in Output Compare */
4156 TIM_OC2_SetConfig(htim->Instance, sConfig);
4157 break;
4158 }
4159
4160 case TIM_CHANNEL_3:
4161 {
4162 /* Check the parameters */
4163 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4164
4165 /* Configure the TIM Channel 3 in Output Compare */
4166 TIM_OC3_SetConfig(htim->Instance, sConfig);
4167 break;
4168 }
4169
4170 case TIM_CHANNEL_4:
4171 {
4172 /* Check the parameters */
4173 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4174
4175 /* Configure the TIM Channel 4 in Output Compare */
4176 TIM_OC4_SetConfig(htim->Instance, sConfig);
4177 break;
4178 }
4179
4180 case TIM_CHANNEL_5:
4181 {
4182 /* Check the parameters */
4183 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4184
4185 /* Configure the TIM Channel 5 in Output Compare */
4186 TIM_OC5_SetConfig(htim->Instance, sConfig);
4187 break;
4188 }
4189
4190 case TIM_CHANNEL_6:
4191 {
4192 /* Check the parameters */
4193 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4194
4195 /* Configure the TIM Channel 6 in Output Compare */
4196 TIM_OC6_SetConfig(htim->Instance, sConfig);
4197 break;
4198 }
4199
4200 default:
4201 status = HAL_ERROR;
4202 break;
4203 }
4204
4205 __HAL_UNLOCK(htim);
4206
4207 return status;
4208 }
4209
4210 /**
4211 * @brief Initializes the TIM Input Capture Channels according to the specified
4212 * parameters in the TIM_IC_InitTypeDef.
4213 * @param htim TIM IC handle
4214 * @param sConfig TIM Input Capture configuration structure
4215 * @param Channel TIM Channel to configure
4216 * This parameter can be one of the following values:
4217 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4218 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4219 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4220 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4221 * @retval HAL status
4222 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4223 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4224 {
4225 HAL_StatusTypeDef status = HAL_OK;
4226
4227 /* Check the parameters */
4228 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4229 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4230 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4231 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4232 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4233
4234 /* Process Locked */
4235 __HAL_LOCK(htim);
4236
4237 if (Channel == TIM_CHANNEL_1)
4238 {
4239 /* TI1 Configuration */
4240 TIM_TI1_SetConfig(htim->Instance,
4241 sConfig->ICPolarity,
4242 sConfig->ICSelection,
4243 sConfig->ICFilter);
4244
4245 /* Reset the IC1PSC Bits */
4246 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4247
4248 /* Set the IC1PSC value */
4249 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4250 }
4251 else if (Channel == TIM_CHANNEL_2)
4252 {
4253 /* TI2 Configuration */
4254 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4255
4256 TIM_TI2_SetConfig(htim->Instance,
4257 sConfig->ICPolarity,
4258 sConfig->ICSelection,
4259 sConfig->ICFilter);
4260
4261 /* Reset the IC2PSC Bits */
4262 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4263
4264 /* Set the IC2PSC value */
4265 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4266 }
4267 else if (Channel == TIM_CHANNEL_3)
4268 {
4269 /* TI3 Configuration */
4270 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4271
4272 TIM_TI3_SetConfig(htim->Instance,
4273 sConfig->ICPolarity,
4274 sConfig->ICSelection,
4275 sConfig->ICFilter);
4276
4277 /* Reset the IC3PSC Bits */
4278 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4279
4280 /* Set the IC3PSC value */
4281 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4282 }
4283 else if (Channel == TIM_CHANNEL_4)
4284 {
4285 /* TI4 Configuration */
4286 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4287
4288 TIM_TI4_SetConfig(htim->Instance,
4289 sConfig->ICPolarity,
4290 sConfig->ICSelection,
4291 sConfig->ICFilter);
4292
4293 /* Reset the IC4PSC Bits */
4294 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4295
4296 /* Set the IC4PSC value */
4297 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4298 }
4299 else
4300 {
4301 status = HAL_ERROR;
4302 }
4303
4304 __HAL_UNLOCK(htim);
4305
4306 return status;
4307 }
4308
4309 /**
4310 * @brief Initializes the TIM PWM channels according to the specified
4311 * parameters in the TIM_OC_InitTypeDef.
4312 * @param htim TIM PWM handle
4313 * @param sConfig TIM PWM configuration structure
4314 * @param Channel TIM Channels to be configured
4315 * This parameter can be one of the following values:
4316 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4317 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4318 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4319 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4320 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
4321 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
4322 * @retval HAL status
4323 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,const TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4324 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4325 const TIM_OC_InitTypeDef *sConfig,
4326 uint32_t Channel)
4327 {
4328 HAL_StatusTypeDef status = HAL_OK;
4329
4330 /* Check the parameters */
4331 assert_param(IS_TIM_CHANNELS(Channel));
4332 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4333 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4334 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4335
4336 /* Process Locked */
4337 __HAL_LOCK(htim);
4338
4339 switch (Channel)
4340 {
4341 case TIM_CHANNEL_1:
4342 {
4343 /* Check the parameters */
4344 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4345
4346 /* Configure the Channel 1 in PWM mode */
4347 TIM_OC1_SetConfig(htim->Instance, sConfig);
4348
4349 /* Set the Preload enable bit for channel1 */
4350 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4351
4352 /* Configure the Output Fast mode */
4353 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4354 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4355 break;
4356 }
4357
4358 case TIM_CHANNEL_2:
4359 {
4360 /* Check the parameters */
4361 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4362
4363 /* Configure the Channel 2 in PWM mode */
4364 TIM_OC2_SetConfig(htim->Instance, sConfig);
4365
4366 /* Set the Preload enable bit for channel2 */
4367 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4368
4369 /* Configure the Output Fast mode */
4370 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4371 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4372 break;
4373 }
4374
4375 case TIM_CHANNEL_3:
4376 {
4377 /* Check the parameters */
4378 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4379
4380 /* Configure the Channel 3 in PWM mode */
4381 TIM_OC3_SetConfig(htim->Instance, sConfig);
4382
4383 /* Set the Preload enable bit for channel3 */
4384 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4385
4386 /* Configure the Output Fast mode */
4387 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4388 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4389 break;
4390 }
4391
4392 case TIM_CHANNEL_4:
4393 {
4394 /* Check the parameters */
4395 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4396
4397 /* Configure the Channel 4 in PWM mode */
4398 TIM_OC4_SetConfig(htim->Instance, sConfig);
4399
4400 /* Set the Preload enable bit for channel4 */
4401 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4402
4403 /* Configure the Output Fast mode */
4404 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4405 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4406 break;
4407 }
4408
4409 case TIM_CHANNEL_5:
4410 {
4411 /* Check the parameters */
4412 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4413
4414 /* Configure the Channel 5 in PWM mode */
4415 TIM_OC5_SetConfig(htim->Instance, sConfig);
4416
4417 /* Set the Preload enable bit for channel5*/
4418 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
4419
4420 /* Configure the Output Fast mode */
4421 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
4422 htim->Instance->CCMR3 |= sConfig->OCFastMode;
4423 break;
4424 }
4425
4426 case TIM_CHANNEL_6:
4427 {
4428 /* Check the parameters */
4429 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4430
4431 /* Configure the Channel 6 in PWM mode */
4432 TIM_OC6_SetConfig(htim->Instance, sConfig);
4433
4434 /* Set the Preload enable bit for channel6 */
4435 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
4436
4437 /* Configure the Output Fast mode */
4438 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
4439 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
4440 break;
4441 }
4442
4443 default:
4444 status = HAL_ERROR;
4445 break;
4446 }
4447
4448 __HAL_UNLOCK(htim);
4449
4450 return status;
4451 }
4452
4453 /**
4454 * @brief Initializes the TIM One Pulse Channels according to the specified
4455 * parameters in the TIM_OnePulse_InitTypeDef.
4456 * @param htim TIM One Pulse handle
4457 * @param sConfig TIM One Pulse configuration structure
4458 * @param OutputChannel TIM output channel to configure
4459 * This parameter can be one of the following values:
4460 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4461 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4462 * @param InputChannel TIM input Channel to configure
4463 * This parameter can be one of the following values:
4464 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4465 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4466 * @note To output a waveform with a minimum delay user can enable the fast
4467 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4468 * output is forced in response to the edge detection on TIx input,
4469 * without taking in account the comparison.
4470 * @retval HAL status
4471 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4472 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4473 uint32_t OutputChannel, uint32_t InputChannel)
4474 {
4475 HAL_StatusTypeDef status = HAL_OK;
4476 TIM_OC_InitTypeDef temp1;
4477
4478 /* Check the parameters */
4479 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4480 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4481
4482 if (OutputChannel != InputChannel)
4483 {
4484 /* Process Locked */
4485 __HAL_LOCK(htim);
4486
4487 htim->State = HAL_TIM_STATE_BUSY;
4488
4489 /* Extract the Output compare configuration from sConfig structure */
4490 temp1.OCMode = sConfig->OCMode;
4491 temp1.Pulse = sConfig->Pulse;
4492 temp1.OCPolarity = sConfig->OCPolarity;
4493 temp1.OCNPolarity = sConfig->OCNPolarity;
4494 temp1.OCIdleState = sConfig->OCIdleState;
4495 temp1.OCNIdleState = sConfig->OCNIdleState;
4496
4497 switch (OutputChannel)
4498 {
4499 case TIM_CHANNEL_1:
4500 {
4501 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4502
4503 TIM_OC1_SetConfig(htim->Instance, &temp1);
4504 break;
4505 }
4506
4507 case TIM_CHANNEL_2:
4508 {
4509 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4510
4511 TIM_OC2_SetConfig(htim->Instance, &temp1);
4512 break;
4513 }
4514
4515 default:
4516 status = HAL_ERROR;
4517 break;
4518 }
4519
4520 if (status == HAL_OK)
4521 {
4522 switch (InputChannel)
4523 {
4524 case TIM_CHANNEL_1:
4525 {
4526 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4527
4528 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4529 sConfig->ICSelection, sConfig->ICFilter);
4530
4531 /* Reset the IC1PSC Bits */
4532 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4533
4534 /* Select the Trigger source */
4535 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4536 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4537
4538 /* Select the Slave Mode */
4539 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4540 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4541 break;
4542 }
4543
4544 case TIM_CHANNEL_2:
4545 {
4546 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4547
4548 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4549 sConfig->ICSelection, sConfig->ICFilter);
4550
4551 /* Reset the IC2PSC Bits */
4552 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4553
4554 /* Select the Trigger source */
4555 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4556 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4557
4558 /* Select the Slave Mode */
4559 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4560 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4561 break;
4562 }
4563
4564 default:
4565 status = HAL_ERROR;
4566 break;
4567 }
4568 }
4569
4570 htim->State = HAL_TIM_STATE_READY;
4571
4572 __HAL_UNLOCK(htim);
4573
4574 return status;
4575 }
4576 else
4577 {
4578 return HAL_ERROR;
4579 }
4580 }
4581
4582 /**
4583 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4584 * @param htim TIM handle
4585 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4586 * This parameter can be one of the following values:
4587 * @arg TIM_DMABASE_CR1
4588 * @arg TIM_DMABASE_CR2
4589 * @arg TIM_DMABASE_SMCR
4590 * @arg TIM_DMABASE_DIER
4591 * @arg TIM_DMABASE_SR
4592 * @arg TIM_DMABASE_EGR
4593 * @arg TIM_DMABASE_CCMR1
4594 * @arg TIM_DMABASE_CCMR2
4595 * @arg TIM_DMABASE_CCER
4596 * @arg TIM_DMABASE_CNT
4597 * @arg TIM_DMABASE_PSC
4598 * @arg TIM_DMABASE_ARR
4599 * @arg TIM_DMABASE_RCR
4600 * @arg TIM_DMABASE_CCR1
4601 * @arg TIM_DMABASE_CCR2
4602 * @arg TIM_DMABASE_CCR3
4603 * @arg TIM_DMABASE_CCR4
4604 * @arg TIM_DMABASE_BDTR
4605 * @arg TIM_DMABASE_CCMR3
4606 * @arg TIM_DMABASE_CCR5
4607 * @arg TIM_DMABASE_CCR6
4608 * @arg TIM_DMABASE_DTR2
4609 * @arg TIM_DMABASE_ECR
4610 * @arg TIM_DMABASE_TISEL
4611 * @arg TIM_DMABASE_AF1
4612 * @arg TIM_DMABASE_AF2
4613 * @param BurstRequestSrc TIM DMA Request sources
4614 * This parameter can be one of the following values:
4615 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4616 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4617 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4618 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4619 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4620 * @arg TIM_DMA_COM: TIM Commutation DMA source
4621 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4622 * @param BurstBuffer The Buffer address.
4623 * @param BurstLength DMA Burst length. This parameter can be one value
4624 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4625 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4626 * @retval HAL status
4627 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength)4628 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4629 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4630 uint32_t BurstLength)
4631 {
4632 HAL_StatusTypeDef status = HAL_OK;
4633 uint32_t BlockDataLength = 0;
4634 uint32_t data_width;
4635 const DMA_HandleTypeDef *hdma = NULL;
4636
4637 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4638
4639 switch (BurstRequestSrc)
4640 {
4641 case TIM_DMA_UPDATE:
4642 {
4643 hdma = htim->hdma[TIM_DMA_ID_UPDATE];
4644 break;
4645 }
4646 case TIM_DMA_CC1:
4647 {
4648 hdma = htim->hdma[TIM_DMA_ID_CC1];
4649 break;
4650 }
4651 case TIM_DMA_CC2:
4652 {
4653 hdma = htim->hdma[TIM_DMA_ID_CC2];
4654 break;
4655 }
4656 case TIM_DMA_CC3:
4657 {
4658 hdma = htim->hdma[TIM_DMA_ID_CC3];
4659 break;
4660 }
4661 case TIM_DMA_CC4:
4662 {
4663 hdma = htim->hdma[TIM_DMA_ID_CC4];
4664 break;
4665 }
4666 case TIM_DMA_COM:
4667 {
4668 hdma = htim->hdma[TIM_DMA_ID_COMMUTATION];
4669 break;
4670 }
4671 case TIM_DMA_TRIGGER:
4672 {
4673 hdma = htim->hdma[TIM_DMA_ID_TRIGGER];
4674 break;
4675 }
4676 default:
4677 status = HAL_ERROR;
4678 break;
4679 }
4680
4681 if (hdma != NULL)
4682 {
4683
4684 if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U)
4685 && (hdma->LinkedListQueue->Head != 0U))
4686 {
4687 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2;
4688 }
4689 else
4690 {
4691 data_width = hdma->Init.SrcDataWidth;
4692 }
4693
4694 switch (data_width)
4695 {
4696 case DMA_SRC_DATAWIDTH_BYTE:
4697 {
4698 BlockDataLength = (BurstLength >> TIM_DCR_DBL_Pos) + 1UL;
4699 break;
4700 }
4701 case DMA_SRC_DATAWIDTH_HALFWORD:
4702 {
4703 BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL;
4704 break;
4705 }
4706 case DMA_SRC_DATAWIDTH_WORD:
4707 {
4708 BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL;
4709 break;
4710 }
4711 default:
4712 status = HAL_ERROR;
4713 break;
4714 }
4715
4716 if (status == HAL_OK)
4717 {
4718 status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4719 BlockDataLength);
4720 }
4721 }
4722
4723
4724 return status;
4725 }
4726
4727 /**
4728 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4729 * @param htim TIM handle
4730 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4731 * This parameter can be one of the following values:
4732 * @arg TIM_DMABASE_CR1
4733 * @arg TIM_DMABASE_CR2
4734 * @arg TIM_DMABASE_SMCR
4735 * @arg TIM_DMABASE_DIER
4736 * @arg TIM_DMABASE_SR
4737 * @arg TIM_DMABASE_EGR
4738 * @arg TIM_DMABASE_CCMR1
4739 * @arg TIM_DMABASE_CCMR2
4740 * @arg TIM_DMABASE_CCER
4741 * @arg TIM_DMABASE_CNT
4742 * @arg TIM_DMABASE_PSC
4743 * @arg TIM_DMABASE_ARR
4744 * @arg TIM_DMABASE_RCR
4745 * @arg TIM_DMABASE_CCR1
4746 * @arg TIM_DMABASE_CCR2
4747 * @arg TIM_DMABASE_CCR3
4748 * @arg TIM_DMABASE_CCR4
4749 * @arg TIM_DMABASE_BDTR
4750 * @arg TIM_DMABASE_CCMR3
4751 * @arg TIM_DMABASE_CCR5
4752 * @arg TIM_DMABASE_CCR6
4753 * @arg TIM_DMABASE_DTR2
4754 * @arg TIM_DMABASE_ECR
4755 * @arg TIM_DMABASE_TISEL
4756 * @arg TIM_DMABASE_AF1
4757 * @arg TIM_DMABASE_AF2
4758 * @param BurstRequestSrc TIM DMA Request sources
4759 * This parameter can be one of the following values:
4760 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4761 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4762 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4763 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4764 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4765 * @arg TIM_DMA_COM: TIM Commutation DMA source
4766 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4767 * @param BurstBuffer The Buffer address.
4768 * @param BurstLength DMA Burst length. This parameter can be one value
4769 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4770 * @param DataLength Data length. This parameter can be one value
4771 * between 1 and 0xFFFF.
4772 * @retval HAL status
4773 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,const uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4774 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4775 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
4776 uint32_t BurstLength, uint32_t DataLength)
4777 {
4778 HAL_StatusTypeDef status = HAL_OK;
4779 uint32_t tmpDBSS = 0;
4780
4781 /* Check the parameters */
4782 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4783 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4784 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4785 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4786 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4787
4788 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4789 {
4790 return HAL_BUSY;
4791 }
4792 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4793 {
4794 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4795 {
4796 return HAL_ERROR;
4797 }
4798 else
4799 {
4800 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4801 }
4802 }
4803 else
4804 {
4805 /* nothing to do */
4806 }
4807
4808 switch (BurstRequestSrc)
4809 {
4810 case TIM_DMA_UPDATE:
4811 {
4812 /* Set the DMA Period elapsed callbacks */
4813 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4814 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4815
4816 /* Set the DMA error callback */
4817 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4818
4819 /* Enable the DMA channel */
4820 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4821 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4822 {
4823 /* Return error status */
4824 return HAL_ERROR;
4825 }
4826 /* Configure the DMA Burst Source Selection */
4827 tmpDBSS = TIM_DCR_DBSS_0;
4828 break;
4829 }
4830 case TIM_DMA_CC1:
4831 {
4832 /* Set the DMA compare callbacks */
4833 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4834 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4835
4836 /* Set the DMA error callback */
4837 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4838
4839 /* Enable the DMA channel */
4840 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4841 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4842 {
4843 /* Return error status */
4844 return HAL_ERROR;
4845 }
4846 /* Configure the DMA Burst Source Selection */
4847 tmpDBSS = TIM_DCR_DBSS_1;
4848 break;
4849 }
4850 case TIM_DMA_CC2:
4851 {
4852 /* Set the DMA compare callbacks */
4853 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4854 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4855
4856 /* Set the DMA error callback */
4857 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4858
4859 /* Enable the DMA channel */
4860 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4861 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4862 {
4863 /* Return error status */
4864 return HAL_ERROR;
4865 }
4866 /* Configure the DMA Burst Source Selection */
4867 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
4868 break;
4869 }
4870 case TIM_DMA_CC3:
4871 {
4872 /* Set the DMA compare callbacks */
4873 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4874 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4875
4876 /* Set the DMA error callback */
4877 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4878
4879 /* Enable the DMA channel */
4880 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4881 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4882 {
4883 /* Return error status */
4884 return HAL_ERROR;
4885 }
4886 /* Configure the DMA Burst Source Selection */
4887 tmpDBSS = TIM_DCR_DBSS_2;
4888 break;
4889 }
4890 case TIM_DMA_CC4:
4891 {
4892 /* Set the DMA compare callbacks */
4893 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4894 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4895
4896 /* Set the DMA error callback */
4897 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4898
4899 /* Enable the DMA channel */
4900 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4901 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4902 {
4903 /* Return error status */
4904 return HAL_ERROR;
4905 }
4906 /* Configure the DMA Burst Source Selection */
4907 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0);
4908 break;
4909 }
4910 case TIM_DMA_COM:
4911 {
4912 /* Set the DMA commutation callbacks */
4913 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4914 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4915
4916 /* Set the DMA error callback */
4917 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4918
4919 /* Enable the DMA channel */
4920 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4921 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4922 {
4923 /* Return error status */
4924 return HAL_ERROR;
4925 }
4926 /* Configure the DMA Burst Source Selection */
4927 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1);
4928 break;
4929 }
4930 case TIM_DMA_TRIGGER:
4931 {
4932 /* Set the DMA trigger callbacks */
4933 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4934 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4935
4936 /* Set the DMA error callback */
4937 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4938
4939 /* Enable the DMA channel */
4940 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4941 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4942 {
4943 /* Return error status */
4944 return HAL_ERROR;
4945 }
4946 /* Configure the DMA Burst Source Selection */
4947 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
4948 break;
4949 }
4950 default:
4951 status = HAL_ERROR;
4952 break;
4953 }
4954
4955 if (status == HAL_OK)
4956 {
4957 /* Configure the DMA Burst Mode */
4958 htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS);
4959 /* Enable the TIM DMA Request */
4960 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4961 }
4962
4963 /* Return function status */
4964 return status;
4965 }
4966
4967 /**
4968 * @brief Stops the TIM DMA Burst mode
4969 * @param htim TIM handle
4970 * @param BurstRequestSrc TIM DMA Request sources to disable
4971 * @retval HAL status
4972 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4973 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4974 {
4975 HAL_StatusTypeDef status = HAL_OK;
4976
4977 /* Check the parameters */
4978 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4979
4980 /* Abort the DMA transfer (at least disable the DMA channel) */
4981 switch (BurstRequestSrc)
4982 {
4983 case TIM_DMA_UPDATE:
4984 {
4985 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4986 break;
4987 }
4988 case TIM_DMA_CC1:
4989 {
4990 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4991 break;
4992 }
4993 case TIM_DMA_CC2:
4994 {
4995 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4996 break;
4997 }
4998 case TIM_DMA_CC3:
4999 {
5000 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5001 break;
5002 }
5003 case TIM_DMA_CC4:
5004 {
5005 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5006 break;
5007 }
5008 case TIM_DMA_COM:
5009 {
5010 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5011 break;
5012 }
5013 case TIM_DMA_TRIGGER:
5014 {
5015 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5016 break;
5017 }
5018 default:
5019 status = HAL_ERROR;
5020 break;
5021 }
5022
5023 if (status == HAL_OK)
5024 {
5025 /* Disable the TIM Update DMA request */
5026 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5027
5028 /* Change the DMA burst operation state */
5029 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5030 }
5031
5032 /* Return function status */
5033 return status;
5034 }
5035
5036 /**
5037 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
5038 * @param htim TIM handle
5039 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
5040 * This parameter can be one of the following values:
5041 * @arg TIM_DMABASE_CR1
5042 * @arg TIM_DMABASE_CR2
5043 * @arg TIM_DMABASE_SMCR
5044 * @arg TIM_DMABASE_DIER
5045 * @arg TIM_DMABASE_SR
5046 * @arg TIM_DMABASE_EGR
5047 * @arg TIM_DMABASE_CCMR1
5048 * @arg TIM_DMABASE_CCMR2
5049 * @arg TIM_DMABASE_CCER
5050 * @arg TIM_DMABASE_CNT
5051 * @arg TIM_DMABASE_PSC
5052 * @arg TIM_DMABASE_ARR
5053 * @arg TIM_DMABASE_RCR
5054 * @arg TIM_DMABASE_CCR1
5055 * @arg TIM_DMABASE_CCR2
5056 * @arg TIM_DMABASE_CCR3
5057 * @arg TIM_DMABASE_CCR4
5058 * @arg TIM_DMABASE_BDTR
5059 * @arg TIM_DMABASE_CCMR3
5060 * @arg TIM_DMABASE_CCR5
5061 * @arg TIM_DMABASE_CCR6
5062 * @arg TIM_DMABASE_DTR2
5063 * @arg TIM_DMABASE_ECR
5064 * @arg TIM_DMABASE_TISEL
5065 * @arg TIM_DMABASE_AF1
5066 * @arg TIM_DMABASE_AF2
5067 * @param BurstRequestSrc TIM DMA Request sources
5068 * This parameter can be one of the following values:
5069 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
5070 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
5071 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
5072 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
5073 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
5074 * @arg TIM_DMA_COM: TIM Commutation DMA source
5075 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
5076 * @param BurstBuffer The Buffer address.
5077 * @param BurstLength DMA Burst length. This parameter can be one value
5078 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
5079 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
5080 * @retval HAL status
5081 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)5082 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
5083 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
5084 {
5085 HAL_StatusTypeDef status = HAL_OK;
5086 uint32_t BlockDataLength = 0;
5087 uint32_t data_width;
5088 const DMA_HandleTypeDef *hdma = NULL;
5089
5090 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5091
5092 switch (BurstRequestSrc)
5093 {
5094 case TIM_DMA_UPDATE:
5095 {
5096 hdma = htim->hdma[TIM_DMA_ID_UPDATE];
5097 break;
5098 }
5099 case TIM_DMA_CC1:
5100 {
5101 hdma = htim->hdma[TIM_DMA_ID_CC1];
5102 break;
5103 }
5104 case TIM_DMA_CC2:
5105 {
5106 hdma = htim->hdma[TIM_DMA_ID_CC2];
5107 break;
5108 }
5109 case TIM_DMA_CC3:
5110 {
5111 hdma = htim->hdma[TIM_DMA_ID_CC3];
5112 break;
5113 }
5114 case TIM_DMA_CC4:
5115 {
5116 hdma = htim->hdma[TIM_DMA_ID_CC4];
5117 break;
5118 }
5119 case TIM_DMA_COM:
5120 {
5121 hdma = htim->hdma[TIM_DMA_ID_COMMUTATION];
5122 break;
5123 }
5124 case TIM_DMA_TRIGGER:
5125 {
5126 hdma = htim->hdma[TIM_DMA_ID_TRIGGER];
5127 break;
5128 }
5129 default:
5130 status = HAL_ERROR;
5131 break;
5132 }
5133
5134 if (hdma != NULL)
5135 {
5136
5137 if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U)
5138 && (hdma->LinkedListQueue->Head != 0U))
5139 {
5140 data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2;
5141 }
5142 else
5143 {
5144 data_width = hdma->Init.SrcDataWidth;
5145 }
5146
5147 switch (data_width)
5148
5149 {
5150 case DMA_SRC_DATAWIDTH_BYTE:
5151 {
5152 BlockDataLength = ((BurstLength) >> TIM_DCR_DBL_Pos) + 1UL;
5153 break;
5154 }
5155 case DMA_SRC_DATAWIDTH_HALFWORD:
5156 {
5157 BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL;
5158 break;
5159 }
5160 case DMA_SRC_DATAWIDTH_WORD:
5161 {
5162 BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL;
5163 break;
5164 }
5165 default:
5166 status = HAL_ERROR;
5167 break;
5168 }
5169
5170 if (status == HAL_OK)
5171 {
5172 status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
5173 BlockDataLength);
5174 }
5175 }
5176
5177 return status;
5178 }
5179
5180 /**
5181 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
5182 * @param htim TIM handle
5183 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
5184 * This parameter can be one of the following values:
5185 * @arg TIM_DMABASE_CR1
5186 * @arg TIM_DMABASE_CR2
5187 * @arg TIM_DMABASE_SMCR
5188 * @arg TIM_DMABASE_DIER
5189 * @arg TIM_DMABASE_SR
5190 * @arg TIM_DMABASE_EGR
5191 * @arg TIM_DMABASE_CCMR1
5192 * @arg TIM_DMABASE_CCMR2
5193 * @arg TIM_DMABASE_CCER
5194 * @arg TIM_DMABASE_CNT
5195 * @arg TIM_DMABASE_PSC
5196 * @arg TIM_DMABASE_ARR
5197 * @arg TIM_DMABASE_RCR
5198 * @arg TIM_DMABASE_CCR1
5199 * @arg TIM_DMABASE_CCR2
5200 * @arg TIM_DMABASE_CCR3
5201 * @arg TIM_DMABASE_CCR4
5202 * @arg TIM_DMABASE_BDTR
5203 * @arg TIM_DMABASE_CCMR3
5204 * @arg TIM_DMABASE_CCR5
5205 * @arg TIM_DMABASE_CCR6
5206 * @arg TIM_DMABASE_DTR2
5207 * @arg TIM_DMABASE_ECR
5208 * @arg TIM_DMABASE_TISEL
5209 * @arg TIM_DMABASE_AF1
5210 * @arg TIM_DMABASE_AF2
5211 * @param BurstRequestSrc TIM DMA Request sources
5212 * This parameter can be one of the following values:
5213 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
5214 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
5215 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
5216 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
5217 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
5218 * @arg TIM_DMA_COM: TIM Commutation DMA source
5219 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
5220 * @param BurstBuffer The Buffer address.
5221 * @param BurstLength DMA Burst length. This parameter can be one value
5222 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
5223 * @param DataLength Data length. This parameter can be one value
5224 * between 1 and 0xFFFF.
5225 * @retval HAL status
5226 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)5227 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
5228 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
5229 uint32_t BurstLength, uint32_t DataLength)
5230 {
5231 HAL_StatusTypeDef status = HAL_OK;
5232 uint32_t tmpDBSS = 0;
5233
5234 /* Check the parameters */
5235 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
5236 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
5237 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5238 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
5239 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
5240
5241 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
5242 {
5243 return HAL_BUSY;
5244 }
5245 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
5246 {
5247 if ((BurstBuffer == NULL) && (BurstLength > 0U))
5248 {
5249 return HAL_ERROR;
5250 }
5251 else
5252 {
5253 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
5254 }
5255 }
5256 else
5257 {
5258 /* nothing to do */
5259 }
5260 switch (BurstRequestSrc)
5261 {
5262 case TIM_DMA_UPDATE:
5263 {
5264 /* Set the DMA Period elapsed callbacks */
5265 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
5266 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
5267
5268 /* Set the DMA error callback */
5269 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
5270
5271 /* Enable the DMA channel */
5272 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5273 DataLength) != HAL_OK)
5274 {
5275 /* Return error status */
5276 return HAL_ERROR;
5277 }
5278 /* Configure the DMA Burst Source Selection */
5279 tmpDBSS = TIM_DCR_DBSS_0;
5280 break;
5281 }
5282 case TIM_DMA_CC1:
5283 {
5284 /* Set the DMA capture callbacks */
5285 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
5286 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5287
5288 /* Set the DMA error callback */
5289 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
5290
5291 /* Enable the DMA channel */
5292 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5293 DataLength) != HAL_OK)
5294 {
5295 /* Return error status */
5296 return HAL_ERROR;
5297 }
5298 /* Configure the DMA Burst Source Selection */
5299 tmpDBSS = TIM_DCR_DBSS_1;
5300 break;
5301 }
5302 case TIM_DMA_CC2:
5303 {
5304 /* Set the DMA capture callbacks */
5305 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
5306 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5307
5308 /* Set the DMA error callback */
5309 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
5310
5311 /* Enable the DMA channel */
5312 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5313 DataLength) != HAL_OK)
5314 {
5315 /* Return error status */
5316 return HAL_ERROR;
5317 }
5318 /* Configure the DMA Burst Source Selection */
5319 tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
5320 break;
5321 }
5322 case TIM_DMA_CC3:
5323 {
5324 /* Set the DMA capture callbacks */
5325 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
5326 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5327
5328 /* Set the DMA error callback */
5329 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
5330
5331 /* Enable the DMA channel */
5332 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5333 DataLength) != HAL_OK)
5334 {
5335 /* Return error status */
5336 return HAL_ERROR;
5337 }
5338 /* Configure the DMA Burst Source Selection */
5339 tmpDBSS = TIM_DCR_DBSS_2;
5340 break;
5341 }
5342 case TIM_DMA_CC4:
5343 {
5344 /* Set the DMA capture callbacks */
5345 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
5346 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
5347
5348 /* Set the DMA error callback */
5349 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
5350
5351 /* Enable the DMA channel */
5352 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5353 DataLength) != HAL_OK)
5354 {
5355 /* Return error status */
5356 return HAL_ERROR;
5357 }
5358 /* Configure the DMA Burst Source Selection */
5359 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0);
5360 break;
5361 }
5362 case TIM_DMA_COM:
5363 {
5364 /* Set the DMA commutation callbacks */
5365 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
5366 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
5367
5368 /* Set the DMA error callback */
5369 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
5370
5371 /* Enable the DMA channel */
5372 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5373 DataLength) != HAL_OK)
5374 {
5375 /* Return error status */
5376 return HAL_ERROR;
5377 }
5378 /* Configure the DMA Burst Source Selection */
5379 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1);
5380 break;
5381 }
5382 case TIM_DMA_TRIGGER:
5383 {
5384 /* Set the DMA trigger callbacks */
5385 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
5386 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
5387
5388 /* Set the DMA error callback */
5389 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
5390
5391 /* Enable the DMA channel */
5392 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
5393 DataLength) != HAL_OK)
5394 {
5395 /* Return error status */
5396 return HAL_ERROR;
5397 }
5398 /* Configure the DMA Burst Source Selection */
5399 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0);
5400 break;
5401 }
5402 default:
5403 status = HAL_ERROR;
5404 break;
5405 }
5406
5407 if (status == HAL_OK)
5408 {
5409 /* Configure the DMA Burst Mode */
5410 htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS);
5411
5412 /* Enable the TIM DMA Request */
5413 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
5414 }
5415
5416 /* Return function status */
5417 return status;
5418 }
5419
5420 /**
5421 * @brief Stop the DMA burst reading
5422 * @param htim TIM handle
5423 * @param BurstRequestSrc TIM DMA Request sources to disable.
5424 * @retval HAL status
5425 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)5426 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
5427 {
5428 HAL_StatusTypeDef status = HAL_OK;
5429
5430 /* Check the parameters */
5431 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
5432
5433 /* Abort the DMA transfer (at least disable the DMA channel) */
5434 switch (BurstRequestSrc)
5435 {
5436 case TIM_DMA_UPDATE:
5437 {
5438 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
5439 break;
5440 }
5441 case TIM_DMA_CC1:
5442 {
5443 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
5444 break;
5445 }
5446 case TIM_DMA_CC2:
5447 {
5448 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
5449 break;
5450 }
5451 case TIM_DMA_CC3:
5452 {
5453 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
5454 break;
5455 }
5456 case TIM_DMA_CC4:
5457 {
5458 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
5459 break;
5460 }
5461 case TIM_DMA_COM:
5462 {
5463 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5464 break;
5465 }
5466 case TIM_DMA_TRIGGER:
5467 {
5468 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5469 break;
5470 }
5471 default:
5472 status = HAL_ERROR;
5473 break;
5474 }
5475
5476 if (status == HAL_OK)
5477 {
5478 /* Disable the TIM Update DMA request */
5479 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5480
5481 /* Change the DMA burst operation state */
5482 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5483 }
5484
5485 /* Return function status */
5486 return status;
5487 }
5488
5489 /**
5490 * @brief Generate a software event
5491 * @param htim TIM handle
5492 * @param EventSource specifies the event source.
5493 * This parameter can be one of the following values:
5494 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5495 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5496 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5497 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5498 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5499 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
5500 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5501 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5502 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
5503 * @note Basic timers can only generate an update event.
5504 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5505 * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
5506 * only for timer instances supporting break input(s).
5507 * @retval HAL status
5508 */
5509
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5510 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5511 {
5512 /* Check the parameters */
5513 assert_param(IS_TIM_INSTANCE(htim->Instance));
5514 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5515
5516 /* Process Locked */
5517 __HAL_LOCK(htim);
5518
5519 /* Change the TIM state */
5520 htim->State = HAL_TIM_STATE_BUSY;
5521
5522 /* Set the event sources */
5523 htim->Instance->EGR = EventSource;
5524
5525 /* Change the TIM state */
5526 htim->State = HAL_TIM_STATE_READY;
5527
5528 __HAL_UNLOCK(htim);
5529
5530 /* Return function status */
5531 return HAL_OK;
5532 }
5533
5534 /**
5535 * @brief Configures the OCRef clear feature
5536 * @param htim TIM handle
5537 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5538 * contains the OCREF clear feature and parameters for the TIM peripheral.
5539 * @param Channel specifies the TIM Channel
5540 * This parameter can be one of the following values:
5541 * @arg TIM_CHANNEL_1: TIM Channel 1
5542 * @arg TIM_CHANNEL_2: TIM Channel 2
5543 * @arg TIM_CHANNEL_3: TIM Channel 3
5544 * @arg TIM_CHANNEL_4: TIM Channel 4
5545 * @arg TIM_CHANNEL_5: TIM Channel 5
5546 * @arg TIM_CHANNEL_6: TIM Channel 6
5547 * @retval HAL status
5548 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,const TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5549 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5550 const TIM_ClearInputConfigTypeDef *sClearInputConfig,
5551 uint32_t Channel)
5552 {
5553 HAL_StatusTypeDef status = HAL_OK;
5554
5555 /* Check the parameters */
5556 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5557 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5558
5559 /* Process Locked */
5560 __HAL_LOCK(htim);
5561
5562 htim->State = HAL_TIM_STATE_BUSY;
5563
5564 switch (sClearInputConfig->ClearInputSource)
5565 {
5566 case TIM_CLEARINPUTSOURCE_NONE:
5567 {
5568 /* Clear the OCREF clear selection bit and the the ETR Bits */
5569 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5570 break;
5571 }
5572
5573 case TIM_CLEARINPUTSOURCE_ETR:
5574 {
5575 /* Check the parameters */
5576 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5577 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5578 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5579
5580 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5581 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5582 {
5583 htim->State = HAL_TIM_STATE_READY;
5584 __HAL_UNLOCK(htim);
5585 return HAL_ERROR;
5586 }
5587
5588 TIM_ETR_SetConfig(htim->Instance,
5589 sClearInputConfig->ClearInputPrescaler,
5590 sClearInputConfig->ClearInputPolarity,
5591 sClearInputConfig->ClearInputFilter);
5592 break;
5593 }
5594
5595 default:
5596 status = HAL_ERROR;
5597 break;
5598 }
5599
5600 if (status == HAL_OK)
5601 {
5602 switch (Channel)
5603 {
5604 case TIM_CHANNEL_1:
5605 {
5606 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5607 {
5608 /* Enable the OCREF clear feature for Channel 1 */
5609 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5610 }
5611 else
5612 {
5613 /* Disable the OCREF clear feature for Channel 1 */
5614 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5615 }
5616 break;
5617 }
5618 case TIM_CHANNEL_2:
5619 {
5620 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5621 {
5622 /* Enable the OCREF clear feature for Channel 2 */
5623 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5624 }
5625 else
5626 {
5627 /* Disable the OCREF clear feature for Channel 2 */
5628 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5629 }
5630 break;
5631 }
5632 case TIM_CHANNEL_3:
5633 {
5634 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5635 {
5636 /* Enable the OCREF clear feature for Channel 3 */
5637 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5638 }
5639 else
5640 {
5641 /* Disable the OCREF clear feature for Channel 3 */
5642 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5643 }
5644 break;
5645 }
5646 case TIM_CHANNEL_4:
5647 {
5648 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5649 {
5650 /* Enable the OCREF clear feature for Channel 4 */
5651 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5652 }
5653 else
5654 {
5655 /* Disable the OCREF clear feature for Channel 4 */
5656 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5657 }
5658 break;
5659 }
5660 case TIM_CHANNEL_5:
5661 {
5662 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5663 {
5664 /* Enable the OCREF clear feature for Channel 5 */
5665 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5666 }
5667 else
5668 {
5669 /* Disable the OCREF clear feature for Channel 5 */
5670 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5671 }
5672 break;
5673 }
5674 case TIM_CHANNEL_6:
5675 {
5676 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5677 {
5678 /* Enable the OCREF clear feature for Channel 6 */
5679 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5680 }
5681 else
5682 {
5683 /* Disable the OCREF clear feature for Channel 6 */
5684 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5685 }
5686 break;
5687 }
5688 default:
5689 break;
5690 }
5691 }
5692
5693 htim->State = HAL_TIM_STATE_READY;
5694
5695 __HAL_UNLOCK(htim);
5696
5697 return status;
5698 }
5699
5700 /**
5701 * @brief Configures the clock source to be used
5702 * @param htim TIM handle
5703 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5704 * contains the clock source information for the TIM peripheral.
5705 * @retval HAL status
5706 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,const TIM_ClockConfigTypeDef * sClockSourceConfig)5707 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
5708 {
5709 HAL_StatusTypeDef status = HAL_OK;
5710 uint32_t tmpsmcr;
5711
5712 /* Process Locked */
5713 __HAL_LOCK(htim);
5714
5715 htim->State = HAL_TIM_STATE_BUSY;
5716
5717 /* Check the parameters */
5718 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5719
5720 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5721 tmpsmcr = htim->Instance->SMCR;
5722 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5723 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5724 htim->Instance->SMCR = tmpsmcr;
5725
5726 switch (sClockSourceConfig->ClockSource)
5727 {
5728 case TIM_CLOCKSOURCE_INTERNAL:
5729 {
5730 assert_param(IS_TIM_INSTANCE(htim->Instance));
5731 break;
5732 }
5733
5734 case TIM_CLOCKSOURCE_ETRMODE1:
5735 {
5736 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5737 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5738
5739 /* Check ETR input conditioning related parameters */
5740 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5741 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5742 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5743
5744 /* Configure the ETR Clock source */
5745 TIM_ETR_SetConfig(htim->Instance,
5746 sClockSourceConfig->ClockPrescaler,
5747 sClockSourceConfig->ClockPolarity,
5748 sClockSourceConfig->ClockFilter);
5749
5750 /* Select the External clock mode1 and the ETRF trigger */
5751 tmpsmcr = htim->Instance->SMCR;
5752 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5753 /* Write to TIMx SMCR */
5754 htim->Instance->SMCR = tmpsmcr;
5755 break;
5756 }
5757
5758 case TIM_CLOCKSOURCE_ETRMODE2:
5759 {
5760 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5761 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5762
5763 /* Check ETR input conditioning related parameters */
5764 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5765 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5766 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5767
5768 /* Configure the ETR Clock source */
5769 TIM_ETR_SetConfig(htim->Instance,
5770 sClockSourceConfig->ClockPrescaler,
5771 sClockSourceConfig->ClockPolarity,
5772 sClockSourceConfig->ClockFilter);
5773 /* Enable the External clock mode2 */
5774 htim->Instance->SMCR |= TIM_SMCR_ECE;
5775 break;
5776 }
5777
5778 case TIM_CLOCKSOURCE_TI1:
5779 {
5780 /* Check whether or not the timer instance supports external clock mode 1 */
5781 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5782
5783 /* Check TI1 input conditioning related parameters */
5784 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5785 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5786
5787 TIM_TI1_ConfigInputStage(htim->Instance,
5788 sClockSourceConfig->ClockPolarity,
5789 sClockSourceConfig->ClockFilter);
5790 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5791 break;
5792 }
5793
5794 case TIM_CLOCKSOURCE_TI2:
5795 {
5796 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5797 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5798
5799 /* Check TI2 input conditioning related parameters */
5800 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5801 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5802
5803 TIM_TI2_ConfigInputStage(htim->Instance,
5804 sClockSourceConfig->ClockPolarity,
5805 sClockSourceConfig->ClockFilter);
5806 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5807 break;
5808 }
5809
5810 case TIM_CLOCKSOURCE_TI1ED:
5811 {
5812 /* Check whether or not the timer instance supports external clock mode 1 */
5813 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5814
5815 /* Check TI1 input conditioning related parameters */
5816 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5817 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5818
5819 TIM_TI1_ConfigInputStage(htim->Instance,
5820 sClockSourceConfig->ClockPolarity,
5821 sClockSourceConfig->ClockFilter);
5822 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5823 break;
5824 }
5825
5826 case TIM_CLOCKSOURCE_ITR0:
5827 case TIM_CLOCKSOURCE_ITR1:
5828 case TIM_CLOCKSOURCE_ITR2:
5829 case TIM_CLOCKSOURCE_ITR3:
5830 case TIM_CLOCKSOURCE_ITR4:
5831 case TIM_CLOCKSOURCE_ITR5:
5832 case TIM_CLOCKSOURCE_ITR6:
5833 case TIM_CLOCKSOURCE_ITR7:
5834 case TIM_CLOCKSOURCE_ITR8:
5835 case TIM_CLOCKSOURCE_ITR9:
5836 case TIM_CLOCKSOURCE_ITR10:
5837 case TIM_CLOCKSOURCE_ITR11:
5838 case TIM_CLOCKSOURCE_ITR13:
5839 case TIM_CLOCKSOURCE_ITR14:
5840 {
5841 /* Check whether or not the timer instance supports internal trigger input */
5842 assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
5843
5844 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5845 break;
5846 }
5847
5848 default:
5849 status = HAL_ERROR;
5850 break;
5851 }
5852 htim->State = HAL_TIM_STATE_READY;
5853
5854 __HAL_UNLOCK(htim);
5855
5856 return status;
5857 }
5858
5859 /**
5860 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5861 * or a XOR combination between CH1_input, CH2_input & CH3_input
5862 * @param htim TIM handle.
5863 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5864 * output of a XOR gate.
5865 * This parameter can be one of the following values:
5866 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5867 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5868 * pins are connected to the TI1 input (XOR combination)
5869 * @retval HAL status
5870 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5871 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5872 {
5873 uint32_t tmpcr2;
5874
5875 /* Check the parameters */
5876 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5877 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5878
5879 /* Get the TIMx CR2 register value */
5880 tmpcr2 = htim->Instance->CR2;
5881
5882 /* Reset the TI1 selection */
5883 tmpcr2 &= ~TIM_CR2_TI1S;
5884
5885 /* Set the TI1 selection */
5886 tmpcr2 |= TI1_Selection;
5887
5888 /* Write to TIMxCR2 */
5889 htim->Instance->CR2 = tmpcr2;
5890
5891 return HAL_OK;
5892 }
5893
5894 /**
5895 * @brief Configures the TIM in Slave mode
5896 * @param htim TIM handle.
5897 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5898 * contains the selected trigger (internal trigger input, filtered
5899 * timer input or external trigger input) and the Slave mode
5900 * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
5901 * @retval HAL status
5902 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5903 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
5904 {
5905 /* Check the parameters */
5906 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5907 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5908 assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
5909
5910 __HAL_LOCK(htim);
5911
5912 htim->State = HAL_TIM_STATE_BUSY;
5913
5914 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5915 {
5916 htim->State = HAL_TIM_STATE_READY;
5917 __HAL_UNLOCK(htim);
5918 return HAL_ERROR;
5919 }
5920
5921 /* Disable Trigger Interrupt */
5922 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5923
5924 /* Disable Trigger DMA request */
5925 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5926
5927 htim->State = HAL_TIM_STATE_READY;
5928
5929 __HAL_UNLOCK(htim);
5930
5931 return HAL_OK;
5932 }
5933
5934 /**
5935 * @brief Configures the TIM in Slave mode in interrupt mode
5936 * @param htim TIM handle.
5937 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5938 * contains the selected trigger (internal trigger input, filtered
5939 * timer input or external trigger input) and the Slave mode
5940 * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
5941 * @retval HAL status
5942 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)5943 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5944 const TIM_SlaveConfigTypeDef *sSlaveConfig)
5945 {
5946 /* Check the parameters */
5947 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5948 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5949 assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
5950
5951 __HAL_LOCK(htim);
5952
5953 htim->State = HAL_TIM_STATE_BUSY;
5954
5955 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5956 {
5957 htim->State = HAL_TIM_STATE_READY;
5958 __HAL_UNLOCK(htim);
5959 return HAL_ERROR;
5960 }
5961
5962 /* Enable Trigger Interrupt */
5963 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5964
5965 /* Disable Trigger DMA request */
5966 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5967
5968 htim->State = HAL_TIM_STATE_READY;
5969
5970 __HAL_UNLOCK(htim);
5971
5972 return HAL_OK;
5973 }
5974
5975 /**
5976 * @brief Read the captured value from Capture Compare unit
5977 * @param htim TIM handle.
5978 * @param Channel TIM Channels to be enabled
5979 * This parameter can be one of the following values:
5980 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5981 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5982 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5983 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5984 * @retval Captured value
5985 */
HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef * htim,uint32_t Channel)5986 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
5987 {
5988 uint32_t tmpreg = 0U;
5989
5990 switch (Channel)
5991 {
5992 case TIM_CHANNEL_1:
5993 {
5994 /* Check the parameters */
5995 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5996
5997 /* Return the capture 1 value */
5998 tmpreg = htim->Instance->CCR1;
5999
6000 break;
6001 }
6002 case TIM_CHANNEL_2:
6003 {
6004 /* Check the parameters */
6005 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6006
6007 /* Return the capture 2 value */
6008 tmpreg = htim->Instance->CCR2;
6009
6010 break;
6011 }
6012
6013 case TIM_CHANNEL_3:
6014 {
6015 /* Check the parameters */
6016 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
6017
6018 /* Return the capture 3 value */
6019 tmpreg = htim->Instance->CCR3;
6020
6021 break;
6022 }
6023
6024 case TIM_CHANNEL_4:
6025 {
6026 /* Check the parameters */
6027 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
6028
6029 /* Return the capture 4 value */
6030 tmpreg = htim->Instance->CCR4;
6031
6032 break;
6033 }
6034
6035 default:
6036 break;
6037 }
6038
6039 return tmpreg;
6040 }
6041
6042 /**
6043 * @brief Start the DMA data transfer.
6044 * @param hdma DMA handle
6045 * @param src : The source memory Buffer address.
6046 * @param dst : The destination memory Buffer address.
6047 * @param length : The size of a source block transfer in byte.
6048 * @retval HAL status
6049 */
TIM_DMA_Start_IT(DMA_HandleTypeDef * hdma,uint32_t src,uint32_t dst,uint32_t length)6050 HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
6051 uint32_t length)
6052 {
6053 HAL_StatusTypeDef status ;
6054
6055 /* Enable the DMA channel */
6056 if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
6057 {
6058 if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U))
6059 {
6060 /* Enable the DMA channel */
6061 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length;
6062 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = src;
6063 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = dst;
6064
6065 status = HAL_DMAEx_List_Start_IT(hdma);
6066 }
6067 else
6068 {
6069 status = HAL_ERROR;
6070 }
6071 }
6072 else
6073 {
6074 status = HAL_DMA_Start_IT(hdma, src, dst, length);
6075 }
6076
6077 return status;
6078 }
6079
6080 /**
6081 * @}
6082 */
6083
6084 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
6085 * @brief TIM Callbacks functions
6086 *
6087 @verbatim
6088 ==============================================================================
6089 ##### TIM Callbacks functions #####
6090 ==============================================================================
6091 [..]
6092 This section provides TIM callback functions:
6093 (+) TIM Period elapsed callback
6094 (+) TIM Output Compare callback
6095 (+) TIM Input capture callback
6096 (+) TIM Trigger callback
6097 (+) TIM Error callback
6098 (+) TIM Index callback
6099 (+) TIM Direction change callback
6100 (+) TIM Index error callback
6101 (+) TIM Transition error callback
6102
6103 @endverbatim
6104 * @{
6105 */
6106
6107 /**
6108 * @brief Period elapsed callback in non-blocking mode
6109 * @param htim TIM handle
6110 * @retval None
6111 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)6112 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
6113 {
6114 /* Prevent unused argument(s) compilation warning */
6115 UNUSED(htim);
6116
6117 /* NOTE : This function should not be modified, when the callback is needed,
6118 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
6119 */
6120 }
6121
6122 /**
6123 * @brief Period elapsed half complete callback in non-blocking mode
6124 * @param htim TIM handle
6125 * @retval None
6126 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)6127 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
6128 {
6129 /* Prevent unused argument(s) compilation warning */
6130 UNUSED(htim);
6131
6132 /* NOTE : This function should not be modified, when the callback is needed,
6133 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
6134 */
6135 }
6136
6137 /**
6138 * @brief Output Compare callback in non-blocking mode
6139 * @param htim TIM OC handle
6140 * @retval None
6141 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)6142 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
6143 {
6144 /* Prevent unused argument(s) compilation warning */
6145 UNUSED(htim);
6146
6147 /* NOTE : This function should not be modified, when the callback is needed,
6148 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
6149 */
6150 }
6151
6152 /**
6153 * @brief Input Capture callback in non-blocking mode
6154 * @param htim TIM IC handle
6155 * @retval None
6156 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)6157 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
6158 {
6159 /* Prevent unused argument(s) compilation warning */
6160 UNUSED(htim);
6161
6162 /* NOTE : This function should not be modified, when the callback is needed,
6163 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
6164 */
6165 }
6166
6167 /**
6168 * @brief Input Capture half complete callback in non-blocking mode
6169 * @param htim TIM IC handle
6170 * @retval None
6171 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)6172 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
6173 {
6174 /* Prevent unused argument(s) compilation warning */
6175 UNUSED(htim);
6176
6177 /* NOTE : This function should not be modified, when the callback is needed,
6178 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
6179 */
6180 }
6181
6182 /**
6183 * @brief PWM Pulse finished callback in non-blocking mode
6184 * @param htim TIM handle
6185 * @retval None
6186 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)6187 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
6188 {
6189 /* Prevent unused argument(s) compilation warning */
6190 UNUSED(htim);
6191
6192 /* NOTE : This function should not be modified, when the callback is needed,
6193 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
6194 */
6195 }
6196
6197 /**
6198 * @brief PWM Pulse finished half complete callback in non-blocking mode
6199 * @param htim TIM handle
6200 * @retval None
6201 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)6202 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
6203 {
6204 /* Prevent unused argument(s) compilation warning */
6205 UNUSED(htim);
6206
6207 /* NOTE : This function should not be modified, when the callback is needed,
6208 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
6209 */
6210 }
6211
6212 /**
6213 * @brief Hall Trigger detection callback in non-blocking mode
6214 * @param htim TIM handle
6215 * @retval None
6216 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)6217 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
6218 {
6219 /* Prevent unused argument(s) compilation warning */
6220 UNUSED(htim);
6221
6222 /* NOTE : This function should not be modified, when the callback is needed,
6223 the HAL_TIM_TriggerCallback could be implemented in the user file
6224 */
6225 }
6226
6227 /**
6228 * @brief Hall Trigger detection half complete callback in non-blocking mode
6229 * @param htim TIM handle
6230 * @retval None
6231 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)6232 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
6233 {
6234 /* Prevent unused argument(s) compilation warning */
6235 UNUSED(htim);
6236
6237 /* NOTE : This function should not be modified, when the callback is needed,
6238 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
6239 */
6240 }
6241
6242 /**
6243 * @brief Timer error callback in non-blocking mode
6244 * @param htim TIM handle
6245 * @retval None
6246 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)6247 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
6248 {
6249 /* Prevent unused argument(s) compilation warning */
6250 UNUSED(htim);
6251
6252 /* NOTE : This function should not be modified, when the callback is needed,
6253 the HAL_TIM_ErrorCallback could be implemented in the user file
6254 */
6255 }
6256
6257 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6258 /**
6259 * @brief Register a User TIM callback to be used instead of the weak predefined callback
6260 * @param htim tim handle
6261 * @param CallbackID ID of the callback to be registered
6262 * This parameter can be one of the following values:
6263 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6264 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6265 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6266 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6267 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6268 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6269 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6270 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6271 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6272 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6273 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6274 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6275 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6276 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6277 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6278 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6279 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6280 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6281 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6282 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6283 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6284 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6285 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6286 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6287 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6288 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6289 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6290 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6291 * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
6292 * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
6293 * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
6294 * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
6295 * @param pCallback pointer to the callback function
6296 * @retval status
6297 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)6298 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
6299 pTIM_CallbackTypeDef pCallback)
6300 {
6301 HAL_StatusTypeDef status = HAL_OK;
6302
6303 if (pCallback == NULL)
6304 {
6305 return HAL_ERROR;
6306 }
6307
6308 if (htim->State == HAL_TIM_STATE_READY)
6309 {
6310 switch (CallbackID)
6311 {
6312 case HAL_TIM_BASE_MSPINIT_CB_ID :
6313 htim->Base_MspInitCallback = pCallback;
6314 break;
6315
6316 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6317 htim->Base_MspDeInitCallback = pCallback;
6318 break;
6319
6320 case HAL_TIM_IC_MSPINIT_CB_ID :
6321 htim->IC_MspInitCallback = pCallback;
6322 break;
6323
6324 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6325 htim->IC_MspDeInitCallback = pCallback;
6326 break;
6327
6328 case HAL_TIM_OC_MSPINIT_CB_ID :
6329 htim->OC_MspInitCallback = pCallback;
6330 break;
6331
6332 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6333 htim->OC_MspDeInitCallback = pCallback;
6334 break;
6335
6336 case HAL_TIM_PWM_MSPINIT_CB_ID :
6337 htim->PWM_MspInitCallback = pCallback;
6338 break;
6339
6340 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6341 htim->PWM_MspDeInitCallback = pCallback;
6342 break;
6343
6344 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6345 htim->OnePulse_MspInitCallback = pCallback;
6346 break;
6347
6348 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6349 htim->OnePulse_MspDeInitCallback = pCallback;
6350 break;
6351
6352 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6353 htim->Encoder_MspInitCallback = pCallback;
6354 break;
6355
6356 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6357 htim->Encoder_MspDeInitCallback = pCallback;
6358 break;
6359
6360 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6361 htim->HallSensor_MspInitCallback = pCallback;
6362 break;
6363
6364 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6365 htim->HallSensor_MspDeInitCallback = pCallback;
6366 break;
6367
6368 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6369 htim->PeriodElapsedCallback = pCallback;
6370 break;
6371
6372 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6373 htim->PeriodElapsedHalfCpltCallback = pCallback;
6374 break;
6375
6376 case HAL_TIM_TRIGGER_CB_ID :
6377 htim->TriggerCallback = pCallback;
6378 break;
6379
6380 case HAL_TIM_TRIGGER_HALF_CB_ID :
6381 htim->TriggerHalfCpltCallback = pCallback;
6382 break;
6383
6384 case HAL_TIM_IC_CAPTURE_CB_ID :
6385 htim->IC_CaptureCallback = pCallback;
6386 break;
6387
6388 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6389 htim->IC_CaptureHalfCpltCallback = pCallback;
6390 break;
6391
6392 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6393 htim->OC_DelayElapsedCallback = pCallback;
6394 break;
6395
6396 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6397 htim->PWM_PulseFinishedCallback = pCallback;
6398 break;
6399
6400 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6401 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
6402 break;
6403
6404 case HAL_TIM_ERROR_CB_ID :
6405 htim->ErrorCallback = pCallback;
6406 break;
6407
6408 case HAL_TIM_COMMUTATION_CB_ID :
6409 htim->CommutationCallback = pCallback;
6410 break;
6411
6412 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6413 htim->CommutationHalfCpltCallback = pCallback;
6414 break;
6415
6416 case HAL_TIM_BREAK_CB_ID :
6417 htim->BreakCallback = pCallback;
6418 break;
6419
6420 case HAL_TIM_BREAK2_CB_ID :
6421 htim->Break2Callback = pCallback;
6422 break;
6423
6424 case HAL_TIM_ENCODER_INDEX_CB_ID :
6425 htim->EncoderIndexCallback = pCallback;
6426 break;
6427
6428 case HAL_TIM_DIRECTION_CHANGE_CB_ID :
6429 htim->DirectionChangeCallback = pCallback;
6430 break;
6431
6432 case HAL_TIM_INDEX_ERROR_CB_ID :
6433 htim->IndexErrorCallback = pCallback;
6434 break;
6435
6436 case HAL_TIM_TRANSITION_ERROR_CB_ID :
6437 htim->TransitionErrorCallback = pCallback;
6438 break;
6439
6440 default :
6441 /* Return error status */
6442 status = HAL_ERROR;
6443 break;
6444 }
6445 }
6446 else if (htim->State == HAL_TIM_STATE_RESET)
6447 {
6448 switch (CallbackID)
6449 {
6450 case HAL_TIM_BASE_MSPINIT_CB_ID :
6451 htim->Base_MspInitCallback = pCallback;
6452 break;
6453
6454 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6455 htim->Base_MspDeInitCallback = pCallback;
6456 break;
6457
6458 case HAL_TIM_IC_MSPINIT_CB_ID :
6459 htim->IC_MspInitCallback = pCallback;
6460 break;
6461
6462 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6463 htim->IC_MspDeInitCallback = pCallback;
6464 break;
6465
6466 case HAL_TIM_OC_MSPINIT_CB_ID :
6467 htim->OC_MspInitCallback = pCallback;
6468 break;
6469
6470 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6471 htim->OC_MspDeInitCallback = pCallback;
6472 break;
6473
6474 case HAL_TIM_PWM_MSPINIT_CB_ID :
6475 htim->PWM_MspInitCallback = pCallback;
6476 break;
6477
6478 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6479 htim->PWM_MspDeInitCallback = pCallback;
6480 break;
6481
6482 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6483 htim->OnePulse_MspInitCallback = pCallback;
6484 break;
6485
6486 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6487 htim->OnePulse_MspDeInitCallback = pCallback;
6488 break;
6489
6490 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6491 htim->Encoder_MspInitCallback = pCallback;
6492 break;
6493
6494 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6495 htim->Encoder_MspDeInitCallback = pCallback;
6496 break;
6497
6498 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6499 htim->HallSensor_MspInitCallback = pCallback;
6500 break;
6501
6502 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6503 htim->HallSensor_MspDeInitCallback = pCallback;
6504 break;
6505
6506 default :
6507 /* Return error status */
6508 status = HAL_ERROR;
6509 break;
6510 }
6511 }
6512 else
6513 {
6514 /* Return error status */
6515 status = HAL_ERROR;
6516 }
6517
6518 return status;
6519 }
6520
6521 /**
6522 * @brief Unregister a TIM callback
6523 * TIM callback is redirected to the weak predefined callback
6524 * @param htim tim handle
6525 * @param CallbackID ID of the callback to be unregistered
6526 * This parameter can be one of the following values:
6527 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6528 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6529 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6530 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6531 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6532 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6533 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6534 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6535 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6536 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6537 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6538 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6539 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6540 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6541 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6542 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6543 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6544 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6545 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6546 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6547 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6548 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6549 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6550 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6551 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6552 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6553 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6554 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6555 * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
6556 * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
6557 * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
6558 * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
6559 * @retval status
6560 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6561 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6562 {
6563 HAL_StatusTypeDef status = HAL_OK;
6564
6565 if (htim->State == HAL_TIM_STATE_READY)
6566 {
6567 switch (CallbackID)
6568 {
6569 case HAL_TIM_BASE_MSPINIT_CB_ID :
6570 /* Legacy weak Base MspInit Callback */
6571 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6572 break;
6573
6574 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6575 /* Legacy weak Base Msp DeInit Callback */
6576 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6577 break;
6578
6579 case HAL_TIM_IC_MSPINIT_CB_ID :
6580 /* Legacy weak IC Msp Init Callback */
6581 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6582 break;
6583
6584 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6585 /* Legacy weak IC Msp DeInit Callback */
6586 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6587 break;
6588
6589 case HAL_TIM_OC_MSPINIT_CB_ID :
6590 /* Legacy weak OC Msp Init Callback */
6591 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6592 break;
6593
6594 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6595 /* Legacy weak OC Msp DeInit Callback */
6596 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6597 break;
6598
6599 case HAL_TIM_PWM_MSPINIT_CB_ID :
6600 /* Legacy weak PWM Msp Init Callback */
6601 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6602 break;
6603
6604 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6605 /* Legacy weak PWM Msp DeInit Callback */
6606 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6607 break;
6608
6609 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6610 /* Legacy weak One Pulse Msp Init Callback */
6611 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6612 break;
6613
6614 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6615 /* Legacy weak One Pulse Msp DeInit Callback */
6616 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6617 break;
6618
6619 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6620 /* Legacy weak Encoder Msp Init Callback */
6621 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6622 break;
6623
6624 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6625 /* Legacy weak Encoder Msp DeInit Callback */
6626 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6627 break;
6628
6629 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6630 /* Legacy weak Hall Sensor Msp Init Callback */
6631 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6632 break;
6633
6634 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6635 /* Legacy weak Hall Sensor Msp DeInit Callback */
6636 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6637 break;
6638
6639 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6640 /* Legacy weak Period Elapsed Callback */
6641 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
6642 break;
6643
6644 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6645 /* Legacy weak Period Elapsed half complete Callback */
6646 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
6647 break;
6648
6649 case HAL_TIM_TRIGGER_CB_ID :
6650 /* Legacy weak Trigger Callback */
6651 htim->TriggerCallback = HAL_TIM_TriggerCallback;
6652 break;
6653
6654 case HAL_TIM_TRIGGER_HALF_CB_ID :
6655 /* Legacy weak Trigger half complete Callback */
6656 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
6657 break;
6658
6659 case HAL_TIM_IC_CAPTURE_CB_ID :
6660 /* Legacy weak IC Capture Callback */
6661 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
6662 break;
6663
6664 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6665 /* Legacy weak IC Capture half complete Callback */
6666 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
6667 break;
6668
6669 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6670 /* Legacy weak OC Delay Elapsed Callback */
6671 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
6672 break;
6673
6674 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6675 /* Legacy weak PWM Pulse Finished Callback */
6676 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
6677 break;
6678
6679 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6680 /* Legacy weak PWM Pulse Finished half complete Callback */
6681 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
6682 break;
6683
6684 case HAL_TIM_ERROR_CB_ID :
6685 /* Legacy weak Error Callback */
6686 htim->ErrorCallback = HAL_TIM_ErrorCallback;
6687 break;
6688
6689 case HAL_TIM_COMMUTATION_CB_ID :
6690 /* Legacy weak Commutation Callback */
6691 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
6692 break;
6693
6694 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6695 /* Legacy weak Commutation half complete Callback */
6696 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
6697 break;
6698
6699 case HAL_TIM_BREAK_CB_ID :
6700 /* Legacy weak Break Callback */
6701 htim->BreakCallback = HAL_TIMEx_BreakCallback;
6702 break;
6703
6704 case HAL_TIM_BREAK2_CB_ID :
6705 /* Legacy weak Break2 Callback */
6706 htim->Break2Callback = HAL_TIMEx_Break2Callback;
6707 break;
6708
6709 case HAL_TIM_ENCODER_INDEX_CB_ID :
6710 /* Legacy weak Encoder Index Callback */
6711 htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback;
6712 break;
6713
6714 case HAL_TIM_DIRECTION_CHANGE_CB_ID :
6715 /* Legacy weak Direction Change Callback */
6716 htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback;
6717 break;
6718
6719 case HAL_TIM_INDEX_ERROR_CB_ID :
6720 /* Legacy weak Index Error Callback */
6721 htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback;
6722 break;
6723
6724 case HAL_TIM_TRANSITION_ERROR_CB_ID :
6725 /* Legacy weak Transition Error Callback */
6726 htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback;
6727 break;
6728
6729 default :
6730 /* Return error status */
6731 status = HAL_ERROR;
6732 break;
6733 }
6734 }
6735 else if (htim->State == HAL_TIM_STATE_RESET)
6736 {
6737 switch (CallbackID)
6738 {
6739 case HAL_TIM_BASE_MSPINIT_CB_ID :
6740 /* Legacy weak Base MspInit Callback */
6741 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
6742 break;
6743
6744 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6745 /* Legacy weak Base Msp DeInit Callback */
6746 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
6747 break;
6748
6749 case HAL_TIM_IC_MSPINIT_CB_ID :
6750 /* Legacy weak IC Msp Init Callback */
6751 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
6752 break;
6753
6754 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6755 /* Legacy weak IC Msp DeInit Callback */
6756 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
6757 break;
6758
6759 case HAL_TIM_OC_MSPINIT_CB_ID :
6760 /* Legacy weak OC Msp Init Callback */
6761 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
6762 break;
6763
6764 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6765 /* Legacy weak OC Msp DeInit Callback */
6766 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
6767 break;
6768
6769 case HAL_TIM_PWM_MSPINIT_CB_ID :
6770 /* Legacy weak PWM Msp Init Callback */
6771 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
6772 break;
6773
6774 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6775 /* Legacy weak PWM Msp DeInit Callback */
6776 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
6777 break;
6778
6779 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6780 /* Legacy weak One Pulse Msp Init Callback */
6781 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
6782 break;
6783
6784 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6785 /* Legacy weak One Pulse Msp DeInit Callback */
6786 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
6787 break;
6788
6789 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6790 /* Legacy weak Encoder Msp Init Callback */
6791 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
6792 break;
6793
6794 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6795 /* Legacy weak Encoder Msp DeInit Callback */
6796 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
6797 break;
6798
6799 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6800 /* Legacy weak Hall Sensor Msp Init Callback */
6801 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
6802 break;
6803
6804 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6805 /* Legacy weak Hall Sensor Msp DeInit Callback */
6806 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
6807 break;
6808
6809 default :
6810 /* Return error status */
6811 status = HAL_ERROR;
6812 break;
6813 }
6814 }
6815 else
6816 {
6817 /* Return error status */
6818 status = HAL_ERROR;
6819 }
6820
6821 return status;
6822 }
6823 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6824
6825 /**
6826 * @}
6827 */
6828
6829 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6830 * @brief TIM Peripheral State functions
6831 *
6832 @verbatim
6833 ==============================================================================
6834 ##### Peripheral State functions #####
6835 ==============================================================================
6836 [..]
6837 This subsection permits to get in run-time the status of the peripheral
6838 and the data flow.
6839
6840 @endverbatim
6841 * @{
6842 */
6843
6844 /**
6845 * @brief Return the TIM Base handle state.
6846 * @param htim TIM Base handle
6847 * @retval HAL state
6848 */
HAL_TIM_Base_GetState(const TIM_HandleTypeDef * htim)6849 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
6850 {
6851 return htim->State;
6852 }
6853
6854 /**
6855 * @brief Return the TIM OC handle state.
6856 * @param htim TIM Output Compare handle
6857 * @retval HAL state
6858 */
HAL_TIM_OC_GetState(const TIM_HandleTypeDef * htim)6859 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
6860 {
6861 return htim->State;
6862 }
6863
6864 /**
6865 * @brief Return the TIM PWM handle state.
6866 * @param htim TIM handle
6867 * @retval HAL state
6868 */
HAL_TIM_PWM_GetState(const TIM_HandleTypeDef * htim)6869 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
6870 {
6871 return htim->State;
6872 }
6873
6874 /**
6875 * @brief Return the TIM Input Capture handle state.
6876 * @param htim TIM IC handle
6877 * @retval HAL state
6878 */
HAL_TIM_IC_GetState(const TIM_HandleTypeDef * htim)6879 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
6880 {
6881 return htim->State;
6882 }
6883
6884 /**
6885 * @brief Return the TIM One Pulse Mode handle state.
6886 * @param htim TIM OPM handle
6887 * @retval HAL state
6888 */
HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef * htim)6889 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
6890 {
6891 return htim->State;
6892 }
6893
6894 /**
6895 * @brief Return the TIM Encoder Mode handle state.
6896 * @param htim TIM Encoder Interface handle
6897 * @retval HAL state
6898 */
HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef * htim)6899 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
6900 {
6901 return htim->State;
6902 }
6903
6904 /**
6905 * @brief Return the TIM Encoder Mode handle state.
6906 * @param htim TIM handle
6907 * @retval Active channel
6908 */
HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef * htim)6909 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
6910 {
6911 return htim->Channel;
6912 }
6913
6914 /**
6915 * @brief Return actual state of the TIM channel.
6916 * @param htim TIM handle
6917 * @param Channel TIM Channel
6918 * This parameter can be one of the following values:
6919 * @arg TIM_CHANNEL_1: TIM Channel 1
6920 * @arg TIM_CHANNEL_2: TIM Channel 2
6921 * @arg TIM_CHANNEL_3: TIM Channel 3
6922 * @arg TIM_CHANNEL_4: TIM Channel 4
6923 * @arg TIM_CHANNEL_5: TIM Channel 5
6924 * @arg TIM_CHANNEL_6: TIM Channel 6
6925 * @retval TIM Channel state
6926 */
HAL_TIM_GetChannelState(const TIM_HandleTypeDef * htim,uint32_t Channel)6927 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel)
6928 {
6929 HAL_TIM_ChannelStateTypeDef channel_state;
6930
6931 /* Check the parameters */
6932 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6933
6934 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6935
6936 return channel_state;
6937 }
6938
6939 /**
6940 * @brief Return actual state of a DMA burst operation.
6941 * @param htim TIM handle
6942 * @retval DMA burst state
6943 */
HAL_TIM_DMABurstState(const TIM_HandleTypeDef * htim)6944 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
6945 {
6946 /* Check the parameters */
6947 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6948
6949 return htim->DMABurstState;
6950 }
6951
6952 /**
6953 * @}
6954 */
6955
6956 /**
6957 * @}
6958 */
6959
6960 /** @defgroup TIM_Private_Functions TIM Private Functions
6961 * @{
6962 */
6963
6964 /**
6965 * @brief TIM DMA error callback
6966 * @param hdma pointer to DMA handle.
6967 * @retval None
6968 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6969 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6970 {
6971 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6972
6973 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6974 {
6975 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6976 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6977 }
6978 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6979 {
6980 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6981 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6982 }
6983 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6984 {
6985 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6986 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6987 }
6988 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6989 {
6990 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6991 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6992 }
6993 else
6994 {
6995 htim->State = HAL_TIM_STATE_READY;
6996 }
6997
6998 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6999 htim->ErrorCallback(htim);
7000 #else
7001 HAL_TIM_ErrorCallback(htim);
7002 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7003
7004 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7005 }
7006
7007 /**
7008 * @brief TIM DMA Delay Pulse complete callback.
7009 * @param hdma pointer to DMA handle.
7010 * @retval None
7011 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)7012 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
7013 {
7014 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7015
7016 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7017 {
7018 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7019 }
7020 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7021 {
7022 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7023 }
7024 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7025 {
7026 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7027 }
7028 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7029 {
7030 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7031 }
7032 else
7033 {
7034 /* nothing to do */
7035 }
7036
7037 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7038 htim->PWM_PulseFinishedCallback(htim);
7039 #else
7040 HAL_TIM_PWM_PulseFinishedCallback(htim);
7041 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7042
7043 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7044 }
7045
7046 /**
7047 * @brief TIM DMA Delay Pulse half complete callback.
7048 * @param hdma pointer to DMA handle.
7049 * @retval None
7050 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)7051 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
7052 {
7053 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7054
7055 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7056 {
7057 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7058 }
7059 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7060 {
7061 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7062 }
7063 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7064 {
7065 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7066 }
7067 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7068 {
7069 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7070 }
7071 else
7072 {
7073 /* nothing to do */
7074 }
7075
7076 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7077 htim->PWM_PulseFinishedHalfCpltCallback(htim);
7078 #else
7079 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
7080 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7081
7082 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7083 }
7084
7085 /**
7086 * @brief TIM DMA Capture complete callback.
7087 * @param hdma pointer to DMA handle.
7088 * @retval None
7089 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)7090 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
7091 {
7092 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7093
7094 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7095 {
7096 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7097 }
7098 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7099 {
7100 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7101 }
7102 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7103 {
7104 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7105 }
7106 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7107 {
7108 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7109 }
7110 else
7111 {
7112 /* nothing to do */
7113 }
7114
7115 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7116 htim->IC_CaptureCallback(htim);
7117 #else
7118 HAL_TIM_IC_CaptureCallback(htim);
7119 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7120
7121 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7122 }
7123
7124 /**
7125 * @brief TIM DMA Capture half complete callback.
7126 * @param hdma pointer to DMA handle.
7127 * @retval None
7128 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)7129 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
7130 {
7131 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7132
7133 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
7134 {
7135 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
7136 }
7137 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
7138 {
7139 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
7140 }
7141 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
7142 {
7143 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
7144 }
7145 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
7146 {
7147 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
7148 }
7149 else
7150 {
7151 /* nothing to do */
7152 }
7153
7154 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7155 htim->IC_CaptureHalfCpltCallback(htim);
7156 #else
7157 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
7158 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7159
7160 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
7161 }
7162
7163 /**
7164 * @brief TIM DMA Period Elapse complete callback.
7165 * @param hdma pointer to DMA handle.
7166 * @retval None
7167 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)7168 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
7169 {
7170 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7171
7172 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7173 htim->PeriodElapsedCallback(htim);
7174 #else
7175 HAL_TIM_PeriodElapsedCallback(htim);
7176 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7177 }
7178
7179 /**
7180 * @brief TIM DMA Period Elapse half complete callback.
7181 * @param hdma pointer to DMA handle.
7182 * @retval None
7183 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)7184 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
7185 {
7186 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7187
7188 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7189 htim->PeriodElapsedHalfCpltCallback(htim);
7190 #else
7191 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
7192 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7193 }
7194
7195 /**
7196 * @brief TIM DMA Trigger callback.
7197 * @param hdma pointer to DMA handle.
7198 * @retval None
7199 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)7200 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
7201 {
7202 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7203
7204 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7205 htim->TriggerCallback(htim);
7206 #else
7207 HAL_TIM_TriggerCallback(htim);
7208 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7209 }
7210
7211 /**
7212 * @brief TIM DMA Trigger half complete callback.
7213 * @param hdma pointer to DMA handle.
7214 * @retval None
7215 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)7216 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
7217 {
7218 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
7219
7220 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7221 htim->TriggerHalfCpltCallback(htim);
7222 #else
7223 HAL_TIM_TriggerHalfCpltCallback(htim);
7224 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7225 }
7226
7227 /**
7228 * @brief Time Base configuration
7229 * @param TIMx TIM peripheral
7230 * @param Structure TIM Base configuration structure
7231 * @retval None
7232 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,const TIM_Base_InitTypeDef * Structure)7233 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
7234 {
7235 uint32_t tmpcr1;
7236 tmpcr1 = TIMx->CR1;
7237
7238 /* Set TIM Time Base Unit parameters ---------------------------------------*/
7239 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
7240 {
7241 /* Select the Counter Mode */
7242 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
7243 tmpcr1 |= Structure->CounterMode;
7244 }
7245
7246 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
7247 {
7248 /* Set the clock division */
7249 tmpcr1 &= ~TIM_CR1_CKD;
7250 tmpcr1 |= (uint32_t)Structure->ClockDivision;
7251 }
7252
7253 /* Set the auto-reload preload */
7254 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
7255
7256 TIMx->CR1 = tmpcr1;
7257
7258 /* Set the Autoreload value */
7259 TIMx->ARR = (uint32_t)Structure->Period ;
7260
7261 /* Set the Prescaler value */
7262 TIMx->PSC = Structure->Prescaler;
7263
7264 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
7265 {
7266 /* Set the Repetition Counter value */
7267 TIMx->RCR = Structure->RepetitionCounter;
7268 }
7269
7270 /* Generate an update event to reload the Prescaler
7271 and the repetition counter (only for advanced timer) value immediately */
7272 TIMx->EGR = TIM_EGR_UG;
7273
7274 /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
7275 if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
7276 {
7277 /* Clear the update flag */
7278 CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
7279 }
7280 }
7281
7282 /**
7283 * @brief Timer Output Compare 1 configuration
7284 * @param TIMx to select the TIM peripheral
7285 * @param OC_Config The output configuration structure
7286 * @retval None
7287 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7288 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7289 {
7290 uint32_t tmpccmrx;
7291 uint32_t tmpccer;
7292 uint32_t tmpcr2;
7293
7294 /* Get the TIMx CCER register value */
7295 tmpccer = TIMx->CCER;
7296
7297 /* Disable the Channel 1: Reset the CC1E Bit */
7298 TIMx->CCER &= ~TIM_CCER_CC1E;
7299
7300 /* Get the TIMx CR2 register value */
7301 tmpcr2 = TIMx->CR2;
7302
7303 /* Get the TIMx CCMR1 register value */
7304 tmpccmrx = TIMx->CCMR1;
7305
7306 /* Reset the Output Compare Mode Bits */
7307 tmpccmrx &= ~TIM_CCMR1_OC1M;
7308 tmpccmrx &= ~TIM_CCMR1_CC1S;
7309 /* Select the Output Compare Mode */
7310 tmpccmrx |= OC_Config->OCMode;
7311
7312 /* Reset the Output Polarity level */
7313 tmpccer &= ~TIM_CCER_CC1P;
7314 /* Set the Output Compare Polarity */
7315 tmpccer |= OC_Config->OCPolarity;
7316
7317 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
7318 {
7319 /* Check parameters */
7320 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7321
7322 /* Reset the Output N Polarity level */
7323 tmpccer &= ~TIM_CCER_CC1NP;
7324 /* Set the Output N Polarity */
7325 tmpccer |= OC_Config->OCNPolarity;
7326 /* Reset the Output N State */
7327 tmpccer &= ~TIM_CCER_CC1NE;
7328 }
7329
7330 if (IS_TIM_BREAK_INSTANCE(TIMx))
7331 {
7332 /* Check parameters */
7333 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7334 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7335
7336 /* Reset the Output Compare and Output Compare N IDLE State */
7337 tmpcr2 &= ~TIM_CR2_OIS1;
7338 tmpcr2 &= ~TIM_CR2_OIS1N;
7339 /* Set the Output Idle state */
7340 tmpcr2 |= OC_Config->OCIdleState;
7341 /* Set the Output N Idle state */
7342 tmpcr2 |= OC_Config->OCNIdleState;
7343 }
7344
7345 /* Write to TIMx CR2 */
7346 TIMx->CR2 = tmpcr2;
7347
7348 /* Write to TIMx CCMR1 */
7349 TIMx->CCMR1 = tmpccmrx;
7350
7351 /* Set the Capture Compare Register value */
7352 TIMx->CCR1 = OC_Config->Pulse;
7353
7354 /* Write to TIMx CCER */
7355 TIMx->CCER = tmpccer;
7356 }
7357
7358 /**
7359 * @brief Timer Output Compare 2 configuration
7360 * @param TIMx to select the TIM peripheral
7361 * @param OC_Config The output configuration structure
7362 * @retval None
7363 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7364 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7365 {
7366 uint32_t tmpccmrx;
7367 uint32_t tmpccer;
7368 uint32_t tmpcr2;
7369
7370 /* Get the TIMx CCER register value */
7371 tmpccer = TIMx->CCER;
7372
7373 /* Disable the Channel 2: Reset the CC2E Bit */
7374 TIMx->CCER &= ~TIM_CCER_CC2E;
7375
7376 /* Get the TIMx CR2 register value */
7377 tmpcr2 = TIMx->CR2;
7378
7379 /* Get the TIMx CCMR1 register value */
7380 tmpccmrx = TIMx->CCMR1;
7381
7382 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7383 tmpccmrx &= ~TIM_CCMR1_OC2M;
7384 tmpccmrx &= ~TIM_CCMR1_CC2S;
7385
7386 /* Select the Output Compare Mode */
7387 tmpccmrx |= (OC_Config->OCMode << 8U);
7388
7389 /* Reset the Output Polarity level */
7390 tmpccer &= ~TIM_CCER_CC2P;
7391 /* Set the Output Compare Polarity */
7392 tmpccer |= (OC_Config->OCPolarity << 4U);
7393
7394 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
7395 {
7396 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7397
7398 /* Reset the Output N Polarity level */
7399 tmpccer &= ~TIM_CCER_CC2NP;
7400 /* Set the Output N Polarity */
7401 tmpccer |= (OC_Config->OCNPolarity << 4U);
7402 /* Reset the Output N State */
7403 tmpccer &= ~TIM_CCER_CC2NE;
7404 }
7405
7406 if (IS_TIM_BREAK_INSTANCE(TIMx))
7407 {
7408 /* Check parameters */
7409 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7410 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7411
7412 /* Reset the Output Compare and Output Compare N IDLE State */
7413 tmpcr2 &= ~TIM_CR2_OIS2;
7414 tmpcr2 &= ~TIM_CR2_OIS2N;
7415 /* Set the Output Idle state */
7416 tmpcr2 |= (OC_Config->OCIdleState << 2U);
7417 /* Set the Output N Idle state */
7418 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
7419 }
7420
7421 /* Write to TIMx CR2 */
7422 TIMx->CR2 = tmpcr2;
7423
7424 /* Write to TIMx CCMR1 */
7425 TIMx->CCMR1 = tmpccmrx;
7426
7427 /* Set the Capture Compare Register value */
7428 TIMx->CCR2 = OC_Config->Pulse;
7429
7430 /* Write to TIMx CCER */
7431 TIMx->CCER = tmpccer;
7432 }
7433
7434 /**
7435 * @brief Timer Output Compare 3 configuration
7436 * @param TIMx to select the TIM peripheral
7437 * @param OC_Config The output configuration structure
7438 * @retval None
7439 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7440 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7441 {
7442 uint32_t tmpccmrx;
7443 uint32_t tmpccer;
7444 uint32_t tmpcr2;
7445
7446 /* Get the TIMx CCER register value */
7447 tmpccer = TIMx->CCER;
7448
7449 /* Disable the Channel 3: Reset the CC2E Bit */
7450 TIMx->CCER &= ~TIM_CCER_CC3E;
7451
7452 /* Get the TIMx CR2 register value */
7453 tmpcr2 = TIMx->CR2;
7454
7455 /* Get the TIMx CCMR2 register value */
7456 tmpccmrx = TIMx->CCMR2;
7457
7458 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7459 tmpccmrx &= ~TIM_CCMR2_OC3M;
7460 tmpccmrx &= ~TIM_CCMR2_CC3S;
7461 /* Select the Output Compare Mode */
7462 tmpccmrx |= OC_Config->OCMode;
7463
7464 /* Reset the Output Polarity level */
7465 tmpccer &= ~TIM_CCER_CC3P;
7466 /* Set the Output Compare Polarity */
7467 tmpccer |= (OC_Config->OCPolarity << 8U);
7468
7469 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7470 {
7471 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7472
7473 /* Reset the Output N Polarity level */
7474 tmpccer &= ~TIM_CCER_CC3NP;
7475 /* Set the Output N Polarity */
7476 tmpccer |= (OC_Config->OCNPolarity << 8U);
7477 /* Reset the Output N State */
7478 tmpccer &= ~TIM_CCER_CC3NE;
7479 }
7480
7481 if (IS_TIM_BREAK_INSTANCE(TIMx))
7482 {
7483 /* Check parameters */
7484 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7485 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7486
7487 /* Reset the Output Compare and Output Compare N IDLE State */
7488 tmpcr2 &= ~TIM_CR2_OIS3;
7489 tmpcr2 &= ~TIM_CR2_OIS3N;
7490 /* Set the Output Idle state */
7491 tmpcr2 |= (OC_Config->OCIdleState << 4U);
7492 /* Set the Output N Idle state */
7493 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7494 }
7495
7496 /* Write to TIMx CR2 */
7497 TIMx->CR2 = tmpcr2;
7498
7499 /* Write to TIMx CCMR2 */
7500 TIMx->CCMR2 = tmpccmrx;
7501
7502 /* Set the Capture Compare Register value */
7503 TIMx->CCR3 = OC_Config->Pulse;
7504
7505 /* Write to TIMx CCER */
7506 TIMx->CCER = tmpccer;
7507 }
7508
7509 /**
7510 * @brief Timer Output Compare 4 configuration
7511 * @param TIMx to select the TIM peripheral
7512 * @param OC_Config The output configuration structure
7513 * @retval None
7514 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7515 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
7516 {
7517 uint32_t tmpccmrx;
7518 uint32_t tmpccer;
7519 uint32_t tmpcr2;
7520
7521 /* Get the TIMx CCER register value */
7522 tmpccer = TIMx->CCER;
7523
7524 /* Disable the Channel 4: Reset the CC4E Bit */
7525 TIMx->CCER &= ~TIM_CCER_CC4E;
7526
7527 /* Get the TIMx CR2 register value */
7528 tmpcr2 = TIMx->CR2;
7529
7530 /* Get the TIMx CCMR2 register value */
7531 tmpccmrx = TIMx->CCMR2;
7532
7533 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7534 tmpccmrx &= ~TIM_CCMR2_OC4M;
7535 tmpccmrx &= ~TIM_CCMR2_CC4S;
7536
7537 /* Select the Output Compare Mode */
7538 tmpccmrx |= (OC_Config->OCMode << 8U);
7539
7540 /* Reset the Output Polarity level */
7541 tmpccer &= ~TIM_CCER_CC4P;
7542 /* Set the Output Compare Polarity */
7543 tmpccer |= (OC_Config->OCPolarity << 12U);
7544
7545 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
7546 {
7547 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7548
7549 /* Reset the Output N Polarity level */
7550 tmpccer &= ~TIM_CCER_CC4NP;
7551 /* Set the Output N Polarity */
7552 tmpccer |= (OC_Config->OCNPolarity << 12U);
7553 /* Reset the Output N State */
7554 tmpccer &= ~TIM_CCER_CC4NE;
7555 }
7556
7557 if (IS_TIM_BREAK_INSTANCE(TIMx))
7558 {
7559 /* Check parameters */
7560 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7561 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7562
7563 /* Reset the Output Compare IDLE State */
7564 tmpcr2 &= ~TIM_CR2_OIS4;
7565 /* Reset the Output Compare N IDLE State */
7566 tmpcr2 &= ~TIM_CR2_OIS4N;
7567
7568 /* Set the Output Idle state */
7569 tmpcr2 |= (OC_Config->OCIdleState << 6U);
7570 /* Set the Output N Idle state */
7571 tmpcr2 |= (OC_Config->OCNIdleState << 6U);
7572 }
7573
7574 /* Write to TIMx CR2 */
7575 TIMx->CR2 = tmpcr2;
7576
7577 /* Write to TIMx CCMR2 */
7578 TIMx->CCMR2 = tmpccmrx;
7579
7580 /* Set the Capture Compare Register value */
7581 TIMx->CCR4 = OC_Config->Pulse;
7582
7583 /* Write to TIMx CCER */
7584 TIMx->CCER = tmpccer;
7585 }
7586
7587 /**
7588 * @brief Timer Output Compare 5 configuration
7589 * @param TIMx to select the TIM peripheral
7590 * @param OC_Config The output configuration structure
7591 * @retval None
7592 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7593 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
7594 const TIM_OC_InitTypeDef *OC_Config)
7595 {
7596 uint32_t tmpccmrx;
7597 uint32_t tmpccer;
7598 uint32_t tmpcr2;
7599
7600 /* Get the TIMx CCER register value */
7601 tmpccer = TIMx->CCER;
7602
7603 /* Disable the output: Reset the CCxE Bit */
7604 TIMx->CCER &= ~TIM_CCER_CC5E;
7605
7606 /* Get the TIMx CR2 register value */
7607 tmpcr2 = TIMx->CR2;
7608 /* Get the TIMx CCMR1 register value */
7609 tmpccmrx = TIMx->CCMR3;
7610
7611 /* Reset the Output Compare Mode Bits */
7612 tmpccmrx &= ~(TIM_CCMR3_OC5M);
7613 /* Select the Output Compare Mode */
7614 tmpccmrx |= OC_Config->OCMode;
7615
7616 /* Reset the Output Polarity level */
7617 tmpccer &= ~TIM_CCER_CC5P;
7618 /* Set the Output Compare Polarity */
7619 tmpccer |= (OC_Config->OCPolarity << 16U);
7620
7621 if (IS_TIM_BREAK_INSTANCE(TIMx))
7622 {
7623 /* Reset the Output Compare IDLE State */
7624 tmpcr2 &= ~TIM_CR2_OIS5;
7625 /* Set the Output Idle state */
7626 tmpcr2 |= (OC_Config->OCIdleState << 8U);
7627 }
7628 /* Write to TIMx CR2 */
7629 TIMx->CR2 = tmpcr2;
7630
7631 /* Write to TIMx CCMR3 */
7632 TIMx->CCMR3 = tmpccmrx;
7633
7634 /* Set the Capture Compare Register value */
7635 TIMx->CCR5 = OC_Config->Pulse;
7636
7637 /* Write to TIMx CCER */
7638 TIMx->CCER = tmpccer;
7639 }
7640
7641 /**
7642 * @brief Timer Output Compare 6 configuration
7643 * @param TIMx to select the TIM peripheral
7644 * @param OC_Config The output configuration structure
7645 * @retval None
7646 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,const TIM_OC_InitTypeDef * OC_Config)7647 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
7648 const TIM_OC_InitTypeDef *OC_Config)
7649 {
7650 uint32_t tmpccmrx;
7651 uint32_t tmpccer;
7652 uint32_t tmpcr2;
7653
7654 /* Get the TIMx CCER register value */
7655 tmpccer = TIMx->CCER;
7656
7657 /* Disable the output: Reset the CCxE Bit */
7658 TIMx->CCER &= ~TIM_CCER_CC6E;
7659
7660 /* Get the TIMx CR2 register value */
7661 tmpcr2 = TIMx->CR2;
7662 /* Get the TIMx CCMR1 register value */
7663 tmpccmrx = TIMx->CCMR3;
7664
7665 /* Reset the Output Compare Mode Bits */
7666 tmpccmrx &= ~(TIM_CCMR3_OC6M);
7667 /* Select the Output Compare Mode */
7668 tmpccmrx |= (OC_Config->OCMode << 8U);
7669
7670 /* Reset the Output Polarity level */
7671 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
7672 /* Set the Output Compare Polarity */
7673 tmpccer |= (OC_Config->OCPolarity << 20U);
7674
7675 if (IS_TIM_BREAK_INSTANCE(TIMx))
7676 {
7677 /* Reset the Output Compare IDLE State */
7678 tmpcr2 &= ~TIM_CR2_OIS6;
7679 /* Set the Output Idle state */
7680 tmpcr2 |= (OC_Config->OCIdleState << 10U);
7681 }
7682
7683 /* Write to TIMx CR2 */
7684 TIMx->CR2 = tmpcr2;
7685
7686 /* Write to TIMx CCMR3 */
7687 TIMx->CCMR3 = tmpccmrx;
7688
7689 /* Set the Capture Compare Register value */
7690 TIMx->CCR6 = OC_Config->Pulse;
7691
7692 /* Write to TIMx CCER */
7693 TIMx->CCER = tmpccer;
7694 }
7695
7696 /**
7697 * @brief Slave Timer configuration function
7698 * @param htim TIM handle
7699 * @param sSlaveConfig Slave timer configuration
7700 * @retval None
7701 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,const TIM_SlaveConfigTypeDef * sSlaveConfig)7702 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7703 const TIM_SlaveConfigTypeDef *sSlaveConfig)
7704 {
7705 HAL_StatusTypeDef status = HAL_OK;
7706 uint32_t tmpsmcr;
7707 uint32_t tmpccmr1;
7708 uint32_t tmpccer;
7709
7710 /* Get the TIMx SMCR register value */
7711 tmpsmcr = htim->Instance->SMCR;
7712
7713 /* Reset the Trigger Selection Bits */
7714 tmpsmcr &= ~TIM_SMCR_TS;
7715 /* Set the Input Trigger source */
7716 tmpsmcr |= sSlaveConfig->InputTrigger;
7717
7718 /* Reset the slave mode Bits */
7719 tmpsmcr &= ~TIM_SMCR_SMS;
7720 /* Set the slave mode */
7721 tmpsmcr |= sSlaveConfig->SlaveMode;
7722
7723 /* Write to TIMx SMCR */
7724 htim->Instance->SMCR = tmpsmcr;
7725
7726 /* Configure the trigger prescaler, filter, and polarity */
7727 switch (sSlaveConfig->InputTrigger)
7728 {
7729 case TIM_TS_ETRF:
7730 {
7731 /* Check the parameters */
7732 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7733 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7734 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7735 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7736 /* Configure the ETR Trigger source */
7737 TIM_ETR_SetConfig(htim->Instance,
7738 sSlaveConfig->TriggerPrescaler,
7739 sSlaveConfig->TriggerPolarity,
7740 sSlaveConfig->TriggerFilter);
7741 break;
7742 }
7743
7744 case TIM_TS_TI1F_ED:
7745 {
7746 /* Check the parameters */
7747 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7748 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7749
7750 if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \
7751 (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
7752 {
7753 return HAL_ERROR;
7754 }
7755
7756 /* Disable the Channel 1: Reset the CC1E Bit */
7757 tmpccer = htim->Instance->CCER;
7758 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7759 tmpccmr1 = htim->Instance->CCMR1;
7760
7761 /* Set the filter */
7762 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7763 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7764
7765 /* Write to TIMx CCMR1 and CCER registers */
7766 htim->Instance->CCMR1 = tmpccmr1;
7767 htim->Instance->CCER = tmpccer;
7768 break;
7769 }
7770
7771 case TIM_TS_TI1FP1:
7772 {
7773 /* Check the parameters */
7774 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7775 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7776 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7777
7778 /* Configure TI1 Filter and Polarity */
7779 TIM_TI1_ConfigInputStage(htim->Instance,
7780 sSlaveConfig->TriggerPolarity,
7781 sSlaveConfig->TriggerFilter);
7782 break;
7783 }
7784
7785 case TIM_TS_TI2FP2:
7786 {
7787 /* Check the parameters */
7788 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7789 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7790 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7791
7792 /* Configure TI2 Filter and Polarity */
7793 TIM_TI2_ConfigInputStage(htim->Instance,
7794 sSlaveConfig->TriggerPolarity,
7795 sSlaveConfig->TriggerFilter);
7796 break;
7797 }
7798
7799 case TIM_TS_ITR0:
7800 case TIM_TS_ITR1:
7801 case TIM_TS_ITR2:
7802 case TIM_TS_ITR3:
7803 case TIM_TS_ITR4:
7804 case TIM_TS_ITR5:
7805 case TIM_TS_ITR6:
7806 case TIM_TS_ITR7:
7807 case TIM_TS_ITR8:
7808 case TIM_TS_ITR9:
7809 case TIM_TS_ITR10:
7810 case TIM_TS_ITR11:
7811 case TIM_TS_ITR13:
7812 case TIM_TS_ITR14:
7813 {
7814 /* Check the parameter */
7815 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger));
7816 break;
7817 }
7818
7819 default:
7820 status = HAL_ERROR;
7821 break;
7822 }
7823
7824 return status;
7825 }
7826
7827 /**
7828 * @brief Configure the TI1 as Input.
7829 * @param TIMx to select the TIM peripheral.
7830 * @param TIM_ICPolarity The Input Polarity.
7831 * This parameter can be one of the following values:
7832 * @arg TIM_ICPOLARITY_RISING
7833 * @arg TIM_ICPOLARITY_FALLING
7834 * @arg TIM_ICPOLARITY_BOTHEDGE
7835 * @param TIM_ICSelection specifies the input to be used.
7836 * This parameter can be one of the following values:
7837 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7838 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7839 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7840 * @param TIM_ICFilter Specifies the Input Capture Filter.
7841 * This parameter must be a value between 0x00 and 0x0F.
7842 * @retval None
7843 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7844 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7845 * protected against un-initialized filter and polarity values.
7846 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7847 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7848 uint32_t TIM_ICFilter)
7849 {
7850 uint32_t tmpccmr1;
7851 uint32_t tmpccer;
7852
7853 /* Disable the Channel 1: Reset the CC1E Bit */
7854 tmpccer = TIMx->CCER;
7855 TIMx->CCER &= ~TIM_CCER_CC1E;
7856 tmpccmr1 = TIMx->CCMR1;
7857
7858 /* Select the Input */
7859 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7860 {
7861 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7862 tmpccmr1 |= TIM_ICSelection;
7863 }
7864 else
7865 {
7866 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7867 }
7868
7869 /* Set the filter */
7870 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7871 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7872
7873 /* Select the Polarity and set the CC1E Bit */
7874 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7875 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7876
7877 /* Write to TIMx CCMR1 and CCER registers */
7878 TIMx->CCMR1 = tmpccmr1;
7879 TIMx->CCER = tmpccer;
7880 }
7881
7882 /**
7883 * @brief Configure the Polarity and Filter for TI1.
7884 * @param TIMx to select the TIM peripheral.
7885 * @param TIM_ICPolarity The Input Polarity.
7886 * This parameter can be one of the following values:
7887 * @arg TIM_ICPOLARITY_RISING
7888 * @arg TIM_ICPOLARITY_FALLING
7889 * @arg TIM_ICPOLARITY_BOTHEDGE
7890 * @param TIM_ICFilter Specifies the Input Capture Filter.
7891 * This parameter must be a value between 0x00 and 0x0F.
7892 * @retval None
7893 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7894 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7895 {
7896 uint32_t tmpccmr1;
7897 uint32_t tmpccer;
7898
7899 /* Disable the Channel 1: Reset the CC1E Bit */
7900 tmpccer = TIMx->CCER;
7901 TIMx->CCER &= ~TIM_CCER_CC1E;
7902 tmpccmr1 = TIMx->CCMR1;
7903
7904 /* Set the filter */
7905 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7906 tmpccmr1 |= (TIM_ICFilter << 4U);
7907
7908 /* Select the Polarity and set the CC1E Bit */
7909 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7910 tmpccer |= TIM_ICPolarity;
7911
7912 /* Write to TIMx CCMR1 and CCER registers */
7913 TIMx->CCMR1 = tmpccmr1;
7914 TIMx->CCER = tmpccer;
7915 }
7916
7917 /**
7918 * @brief Configure the TI2 as Input.
7919 * @param TIMx to select the TIM peripheral
7920 * @param TIM_ICPolarity The Input Polarity.
7921 * This parameter can be one of the following values:
7922 * @arg TIM_ICPOLARITY_RISING
7923 * @arg TIM_ICPOLARITY_FALLING
7924 * @arg TIM_ICPOLARITY_BOTHEDGE
7925 * @param TIM_ICSelection specifies the input to be used.
7926 * This parameter can be one of the following values:
7927 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7928 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7929 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7930 * @param TIM_ICFilter Specifies the Input Capture Filter.
7931 * This parameter must be a value between 0x00 and 0x0F.
7932 * @retval None
7933 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7934 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7935 * protected against un-initialized filter and polarity values.
7936 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7937 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7938 uint32_t TIM_ICFilter)
7939 {
7940 uint32_t tmpccmr1;
7941 uint32_t tmpccer;
7942
7943 /* Disable the Channel 2: Reset the CC2E Bit */
7944 tmpccer = TIMx->CCER;
7945 TIMx->CCER &= ~TIM_CCER_CC2E;
7946 tmpccmr1 = TIMx->CCMR1;
7947
7948 /* Select the Input */
7949 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7950 tmpccmr1 |= (TIM_ICSelection << 8U);
7951
7952 /* Set the filter */
7953 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7954 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7955
7956 /* Select the Polarity and set the CC2E Bit */
7957 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7958 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7959
7960 /* Write to TIMx CCMR1 and CCER registers */
7961 TIMx->CCMR1 = tmpccmr1 ;
7962 TIMx->CCER = tmpccer;
7963 }
7964
7965 /**
7966 * @brief Configure the Polarity and Filter for TI2.
7967 * @param TIMx to select the TIM peripheral.
7968 * @param TIM_ICPolarity The Input Polarity.
7969 * This parameter can be one of the following values:
7970 * @arg TIM_ICPOLARITY_RISING
7971 * @arg TIM_ICPOLARITY_FALLING
7972 * @arg TIM_ICPOLARITY_BOTHEDGE
7973 * @param TIM_ICFilter Specifies the Input Capture Filter.
7974 * This parameter must be a value between 0x00 and 0x0F.
7975 * @retval None
7976 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7977 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7978 {
7979 uint32_t tmpccmr1;
7980 uint32_t tmpccer;
7981
7982 /* Disable the Channel 2: Reset the CC2E Bit */
7983 tmpccer = TIMx->CCER;
7984 TIMx->CCER &= ~TIM_CCER_CC2E;
7985 tmpccmr1 = TIMx->CCMR1;
7986
7987 /* Set the filter */
7988 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7989 tmpccmr1 |= (TIM_ICFilter << 12U);
7990
7991 /* Select the Polarity and set the CC2E Bit */
7992 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7993 tmpccer |= (TIM_ICPolarity << 4U);
7994
7995 /* Write to TIMx CCMR1 and CCER registers */
7996 TIMx->CCMR1 = tmpccmr1 ;
7997 TIMx->CCER = tmpccer;
7998 }
7999
8000 /**
8001 * @brief Configure the TI3 as Input.
8002 * @param TIMx to select the TIM peripheral
8003 * @param TIM_ICPolarity The Input Polarity.
8004 * This parameter can be one of the following values:
8005 * @arg TIM_ICPOLARITY_RISING
8006 * @arg TIM_ICPOLARITY_FALLING
8007 * @arg TIM_ICPOLARITY_BOTHEDGE
8008 * @param TIM_ICSelection specifies the input to be used.
8009 * This parameter can be one of the following values:
8010 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
8011 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
8012 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
8013 * @param TIM_ICFilter Specifies the Input Capture Filter.
8014 * This parameter must be a value between 0x00 and 0x0F.
8015 * @retval None
8016 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
8017 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
8018 * protected against un-initialized filter and polarity values.
8019 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)8020 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
8021 uint32_t TIM_ICFilter)
8022 {
8023 uint32_t tmpccmr2;
8024 uint32_t tmpccer;
8025
8026 /* Disable the Channel 3: Reset the CC3E Bit */
8027 tmpccer = TIMx->CCER;
8028 TIMx->CCER &= ~TIM_CCER_CC3E;
8029 tmpccmr2 = TIMx->CCMR2;
8030
8031 /* Select the Input */
8032 tmpccmr2 &= ~TIM_CCMR2_CC3S;
8033 tmpccmr2 |= TIM_ICSelection;
8034
8035 /* Set the filter */
8036 tmpccmr2 &= ~TIM_CCMR2_IC3F;
8037 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
8038
8039 /* Select the Polarity and set the CC3E Bit */
8040 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
8041 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
8042
8043 /* Write to TIMx CCMR2 and CCER registers */
8044 TIMx->CCMR2 = tmpccmr2;
8045 TIMx->CCER = tmpccer;
8046 }
8047
8048 /**
8049 * @brief Configure the TI4 as Input.
8050 * @param TIMx to select the TIM peripheral
8051 * @param TIM_ICPolarity The Input Polarity.
8052 * This parameter can be one of the following values:
8053 * @arg TIM_ICPOLARITY_RISING
8054 * @arg TIM_ICPOLARITY_FALLING
8055 * @arg TIM_ICPOLARITY_BOTHEDGE
8056 * @param TIM_ICSelection specifies the input to be used.
8057 * This parameter can be one of the following values:
8058 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
8059 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
8060 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
8061 * @param TIM_ICFilter Specifies the Input Capture Filter.
8062 * This parameter must be a value between 0x00 and 0x0F.
8063 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
8064 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
8065 * protected against un-initialized filter and polarity values.
8066 * @retval None
8067 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)8068 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
8069 uint32_t TIM_ICFilter)
8070 {
8071 uint32_t tmpccmr2;
8072 uint32_t tmpccer;
8073
8074 /* Disable the Channel 4: Reset the CC4E Bit */
8075 tmpccer = TIMx->CCER;
8076 TIMx->CCER &= ~TIM_CCER_CC4E;
8077 tmpccmr2 = TIMx->CCMR2;
8078
8079 /* Select the Input */
8080 tmpccmr2 &= ~TIM_CCMR2_CC4S;
8081 tmpccmr2 |= (TIM_ICSelection << 8U);
8082
8083 /* Set the filter */
8084 tmpccmr2 &= ~TIM_CCMR2_IC4F;
8085 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
8086
8087 /* Select the Polarity and set the CC4E Bit */
8088 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
8089 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
8090
8091 /* Write to TIMx CCMR2 and CCER registers */
8092 TIMx->CCMR2 = tmpccmr2;
8093 TIMx->CCER = tmpccer ;
8094 }
8095
8096 /**
8097 * @brief Selects the Input Trigger source
8098 * @param TIMx to select the TIM peripheral
8099 * @param InputTriggerSource The Input Trigger source.
8100 * This parameter can be one of the following values:
8101 * @arg TIM_TS_ITR0: Internal Trigger 0
8102 * @arg TIM_TS_ITR1: Internal Trigger 1
8103 * @arg TIM_TS_ITR2: Internal Trigger 2
8104 * @arg TIM_CLOCKSOURCE_ITR3: Internal Trigger 3
8105 * @arg TIM_CLOCKSOURCE_ITR4: Internal Trigger 4
8106 * @arg TIM_CLOCKSOURCE_ITR5: Internal Trigger 5
8107 * @arg TIM_CLOCKSOURCE_ITR6: Internal Trigger 6
8108 * @arg TIM_CLOCKSOURCE_ITR7: Internal Trigger 7
8109 * @arg TIM_CLOCKSOURCE_ITR8: Internal Trigger 8
8110 * @arg TIM_CLOCKSOURCE_ITR9: Internal Trigger 9
8111 * @arg TIM_CLOCKSOURCE_ITR10: Internal Trigger 10
8112 * @arg TIM_CLOCKSOURCE_ITR11: Internal Trigger 11
8113 * @arg TIM_CLOCKSOURCE_ITR13: Internal Trigger 13
8114 * @arg TIM_CLOCKSOURCE_ITR14: Internal Trigger 14
8115 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
8116 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
8117 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
8118 * @arg TIM_TS_ETRF: External Trigger input
8119 * @retval None
8120 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)8121 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
8122 {
8123 uint32_t tmpsmcr;
8124
8125 /* Get the TIMx SMCR register value */
8126 tmpsmcr = TIMx->SMCR;
8127 /* Reset the TS Bits */
8128 tmpsmcr &= ~TIM_SMCR_TS;
8129 /* Set the Input Trigger source and the slave mode*/
8130 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8131 /* Write to TIMx SMCR */
8132 TIMx->SMCR = tmpsmcr;
8133 }
8134 /**
8135 * @brief Configures the TIMx External Trigger (ETR).
8136 * @param TIMx to select the TIM peripheral
8137 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
8138 * This parameter can be one of the following values:
8139 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
8140 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
8141 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
8142 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
8143 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
8144 * This parameter can be one of the following values:
8145 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
8146 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
8147 * @param ExtTRGFilter External Trigger Filter.
8148 * This parameter must be a value between 0x00 and 0x0F
8149 * @retval None
8150 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)8151 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
8152 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
8153 {
8154 uint32_t tmpsmcr;
8155
8156 tmpsmcr = TIMx->SMCR;
8157
8158 /* Reset the ETR Bits */
8159 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8160
8161 /* Set the Prescaler, the Filter value and the Polarity */
8162 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8163
8164 /* Write to TIMx SMCR */
8165 TIMx->SMCR = tmpsmcr;
8166 }
8167
8168 /**
8169 * @brief Enables or disables the TIM Capture Compare Channel x.
8170 * @param TIMx to select the TIM peripheral
8171 * @param Channel specifies the TIM Channel
8172 * This parameter can be one of the following values:
8173 * @arg TIM_CHANNEL_1: TIM Channel 1
8174 * @arg TIM_CHANNEL_2: TIM Channel 2
8175 * @arg TIM_CHANNEL_3: TIM Channel 3
8176 * @arg TIM_CHANNEL_4: TIM Channel 4
8177 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
8178 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
8179 * @param ChannelState specifies the TIM Channel CCxE bit new state.
8180 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
8181 * @retval None
8182 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)8183 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
8184 {
8185 uint32_t tmp;
8186
8187 /* Check the parameters */
8188 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
8189 assert_param(IS_TIM_CHANNELS(Channel));
8190
8191 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8192
8193 /* Reset the CCxE Bit */
8194 TIMx->CCER &= ~tmp;
8195
8196 /* Set or reset the CCxE Bit */
8197 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8198 }
8199
8200 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
8201 /**
8202 * @brief Reset interrupt callbacks to the legacy weak callbacks.
8203 * @param htim pointer to a TIM_HandleTypeDef structure that contains
8204 * the configuration information for TIM module.
8205 * @retval None
8206 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)8207 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
8208 {
8209 /* Reset the TIM callback to the legacy weak callbacks */
8210 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback;
8211 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback;
8212 htim->TriggerCallback = HAL_TIM_TriggerCallback;
8213 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback;
8214 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback;
8215 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback;
8216 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback;
8217 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback;
8218 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
8219 htim->ErrorCallback = HAL_TIM_ErrorCallback;
8220 htim->CommutationCallback = HAL_TIMEx_CommutCallback;
8221 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback;
8222 htim->BreakCallback = HAL_TIMEx_BreakCallback;
8223 htim->Break2Callback = HAL_TIMEx_Break2Callback;
8224 htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback;
8225 htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback;
8226 htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback;
8227 htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback;
8228 }
8229 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
8230
8231 /**
8232 * @}
8233 */
8234
8235 #endif /* HAL_TIM_MODULE_ENABLED */
8236 /**
8237 * @}
8238 */
8239
8240 /**
8241 * @}
8242 */
8243
