1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_hal_i2s.c
4 * @author MCD Application Team
5 * @brief I2S HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2022 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ===============================================================================
24 ##### How to use this driver #####
25 ===============================================================================
26 [..]
27 The I2S HAL driver can be used as follow:
28
29 (#) Declare a I2S_HandleTypeDef handle structure.
30 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
31 (##) Enable the SPIx interface clock.
32 (##) I2S pins configuration:
33 (+++) Enable the clock for the I2S GPIOs.
34 (+++) Configure these I2S pins as alternate function pull-up.
35 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
36 and HAL_I2S_Receive_IT() APIs).
37 (+++) Configure the I2Sx interrupt priority.
38 (+++) Enable the NVIC I2S IRQ handle.
39 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
40 and HAL_I2S_Receive_DMA() APIs:
41 (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
42 (+++) Enable the DMAx interface clock.
43 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
44 (+++) Configure the DMA Tx/Rx Stream/Channel.
45 (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
46 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
47 DMA Tx/Rx Stream/Channel.
48
49 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
50 using HAL_I2S_Init() function.
51
52 -@- The specific I2S interrupts (Transmission complete interrupt,
53 RXNE interrupt and Error Interrupts) will be managed using the macros
54 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
55
56 (+@) External clock source is configured after setting correctly
57 the define constant EXTERNAL_CLOCK_VALUE in the stm32h7rsxx_hal_conf.h file.
58
59 (#) Three mode of operations are available within this driver :
60
61 *** Polling mode IO operation ***
62 =================================
63 [..]
64 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
65 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
66
67 *** Interrupt mode IO operation ***
68 ===================================
69 [..]
70 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
71 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
72 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
73 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
74 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
75 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
76 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
77 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
78 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
79 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
80 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
81 add his own code by customization of function pointer HAL_I2S_ErrorCallback
82
83 *** DMA mode IO operation ***
84 ==============================
85 [..]
86 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
87 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
88 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
89 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
90 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
91 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
92 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
93 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
94 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
95 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
96 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
97 add his own code by customization of function pointer HAL_I2S_ErrorCallback
98 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
99 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
100 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
101
102 *** I2S HAL driver macros list ***
103 ===================================
104 [..]
105 Below the list of most used macros in I2S HAL driver.
106
107 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
108 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
109 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
110 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
111 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
112
113 [..]
114 (@) You can refer to the I2S HAL driver header file for more useful macros
115
116 *** I2S HAL driver macros list ***
117 ===================================
118 [..]
119 Callback registration:
120
121 (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1UL
122 allows the user to configure dynamically the driver callbacks.
123 Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
124
125 Function HAL_I2S_RegisterCallback() allows to register following callbacks:
126 (+) TxCpltCallback : I2S Tx Completed callback
127 (+) RxCpltCallback : I2S Rx Completed callback
128 (+) TxRxCpltCallback : I2S TxRx Completed callback
129 (+) TxHalfCpltCallback : I2S Tx Half Completed callback
130 (+) RxHalfCpltCallback : I2S Rx Half Completed callback
131 (+) TxRxHalfCpltCallback : I2S TxRx Half Completed callback
132 (+) ErrorCallback : I2S Error callback
133 (+) MspInitCallback : I2S Msp Init callback
134 (+) MspDeInitCallback : I2S Msp DeInit callback
135 This function takes as parameters the HAL peripheral handle, the Callback ID
136 and a pointer to the user callback function.
137
138
139 (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
140 weak function.
141 HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
142 and the Callback ID.
143 This function allows to reset following callbacks:
144 (+) TxCpltCallback : I2S Tx Completed callback
145 (+) RxCpltCallback : I2S Rx Completed callback
146 (+) TxRxCpltCallback : I2S TxRx Completed callback
147 (+) TxHalfCpltCallback : I2S Tx Half Completed callback
148 (+) RxHalfCpltCallback : I2S Rx Half Completed callback
149 (+) TxRxHalfCpltCallback : I2S TxRx Half Completed callback
150 (+) ErrorCallback : I2S Error callback
151 (+) MspInitCallback : I2S Msp Init callback
152 (+) MspDeInitCallback : I2S Msp DeInit callback
153
154 By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
155 all callbacks are set to the corresponding weak functions:
156 examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
157 Exception done for MspInit and MspDeInit functions that are
158 reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
159 these callbacks are null (not registered beforehand).
160 If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
161 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
162
163 Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
164 Exception done MspInit/MspDeInit functions that can be registered/unregistered
165 in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
166 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
167 Then, the user first registers the MspInit/MspDeInit user callbacks
168 using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
169 or HAL_I2S_Init() function.
170
171 When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
172 not defined, the callback registering feature is not available
173 and weak (surcharged) callbacks are used.
174
175
176 @endverbatim
177 */
178
179 /* Includes ------------------------------------------------------------------*/
180 #include "stm32h7rsxx_hal.h"
181
182 #ifdef HAL_I2S_MODULE_ENABLED
183
184 /** @addtogroup STM32H7RSxx_HAL_Driver
185 * @{
186 */
187
188 /** @defgroup I2S I2S
189 * @brief I2S HAL module driver
190 * @{
191 */
192
193 /* Private typedef -----------------------------------------------------------*/
194 /* Private define ------------------------------------------------------------*/
195 /** @defgroup I2S_Private_Define I2S Private Define
196 * @{
197 */
198 #define I2S_TIMEOUT 0xFFFFUL
199 /**
200 * @}
201 */
202
203 /* Private macro -------------------------------------------------------------*/
204 /* Private variables ---------------------------------------------------------*/
205 /* Private function prototypes -----------------------------------------------*/
206 /** @defgroup I2S_Private_Functions I2S Private Functions
207 * @{
208 */
209 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
210 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
211 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
212 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
213 static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma);
214 static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma);
215 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
216 static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s);
217 static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s);
218 static void I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s);
219 static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s);
220 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
221 uint32_t Tickstart, uint32_t Timeout);
222 /**
223 * @}
224 */
225
226 /* Exported functions ---------------------------------------------------------*/
227
228 /** @defgroup I2S_Exported_Functions I2S Exported Functions
229 * @{
230 */
231
232 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
233 * @brief Initialization and Configuration functions
234 *
235 @verbatim
236 ===============================================================================
237 ##### Initialization and de-initialization functions #####
238 ===============================================================================
239 [..] This subsection provides a set of functions allowing to initialize and
240 de-initialize the I2Sx peripheral in simplex mode:
241
242 (+) User must Implement HAL_I2S_MspInit() function in which he configures
243 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
244
245 (+) Call the function HAL_I2S_Init() to configure the selected device with
246 the selected configuration:
247 (++) Mode
248 (++) Standard
249 (++) Data Format
250 (++) MCLK Output
251 (++) Audio frequency
252 (++) Polarity
253
254 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
255 of the selected I2Sx peripheral.
256 @endverbatim
257 * @{
258 */
259
260 /**
261 * @brief Initializes the I2S according to the specified parameters
262 * in the I2S_InitTypeDef and create the associated handle.
263 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
264 * the configuration information for I2S module
265 * @retval HAL status
266 */
HAL_I2S_Init(I2S_HandleTypeDef * hi2s)267 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
268 {
269 uint32_t i2sdiv;
270 uint32_t i2sodd;
271 uint32_t packetlength;
272 uint32_t tmp;
273 uint32_t i2sclk;
274 uint32_t ispcm;
275
276 /* Check the I2S handle allocation */
277 if (hi2s == NULL)
278 {
279 return HAL_ERROR;
280 }
281
282 /* Check the I2S parameters */
283 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
284 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
285 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
286 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
287 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
288 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
289 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
290 assert_param(IS_I2S_FIRST_BIT(hi2s->Init.FirstBit));
291 assert_param(IS_I2S_WS_INVERSION(hi2s->Init.WSInversion));
292 assert_param(IS_I2S_DATA_24BIT_ALIGNMENT(hi2s->Init.Data24BitAlignment));
293 assert_param(IS_I2S_MASTER_KEEP_IO_STATE(hi2s->Init.MasterKeepIOState));
294
295 if (hi2s->State == HAL_I2S_STATE_RESET)
296 {
297 /* Allocate lock resource and initialize it */
298 hi2s->Lock = HAL_UNLOCKED;
299
300 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
301 /* Init the I2S Callback settings */
302 hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
303 hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
304 hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
305 hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
306 hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
307 hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
308 hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
309
310 if (hi2s->MspInitCallback == NULL)
311 {
312 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
313 }
314
315 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
316 hi2s->MspInitCallback(hi2s);
317 #else
318 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
319 HAL_I2S_MspInit(hi2s);
320 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
321 }
322
323 hi2s->State = HAL_I2S_STATE_BUSY;
324
325 /* Disable the selected I2S peripheral */
326 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) == SPI_CR1_SPE)
327 {
328 /* Disable I2S peripheral */
329 __HAL_I2S_DISABLE(hi2s);
330 }
331
332 /* Clear I2S configuration register */
333 CLEAR_REG(hi2s->Instance->I2SCFGR);
334
335 if (IS_I2S_MASTER(hi2s->Init.Mode))
336 {
337 /*------------------------- I2SDIV and ODD Calculation ---------------------*/
338 /* If the requested audio frequency is not the default, compute the prescaler */
339 if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
340 {
341 /* Check the frame length (For the Prescaler computing) ********************/
342 if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
343 {
344 /* Channel length is 32 bits */
345 packetlength = 2UL;
346 }
347 else
348 {
349 /* Channel length is 16 bits */
350 packetlength = 1UL;
351 }
352
353 /* Check if PCM standard is used */
354 if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) ||
355 (hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))
356 {
357 ispcm = 1UL;
358 }
359 else
360 {
361 ispcm = 0UL;
362 }
363
364 /* Get the source clock value: based on System Clock value */
365 if (hi2s->Instance == SPI1)
366 {
367 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI1);
368 }
369 else if ((hi2s->Instance == SPI2) || (hi2s->Instance == SPI3))
370 {
371 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI23);
372 }
373 else /* SPI6 source clock */
374 {
375 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6);
376 }
377
378 /* Compute the Real divider depending on the MCLK output state, with a floating point */
379 if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
380 {
381 /* MCLK output is enabled */
382 tmp = (uint32_t)((((i2sclk / (256UL >> ispcm)) * 10UL) / hi2s->Init.AudioFreq) + 5UL);
383 }
384 else
385 {
386 /* MCLK output is disabled */
387 tmp = (uint32_t)((((i2sclk / ((32UL >> ispcm) * packetlength)) * 10UL) / hi2s->Init.AudioFreq) + 5UL);
388 }
389
390 /* Remove the flatting point */
391 tmp = tmp / 10UL;
392
393 /* Check the parity of the divider */
394 i2sodd = (uint32_t)(tmp & (uint32_t)1UL);
395
396 /* Compute the i2sdiv prescaler */
397 i2sdiv = (uint32_t)((tmp - i2sodd) / 2UL);
398 }
399 else
400 {
401 /* Set the default values */
402 i2sdiv = 2UL;
403 i2sodd = 0UL;
404 }
405
406 /* Test if the obtain values are forbidden or out of range */
407 if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
408 {
409 /* Set the error code */
410 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
411 return HAL_ERROR;
412 }
413
414 /* Force i2smod to 1 just to be sure that (2xi2sdiv + i2sodd) is always higher than 0 */
415 if (i2sdiv == 0UL)
416 {
417 i2sodd = 1UL;
418 }
419
420 MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD),
421 ((i2sdiv << SPI_I2SCFGR_I2SDIV_Pos) | (i2sodd << SPI_I2SCFGR_ODD_Pos)));
422 }
423
424 /*-------------------------- I2Sx I2SCFGR Configuration --------------------*/
425 /* Configure I2SMOD, I2SCFG, I2SSTD, PCMSYNC, DATLEN ,CHLEN ,CKPOL, WSINV, DATAFMT, I2SDIV, ODD and MCKOE bits bits */
426 /* And configure the I2S with the I2S_InitStruct values */
427 MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SCFG | \
428 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | \
429 SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | \
430 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_WSINV | \
431 SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_MCKOE),
432 (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
433 hi2s->Init.Standard | hi2s->Init.DataFormat | \
434 hi2s->Init.CPOL | hi2s->Init.WSInversion | \
435 hi2s->Init.Data24BitAlignment | hi2s->Init.MCLKOutput));
436 /*Clear status register*/
437 WRITE_REG(hi2s->Instance->IFCR, 0x0FF8);
438
439 /*---------------------------- I2Sx CFG2 Configuration ----------------------*/
440
441 /* Unlock the AF configuration to configure CFG2 register*/
442 CLEAR_BIT(hi2s->Instance->CR1, SPI_CR1_IOLOCK);
443
444 MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_LSBFRST, hi2s->Init.FirstBit);
445
446 /* Insure that AFCNTR is managed only by Master */
447 if (IS_I2S_MASTER(hi2s->Init.Mode))
448 {
449 /* Alternate function GPIOs control */
450 MODIFY_REG(hi2s->Instance->CFG2, SPI_CFG2_AFCNTR, (hi2s->Init.MasterKeepIOState));
451 }
452
453 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
454 hi2s->State = HAL_I2S_STATE_READY;
455
456 return HAL_OK;
457 }
458
459 /**
460 * @brief DeInitializes the I2S peripheral
461 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
462 * the configuration information for I2S module
463 * @retval HAL status
464 */
HAL_I2S_DeInit(I2S_HandleTypeDef * hi2s)465 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
466 {
467 /* Check the I2S handle allocation */
468 if (hi2s == NULL)
469 {
470 return HAL_ERROR;
471 }
472
473 /* Check the parameters */
474 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
475
476 hi2s->State = HAL_I2S_STATE_BUSY;
477
478 /* Disable the I2S Peripheral Clock */
479 __HAL_I2S_DISABLE(hi2s);
480
481 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
482 if (hi2s->MspDeInitCallback == NULL)
483 {
484 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
485 }
486
487 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
488 hi2s->MspDeInitCallback(hi2s);
489 #else
490 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
491 HAL_I2S_MspDeInit(hi2s);
492 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
493
494 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
495 hi2s->State = HAL_I2S_STATE_RESET;
496
497 /* Release Lock */
498 __HAL_UNLOCK(hi2s);
499
500 return HAL_OK;
501 }
502
503 /**
504 * @brief I2S MSP Init
505 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
506 * the configuration information for I2S module
507 * @retval None
508 */
HAL_I2S_MspInit(I2S_HandleTypeDef * hi2s)509 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
510 {
511 /* Prevent unused argument(s) compilation warning */
512 UNUSED(hi2s);
513
514 /* NOTE : This function Should not be modified, when the callback is needed,
515 the HAL_I2S_MspInit could be implemented in the user file
516 */
517 }
518
519 /**
520 * @brief I2S MSP DeInit
521 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
522 * the configuration information for I2S module
523 * @retval None
524 */
HAL_I2S_MspDeInit(I2S_HandleTypeDef * hi2s)525 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
526 {
527 /* Prevent unused argument(s) compilation warning */
528 UNUSED(hi2s);
529
530 /* NOTE : This function Should not be modified, when the callback is needed,
531 the HAL_I2S_MspDeInit could be implemented in the user file
532 */
533 }
534
535 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
536 /**
537 * @brief Register a User I2S Callback
538 * To be used instead of the weak predefined callback
539 * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
540 * the configuration information for the specified I2S.
541 * @param CallbackID ID of the callback to be registered
542 * @param pCallback pointer to the Callback function
543 * @retval HAL status
544 */
HAL_I2S_RegisterCallback(I2S_HandleTypeDef * hi2s,HAL_I2S_CallbackIDTypeDef CallbackID,pI2S_CallbackTypeDef pCallback)545 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
546 pI2S_CallbackTypeDef pCallback)
547 {
548 HAL_StatusTypeDef status = HAL_OK;
549
550 if (pCallback == NULL)
551 {
552 /* Update the error code */
553 hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
554
555 return HAL_ERROR;
556 }
557 /* Process locked */
558 __HAL_LOCK(hi2s);
559
560 if (HAL_I2S_STATE_READY == hi2s->State)
561 {
562 switch (CallbackID)
563 {
564 case HAL_I2S_TX_COMPLETE_CB_ID :
565 hi2s->TxCpltCallback = pCallback;
566 break;
567
568 case HAL_I2S_RX_COMPLETE_CB_ID :
569 hi2s->RxCpltCallback = pCallback;
570 break;
571
572 case HAL_I2S_TX_RX_COMPLETE_CB_ID :
573 hi2s->TxRxCpltCallback = pCallback;
574 break;
575
576 case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
577 hi2s->TxHalfCpltCallback = pCallback;
578 break;
579
580 case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
581 hi2s->RxHalfCpltCallback = pCallback;
582 break;
583
584
585 case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
586 hi2s->TxRxHalfCpltCallback = pCallback;
587 break;
588
589 case HAL_I2S_ERROR_CB_ID :
590 hi2s->ErrorCallback = pCallback;
591 break;
592
593 case HAL_I2S_MSPINIT_CB_ID :
594 hi2s->MspInitCallback = pCallback;
595 break;
596
597 case HAL_I2S_MSPDEINIT_CB_ID :
598 hi2s->MspDeInitCallback = pCallback;
599 break;
600
601 default :
602 /* Update the error code */
603 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
604
605 /* Return error status */
606 status = HAL_ERROR;
607 break;
608 }
609 }
610 else if (HAL_I2S_STATE_RESET == hi2s->State)
611 {
612 switch (CallbackID)
613 {
614 case HAL_I2S_MSPINIT_CB_ID :
615 hi2s->MspInitCallback = pCallback;
616 break;
617
618 case HAL_I2S_MSPDEINIT_CB_ID :
619 hi2s->MspDeInitCallback = pCallback;
620 break;
621
622 default :
623 /* Update the error code */
624 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
625
626 /* Return error status */
627 status = HAL_ERROR;
628 break;
629 }
630 }
631 else
632 {
633 /* Update the error code */
634 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
635
636 /* Return error status */
637 status = HAL_ERROR;
638 }
639
640 /* Release Lock */
641 __HAL_UNLOCK(hi2s);
642 return status;
643 }
644
645 /**
646 * @brief Unregister an I2S Callback
647 * I2S callback is redirected to the weak predefined callback
648 * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
649 * the configuration information for the specified I2S.
650 * @param CallbackID ID of the callback to be unregistered
651 * @retval HAL status
652 */
HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef * hi2s,HAL_I2S_CallbackIDTypeDef CallbackID)653 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
654 {
655 HAL_StatusTypeDef status = HAL_OK;
656
657 /* Process locked */
658 __HAL_LOCK(hi2s);
659
660 if (HAL_I2S_STATE_READY == hi2s->State)
661 {
662 switch (CallbackID)
663 {
664 case HAL_I2S_TX_COMPLETE_CB_ID :
665 hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
666 break;
667
668 case HAL_I2S_RX_COMPLETE_CB_ID :
669 hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
670 break;
671
672 case HAL_I2S_TX_RX_COMPLETE_CB_ID :
673 hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
674 break;
675
676 case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
677 hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
678 break;
679
680 case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
681 hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
682 break;
683
684 case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
685 hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
686 break;
687
688 case HAL_I2S_ERROR_CB_ID :
689 hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
690 break;
691
692 case HAL_I2S_MSPINIT_CB_ID :
693 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
694 break;
695
696 case HAL_I2S_MSPDEINIT_CB_ID :
697 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
698 break;
699
700 default :
701 /* Update the error code */
702 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
703
704 /* Return error status */
705 status = HAL_ERROR;
706 break;
707 }
708 }
709 else if (HAL_I2S_STATE_RESET == hi2s->State)
710 {
711 switch (CallbackID)
712 {
713 case HAL_I2S_MSPINIT_CB_ID :
714 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
715 break;
716
717 case HAL_I2S_MSPDEINIT_CB_ID :
718 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
719 break;
720
721 default :
722 /* Update the error code */
723 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
724
725 /* Return error status */
726 status = HAL_ERROR;
727 break;
728 }
729 }
730 else
731 {
732 /* Update the error code */
733 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
734
735 /* Return error status */
736 status = HAL_ERROR;
737 }
738
739 /* Release Lock */
740 __HAL_UNLOCK(hi2s);
741 return status;
742 }
743 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
744 /**
745 * @}
746 */
747
748 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
749 * @brief Data transfers functions
750 *
751 @verbatim
752 ===============================================================================
753 ##### IO operation functions #####
754 ===============================================================================
755 [..]
756 This subsection provides a set of functions allowing to manage the I2S data
757 transfers.
758
759 (#) There are two modes of transfer:
760 (++) Blocking mode : The communication is performed in the polling mode.
761 The status of all data processing is returned by the same function
762 after finishing transfer.
763 (++) No-Blocking mode : The communication is performed using Interrupts
764 or DMA. These functions return the status of the transfer startup.
765 The end of the data processing will be indicated through the
766 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
767 using DMA mode.
768
769 (#) Blocking mode functions are :
770 (++) HAL_I2S_Transmit()
771 (++) HAL_I2S_Receive()
772 (++) HAL_I2SEx_TransmitReceive()
773
774 (#) No-Blocking mode functions with Interrupt are :
775 (++) HAL_I2S_Transmit_IT()
776 (++) HAL_I2S_Receive_IT()
777 (++) HAL_I2SEx_TransmitReceive_IT()
778
779 (#) No-Blocking mode functions with DMA are :
780 (++) HAL_I2S_Transmit_DMA()
781 (++) HAL_I2S_Receive_DMA()
782 (++) HAL_I2SEx_TransmitReceive_DMA()
783
784 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
785 (++) HAL_I2S_TxCpltCallback()
786 (++) HAL_I2S_RxCpltCallback()
787 (++) HAL_I2SEx_TxRxCpltCallback()
788 (++) HAL_I2S_ErrorCallback()
789
790 @endverbatim
791 * @{
792 */
793
794 /**
795 * @brief Transmit an amount of data in blocking mode
796 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
797 * the configuration information for I2S module
798 * @param pData a 16-bit pointer to data buffer.
799 * @param Size number of data sample to be sent:
800 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
801 * configuration phase, the Size parameter means the number of 16-bit data length
802 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
803 * the Size parameter means the number of 16-bit data length.
804 * @param Timeout Timeout duration
805 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
806 * between Master and Slave(example: audio streaming).
807 * @retval HAL status
808 */
HAL_I2S_Transmit(I2S_HandleTypeDef * hi2s,const uint16_t * pData,uint16_t Size,uint32_t Timeout)809 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size, uint32_t Timeout)
810 {
811 #if defined (__GNUC__)
812 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
813 #endif /* __GNUC__ */
814 uint32_t tickstart;
815
816 if ((pData == NULL) || (Size == 0UL))
817 {
818 return HAL_ERROR;
819 }
820
821 if (hi2s->State != HAL_I2S_STATE_READY)
822 {
823 return HAL_BUSY;
824 }
825
826 /* Process Locked */
827 __HAL_LOCK(hi2s);
828
829 /* Init tickstart for timeout management*/
830 tickstart = HAL_GetTick();
831
832 /* Set state and reset error code */
833 hi2s->State = HAL_I2S_STATE_BUSY_TX;
834 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
835 hi2s->pTxBuffPtr = (const uint16_t *)pData;
836 hi2s->TxXferSize = Size;
837 hi2s->TxXferCount = Size;
838
839 /* Initialize fields not used in handle to zero */
840 hi2s->pRxBuffPtr = NULL;
841 hi2s->RxXferSize = (uint16_t) 0UL;
842 hi2s->RxXferCount = (uint16_t) 0UL;
843
844 /* Check if the I2S is already enabled */
845 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
846 {
847 /* Enable I2S peripheral */
848 __HAL_I2S_ENABLE(hi2s);
849 }
850
851 /* Start the transfer */
852 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
853
854
855 /* Wait until TXP flag is set */
856 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, tickstart, Timeout) != HAL_OK)
857 {
858 /* Set the error code */
859 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
860 hi2s->State = HAL_I2S_STATE_READY;
861 __HAL_UNLOCK(hi2s);
862 return HAL_TIMEOUT;
863 }
864
865 while (hi2s->TxXferCount > 0UL)
866 {
867 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
868 {
869 /* Transmit data in 32 Bit mode */
870 hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr);
871 hi2s->pTxBuffPtr += 2;
872 hi2s->TxXferCount--;
873 }
874 else
875 {
876 /* Transmit data in 16 Bit mode */
877 #if defined (__GNUC__)
878 *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr);
879 #else
880 *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr);
881 #endif /* __GNUC__ */
882
883 hi2s->pTxBuffPtr++;
884 hi2s->TxXferCount--;
885 }
886
887 /* Wait until TXP flag is set */
888 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, tickstart, Timeout) != HAL_OK)
889 {
890 /* Set the error code */
891 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
892 hi2s->State = HAL_I2S_STATE_READY;
893 __HAL_UNLOCK(hi2s);
894 return HAL_TIMEOUT;
895 }
896
897 /* Check if an underrun occurs */
898 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
899 {
900 /* Clear underrun flag */
901 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
902
903 /* Set the error code */
904 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
905 }
906 }
907
908 hi2s->State = HAL_I2S_STATE_READY;
909 __HAL_UNLOCK(hi2s);
910 return HAL_OK;
911 }
912
913 /**
914 * @brief Receive an amount of data in blocking mode
915 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
916 * the configuration information for I2S module
917 * @param pData a 16-bit pointer to data buffer.
918 * @param Size number of data sample to be sent:
919 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
920 * configuration phase, the Size parameter means the number of 16-bit data length
921 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
922 * the Size parameter means the number of 16-bit data length.
923 * @param Timeout Timeout duration
924 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
925 * between Master and Slave(example: audio streaming).
926 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
927 * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
928 * @retval HAL status
929 */
HAL_I2S_Receive(I2S_HandleTypeDef * hi2s,uint16_t * pData,uint16_t Size,uint32_t Timeout)930 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
931 {
932 #if defined (__GNUC__)
933 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
934 #endif /* __GNUC__ */
935 uint32_t tickstart;
936
937 if ((pData == NULL) || (Size == 0UL))
938 {
939 return HAL_ERROR;
940 }
941
942 if (hi2s->State != HAL_I2S_STATE_READY)
943 {
944 return HAL_BUSY;
945 }
946
947 /* Process Locked */
948 __HAL_LOCK(hi2s);
949
950 /* Init tickstart for timeout management*/
951 tickstart = HAL_GetTick();
952
953 /* Set state and reset error code */
954 hi2s->State = HAL_I2S_STATE_BUSY_RX;
955 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
956 hi2s->pRxBuffPtr = pData;
957 hi2s->RxXferSize = Size;
958 hi2s->RxXferCount = Size;
959
960 /* Initialize fields not used in handle to zero */
961 hi2s->pTxBuffPtr = NULL;
962 hi2s->TxXferSize = (uint16_t) 0UL;
963 hi2s->TxXferCount = (uint16_t) 0UL;
964
965 /* Check if the I2S is already enabled */
966 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
967 {
968 /* Enable I2S peripheral */
969 __HAL_I2S_ENABLE(hi2s);
970 }
971
972 /* Start the transfer */
973 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
974
975 /* Receive data */
976 while (hi2s->RxXferCount > 0UL)
977 {
978 /* Wait until RXP flag is set */
979 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXP, SET, tickstart, Timeout) != HAL_OK)
980 {
981 /* Set the error code */
982 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
983 hi2s->State = HAL_I2S_STATE_READY;
984 __HAL_UNLOCK(hi2s);
985 return HAL_TIMEOUT;
986 }
987
988 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
989 {
990 /* Receive data in 32 Bit mode */
991 *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
992 hi2s->pRxBuffPtr += 2;
993 hi2s->RxXferCount--;
994 }
995 else
996 {
997 /* Receive data in 16 Bit mode */
998 #if defined (__GNUC__)
999 *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
1000 #else
1001 *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
1002 #endif /* __GNUC__ */
1003 hi2s->pRxBuffPtr++;
1004 hi2s->RxXferCount--;
1005 }
1006
1007 /* Check if an overrun occurs */
1008 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
1009 {
1010 /* Clear overrun flag */
1011 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1012
1013 /* Set the error code */
1014 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
1015 }
1016 }
1017
1018 hi2s->State = HAL_I2S_STATE_READY;
1019 __HAL_UNLOCK(hi2s);
1020 return HAL_OK;
1021 }
1022
1023 /**
1024 * @brief Full-Duplex Transmit/Receive data in blocking mode.
1025 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1026 * the configuration information for I2S module
1027 * @param pTxData a 16-bit pointer to the Transmit data buffer.
1028 * @param pRxData a 16-bit pointer to the Receive data buffer.
1029 * @param Size number of data sample to be sent:
1030 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1031 * configuration phase, the Size parameter means the number of 16-bit data length
1032 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1033 * the Size parameter means the number of 16-bit data length.
1034 * @param Timeout Timeout duration
1035 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1036 * between Master and Slave(example: audio streaming).
1037 * @retval HAL status
1038 */
1039
HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef * hi2s,const uint16_t * pTxData,uint16_t * pRxData,uint16_t Size,uint32_t Timeout)1040 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
1041 uint16_t Size, uint32_t Timeout)
1042 {
1043 uint32_t tmp_TxXferCount;
1044 uint32_t tmp_RxXferCount;
1045 uint32_t tickstart;
1046
1047 #if defined (__GNUC__)
1048 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
1049 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
1050 #endif /* __GNUC__ */
1051
1052 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1053 {
1054 return HAL_ERROR;
1055 }
1056
1057 if (hi2s->State != HAL_I2S_STATE_READY)
1058 {
1059 return HAL_BUSY;
1060 }
1061
1062 /* Process Locked */
1063 __HAL_LOCK(hi2s);
1064
1065 /* Init tickstart for timeout management*/
1066 tickstart = HAL_GetTick();
1067
1068 hi2s->TxXferSize = Size;
1069 hi2s->TxXferCount = Size;
1070 hi2s->pTxBuffPtr = (const uint16_t *)pTxData;
1071 hi2s->RxXferSize = Size;
1072 hi2s->RxXferCount = Size;
1073 hi2s->pRxBuffPtr = pRxData;
1074
1075 tmp_TxXferCount = hi2s->TxXferCount;
1076 tmp_RxXferCount = hi2s->RxXferCount;
1077
1078 /* Set state and reset error code */
1079 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1080 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
1081
1082 /* Check if the I2S is already enabled */
1083 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1084 {
1085 /* Enable I2S peripheral */
1086 __HAL_I2S_ENABLE(hi2s);
1087 }
1088
1089 /* Start the transfer */
1090 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1091
1092 while ((tmp_TxXferCount > 0UL) || (tmp_RxXferCount > 0UL))
1093 {
1094 if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXP) == SET) && (tmp_TxXferCount != 0UL))
1095 {
1096 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1097 {
1098 /* Transmit data in 32 Bit mode */
1099 hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr);
1100 hi2s->pTxBuffPtr += 2;
1101 tmp_TxXferCount--;
1102 }
1103 else
1104 {
1105 /* Transmit data in 16 Bit mode */
1106 #if defined (__GNUC__)
1107 *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr);
1108 #else
1109 *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr);
1110 #endif /* __GNUC__ */
1111
1112 hi2s->pTxBuffPtr++;
1113 tmp_TxXferCount--;
1114 }
1115
1116 /* Check if an underrun occurs */
1117 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
1118 {
1119 /* Clear underrun flag */
1120 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
1121
1122 /* Set the error code */
1123 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
1124 }
1125 }
1126
1127 if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXP) == SET) && (tmp_RxXferCount != 0UL))
1128 {
1129 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1130 {
1131 /* Receive data in 32 Bit mode */
1132 *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
1133 hi2s->pRxBuffPtr += 2;
1134 tmp_RxXferCount--;
1135 }
1136 else
1137 {
1138 /* Receive data in 16 Bit mode */
1139 #if defined (__GNUC__)
1140 *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
1141 #else
1142 *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
1143 #endif /* __GNUC__ */
1144 hi2s->pRxBuffPtr++;
1145 tmp_RxXferCount--;
1146 }
1147
1148 /* Check if an overrun occurs */
1149 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
1150 {
1151 /* Clear overrun flag */
1152 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1153
1154 /* Set the error code */
1155 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
1156 }
1157 }
1158
1159 /* Timeout management */
1160 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1161 {
1162 /* Set the error code */
1163 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
1164 hi2s->State = HAL_I2S_STATE_READY;
1165 __HAL_UNLOCK(hi2s);
1166 return HAL_TIMEOUT;
1167 }
1168 }
1169
1170 hi2s->State = HAL_I2S_STATE_READY;
1171 __HAL_UNLOCK(hi2s);
1172 return HAL_OK;
1173 }
1174
1175 /**
1176 * @brief Transmit an amount of data in non-blocking mode with Interrupt
1177 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1178 * the configuration information for I2S module
1179 * @param pData a 16-bit pointer to data buffer.
1180 * @param Size number of data sample to be sent:
1181 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1182 * configuration phase, the Size parameter means the number of 16-bit data length
1183 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1184 * the Size parameter means the number of 16-bit data length.
1185 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1186 * between Master and Slave(example: audio streaming).
1187 * @retval HAL status
1188 */
HAL_I2S_Transmit_IT(I2S_HandleTypeDef * hi2s,const uint16_t * pData,uint16_t Size)1189 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size)
1190 {
1191 if ((pData == NULL) || (Size == 0UL))
1192 {
1193 return HAL_ERROR;
1194 }
1195
1196 if (hi2s->State != HAL_I2S_STATE_READY)
1197 {
1198 return HAL_BUSY;
1199 }
1200
1201 /* Process Locked */
1202 __HAL_LOCK(hi2s);
1203
1204 /* Set state and reset error code */
1205 hi2s->State = HAL_I2S_STATE_BUSY_TX;
1206 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1207 hi2s->pTxBuffPtr = (const uint16_t *)pData;
1208 hi2s->TxXferSize = Size;
1209 hi2s->TxXferCount = Size;
1210
1211 /* Initialize fields not used in handle to zero */
1212 hi2s->pRxBuffPtr = NULL;
1213 hi2s->RxXferSize = (uint16_t) 0UL;
1214 hi2s->RxXferCount = (uint16_t) 0UL;
1215
1216 /* Set the function for IT treatment */
1217 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1218 {
1219 hi2s->TxISR = I2S_Transmit_32Bit_IT;
1220 }
1221 else
1222 {
1223 hi2s->TxISR = I2S_Transmit_16Bit_IT;
1224 }
1225
1226 /* Check if the I2S is already enabled */
1227 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1228 {
1229 /* Enable I2S peripheral */
1230 __HAL_I2S_ENABLE(hi2s);
1231 }
1232
1233 /* Enable TXP and UDR interrupt */
1234 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_UDR));
1235
1236 /* Enable TIFRE interrupt if the mode is Slave */
1237 if (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)
1238 {
1239 __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
1240 }
1241
1242 /* Start the transfer */
1243 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1244
1245 __HAL_UNLOCK(hi2s);
1246 return HAL_OK;
1247 }
1248
1249 /**
1250 * @brief Receive an amount of data in non-blocking mode with Interrupt
1251 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1252 * the configuration information for I2S module
1253 * @param pData a 16-bit pointer to the Receive data buffer.
1254 * @param Size number of data sample to be sent:
1255 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1256 * configuration phase, the Size parameter means the number of 16-bit data length
1257 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1258 * the Size parameter means the number of 16-bit data length.
1259 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1260 * between Master and Slave(example: audio streaming).
1261 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
1262 * between Master and Slave otherwise the I2S interrupt should be optimized.
1263 * @retval HAL status
1264 */
HAL_I2S_Receive_IT(I2S_HandleTypeDef * hi2s,uint16_t * pData,uint16_t Size)1265 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1266 {
1267 if ((pData == NULL) || (Size == 0UL))
1268 {
1269 return HAL_ERROR;
1270 }
1271
1272 if (hi2s->State != HAL_I2S_STATE_READY)
1273 {
1274 return HAL_BUSY;
1275 }
1276
1277 /* Process Locked */
1278 __HAL_LOCK(hi2s);
1279
1280 /* Set state and reset error code */
1281 hi2s->State = HAL_I2S_STATE_BUSY_RX;
1282 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1283 hi2s->pRxBuffPtr = pData;
1284 hi2s->RxXferSize = Size;
1285 hi2s->RxXferCount = Size;
1286
1287 /* Initialize fields not used in handle to zero */
1288 hi2s->pTxBuffPtr = NULL;
1289 hi2s->TxXferSize = (uint16_t) 0UL;
1290 hi2s->TxXferCount = (uint16_t) 0UL;
1291
1292 /* Set the function for IT treatment */
1293 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1294 {
1295 hi2s->RxISR = I2S_Receive_32Bit_IT;
1296 }
1297 else
1298 {
1299 hi2s->RxISR = I2S_Receive_16Bit_IT;
1300 }
1301
1302 /* Check if the I2S is already enabled */
1303 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1304 {
1305 /* Enable I2S peripheral */
1306 __HAL_I2S_ENABLE(hi2s);
1307 }
1308 /* Enable RXP and ERR interrupt */
1309 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_OVR));
1310
1311 /* Enable TIFRE interrupt if the mode is Slave */
1312 if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
1313 {
1314 __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
1315 }
1316
1317 /* Start the transfer */
1318 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1319
1320 __HAL_UNLOCK(hi2s);
1321 return HAL_OK;
1322 }
1323
1324 /**
1325 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
1326 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1327 * the configuration information for I2S module
1328 * @param pTxData a 16-bit pointer to the Transmit data buffer.
1329 * @param pRxData a 16-bit pointer to the Receive data buffer.
1330 * @param Size number of data sample to be sent:
1331 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1332 * configuration phase, the Size parameter means the number of 16-bit data length
1333 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1334 * the Size parameter means the number of 16-bit data length.
1335 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1336 * between Master and Slave(example: audio streaming).
1337 * @retval HAL status
1338 */
HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef * hi2s,const uint16_t * pTxData,uint16_t * pRxData,uint16_t Size)1339 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
1340 uint16_t Size)
1341 {
1342 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1343 {
1344 return HAL_ERROR;
1345 }
1346
1347 if (hi2s->State != HAL_I2S_STATE_READY)
1348 {
1349 return HAL_BUSY;
1350 }
1351
1352 /* Process Locked */
1353 __HAL_LOCK(hi2s);
1354
1355 hi2s->pTxBuffPtr = (const uint16_t *)pTxData;
1356 hi2s->pRxBuffPtr = pRxData;
1357
1358 hi2s->TxXferSize = Size;
1359 hi2s->TxXferCount = Size;
1360 hi2s->RxXferSize = Size;
1361 hi2s->RxXferCount = Size;
1362
1363 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1364 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
1365
1366
1367 /* Set the function for IT treatment */
1368 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
1369 {
1370 hi2s->TxISR = I2S_Transmit_32Bit_IT;
1371 hi2s->RxISR = I2S_Receive_32Bit_IT;
1372 }
1373 else
1374 {
1375 hi2s->TxISR = I2S_Transmit_16Bit_IT;
1376 hi2s->RxISR = I2S_Receive_16Bit_IT;
1377 }
1378
1379 /* Check if the I2S is already enabled */
1380 if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1381 {
1382 /* Enable I2S peripheral */
1383 __HAL_I2S_ENABLE(hi2s);
1384 }
1385
1386 /* Enable TXP, RXP, DXP, UDR, OVR interrupts */
1387 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_UDR | I2S_IT_OVR));
1388
1389 /* Enable TIFRE interrupt if the mode is Slave */
1390 if (hi2s->Init.Mode == I2S_MODE_SLAVE_FULLDUPLEX)
1391 {
1392 __HAL_I2S_ENABLE_IT(hi2s, I2S_IT_FRE);
1393 }
1394
1395 /* Start the transfer */
1396 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1397
1398 __HAL_UNLOCK(hi2s);
1399 return HAL_OK;
1400
1401 }
1402
1403 /**
1404 * @brief Transmit an amount of data in non-blocking mode with DMA
1405 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1406 * the configuration information for I2S module
1407 * @param pData a 16-bit pointer to the Transmit data buffer.
1408 * @param Size number of data sample to be sent:
1409 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1410 * configuration phase, the Size parameter means the number of 16-bit data length
1411 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1412 * the Size parameter means the number of 16-bit data length.
1413 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1414 * between Master and Slave(example: audio streaming).
1415 * @retval HAL status
1416 */
HAL_I2S_Transmit_DMA(I2S_HandleTypeDef * hi2s,const uint16_t * pData,uint16_t Size)1417 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size)
1418 {
1419 HAL_StatusTypeDef errorcode;
1420
1421 if ((pData == NULL) || (Size == 0UL))
1422 {
1423 return HAL_ERROR;
1424 }
1425
1426 if (hi2s->State != HAL_I2S_STATE_READY)
1427 {
1428 return HAL_BUSY;
1429 }
1430
1431 /* Process Locked */
1432 __HAL_LOCK(hi2s);
1433
1434 /* Set state and reset error code */
1435 hi2s->State = HAL_I2S_STATE_BUSY_TX;
1436 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1437 hi2s->pTxBuffPtr = (const uint16_t *)pData;
1438 hi2s->TxXferSize = Size;
1439 hi2s->TxXferCount = Size;
1440
1441 /* Init field not used in handle to zero */
1442 hi2s->pRxBuffPtr = NULL;
1443 hi2s->RxXferSize = (uint16_t)0UL;
1444 hi2s->RxXferCount = (uint16_t)0UL;
1445
1446 /* Set the I2S Tx DMA Half transfer complete callback */
1447 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
1448
1449 /* Set the I2S Tx DMA transfer complete callback */
1450 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
1451
1452 /* Set the DMA error callback */
1453 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
1454
1455 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED))
1456 {
1457 hi2s->TxXferCount = Size * 2U;
1458 }
1459 else
1460 {
1461 hi2s->TxXferCount = Size * 4U;
1462 }
1463
1464 /* Enable the Tx DMA Stream/Channel */
1465 if ((hi2s->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1466 {
1467 if (hi2s->hdmatx->LinkedListQueue != NULL)
1468 {
1469 /* Set DMA data size */
1470 hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->TxXferCount;
1471
1472 /* Set DMA source address */
1473 hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pTxBuffPtr;
1474
1475 /* Set DMA destination address */
1476 hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->TXDR;
1477
1478 errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmatx);
1479 }
1480 else
1481 {
1482 /* Update SPI error code */
1483 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1484
1485 /* Unlock the process */
1486 __HAL_UNLOCK(hi2s);
1487
1488 hi2s->State = HAL_I2S_STATE_READY;
1489 errorcode = HAL_ERROR;
1490 return errorcode;
1491 }
1492 }
1493 else
1494 {
1495 errorcode = HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR,
1496 hi2s->TxXferCount);
1497 }
1498
1499 /* Check status */
1500 if (errorcode != HAL_OK)
1501 {
1502 /* Update I2S error code */
1503 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1504 hi2s->State = HAL_I2S_STATE_READY;
1505
1506 __HAL_UNLOCK(hi2s);
1507 errorcode = HAL_ERROR;
1508 return errorcode;
1509 }
1510
1511 /* Check if the I2S Tx request is already enabled */
1512 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
1513 {
1514 /* Enable Tx DMA Request */
1515 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
1516 }
1517
1518 /* Check if the I2S is already enabled */
1519 if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
1520 {
1521 /* Enable I2S peripheral */
1522 __HAL_I2S_ENABLE(hi2s);
1523 }
1524
1525 /* Start the transfer */
1526 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1527
1528 __HAL_UNLOCK(hi2s);
1529 return errorcode;
1530 }
1531
1532 /**
1533 * @brief Receive an amount of data in non-blocking mode with DMA
1534 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1535 * the configuration information for I2S module
1536 * @param pData a 16-bit pointer to the Receive data buffer.
1537 * @param Size number of data sample to be sent:
1538 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1539 * configuration phase, the Size parameter means the number of 16-bit data length
1540 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1541 * the Size parameter means the number of 16-bit data length.
1542 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1543 * between Master and Slave(example: audio streaming).
1544 * @retval HAL status
1545 */
HAL_I2S_Receive_DMA(I2S_HandleTypeDef * hi2s,uint16_t * pData,uint16_t Size)1546 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1547 {
1548 HAL_StatusTypeDef errorcode;
1549
1550 if ((pData == NULL) || (Size == 0UL))
1551 {
1552 return HAL_ERROR;
1553 }
1554
1555 if (hi2s->State != HAL_I2S_STATE_READY)
1556 {
1557 return HAL_BUSY;
1558 }
1559
1560 /* Process Locked */
1561 __HAL_LOCK(hi2s);
1562
1563 /* Set state and reset error code */
1564 hi2s->State = HAL_I2S_STATE_BUSY_RX;
1565 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1566 hi2s->pRxBuffPtr = pData;
1567 hi2s->RxXferSize = Size;
1568 hi2s->RxXferCount = Size;
1569
1570 /* Init field not used in handle to zero */
1571 hi2s->pTxBuffPtr = NULL;
1572 hi2s->TxXferSize = (uint16_t)0UL;
1573 hi2s->TxXferCount = (uint16_t)0UL;
1574
1575
1576 /* Set the I2S Rx DMA Half transfer complete callback */
1577 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
1578
1579 /* Set the I2S Rx DMA transfer complete callback */
1580 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
1581
1582 /* Set the DMA error callback */
1583 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
1584
1585 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED))
1586 {
1587 hi2s->RxXferCount = Size * 2U;
1588 }
1589 else
1590 {
1591 hi2s->RxXferCount = Size * 4U;
1592 }
1593
1594 /* Enable the Rx DMA Stream/Channel */
1595 if ((hi2s->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1596 {
1597 if (hi2s->hdmarx->LinkedListQueue != NULL)
1598 {
1599 /* Set DMA data size */
1600 hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->RxXferCount;
1601
1602 /* Set DMA source address */
1603 hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->RXDR;
1604
1605 /* Set DMA destination address */
1606 hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pRxBuffPtr;
1607
1608 errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmarx);
1609 }
1610 else
1611 {
1612 /* Update SPI error code */
1613 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1614
1615 /* Unlock the process */
1616 __HAL_UNLOCK(hi2s);
1617
1618 hi2s->State = HAL_I2S_STATE_READY;
1619 errorcode = HAL_ERROR;
1620 return errorcode;
1621 }
1622 }
1623 else
1624 {
1625 errorcode = HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr,
1626 hi2s->RxXferCount);
1627 }
1628
1629 /* Check status */
1630 if (errorcode != HAL_OK)
1631 {
1632 /* Update I2S error code */
1633 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1634 hi2s->State = HAL_I2S_STATE_READY;
1635 errorcode = HAL_ERROR;
1636 __HAL_UNLOCK(hi2s);
1637 return errorcode;
1638 }
1639
1640 /* Check if the I2S Rx request is already enabled */
1641 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
1642 {
1643 /* Enable Rx DMA Request */
1644 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
1645 }
1646
1647 /* Check if the I2S is already enabled */
1648 if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
1649 {
1650 /* Enable I2S peripheral */
1651 __HAL_I2S_ENABLE(hi2s);
1652 }
1653
1654 /* Start the transfer */
1655 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1656
1657 __HAL_UNLOCK(hi2s);
1658 return errorcode;
1659 }
1660
1661 /**
1662 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
1663 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1664 * the configuration information for I2S module
1665 * @param pTxData a 16-bit pointer to the Transmit data buffer.
1666 * @param pRxData a 16-bit pointer to the Receive data buffer.
1667 * @param Size number of data sample to be sent:
1668 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1669 * configuration phase, the Size parameter means the number of 16-bit data length
1670 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1671 * the Size parameter means the number of 16-bit data length.
1672 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1673 * between Master and Slave(example: audio streaming).
1674 * @retval HAL status
1675 */
HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef * hi2s,const uint16_t * pTxData,uint16_t * pRxData,uint16_t Size)1676 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
1677 uint16_t Size)
1678 {
1679 HAL_StatusTypeDef errorcode;
1680
1681
1682 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1683 {
1684 return HAL_ERROR;
1685 }
1686
1687 if (hi2s->State != HAL_I2S_STATE_READY)
1688 {
1689 return HAL_BUSY;
1690 }
1691
1692 /* Process Locked */
1693 __HAL_LOCK(hi2s);
1694
1695 hi2s->pTxBuffPtr = (const uint16_t *)pTxData;
1696 hi2s->pRxBuffPtr = pRxData;
1697
1698 hi2s->TxXferSize = Size;
1699 hi2s->TxXferCount = Size;
1700 hi2s->RxXferSize = Size;
1701 hi2s->RxXferCount = Size;
1702
1703 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1704 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
1705
1706 /* Reset the Tx/Rx DMA bits */
1707 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
1708
1709 /* Set the I2S Rx DMA Half transfer complete callback */
1710 hi2s->hdmarx->XferHalfCpltCallback = I2SEx_DMATxRxHalfCplt;
1711
1712 /* Set the I2S Rx DMA transfer complete callback */
1713 hi2s->hdmarx->XferCpltCallback = I2SEx_DMATxRxCplt;
1714
1715 /* Set the I2S Rx DMA error callback */
1716 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
1717 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED))
1718 {
1719 hi2s->TxXferCount = Size * 2U;
1720 }
1721 else
1722 {
1723 hi2s->TxXferCount = Size * 4U;
1724 }
1725
1726 /* Enable the Tx DMA Stream/Channel */
1727 if ((hi2s->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1728 {
1729 if (hi2s->hdmatx->LinkedListQueue != NULL)
1730 {
1731 /* Set DMA data size */
1732 hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->TxXferCount;
1733
1734 /* Set DMA source address */
1735 hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pTxBuffPtr;
1736
1737 /* Set DMA destination address */
1738 hi2s->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->TXDR;
1739
1740 errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmatx);
1741 }
1742 else
1743 {
1744 /* Update SPI error code */
1745 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1746
1747 /* Unlock the process */
1748 __HAL_UNLOCK(hi2s);
1749
1750 hi2s->State = HAL_I2S_STATE_READY;
1751 errorcode = HAL_ERROR;
1752 return errorcode;
1753 }
1754 }
1755 else
1756 {
1757 errorcode = HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR,
1758 hi2s->TxXferCount);
1759 }
1760
1761 /* Check status */
1762 if (errorcode != HAL_OK)
1763 {
1764 /* Update I2S error code */
1765 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1766 hi2s->State = HAL_I2S_STATE_READY;
1767
1768 __HAL_UNLOCK(hi2s);
1769 errorcode = HAL_ERROR;
1770 return errorcode;
1771 }
1772
1773 /* Check if the I2S Tx request is already enabled */
1774 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN))
1775 {
1776 /* Enable Tx DMA Request */
1777 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
1778 }
1779
1780 if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B_EXTENDED))
1781 {
1782 hi2s->RxXferCount = Size * 2U;
1783 }
1784 else
1785 {
1786 hi2s->RxXferCount = Size * 4U;
1787 }
1788
1789 /* Enable the Rx DMA Stream/Channel */
1790 if ((hi2s->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1791 {
1792 if (hi2s->hdmarx->LinkedListQueue != NULL)
1793 {
1794 /* Set DMA data size */
1795 hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2s->RxXferCount;
1796
1797 /* Set DMA source address */
1798 hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2s->Instance->RXDR;
1799
1800 /* Set DMA destination address */
1801 hi2s->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2s->pRxBuffPtr;
1802
1803 errorcode = HAL_DMAEx_List_Start_IT(hi2s->hdmarx);
1804 }
1805 else
1806 {
1807 /* Update SPI error code */
1808 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1809
1810 /* Unlock the process */
1811 __HAL_UNLOCK(hi2s);
1812
1813 hi2s->State = HAL_I2S_STATE_READY;
1814 errorcode = HAL_ERROR;
1815 return errorcode;
1816 }
1817 }
1818 else
1819 {
1820 errorcode = HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr,
1821 hi2s->RxXferCount);
1822 }
1823
1824 /* Check status */
1825 if (errorcode != HAL_OK)
1826 {
1827 /* Update I2S error code */
1828 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1829 hi2s->State = HAL_I2S_STATE_READY;
1830 errorcode = HAL_ERROR;
1831 __HAL_UNLOCK(hi2s);
1832 return errorcode;
1833 }
1834
1835 /* Check if the I2S Rx request is already enabled */
1836 if (HAL_IS_BIT_CLR(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN))
1837 {
1838 /* Enable Rx DMA Request */
1839 SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
1840 }
1841
1842 /* Check if the I2S is already enabled */
1843 if (HAL_IS_BIT_CLR(hi2s->Instance->CR1, SPI_CR1_SPE))
1844 {
1845 /* Enable I2S peripheral */
1846 __HAL_I2S_ENABLE(hi2s);
1847 }
1848
1849 /* Start the transfer */
1850 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1851
1852 __HAL_UNLOCK(hi2s);
1853 return errorcode;
1854 }
1855
1856 /**
1857 * @brief Pauses the audio DMA Stream/Channel playing from the Media.
1858 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1859 * the configuration information for I2S module
1860 * @retval HAL status
1861 */
HAL_I2S_DMAPause(I2S_HandleTypeDef * hi2s)1862 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
1863 {
1864 /* Process Locked */
1865 __HAL_LOCK(hi2s);
1866
1867 uint32_t tickstart;
1868
1869 /* Get tick */
1870 tickstart = HAL_GetTick();
1871
1872
1873 /* Check if the I2S peripheral is in master mode */
1874 if (IS_I2S_MASTER(hi2s->Init.Mode))
1875 {
1876 /* Check if there is a transfer on-going */
1877 if (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) == 0UL)
1878 {
1879 /* Set error code to no on going transfer */
1880 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NO_OGT);
1881 hi2s->State = HAL_I2S_STATE_READY;
1882
1883 __HAL_UNLOCK(hi2s);
1884 return HAL_ERROR;
1885 }
1886
1887 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSUSP);
1888
1889 while (HAL_IS_BIT_SET(hi2s->Instance->CR1, SPI_CR1_CSTART) != 0UL)
1890 {
1891 if ((((HAL_GetTick() - tickstart) >= I2S_TIMEOUT) && (I2S_TIMEOUT != HAL_MAX_DELAY)) || (I2S_TIMEOUT == 0U))
1892 {
1893 /* Set the I2S State ready */
1894 hi2s->State = HAL_I2S_STATE_READY;
1895
1896 /* Process Unlocked */
1897 __HAL_UNLOCK(hi2s);
1898
1899 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
1900 hi2s->State = HAL_I2S_STATE_READY;
1901 return HAL_TIMEOUT;
1902 }
1903 }
1904
1905 /* Disable I2S peripheral */
1906 __HAL_I2S_DISABLE(hi2s);
1907
1908 hi2s->State = HAL_I2S_STATE_READY;
1909
1910 /* Process Unlocked */
1911 __HAL_UNLOCK(hi2s);
1912
1913 return HAL_OK;
1914 }
1915 else
1916 {
1917 /* Set error code to not supported */
1918 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_NOT_SUPPORTED);
1919 hi2s->State = HAL_I2S_STATE_READY;
1920
1921 /* Process Unlocked */
1922 __HAL_UNLOCK(hi2s);
1923
1924 return HAL_ERROR;
1925 }
1926 }
1927
1928 /**
1929 * @brief Resumes the audio DMA Stream/Channel playing from the Media.
1930 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1931 * the configuration information for I2S module
1932 * @retval HAL status
1933 */
HAL_I2S_DMAResume(I2S_HandleTypeDef * hi2s)1934 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
1935 {
1936 /* Process Locked */
1937 __HAL_LOCK(hi2s);
1938
1939 if (hi2s->State != HAL_I2S_STATE_READY)
1940 {
1941 hi2s->State = HAL_I2S_STATE_READY;
1942
1943 __HAL_UNLOCK(hi2s);
1944 return HAL_ERROR;
1945 }
1946
1947 /* Set state and reset error code */
1948 hi2s->State = HAL_I2S_STATE_BUSY;
1949 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1950
1951 /* Enable I2S peripheral */
1952 __HAL_I2S_ENABLE(hi2s);
1953
1954 /* Start the transfer */
1955 SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
1956
1957 /* Process Unlocked */
1958 __HAL_UNLOCK(hi2s);
1959
1960 return HAL_OK;
1961 }
1962
1963 /**
1964 * @brief Stops the audio DMA Stream/Channel playing from the Media.
1965 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1966 * the configuration information for I2S module
1967 * @retval HAL status
1968 */
HAL_I2S_DMAStop(I2S_HandleTypeDef * hi2s)1969 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
1970 {
1971 HAL_StatusTypeDef errorcode = HAL_OK;
1972 /* The Lock is not implemented on this API to allow the user application
1973 to call the HAL I2S API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
1974 when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
1975 and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
1976 */
1977
1978 /* Disable the I2S Tx/Rx DMA requests */
1979 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
1980 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
1981
1982 /* Abort the I2S DMA tx Stream/Channel */
1983 if (hi2s->hdmatx != NULL)
1984 {
1985 /* Disable the I2S DMA tx Stream/Channel */
1986 if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
1987 {
1988 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1989 errorcode = HAL_ERROR;
1990 }
1991 }
1992
1993 /* Abort the I2S DMA rx Stream/Channel */
1994 if (hi2s->hdmarx != NULL)
1995 {
1996 /* Disable the I2S DMA rx Stream/Channel */
1997 if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
1998 {
1999 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
2000 errorcode = HAL_ERROR;
2001 }
2002 }
2003
2004 /* Disable I2S peripheral */
2005 __HAL_I2S_DISABLE(hi2s);
2006
2007 hi2s->State = HAL_I2S_STATE_READY;
2008
2009 return errorcode;
2010 }
2011
2012 /**
2013 * @brief This function handles I2S interrupt request.
2014 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2015 * the configuration information for I2S module
2016 * @retval None
2017 */
HAL_I2S_IRQHandler(I2S_HandleTypeDef * hi2s)2018 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
2019 {
2020 uint32_t i2sier = hi2s->Instance->IER;
2021 uint32_t i2ssr = hi2s->Instance->SR;
2022 uint32_t trigger = i2sier & i2ssr;
2023
2024 if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
2025 {
2026 /* I2S in mode Receiver ------------------------------------------------*/
2027 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_OVR))
2028 {
2029 hi2s->RxISR(hi2s);
2030 }
2031
2032 /* I2S Overrun error interrupt occurred -------------------------------------*/
2033 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_OVR))
2034 {
2035 /* Disable RXP and ERR interrupt */
2036 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
2037
2038 /* Clear Overrun flag */
2039 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
2040
2041 /* Set the I2S State ready */
2042 hi2s->State = HAL_I2S_STATE_READY;
2043
2044
2045 /* Set the error code and execute error callback*/
2046 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
2047 /* Call user error callback */
2048 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2049 hi2s->ErrorCallback(hi2s);
2050 #else
2051 HAL_I2S_ErrorCallback(hi2s);
2052 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2053 }
2054 }
2055
2056 if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
2057 {
2058 /* I2S in mode Transmitter -----------------------------------------------*/
2059 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_UDR))
2060 {
2061 hi2s->TxISR(hi2s);
2062 }
2063
2064 /* I2S Underrun error interrupt occurred --------------------------------*/
2065 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_UDR))
2066 {
2067 /* Disable TXP and ERR interrupt */
2068 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
2069
2070 /* Clear Underrun flag */
2071 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
2072
2073 /* Set the I2S State ready */
2074 hi2s->State = HAL_I2S_STATE_READY;
2075
2076 /* Set the error code and execute error callback*/
2077 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
2078 /* Call user error callback */
2079 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2080 hi2s->ErrorCallback(hi2s);
2081 #else
2082 HAL_I2S_ErrorCallback(hi2s);
2083 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2084 }
2085 }
2086 if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
2087 {
2088 /* I2S in mode Transmitter -----------------------------------------------*/
2089 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_DXP))
2090 {
2091 hi2s->TxISR(hi2s);
2092 hi2s->RxISR(hi2s);
2093 }
2094 /* I2S in mode Receiver ------------------------------------------------*/
2095 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_DXP))
2096 {
2097 hi2s->RxISR(hi2s);
2098 }
2099 /* I2S in mode Transmitter -----------------------------------------------*/
2100 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, I2S_FLAG_DXP))
2101 {
2102 hi2s->TxISR(hi2s);
2103 }
2104
2105 /* I2S Underrun error interrupt occurred --------------------------------*/
2106 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_UDR))
2107 {
2108 /* Disable TXP, RXP and ERR interrupt */
2109 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_ERR));
2110
2111 /* Clear Underrun flag */
2112 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
2113
2114 /* Set the I2S State ready */
2115 hi2s->State = HAL_I2S_STATE_READY;
2116
2117 /* Set the error code and execute error callback*/
2118 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
2119 /* Call user error callback */
2120 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2121 hi2s->ErrorCallback(hi2s);
2122 #else
2123 HAL_I2S_ErrorCallback(hi2s);
2124 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2125 }
2126
2127 /* I2S Overrun error interrupt occurred -------------------------------------*/
2128 if (HAL_IS_BIT_SET(trigger, I2S_FLAG_OVR))
2129 {
2130 /* Disable TXP, RXP and ERR interrupt */
2131 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_ERR));
2132
2133 /* Clear Overrun flag */
2134 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
2135
2136 /* Set the I2S State ready */
2137 hi2s->State = HAL_I2S_STATE_READY;
2138
2139
2140 /* Set the error code and execute error callback*/
2141 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
2142
2143 /* Call user error callback */
2144 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2145 hi2s->ErrorCallback(hi2s);
2146 #else
2147 HAL_I2S_ErrorCallback(hi2s);
2148 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2149 }
2150 }
2151 }
2152
2153 /**
2154 * @brief Tx Transfer Half completed callbacks
2155 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2156 * the configuration information for I2S module
2157 * @retval None
2158 */
HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef * hi2s)2159 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
2160 {
2161 /* Prevent unused argument(s) compilation warning */
2162 UNUSED(hi2s);
2163
2164 /* NOTE : This function Should not be modified, when the callback is needed,
2165 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
2166 */
2167 }
2168
2169 /**
2170 * @brief Tx Transfer completed callbacks
2171 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2172 * the configuration information for I2S module
2173 * @retval None
2174 */
HAL_I2S_TxCpltCallback(I2S_HandleTypeDef * hi2s)2175 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
2176 {
2177 /* Prevent unused argument(s) compilation warning */
2178 UNUSED(hi2s);
2179
2180 /* NOTE : This function Should not be modified, when the callback is needed,
2181 the HAL_I2S_TxCpltCallback could be implemented in the user file
2182 */
2183 }
2184
2185 /**
2186 * @brief Rx Transfer half completed callbacks
2187 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2188 * the configuration information for I2S module
2189 * @retval None
2190 */
HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef * hi2s)2191 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
2192 {
2193 /* Prevent unused argument(s) compilation warning */
2194 UNUSED(hi2s);
2195
2196 /* NOTE : This function Should not be modified, when the callback is needed,
2197 the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
2198 */
2199 }
2200
2201 /**
2202 * @brief Rx Transfer completed callbacks
2203 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2204 * the configuration information for I2S module
2205 * @retval None
2206 */
HAL_I2S_RxCpltCallback(I2S_HandleTypeDef * hi2s)2207 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
2208 {
2209 /* Prevent unused argument(s) compilation warning */
2210 UNUSED(hi2s);
2211
2212 /* NOTE : This function Should not be modified, when the callback is needed,
2213 the HAL_I2S_RxCpltCallback could be implemented in the user file
2214 */
2215 }
2216
2217 /**
2218 * @brief Rx Transfer half completed callbacks
2219 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2220 * the configuration information for I2S module
2221 * @retval None
2222 */
HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef * hi2s)2223 __weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
2224 {
2225 /* Prevent unused argument(s) compilation warning */
2226 UNUSED(hi2s);
2227
2228 /* NOTE : This function Should not be modified, when the callback is needed,
2229 the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
2230 */
2231 }
2232
2233 /**
2234 * @brief Rx Transfer completed callbacks
2235 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2236 * the configuration information for I2S module
2237 * @retval None
2238 */
HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef * hi2s)2239 __weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
2240 {
2241 /* Prevent unused argument(s) compilation warning */
2242 UNUSED(hi2s);
2243
2244 /* NOTE : This function Should not be modified, when the callback is needed,
2245 the HAL_I2S_RxCpltCallback could be implemented in the user file
2246 */
2247 }
2248
2249 /**
2250 * @brief I2S error callbacks
2251 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2252 * the configuration information for I2S module
2253 * @retval None
2254 */
HAL_I2S_ErrorCallback(I2S_HandleTypeDef * hi2s)2255 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
2256 {
2257 /* Prevent unused argument(s) compilation warning */
2258 UNUSED(hi2s);
2259
2260 /* NOTE : This function Should not be modified, when the callback is needed,
2261 the HAL_I2S_ErrorCallback could be implemented in the user file
2262 */
2263 }
2264
2265 /**
2266 * @}
2267 */
2268
2269 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
2270 * @brief Peripheral State functions
2271 *
2272 @verbatim
2273 ===============================================================================
2274 ##### Peripheral State and Errors functions #####
2275 ===============================================================================
2276 [..]
2277 This subsection permits to get in run-time the status of the peripheral
2278 and the data flow.
2279
2280 @endverbatim
2281 * @{
2282 */
2283
2284 /**
2285 * @brief Return the I2S state
2286 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2287 * the configuration information for I2S module
2288 * @retval HAL state
2289 */
HAL_I2S_GetState(const I2S_HandleTypeDef * hi2s)2290 HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s)
2291 {
2292 return hi2s->State;
2293 }
2294
2295 /**
2296 * @brief Return the I2S error code
2297 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2298 * the configuration information for I2S module
2299 * @retval I2S Error Code
2300 */
HAL_I2S_GetError(const I2S_HandleTypeDef * hi2s)2301 uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s)
2302 {
2303 return hi2s->ErrorCode;
2304 }
2305 /**
2306 * @}
2307 */
2308
2309 /**
2310 * @}
2311 */
2312
2313 /** @addtogroup I2S_Private_Functions
2314 * @{
2315 */
2316 /**
2317 * @brief DMA I2S transmit process complete callback
2318 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2319 * the configuration information for the specified DMA module.
2320 * @retval None
2321 */
I2S_DMATxCplt(DMA_HandleTypeDef * hdma)2322 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
2323 {
2324 /* Derogation MISRAC2012-Rule-11.5 */
2325 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2326
2327 /* if DMA is configured in DMA_NORMAL Mode */
2328 if (hdma->Init.Mode == DMA_NORMAL)
2329 {
2330 /* Disable Tx DMA Request */
2331 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
2332
2333 hi2s->TxXferCount = (uint16_t) 0UL;
2334 hi2s->State = HAL_I2S_STATE_READY;
2335 }
2336 /* Call user Tx complete callback */
2337 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2338 hi2s->TxCpltCallback(hi2s);
2339 #else
2340 HAL_I2S_TxCpltCallback(hi2s);
2341 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2342 }
2343
2344 /**
2345 * @brief DMA I2S transmit process half complete callback
2346 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2347 * the configuration information for the specified DMA module.
2348 * @retval None
2349 */
I2S_DMATxHalfCplt(DMA_HandleTypeDef * hdma)2350 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
2351 {
2352 /* Derogation MISRAC2012-Rule-11.5 */
2353 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2354
2355 /* Call user Tx half complete callback */
2356 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2357 hi2s->TxHalfCpltCallback(hi2s);
2358 #else
2359 HAL_I2S_TxHalfCpltCallback(hi2s);
2360 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2361 }
2362
2363 /**
2364 * @brief DMA I2S receive process complete callback
2365 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2366 * the configuration information for the specified DMA module.
2367 * @retval None
2368 */
I2S_DMARxCplt(DMA_HandleTypeDef * hdma)2369 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
2370 {
2371 /* Derogation MISRAC2012-Rule-11.5 */
2372 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2373
2374 /* if DMA is configured in DMA_NORMAL Mode */
2375 if (hdma->Init.Mode == DMA_NORMAL)
2376 {
2377 /* Disable Rx DMA Request */
2378 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
2379 hi2s->RxXferCount = (uint16_t)0UL;
2380 hi2s->State = HAL_I2S_STATE_READY;
2381 }
2382 /* Call user Rx complete callback */
2383 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2384 hi2s->RxCpltCallback(hi2s);
2385 #else
2386 HAL_I2S_RxCpltCallback(hi2s);
2387 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2388 }
2389
2390 /**
2391 * @brief DMA I2S receive process half complete callback
2392 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2393 * the configuration information for the specified DMA module.
2394 * @retval None
2395 */
I2S_DMARxHalfCplt(DMA_HandleTypeDef * hdma)2396 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
2397 {
2398 /* Derogation MISRAC2012-Rule-11.5 */
2399 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2400
2401 /* Call user Rx half complete callback */
2402 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2403 hi2s->RxHalfCpltCallback(hi2s);
2404 #else
2405 HAL_I2S_RxHalfCpltCallback(hi2s);
2406 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2407 }
2408
2409 /**
2410 * @brief DMA I2S transmit receive process complete callback
2411 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2412 * the configuration information for the specified DMA module.
2413 * @retval None
2414 */
I2SEx_DMATxRxCplt(DMA_HandleTypeDef * hdma)2415 static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma)
2416 {
2417 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2418
2419 /* if DMA is configured in DMA_NORMAL Mode */
2420 if (hdma->Init.Mode == DMA_NORMAL)
2421 {
2422 /* Disable Tx DMA Request */
2423 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
2424 hi2s->TxXferCount = (uint16_t) 0UL;
2425
2426 /* Disable Rx DMA Request */
2427 CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
2428 hi2s->RxXferCount = (uint16_t)0UL;
2429
2430 /* Updated HAL State */
2431 hi2s->State = HAL_I2S_STATE_READY;
2432 }
2433
2434 /* Call user TxRx complete callback */
2435 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
2436 hi2s->TxRxCpltCallback(hi2s);
2437 #else
2438 HAL_I2SEx_TxRxCpltCallback(hi2s);
2439 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2440 }
2441
2442 /**
2443 * @brief DMA I2S transmit receive process half complete callback
2444 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2445 * the configuration information for the specified DMA module.
2446 * @retval None
2447 */
I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef * hdma)2448 static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma)
2449 {
2450 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2451
2452 /* Call user TxRx Half complete callback */
2453 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
2454 hi2s->TxRxHalfCpltCallback(hi2s);
2455 #else
2456 HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
2457 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2458 }
2459
2460 /**
2461 * @brief DMA I2S communication error callback
2462 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2463 * the configuration information for the specified DMA module.
2464 * @retval None
2465 */
I2S_DMAError(DMA_HandleTypeDef * hdma)2466 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
2467 {
2468 /* Derogation MISRAC2012-Rule-11.5 */
2469 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2470
2471 /* Disable Rx and Tx DMA Request */
2472 CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
2473 hi2s->TxXferCount = (uint16_t) 0UL;
2474 hi2s->RxXferCount = (uint16_t) 0UL;
2475
2476 hi2s->State = HAL_I2S_STATE_READY;
2477
2478 /* Set the error code and execute error callback*/
2479 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
2480 /* Call user error callback */
2481 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2482 hi2s->ErrorCallback(hi2s);
2483 #else
2484 HAL_I2S_ErrorCallback(hi2s);
2485 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2486 }
2487
2488 /**
2489 * @brief Manage the transmission 16-bit in Interrupt context
2490 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2491 * the configuration information for I2S module
2492 * @retval None
2493 */
I2S_Transmit_16Bit_IT(I2S_HandleTypeDef * hi2s)2494 static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s)
2495 {
2496 /* Transmit data */
2497 #if defined (__GNUC__)
2498 __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
2499
2500 *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr);
2501 #else
2502 *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr);
2503 #endif /* __GNUC__ */
2504 hi2s->pTxBuffPtr++;
2505 hi2s->TxXferCount--;
2506
2507 if (hi2s->TxXferCount == 0UL)
2508 {
2509 /* Disable TXP and ERR interrupt */
2510 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
2511
2512 if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX))
2513 {
2514 hi2s->State = HAL_I2S_STATE_READY;
2515
2516 /* Call user Tx complete callback */
2517 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2518 hi2s->TxCpltCallback(hi2s);
2519 #else
2520 HAL_I2S_TxCpltCallback(hi2s);
2521 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2522 }
2523 }
2524 }
2525
2526 /**
2527 * @brief Manage the transmission 32-bit in Interrupt context
2528 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2529 * the configuration information for I2S module
2530 * @retval None
2531 */
I2S_Transmit_32Bit_IT(I2S_HandleTypeDef * hi2s)2532 static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s)
2533 {
2534 /* Transmit data */
2535 hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr);
2536 hi2s->pTxBuffPtr += 2;
2537 hi2s->TxXferCount--;
2538
2539 if (hi2s->TxXferCount == 0UL)
2540 {
2541 /* Disable TXP and ERR interrupt */
2542 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
2543
2544 if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX))
2545 {
2546 hi2s->State = HAL_I2S_STATE_READY;
2547
2548 /* Call user Tx complete callback */
2549 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2550 hi2s->TxCpltCallback(hi2s);
2551 #else
2552 HAL_I2S_TxCpltCallback(hi2s);
2553 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2554 }
2555 }
2556 }
2557
2558 /**
2559 * @brief Manage the reception 16-bit in Interrupt context
2560 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2561 * the configuration information for I2S module
2562 * @retval None
2563 */
I2S_Receive_16Bit_IT(I2S_HandleTypeDef * hi2s)2564 static void I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s)
2565 {
2566 /* Receive data */
2567 #if defined (__GNUC__)
2568 __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
2569
2570 *((uint16_t *)hi2s->pRxBuffPtr) = *prxdr_16bits;
2571 #else
2572 *((uint16_t *)hi2s->pRxBuffPtr) = *((__IO uint16_t *)&hi2s->Instance->RXDR);
2573 #endif /* __GNUC__ */
2574 hi2s->pRxBuffPtr++;
2575 hi2s->RxXferCount--;
2576
2577 if (hi2s->RxXferCount == 0UL)
2578 {
2579 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2580 {
2581 /* Disable TXP, RXP, DXP, ERR interrupts */
2582 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_ERR));
2583 }
2584 else
2585 {
2586 /* Disable RXP and ERR interrupt */
2587 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
2588 }
2589
2590 hi2s->State = HAL_I2S_STATE_READY;
2591 /* Call user Rx complete callback */
2592 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2593 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2594 {
2595 hi2s->TxRxCpltCallback(hi2s);
2596 }
2597 else
2598 {
2599 hi2s->RxCpltCallback(hi2s);
2600 }
2601 #else
2602 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2603 {
2604 HAL_I2SEx_TxRxCpltCallback(hi2s);
2605 }
2606 else
2607 {
2608 HAL_I2S_RxCpltCallback(hi2s);
2609 }
2610 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2611 }
2612 }
2613
2614 /**
2615 * @brief Manage the reception 32-bit in Interrupt context
2616 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2617 * the configuration information for I2S module
2618 * @retval None
2619 */
I2S_Receive_32Bit_IT(I2S_HandleTypeDef * hi2s)2620 static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s)
2621 {
2622 /* Receive data */
2623 *((uint32_t *)hi2s->pRxBuffPtr) = hi2s->Instance->RXDR;
2624 hi2s->pRxBuffPtr += 2;
2625 hi2s->RxXferCount--;
2626
2627 if (hi2s->RxXferCount == 0UL)
2628 {
2629 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2630 {
2631 /* Disable TXP, RXP, DXP, ERR interrupts */
2632 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_DXP | I2S_IT_ERR));
2633 }
2634 else
2635 {
2636 /* Disable RXP and ERR interrupt */
2637 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
2638 }
2639
2640 hi2s->State = HAL_I2S_STATE_READY;
2641 /* Call user Rx complete callback */
2642 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
2643 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2644 {
2645 hi2s->TxRxCpltCallback(hi2s);
2646 }
2647 else
2648 {
2649 hi2s->RxCpltCallback(hi2s);
2650 }
2651 #else
2652 if (IS_I2S_FULLDUPLEX(hi2s->Init.Mode))
2653 {
2654 HAL_I2SEx_TxRxCpltCallback(hi2s);
2655 }
2656 else
2657 {
2658 HAL_I2S_RxCpltCallback(hi2s);
2659 }
2660 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
2661 }
2662 }
2663
2664 /**
2665 * @brief This function handles I2S Communication Timeout.
2666 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
2667 * the configuration information for I2S module
2668 * @param Flag Flag checked
2669 * @param State Value of the flag expected
2670 * @param Tickstart Tick start value
2671 * @param Timeout Duration of the timeout
2672 * @retval HAL status
2673 */
I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef * hi2s,uint32_t Flag,FlagStatus State,uint32_t Tickstart,uint32_t Timeout)2674 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
2675 uint32_t Tickstart, uint32_t Timeout)
2676 {
2677 /* Wait until flag is set to status*/
2678 while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
2679 {
2680 if (Timeout != HAL_MAX_DELAY)
2681 {
2682 if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0UL))
2683 {
2684 /* Set the I2S State ready */
2685 hi2s->State = HAL_I2S_STATE_READY;
2686
2687 /* Process Unlocked */
2688 __HAL_UNLOCK(hi2s);
2689
2690 return HAL_TIMEOUT;
2691 }
2692 }
2693 }
2694 return HAL_OK;
2695 }
2696
2697 /**
2698 * @}
2699 */
2700
2701 /**
2702 * @}
2703 */
2704
2705 /**
2706 * @}
2707 */
2708
2709 #endif /* HAL_I2S_MODULE_ENABLED */
2710
