1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2022 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for
43 the transmit or receive channel
44 (+++) Enable the DMAx interface clock using
45 (+++) Configure the DMA handle parameters
46 (+++) Configure the DMA Tx or Rx channel
47 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
48 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
49 the DMA Tx or Rx channel
50
51 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
52 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
53
54 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
55 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
56
57 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
58
59 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
60
61 *** Polling mode IO operation ***
62 =================================
63 [..]
64 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
65 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
66 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
67 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
68
69 *** Polling mode IO MEM operation ***
70 =====================================
71 [..]
72 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
73 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
74
75
76 *** Interrupt mode IO operation ***
77 ===================================
78 [..]
79 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
80 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
81 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
82 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
83 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
84 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
85 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
86 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
87 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
88 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
89 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
90 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
91 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
92 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
93 (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
94 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
95 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
96 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
97 This action will inform Master to generate a Stop condition to discard the communication.
98
99
100 *** Interrupt mode or DMA mode IO sequential operation ***
101 ==========================================================
102 [..]
103 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
104 when a direction change during transfer
105 [..]
106 (+) A specific option field manage the different steps of a sequential transfer
107 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
108 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
109 no sequential mode
110 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
111 and data to transfer without a final stop condition
112 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
113 start condition, address and data to transfer without a final stop condition,
114 an then permit a call the same master sequential interface several times
115 (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
116 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
117 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
118 and with new data to transfer if the direction change or manage only the new data to
119 transfer
120 if no direction change and without a final stop condition in both cases
121 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
122 and with new data to transfer if the direction change or manage only the new data to
123 transfer
124 if no direction change and with a final stop condition in both cases
125 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
126 after several call of the same master sequential interface several times
127 (link with option I2C_FIRST_AND_NEXT_FRAME).
128 Usage can, transfer several bytes one by one using
129 HAL_I2C_Master_Seq_Transmit_IT
130 or HAL_I2C_Master_Seq_Receive_IT
131 or HAL_I2C_Master_Seq_Transmit_DMA
132 or HAL_I2C_Master_Seq_Receive_DMA
133 with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
134 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
135 Receive sequence permit to call the opposite interface Receive or Transmit
136 without stopping the communication and so generate a restart condition.
137 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
138 each call of the same master sequential
139 interface.
140 Usage can, transfer several bytes one by one with a restart with slave address between
141 each bytes using
142 HAL_I2C_Master_Seq_Transmit_IT
143 or HAL_I2C_Master_Seq_Receive_IT
144 or HAL_I2C_Master_Seq_Transmit_DMA
145 or HAL_I2C_Master_Seq_Receive_DMA
146 with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
147 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
148 generation of STOP condition.
149
150 (+) Different sequential I2C interfaces are listed below:
151 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
152 HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
153 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
154 users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
155 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
156 HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
157 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
158 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
159 (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
160 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
161 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
162 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
163 HAL_I2C_DisableListen_IT()
164 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
165 add their own code to check the Address Match Code and the transmission direction request by master
166 (Write/Read).
167 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
168 add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
169 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
170 HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
171 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
172 users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
173 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
174 HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
175 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
176 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
177 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
178 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
179 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
180 This action will inform Master to generate a Stop condition to discard the communication.
181
182 *** Interrupt mode IO MEM operation ***
183 =======================================
184 [..]
185 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
186 HAL_I2C_Mem_Write_IT()
187 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
188 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
189 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
190 HAL_I2C_Mem_Read_IT()
191 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
192 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
193 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
194 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
195
196 *** DMA mode IO operation ***
197 ==============================
198 [..]
199 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
200 HAL_I2C_Master_Transmit_DMA()
201 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
202 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
203 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
204 HAL_I2C_Master_Receive_DMA()
205 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
206 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
207 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
208 HAL_I2C_Slave_Transmit_DMA()
209 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
210 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
211 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
212 HAL_I2C_Slave_Receive_DMA()
213 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
214 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
215 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
216 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
217 (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
218 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
219 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
220 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
221 This action will inform Master to generate a Stop condition to discard the communication.
222
223 *** DMA mode IO MEM operation ***
224 =================================
225 [..]
226 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
227 HAL_I2C_Mem_Write_DMA()
228 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
229 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
230 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
231 HAL_I2C_Mem_Read_DMA()
232 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
233 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
234 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
235 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
236
237
238 *** I2C HAL driver macros list ***
239 ==================================
240 [..]
241 Below the list of most used macros in I2C HAL driver.
242
243 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
244 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
245 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
246 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
247 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
248 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
249 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
250
251 *** Callback registration ***
252 =============================================
253 [..]
254 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
255 allows the user to configure dynamically the driver callbacks.
256 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
257 to register an interrupt callback.
258 [..]
259 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
260 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
261 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
262 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
263 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
264 (+) ListenCpltCallback : callback for end of listen mode.
265 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
266 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
267 (+) ErrorCallback : callback for error detection.
268 (+) AbortCpltCallback : callback for abort completion process.
269 (+) MspInitCallback : callback for Msp Init.
270 (+) MspDeInitCallback : callback for Msp DeInit.
271 This function takes as parameters the HAL peripheral handle, the Callback ID
272 and a pointer to the user callback function.
273 [..]
274 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
275 [..]
276 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
277 weak function.
278 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
279 and the Callback ID.
280 This function allows to reset following callbacks:
281 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
282 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
283 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
284 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
285 (+) ListenCpltCallback : callback for end of listen mode.
286 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
287 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
288 (+) ErrorCallback : callback for error detection.
289 (+) AbortCpltCallback : callback for abort completion process.
290 (+) MspInitCallback : callback for Msp Init.
291 (+) MspDeInitCallback : callback for Msp DeInit.
292 [..]
293 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
294 [..]
295 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
296 all callbacks are set to the corresponding weak functions:
297 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
298 Exception done for MspInit and MspDeInit functions that are
299 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
300 these callbacks are null (not registered beforehand).
301 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
302 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
303 [..]
304 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
305 Exception done MspInit/MspDeInit functions that can be registered/unregistered
306 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
307 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
308 Then, the user first registers the MspInit/MspDeInit user callbacks
309 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
310 or HAL_I2C_Init() function.
311 [..]
312 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
313 not defined, the callback registration feature is not available and all callbacks
314 are set to the corresponding weak functions.
315
316 [..]
317 (@) You can refer to the I2C HAL driver header file for more useful macros
318
319 @endverbatim
320 */
321
322 /* Includes ------------------------------------------------------------------*/
323 #include "stm32h7rsxx_hal.h"
324
325 /** @addtogroup STM32H7RSxx_HAL_Driver
326 * @{
327 */
328
329 /** @defgroup I2C I2C
330 * @brief I2C HAL module driver
331 * @{
332 */
333
334 #ifdef HAL_I2C_MODULE_ENABLED
335
336 /* Private typedef -----------------------------------------------------------*/
337 /* Private define ------------------------------------------------------------*/
338
339 /** @defgroup I2C_Private_Define I2C Private Define
340 * @{
341 */
342 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
343 #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
344 #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
345 #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
346 #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
347 #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
348 #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
349 #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
350 #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
351 #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
352
353 #define MAX_NBYTE_SIZE 255U
354 #define SLAVE_ADDR_SHIFT 7U
355 #define SLAVE_ADDR_MSK 0x06U
356
357 /* Private define for @ref PreviousState usage */
358 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
359 (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
360 (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
361 /*!< Mask State define, keep only RX and TX bits */
362 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
363 /*!< Default Value */
364 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
365 (uint32_t)HAL_I2C_MODE_MASTER))
366 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
367 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
368 (uint32_t)HAL_I2C_MODE_MASTER))
369 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
370 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
371 (uint32_t)HAL_I2C_MODE_SLAVE))
372 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
373 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
374 (uint32_t)HAL_I2C_MODE_SLAVE))
375 /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
376 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
377 (uint32_t)HAL_I2C_MODE_MEM))
378 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
379 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
380 (uint32_t)HAL_I2C_MODE_MEM))
381 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
382
383
384 /* Private define to centralize the enable/disable of Interrupts */
385 #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
386 @ref I2C_XFER_LISTEN_IT */
387 #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
388 @ref I2C_XFER_LISTEN_IT */
389 #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
390 and @ref I2C_XFER_RX_IT */
391
392 #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
393 and NACK treatment */
394 #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
395 #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
396
397 /* Private define Sequential Transfer Options default/reset value */
398 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
399 /**
400 * @}
401 */
402
403 /* Private macros ------------------------------------------------------------*/
404 /** @addtogroup I2C_Private_Macro
405 * @{
406 */
407 #if defined(HAL_DMA_MODULE_ENABLED)
408 /* Macro to get remaining data to transfer on DMA side */
409 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__))
410 #endif /* HAL_DMA_MODULE_ENABLED */
411 /**
412 * @}
413 */
414
415 /* Private variables ---------------------------------------------------------*/
416 /* Private function prototypes -----------------------------------------------*/
417
418 /** @defgroup I2C_Private_Functions I2C Private Functions
419 * @{
420 */
421 #if defined(HAL_DMA_MODULE_ENABLED)
422 /* Private functions to handle DMA transfer */
423 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
424 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
425 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
426 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
427 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
428 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
429
430 #endif /* HAL_DMA_MODULE_ENABLED */
431
432 /* Private functions to handle IT transfer */
433 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
434 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
435 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
436 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
437 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
438 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
439 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
440
441 /* Private functions to handle IT transfer */
442 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
443 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
444 uint32_t Tickstart);
445 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
446 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
447 uint32_t Tickstart);
448
449 /* Private functions for I2C transfer IRQ handler */
450 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
451 uint32_t ITSources);
452 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
453 uint32_t ITSources);
454 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
455 uint32_t ITSources);
456 #if defined(HAL_DMA_MODULE_ENABLED)
457 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
458 uint32_t ITSources);
459 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
460 uint32_t ITSources);
461 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
462 uint32_t ITSources);
463 #endif /* HAL_DMA_MODULE_ENABLED */
464
465 /* Private functions to handle flags during polling transfer */
466 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
467 uint32_t Timeout, uint32_t Tickstart);
468 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
469 uint32_t Tickstart);
470 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
471 uint32_t Tickstart);
472 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
473 uint32_t Tickstart);
474 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
475 uint32_t Tickstart);
476
477 /* Private functions to centralize the enable/disable of Interrupts */
478 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
479 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
480
481 /* Private function to treat different error callback */
482 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
483
484 /* Private function to flush TXDR register */
485 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
486
487 /* Private function to handle start, restart or stop a transfer */
488 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
489 uint32_t Request);
490
491 /* Private function to Convert Specific options */
492 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
493 /**
494 * @}
495 */
496
497 /* Exported functions --------------------------------------------------------*/
498
499 /** @defgroup I2C_Exported_Functions I2C Exported Functions
500 * @{
501 */
502
503 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
504 * @brief Initialization and Configuration functions
505 *
506 @verbatim
507 ===============================================================================
508 ##### Initialization and de-initialization functions #####
509 ===============================================================================
510 [..] This subsection provides a set of functions allowing to initialize and
511 deinitialize the I2Cx peripheral:
512
513 (+) User must Implement HAL_I2C_MspInit() function in which he configures
514 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
515
516 (+) Call the function HAL_I2C_Init() to configure the selected device with
517 the selected configuration:
518 (++) Clock Timing
519 (++) Own Address 1
520 (++) Addressing mode (Master, Slave)
521 (++) Dual Addressing mode
522 (++) Own Address 2
523 (++) Own Address 2 Mask
524 (++) General call mode
525 (++) Nostretch mode
526
527 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
528 of the selected I2Cx peripheral.
529
530 @endverbatim
531 * @{
532 */
533
534 /**
535 * @brief Initializes the I2C according to the specified parameters
536 * in the I2C_InitTypeDef and initialize the associated handle.
537 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
538 * the configuration information for the specified I2C.
539 * @retval HAL status
540 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)541 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
542 {
543 /* Check the I2C handle allocation */
544 if (hi2c == NULL)
545 {
546 return HAL_ERROR;
547 }
548
549 /* Check the parameters */
550 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
551 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
552 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
553 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
554 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
555 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
556 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
557 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
558
559 if (hi2c->State == HAL_I2C_STATE_RESET)
560 {
561 /* Allocate lock resource and initialize it */
562 hi2c->Lock = HAL_UNLOCKED;
563
564 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
565 /* Init the I2C Callback settings */
566 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
567 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
568 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
569 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
570 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
571 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
572 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
573 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
574 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
575 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
576
577 if (hi2c->MspInitCallback == NULL)
578 {
579 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
580 }
581
582 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
583 hi2c->MspInitCallback(hi2c);
584 #else
585 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
586 HAL_I2C_MspInit(hi2c);
587 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
588 }
589
590 hi2c->State = HAL_I2C_STATE_BUSY;
591
592 /* Disable the selected I2C peripheral */
593 __HAL_I2C_DISABLE(hi2c);
594
595 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
596 /* Configure I2Cx: Frequency range */
597 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
598
599 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
600 /* Disable Own Address1 before set the Own Address1 configuration */
601 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
602
603 /* Configure I2Cx: Own Address1 and ack own address1 mode */
604 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
605 {
606 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
607 }
608 else /* I2C_ADDRESSINGMODE_10BIT */
609 {
610 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
611 }
612
613 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
614 /* Configure I2Cx: Addressing Master mode */
615 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
616 {
617 SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
618 }
619 else
620 {
621 /* Clear the I2C ADD10 bit */
622 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
623 }
624 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
625 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
626
627 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
628 /* Disable Own Address2 before set the Own Address2 configuration */
629 hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
630
631 /* Configure I2Cx: Dual mode and Own Address2 */
632 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
633 (hi2c->Init.OwnAddress2Masks << 8));
634
635 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
636 /* Configure I2Cx: Generalcall and NoStretch mode */
637 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
638
639 /* Enable the selected I2C peripheral */
640 __HAL_I2C_ENABLE(hi2c);
641
642 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
643 hi2c->State = HAL_I2C_STATE_READY;
644 hi2c->PreviousState = I2C_STATE_NONE;
645 hi2c->Mode = HAL_I2C_MODE_NONE;
646
647 return HAL_OK;
648 }
649
650 /**
651 * @brief DeInitialize the I2C peripheral.
652 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
653 * the configuration information for the specified I2C.
654 * @retval HAL status
655 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)656 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
657 {
658 /* Check the I2C handle allocation */
659 if (hi2c == NULL)
660 {
661 return HAL_ERROR;
662 }
663
664 /* Check the parameters */
665 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
666
667 hi2c->State = HAL_I2C_STATE_BUSY;
668
669 /* Disable the I2C Peripheral Clock */
670 __HAL_I2C_DISABLE(hi2c);
671
672 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
673 if (hi2c->MspDeInitCallback == NULL)
674 {
675 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
676 }
677
678 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
679 hi2c->MspDeInitCallback(hi2c);
680 #else
681 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
682 HAL_I2C_MspDeInit(hi2c);
683 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
684
685 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
686 hi2c->State = HAL_I2C_STATE_RESET;
687 hi2c->PreviousState = I2C_STATE_NONE;
688 hi2c->Mode = HAL_I2C_MODE_NONE;
689
690 /* Release Lock */
691 __HAL_UNLOCK(hi2c);
692
693 return HAL_OK;
694 }
695
696 /**
697 * @brief Initialize the I2C MSP.
698 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
699 * the configuration information for the specified I2C.
700 * @retval None
701 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)702 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
703 {
704 /* Prevent unused argument(s) compilation warning */
705 UNUSED(hi2c);
706
707 /* NOTE : This function should not be modified, when the callback is needed,
708 the HAL_I2C_MspInit could be implemented in the user file
709 */
710 }
711
712 /**
713 * @brief DeInitialize the I2C MSP.
714 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
715 * the configuration information for the specified I2C.
716 * @retval None
717 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)718 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
719 {
720 /* Prevent unused argument(s) compilation warning */
721 UNUSED(hi2c);
722
723 /* NOTE : This function should not be modified, when the callback is needed,
724 the HAL_I2C_MspDeInit could be implemented in the user file
725 */
726 }
727
728 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
729 /**
730 * @brief Register a User I2C Callback
731 * To be used instead of the weak predefined callback
732 * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
733 * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
734 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
735 * the configuration information for the specified I2C.
736 * @param CallbackID ID of the callback to be registered
737 * This parameter can be one of the following values:
738 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
739 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
740 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
741 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
742 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
743 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
744 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
745 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
746 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
747 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
748 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
749 * @param pCallback pointer to the Callback function
750 * @retval HAL status
751 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)752 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
753 pI2C_CallbackTypeDef pCallback)
754 {
755 HAL_StatusTypeDef status = HAL_OK;
756
757 if (pCallback == NULL)
758 {
759 /* Update the error code */
760 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
761
762 return HAL_ERROR;
763 }
764
765 if (HAL_I2C_STATE_READY == hi2c->State)
766 {
767 switch (CallbackID)
768 {
769 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
770 hi2c->MasterTxCpltCallback = pCallback;
771 break;
772
773 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
774 hi2c->MasterRxCpltCallback = pCallback;
775 break;
776
777 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
778 hi2c->SlaveTxCpltCallback = pCallback;
779 break;
780
781 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
782 hi2c->SlaveRxCpltCallback = pCallback;
783 break;
784
785 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
786 hi2c->ListenCpltCallback = pCallback;
787 break;
788
789 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
790 hi2c->MemTxCpltCallback = pCallback;
791 break;
792
793 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
794 hi2c->MemRxCpltCallback = pCallback;
795 break;
796
797 case HAL_I2C_ERROR_CB_ID :
798 hi2c->ErrorCallback = pCallback;
799 break;
800
801 case HAL_I2C_ABORT_CB_ID :
802 hi2c->AbortCpltCallback = pCallback;
803 break;
804
805 case HAL_I2C_MSPINIT_CB_ID :
806 hi2c->MspInitCallback = pCallback;
807 break;
808
809 case HAL_I2C_MSPDEINIT_CB_ID :
810 hi2c->MspDeInitCallback = pCallback;
811 break;
812
813 default :
814 /* Update the error code */
815 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
816
817 /* Return error status */
818 status = HAL_ERROR;
819 break;
820 }
821 }
822 else if (HAL_I2C_STATE_RESET == hi2c->State)
823 {
824 switch (CallbackID)
825 {
826 case HAL_I2C_MSPINIT_CB_ID :
827 hi2c->MspInitCallback = pCallback;
828 break;
829
830 case HAL_I2C_MSPDEINIT_CB_ID :
831 hi2c->MspDeInitCallback = pCallback;
832 break;
833
834 default :
835 /* Update the error code */
836 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
837
838 /* Return error status */
839 status = HAL_ERROR;
840 break;
841 }
842 }
843 else
844 {
845 /* Update the error code */
846 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
847
848 /* Return error status */
849 status = HAL_ERROR;
850 }
851
852 return status;
853 }
854
855 /**
856 * @brief Unregister an I2C Callback
857 * I2C callback is redirected to the weak predefined callback
858 * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
859 * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
860 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
861 * the configuration information for the specified I2C.
862 * @param CallbackID ID of the callback to be unregistered
863 * This parameter can be one of the following values:
864 * This parameter can be one of the following values:
865 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
866 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
867 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
868 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
869 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
870 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
871 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
872 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
873 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
874 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
875 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
876 * @retval HAL status
877 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)878 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
879 {
880 HAL_StatusTypeDef status = HAL_OK;
881
882 if (HAL_I2C_STATE_READY == hi2c->State)
883 {
884 switch (CallbackID)
885 {
886 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
887 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
888 break;
889
890 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
891 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
892 break;
893
894 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
895 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
896 break;
897
898 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
899 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
900 break;
901
902 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
903 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
904 break;
905
906 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
907 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
908 break;
909
910 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
911 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
912 break;
913
914 case HAL_I2C_ERROR_CB_ID :
915 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
916 break;
917
918 case HAL_I2C_ABORT_CB_ID :
919 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
920 break;
921
922 case HAL_I2C_MSPINIT_CB_ID :
923 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
924 break;
925
926 case HAL_I2C_MSPDEINIT_CB_ID :
927 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
928 break;
929
930 default :
931 /* Update the error code */
932 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
933
934 /* Return error status */
935 status = HAL_ERROR;
936 break;
937 }
938 }
939 else if (HAL_I2C_STATE_RESET == hi2c->State)
940 {
941 switch (CallbackID)
942 {
943 case HAL_I2C_MSPINIT_CB_ID :
944 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
945 break;
946
947 case HAL_I2C_MSPDEINIT_CB_ID :
948 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
949 break;
950
951 default :
952 /* Update the error code */
953 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
954
955 /* Return error status */
956 status = HAL_ERROR;
957 break;
958 }
959 }
960 else
961 {
962 /* Update the error code */
963 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
964
965 /* Return error status */
966 status = HAL_ERROR;
967 }
968
969 return status;
970 }
971
972 /**
973 * @brief Register the Slave Address Match I2C Callback
974 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
975 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
976 * the configuration information for the specified I2C.
977 * @param pCallback pointer to the Address Match Callback function
978 * @retval HAL status
979 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)980 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
981 {
982 HAL_StatusTypeDef status = HAL_OK;
983
984 if (pCallback == NULL)
985 {
986 /* Update the error code */
987 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
988
989 return HAL_ERROR;
990 }
991
992 if (HAL_I2C_STATE_READY == hi2c->State)
993 {
994 hi2c->AddrCallback = pCallback;
995 }
996 else
997 {
998 /* Update the error code */
999 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1000
1001 /* Return error status */
1002 status = HAL_ERROR;
1003 }
1004
1005 return status;
1006 }
1007
1008 /**
1009 * @brief UnRegister the Slave Address Match I2C Callback
1010 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
1011 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1012 * the configuration information for the specified I2C.
1013 * @retval HAL status
1014 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)1015 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
1016 {
1017 HAL_StatusTypeDef status = HAL_OK;
1018
1019 if (HAL_I2C_STATE_READY == hi2c->State)
1020 {
1021 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
1022 }
1023 else
1024 {
1025 /* Update the error code */
1026 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1027
1028 /* Return error status */
1029 status = HAL_ERROR;
1030 }
1031
1032 return status;
1033 }
1034
1035 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
1036
1037 /**
1038 * @}
1039 */
1040
1041 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
1042 * @brief Data transfers functions
1043 *
1044 @verbatim
1045 ===============================================================================
1046 ##### IO operation functions #####
1047 ===============================================================================
1048 [..]
1049 This subsection provides a set of functions allowing to manage the I2C data
1050 transfers.
1051
1052 (#) There are two modes of transfer:
1053 (++) Blocking mode : The communication is performed in the polling mode.
1054 The status of all data processing is returned by the same function
1055 after finishing transfer.
1056 (++) No-Blocking mode : The communication is performed using Interrupts
1057 or DMA. These functions return the status of the transfer startup.
1058 The end of the data processing will be indicated through the
1059 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
1060 using DMA mode.
1061
1062 (#) Blocking mode functions are :
1063 (++) HAL_I2C_Master_Transmit()
1064 (++) HAL_I2C_Master_Receive()
1065 (++) HAL_I2C_Slave_Transmit()
1066 (++) HAL_I2C_Slave_Receive()
1067 (++) HAL_I2C_Mem_Write()
1068 (++) HAL_I2C_Mem_Read()
1069 (++) HAL_I2C_IsDeviceReady()
1070
1071 (#) No-Blocking mode functions with Interrupt are :
1072 (++) HAL_I2C_Master_Transmit_IT()
1073 (++) HAL_I2C_Master_Receive_IT()
1074 (++) HAL_I2C_Slave_Transmit_IT()
1075 (++) HAL_I2C_Slave_Receive_IT()
1076 (++) HAL_I2C_Mem_Write_IT()
1077 (++) HAL_I2C_Mem_Read_IT()
1078 (++) HAL_I2C_Master_Seq_Transmit_IT()
1079 (++) HAL_I2C_Master_Seq_Receive_IT()
1080 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1081 (++) HAL_I2C_Slave_Seq_Receive_IT()
1082 (++) HAL_I2C_EnableListen_IT()
1083 (++) HAL_I2C_DisableListen_IT()
1084 (++) HAL_I2C_Master_Abort_IT()
1085
1086 (#) No-Blocking mode functions with DMA are :
1087 (++) HAL_I2C_Master_Transmit_DMA()
1088 (++) HAL_I2C_Master_Receive_DMA()
1089 (++) HAL_I2C_Slave_Transmit_DMA()
1090 (++) HAL_I2C_Slave_Receive_DMA()
1091 (++) HAL_I2C_Mem_Write_DMA()
1092 (++) HAL_I2C_Mem_Read_DMA()
1093 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1094 (++) HAL_I2C_Master_Seq_Receive_DMA()
1095 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1096 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1097
1098 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1099 (++) HAL_I2C_MasterTxCpltCallback()
1100 (++) HAL_I2C_MasterRxCpltCallback()
1101 (++) HAL_I2C_SlaveTxCpltCallback()
1102 (++) HAL_I2C_SlaveRxCpltCallback()
1103 (++) HAL_I2C_MemTxCpltCallback()
1104 (++) HAL_I2C_MemRxCpltCallback()
1105 (++) HAL_I2C_AddrCallback()
1106 (++) HAL_I2C_ListenCpltCallback()
1107 (++) HAL_I2C_ErrorCallback()
1108 (++) HAL_I2C_AbortCpltCallback()
1109
1110 @endverbatim
1111 * @{
1112 */
1113
1114 /**
1115 * @brief Transmits in master mode an amount of data in blocking mode.
1116 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1117 * the configuration information for the specified I2C.
1118 * @param DevAddress Target device address: The device 7 bits address value
1119 * in datasheet must be shifted to the left before calling the interface
1120 * @param pData Pointer to data buffer
1121 * @param Size Amount of data to be sent
1122 * @param Timeout Timeout duration
1123 * @retval HAL status
1124 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1125 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1126 uint16_t Size, uint32_t Timeout)
1127 {
1128 uint32_t tickstart;
1129
1130 if (hi2c->State == HAL_I2C_STATE_READY)
1131 {
1132 /* Process Locked */
1133 __HAL_LOCK(hi2c);
1134
1135 /* Init tickstart for timeout management*/
1136 tickstart = HAL_GetTick();
1137
1138 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1139 {
1140 return HAL_ERROR;
1141 }
1142
1143 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1144 hi2c->Mode = HAL_I2C_MODE_MASTER;
1145 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1146
1147 /* Prepare transfer parameters */
1148 hi2c->pBuffPtr = pData;
1149 hi2c->XferCount = Size;
1150 hi2c->XferISR = NULL;
1151
1152 /* Send Slave Address */
1153 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1154 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1155 {
1156 hi2c->XferSize = MAX_NBYTE_SIZE;
1157 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1158 I2C_GENERATE_START_WRITE);
1159 }
1160 else
1161 {
1162 hi2c->XferSize = hi2c->XferCount;
1163 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1164 I2C_GENERATE_START_WRITE);
1165 }
1166
1167 while (hi2c->XferCount > 0U)
1168 {
1169 /* Wait until TXIS flag is set */
1170 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1171 {
1172 return HAL_ERROR;
1173 }
1174 /* Write data to TXDR */
1175 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1176
1177 /* Increment Buffer pointer */
1178 hi2c->pBuffPtr++;
1179
1180 hi2c->XferCount--;
1181 hi2c->XferSize--;
1182
1183 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1184 {
1185 /* Wait until TCR flag is set */
1186 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1187 {
1188 return HAL_ERROR;
1189 }
1190
1191 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1192 {
1193 hi2c->XferSize = MAX_NBYTE_SIZE;
1194 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1195 I2C_NO_STARTSTOP);
1196 }
1197 else
1198 {
1199 hi2c->XferSize = hi2c->XferCount;
1200 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1201 I2C_NO_STARTSTOP);
1202 }
1203 }
1204 }
1205
1206 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1207 /* Wait until STOPF flag is set */
1208 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1209 {
1210 return HAL_ERROR;
1211 }
1212
1213 /* Clear STOP Flag */
1214 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1215
1216 /* Clear Configuration Register 2 */
1217 I2C_RESET_CR2(hi2c);
1218
1219 hi2c->State = HAL_I2C_STATE_READY;
1220 hi2c->Mode = HAL_I2C_MODE_NONE;
1221
1222 /* Process Unlocked */
1223 __HAL_UNLOCK(hi2c);
1224
1225 return HAL_OK;
1226 }
1227 else
1228 {
1229 return HAL_BUSY;
1230 }
1231 }
1232
1233 /**
1234 * @brief Receives in master mode an amount of data in blocking mode.
1235 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1236 * the configuration information for the specified I2C.
1237 * @param DevAddress Target device address: The device 7 bits address value
1238 * in datasheet must be shifted to the left before calling the interface
1239 * @param pData Pointer to data buffer
1240 * @param Size Amount of data to be sent
1241 * @param Timeout Timeout duration
1242 * @retval HAL status
1243 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1244 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1245 uint16_t Size, uint32_t Timeout)
1246 {
1247 uint32_t tickstart;
1248
1249 if (hi2c->State == HAL_I2C_STATE_READY)
1250 {
1251 /* Process Locked */
1252 __HAL_LOCK(hi2c);
1253
1254 /* Init tickstart for timeout management*/
1255 tickstart = HAL_GetTick();
1256
1257 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1258 {
1259 return HAL_ERROR;
1260 }
1261
1262 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1263 hi2c->Mode = HAL_I2C_MODE_MASTER;
1264 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1265
1266 /* Prepare transfer parameters */
1267 hi2c->pBuffPtr = pData;
1268 hi2c->XferCount = Size;
1269 hi2c->XferISR = NULL;
1270
1271 /* Send Slave Address */
1272 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1273 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1274 {
1275 hi2c->XferSize = MAX_NBYTE_SIZE;
1276 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1277 I2C_GENERATE_START_READ);
1278 }
1279 else
1280 {
1281 hi2c->XferSize = hi2c->XferCount;
1282 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1283 I2C_GENERATE_START_READ);
1284 }
1285
1286 while (hi2c->XferCount > 0U)
1287 {
1288 /* Wait until RXNE flag is set */
1289 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1290 {
1291 return HAL_ERROR;
1292 }
1293
1294 /* Read data from RXDR */
1295 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1296
1297 /* Increment Buffer pointer */
1298 hi2c->pBuffPtr++;
1299
1300 hi2c->XferSize--;
1301 hi2c->XferCount--;
1302
1303 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1304 {
1305 /* Wait until TCR flag is set */
1306 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1307 {
1308 return HAL_ERROR;
1309 }
1310
1311 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1312 {
1313 hi2c->XferSize = MAX_NBYTE_SIZE;
1314 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1315 I2C_NO_STARTSTOP);
1316 }
1317 else
1318 {
1319 hi2c->XferSize = hi2c->XferCount;
1320 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1321 I2C_NO_STARTSTOP);
1322 }
1323 }
1324 }
1325
1326 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1327 /* Wait until STOPF flag is set */
1328 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1329 {
1330 return HAL_ERROR;
1331 }
1332
1333 /* Clear STOP Flag */
1334 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1335
1336 /* Clear Configuration Register 2 */
1337 I2C_RESET_CR2(hi2c);
1338
1339 hi2c->State = HAL_I2C_STATE_READY;
1340 hi2c->Mode = HAL_I2C_MODE_NONE;
1341
1342 /* Process Unlocked */
1343 __HAL_UNLOCK(hi2c);
1344
1345 return HAL_OK;
1346 }
1347 else
1348 {
1349 return HAL_BUSY;
1350 }
1351 }
1352
1353 /**
1354 * @brief Transmits in slave mode an amount of data in blocking mode.
1355 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1356 * the configuration information for the specified I2C.
1357 * @param pData Pointer to data buffer
1358 * @param Size Amount of data to be sent
1359 * @param Timeout Timeout duration
1360 * @retval HAL status
1361 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1362 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1363 uint32_t Timeout)
1364 {
1365 uint32_t tickstart;
1366 uint16_t tmpXferCount;
1367 HAL_StatusTypeDef error;
1368
1369 if (hi2c->State == HAL_I2C_STATE_READY)
1370 {
1371 if ((pData == NULL) || (Size == 0U))
1372 {
1373 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1374 return HAL_ERROR;
1375 }
1376 /* Process Locked */
1377 __HAL_LOCK(hi2c);
1378
1379 /* Init tickstart for timeout management*/
1380 tickstart = HAL_GetTick();
1381
1382 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1383 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1384 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1385
1386 /* Prepare transfer parameters */
1387 hi2c->pBuffPtr = pData;
1388 hi2c->XferCount = Size;
1389 hi2c->XferISR = NULL;
1390
1391 /* Enable Address Acknowledge */
1392 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1393
1394 /* Preload TX data if no stretch enable */
1395 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1396 {
1397 /* Preload TX register */
1398 /* Write data to TXDR */
1399 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1400
1401 /* Increment Buffer pointer */
1402 hi2c->pBuffPtr++;
1403
1404 hi2c->XferCount--;
1405 }
1406
1407 /* Wait until ADDR flag is set */
1408 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1409 {
1410 /* Disable Address Acknowledge */
1411 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1412
1413 /* Flush TX register */
1414 I2C_Flush_TXDR(hi2c);
1415
1416 return HAL_ERROR;
1417 }
1418
1419 /* Clear ADDR flag */
1420 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1421
1422 /* If 10bit addressing mode is selected */
1423 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1424 {
1425 /* Wait until ADDR flag is set */
1426 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1427 {
1428 /* Disable Address Acknowledge */
1429 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1430
1431 /* Flush TX register */
1432 I2C_Flush_TXDR(hi2c);
1433
1434 return HAL_ERROR;
1435 }
1436
1437 /* Clear ADDR flag */
1438 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1439 }
1440
1441 /* Wait until DIR flag is set Transmitter mode */
1442 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
1443 {
1444 /* Disable Address Acknowledge */
1445 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1446
1447 /* Flush TX register */
1448 I2C_Flush_TXDR(hi2c);
1449
1450 return HAL_ERROR;
1451 }
1452
1453 while (hi2c->XferCount > 0U)
1454 {
1455 /* Wait until TXIS flag is set */
1456 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1457 {
1458 /* Disable Address Acknowledge */
1459 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1460 return HAL_ERROR;
1461 }
1462
1463 /* Write data to TXDR */
1464 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1465
1466 /* Increment Buffer pointer */
1467 hi2c->pBuffPtr++;
1468
1469 hi2c->XferCount--;
1470 }
1471
1472 /* Wait until AF flag is set */
1473 error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
1474
1475 if (error != HAL_OK)
1476 {
1477 /* Check that I2C transfer finished */
1478 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
1479 /* Mean XferCount == 0 */
1480
1481 tmpXferCount = hi2c->XferCount;
1482 if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
1483 {
1484 /* Reset ErrorCode to NONE */
1485 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1486 }
1487 else
1488 {
1489 /* Disable Address Acknowledge */
1490 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1491 return HAL_ERROR;
1492 }
1493 }
1494 else
1495 {
1496 /* Flush TX register */
1497 I2C_Flush_TXDR(hi2c);
1498
1499 /* Clear AF flag */
1500 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1501
1502 /* Wait until STOP flag is set */
1503 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1504 {
1505 /* Disable Address Acknowledge */
1506 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1507
1508 return HAL_ERROR;
1509 }
1510
1511 /* Clear STOP flag */
1512 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1513 }
1514
1515 /* Wait until BUSY flag is reset */
1516 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1517 {
1518 /* Disable Address Acknowledge */
1519 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1520 return HAL_ERROR;
1521 }
1522
1523 /* Disable Address Acknowledge */
1524 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1525
1526 hi2c->State = HAL_I2C_STATE_READY;
1527 hi2c->Mode = HAL_I2C_MODE_NONE;
1528
1529 /* Process Unlocked */
1530 __HAL_UNLOCK(hi2c);
1531
1532 return HAL_OK;
1533 }
1534 else
1535 {
1536 return HAL_BUSY;
1537 }
1538 }
1539
1540 /**
1541 * @brief Receive in slave mode an amount of data in blocking mode
1542 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1543 * the configuration information for the specified I2C.
1544 * @param pData Pointer to data buffer
1545 * @param Size Amount of data to be sent
1546 * @param Timeout Timeout duration
1547 * @retval HAL status
1548 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1549 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1550 uint32_t Timeout)
1551 {
1552 uint32_t tickstart;
1553
1554 if (hi2c->State == HAL_I2C_STATE_READY)
1555 {
1556 if ((pData == NULL) || (Size == 0U))
1557 {
1558 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1559 return HAL_ERROR;
1560 }
1561 /* Process Locked */
1562 __HAL_LOCK(hi2c);
1563
1564 /* Init tickstart for timeout management*/
1565 tickstart = HAL_GetTick();
1566
1567 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1568 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1569 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1570
1571 /* Prepare transfer parameters */
1572 hi2c->pBuffPtr = pData;
1573 hi2c->XferCount = Size;
1574 hi2c->XferSize = hi2c->XferCount;
1575 hi2c->XferISR = NULL;
1576
1577 /* Enable Address Acknowledge */
1578 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1579
1580 /* Wait until ADDR flag is set */
1581 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1582 {
1583 /* Disable Address Acknowledge */
1584 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1585 return HAL_ERROR;
1586 }
1587
1588 /* Clear ADDR flag */
1589 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1590
1591 /* Wait until DIR flag is reset Receiver mode */
1592 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1593 {
1594 /* Disable Address Acknowledge */
1595 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1596 return HAL_ERROR;
1597 }
1598
1599 while (hi2c->XferCount > 0U)
1600 {
1601 /* Wait until RXNE flag is set */
1602 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1603 {
1604 /* Disable Address Acknowledge */
1605 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1606
1607 /* Store Last receive data if any */
1608 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1609 {
1610 /* Read data from RXDR */
1611 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1612
1613 /* Increment Buffer pointer */
1614 hi2c->pBuffPtr++;
1615
1616 hi2c->XferCount--;
1617 hi2c->XferSize--;
1618 }
1619
1620 return HAL_ERROR;
1621 }
1622
1623 /* Read data from RXDR */
1624 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1625
1626 /* Increment Buffer pointer */
1627 hi2c->pBuffPtr++;
1628
1629 hi2c->XferCount--;
1630 hi2c->XferSize--;
1631 }
1632
1633 /* Wait until STOP flag is set */
1634 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1635 {
1636 /* Disable Address Acknowledge */
1637 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1638 return HAL_ERROR;
1639 }
1640
1641 /* Clear STOP flag */
1642 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1643
1644 /* Wait until BUSY flag is reset */
1645 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1646 {
1647 /* Disable Address Acknowledge */
1648 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1649 return HAL_ERROR;
1650 }
1651
1652 /* Disable Address Acknowledge */
1653 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1654
1655 hi2c->State = HAL_I2C_STATE_READY;
1656 hi2c->Mode = HAL_I2C_MODE_NONE;
1657
1658 /* Process Unlocked */
1659 __HAL_UNLOCK(hi2c);
1660
1661 return HAL_OK;
1662 }
1663 else
1664 {
1665 return HAL_BUSY;
1666 }
1667 }
1668
1669 /**
1670 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1671 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1672 * the configuration information for the specified I2C.
1673 * @param DevAddress Target device address: The device 7 bits address value
1674 * in datasheet must be shifted to the left before calling the interface
1675 * @param pData Pointer to data buffer
1676 * @param Size Amount of data to be sent
1677 * @retval HAL status
1678 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1679 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1680 uint16_t Size)
1681 {
1682 uint32_t xfermode;
1683
1684 if (hi2c->State == HAL_I2C_STATE_READY)
1685 {
1686 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1687 {
1688 return HAL_BUSY;
1689 }
1690
1691 /* Process Locked */
1692 __HAL_LOCK(hi2c);
1693
1694 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1695 hi2c->Mode = HAL_I2C_MODE_MASTER;
1696 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1697
1698 /* Prepare transfer parameters */
1699 hi2c->pBuffPtr = pData;
1700 hi2c->XferCount = Size;
1701 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1702 hi2c->XferISR = I2C_Master_ISR_IT;
1703
1704 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1705 {
1706 hi2c->XferSize = MAX_NBYTE_SIZE;
1707 xfermode = I2C_RELOAD_MODE;
1708 }
1709 else
1710 {
1711 hi2c->XferSize = hi2c->XferCount;
1712 xfermode = I2C_AUTOEND_MODE;
1713 }
1714
1715 /* Send Slave Address */
1716 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1717 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1718
1719 /* Process Unlocked */
1720 __HAL_UNLOCK(hi2c);
1721
1722 /* Note : The I2C interrupts must be enabled after unlocking current process
1723 to avoid the risk of I2C interrupt handle execution before current
1724 process unlock */
1725
1726 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1727 /* possible to enable all of these */
1728 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1729 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1730 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1731
1732 return HAL_OK;
1733 }
1734 else
1735 {
1736 return HAL_BUSY;
1737 }
1738 }
1739
1740 /**
1741 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1742 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1743 * the configuration information for the specified I2C.
1744 * @param DevAddress Target device address: The device 7 bits address value
1745 * in datasheet must be shifted to the left before calling the interface
1746 * @param pData Pointer to data buffer
1747 * @param Size Amount of data to be sent
1748 * @retval HAL status
1749 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1750 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1751 uint16_t Size)
1752 {
1753 uint32_t xfermode;
1754
1755 if (hi2c->State == HAL_I2C_STATE_READY)
1756 {
1757 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1758 {
1759 return HAL_BUSY;
1760 }
1761
1762 /* Process Locked */
1763 __HAL_LOCK(hi2c);
1764
1765 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1766 hi2c->Mode = HAL_I2C_MODE_MASTER;
1767 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1768
1769 /* Prepare transfer parameters */
1770 hi2c->pBuffPtr = pData;
1771 hi2c->XferCount = Size;
1772 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1773 hi2c->XferISR = I2C_Master_ISR_IT;
1774
1775 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1776 {
1777 hi2c->XferSize = MAX_NBYTE_SIZE;
1778 xfermode = I2C_RELOAD_MODE;
1779 }
1780 else
1781 {
1782 hi2c->XferSize = hi2c->XferCount;
1783 xfermode = I2C_AUTOEND_MODE;
1784 }
1785
1786 /* Send Slave Address */
1787 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1788 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1789
1790 /* Process Unlocked */
1791 __HAL_UNLOCK(hi2c);
1792
1793 /* Note : The I2C interrupts must be enabled after unlocking current process
1794 to avoid the risk of I2C interrupt handle execution before current
1795 process unlock */
1796
1797 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1798 /* possible to enable all of these */
1799 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1800 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1801 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1802
1803 return HAL_OK;
1804 }
1805 else
1806 {
1807 return HAL_BUSY;
1808 }
1809 }
1810
1811 /**
1812 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1813 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1814 * the configuration information for the specified I2C.
1815 * @param pData Pointer to data buffer
1816 * @param Size Amount of data to be sent
1817 * @retval HAL status
1818 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1819 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1820 {
1821 if (hi2c->State == HAL_I2C_STATE_READY)
1822 {
1823 /* Process Locked */
1824 __HAL_LOCK(hi2c);
1825
1826 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1827 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1828 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1829
1830 /* Enable Address Acknowledge */
1831 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1832
1833 /* Prepare transfer parameters */
1834 hi2c->pBuffPtr = pData;
1835 hi2c->XferCount = Size;
1836 hi2c->XferSize = hi2c->XferCount;
1837 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1838 hi2c->XferISR = I2C_Slave_ISR_IT;
1839
1840 /* Preload TX data if no stretch enable */
1841 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1842 {
1843 /* Preload TX register */
1844 /* Write data to TXDR */
1845 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1846
1847 /* Increment Buffer pointer */
1848 hi2c->pBuffPtr++;
1849
1850 hi2c->XferCount--;
1851 hi2c->XferSize--;
1852 }
1853
1854 /* Process Unlocked */
1855 __HAL_UNLOCK(hi2c);
1856
1857 /* Note : The I2C interrupts must be enabled after unlocking current process
1858 to avoid the risk of I2C interrupt handle execution before current
1859 process unlock */
1860
1861 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1862 /* possible to enable all of these */
1863 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1864 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1865 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1866
1867 return HAL_OK;
1868 }
1869 else
1870 {
1871 return HAL_BUSY;
1872 }
1873 }
1874
1875 /**
1876 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1877 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1878 * the configuration information for the specified I2C.
1879 * @param pData Pointer to data buffer
1880 * @param Size Amount of data to be sent
1881 * @retval HAL status
1882 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1883 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1884 {
1885 if (hi2c->State == HAL_I2C_STATE_READY)
1886 {
1887 /* Process Locked */
1888 __HAL_LOCK(hi2c);
1889
1890 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1891 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1892 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1893
1894 /* Enable Address Acknowledge */
1895 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1896
1897 /* Prepare transfer parameters */
1898 hi2c->pBuffPtr = pData;
1899 hi2c->XferCount = Size;
1900 hi2c->XferSize = hi2c->XferCount;
1901 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1902 hi2c->XferISR = I2C_Slave_ISR_IT;
1903
1904 /* Process Unlocked */
1905 __HAL_UNLOCK(hi2c);
1906
1907 /* Note : The I2C interrupts must be enabled after unlocking current process
1908 to avoid the risk of I2C interrupt handle execution before current
1909 process unlock */
1910
1911 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1912 /* possible to enable all of these */
1913 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1914 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1915 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1916
1917 return HAL_OK;
1918 }
1919 else
1920 {
1921 return HAL_BUSY;
1922 }
1923 }
1924
1925 #if defined(HAL_DMA_MODULE_ENABLED)
1926 /**
1927 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1928 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1929 * the configuration information for the specified I2C.
1930 * @param DevAddress Target device address: The device 7 bits address value
1931 * in datasheet must be shifted to the left before calling the interface
1932 * @param pData Pointer to data buffer
1933 * @param Size Amount of data to be sent
1934 * @retval HAL status
1935 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1936 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1937 uint16_t Size)
1938 {
1939 uint32_t xfermode;
1940 HAL_StatusTypeDef dmaxferstatus;
1941
1942 if (hi2c->State == HAL_I2C_STATE_READY)
1943 {
1944 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1945 {
1946 return HAL_BUSY;
1947 }
1948
1949 /* Process Locked */
1950 __HAL_LOCK(hi2c);
1951
1952 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1953 hi2c->Mode = HAL_I2C_MODE_MASTER;
1954 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1955
1956 /* Prepare transfer parameters */
1957 hi2c->pBuffPtr = pData;
1958 hi2c->XferCount = Size;
1959 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1960 hi2c->XferISR = I2C_Master_ISR_DMA;
1961
1962 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1963 {
1964 hi2c->XferSize = MAX_NBYTE_SIZE;
1965 xfermode = I2C_RELOAD_MODE;
1966 }
1967 else
1968 {
1969 hi2c->XferSize = hi2c->XferCount;
1970 xfermode = I2C_AUTOEND_MODE;
1971 }
1972
1973 if (hi2c->XferSize > 0U)
1974 {
1975 if (hi2c->hdmatx != NULL)
1976 {
1977 /* Set the I2C DMA transfer complete callback */
1978 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
1979
1980 /* Set the DMA error callback */
1981 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1982
1983 /* Set the unused DMA callbacks to NULL */
1984 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1985 hi2c->hdmatx->XferAbortCallback = NULL;
1986
1987 /* Enable the DMA channel */
1988 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1989 {
1990 if (hi2c->hdmatx->LinkedListQueue != NULL)
1991 {
1992 /* Set DMA data size */
1993 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
1994
1995 /* Set DMA source address */
1996 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
1997
1998 /* Set DMA destination address */
1999 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
2000 = (uint32_t)&hi2c->Instance->TXDR;
2001
2002 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
2003 }
2004 else
2005 {
2006 /* Update I2C state */
2007 hi2c->State = HAL_I2C_STATE_READY;
2008 hi2c->Mode = HAL_I2C_MODE_NONE;
2009
2010 /* Update I2C error code */
2011 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2012
2013 /* Process Unlocked */
2014 __HAL_UNLOCK(hi2c);
2015
2016 return HAL_ERROR;
2017 }
2018 }
2019 else
2020 {
2021 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
2022 hi2c->XferSize);
2023 }
2024 }
2025 else
2026 {
2027 /* Update I2C state */
2028 hi2c->State = HAL_I2C_STATE_READY;
2029 hi2c->Mode = HAL_I2C_MODE_NONE;
2030
2031 /* Update I2C error code */
2032 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2033
2034 /* Process Unlocked */
2035 __HAL_UNLOCK(hi2c);
2036
2037 return HAL_ERROR;
2038 }
2039
2040 if (dmaxferstatus == HAL_OK)
2041 {
2042 /* Send Slave Address */
2043 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2044 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
2045
2046 /* Update XferCount value */
2047 hi2c->XferCount -= hi2c->XferSize;
2048
2049 /* Process Unlocked */
2050 __HAL_UNLOCK(hi2c);
2051
2052 /* Note : The I2C interrupts must be enabled after unlocking current process
2053 to avoid the risk of I2C interrupt handle execution before current
2054 process unlock */
2055 /* Enable ERR and NACK interrupts */
2056 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2057
2058 /* Enable DMA Request */
2059 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2060 }
2061 else
2062 {
2063 /* Update I2C state */
2064 hi2c->State = HAL_I2C_STATE_READY;
2065 hi2c->Mode = HAL_I2C_MODE_NONE;
2066
2067 /* Update I2C error code */
2068 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2069
2070 /* Process Unlocked */
2071 __HAL_UNLOCK(hi2c);
2072
2073 return HAL_ERROR;
2074 }
2075 }
2076 else
2077 {
2078 /* Update Transfer ISR function pointer */
2079 hi2c->XferISR = I2C_Master_ISR_IT;
2080
2081 /* Send Slave Address */
2082 /* Set NBYTES to write and generate START condition */
2083 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2084 I2C_GENERATE_START_WRITE);
2085
2086 /* Process Unlocked */
2087 __HAL_UNLOCK(hi2c);
2088
2089 /* Note : The I2C interrupts must be enabled after unlocking current process
2090 to avoid the risk of I2C interrupt handle execution before current
2091 process unlock */
2092 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2093 /* possible to enable all of these */
2094 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2095 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2096 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2097 }
2098
2099 return HAL_OK;
2100 }
2101 else
2102 {
2103 return HAL_BUSY;
2104 }
2105 }
2106
2107 /**
2108 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2109 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2110 * the configuration information for the specified I2C.
2111 * @param DevAddress Target device address: The device 7 bits address value
2112 * in datasheet must be shifted to the left before calling the interface
2113 * @param pData Pointer to data buffer
2114 * @param Size Amount of data to be sent
2115 * @retval HAL status
2116 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2117 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
2118 uint16_t Size)
2119 {
2120 uint32_t xfermode;
2121 HAL_StatusTypeDef dmaxferstatus;
2122
2123 if (hi2c->State == HAL_I2C_STATE_READY)
2124 {
2125 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2126 {
2127 return HAL_BUSY;
2128 }
2129
2130 /* Process Locked */
2131 __HAL_LOCK(hi2c);
2132
2133 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2134 hi2c->Mode = HAL_I2C_MODE_MASTER;
2135 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2136
2137 /* Prepare transfer parameters */
2138 hi2c->pBuffPtr = pData;
2139 hi2c->XferCount = Size;
2140 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2141 hi2c->XferISR = I2C_Master_ISR_DMA;
2142
2143 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2144 {
2145 hi2c->XferSize = MAX_NBYTE_SIZE;
2146 xfermode = I2C_RELOAD_MODE;
2147 }
2148 else
2149 {
2150 hi2c->XferSize = hi2c->XferCount;
2151 xfermode = I2C_AUTOEND_MODE;
2152 }
2153
2154 if (hi2c->XferSize > 0U)
2155 {
2156 if (hi2c->hdmarx != NULL)
2157 {
2158 /* Set the I2C DMA transfer complete callback */
2159 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2160
2161 /* Set the DMA error callback */
2162 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2163
2164 /* Set the unused DMA callbacks to NULL */
2165 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2166 hi2c->hdmarx->XferAbortCallback = NULL;
2167
2168 /* Enable the DMA channel */
2169 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2170 {
2171 if (hi2c->hdmarx->LinkedListQueue != NULL)
2172 {
2173 /* Set DMA data size */
2174 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2175
2176 /* Set DMA source address */
2177 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
2178 = (uint32_t)&hi2c->Instance->RXDR;
2179
2180 /* Set DMA destination address */
2181 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
2182
2183 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
2184 }
2185 else
2186 {
2187 /* Update I2C state */
2188 hi2c->State = HAL_I2C_STATE_READY;
2189 hi2c->Mode = HAL_I2C_MODE_NONE;
2190
2191 /* Update I2C error code */
2192 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2193
2194 /* Process Unlocked */
2195 __HAL_UNLOCK(hi2c);
2196
2197 return HAL_ERROR;
2198 }
2199 }
2200 else
2201 {
2202 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2203 hi2c->XferSize);
2204 }
2205 }
2206 else
2207 {
2208 /* Update I2C state */
2209 hi2c->State = HAL_I2C_STATE_READY;
2210 hi2c->Mode = HAL_I2C_MODE_NONE;
2211
2212 /* Update I2C error code */
2213 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2214
2215 /* Process Unlocked */
2216 __HAL_UNLOCK(hi2c);
2217
2218 return HAL_ERROR;
2219 }
2220
2221 if (dmaxferstatus == HAL_OK)
2222 {
2223 /* Send Slave Address */
2224 /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2225 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2226
2227 /* Update XferCount value */
2228 hi2c->XferCount -= hi2c->XferSize;
2229
2230 /* Process Unlocked */
2231 __HAL_UNLOCK(hi2c);
2232
2233 /* Note : The I2C interrupts must be enabled after unlocking current process
2234 to avoid the risk of I2C interrupt handle execution before current
2235 process unlock */
2236 /* Enable ERR and NACK interrupts */
2237 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2238
2239 /* Enable DMA Request */
2240 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2241 }
2242 else
2243 {
2244 /* Update I2C state */
2245 hi2c->State = HAL_I2C_STATE_READY;
2246 hi2c->Mode = HAL_I2C_MODE_NONE;
2247
2248 /* Update I2C error code */
2249 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2250
2251 /* Process Unlocked */
2252 __HAL_UNLOCK(hi2c);
2253
2254 return HAL_ERROR;
2255 }
2256 }
2257 else
2258 {
2259 /* Update Transfer ISR function pointer */
2260 hi2c->XferISR = I2C_Master_ISR_IT;
2261
2262 /* Send Slave Address */
2263 /* Set NBYTES to read and generate START condition */
2264 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2265 I2C_GENERATE_START_READ);
2266
2267 /* Process Unlocked */
2268 __HAL_UNLOCK(hi2c);
2269
2270 /* Note : The I2C interrupts must be enabled after unlocking current process
2271 to avoid the risk of I2C interrupt handle execution before current
2272 process unlock */
2273 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2274 /* possible to enable all of these */
2275 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2276 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2277 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
2278 }
2279
2280 return HAL_OK;
2281 }
2282 else
2283 {
2284 return HAL_BUSY;
2285 }
2286 }
2287
2288 /**
2289 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2290 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2291 * the configuration information for the specified I2C.
2292 * @param pData Pointer to data buffer
2293 * @param Size Amount of data to be sent
2294 * @retval HAL status
2295 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2296 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2297 {
2298 HAL_StatusTypeDef dmaxferstatus;
2299
2300 if (hi2c->State == HAL_I2C_STATE_READY)
2301 {
2302 if ((pData == NULL) || (Size == 0U))
2303 {
2304 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2305 return HAL_ERROR;
2306 }
2307 /* Process Locked */
2308 __HAL_LOCK(hi2c);
2309
2310 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2311 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2312 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2313
2314 /* Prepare transfer parameters */
2315 hi2c->pBuffPtr = pData;
2316 hi2c->XferCount = Size;
2317 hi2c->XferSize = hi2c->XferCount;
2318 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2319 hi2c->XferISR = I2C_Slave_ISR_DMA;
2320
2321 /* Preload TX data if no stretch enable */
2322 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
2323 {
2324 /* Preload TX register */
2325 /* Write data to TXDR */
2326 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2327
2328 /* Increment Buffer pointer */
2329 hi2c->pBuffPtr++;
2330
2331 hi2c->XferCount--;
2332 hi2c->XferSize--;
2333 }
2334
2335 if (hi2c->XferCount != 0U)
2336 {
2337 if (hi2c->hdmatx != NULL)
2338 {
2339 /* Set the I2C DMA transfer complete callback */
2340 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
2341
2342 /* Set the DMA error callback */
2343 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2344
2345 /* Set the unused DMA callbacks to NULL */
2346 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2347 hi2c->hdmatx->XferAbortCallback = NULL;
2348
2349 /* Enable the DMA channel */
2350 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2351 {
2352 if (hi2c->hdmatx->LinkedListQueue != NULL)
2353 {
2354 /* Set DMA data size */
2355 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2356
2357 /* Set DMA source address */
2358 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
2359
2360 /* Set DMA destination address */
2361 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
2362 = (uint32_t)&hi2c->Instance->TXDR;
2363
2364 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
2365 }
2366 else
2367 {
2368 /* Update I2C state */
2369 hi2c->State = HAL_I2C_STATE_LISTEN;
2370 hi2c->Mode = HAL_I2C_MODE_NONE;
2371
2372 /* Update I2C error code */
2373 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2374
2375 /* Process Unlocked */
2376 __HAL_UNLOCK(hi2c);
2377
2378 return HAL_ERROR;
2379 }
2380 }
2381 else
2382 {
2383 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
2384 (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
2385 hi2c->XferSize);
2386 }
2387 }
2388 else
2389 {
2390 /* Update I2C state */
2391 hi2c->State = HAL_I2C_STATE_LISTEN;
2392 hi2c->Mode = HAL_I2C_MODE_NONE;
2393
2394 /* Update I2C error code */
2395 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2396
2397 /* Process Unlocked */
2398 __HAL_UNLOCK(hi2c);
2399
2400 return HAL_ERROR;
2401 }
2402
2403 if (dmaxferstatus == HAL_OK)
2404 {
2405 /* Enable Address Acknowledge */
2406 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2407
2408 /* Process Unlocked */
2409 __HAL_UNLOCK(hi2c);
2410
2411 /* Note : The I2C interrupts must be enabled after unlocking current process
2412 to avoid the risk of I2C interrupt handle execution before current
2413 process unlock */
2414 /* Enable ERR, STOP, NACK, ADDR interrupts */
2415 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2416
2417 /* Enable DMA Request */
2418 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2419 }
2420 else
2421 {
2422 /* Update I2C state */
2423 hi2c->State = HAL_I2C_STATE_LISTEN;
2424 hi2c->Mode = HAL_I2C_MODE_NONE;
2425
2426 /* Update I2C error code */
2427 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2428
2429 /* Process Unlocked */
2430 __HAL_UNLOCK(hi2c);
2431
2432 return HAL_ERROR;
2433 }
2434 }
2435 else
2436 {
2437 /* Enable Address Acknowledge */
2438 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2439
2440 /* Process Unlocked */
2441 __HAL_UNLOCK(hi2c);
2442
2443 /* Note : The I2C interrupts must be enabled after unlocking current process
2444 to avoid the risk of I2C interrupt handle execution before current
2445 process unlock */
2446 /* Enable ERR, STOP, NACK, ADDR interrupts */
2447 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2448 }
2449
2450 return HAL_OK;
2451 }
2452 else
2453 {
2454 return HAL_BUSY;
2455 }
2456 }
2457
2458 /**
2459 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2460 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2461 * the configuration information for the specified I2C.
2462 * @param pData Pointer to data buffer
2463 * @param Size Amount of data to be sent
2464 * @retval HAL status
2465 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2466 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2467 {
2468 HAL_StatusTypeDef dmaxferstatus;
2469
2470 if (hi2c->State == HAL_I2C_STATE_READY)
2471 {
2472 if ((pData == NULL) || (Size == 0U))
2473 {
2474 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2475 return HAL_ERROR;
2476 }
2477 /* Process Locked */
2478 __HAL_LOCK(hi2c);
2479
2480 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2481 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2482 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2483
2484 /* Prepare transfer parameters */
2485 hi2c->pBuffPtr = pData;
2486 hi2c->XferCount = Size;
2487 hi2c->XferSize = hi2c->XferCount;
2488 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2489 hi2c->XferISR = I2C_Slave_ISR_DMA;
2490
2491 if (hi2c->hdmarx != NULL)
2492 {
2493 /* Set the I2C DMA transfer complete callback */
2494 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
2495
2496 /* Set the DMA error callback */
2497 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2498
2499 /* Set the unused DMA callbacks to NULL */
2500 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2501 hi2c->hdmarx->XferAbortCallback = NULL;
2502
2503 /* Enable the DMA channel */
2504 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2505 {
2506 if (hi2c->hdmarx->LinkedListQueue != NULL)
2507 {
2508 /* Set DMA data size */
2509 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2510
2511 /* Set DMA source address */
2512 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
2513 = (uint32_t)&hi2c->Instance->RXDR;
2514
2515 /* Set DMA destination address */
2516 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
2517
2518 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
2519 }
2520 else
2521 {
2522 /* Update I2C state */
2523 hi2c->State = HAL_I2C_STATE_LISTEN;
2524 hi2c->Mode = HAL_I2C_MODE_NONE;
2525
2526 /* Update I2C error code */
2527 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2528
2529 /* Process Unlocked */
2530 __HAL_UNLOCK(hi2c);
2531
2532 return HAL_ERROR;
2533 }
2534 }
2535 else
2536 {
2537 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2538 hi2c->XferSize);
2539 }
2540 }
2541 else
2542 {
2543 /* Update I2C state */
2544 hi2c->State = HAL_I2C_STATE_LISTEN;
2545 hi2c->Mode = HAL_I2C_MODE_NONE;
2546
2547 /* Update I2C error code */
2548 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2549
2550 /* Process Unlocked */
2551 __HAL_UNLOCK(hi2c);
2552
2553 return HAL_ERROR;
2554 }
2555
2556 if (dmaxferstatus == HAL_OK)
2557 {
2558 /* Enable Address Acknowledge */
2559 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2560
2561 /* Process Unlocked */
2562 __HAL_UNLOCK(hi2c);
2563
2564 /* Note : The I2C interrupts must be enabled after unlocking current process
2565 to avoid the risk of I2C interrupt handle execution before current
2566 process unlock */
2567 /* Enable ERR, STOP, NACK, ADDR interrupts */
2568 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2569
2570 /* Enable DMA Request */
2571 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2572 }
2573 else
2574 {
2575 /* Update I2C state */
2576 hi2c->State = HAL_I2C_STATE_LISTEN;
2577 hi2c->Mode = HAL_I2C_MODE_NONE;
2578
2579 /* Update I2C error code */
2580 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2581
2582 /* Process Unlocked */
2583 __HAL_UNLOCK(hi2c);
2584
2585 return HAL_ERROR;
2586 }
2587
2588 return HAL_OK;
2589 }
2590 else
2591 {
2592 return HAL_BUSY;
2593 }
2594 }
2595 #endif /* HAL_DMA_MODULE_ENABLED */
2596
2597 /**
2598 * @brief Write an amount of data in blocking mode to a specific memory address
2599 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2600 * the configuration information for the specified I2C.
2601 * @param DevAddress Target device address: The device 7 bits address value
2602 * in datasheet must be shifted to the left before calling the interface
2603 * @param MemAddress Internal memory address
2604 * @param MemAddSize Size of internal memory address
2605 * @param pData Pointer to data buffer
2606 * @param Size Amount of data to be sent
2607 * @param Timeout Timeout duration
2608 * @retval HAL status
2609 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2610 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2611 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2612 {
2613 uint32_t tickstart;
2614
2615 /* Check the parameters */
2616 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2617
2618 if (hi2c->State == HAL_I2C_STATE_READY)
2619 {
2620 if ((pData == NULL) || (Size == 0U))
2621 {
2622 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2623 return HAL_ERROR;
2624 }
2625
2626 /* Process Locked */
2627 __HAL_LOCK(hi2c);
2628
2629 /* Init tickstart for timeout management*/
2630 tickstart = HAL_GetTick();
2631
2632 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2633 {
2634 return HAL_ERROR;
2635 }
2636
2637 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2638 hi2c->Mode = HAL_I2C_MODE_MEM;
2639 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2640
2641 /* Prepare transfer parameters */
2642 hi2c->pBuffPtr = pData;
2643 hi2c->XferCount = Size;
2644 hi2c->XferISR = NULL;
2645
2646 /* Send Slave Address and Memory Address */
2647 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2648 {
2649 /* Process Unlocked */
2650 __HAL_UNLOCK(hi2c);
2651 return HAL_ERROR;
2652 }
2653
2654 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
2655 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2656 {
2657 hi2c->XferSize = MAX_NBYTE_SIZE;
2658 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2659 }
2660 else
2661 {
2662 hi2c->XferSize = hi2c->XferCount;
2663 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2664 }
2665
2666 do
2667 {
2668 /* Wait until TXIS flag is set */
2669 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2670 {
2671 return HAL_ERROR;
2672 }
2673
2674 /* Write data to TXDR */
2675 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2676
2677 /* Increment Buffer pointer */
2678 hi2c->pBuffPtr++;
2679
2680 hi2c->XferCount--;
2681 hi2c->XferSize--;
2682
2683 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2684 {
2685 /* Wait until TCR flag is set */
2686 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2687 {
2688 return HAL_ERROR;
2689 }
2690
2691 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2692 {
2693 hi2c->XferSize = MAX_NBYTE_SIZE;
2694 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2695 I2C_NO_STARTSTOP);
2696 }
2697 else
2698 {
2699 hi2c->XferSize = hi2c->XferCount;
2700 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2701 I2C_NO_STARTSTOP);
2702 }
2703 }
2704
2705 } while (hi2c->XferCount > 0U);
2706
2707 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2708 /* Wait until STOPF flag is reset */
2709 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2710 {
2711 return HAL_ERROR;
2712 }
2713
2714 /* Clear STOP Flag */
2715 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2716
2717 /* Clear Configuration Register 2 */
2718 I2C_RESET_CR2(hi2c);
2719
2720 hi2c->State = HAL_I2C_STATE_READY;
2721 hi2c->Mode = HAL_I2C_MODE_NONE;
2722
2723 /* Process Unlocked */
2724 __HAL_UNLOCK(hi2c);
2725
2726 return HAL_OK;
2727 }
2728 else
2729 {
2730 return HAL_BUSY;
2731 }
2732 }
2733
2734 /**
2735 * @brief Read an amount of data in blocking mode from a specific memory address
2736 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2737 * the configuration information for the specified I2C.
2738 * @param DevAddress Target device address: The device 7 bits address value
2739 * in datasheet must be shifted to the left before calling the interface
2740 * @param MemAddress Internal memory address
2741 * @param MemAddSize Size of internal memory address
2742 * @param pData Pointer to data buffer
2743 * @param Size Amount of data to be sent
2744 * @param Timeout Timeout duration
2745 * @retval HAL status
2746 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2747 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2748 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2749 {
2750 uint32_t tickstart;
2751
2752 /* Check the parameters */
2753 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2754
2755 if (hi2c->State == HAL_I2C_STATE_READY)
2756 {
2757 if ((pData == NULL) || (Size == 0U))
2758 {
2759 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2760 return HAL_ERROR;
2761 }
2762
2763 /* Process Locked */
2764 __HAL_LOCK(hi2c);
2765
2766 /* Init tickstart for timeout management*/
2767 tickstart = HAL_GetTick();
2768
2769 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2770 {
2771 return HAL_ERROR;
2772 }
2773
2774 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2775 hi2c->Mode = HAL_I2C_MODE_MEM;
2776 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2777
2778 /* Prepare transfer parameters */
2779 hi2c->pBuffPtr = pData;
2780 hi2c->XferCount = Size;
2781 hi2c->XferISR = NULL;
2782
2783 /* Send Slave Address and Memory Address */
2784 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2785 {
2786 /* Process Unlocked */
2787 __HAL_UNLOCK(hi2c);
2788 return HAL_ERROR;
2789 }
2790
2791 /* Send Slave Address */
2792 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2793 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2794 {
2795 hi2c->XferSize = MAX_NBYTE_SIZE;
2796 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2797 I2C_GENERATE_START_READ);
2798 }
2799 else
2800 {
2801 hi2c->XferSize = hi2c->XferCount;
2802 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2803 I2C_GENERATE_START_READ);
2804 }
2805
2806 do
2807 {
2808 /* Wait until RXNE flag is set */
2809 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
2810 {
2811 return HAL_ERROR;
2812 }
2813
2814 /* Read data from RXDR */
2815 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
2816
2817 /* Increment Buffer pointer */
2818 hi2c->pBuffPtr++;
2819
2820 hi2c->XferSize--;
2821 hi2c->XferCount--;
2822
2823 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2824 {
2825 /* Wait until TCR flag is set */
2826 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2827 {
2828 return HAL_ERROR;
2829 }
2830
2831 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2832 {
2833 hi2c->XferSize = MAX_NBYTE_SIZE;
2834 I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
2835 I2C_NO_STARTSTOP);
2836 }
2837 else
2838 {
2839 hi2c->XferSize = hi2c->XferCount;
2840 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2841 I2C_NO_STARTSTOP);
2842 }
2843 }
2844 } while (hi2c->XferCount > 0U);
2845
2846 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2847 /* Wait until STOPF flag is reset */
2848 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2849 {
2850 return HAL_ERROR;
2851 }
2852
2853 /* Clear STOP Flag */
2854 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2855
2856 /* Clear Configuration Register 2 */
2857 I2C_RESET_CR2(hi2c);
2858
2859 hi2c->State = HAL_I2C_STATE_READY;
2860 hi2c->Mode = HAL_I2C_MODE_NONE;
2861
2862 /* Process Unlocked */
2863 __HAL_UNLOCK(hi2c);
2864
2865 return HAL_OK;
2866 }
2867 else
2868 {
2869 return HAL_BUSY;
2870 }
2871 }
2872 /**
2873 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2874 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2875 * the configuration information for the specified I2C.
2876 * @param DevAddress Target device address: The device 7 bits address value
2877 * in datasheet must be shifted to the left before calling the interface
2878 * @param MemAddress Internal memory address
2879 * @param MemAddSize Size of internal memory address
2880 * @param pData Pointer to data buffer
2881 * @param Size Amount of data to be sent
2882 * @retval HAL status
2883 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2884 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2885 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2886 {
2887 /* Check the parameters */
2888 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2889
2890 if (hi2c->State == HAL_I2C_STATE_READY)
2891 {
2892 if ((pData == NULL) || (Size == 0U))
2893 {
2894 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2895 return HAL_ERROR;
2896 }
2897
2898 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2899 {
2900 return HAL_BUSY;
2901 }
2902
2903 /* Process Locked */
2904 __HAL_LOCK(hi2c);
2905
2906 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2907 hi2c->Mode = HAL_I2C_MODE_MEM;
2908 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2909
2910 /* Prepare transfer parameters */
2911 hi2c->XferSize = 0U;
2912 hi2c->pBuffPtr = pData;
2913 hi2c->XferCount = Size;
2914 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2915 hi2c->XferISR = I2C_Mem_ISR_IT;
2916 hi2c->Devaddress = DevAddress;
2917
2918 /* If Memory address size is 8Bit */
2919 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2920 {
2921 /* Prefetch Memory Address */
2922 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2923
2924 /* Reset Memaddress content */
2925 hi2c->Memaddress = 0xFFFFFFFFU;
2926 }
2927 /* If Memory address size is 16Bit */
2928 else
2929 {
2930 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2931 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2932
2933 /* Prepare Memaddress buffer for LSB part */
2934 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2935 }
2936 /* Send Slave Address and Memory Address */
2937 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2938
2939 /* Process Unlocked */
2940 __HAL_UNLOCK(hi2c);
2941
2942 /* Note : The I2C interrupts must be enabled after unlocking current process
2943 to avoid the risk of I2C interrupt handle execution before current
2944 process unlock */
2945
2946 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2947 /* possible to enable all of these */
2948 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2949 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2950 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2951
2952 return HAL_OK;
2953 }
2954 else
2955 {
2956 return HAL_BUSY;
2957 }
2958 }
2959
2960 /**
2961 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2962 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2963 * the configuration information for the specified I2C.
2964 * @param DevAddress Target device address: The device 7 bits address value
2965 * in datasheet must be shifted to the left before calling the interface
2966 * @param MemAddress Internal memory address
2967 * @param MemAddSize Size of internal memory address
2968 * @param pData Pointer to data buffer
2969 * @param Size Amount of data to be sent
2970 * @retval HAL status
2971 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2972 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2973 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2974 {
2975 /* Check the parameters */
2976 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2977
2978 if (hi2c->State == HAL_I2C_STATE_READY)
2979 {
2980 if ((pData == NULL) || (Size == 0U))
2981 {
2982 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2983 return HAL_ERROR;
2984 }
2985
2986 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2987 {
2988 return HAL_BUSY;
2989 }
2990
2991 /* Process Locked */
2992 __HAL_LOCK(hi2c);
2993
2994 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2995 hi2c->Mode = HAL_I2C_MODE_MEM;
2996 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2997
2998 /* Prepare transfer parameters */
2999 hi2c->pBuffPtr = pData;
3000 hi2c->XferCount = Size;
3001 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3002 hi2c->XferISR = I2C_Mem_ISR_IT;
3003 hi2c->Devaddress = DevAddress;
3004
3005 /* If Memory address size is 8Bit */
3006 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3007 {
3008 /* Prefetch Memory Address */
3009 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3010
3011 /* Reset Memaddress content */
3012 hi2c->Memaddress = 0xFFFFFFFFU;
3013 }
3014 /* If Memory address size is 16Bit */
3015 else
3016 {
3017 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3018 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3019
3020 /* Prepare Memaddress buffer for LSB part */
3021 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3022 }
3023 /* Send Slave Address and Memory Address */
3024 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3025
3026 /* Process Unlocked */
3027 __HAL_UNLOCK(hi2c);
3028
3029 /* Note : The I2C interrupts must be enabled after unlocking current process
3030 to avoid the risk of I2C interrupt handle execution before current
3031 process unlock */
3032
3033 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3034 /* possible to enable all of these */
3035 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3036 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3037 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3038
3039 return HAL_OK;
3040 }
3041 else
3042 {
3043 return HAL_BUSY;
3044 }
3045 }
3046
3047 #if defined(HAL_DMA_MODULE_ENABLED)
3048 /**
3049 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
3050 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3051 * the configuration information for the specified I2C.
3052 * @param DevAddress Target device address: The device 7 bits address value
3053 * in datasheet must be shifted to the left before calling the interface
3054 * @param MemAddress Internal memory address
3055 * @param MemAddSize Size of internal memory address
3056 * @param pData Pointer to data buffer
3057 * @param Size Amount of data to be sent
3058 * @retval HAL status
3059 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3060 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3061 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3062 {
3063 HAL_StatusTypeDef dmaxferstatus;
3064
3065 /* Check the parameters */
3066 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3067
3068 if (hi2c->State == HAL_I2C_STATE_READY)
3069 {
3070 if ((pData == NULL) || (Size == 0U))
3071 {
3072 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3073 return HAL_ERROR;
3074 }
3075
3076 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3077 {
3078 return HAL_BUSY;
3079 }
3080
3081 /* Process Locked */
3082 __HAL_LOCK(hi2c);
3083
3084 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3085 hi2c->Mode = HAL_I2C_MODE_MEM;
3086 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3087
3088 /* Prepare transfer parameters */
3089 hi2c->pBuffPtr = pData;
3090 hi2c->XferCount = Size;
3091 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3092 hi2c->XferISR = I2C_Mem_ISR_DMA;
3093 hi2c->Devaddress = DevAddress;
3094
3095 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3096 {
3097 hi2c->XferSize = MAX_NBYTE_SIZE;
3098 }
3099 else
3100 {
3101 hi2c->XferSize = hi2c->XferCount;
3102 }
3103
3104 /* If Memory address size is 8Bit */
3105 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3106 {
3107 /* Prefetch Memory Address */
3108 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3109
3110 /* Reset Memaddress content */
3111 hi2c->Memaddress = 0xFFFFFFFFU;
3112 }
3113 /* If Memory address size is 16Bit */
3114 else
3115 {
3116 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3117 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3118
3119 /* Prepare Memaddress buffer for LSB part */
3120 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3121 }
3122
3123 if (hi2c->hdmatx != NULL)
3124 {
3125 /* Set the I2C DMA transfer complete callback */
3126 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3127
3128 /* Set the DMA error callback */
3129 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3130
3131 /* Set the unused DMA callbacks to NULL */
3132 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3133 hi2c->hdmatx->XferAbortCallback = NULL;
3134
3135 /* Enable the DMA channel */
3136 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3137 {
3138 if (hi2c->hdmatx->LinkedListQueue != NULL)
3139 {
3140 /* Set DMA data size */
3141 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3142
3143 /* Set DMA source address */
3144 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
3145
3146 /* Set DMA destination address */
3147 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
3148 = (uint32_t)&hi2c->Instance->TXDR;
3149
3150 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
3151 }
3152 else
3153 {
3154 /* Update I2C state */
3155 hi2c->State = HAL_I2C_STATE_READY;
3156 hi2c->Mode = HAL_I2C_MODE_NONE;
3157
3158 /* Update I2C error code */
3159 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3160
3161 /* Process Unlocked */
3162 __HAL_UNLOCK(hi2c);
3163
3164 return HAL_ERROR;
3165 }
3166 }
3167 else
3168 {
3169 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3170 hi2c->XferSize);
3171 }
3172 }
3173 else
3174 {
3175 /* Update I2C state */
3176 hi2c->State = HAL_I2C_STATE_READY;
3177 hi2c->Mode = HAL_I2C_MODE_NONE;
3178
3179 /* Update I2C error code */
3180 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3181
3182 /* Process Unlocked */
3183 __HAL_UNLOCK(hi2c);
3184
3185 return HAL_ERROR;
3186 }
3187
3188 if (dmaxferstatus == HAL_OK)
3189 {
3190 /* Send Slave Address and Memory Address */
3191 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
3192
3193 /* Process Unlocked */
3194 __HAL_UNLOCK(hi2c);
3195
3196 /* Note : The I2C interrupts must be enabled after unlocking current process
3197 to avoid the risk of I2C interrupt handle execution before current
3198 process unlock */
3199 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3200 /* possible to enable all of these */
3201 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3202 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3203 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3204 }
3205 else
3206 {
3207 /* Update I2C state */
3208 hi2c->State = HAL_I2C_STATE_READY;
3209 hi2c->Mode = HAL_I2C_MODE_NONE;
3210
3211 /* Update I2C error code */
3212 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3213
3214 /* Process Unlocked */
3215 __HAL_UNLOCK(hi2c);
3216
3217 return HAL_ERROR;
3218 }
3219
3220 return HAL_OK;
3221 }
3222 else
3223 {
3224 return HAL_BUSY;
3225 }
3226 }
3227
3228 /**
3229 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3230 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3231 * the configuration information for the specified I2C.
3232 * @param DevAddress Target device address: The device 7 bits address value
3233 * in datasheet must be shifted to the left before calling the interface
3234 * @param MemAddress Internal memory address
3235 * @param MemAddSize Size of internal memory address
3236 * @param pData Pointer to data buffer
3237 * @param Size Amount of data to be read
3238 * @retval HAL status
3239 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3240 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3241 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3242 {
3243 HAL_StatusTypeDef dmaxferstatus;
3244
3245 /* Check the parameters */
3246 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3247
3248 if (hi2c->State == HAL_I2C_STATE_READY)
3249 {
3250 if ((pData == NULL) || (Size == 0U))
3251 {
3252 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3253 return HAL_ERROR;
3254 }
3255
3256 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3257 {
3258 return HAL_BUSY;
3259 }
3260
3261 /* Process Locked */
3262 __HAL_LOCK(hi2c);
3263
3264 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3265 hi2c->Mode = HAL_I2C_MODE_MEM;
3266 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3267
3268 /* Prepare transfer parameters */
3269 hi2c->pBuffPtr = pData;
3270 hi2c->XferCount = Size;
3271 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3272 hi2c->XferISR = I2C_Mem_ISR_DMA;
3273 hi2c->Devaddress = DevAddress;
3274
3275 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3276 {
3277 hi2c->XferSize = MAX_NBYTE_SIZE;
3278 }
3279 else
3280 {
3281 hi2c->XferSize = hi2c->XferCount;
3282 }
3283
3284 /* If Memory address size is 8Bit */
3285 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3286 {
3287 /* Prefetch Memory Address */
3288 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3289
3290 /* Reset Memaddress content */
3291 hi2c->Memaddress = 0xFFFFFFFFU;
3292 }
3293 /* If Memory address size is 16Bit */
3294 else
3295 {
3296 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3297 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3298
3299 /* Prepare Memaddress buffer for LSB part */
3300 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3301 }
3302
3303 if (hi2c->hdmarx != NULL)
3304 {
3305 /* Set the I2C DMA transfer complete callback */
3306 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3307
3308 /* Set the DMA error callback */
3309 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3310
3311 /* Set the unused DMA callbacks to NULL */
3312 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3313 hi2c->hdmarx->XferAbortCallback = NULL;
3314
3315 /* Enable the DMA channel */
3316 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3317 {
3318 if (hi2c->hdmarx->LinkedListQueue != NULL)
3319 {
3320 /* Set DMA data size */
3321 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3322
3323 /* Set DMA source address */
3324 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
3325 = (uint32_t)&hi2c->Instance->RXDR;
3326
3327 /* Set DMA destination address */
3328 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
3329
3330 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
3331 }
3332 else
3333 {
3334 /* Update I2C state */
3335 hi2c->State = HAL_I2C_STATE_READY;
3336 hi2c->Mode = HAL_I2C_MODE_NONE;
3337
3338 /* Update I2C error code */
3339 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3340
3341 /* Process Unlocked */
3342 __HAL_UNLOCK(hi2c);
3343
3344 return HAL_ERROR;
3345 }
3346 }
3347 else
3348 {
3349 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3350 hi2c->XferSize);
3351 }
3352 }
3353 else
3354 {
3355 /* Update I2C state */
3356 hi2c->State = HAL_I2C_STATE_READY;
3357 hi2c->Mode = HAL_I2C_MODE_NONE;
3358
3359 /* Update I2C error code */
3360 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3361
3362 /* Process Unlocked */
3363 __HAL_UNLOCK(hi2c);
3364
3365 return HAL_ERROR;
3366 }
3367
3368 if (dmaxferstatus == HAL_OK)
3369 {
3370 /* Send Slave Address and Memory Address */
3371 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3372
3373 /* Process Unlocked */
3374 __HAL_UNLOCK(hi2c);
3375
3376 /* Note : The I2C interrupts must be enabled after unlocking current process
3377 to avoid the risk of I2C interrupt handle execution before current
3378 process unlock */
3379 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3380 /* possible to enable all of these */
3381 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3382 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3383 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3384 }
3385 else
3386 {
3387 /* Update I2C state */
3388 hi2c->State = HAL_I2C_STATE_READY;
3389 hi2c->Mode = HAL_I2C_MODE_NONE;
3390
3391 /* Update I2C error code */
3392 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3393
3394 /* Process Unlocked */
3395 __HAL_UNLOCK(hi2c);
3396
3397 return HAL_ERROR;
3398 }
3399
3400 return HAL_OK;
3401 }
3402 else
3403 {
3404 return HAL_BUSY;
3405 }
3406 }
3407 #endif /* HAL_DMA_MODULE_ENABLED */
3408
3409 /**
3410 * @brief Checks if target device is ready for communication.
3411 * @note This function is used with Memory devices
3412 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3413 * the configuration information for the specified I2C.
3414 * @param DevAddress Target device address: The device 7 bits address value
3415 * in datasheet must be shifted to the left before calling the interface
3416 * @param Trials Number of trials
3417 * @param Timeout Timeout duration
3418 * @retval HAL status
3419 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3420 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
3421 uint32_t Timeout)
3422 {
3423 uint32_t tickstart;
3424
3425 __IO uint32_t I2C_Trials = 0UL;
3426
3427 FlagStatus tmp1;
3428 FlagStatus tmp2;
3429
3430 if (hi2c->State == HAL_I2C_STATE_READY)
3431 {
3432 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3433 {
3434 return HAL_BUSY;
3435 }
3436
3437 /* Process Locked */
3438 __HAL_LOCK(hi2c);
3439
3440 hi2c->State = HAL_I2C_STATE_BUSY;
3441 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3442
3443 do
3444 {
3445 /* Generate Start */
3446 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
3447
3448 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
3449 /* Wait until STOPF flag is set or a NACK flag is set*/
3450 tickstart = HAL_GetTick();
3451
3452 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3453 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3454
3455 while ((tmp1 == RESET) && (tmp2 == RESET))
3456 {
3457 if (Timeout != HAL_MAX_DELAY)
3458 {
3459 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3460 {
3461 /* Update I2C state */
3462 hi2c->State = HAL_I2C_STATE_READY;
3463
3464 /* Update I2C error code */
3465 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3466
3467 /* Process Unlocked */
3468 __HAL_UNLOCK(hi2c);
3469
3470 return HAL_ERROR;
3471 }
3472 }
3473
3474 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3475 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3476 }
3477
3478 /* Check if the NACKF flag has not been set */
3479 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
3480 {
3481 /* Wait until STOPF flag is reset */
3482 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3483 {
3484 return HAL_ERROR;
3485 }
3486
3487 /* Clear STOP Flag */
3488 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3489
3490 /* Device is ready */
3491 hi2c->State = HAL_I2C_STATE_READY;
3492
3493 /* Process Unlocked */
3494 __HAL_UNLOCK(hi2c);
3495
3496 return HAL_OK;
3497 }
3498 else
3499 {
3500 /* Wait until STOPF flag is reset */
3501 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3502 {
3503 return HAL_ERROR;
3504 }
3505
3506 /* Clear NACK Flag */
3507 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3508
3509 /* Clear STOP Flag, auto generated with autoend*/
3510 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3511 }
3512
3513 /* Increment Trials */
3514 I2C_Trials++;
3515 } while (I2C_Trials < Trials);
3516
3517 /* Update I2C state */
3518 hi2c->State = HAL_I2C_STATE_READY;
3519
3520 /* Update I2C error code */
3521 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3522
3523 /* Process Unlocked */
3524 __HAL_UNLOCK(hi2c);
3525
3526 return HAL_ERROR;
3527 }
3528 else
3529 {
3530 return HAL_BUSY;
3531 }
3532 }
3533
3534 /**
3535 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3536 * @note This interface allow to manage repeated start condition when a direction change during transfer
3537 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3538 * the configuration information for the specified I2C.
3539 * @param DevAddress Target device address: The device 7 bits address value
3540 * in datasheet must be shifted to the left before calling the interface
3541 * @param pData Pointer to data buffer
3542 * @param Size Amount of data to be sent
3543 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3544 * @retval HAL status
3545 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3546 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3547 uint16_t Size, uint32_t XferOptions)
3548 {
3549 uint32_t xfermode;
3550 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3551
3552 /* Check the parameters */
3553 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3554
3555 if (hi2c->State == HAL_I2C_STATE_READY)
3556 {
3557 /* Process Locked */
3558 __HAL_LOCK(hi2c);
3559
3560 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3561 hi2c->Mode = HAL_I2C_MODE_MASTER;
3562 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3563
3564 /* Prepare transfer parameters */
3565 hi2c->pBuffPtr = pData;
3566 hi2c->XferCount = Size;
3567 hi2c->XferOptions = XferOptions;
3568 hi2c->XferISR = I2C_Master_ISR_IT;
3569
3570 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3571 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3572 {
3573 hi2c->XferSize = MAX_NBYTE_SIZE;
3574 xfermode = I2C_RELOAD_MODE;
3575 }
3576 else
3577 {
3578 hi2c->XferSize = hi2c->XferCount;
3579 xfermode = hi2c->XferOptions;
3580 }
3581
3582 /* If transfer direction not change and there is no request to start another frame,
3583 do not generate Restart Condition */
3584 /* Mean Previous state is same as current state */
3585 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3586 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3587 {
3588 xferrequest = I2C_NO_STARTSTOP;
3589 }
3590 else
3591 {
3592 /* Convert OTHER_xxx XferOptions if any */
3593 I2C_ConvertOtherXferOptions(hi2c);
3594
3595 /* Update xfermode accordingly if no reload is necessary */
3596 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3597 {
3598 xfermode = hi2c->XferOptions;
3599 }
3600 }
3601
3602 /* Send Slave Address and set NBYTES to write */
3603 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3604
3605 /* Process Unlocked */
3606 __HAL_UNLOCK(hi2c);
3607
3608 /* Note : The I2C interrupts must be enabled after unlocking current process
3609 to avoid the risk of I2C interrupt handle execution before current
3610 process unlock */
3611 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3612 /* possible to enable all of these */
3613 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3614 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3615 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3616
3617 return HAL_OK;
3618 }
3619 else
3620 {
3621 return HAL_BUSY;
3622 }
3623 }
3624
3625 #if defined(HAL_DMA_MODULE_ENABLED)
3626 /**
3627 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3628 * @note This interface allow to manage repeated start condition when a direction change during transfer
3629 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3630 * the configuration information for the specified I2C.
3631 * @param DevAddress Target device address: The device 7 bits address value
3632 * in datasheet must be shifted to the left before calling the interface
3633 * @param pData Pointer to data buffer
3634 * @param Size Amount of data to be sent
3635 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3636 * @retval HAL status
3637 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3638 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3639 uint16_t Size, uint32_t XferOptions)
3640 {
3641 uint32_t xfermode;
3642 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3643 HAL_StatusTypeDef dmaxferstatus;
3644
3645 /* Check the parameters */
3646 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3647
3648 if (hi2c->State == HAL_I2C_STATE_READY)
3649 {
3650 /* Process Locked */
3651 __HAL_LOCK(hi2c);
3652
3653 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3654 hi2c->Mode = HAL_I2C_MODE_MASTER;
3655 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3656
3657 /* Prepare transfer parameters */
3658 hi2c->pBuffPtr = pData;
3659 hi2c->XferCount = Size;
3660 hi2c->XferOptions = XferOptions;
3661 hi2c->XferISR = I2C_Master_ISR_DMA;
3662
3663 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3664 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3665 {
3666 hi2c->XferSize = MAX_NBYTE_SIZE;
3667 xfermode = I2C_RELOAD_MODE;
3668 }
3669 else
3670 {
3671 hi2c->XferSize = hi2c->XferCount;
3672 xfermode = hi2c->XferOptions;
3673 }
3674
3675 /* If transfer direction not change and there is no request to start another frame,
3676 do not generate Restart Condition */
3677 /* Mean Previous state is same as current state */
3678 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3679 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3680 {
3681 xferrequest = I2C_NO_STARTSTOP;
3682 }
3683 else
3684 {
3685 /* Convert OTHER_xxx XferOptions if any */
3686 I2C_ConvertOtherXferOptions(hi2c);
3687
3688 /* Update xfermode accordingly if no reload is necessary */
3689 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3690 {
3691 xfermode = hi2c->XferOptions;
3692 }
3693 }
3694
3695 if (hi2c->XferSize > 0U)
3696 {
3697 if (hi2c->hdmatx != NULL)
3698 {
3699 /* Set the I2C DMA transfer complete callback */
3700 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3701
3702 /* Set the DMA error callback */
3703 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3704
3705 /* Set the unused DMA callbacks to NULL */
3706 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3707 hi2c->hdmatx->XferAbortCallback = NULL;
3708
3709 /* Enable the DMA channel */
3710 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3711 {
3712 if (hi2c->hdmatx->LinkedListQueue != NULL)
3713 {
3714 /* Set DMA data size */
3715 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3716
3717 /* Set DMA source address */
3718 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
3719
3720 /* Set DMA destination address */
3721 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
3722 = (uint32_t)&hi2c->Instance->TXDR;
3723
3724 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
3725 }
3726 else
3727 {
3728 /* Update I2C state */
3729 hi2c->State = HAL_I2C_STATE_READY;
3730 hi2c->Mode = HAL_I2C_MODE_NONE;
3731
3732 /* Update I2C error code */
3733 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3734
3735 /* Process Unlocked */
3736 __HAL_UNLOCK(hi2c);
3737
3738 return HAL_ERROR;
3739 }
3740 }
3741 else
3742 {
3743 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3744 hi2c->XferSize);
3745 }
3746 }
3747 else
3748 {
3749 /* Update I2C state */
3750 hi2c->State = HAL_I2C_STATE_READY;
3751 hi2c->Mode = HAL_I2C_MODE_NONE;
3752
3753 /* Update I2C error code */
3754 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3755
3756 /* Process Unlocked */
3757 __HAL_UNLOCK(hi2c);
3758
3759 return HAL_ERROR;
3760 }
3761
3762 if (dmaxferstatus == HAL_OK)
3763 {
3764 /* Send Slave Address and set NBYTES to write */
3765 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3766
3767 /* Update XferCount value */
3768 hi2c->XferCount -= hi2c->XferSize;
3769
3770 /* Process Unlocked */
3771 __HAL_UNLOCK(hi2c);
3772
3773 /* Note : The I2C interrupts must be enabled after unlocking current process
3774 to avoid the risk of I2C interrupt handle execution before current
3775 process unlock */
3776 /* Enable ERR and NACK interrupts */
3777 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3778
3779 /* Enable DMA Request */
3780 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3781 }
3782 else
3783 {
3784 /* Update I2C state */
3785 hi2c->State = HAL_I2C_STATE_READY;
3786 hi2c->Mode = HAL_I2C_MODE_NONE;
3787
3788 /* Update I2C error code */
3789 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3790
3791 /* Process Unlocked */
3792 __HAL_UNLOCK(hi2c);
3793
3794 return HAL_ERROR;
3795 }
3796 }
3797 else
3798 {
3799 /* Update Transfer ISR function pointer */
3800 hi2c->XferISR = I2C_Master_ISR_IT;
3801
3802 /* Send Slave Address */
3803 /* Set NBYTES to write and generate START condition */
3804 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3805 I2C_GENERATE_START_WRITE);
3806
3807 /* Process Unlocked */
3808 __HAL_UNLOCK(hi2c);
3809
3810 /* Note : The I2C interrupts must be enabled after unlocking current process
3811 to avoid the risk of I2C interrupt handle execution before current
3812 process unlock */
3813 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3814 /* possible to enable all of these */
3815 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3816 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3817 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3818 }
3819
3820 return HAL_OK;
3821 }
3822 else
3823 {
3824 return HAL_BUSY;
3825 }
3826 }
3827 #endif /* HAL_DMA_MODULE_ENABLED */
3828
3829 /**
3830 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3831 * @note This interface allow to manage repeated start condition when a direction change during transfer
3832 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3833 * the configuration information for the specified I2C.
3834 * @param DevAddress Target device address: The device 7 bits address value
3835 * in datasheet must be shifted to the left before calling the interface
3836 * @param pData Pointer to data buffer
3837 * @param Size Amount of data to be sent
3838 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3839 * @retval HAL status
3840 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3841 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3842 uint16_t Size, uint32_t XferOptions)
3843 {
3844 uint32_t xfermode;
3845 uint32_t xferrequest = I2C_GENERATE_START_READ;
3846
3847 /* Check the parameters */
3848 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3849
3850 if (hi2c->State == HAL_I2C_STATE_READY)
3851 {
3852 /* Process Locked */
3853 __HAL_LOCK(hi2c);
3854
3855 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3856 hi2c->Mode = HAL_I2C_MODE_MASTER;
3857 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3858
3859 /* Prepare transfer parameters */
3860 hi2c->pBuffPtr = pData;
3861 hi2c->XferCount = Size;
3862 hi2c->XferOptions = XferOptions;
3863 hi2c->XferISR = I2C_Master_ISR_IT;
3864
3865 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3866 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3867 {
3868 hi2c->XferSize = MAX_NBYTE_SIZE;
3869 xfermode = I2C_RELOAD_MODE;
3870 }
3871 else
3872 {
3873 hi2c->XferSize = hi2c->XferCount;
3874 xfermode = hi2c->XferOptions;
3875 }
3876
3877 /* If transfer direction not change and there is no request to start another frame,
3878 do not generate Restart Condition */
3879 /* Mean Previous state is same as current state */
3880 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3881 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3882 {
3883 xferrequest = I2C_NO_STARTSTOP;
3884 }
3885 else
3886 {
3887 /* Convert OTHER_xxx XferOptions if any */
3888 I2C_ConvertOtherXferOptions(hi2c);
3889
3890 /* Update xfermode accordingly if no reload is necessary */
3891 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3892 {
3893 xfermode = hi2c->XferOptions;
3894 }
3895 }
3896
3897 /* Send Slave Address and set NBYTES to read */
3898 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3899
3900 /* Process Unlocked */
3901 __HAL_UNLOCK(hi2c);
3902
3903 /* Note : The I2C interrupts must be enabled after unlocking current process
3904 to avoid the risk of I2C interrupt handle execution before current
3905 process unlock */
3906 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3907
3908 return HAL_OK;
3909 }
3910 else
3911 {
3912 return HAL_BUSY;
3913 }
3914 }
3915
3916 #if defined(HAL_DMA_MODULE_ENABLED)
3917 /**
3918 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
3919 * @note This interface allow to manage repeated start condition when a direction change during transfer
3920 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3921 * the configuration information for the specified I2C.
3922 * @param DevAddress Target device address: The device 7 bits address value
3923 * in datasheet must be shifted to the left before calling the interface
3924 * @param pData Pointer to data buffer
3925 * @param Size Amount of data to be sent
3926 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3927 * @retval HAL status
3928 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3929 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3930 uint16_t Size, uint32_t XferOptions)
3931 {
3932 uint32_t xfermode;
3933 uint32_t xferrequest = I2C_GENERATE_START_READ;
3934 HAL_StatusTypeDef dmaxferstatus;
3935
3936 /* Check the parameters */
3937 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3938
3939 if (hi2c->State == HAL_I2C_STATE_READY)
3940 {
3941 /* Process Locked */
3942 __HAL_LOCK(hi2c);
3943
3944 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3945 hi2c->Mode = HAL_I2C_MODE_MASTER;
3946 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3947
3948 /* Prepare transfer parameters */
3949 hi2c->pBuffPtr = pData;
3950 hi2c->XferCount = Size;
3951 hi2c->XferOptions = XferOptions;
3952 hi2c->XferISR = I2C_Master_ISR_DMA;
3953
3954 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3955 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3956 {
3957 hi2c->XferSize = MAX_NBYTE_SIZE;
3958 xfermode = I2C_RELOAD_MODE;
3959 }
3960 else
3961 {
3962 hi2c->XferSize = hi2c->XferCount;
3963 xfermode = hi2c->XferOptions;
3964 }
3965
3966 /* If transfer direction not change and there is no request to start another frame,
3967 do not generate Restart Condition */
3968 /* Mean Previous state is same as current state */
3969 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3970 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3971 {
3972 xferrequest = I2C_NO_STARTSTOP;
3973 }
3974 else
3975 {
3976 /* Convert OTHER_xxx XferOptions if any */
3977 I2C_ConvertOtherXferOptions(hi2c);
3978
3979 /* Update xfermode accordingly if no reload is necessary */
3980 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3981 {
3982 xfermode = hi2c->XferOptions;
3983 }
3984 }
3985
3986 if (hi2c->XferSize > 0U)
3987 {
3988 if (hi2c->hdmarx != NULL)
3989 {
3990 /* Set the I2C DMA transfer complete callback */
3991 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3992
3993 /* Set the DMA error callback */
3994 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3995
3996 /* Set the unused DMA callbacks to NULL */
3997 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3998 hi2c->hdmarx->XferAbortCallback = NULL;
3999
4000 /* Enable the DMA channel */
4001 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
4002 {
4003 if (hi2c->hdmarx->LinkedListQueue != NULL)
4004 {
4005 /* Set DMA data size */
4006 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
4007
4008 /* Set DMA source address */
4009 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
4010 = (uint32_t)&hi2c->Instance->RXDR;
4011
4012 /* Set DMA destination address */
4013 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
4014
4015 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
4016 }
4017 else
4018 {
4019 hi2c->State = HAL_I2C_STATE_READY;
4020 hi2c->Mode = HAL_I2C_MODE_NONE;
4021
4022 /* Update I2C error code */
4023 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4024
4025 /* Process Unlocked */
4026 __HAL_UNLOCK(hi2c);
4027
4028 return HAL_ERROR;
4029 }
4030 }
4031 else
4032 {
4033 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
4034 hi2c->XferSize);
4035 }
4036 }
4037 else
4038 {
4039 /* Update I2C state */
4040 hi2c->State = HAL_I2C_STATE_READY;
4041 hi2c->Mode = HAL_I2C_MODE_NONE;
4042
4043 /* Update I2C error code */
4044 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4045
4046 /* Process Unlocked */
4047 __HAL_UNLOCK(hi2c);
4048
4049 return HAL_ERROR;
4050 }
4051
4052 if (dmaxferstatus == HAL_OK)
4053 {
4054 /* Send Slave Address and set NBYTES to read */
4055 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
4056
4057 /* Update XferCount value */
4058 hi2c->XferCount -= hi2c->XferSize;
4059
4060 /* Process Unlocked */
4061 __HAL_UNLOCK(hi2c);
4062
4063 /* Note : The I2C interrupts must be enabled after unlocking current process
4064 to avoid the risk of I2C interrupt handle execution before current
4065 process unlock */
4066 /* Enable ERR and NACK interrupts */
4067 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
4068
4069 /* Enable DMA Request */
4070 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4071 }
4072 else
4073 {
4074 /* Update I2C state */
4075 hi2c->State = HAL_I2C_STATE_READY;
4076 hi2c->Mode = HAL_I2C_MODE_NONE;
4077
4078 /* Update I2C error code */
4079 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4080
4081 /* Process Unlocked */
4082 __HAL_UNLOCK(hi2c);
4083
4084 return HAL_ERROR;
4085 }
4086 }
4087 else
4088 {
4089 /* Update Transfer ISR function pointer */
4090 hi2c->XferISR = I2C_Master_ISR_IT;
4091
4092 /* Send Slave Address */
4093 /* Set NBYTES to read and generate START condition */
4094 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
4095 I2C_GENERATE_START_READ);
4096
4097 /* Process Unlocked */
4098 __HAL_UNLOCK(hi2c);
4099
4100 /* Note : The I2C interrupts must be enabled after unlocking current process
4101 to avoid the risk of I2C interrupt handle execution before current
4102 process unlock */
4103 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
4104 /* possible to enable all of these */
4105 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
4106 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
4107 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
4108 }
4109
4110 return HAL_OK;
4111 }
4112 else
4113 {
4114 return HAL_BUSY;
4115 }
4116 }
4117 #endif /* HAL_DMA_MODULE_ENABLED */
4118
4119 /**
4120 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4121 * @note This interface allow to manage repeated start condition when a direction change during transfer
4122 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4123 * the configuration information for the specified I2C.
4124 * @param pData Pointer to data buffer
4125 * @param Size Amount of data to be sent
4126 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4127 * @retval HAL status
4128 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4129 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4130 uint32_t XferOptions)
4131 {
4132 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4133 FlagStatus tmp;
4134
4135 /* Check the parameters */
4136 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4137
4138 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4139 {
4140 if ((pData == NULL) || (Size == 0U))
4141 {
4142 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4143 return HAL_ERROR;
4144 }
4145
4146 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4147 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4148
4149 /* Process Locked */
4150 __HAL_LOCK(hi2c);
4151
4152 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4153 /* and then toggle the HAL slave RX state to TX state */
4154 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4155 {
4156 /* Disable associated Interrupts */
4157 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4158
4159 #if defined(HAL_DMA_MODULE_ENABLED)
4160 /* Abort DMA Xfer if any */
4161 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4162 {
4163 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4164
4165 if (hi2c->hdmarx != NULL)
4166 {
4167 /* Set the I2C DMA Abort callback :
4168 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4169 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4170
4171 /* Abort DMA RX */
4172 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4173 {
4174 /* Call Directly XferAbortCallback function in case of error */
4175 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4176 }
4177 }
4178 }
4179 #endif /* HAL_DMA_MODULE_ENABLED */
4180 }
4181
4182 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4183 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4184 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4185
4186 /* Enable Address Acknowledge */
4187 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4188
4189 /* Prepare transfer parameters */
4190 hi2c->pBuffPtr = pData;
4191 hi2c->XferCount = Size;
4192 hi2c->XferSize = hi2c->XferCount;
4193 hi2c->XferOptions = XferOptions;
4194 hi2c->XferISR = I2C_Slave_ISR_IT;
4195
4196 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4197 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4198 {
4199 /* Clear ADDR flag after prepare the transfer parameters */
4200 /* This action will generate an acknowledge to the Master */
4201 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4202 }
4203
4204 /* Process Unlocked */
4205 __HAL_UNLOCK(hi2c);
4206
4207 /* Note : The I2C interrupts must be enabled after unlocking current process
4208 to avoid the risk of I2C interrupt handle execution before current
4209 process unlock */
4210 /* REnable ADDR interrupt */
4211 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
4212
4213 return HAL_OK;
4214 }
4215 else
4216 {
4217 return HAL_ERROR;
4218 }
4219 }
4220
4221 #if defined(HAL_DMA_MODULE_ENABLED)
4222 /**
4223 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
4224 * @note This interface allow to manage repeated start condition when a direction change during transfer
4225 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4226 * the configuration information for the specified I2C.
4227 * @param pData Pointer to data buffer
4228 * @param Size Amount of data to be sent
4229 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4230 * @retval HAL status
4231 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4232 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4233 uint32_t XferOptions)
4234 {
4235 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4236 FlagStatus tmp;
4237 HAL_StatusTypeDef dmaxferstatus;
4238
4239 /* Check the parameters */
4240 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4241
4242 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4243 {
4244 if ((pData == NULL) || (Size == 0U))
4245 {
4246 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4247 return HAL_ERROR;
4248 }
4249
4250 /* Process Locked */
4251 __HAL_LOCK(hi2c);
4252
4253 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4254 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4255
4256 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4257 /* and then toggle the HAL slave RX state to TX state */
4258 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4259 {
4260 /* Disable associated Interrupts */
4261 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4262
4263 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4264 {
4265 /* Abort DMA Xfer if any */
4266 if (hi2c->hdmarx != NULL)
4267 {
4268 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4269
4270 /* Set the I2C DMA Abort callback :
4271 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4272 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4273
4274 /* Abort DMA RX */
4275 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4276 {
4277 /* Call Directly XferAbortCallback function in case of error */
4278 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4279 }
4280 }
4281 }
4282 }
4283 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4284 {
4285 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4286 {
4287 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4288
4289 /* Abort DMA Xfer if any */
4290 if (hi2c->hdmatx != NULL)
4291 {
4292 /* Set the I2C DMA Abort callback :
4293 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4294 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4295
4296 /* Abort DMA TX */
4297 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4298 {
4299 /* Call Directly XferAbortCallback function in case of error */
4300 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4301 }
4302 }
4303 }
4304 }
4305 else
4306 {
4307 /* Nothing to do */
4308 }
4309
4310 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4311 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4312 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4313
4314 /* Enable Address Acknowledge */
4315 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4316
4317 /* Prepare transfer parameters */
4318 hi2c->pBuffPtr = pData;
4319 hi2c->XferCount = Size;
4320 hi2c->XferSize = hi2c->XferCount;
4321 hi2c->XferOptions = XferOptions;
4322 hi2c->XferISR = I2C_Slave_ISR_DMA;
4323
4324 if (hi2c->hdmatx != NULL)
4325 {
4326 /* Set the I2C DMA transfer complete callback */
4327 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
4328
4329 /* Set the DMA error callback */
4330 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4331
4332 /* Set the unused DMA callbacks to NULL */
4333 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4334 hi2c->hdmatx->XferAbortCallback = NULL;
4335
4336 /* Enable the DMA channel */
4337 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
4338 {
4339 if (hi2c->hdmatx->LinkedListQueue != NULL)
4340 {
4341 /* Set DMA data size */
4342 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
4343
4344 /* Set DMA source address */
4345 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
4346
4347 /* Set DMA destination address */
4348 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
4349 = (uint32_t)&hi2c->Instance->TXDR;
4350
4351 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
4352 }
4353 else
4354 {
4355 /* Update I2C state */
4356 hi2c->State = HAL_I2C_STATE_LISTEN;
4357 hi2c->Mode = HAL_I2C_MODE_NONE;
4358
4359 /* Update I2C error code */
4360 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4361
4362 /* Process Unlocked */
4363 __HAL_UNLOCK(hi2c);
4364
4365 return HAL_ERROR;
4366 }
4367 }
4368 else
4369 {
4370 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
4371 hi2c->XferSize);
4372 }
4373 }
4374 else
4375 {
4376 /* Update I2C state */
4377 hi2c->State = HAL_I2C_STATE_LISTEN;
4378 hi2c->Mode = HAL_I2C_MODE_NONE;
4379
4380 /* Update I2C error code */
4381 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4382
4383 /* Process Unlocked */
4384 __HAL_UNLOCK(hi2c);
4385
4386 return HAL_ERROR;
4387 }
4388
4389 if (dmaxferstatus == HAL_OK)
4390 {
4391 /* Update XferCount value */
4392 hi2c->XferCount -= hi2c->XferSize;
4393
4394 /* Reset XferSize */
4395 hi2c->XferSize = 0;
4396 }
4397 else
4398 {
4399 /* Update I2C state */
4400 hi2c->State = HAL_I2C_STATE_LISTEN;
4401 hi2c->Mode = HAL_I2C_MODE_NONE;
4402
4403 /* Update I2C error code */
4404 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4405
4406 /* Process Unlocked */
4407 __HAL_UNLOCK(hi2c);
4408
4409 return HAL_ERROR;
4410 }
4411
4412 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4413 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4414 {
4415 /* Clear ADDR flag after prepare the transfer parameters */
4416 /* This action will generate an acknowledge to the Master */
4417 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4418 }
4419
4420 /* Process Unlocked */
4421 __HAL_UNLOCK(hi2c);
4422
4423 /* Enable DMA Request */
4424 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
4425
4426 /* Note : The I2C interrupts must be enabled after unlocking current process
4427 to avoid the risk of I2C interrupt handle execution before current
4428 process unlock */
4429 /* Enable ERR, STOP, NACK, ADDR interrupts */
4430 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4431
4432 return HAL_OK;
4433 }
4434 else
4435 {
4436 return HAL_ERROR;
4437 }
4438 }
4439 #endif /* HAL_DMA_MODULE_ENABLED */
4440
4441 /**
4442 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4443 * @note This interface allow to manage repeated start condition when a direction change during transfer
4444 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4445 * the configuration information for the specified I2C.
4446 * @param pData Pointer to data buffer
4447 * @param Size Amount of data to be sent
4448 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4449 * @retval HAL status
4450 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4451 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4452 uint32_t XferOptions)
4453 {
4454 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4455 FlagStatus tmp;
4456
4457 /* Check the parameters */
4458 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4459
4460 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4461 {
4462 if ((pData == NULL) || (Size == 0U))
4463 {
4464 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4465 return HAL_ERROR;
4466 }
4467
4468 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4469 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4470
4471 /* Process Locked */
4472 __HAL_LOCK(hi2c);
4473
4474 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4475 /* and then toggle the HAL slave TX state to RX state */
4476 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4477 {
4478 /* Disable associated Interrupts */
4479 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4480
4481 #if defined(HAL_DMA_MODULE_ENABLED)
4482 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4483 {
4484 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4485
4486 /* Abort DMA Xfer if any */
4487 if (hi2c->hdmatx != NULL)
4488 {
4489 /* Set the I2C DMA Abort callback :
4490 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4491 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4492
4493 /* Abort DMA TX */
4494 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4495 {
4496 /* Call Directly XferAbortCallback function in case of error */
4497 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4498 }
4499 }
4500 }
4501 #endif /* HAL_DMA_MODULE_ENABLED */
4502 }
4503
4504 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4505 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4506 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4507
4508 /* Enable Address Acknowledge */
4509 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4510
4511 /* Prepare transfer parameters */
4512 hi2c->pBuffPtr = pData;
4513 hi2c->XferCount = Size;
4514 hi2c->XferSize = hi2c->XferCount;
4515 hi2c->XferOptions = XferOptions;
4516 hi2c->XferISR = I2C_Slave_ISR_IT;
4517
4518 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4519 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4520 {
4521 /* Clear ADDR flag after prepare the transfer parameters */
4522 /* This action will generate an acknowledge to the Master */
4523 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4524 }
4525
4526 /* Process Unlocked */
4527 __HAL_UNLOCK(hi2c);
4528
4529 /* Note : The I2C interrupts must be enabled after unlocking current process
4530 to avoid the risk of I2C interrupt handle execution before current
4531 process unlock */
4532 /* REnable ADDR interrupt */
4533 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4534
4535 return HAL_OK;
4536 }
4537 else
4538 {
4539 return HAL_ERROR;
4540 }
4541 }
4542
4543 #if defined(HAL_DMA_MODULE_ENABLED)
4544 /**
4545 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
4546 * @note This interface allow to manage repeated start condition when a direction change during transfer
4547 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4548 * the configuration information for the specified I2C.
4549 * @param pData Pointer to data buffer
4550 * @param Size Amount of data to be sent
4551 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4552 * @retval HAL status
4553 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4554 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4555 uint32_t XferOptions)
4556 {
4557 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4558 FlagStatus tmp;
4559 HAL_StatusTypeDef dmaxferstatus;
4560
4561 /* Check the parameters */
4562 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4563
4564 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4565 {
4566 if ((pData == NULL) || (Size == 0U))
4567 {
4568 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4569 return HAL_ERROR;
4570 }
4571
4572 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4573 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4574
4575 /* Process Locked */
4576 __HAL_LOCK(hi2c);
4577
4578 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4579 /* and then toggle the HAL slave TX state to RX state */
4580 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4581 {
4582 /* Disable associated Interrupts */
4583 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4584
4585 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4586 {
4587 /* Abort DMA Xfer if any */
4588 if (hi2c->hdmatx != NULL)
4589 {
4590 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4591
4592 /* Set the I2C DMA Abort callback :
4593 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4594 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4595
4596 /* Abort DMA TX */
4597 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4598 {
4599 /* Call Directly XferAbortCallback function in case of error */
4600 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4601 }
4602 }
4603 }
4604 }
4605 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4606 {
4607 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4608 {
4609 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4610
4611 /* Abort DMA Xfer if any */
4612 if (hi2c->hdmarx != NULL)
4613 {
4614 /* Set the I2C DMA Abort callback :
4615 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4616 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4617
4618 /* Abort DMA RX */
4619 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4620 {
4621 /* Call Directly XferAbortCallback function in case of error */
4622 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4623 }
4624 }
4625 }
4626 }
4627 else
4628 {
4629 /* Nothing to do */
4630 }
4631
4632 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4633 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4634 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4635
4636 /* Enable Address Acknowledge */
4637 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4638
4639 /* Prepare transfer parameters */
4640 hi2c->pBuffPtr = pData;
4641 hi2c->XferCount = Size;
4642 hi2c->XferSize = hi2c->XferCount;
4643 hi2c->XferOptions = XferOptions;
4644 hi2c->XferISR = I2C_Slave_ISR_DMA;
4645
4646 if (hi2c->hdmarx != NULL)
4647 {
4648 /* Set the I2C DMA transfer complete callback */
4649 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
4650
4651 /* Set the DMA error callback */
4652 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4653
4654 /* Set the unused DMA callbacks to NULL */
4655 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4656 hi2c->hdmarx->XferAbortCallback = NULL;
4657
4658 /* Enable the DMA channel */
4659 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
4660 {
4661 if (hi2c->hdmarx->LinkedListQueue != NULL)
4662 {
4663 /* Set DMA data size */
4664 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
4665
4666 /* Set DMA source address */
4667 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
4668 = (uint32_t)&hi2c->Instance->RXDR;
4669
4670 /* Set DMA destination address */
4671 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
4672
4673 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
4674 }
4675 else
4676 {
4677 /* Update I2C state */
4678 hi2c->State = HAL_I2C_STATE_LISTEN;
4679 hi2c->Mode = HAL_I2C_MODE_NONE;
4680
4681 /* Update I2C error code */
4682 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4683
4684 /* Process Unlocked */
4685 __HAL_UNLOCK(hi2c);
4686
4687 return HAL_ERROR;
4688 }
4689 }
4690 else
4691 {
4692 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
4693 hi2c->XferSize);
4694 }
4695 }
4696 else
4697 {
4698 /* Update I2C state */
4699 hi2c->State = HAL_I2C_STATE_LISTEN;
4700 hi2c->Mode = HAL_I2C_MODE_NONE;
4701
4702 /* Update I2C error code */
4703 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4704
4705 /* Process Unlocked */
4706 __HAL_UNLOCK(hi2c);
4707
4708 return HAL_ERROR;
4709 }
4710
4711 if (dmaxferstatus == HAL_OK)
4712 {
4713 /* Update XferCount value */
4714 hi2c->XferCount -= hi2c->XferSize;
4715
4716 /* Reset XferSize */
4717 hi2c->XferSize = 0;
4718 }
4719 else
4720 {
4721 /* Update I2C state */
4722 hi2c->State = HAL_I2C_STATE_LISTEN;
4723 hi2c->Mode = HAL_I2C_MODE_NONE;
4724
4725 /* Update I2C error code */
4726 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4727
4728 /* Process Unlocked */
4729 __HAL_UNLOCK(hi2c);
4730
4731 return HAL_ERROR;
4732 }
4733
4734 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4735 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4736 {
4737 /* Clear ADDR flag after prepare the transfer parameters */
4738 /* This action will generate an acknowledge to the Master */
4739 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4740 }
4741
4742 /* Process Unlocked */
4743 __HAL_UNLOCK(hi2c);
4744
4745 /* Enable DMA Request */
4746 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4747
4748 /* Note : The I2C interrupts must be enabled after unlocking current process
4749 to avoid the risk of I2C interrupt handle execution before current
4750 process unlock */
4751 /* REnable ADDR interrupt */
4752 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4753
4754 return HAL_OK;
4755 }
4756 else
4757 {
4758 return HAL_ERROR;
4759 }
4760 }
4761 #endif /* HAL_DMA_MODULE_ENABLED */
4762
4763 /**
4764 * @brief Enable the Address listen mode with Interrupt.
4765 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4766 * the configuration information for the specified I2C.
4767 * @retval HAL status
4768 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4769 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4770 {
4771 if (hi2c->State == HAL_I2C_STATE_READY)
4772 {
4773 hi2c->State = HAL_I2C_STATE_LISTEN;
4774 hi2c->XferISR = I2C_Slave_ISR_IT;
4775
4776 /* Enable the Address Match interrupt */
4777 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4778
4779 return HAL_OK;
4780 }
4781 else
4782 {
4783 return HAL_BUSY;
4784 }
4785 }
4786
4787 /**
4788 * @brief Disable the Address listen mode with Interrupt.
4789 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4790 * the configuration information for the specified I2C
4791 * @retval HAL status
4792 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4793 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4794 {
4795 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4796 uint32_t tmp;
4797
4798 /* Disable Address listen mode only if a transfer is not ongoing */
4799 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4800 {
4801 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4802 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4803 hi2c->State = HAL_I2C_STATE_READY;
4804 hi2c->Mode = HAL_I2C_MODE_NONE;
4805 hi2c->XferISR = NULL;
4806
4807 /* Disable the Address Match interrupt */
4808 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4809
4810 return HAL_OK;
4811 }
4812 else
4813 {
4814 return HAL_BUSY;
4815 }
4816 }
4817
4818 /**
4819 * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt.
4820 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4821 * the configuration information for the specified I2C.
4822 * @param DevAddress Target device address: The device 7 bits address value
4823 * in datasheet must be shifted to the left before calling the interface
4824 * @retval HAL status
4825 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4826 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4827 {
4828 HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
4829
4830 if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM))
4831 {
4832 /* Process Locked */
4833 __HAL_LOCK(hi2c);
4834
4835 /* Disable Interrupts and Store Previous state */
4836 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
4837 {
4838 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4839 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
4840 }
4841 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4842 {
4843 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4844 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
4845 }
4846 else
4847 {
4848 /* Do nothing */
4849 }
4850
4851 /* Set State at HAL_I2C_STATE_ABORT */
4852 hi2c->State = HAL_I2C_STATE_ABORT;
4853
4854 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
4855 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
4856 I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
4857
4858 /* Process Unlocked */
4859 __HAL_UNLOCK(hi2c);
4860
4861 /* Note : The I2C interrupts must be enabled after unlocking current process
4862 to avoid the risk of I2C interrupt handle execution before current
4863 process unlock */
4864 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4865
4866 return HAL_OK;
4867 }
4868 else
4869 {
4870 /* Wrong usage of abort function */
4871 /* This function should be used only in case of abort monitored by master device */
4872 return HAL_ERROR;
4873 }
4874 }
4875
4876 /**
4877 * @}
4878 */
4879
4880 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4881 * @{
4882 */
4883
4884 /**
4885 * @brief This function handles I2C event interrupt request.
4886 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4887 * the configuration information for the specified I2C.
4888 * @retval None
4889 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4890 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
4891 {
4892 /* Get current IT Flags and IT sources value */
4893 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4894 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4895
4896 /* I2C events treatment -------------------------------------*/
4897 if (hi2c->XferISR != NULL)
4898 {
4899 hi2c->XferISR(hi2c, itflags, itsources);
4900 }
4901 }
4902
4903 /**
4904 * @brief This function handles I2C error interrupt request.
4905 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4906 * the configuration information for the specified I2C.
4907 * @retval None
4908 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4909 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4910 {
4911 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4912 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4913 uint32_t tmperror;
4914
4915 /* I2C Bus error interrupt occurred ------------------------------------*/
4916 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
4917 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4918 {
4919 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
4920
4921 /* Clear BERR flag */
4922 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4923 }
4924
4925 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
4926 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
4927 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4928 {
4929 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
4930
4931 /* Clear OVR flag */
4932 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4933 }
4934
4935 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
4936 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
4937 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4938 {
4939 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
4940
4941 /* Clear ARLO flag */
4942 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4943 }
4944
4945 /* Store current volatile hi2c->ErrorCode, misra rule */
4946 tmperror = hi2c->ErrorCode;
4947
4948 /* Call the Error Callback in case of Error detected */
4949 if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
4950 {
4951 I2C_ITError(hi2c, tmperror);
4952 }
4953 }
4954
4955 /**
4956 * @brief Master Tx Transfer completed callback.
4957 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4958 * the configuration information for the specified I2C.
4959 * @retval None
4960 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4961 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4962 {
4963 /* Prevent unused argument(s) compilation warning */
4964 UNUSED(hi2c);
4965
4966 /* NOTE : This function should not be modified, when the callback is needed,
4967 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4968 */
4969 }
4970
4971 /**
4972 * @brief Master Rx Transfer completed callback.
4973 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4974 * the configuration information for the specified I2C.
4975 * @retval None
4976 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)4977 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4978 {
4979 /* Prevent unused argument(s) compilation warning */
4980 UNUSED(hi2c);
4981
4982 /* NOTE : This function should not be modified, when the callback is needed,
4983 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
4984 */
4985 }
4986
4987 /** @brief Slave Tx Transfer completed callback.
4988 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4989 * the configuration information for the specified I2C.
4990 * @retval None
4991 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)4992 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
4993 {
4994 /* Prevent unused argument(s) compilation warning */
4995 UNUSED(hi2c);
4996
4997 /* NOTE : This function should not be modified, when the callback is needed,
4998 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
4999 */
5000 }
5001
5002 /**
5003 * @brief Slave Rx Transfer completed callback.
5004 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5005 * the configuration information for the specified I2C.
5006 * @retval None
5007 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)5008 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
5009 {
5010 /* Prevent unused argument(s) compilation warning */
5011 UNUSED(hi2c);
5012
5013 /* NOTE : This function should not be modified, when the callback is needed,
5014 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
5015 */
5016 }
5017
5018 /**
5019 * @brief Slave Address Match callback.
5020 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5021 * the configuration information for the specified I2C.
5022 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
5023 * @param AddrMatchCode Address Match Code
5024 * @retval None
5025 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)5026 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
5027 {
5028 /* Prevent unused argument(s) compilation warning */
5029 UNUSED(hi2c);
5030 UNUSED(TransferDirection);
5031 UNUSED(AddrMatchCode);
5032
5033 /* NOTE : This function should not be modified, when the callback is needed,
5034 the HAL_I2C_AddrCallback() could be implemented in the user file
5035 */
5036 }
5037
5038 /**
5039 * @brief Listen Complete callback.
5040 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5041 * the configuration information for the specified I2C.
5042 * @retval None
5043 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)5044 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
5045 {
5046 /* Prevent unused argument(s) compilation warning */
5047 UNUSED(hi2c);
5048
5049 /* NOTE : This function should not be modified, when the callback is needed,
5050 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
5051 */
5052 }
5053
5054 /**
5055 * @brief Memory Tx Transfer completed callback.
5056 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5057 * the configuration information for the specified I2C.
5058 * @retval None
5059 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)5060 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
5061 {
5062 /* Prevent unused argument(s) compilation warning */
5063 UNUSED(hi2c);
5064
5065 /* NOTE : This function should not be modified, when the callback is needed,
5066 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
5067 */
5068 }
5069
5070 /**
5071 * @brief Memory Rx Transfer completed callback.
5072 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5073 * the configuration information for the specified I2C.
5074 * @retval None
5075 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)5076 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
5077 {
5078 /* Prevent unused argument(s) compilation warning */
5079 UNUSED(hi2c);
5080
5081 /* NOTE : This function should not be modified, when the callback is needed,
5082 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
5083 */
5084 }
5085
5086 /**
5087 * @brief I2C error callback.
5088 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5089 * the configuration information for the specified I2C.
5090 * @retval None
5091 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)5092 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
5093 {
5094 /* Prevent unused argument(s) compilation warning */
5095 UNUSED(hi2c);
5096
5097 /* NOTE : This function should not be modified, when the callback is needed,
5098 the HAL_I2C_ErrorCallback could be implemented in the user file
5099 */
5100 }
5101
5102 /**
5103 * @brief I2C abort callback.
5104 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5105 * the configuration information for the specified I2C.
5106 * @retval None
5107 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)5108 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
5109 {
5110 /* Prevent unused argument(s) compilation warning */
5111 UNUSED(hi2c);
5112
5113 /* NOTE : This function should not be modified, when the callback is needed,
5114 the HAL_I2C_AbortCpltCallback could be implemented in the user file
5115 */
5116 }
5117
5118 /**
5119 * @}
5120 */
5121
5122 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
5123 * @brief Peripheral State, Mode and Error functions
5124 *
5125 @verbatim
5126 ===============================================================================
5127 ##### Peripheral State, Mode and Error functions #####
5128 ===============================================================================
5129 [..]
5130 This subsection permit to get in run-time the status of the peripheral
5131 and the data flow.
5132
5133 @endverbatim
5134 * @{
5135 */
5136
5137 /**
5138 * @brief Return the I2C handle state.
5139 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5140 * the configuration information for the specified I2C.
5141 * @retval HAL state
5142 */
HAL_I2C_GetState(const I2C_HandleTypeDef * hi2c)5143 HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
5144 {
5145 /* Return I2C handle state */
5146 return hi2c->State;
5147 }
5148
5149 /**
5150 * @brief Returns the I2C Master, Slave, Memory or no mode.
5151 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5152 * the configuration information for I2C module
5153 * @retval HAL mode
5154 */
HAL_I2C_GetMode(const I2C_HandleTypeDef * hi2c)5155 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
5156 {
5157 return hi2c->Mode;
5158 }
5159
5160 /**
5161 * @brief Return the I2C error code.
5162 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5163 * the configuration information for the specified I2C.
5164 * @retval I2C Error Code
5165 */
HAL_I2C_GetError(const I2C_HandleTypeDef * hi2c)5166 uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
5167 {
5168 return hi2c->ErrorCode;
5169 }
5170
5171 /**
5172 * @}
5173 */
5174
5175 /**
5176 * @}
5177 */
5178
5179 /** @addtogroup I2C_Private_Functions
5180 * @{
5181 */
5182
5183 /**
5184 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
5185 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5186 * the configuration information for the specified I2C.
5187 * @param ITFlags Interrupt flags to handle.
5188 * @param ITSources Interrupt sources enabled.
5189 * @retval HAL status
5190 */
I2C_Master_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5191 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5192 uint32_t ITSources)
5193 {
5194 uint16_t devaddress;
5195 uint32_t tmpITFlags = ITFlags;
5196
5197 /* Process Locked */
5198 __HAL_LOCK(hi2c);
5199
5200 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5201 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5202 {
5203 /* Clear NACK Flag */
5204 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5205
5206 /* Set corresponding Error Code */
5207 /* No need to generate STOP, it is automatically done */
5208 /* Error callback will be send during stop flag treatment */
5209 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5210
5211 /* Flush TX register */
5212 I2C_Flush_TXDR(hi2c);
5213 }
5214 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5215 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5216 {
5217 /* Remove RXNE flag on temporary variable as read done */
5218 tmpITFlags &= ~I2C_FLAG_RXNE;
5219
5220 /* Read data from RXDR */
5221 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5222
5223 /* Increment Buffer pointer */
5224 hi2c->pBuffPtr++;
5225
5226 hi2c->XferSize--;
5227 hi2c->XferCount--;
5228 }
5229 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5230 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5231 {
5232 /* Write data to TXDR */
5233 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5234
5235 /* Increment Buffer pointer */
5236 hi2c->pBuffPtr++;
5237
5238 hi2c->XferSize--;
5239 hi2c->XferCount--;
5240 }
5241 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5242 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5243 {
5244 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5245 {
5246 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5247
5248 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5249 {
5250 hi2c->XferSize = MAX_NBYTE_SIZE;
5251 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5252 }
5253 else
5254 {
5255 hi2c->XferSize = hi2c->XferCount;
5256 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5257 {
5258 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5259 hi2c->XferOptions, I2C_NO_STARTSTOP);
5260 }
5261 else
5262 {
5263 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5264 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5265 }
5266 }
5267 }
5268 else
5269 {
5270 /* Call TxCpltCallback() if no stop mode is set */
5271 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5272 {
5273 /* Call I2C Master Sequential complete process */
5274 I2C_ITMasterSeqCplt(hi2c);
5275 }
5276 else
5277 {
5278 /* Wrong size Status regarding TCR flag event */
5279 /* Call the corresponding callback to inform upper layer of End of Transfer */
5280 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5281 }
5282 }
5283 }
5284 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5285 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5286 {
5287 if (hi2c->XferCount == 0U)
5288 {
5289 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5290 {
5291 /* Generate a stop condition in case of no transfer option */
5292 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5293 {
5294 /* Generate Stop */
5295 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5296 }
5297 else
5298 {
5299 /* Call I2C Master Sequential complete process */
5300 I2C_ITMasterSeqCplt(hi2c);
5301 }
5302 }
5303 }
5304 else
5305 {
5306 /* Wrong size Status regarding TC flag event */
5307 /* Call the corresponding callback to inform upper layer of End of Transfer */
5308 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5309 }
5310 }
5311 else
5312 {
5313 /* Nothing to do */
5314 }
5315
5316 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5317 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5318 {
5319 /* Call I2C Master complete process */
5320 I2C_ITMasterCplt(hi2c, tmpITFlags);
5321 }
5322
5323 /* Process Unlocked */
5324 __HAL_UNLOCK(hi2c);
5325
5326 return HAL_OK;
5327 }
5328
5329 /**
5330 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
5331 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5332 * the configuration information for the specified I2C.
5333 * @param ITFlags Interrupt flags to handle.
5334 * @param ITSources Interrupt sources enabled.
5335 * @retval HAL status
5336 */
I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5337 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5338 uint32_t ITSources)
5339 {
5340 uint32_t direction = I2C_GENERATE_START_WRITE;
5341 uint32_t tmpITFlags = ITFlags;
5342
5343 /* Process Locked */
5344 __HAL_LOCK(hi2c);
5345
5346 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5347 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5348 {
5349 /* Clear NACK Flag */
5350 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5351
5352 /* Set corresponding Error Code */
5353 /* No need to generate STOP, it is automatically done */
5354 /* Error callback will be send during stop flag treatment */
5355 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5356
5357 /* Flush TX register */
5358 I2C_Flush_TXDR(hi2c);
5359 }
5360 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5361 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5362 {
5363 /* Remove RXNE flag on temporary variable as read done */
5364 tmpITFlags &= ~I2C_FLAG_RXNE;
5365
5366 /* Read data from RXDR */
5367 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5368
5369 /* Increment Buffer pointer */
5370 hi2c->pBuffPtr++;
5371
5372 hi2c->XferSize--;
5373 hi2c->XferCount--;
5374 }
5375 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5376 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5377 {
5378 if (hi2c->Memaddress == 0xFFFFFFFFU)
5379 {
5380 /* Write data to TXDR */
5381 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5382
5383 /* Increment Buffer pointer */
5384 hi2c->pBuffPtr++;
5385
5386 hi2c->XferSize--;
5387 hi2c->XferCount--;
5388 }
5389 else
5390 {
5391 /* Write LSB part of Memory Address */
5392 hi2c->Instance->TXDR = hi2c->Memaddress;
5393
5394 /* Reset Memaddress content */
5395 hi2c->Memaddress = 0xFFFFFFFFU;
5396 }
5397 }
5398 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5399 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5400 {
5401 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5402 {
5403 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5404 {
5405 hi2c->XferSize = MAX_NBYTE_SIZE;
5406 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5407 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5408 }
5409 else
5410 {
5411 hi2c->XferSize = hi2c->XferCount;
5412 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5413 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5414 }
5415 }
5416 else
5417 {
5418 /* Wrong size Status regarding TCR flag event */
5419 /* Call the corresponding callback to inform upper layer of End of Transfer */
5420 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5421 }
5422 }
5423 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5424 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5425 {
5426 /* Disable Interrupt related to address step */
5427 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5428
5429 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
5430 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
5431
5432 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5433 {
5434 direction = I2C_GENERATE_START_READ;
5435 }
5436
5437 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5438 {
5439 hi2c->XferSize = MAX_NBYTE_SIZE;
5440
5441 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5442 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5443 I2C_RELOAD_MODE, direction);
5444 }
5445 else
5446 {
5447 hi2c->XferSize = hi2c->XferCount;
5448
5449 /* Set NBYTES to write and generate RESTART */
5450 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5451 I2C_AUTOEND_MODE, direction);
5452 }
5453 }
5454 else
5455 {
5456 /* Nothing to do */
5457 }
5458
5459 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5460 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5461 {
5462 /* Call I2C Master complete process */
5463 I2C_ITMasterCplt(hi2c, tmpITFlags);
5464 }
5465
5466 /* Process Unlocked */
5467 __HAL_UNLOCK(hi2c);
5468
5469 return HAL_OK;
5470 }
5471
5472 /**
5473 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
5474 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5475 * the configuration information for the specified I2C.
5476 * @param ITFlags Interrupt flags to handle.
5477 * @param ITSources Interrupt sources enabled.
5478 * @retval HAL status
5479 */
I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5480 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5481 uint32_t ITSources)
5482 {
5483 uint32_t tmpoptions = hi2c->XferOptions;
5484 uint32_t tmpITFlags = ITFlags;
5485
5486 /* Process locked */
5487 __HAL_LOCK(hi2c);
5488
5489 /* Check if STOPF is set */
5490 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5491 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5492 {
5493 /* Call I2C Slave complete process */
5494 I2C_ITSlaveCplt(hi2c, tmpITFlags);
5495 }
5496 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5497 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5498 {
5499 /* Check that I2C transfer finished */
5500 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5501 /* Mean XferCount == 0*/
5502 /* So clear Flag NACKF only */
5503 if (hi2c->XferCount == 0U)
5504 {
5505 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5506 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5507 Warning[Pa134]: left and right operands are identical */
5508 {
5509 /* Call I2C Listen complete process */
5510 I2C_ITListenCplt(hi2c, tmpITFlags);
5511 }
5512 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5513 {
5514 /* Clear NACK Flag */
5515 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5516
5517 /* Flush TX register */
5518 I2C_Flush_TXDR(hi2c);
5519
5520 /* Last Byte is Transmitted */
5521 /* Call I2C Slave Sequential complete process */
5522 I2C_ITSlaveSeqCplt(hi2c);
5523 }
5524 else
5525 {
5526 /* Clear NACK Flag */
5527 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5528 }
5529 }
5530 else
5531 {
5532 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5533 /* Clear NACK Flag */
5534 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5535
5536 /* Set ErrorCode corresponding to a Non-Acknowledge */
5537 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5538
5539 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5540 {
5541 /* Call the corresponding callback to inform upper layer of End of Transfer */
5542 I2C_ITError(hi2c, hi2c->ErrorCode);
5543 }
5544 }
5545 }
5546 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5547 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5548 {
5549 if (hi2c->XferCount > 0U)
5550 {
5551 /* Read data from RXDR */
5552 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5553
5554 /* Increment Buffer pointer */
5555 hi2c->pBuffPtr++;
5556
5557 hi2c->XferSize--;
5558 hi2c->XferCount--;
5559 }
5560
5561 if ((hi2c->XferCount == 0U) && \
5562 (tmpoptions != I2C_NO_OPTION_FRAME))
5563 {
5564 /* Call I2C Slave Sequential complete process */
5565 I2C_ITSlaveSeqCplt(hi2c);
5566 }
5567 }
5568 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
5569 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5570 {
5571 I2C_ITAddrCplt(hi2c, tmpITFlags);
5572 }
5573 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5574 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5575 {
5576 /* Write data to TXDR only if XferCount not reach "0" */
5577 /* A TXIS flag can be set, during STOP treatment */
5578 /* Check if all Data have already been sent */
5579 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
5580 if (hi2c->XferCount > 0U)
5581 {
5582 /* Write data to TXDR */
5583 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5584
5585 /* Increment Buffer pointer */
5586 hi2c->pBuffPtr++;
5587
5588 hi2c->XferCount--;
5589 hi2c->XferSize--;
5590 }
5591 else
5592 {
5593 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
5594 {
5595 /* Last Byte is Transmitted */
5596 /* Call I2C Slave Sequential complete process */
5597 I2C_ITSlaveSeqCplt(hi2c);
5598 }
5599 }
5600 }
5601 else
5602 {
5603 /* Nothing to do */
5604 }
5605
5606 /* Process Unlocked */
5607 __HAL_UNLOCK(hi2c);
5608
5609 return HAL_OK;
5610 }
5611
5612 #if defined(HAL_DMA_MODULE_ENABLED)
5613 /**
5614 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
5615 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5616 * the configuration information for the specified I2C.
5617 * @param ITFlags Interrupt flags to handle.
5618 * @param ITSources Interrupt sources enabled.
5619 * @retval HAL status
5620 */
I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5621 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5622 uint32_t ITSources)
5623 {
5624 uint16_t devaddress;
5625 uint32_t xfermode;
5626
5627 /* Process Locked */
5628 __HAL_LOCK(hi2c);
5629
5630 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5631 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5632 {
5633 /* Clear NACK Flag */
5634 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5635
5636 /* Set corresponding Error Code */
5637 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5638
5639 /* No need to generate STOP, it is automatically done */
5640 /* But enable STOP interrupt, to treat it */
5641 /* Error callback will be send during stop flag treatment */
5642 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5643
5644 /* Flush TX register */
5645 I2C_Flush_TXDR(hi2c);
5646 }
5647 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5648 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5649 {
5650 /* Disable TC interrupt */
5651 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
5652
5653 if (hi2c->XferCount != 0U)
5654 {
5655 /* Recover Slave address */
5656 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5657
5658 /* Prepare the new XferSize to transfer */
5659 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5660 {
5661 hi2c->XferSize = MAX_NBYTE_SIZE;
5662 xfermode = I2C_RELOAD_MODE;
5663 }
5664 else
5665 {
5666 hi2c->XferSize = hi2c->XferCount;
5667 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5668 {
5669 xfermode = hi2c->XferOptions;
5670 }
5671 else
5672 {
5673 xfermode = I2C_AUTOEND_MODE;
5674 }
5675 }
5676
5677 /* Set the new XferSize in Nbytes register */
5678 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
5679
5680 /* Update XferCount value */
5681 hi2c->XferCount -= hi2c->XferSize;
5682
5683 /* Enable DMA Request */
5684 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5685 {
5686 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5687 }
5688 else
5689 {
5690 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5691 }
5692 }
5693 else
5694 {
5695 /* Call TxCpltCallback() if no stop mode is set */
5696 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5697 {
5698 /* Call I2C Master Sequential complete process */
5699 I2C_ITMasterSeqCplt(hi2c);
5700 }
5701 else
5702 {
5703 /* Wrong size Status regarding TCR flag event */
5704 /* Call the corresponding callback to inform upper layer of End of Transfer */
5705 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5706 }
5707 }
5708 }
5709 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5710 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5711 {
5712 if (hi2c->XferCount == 0U)
5713 {
5714 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5715 {
5716 /* Generate a stop condition in case of no transfer option */
5717 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5718 {
5719 /* Generate Stop */
5720 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5721 }
5722 else
5723 {
5724 /* Call I2C Master Sequential complete process */
5725 I2C_ITMasterSeqCplt(hi2c);
5726 }
5727 }
5728 }
5729 else
5730 {
5731 /* Wrong size Status regarding TC flag event */
5732 /* Call the corresponding callback to inform upper layer of End of Transfer */
5733 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5734 }
5735 }
5736 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5737 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5738 {
5739 /* Call I2C Master complete process */
5740 I2C_ITMasterCplt(hi2c, ITFlags);
5741 }
5742 else
5743 {
5744 /* Nothing to do */
5745 }
5746
5747 /* Process Unlocked */
5748 __HAL_UNLOCK(hi2c);
5749
5750 return HAL_OK;
5751 }
5752
5753 /**
5754 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
5755 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5756 * the configuration information for the specified I2C.
5757 * @param ITFlags Interrupt flags to handle.
5758 * @param ITSources Interrupt sources enabled.
5759 * @retval HAL status
5760 */
I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5761 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5762 uint32_t ITSources)
5763 {
5764 uint32_t direction = I2C_GENERATE_START_WRITE;
5765
5766 /* Process Locked */
5767 __HAL_LOCK(hi2c);
5768
5769 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5770 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5771 {
5772 /* Clear NACK Flag */
5773 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5774
5775 /* Set corresponding Error Code */
5776 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5777
5778 /* No need to generate STOP, it is automatically done */
5779 /* But enable STOP interrupt, to treat it */
5780 /* Error callback will be send during stop flag treatment */
5781 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5782
5783 /* Flush TX register */
5784 I2C_Flush_TXDR(hi2c);
5785 }
5786 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
5787 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5788 {
5789 /* Write LSB part of Memory Address */
5790 hi2c->Instance->TXDR = hi2c->Memaddress;
5791
5792 /* Reset Memaddress content */
5793 hi2c->Memaddress = 0xFFFFFFFFU;
5794 }
5795 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5796 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5797 {
5798 /* Disable Interrupt related to address step */
5799 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5800
5801 /* Enable only Error interrupt */
5802 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5803
5804 if (hi2c->XferCount != 0U)
5805 {
5806 /* Prepare the new XferSize to transfer */
5807 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5808 {
5809 hi2c->XferSize = MAX_NBYTE_SIZE;
5810 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5811 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5812 }
5813 else
5814 {
5815 hi2c->XferSize = hi2c->XferCount;
5816 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5817 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5818 }
5819
5820 /* Update XferCount value */
5821 hi2c->XferCount -= hi2c->XferSize;
5822
5823 /* Enable DMA Request */
5824 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5825 {
5826 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5827 }
5828 else
5829 {
5830 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5831 }
5832 }
5833 else
5834 {
5835 /* Wrong size Status regarding TCR flag event */
5836 /* Call the corresponding callback to inform upper layer of End of Transfer */
5837 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5838 }
5839 }
5840 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5841 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5842 {
5843 /* Disable Interrupt related to address step */
5844 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5845
5846 /* Enable only Error and NACK interrupt for data transfer */
5847 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5848
5849 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5850 {
5851 direction = I2C_GENERATE_START_READ;
5852 }
5853
5854 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5855 {
5856 hi2c->XferSize = MAX_NBYTE_SIZE;
5857
5858 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5859 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5860 I2C_RELOAD_MODE, direction);
5861 }
5862 else
5863 {
5864 hi2c->XferSize = hi2c->XferCount;
5865
5866 /* Set NBYTES to write and generate RESTART */
5867 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5868 I2C_AUTOEND_MODE, direction);
5869 }
5870
5871 /* Update XferCount value */
5872 hi2c->XferCount -= hi2c->XferSize;
5873
5874 /* Enable DMA Request */
5875 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5876 {
5877 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5878 }
5879 else
5880 {
5881 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5882 }
5883 }
5884 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5885 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5886 {
5887 /* Call I2C Master complete process */
5888 I2C_ITMasterCplt(hi2c, ITFlags);
5889 }
5890 else
5891 {
5892 /* Nothing to do */
5893 }
5894
5895 /* Process Unlocked */
5896 __HAL_UNLOCK(hi2c);
5897
5898 return HAL_OK;
5899 }
5900
5901 /**
5902 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
5903 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5904 * the configuration information for the specified I2C.
5905 * @param ITFlags Interrupt flags to handle.
5906 * @param ITSources Interrupt sources enabled.
5907 * @retval HAL status
5908 */
I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5909 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5910 uint32_t ITSources)
5911 {
5912 uint32_t tmpoptions = hi2c->XferOptions;
5913 uint32_t treatdmanack = 0U;
5914 HAL_I2C_StateTypeDef tmpstate;
5915
5916 /* Process locked */
5917 __HAL_LOCK(hi2c);
5918
5919 /* Check if STOPF is set */
5920 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5921 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5922 {
5923 /* Call I2C Slave complete process */
5924 I2C_ITSlaveCplt(hi2c, ITFlags);
5925 }
5926 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5927 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5928 {
5929 /* Check that I2C transfer finished */
5930 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5931 /* Mean XferCount == 0 */
5932 /* So clear Flag NACKF only */
5933 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
5934 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
5935 {
5936 /* Split check of hdmarx, for MISRA compliance */
5937 if (hi2c->hdmarx != NULL)
5938 {
5939 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5940 {
5941 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
5942 {
5943 treatdmanack = 1U;
5944 }
5945 }
5946 }
5947
5948 /* Split check of hdmatx, for MISRA compliance */
5949 if (hi2c->hdmatx != NULL)
5950 {
5951 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5952 {
5953 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
5954 {
5955 treatdmanack = 1U;
5956 }
5957 }
5958 }
5959
5960 if (treatdmanack == 1U)
5961 {
5962 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5963 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5964 Warning[Pa134]: left and right operands are identical */
5965 {
5966 /* Call I2C Listen complete process */
5967 I2C_ITListenCplt(hi2c, ITFlags);
5968 }
5969 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5970 {
5971 /* Clear NACK Flag */
5972 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5973
5974 /* Flush TX register */
5975 I2C_Flush_TXDR(hi2c);
5976
5977 /* Last Byte is Transmitted */
5978 /* Call I2C Slave Sequential complete process */
5979 I2C_ITSlaveSeqCplt(hi2c);
5980 }
5981 else
5982 {
5983 /* Clear NACK Flag */
5984 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5985 }
5986 }
5987 else
5988 {
5989 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5990 /* Clear NACK Flag */
5991 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5992
5993 /* Set ErrorCode corresponding to a Non-Acknowledge */
5994 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5995
5996 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
5997 tmpstate = hi2c->State;
5998
5999 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
6000 {
6001 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6002 {
6003 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6004 }
6005 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6006 {
6007 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6008 }
6009 else
6010 {
6011 /* Do nothing */
6012 }
6013
6014 /* Call the corresponding callback to inform upper layer of End of Transfer */
6015 I2C_ITError(hi2c, hi2c->ErrorCode);
6016 }
6017 }
6018 }
6019 else
6020 {
6021 /* Only Clear NACK Flag, no DMA treatment is pending */
6022 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6023 }
6024 }
6025 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
6026 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
6027 {
6028 I2C_ITAddrCplt(hi2c, ITFlags);
6029 }
6030 else
6031 {
6032 /* Nothing to do */
6033 }
6034
6035 /* Process Unlocked */
6036 __HAL_UNLOCK(hi2c);
6037
6038 return HAL_OK;
6039 }
6040 #endif /* HAL_DMA_MODULE_ENABLED */
6041
6042 /**
6043 * @brief Master sends target device address followed by internal memory address for write request.
6044 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6045 * the configuration information for the specified I2C.
6046 * @param DevAddress Target device address: The device 7 bits address value
6047 * in datasheet must be shifted to the left before calling the interface
6048 * @param MemAddress Internal memory address
6049 * @param MemAddSize Size of internal memory address
6050 * @param Timeout Timeout duration
6051 * @param Tickstart Tick start value
6052 * @retval HAL status
6053 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6054 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
6055 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
6056 uint32_t Tickstart)
6057 {
6058 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
6059
6060 /* Wait until TXIS flag is set */
6061 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6062 {
6063 return HAL_ERROR;
6064 }
6065
6066 /* If Memory address size is 8Bit */
6067 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6068 {
6069 /* Send Memory Address */
6070 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6071 }
6072 /* If Memory address size is 16Bit */
6073 else
6074 {
6075 /* Send MSB of Memory Address */
6076 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
6077
6078 /* Wait until TXIS flag is set */
6079 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6080 {
6081 return HAL_ERROR;
6082 }
6083
6084 /* Send LSB of Memory Address */
6085 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6086 }
6087
6088 /* Wait until TCR flag is set */
6089 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
6090 {
6091 return HAL_ERROR;
6092 }
6093
6094 return HAL_OK;
6095 }
6096
6097 /**
6098 * @brief Master sends target device address followed by internal memory address for read request.
6099 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6100 * the configuration information for the specified I2C.
6101 * @param DevAddress Target device address: The device 7 bits address value
6102 * in datasheet must be shifted to the left before calling the interface
6103 * @param MemAddress Internal memory address
6104 * @param MemAddSize Size of internal memory address
6105 * @param Timeout Timeout duration
6106 * @param Tickstart Tick start value
6107 * @retval HAL status
6108 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6109 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
6110 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
6111 uint32_t Tickstart)
6112 {
6113 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
6114
6115 /* Wait until TXIS flag is set */
6116 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6117 {
6118 return HAL_ERROR;
6119 }
6120
6121 /* If Memory address size is 8Bit */
6122 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6123 {
6124 /* Send Memory Address */
6125 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6126 }
6127 /* If Memory address size is 16Bit */
6128 else
6129 {
6130 /* Send MSB of Memory Address */
6131 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
6132
6133 /* Wait until TXIS flag is set */
6134 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6135 {
6136 return HAL_ERROR;
6137 }
6138
6139 /* Send LSB of Memory Address */
6140 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6141 }
6142
6143 /* Wait until TC flag is set */
6144 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
6145 {
6146 return HAL_ERROR;
6147 }
6148
6149 return HAL_OK;
6150 }
6151
6152 /**
6153 * @brief I2C Address complete process callback.
6154 * @param hi2c I2C handle.
6155 * @param ITFlags Interrupt flags to handle.
6156 * @retval None
6157 */
I2C_ITAddrCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6158 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6159 {
6160 uint8_t transferdirection;
6161 uint16_t slaveaddrcode;
6162 uint16_t ownadd1code;
6163 uint16_t ownadd2code;
6164
6165 /* Prevent unused argument(s) compilation warning */
6166 UNUSED(ITFlags);
6167
6168 /* In case of Listen state, need to inform upper layer of address match code event */
6169 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6170 {
6171 transferdirection = I2C_GET_DIR(hi2c);
6172 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
6173 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
6174 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
6175
6176 /* If 10bits addressing mode is selected */
6177 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
6178 {
6179 if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
6180 {
6181 slaveaddrcode = ownadd1code;
6182 hi2c->AddrEventCount++;
6183 if (hi2c->AddrEventCount == 2U)
6184 {
6185 /* Reset Address Event counter */
6186 hi2c->AddrEventCount = 0U;
6187
6188 /* Clear ADDR flag */
6189 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
6190
6191 /* Process Unlocked */
6192 __HAL_UNLOCK(hi2c);
6193
6194 /* Call Slave Addr callback */
6195 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6196 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6197 #else
6198 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6199 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6200 }
6201 }
6202 else
6203 {
6204 slaveaddrcode = ownadd2code;
6205
6206 /* Disable ADDR Interrupts */
6207 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
6208
6209 /* Process Unlocked */
6210 __HAL_UNLOCK(hi2c);
6211
6212 /* Call Slave Addr callback */
6213 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6214 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6215 #else
6216 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6217 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6218 }
6219 }
6220 /* else 7 bits addressing mode is selected */
6221 else
6222 {
6223 /* Disable ADDR Interrupts */
6224 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
6225
6226 /* Process Unlocked */
6227 __HAL_UNLOCK(hi2c);
6228
6229 /* Call Slave Addr callback */
6230 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6231 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6232 #else
6233 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6234 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6235 }
6236 }
6237 /* Else clear address flag only */
6238 else
6239 {
6240 /* Clear ADDR flag */
6241 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
6242
6243 /* Process Unlocked */
6244 __HAL_UNLOCK(hi2c);
6245 }
6246 }
6247
6248 /**
6249 * @brief I2C Master sequential complete process.
6250 * @param hi2c I2C handle.
6251 * @retval None
6252 */
I2C_ITMasterSeqCplt(I2C_HandleTypeDef * hi2c)6253 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
6254 {
6255 /* Reset I2C handle mode */
6256 hi2c->Mode = HAL_I2C_MODE_NONE;
6257
6258 /* No Generate Stop, to permit restart mode */
6259 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
6260 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6261 {
6262 hi2c->State = HAL_I2C_STATE_READY;
6263 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6264 hi2c->XferISR = NULL;
6265
6266 /* Disable Interrupts */
6267 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6268
6269 /* Process Unlocked */
6270 __HAL_UNLOCK(hi2c);
6271
6272 /* Call the corresponding callback to inform upper layer of End of Transfer */
6273 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6274 hi2c->MasterTxCpltCallback(hi2c);
6275 #else
6276 HAL_I2C_MasterTxCpltCallback(hi2c);
6277 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6278 }
6279 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6280 else
6281 {
6282 hi2c->State = HAL_I2C_STATE_READY;
6283 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6284 hi2c->XferISR = NULL;
6285
6286 /* Disable Interrupts */
6287 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6288
6289 /* Process Unlocked */
6290 __HAL_UNLOCK(hi2c);
6291
6292 /* Call the corresponding callback to inform upper layer of End of Transfer */
6293 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6294 hi2c->MasterRxCpltCallback(hi2c);
6295 #else
6296 HAL_I2C_MasterRxCpltCallback(hi2c);
6297 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6298 }
6299 }
6300
6301 /**
6302 * @brief I2C Slave sequential complete process.
6303 * @param hi2c I2C handle.
6304 * @retval None
6305 */
I2C_ITSlaveSeqCplt(I2C_HandleTypeDef * hi2c)6306 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
6307 {
6308 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6309
6310 /* Reset I2C handle mode */
6311 hi2c->Mode = HAL_I2C_MODE_NONE;
6312
6313 #if defined(HAL_DMA_MODULE_ENABLED)
6314 /* If a DMA is ongoing, Update handle size context */
6315 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6316 {
6317 /* Disable DMA Request */
6318 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6319 }
6320 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6321 {
6322 /* Disable DMA Request */
6323 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6324 }
6325 else
6326 {
6327 /* Do nothing */
6328 }
6329 #endif /* HAL_DMA_MODULE_ENABLED */
6330
6331 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
6332 {
6333 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
6334 hi2c->State = HAL_I2C_STATE_LISTEN;
6335 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6336
6337 /* Disable Interrupts */
6338 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6339
6340 /* Process Unlocked */
6341 __HAL_UNLOCK(hi2c);
6342
6343 /* Call the corresponding callback to inform upper layer of End of Transfer */
6344 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6345 hi2c->SlaveTxCpltCallback(hi2c);
6346 #else
6347 HAL_I2C_SlaveTxCpltCallback(hi2c);
6348 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6349 }
6350
6351 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
6352 {
6353 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
6354 hi2c->State = HAL_I2C_STATE_LISTEN;
6355 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6356
6357 /* Disable Interrupts */
6358 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6359
6360 /* Process Unlocked */
6361 __HAL_UNLOCK(hi2c);
6362
6363 /* Call the corresponding callback to inform upper layer of End of Transfer */
6364 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6365 hi2c->SlaveRxCpltCallback(hi2c);
6366 #else
6367 HAL_I2C_SlaveRxCpltCallback(hi2c);
6368 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6369 }
6370 else
6371 {
6372 /* Nothing to do */
6373 }
6374 }
6375
6376 /**
6377 * @brief I2C Master complete process.
6378 * @param hi2c I2C handle.
6379 * @param ITFlags Interrupt flags to handle.
6380 * @retval None
6381 */
I2C_ITMasterCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6382 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6383 {
6384 uint32_t tmperror;
6385 uint32_t tmpITFlags = ITFlags;
6386 __IO uint32_t tmpreg;
6387
6388 /* Clear STOP Flag */
6389 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6390
6391 /* Disable Interrupts and Store Previous state */
6392 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6393 {
6394 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6395 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6396 }
6397 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6398 {
6399 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6400 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6401 }
6402 else
6403 {
6404 /* Do nothing */
6405 }
6406
6407 /* Clear Configuration Register 2 */
6408 I2C_RESET_CR2(hi2c);
6409
6410 /* Reset handle parameters */
6411 hi2c->XferISR = NULL;
6412 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6413
6414 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
6415 {
6416 /* Clear NACK Flag */
6417 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6418
6419 /* Set acknowledge error code */
6420 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6421 }
6422
6423 /* Fetch Last receive data if any */
6424 if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
6425 {
6426 /* Read data from RXDR */
6427 tmpreg = (uint8_t)hi2c->Instance->RXDR;
6428 UNUSED(tmpreg);
6429 }
6430
6431 /* Flush TX register */
6432 I2C_Flush_TXDR(hi2c);
6433
6434 /* Store current volatile hi2c->ErrorCode, misra rule */
6435 tmperror = hi2c->ErrorCode;
6436
6437 /* Call the corresponding callback to inform upper layer of End of Transfer */
6438 if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
6439 {
6440 /* Call the corresponding callback to inform upper layer of End of Transfer */
6441 I2C_ITError(hi2c, hi2c->ErrorCode);
6442 }
6443 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
6444 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6445 {
6446 hi2c->State = HAL_I2C_STATE_READY;
6447 hi2c->PreviousState = I2C_STATE_NONE;
6448
6449 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6450 {
6451 hi2c->Mode = HAL_I2C_MODE_NONE;
6452
6453 /* Process Unlocked */
6454 __HAL_UNLOCK(hi2c);
6455
6456 /* Call the corresponding callback to inform upper layer of End of Transfer */
6457 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6458 hi2c->MemTxCpltCallback(hi2c);
6459 #else
6460 HAL_I2C_MemTxCpltCallback(hi2c);
6461 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6462 }
6463 else
6464 {
6465 hi2c->Mode = HAL_I2C_MODE_NONE;
6466
6467 /* Process Unlocked */
6468 __HAL_UNLOCK(hi2c);
6469
6470 /* Call the corresponding callback to inform upper layer of End of Transfer */
6471 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6472 hi2c->MasterTxCpltCallback(hi2c);
6473 #else
6474 HAL_I2C_MasterTxCpltCallback(hi2c);
6475 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6476 }
6477 }
6478 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6479 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6480 {
6481 hi2c->State = HAL_I2C_STATE_READY;
6482 hi2c->PreviousState = I2C_STATE_NONE;
6483
6484 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6485 {
6486 hi2c->Mode = HAL_I2C_MODE_NONE;
6487
6488 /* Process Unlocked */
6489 __HAL_UNLOCK(hi2c);
6490
6491 /* Call the corresponding callback to inform upper layer of End of Transfer */
6492 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6493 hi2c->MemRxCpltCallback(hi2c);
6494 #else
6495 HAL_I2C_MemRxCpltCallback(hi2c);
6496 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6497 }
6498 else
6499 {
6500 hi2c->Mode = HAL_I2C_MODE_NONE;
6501
6502 /* Process Unlocked */
6503 __HAL_UNLOCK(hi2c);
6504
6505 /* Call the corresponding callback to inform upper layer of End of Transfer */
6506 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6507 hi2c->MasterRxCpltCallback(hi2c);
6508 #else
6509 HAL_I2C_MasterRxCpltCallback(hi2c);
6510 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6511 }
6512 }
6513 else
6514 {
6515 /* Nothing to do */
6516 }
6517 }
6518
6519 /**
6520 * @brief I2C Slave complete process.
6521 * @param hi2c I2C handle.
6522 * @param ITFlags Interrupt flags to handle.
6523 * @retval None
6524 */
I2C_ITSlaveCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6525 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6526 {
6527 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6528 uint32_t tmpITFlags = ITFlags;
6529 uint32_t tmpoptions = hi2c->XferOptions;
6530 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6531
6532 /* Clear STOP Flag */
6533 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6534
6535 /* Disable Interrupts and Store Previous state */
6536 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6537 {
6538 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
6539 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6540 }
6541 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6542 {
6543 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
6544 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6545 }
6546 else if (tmpstate == HAL_I2C_STATE_LISTEN)
6547 {
6548 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
6549 hi2c->PreviousState = I2C_STATE_NONE;
6550 }
6551 else
6552 {
6553 /* Do nothing */
6554 }
6555
6556 /* Disable Address Acknowledge */
6557 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6558
6559 /* Clear Configuration Register 2 */
6560 I2C_RESET_CR2(hi2c);
6561
6562 /* Flush TX register */
6563 I2C_Flush_TXDR(hi2c);
6564
6565 #if defined(HAL_DMA_MODULE_ENABLED)
6566 /* If a DMA is ongoing, Update handle size context */
6567 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6568 {
6569 /* Disable DMA Request */
6570 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6571
6572 if (hi2c->hdmatx != NULL)
6573 {
6574 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
6575 }
6576 }
6577 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6578 {
6579 /* Disable DMA Request */
6580 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6581
6582 if (hi2c->hdmarx != NULL)
6583 {
6584 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
6585 }
6586 }
6587 else
6588 {
6589 /* Do nothing */
6590 }
6591 #endif /* HAL_DMA_MODULE_ENABLED */
6592
6593 /* Store Last receive data if any */
6594 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
6595 {
6596 /* Remove RXNE flag on temporary variable as read done */
6597 tmpITFlags &= ~I2C_FLAG_RXNE;
6598
6599 /* Read data from RXDR */
6600 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6601
6602 /* Increment Buffer pointer */
6603 hi2c->pBuffPtr++;
6604
6605 if ((hi2c->XferSize > 0U))
6606 {
6607 hi2c->XferSize--;
6608 hi2c->XferCount--;
6609 }
6610 }
6611
6612 /* All data are not transferred, so set error code accordingly */
6613 if (hi2c->XferCount != 0U)
6614 {
6615 /* Set ErrorCode corresponding to a Non-Acknowledge */
6616 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6617 }
6618
6619 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
6620 (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
6621 {
6622 /* Check that I2C transfer finished */
6623 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
6624 /* Mean XferCount == 0*/
6625 /* So clear Flag NACKF only */
6626 if (hi2c->XferCount == 0U)
6627 {
6628 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
6629 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
6630 Warning[Pa134]: left and right operands are identical */
6631 {
6632 /* Call I2C Listen complete process */
6633 I2C_ITListenCplt(hi2c, tmpITFlags);
6634 }
6635 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
6636 {
6637 /* Clear NACK Flag */
6638 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6639
6640 /* Flush TX register */
6641 I2C_Flush_TXDR(hi2c);
6642
6643 /* Last Byte is Transmitted */
6644 /* Call I2C Slave Sequential complete process */
6645 I2C_ITSlaveSeqCplt(hi2c);
6646 }
6647 else
6648 {
6649 /* Clear NACK Flag */
6650 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6651 }
6652 }
6653 else
6654 {
6655 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
6656 /* Clear NACK Flag */
6657 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6658
6659 /* Set ErrorCode corresponding to a Non-Acknowledge */
6660 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6661
6662 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
6663 {
6664 /* Call the corresponding callback to inform upper layer of End of Transfer */
6665 I2C_ITError(hi2c, hi2c->ErrorCode);
6666 }
6667 }
6668 }
6669
6670 hi2c->Mode = HAL_I2C_MODE_NONE;
6671 hi2c->XferISR = NULL;
6672
6673 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6674 {
6675 /* Call the corresponding callback to inform upper layer of End of Transfer */
6676 I2C_ITError(hi2c, hi2c->ErrorCode);
6677
6678 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6679 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6680 {
6681 /* Call I2C Listen complete process */
6682 I2C_ITListenCplt(hi2c, tmpITFlags);
6683 }
6684 }
6685 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
6686 {
6687 /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
6688 I2C_ITSlaveSeqCplt(hi2c);
6689
6690 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6691 hi2c->State = HAL_I2C_STATE_READY;
6692 hi2c->PreviousState = I2C_STATE_NONE;
6693
6694 /* Process Unlocked */
6695 __HAL_UNLOCK(hi2c);
6696
6697 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6698 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6699 hi2c->ListenCpltCallback(hi2c);
6700 #else
6701 HAL_I2C_ListenCpltCallback(hi2c);
6702 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6703 }
6704 /* Call the corresponding callback to inform upper layer of End of Transfer */
6705 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6706 {
6707 hi2c->State = HAL_I2C_STATE_READY;
6708 hi2c->PreviousState = I2C_STATE_NONE;
6709
6710 /* Process Unlocked */
6711 __HAL_UNLOCK(hi2c);
6712
6713 /* Call the corresponding callback to inform upper layer of End of Transfer */
6714 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6715 hi2c->SlaveRxCpltCallback(hi2c);
6716 #else
6717 HAL_I2C_SlaveRxCpltCallback(hi2c);
6718 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6719 }
6720 else
6721 {
6722 hi2c->State = HAL_I2C_STATE_READY;
6723 hi2c->PreviousState = I2C_STATE_NONE;
6724
6725 /* Process Unlocked */
6726 __HAL_UNLOCK(hi2c);
6727
6728 /* Call the corresponding callback to inform upper layer of End of Transfer */
6729 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6730 hi2c->SlaveTxCpltCallback(hi2c);
6731 #else
6732 HAL_I2C_SlaveTxCpltCallback(hi2c);
6733 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6734 }
6735 }
6736
6737 /**
6738 * @brief I2C Listen complete process.
6739 * @param hi2c I2C handle.
6740 * @param ITFlags Interrupt flags to handle.
6741 * @retval None
6742 */
I2C_ITListenCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6743 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6744 {
6745 /* Reset handle parameters */
6746 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6747 hi2c->PreviousState = I2C_STATE_NONE;
6748 hi2c->State = HAL_I2C_STATE_READY;
6749 hi2c->Mode = HAL_I2C_MODE_NONE;
6750 hi2c->XferISR = NULL;
6751
6752 /* Store Last receive data if any */
6753 if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
6754 {
6755 /* Read data from RXDR */
6756 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6757
6758 /* Increment Buffer pointer */
6759 hi2c->pBuffPtr++;
6760
6761 if ((hi2c->XferSize > 0U))
6762 {
6763 hi2c->XferSize--;
6764 hi2c->XferCount--;
6765
6766 /* Set ErrorCode corresponding to a Non-Acknowledge */
6767 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6768 }
6769 }
6770
6771 /* Disable all Interrupts*/
6772 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6773
6774 /* Clear NACK Flag */
6775 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6776
6777 /* Process Unlocked */
6778 __HAL_UNLOCK(hi2c);
6779
6780 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6781 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6782 hi2c->ListenCpltCallback(hi2c);
6783 #else
6784 HAL_I2C_ListenCpltCallback(hi2c);
6785 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6786 }
6787
6788 /**
6789 * @brief I2C interrupts error process.
6790 * @param hi2c I2C handle.
6791 * @param ErrorCode Error code to handle.
6792 * @retval None
6793 */
I2C_ITError(I2C_HandleTypeDef * hi2c,uint32_t ErrorCode)6794 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
6795 {
6796 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6797
6798 #if defined(HAL_DMA_MODULE_ENABLED)
6799 uint32_t tmppreviousstate;
6800 #endif /* HAL_DMA_MODULE_ENABLED */
6801
6802 /* Reset handle parameters */
6803 hi2c->Mode = HAL_I2C_MODE_NONE;
6804 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6805 hi2c->XferCount = 0U;
6806
6807 /* Set new error code */
6808 hi2c->ErrorCode |= ErrorCode;
6809
6810 /* Disable Interrupts */
6811 if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
6812 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
6813 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6814 {
6815 /* Disable all interrupts, except interrupts related to LISTEN state */
6816 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6817
6818 /* keep HAL_I2C_STATE_LISTEN if set */
6819 hi2c->State = HAL_I2C_STATE_LISTEN;
6820 hi2c->XferISR = I2C_Slave_ISR_IT;
6821 }
6822 else
6823 {
6824 /* Disable all interrupts */
6825 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6826
6827 /* Flush TX register */
6828 I2C_Flush_TXDR(hi2c);
6829
6830 /* If state is an abort treatment on going, don't change state */
6831 /* This change will be do later */
6832 if (hi2c->State != HAL_I2C_STATE_ABORT)
6833 {
6834 /* Set HAL_I2C_STATE_READY */
6835 hi2c->State = HAL_I2C_STATE_READY;
6836
6837 /* Check if a STOPF is detected */
6838 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6839 {
6840 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6841 {
6842 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6843 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6844 }
6845
6846 /* Clear STOP Flag */
6847 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6848 }
6849
6850 }
6851 hi2c->XferISR = NULL;
6852 }
6853
6854 #if defined(HAL_DMA_MODULE_ENABLED)
6855 /* Abort DMA TX transfer if any */
6856 tmppreviousstate = hi2c->PreviousState;
6857
6858 if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
6859 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
6860 {
6861 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
6862 {
6863 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6864 }
6865
6866 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6867 {
6868 /* Set the I2C DMA Abort callback :
6869 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6870 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6871
6872 /* Process Unlocked */
6873 __HAL_UNLOCK(hi2c);
6874
6875 /* Abort DMA TX */
6876 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6877 {
6878 /* Call Directly XferAbortCallback function in case of error */
6879 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6880 }
6881 }
6882 else
6883 {
6884 I2C_TreatErrorCallback(hi2c);
6885 }
6886 }
6887 /* Abort DMA RX transfer if any */
6888 else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
6889 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
6890 {
6891 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
6892 {
6893 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6894 }
6895
6896 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6897 {
6898 /* Set the I2C DMA Abort callback :
6899 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6900 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6901
6902 /* Process Unlocked */
6903 __HAL_UNLOCK(hi2c);
6904
6905 /* Abort DMA RX */
6906 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6907 {
6908 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6909 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6910 }
6911 }
6912 else
6913 {
6914 I2C_TreatErrorCallback(hi2c);
6915 }
6916 }
6917 else
6918 #endif /* HAL_DMA_MODULE_ENABLED */
6919 {
6920 I2C_TreatErrorCallback(hi2c);
6921 }
6922 }
6923
6924 /**
6925 * @brief I2C Error callback treatment.
6926 * @param hi2c I2C handle.
6927 * @retval None
6928 */
I2C_TreatErrorCallback(I2C_HandleTypeDef * hi2c)6929 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
6930 {
6931 if (hi2c->State == HAL_I2C_STATE_ABORT)
6932 {
6933 hi2c->State = HAL_I2C_STATE_READY;
6934 hi2c->PreviousState = I2C_STATE_NONE;
6935
6936 /* Process Unlocked */
6937 __HAL_UNLOCK(hi2c);
6938
6939 /* Call the corresponding callback to inform upper layer of End of Transfer */
6940 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6941 hi2c->AbortCpltCallback(hi2c);
6942 #else
6943 HAL_I2C_AbortCpltCallback(hi2c);
6944 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6945 }
6946 else
6947 {
6948 hi2c->PreviousState = I2C_STATE_NONE;
6949
6950 /* Process Unlocked */
6951 __HAL_UNLOCK(hi2c);
6952
6953 /* Call the corresponding callback to inform upper layer of End of Transfer */
6954 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6955 hi2c->ErrorCallback(hi2c);
6956 #else
6957 HAL_I2C_ErrorCallback(hi2c);
6958 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6959 }
6960 }
6961
6962 /**
6963 * @brief I2C Tx data register flush process.
6964 * @param hi2c I2C handle.
6965 * @retval None
6966 */
I2C_Flush_TXDR(I2C_HandleTypeDef * hi2c)6967 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
6968 {
6969 /* If a pending TXIS flag is set */
6970 /* Write a dummy data in TXDR to clear it */
6971 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
6972 {
6973 hi2c->Instance->TXDR = 0x00U;
6974 }
6975
6976 /* Flush TX register if not empty */
6977 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
6978 {
6979 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
6980 }
6981 }
6982
6983 #if defined(HAL_DMA_MODULE_ENABLED)
6984 /**
6985 * @brief DMA I2C master transmit process complete callback.
6986 * @param hdma DMA handle
6987 * @retval None
6988 */
I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef * hdma)6989 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
6990 {
6991 HAL_StatusTypeDef dmaxferstatus = HAL_OK;
6992 /* Derogation MISRAC2012-Rule-11.5 */
6993 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6994
6995 /* Disable DMA Request */
6996 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6997
6998 /* If last transfer, enable STOP interrupt */
6999 if (hi2c->XferCount == 0U)
7000 {
7001 /* Enable STOP interrupt */
7002 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
7003 }
7004 /* else prepare a new DMA transfer and enable TCReload interrupt */
7005 else
7006 {
7007 /* Update Buffer pointer */
7008 hi2c->pBuffPtr += hi2c->XferSize;
7009
7010 /* Set the XferSize to transfer */
7011 if (hi2c->XferCount > MAX_NBYTE_SIZE)
7012 {
7013 hi2c->XferSize = MAX_NBYTE_SIZE;
7014 }
7015 else
7016 {
7017 hi2c->XferSize = hi2c->XferCount;
7018 }
7019
7020 /* Enable the DMA channel */
7021 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
7022 {
7023 if (hi2c->hdmatx->LinkedListQueue != NULL)
7024 {
7025 /* Set DMA data size */
7026 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
7027
7028 /* Set DMA source address */
7029 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
7030
7031 /* Set DMA destination address */
7032 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->TXDR;
7033
7034 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
7035 }
7036 else
7037 {
7038 /* Call the corresponding callback to inform upper layer of End of Transfer */
7039 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7040 }
7041 }
7042 else
7043 {
7044 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
7045 hi2c->XferSize);
7046 }
7047
7048 if (dmaxferstatus != HAL_OK)
7049 {
7050 /* Call the corresponding callback to inform upper layer of End of Transfer */
7051 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7052 }
7053 else
7054 {
7055 /* Enable TC interrupts */
7056 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
7057 }
7058 }
7059 }
7060
7061
7062 /**
7063 * @brief DMA I2C slave transmit process complete callback.
7064 * @param hdma DMA handle
7065 * @retval None
7066 */
I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef * hdma)7067 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
7068 {
7069 /* Derogation MISRAC2012-Rule-11.5 */
7070 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7071 uint32_t tmpoptions = hi2c->XferOptions;
7072
7073 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
7074 {
7075 /* Disable DMA Request */
7076 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
7077
7078 /* Last Byte is Transmitted */
7079 /* Call I2C Slave Sequential complete process */
7080 I2C_ITSlaveSeqCplt(hi2c);
7081 }
7082 else
7083 {
7084 /* No specific action, Master fully manage the generation of STOP condition */
7085 /* Mean that this generation can arrive at any time, at the end or during DMA process */
7086 /* So STOP condition should be manage through Interrupt treatment */
7087 }
7088 }
7089
7090
7091 /**
7092 * @brief DMA I2C master receive process complete callback.
7093 * @param hdma DMA handle
7094 * @retval None
7095 */
I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef * hdma)7096 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
7097 {
7098 HAL_StatusTypeDef dmaxferstatus = HAL_OK;
7099 /* Derogation MISRAC2012-Rule-11.5 */
7100 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7101
7102 /* Disable DMA Request */
7103 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
7104
7105 /* If last transfer, enable STOP interrupt */
7106 if (hi2c->XferCount == 0U)
7107 {
7108 /* Enable STOP interrupt */
7109 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
7110 }
7111 /* else prepare a new DMA transfer and enable TCReload interrupt */
7112 else
7113 {
7114 /* Update Buffer pointer */
7115 hi2c->pBuffPtr += hi2c->XferSize;
7116
7117 /* Set the XferSize to transfer */
7118 if (hi2c->XferCount > MAX_NBYTE_SIZE)
7119 {
7120 hi2c->XferSize = MAX_NBYTE_SIZE;
7121 }
7122 else
7123 {
7124 hi2c->XferSize = hi2c->XferCount;
7125 }
7126
7127 /* Enable the DMA channel */
7128 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
7129 {
7130 if (hi2c->hdmarx->LinkedListQueue != NULL)
7131 {
7132 /* Set DMA data size */
7133 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
7134
7135 /* Set DMA source address */
7136 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->RXDR;
7137
7138 /* Set DMA destination address */
7139 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
7140
7141 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
7142 }
7143 else
7144 {
7145 /* Call the corresponding callback to inform upper layer of End of Transfer */
7146 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7147 }
7148 }
7149 else
7150 {
7151 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
7152 hi2c->XferSize);
7153 }
7154
7155 if (dmaxferstatus != HAL_OK)
7156 {
7157 /* Call the corresponding callback to inform upper layer of End of Transfer */
7158 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7159 }
7160 else
7161 {
7162 /* Enable TC interrupts */
7163 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
7164 }
7165 }
7166 }
7167
7168
7169 /**
7170 * @brief DMA I2C slave receive process complete callback.
7171 * @param hdma DMA handle
7172 * @retval None
7173 */
I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef * hdma)7174 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
7175 {
7176 /* Derogation MISRAC2012-Rule-11.5 */
7177 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7178 uint32_t tmpoptions = hi2c->XferOptions;
7179
7180 if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
7181 (tmpoptions != I2C_NO_OPTION_FRAME))
7182 {
7183 /* Disable DMA Request */
7184 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
7185
7186 /* Call I2C Slave Sequential complete process */
7187 I2C_ITSlaveSeqCplt(hi2c);
7188 }
7189 else
7190 {
7191 /* No specific action, Master fully manage the generation of STOP condition */
7192 /* Mean that this generation can arrive at any time, at the end or during DMA process */
7193 /* So STOP condition should be manage through Interrupt treatment */
7194 }
7195 }
7196
7197
7198 /**
7199 * @brief DMA I2C communication error callback.
7200 * @param hdma DMA handle
7201 * @retval None
7202 */
I2C_DMAError(DMA_HandleTypeDef * hdma)7203 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
7204 {
7205 /* Derogation MISRAC2012-Rule-11.5 */
7206 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7207
7208 /* Disable Acknowledge */
7209 hi2c->Instance->CR2 |= I2C_CR2_NACK;
7210
7211 /* Call the corresponding callback to inform upper layer of End of Transfer */
7212 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7213 }
7214
7215
7216 /**
7217 * @brief DMA I2C communication abort callback
7218 * (To be called at end of DMA Abort procedure).
7219 * @param hdma DMA handle.
7220 * @retval None
7221 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)7222 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
7223 {
7224 /* Derogation MISRAC2012-Rule-11.5 */
7225 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7226
7227 /* Reset AbortCpltCallback */
7228 if (hi2c->hdmatx != NULL)
7229 {
7230 hi2c->hdmatx->XferAbortCallback = NULL;
7231 }
7232 if (hi2c->hdmarx != NULL)
7233 {
7234 hi2c->hdmarx->XferAbortCallback = NULL;
7235 }
7236
7237 I2C_TreatErrorCallback(hi2c);
7238 }
7239
7240 #endif /* HAL_DMA_MODULE_ENABLED */
7241
7242 /**
7243 * @brief This function handles I2C Communication Timeout. It waits
7244 * until a flag is no longer in the specified status.
7245 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7246 * the configuration information for the specified I2C.
7247 * @param Flag Specifies the I2C flag to check.
7248 * @param Status The actual Flag status (SET or RESET).
7249 * @param Timeout Timeout duration
7250 * @param Tickstart Tick start value
7251 * @retval HAL status
7252 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)7253 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
7254 uint32_t Timeout, uint32_t Tickstart)
7255 {
7256 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
7257 {
7258 /* Check if an error is detected */
7259 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7260 {
7261 return HAL_ERROR;
7262 }
7263
7264 /* Check for the Timeout */
7265 if (Timeout != HAL_MAX_DELAY)
7266 {
7267 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7268 {
7269 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
7270 {
7271 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7272 hi2c->State = HAL_I2C_STATE_READY;
7273 hi2c->Mode = HAL_I2C_MODE_NONE;
7274
7275 /* Process Unlocked */
7276 __HAL_UNLOCK(hi2c);
7277 return HAL_ERROR;
7278 }
7279 }
7280 }
7281 }
7282 return HAL_OK;
7283 }
7284
7285 /**
7286 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
7287 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7288 * the configuration information for the specified I2C.
7289 * @param Timeout Timeout duration
7290 * @param Tickstart Tick start value
7291 * @retval HAL status
7292 */
I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7293 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7294 uint32_t Tickstart)
7295 {
7296 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
7297 {
7298 /* Check if an error is detected */
7299 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7300 {
7301 return HAL_ERROR;
7302 }
7303
7304 /* Check for the Timeout */
7305 if (Timeout != HAL_MAX_DELAY)
7306 {
7307 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7308 {
7309 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
7310 {
7311 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7312 hi2c->State = HAL_I2C_STATE_READY;
7313 hi2c->Mode = HAL_I2C_MODE_NONE;
7314
7315 /* Process Unlocked */
7316 __HAL_UNLOCK(hi2c);
7317
7318 return HAL_ERROR;
7319 }
7320 }
7321 }
7322 }
7323 return HAL_OK;
7324 }
7325
7326 /**
7327 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
7328 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7329 * the configuration information for the specified I2C.
7330 * @param Timeout Timeout duration
7331 * @param Tickstart Tick start value
7332 * @retval HAL status
7333 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7334 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7335 uint32_t Tickstart)
7336 {
7337 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7338 {
7339 /* Check if an error is detected */
7340 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7341 {
7342 return HAL_ERROR;
7343 }
7344
7345 /* Check for the Timeout */
7346 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7347 {
7348 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
7349 {
7350 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7351 hi2c->State = HAL_I2C_STATE_READY;
7352 hi2c->Mode = HAL_I2C_MODE_NONE;
7353
7354 /* Process Unlocked */
7355 __HAL_UNLOCK(hi2c);
7356
7357 return HAL_ERROR;
7358 }
7359 }
7360 }
7361 return HAL_OK;
7362 }
7363
7364 /**
7365 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
7366 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7367 * the configuration information for the specified I2C.
7368 * @param Timeout Timeout duration
7369 * @param Tickstart Tick start value
7370 * @retval HAL status
7371 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7372 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7373 uint32_t Tickstart)
7374 {
7375 HAL_StatusTypeDef status = HAL_OK;
7376
7377 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
7378 {
7379 /* Check if an error is detected */
7380 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7381 {
7382 status = HAL_ERROR;
7383 }
7384
7385 /* Check if a STOPF is detected */
7386 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
7387 {
7388 /* Check if an RXNE is pending */
7389 /* Store Last receive data if any */
7390 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
7391 {
7392 /* Return HAL_OK */
7393 /* The Reading of data from RXDR will be done in caller function */
7394 status = HAL_OK;
7395 }
7396
7397 /* Check a no-acknowledge have been detected */
7398 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7399 {
7400 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7401 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
7402
7403 /* Clear STOP Flag */
7404 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7405
7406 /* Clear Configuration Register 2 */
7407 I2C_RESET_CR2(hi2c);
7408
7409 hi2c->State = HAL_I2C_STATE_READY;
7410 hi2c->Mode = HAL_I2C_MODE_NONE;
7411
7412 /* Process Unlocked */
7413 __HAL_UNLOCK(hi2c);
7414
7415 status = HAL_ERROR;
7416 }
7417 else
7418 {
7419 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
7420 }
7421 }
7422
7423 /* Check for the Timeout */
7424 if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
7425 {
7426 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
7427 {
7428 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7429 hi2c->State = HAL_I2C_STATE_READY;
7430
7431 /* Process Unlocked */
7432 __HAL_UNLOCK(hi2c);
7433
7434 status = HAL_ERROR;
7435 }
7436 }
7437 }
7438 return status;
7439 }
7440
7441 /**
7442 * @brief This function handles errors detection during an I2C Communication.
7443 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7444 * the configuration information for the specified I2C.
7445 * @param Timeout Timeout duration
7446 * @param Tickstart Tick start value
7447 * @retval HAL status
7448 */
I2C_IsErrorOccurred(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7449 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7450 {
7451 HAL_StatusTypeDef status = HAL_OK;
7452 uint32_t itflag = hi2c->Instance->ISR;
7453 uint32_t error_code = 0;
7454 uint32_t tickstart = Tickstart;
7455 uint32_t tmp1;
7456 HAL_I2C_ModeTypeDef tmp2;
7457
7458 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
7459 {
7460 /* Clear NACKF Flag */
7461 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7462
7463 /* Wait until STOP Flag is set or timeout occurred */
7464 /* AutoEnd should be initiate after AF */
7465 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
7466 {
7467 /* Check for the Timeout */
7468 if (Timeout != HAL_MAX_DELAY)
7469 {
7470 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7471 {
7472 tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
7473 tmp2 = hi2c->Mode;
7474
7475 /* In case of I2C still busy, try to regenerate a STOP manually */
7476 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
7477 (tmp1 != I2C_CR2_STOP) && \
7478 (tmp2 != HAL_I2C_MODE_SLAVE))
7479 {
7480 /* Generate Stop */
7481 hi2c->Instance->CR2 |= I2C_CR2_STOP;
7482
7483 /* Update Tick with new reference */
7484 tickstart = HAL_GetTick();
7485 }
7486
7487 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7488 {
7489 /* Check for the Timeout */
7490 if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
7491 {
7492 error_code |= HAL_I2C_ERROR_TIMEOUT;
7493
7494 status = HAL_ERROR;
7495
7496 break;
7497 }
7498 }
7499 }
7500 }
7501 }
7502
7503 /* In case STOP Flag is detected, clear it */
7504 if (status == HAL_OK)
7505 {
7506 /* Clear STOP Flag */
7507 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7508 }
7509
7510 error_code |= HAL_I2C_ERROR_AF;
7511
7512 status = HAL_ERROR;
7513 }
7514
7515 /* Refresh Content of Status register */
7516 itflag = hi2c->Instance->ISR;
7517
7518 /* Then verify if an additional errors occurs */
7519 /* Check if a Bus error occurred */
7520 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
7521 {
7522 error_code |= HAL_I2C_ERROR_BERR;
7523
7524 /* Clear BERR flag */
7525 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
7526
7527 status = HAL_ERROR;
7528 }
7529
7530 /* Check if an Over-Run/Under-Run error occurred */
7531 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
7532 {
7533 error_code |= HAL_I2C_ERROR_OVR;
7534
7535 /* Clear OVR flag */
7536 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
7537
7538 status = HAL_ERROR;
7539 }
7540
7541 /* Check if an Arbitration Loss error occurred */
7542 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
7543 {
7544 error_code |= HAL_I2C_ERROR_ARLO;
7545
7546 /* Clear ARLO flag */
7547 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
7548
7549 status = HAL_ERROR;
7550 }
7551
7552 if (status != HAL_OK)
7553 {
7554 /* Flush TX register */
7555 I2C_Flush_TXDR(hi2c);
7556
7557 /* Clear Configuration Register 2 */
7558 I2C_RESET_CR2(hi2c);
7559
7560 hi2c->ErrorCode |= error_code;
7561 hi2c->State = HAL_I2C_STATE_READY;
7562 hi2c->Mode = HAL_I2C_MODE_NONE;
7563
7564 /* Process Unlocked */
7565 __HAL_UNLOCK(hi2c);
7566 }
7567
7568 return status;
7569 }
7570
7571 /**
7572 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
7573 * @param hi2c I2C handle.
7574 * @param DevAddress Specifies the slave address to be programmed.
7575 * @param Size Specifies the number of bytes to be programmed.
7576 * This parameter must be a value between 0 and 255.
7577 * @param Mode New state of the I2C START condition generation.
7578 * This parameter can be one of the following values:
7579 * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
7580 * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
7581 * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
7582 * @param Request New state of the I2C START condition generation.
7583 * This parameter can be one of the following values:
7584 * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
7585 * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
7586 * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
7587 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
7588 * @retval None
7589 */
I2C_TransferConfig(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t Size,uint32_t Mode,uint32_t Request)7590 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
7591 uint32_t Request)
7592 {
7593 /* Check the parameters */
7594 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
7595 assert_param(IS_TRANSFER_MODE(Mode));
7596 assert_param(IS_TRANSFER_REQUEST(Request));
7597
7598 /* Declaration of tmp to prevent undefined behavior of volatile usage */
7599 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
7600 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
7601 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
7602
7603 /* update CR2 register */
7604 MODIFY_REG(hi2c->Instance->CR2, \
7605 ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
7606 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
7607 I2C_CR2_START | I2C_CR2_STOP)), tmp);
7608 }
7609
7610 /**
7611 * @brief Manage the enabling of Interrupts.
7612 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7613 * the configuration information for the specified I2C.
7614 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7615 * @retval None
7616 */
I2C_Enable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7617 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7618 {
7619 uint32_t tmpisr = 0U;
7620
7621 #if defined(HAL_DMA_MODULE_ENABLED)
7622 if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
7623 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
7624 (hi2c->XferISR != I2C_Mem_ISR_DMA))
7625 #endif /* HAL_DMA_MODULE_ENABLED */
7626 {
7627 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7628 {
7629 /* Enable ERR, STOP, NACK and ADDR interrupts */
7630 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7631 }
7632
7633 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7634 {
7635 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7636 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7637 }
7638
7639 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7640 {
7641 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7642 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7643 }
7644
7645 if (InterruptRequest == I2C_XFER_ERROR_IT)
7646 {
7647 /* Enable ERR and NACK interrupts */
7648 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7649 }
7650
7651 if (InterruptRequest == I2C_XFER_CPLT_IT)
7652 {
7653 /* Enable STOP interrupts */
7654 tmpisr |= I2C_IT_STOPI;
7655 }
7656 }
7657
7658 #if defined(HAL_DMA_MODULE_ENABLED)
7659 else
7660 {
7661 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7662 {
7663 /* Enable ERR, STOP, NACK and ADDR interrupts */
7664 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7665 }
7666
7667 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7668 {
7669 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7670 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7671 }
7672
7673 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7674 {
7675 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7676 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7677 }
7678
7679 if (InterruptRequest == I2C_XFER_ERROR_IT)
7680 {
7681 /* Enable ERR and NACK interrupts */
7682 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7683 }
7684
7685 if (InterruptRequest == I2C_XFER_CPLT_IT)
7686 {
7687 /* Enable STOP interrupts */
7688 tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
7689 }
7690
7691 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7692 {
7693 /* Enable TC interrupts */
7694 tmpisr |= I2C_IT_TCI;
7695 }
7696 }
7697 #endif /* HAL_DMA_MODULE_ENABLED */
7698
7699 /* Enable interrupts only at the end */
7700 /* to avoid the risk of I2C interrupt handle execution before */
7701 /* all interrupts requested done */
7702 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
7703 }
7704
7705 /**
7706 * @brief Manage the disabling of Interrupts.
7707 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7708 * the configuration information for the specified I2C.
7709 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7710 * @retval None
7711 */
I2C_Disable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7712 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7713 {
7714 uint32_t tmpisr = 0U;
7715
7716 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7717 {
7718 /* Disable TC and TXI interrupts */
7719 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
7720
7721 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7722 {
7723 /* Disable NACK and STOP interrupts */
7724 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7725 }
7726 }
7727
7728 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7729 {
7730 /* Disable TC and RXI interrupts */
7731 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
7732
7733 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7734 {
7735 /* Disable NACK and STOP interrupts */
7736 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7737 }
7738 }
7739
7740 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7741 {
7742 /* Disable ADDR, NACK and STOP interrupts */
7743 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7744 }
7745
7746 if (InterruptRequest == I2C_XFER_ERROR_IT)
7747 {
7748 /* Enable ERR and NACK interrupts */
7749 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7750 }
7751
7752 if (InterruptRequest == I2C_XFER_CPLT_IT)
7753 {
7754 /* Enable STOP interrupts */
7755 tmpisr |= I2C_IT_STOPI;
7756 }
7757
7758 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7759 {
7760 /* Enable TC interrupts */
7761 tmpisr |= I2C_IT_TCI;
7762 }
7763
7764 /* Disable interrupts only at the end */
7765 /* to avoid a breaking situation like at "t" time */
7766 /* all disable interrupts request are not done */
7767 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
7768 }
7769
7770 /**
7771 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7772 * @param hi2c I2C handle.
7773 * @retval None
7774 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7775 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7776 {
7777 /* if user set XferOptions to I2C_OTHER_FRAME */
7778 /* it request implicitly to generate a restart condition */
7779 /* set XferOptions to I2C_FIRST_FRAME */
7780 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7781 {
7782 hi2c->XferOptions = I2C_FIRST_FRAME;
7783 }
7784 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7785 /* it request implicitly to generate a restart condition */
7786 /* then generate a stop condition at the end of transfer */
7787 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7788 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7789 {
7790 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7791 }
7792 else
7793 {
7794 /* Nothing to do */
7795 }
7796 }
7797
7798 /**
7799 * @}
7800 */
7801
7802 #endif /* HAL_I2C_MODULE_ENABLED */
7803 /**
7804 * @}
7805 */
7806
7807 /**
7808 * @}
7809 */
7810
