1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_hal_cryp.c
4 * @author MCD Application Team
5 * @brief CRYP HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Cryptography (CRYP) peripheral:
8 * + Initialization and de-initialization functions
9 * + AES processing functions
10 * + DMA callback functions
11 * + CRYP IRQ handler management
12 * + Peripheral State functions
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2022 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### How to use this driver #####
28 ==============================================================================
29 [..]
30 The CRYP HAL driver can be used in CRYP IP as follows:
31
32 (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
33 (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
34 (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
35 (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
36 (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
37 (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
38 (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
39 (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
40 (+++) Configure and enable two DMA streams one for managing data transfer from
41 memory to peripheral (input stream) and another stream for managing data
42 transfer from peripheral to memory (output stream)
43 (+++) Associate the initialized DMA handle to the CRYP DMA handle
44 using __HAL_LINKDMA()
45 (+++) Configure the priority and enable the NVIC for the transfer complete
46 interrupt on the two DMA Streams. The output stream should have higher
47 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
48
49 (#)Initialize the CRYP according to the specified parameters :
50 (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
51 (##) The key size: 128, 192 or 256.
52 (##) The AlgoMode AES Algorithm ECB/CBC/CTR/GCM or CCM.
53 (##) The initialization vector (counter). It is not used in ECB mode.
54 (##) The key buffer used for encryption/decryption.
55 (##) The Header used only in AES GCM and CCM Algorithm for authentication.
56 (##) The HeaderSize used to give size of header buffer in words or bytes, depending upon
57 HeaderWidthUnit field.
58 (##) The HeaderWidthUnit field. It specifies whether the header length
59 (##) The HeaderSize The size of header buffer in word.
60 (##) The B0 block is the first authentication block used only in AES CCM mode.
61
62 (#)Three processing (encryption/decryption) functions are available:
63 (##) Polling mode: encryption and decryption APIs are blocking functions
64 i.e. they process the data and wait till the processing is finished,
65 e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
66 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
67 i.e. they process the data under interrupt,
68 e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
69 (##) DMA mode: encryption and decryption APIs are not blocking functions
70 i.e. the data transfer is ensured by DMA,
71 e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
72
73 (#)When the processing function is called at first time after HAL_CRYP_Init()
74 the CRYP peripheral is configured and processes the buffer in input.
75 At second call, no need to Initialize the CRYP, user have to get current configuration via
76 HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
77 new parameters, finally user can start encryption/decryption.
78
79 (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
80
81 (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
82 without having to configure again the Key or the Initialization Vector between each API call,
83 the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
84 Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(),
85 HAL_CRYP_Encrypt_DMA()or HAL_CRYP_Decrypt_DMA().
86
87 [..]
88 The cryptographic processor supports following standards:
89 (#) The advanced encryption standard (AES) supported by CRYP:
90 (##)128-bit data block processing
91 (##) chaining modes supported :
92 (+++) Electronic Code Book(ECB)
93 (+++) Cipher Block Chaining (CBC)
94 (+++) Counter mode (CTR)
95 (+++) Galois/counter mode (GCM/GMAC)
96 (+++) Counter with Cipher Block Chaining-Message(CCM)
97 (##) keys length Supported :
98 (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
99
100 [..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
101 (#) Algorithm supported :
102 (##) Galois/counter mode (GCM)
103 (##) Galois message authentication code (GMAC) :is exactly the same as
104 GCM algorithm composed only by an header.
105 (#) Four phases are performed in GCM :
106 (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
107 (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
108 computation only.
109 (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
110 encryption + data XORing. It works in a similar way for ciphertext (C).
111 (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
112 HAL_CRYPEx_AESGCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond
113 to the Tag. user should consider only part of this 4 words, if Tag length is less than 128 bits.
114 (#) structure of message construction in GCM is defined as below :
115 (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
116 (##) The authenticated header A (also knows as Additional Authentication Data AAD)
117 this part of the message is only authenticated, not encrypted.
118 (##) The plaintext message P is both authenticated and encrypted as ciphertext.
119 GCM standard specifies that ciphertext has same bit length as the plaintext.
120 (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
121 (on 64 bits)
122
123 [..] This section describe The AES Counter with Cipher Block Chaining-Message
124 Authentication Code (CCM) supported by both CRYP IP:
125 (#) Specific parameters for CCM :
126
127 (##) B0 block : According to NIST Special Publication 800-38C,
128 The first block B0 is formatted as follows, where l(m) is encoded in
129 most-significant-byte first order(see below table 3)
130
131 (+++) Q: a bit string representation of the octet length of P (plaintext)
132 (+++) q The octet length of the binary representation of the octet length of the payload
133 (+++) A nonce (N), n The octet length of the where n+q=15.
134 (+++) Flags: most significant octet containing four flags for control information,
135 (+++) t The octet length of the MAC.
136 (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
137 the associated data length expressed in bytes (a) defined as below:
138 (+++) If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
139 (+++) If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
140 (+++) If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
141 (##) CTRx block : control blocks
142 (+++) Generation of CTR1 from first block B0 information :
143 equal to B0 with first 5 bits zeroed and most significant bits storing octet
144 length of P also zeroed, then incremented by one ( see below Table 4)
145 (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.
146
147 (#) Four phases are performed in CCM for CRYP IP:
148 (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
149 (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
150 computation only.
151 (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
152 encryption + data XORing. It works in a similar way for ciphertext (C).
153 (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
154 HAL_CRYPEx_AESCCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond to the Tag.
155 user should consider only part of this 4 words, if Tag length is less than 128 bits
156
157 *** Callback registration ***
158 =============================
159
160 [..]
161 The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
162 allows the user to configure dynamically the driver callbacks.
163 Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
164 to register an interrupt callback.
165
166 [..]
167 Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
168 (+) InCpltCallback : Input FIFO transfer completed callback.
169 (+) OutCpltCallback : Output FIFO transfer completed callback.
170 (+) ErrorCallback : callback for error detection.
171 (+) MspInitCallback : CRYP MspInit.
172 (+) MspDeInitCallback : CRYP MspDeInit.
173 This function takes as parameters the HAL peripheral handle, the Callback ID
174 and a pointer to the user callback function.
175
176 [..]
177 Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
178 weak function.
179 @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
180 and the Callback ID.
181 This function allows to reset following callbacks:
182 (+) InCpltCallback : Input FIFO transfer completed callback.
183 (+) OutCpltCallback : Output FIFO transfer completed callback.
184 (+) ErrorCallback : callback for error detection.
185 (+) MspInitCallback : CRYP MspInit.
186 (+) MspDeInitCallback : CRYP MspDeInit.
187
188 [..]
189 By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
190 all callbacks are set to the corresponding weak functions :
191 examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
192 Exception done for MspInit and MspDeInit functions that are
193 reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
194 these callbacks are null (not registered beforehand).
195 if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
196 keep and use the user MspInit/MspDeInit functions (registered beforehand)
197
198 [..]
199 Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
200 Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
201 in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
202 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
203 In that case first register the MspInit/MspDeInit user callbacks
204 using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
205 or @ref HAL_CRYP_Init() function.
206
207 [..]
208 When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
209 not defined, the callback registration feature is not available and all callbacks
210 are set to the corresponding weak functions.
211
212 @endverbatim
213
214 Table 1. Initial Counter Block (ICB)
215 +-------------------------------------------------------+
216 | Initialization vector (IV) | Counter |
217 |----------------|----------------|-----------|---------|
218 127 95 63 31 0
219
220
221 Bit Number Register Contents
222 ---------- --------------- -----------
223 127 ...96 CRYP_IV1R[31:0] ICB[127:96]
224 95 ...64 CRYP_IV1L[31:0] B0[95:64]
225 63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
226 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
227
228 Table 2. GCM last block definition
229
230 +-------------------------------------------------------------------+
231 | Bit[0] | Bit[32] | Bit[64] | Bit[96] |
232 |-----------|--------------------|-----------|----------------------|
233 | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
234 |-----------|--------------------|-----------|----------------------|
235
236 Table 3. B0 block
237 Octet Number Contents
238 ------------ ---------
239 0 Flags
240 1 ... 15-q Nonce N
241 16-q ... 15 Q
242
243 the Flags field is formatted as follows:
244
245 Bit Number Contents
246 ---------- ----------------------
247 7 Reserved (always zero)
248 6 Adata
249 5 ... 3 (t-2)/2
250 2 ... 0 [q-1]3
251
252 Table 4. CTRx block
253 Bit Number Register Contents
254 ---------- --------------- -----------
255 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
256 bit 0 that is set to 1
257 95 ...64 CRYP_IV1L[31:0] B0[95:64]
258 63 ... 32 CRYP_IV0R[31:0] B0[63:32]
259 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
260 */
261
262 /* Includes ------------------------------------------------------------------*/
263 #include "stm32h7rsxx_hal.h"
264
265 /** @addtogroup STM32H7RSxx_HAL_Driver
266 * @{
267 */
268
269 #if defined (CRYP)
270
271 /** @defgroup CRYP CRYP
272 * @brief CRYP HAL module driver.
273 * @{
274 */
275
276
277 #ifdef HAL_CRYP_MODULE_ENABLED
278
279 /* Private typedef -----------------------------------------------------------*/
280 /* Private define ------------------------------------------------------------*/
281 /** @addtogroup CRYP_Private_Defines
282 * @{
283 */
284 #define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/
285 #define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is
286 299 clock cycles.*/
287 #define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
288
289 #define CRYP_GENERAL_TIMEOUT 500U
290
291 #define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
292 #define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
293 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
294 #define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */
295 #define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U /*!< GCM/CCM payload phase is suspended */
296 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
297 #define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in
298 DMA mode */
299
300 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
301 #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
302 #define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */
303 #define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */
304 #define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */
305 #endif /* USE_HAL_CRYP_ONLY */
306
307 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
308 #define SAES_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
309 #define SAES_PHASE_HEADER SAES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
310 #define SAES_PHASE_PAYLOAD SAES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
311 #define SAES_PHASE_FINAL SAES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
312 #endif /* USE_HAL_SAES_ONLY */
313
314 /* CTR1 information to use in CCM algorithm */
315 #define CRYP_CCM_CTR1_0 0x07FFFFFFU
316 #define CRYP_CCM_CTR1_1 0xFFFFFF00U
317 #define CRYP_CCM_CTR1_2 0x00000001U
318
319 #define IT_SUSPENDED 0x00000000U
320 #define DMA_SUSPENDED 0x00000001U
321
322 #define ALGOMODE_CRYP_TO_CHMOD_SAES 0
323 #define ALGOMODE_SAES_TO_CHMOD_CRYP 1
324 /**
325 * @}
326 */
327
328
329 /* Private macro -------------------------------------------------------------*/
330 /** @addtogroup CRYP_Private_Macros
331 * @{
332 */
333
334 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
335 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{MODIFY_REG(((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR, \
336 CRYP_CR_GCM_CCMPH, (__PHASE__)); \
337 }while(0)
338 #endif /* USE_HAL_CRYP_ONLY */
339
340 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
341 #define SAES_SET_PHASE(__HANDLE__, __PHASE__) do{MODIFY_REG(((SAES_TypeDef *)((__HANDLE__)->Instance))->CR, \
342 SAES_CR_GCMPH, (__PHASE__)); \
343 }while(0)
344 #endif /* USE_HAL_SAES_ONLY */
345
346 #define HAL_CRYP_FIFO_FLUSH(__HANDLE__) (((CRYP_TypeDef *)((__HANDLE__)->Instance))->CR |= CRYP_CR_FFLUSH)
347
348
349 /**
350 * @}
351 */
352
353 /* Private struct -------------------------------------------------------------*/
354 /* Private variables ---------------------------------------------------------*/
355 /* Private function prototypes -----------------------------------------------*/
356 /** @addtogroup CRYP_Private_Functions_prototypes
357 * @{
358 */
359
360 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
361 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
362 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
363 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
364 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
365 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
366 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
367 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
368 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
369 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
370 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
371 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
372 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
373 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
374 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
375 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
376 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
377 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
378 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
379 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
380 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
381 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
382 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
383 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
384 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
385 #endif /* USE_HAL_CRYP_ONLY */
386 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
387 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
388 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
389 #endif /* USE_HAL_SAES_ONLY */
390 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
391 static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output);
392 static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input);
393 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
394 static void CRYP_Read_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t Algorithm);
395 #endif /* USE_HAL_CRYP_ONLY */
396 static void CRYP_Write_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t Algorithm);
397 static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp);
398 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
399 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
400 static uint32_t CRYP_SAES_AlgoConversion(uint32_t algo, uint32_t order);
401 #endif /* USE_HAL_SAES_ONLY */
402 /**
403 * @}
404 */
405
406 /* Exported functions ---------------------------------------------------------*/
407
408 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
409 * @{
410 */
411
412
413 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
414 * @brief CRYP Initialization and Configuration functions.
415 *
416 @verbatim
417 ========================================================================================
418 ##### Initialization, de-initialization and Set and Get configuration functions #####
419 ========================================================================================
420 [..] This section provides functions allowing to:
421 (+) Initialize the CRYP
422 (+) DeInitialize the CRYP
423 (+) Initialize the CRYP MSP
424 (+) DeInitialize the CRYP MSP
425 (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
426 Parameters which are configured in This section are :
427 (++) Key size
428 (++) Data Type : 32, 16, 8 or 1 bit
429 ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
430 (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
431
432
433 @endverbatim
434 * @{
435 */
436
437
438 /**
439 * @brief Initializes the CRYP according to the specified
440 * parameters in the CRYP_ConfigTypeDef and creates the associated handle.
441 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
442 * the configuration information for CRYP module
443 * @retval HAL status
444 */
HAL_CRYP_Init(CRYP_HandleTypeDef * hcryp)445 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
446 {
447 /* Check the CRYP handle allocation */
448 if (hcryp == NULL)
449 {
450 return HAL_ERROR;
451 }
452
453 #if ((USE_HAL_CRYP_ONLY == 1) && (USE_HAL_SAES_ONLY == 0))
454 if (IS_SAES_INSTANCE(hcryp->Instance))
455 {
456 return HAL_ERROR;
457 }
458 #endif /* USE_HAL_CRYP_ONLY */
459
460 #if ((USE_HAL_CRYP_ONLY == 0) && (USE_HAL_SAES_ONLY == 1))
461 if (IS_CRYP_INSTANCE(hcryp->Instance))
462 {
463 return HAL_ERROR;
464 }
465 #endif /* USE_HAL_SAES_ONLY */
466
467 /* Check parameters */
468 #ifdef USE_FULL_ASSERT
469 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
470 if (IS_CRYP_INSTANCE(hcryp->Instance))
471 {
472 assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
473 assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
474 assert_param(IS_CRYP_KEYMODE(hcryp->Init.KeyMode));
475 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
476 {
477 return HAL_ERROR; /* CRYP does not support BYTE as header width unit */
478 }
479 }
480 #endif /* USE_HAL_CRYP_ONLY */
481 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
482 if (IS_SAES_INSTANCE(hcryp->Instance))
483 {
484 assert_param(IS_SAES_KEYSIZE(hcryp->Init.KeySize));
485 assert_param(IS_SAES_ALGORITHM(hcryp->Init.Algorithm));
486 assert_param(IS_SAES_KEYMODE(hcryp->Init.KeyMode));
487 assert_param(IS_SAES_KEYSEL(hcryp->Init.KeySelect));
488 }
489 #endif /* USE_HAL_SAES_ONLY */
490 assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
491 assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
492 #endif /* USE_FULL_ASSERT */
493
494 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
495 if (hcryp->State == HAL_CRYP_STATE_RESET)
496 {
497 /* Allocate lock resource and initialize it */
498 hcryp->Lock = HAL_UNLOCKED;
499
500 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy InCpltCallback */
501 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy OutCpltCallback */
502 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy ErrorCallback */
503
504 if (hcryp->MspInitCallback == NULL)
505 {
506 hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy MspInit */
507 }
508
509 /* Init the low level hardware */
510 hcryp->MspInitCallback(hcryp);
511 }
512 #else
513 if (hcryp->State == HAL_CRYP_STATE_RESET)
514 {
515 /* Allocate lock resource and initialize it */
516 hcryp->Lock = HAL_UNLOCKED;
517
518 /* Init the low level hardware */
519 HAL_CRYP_MspInit(hcryp);
520 }
521 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
522
523 /* Set the key size, data type and algorithm */
524 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
525 if (IS_CRYP_INSTANCE(hcryp->Instance))
526 {
527 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR,
528 CRYP_CR_KMOD | CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
529 hcryp->Init.KeyMode | hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
530 }
531 #endif /* USE_HAL_CRYP_ONLY */
532 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
533 if (IS_SAES_INSTANCE(hcryp->Instance))
534 {
535 /* Wait for BUSY flag to go to 0 */
536 if (CRYP_WaitOnBUSYFlag(hcryp, CRYP_GENERAL_TIMEOUT) != HAL_OK)
537 {
538 /* Disable the CRYP peripheral clock */
539 __HAL_CRYP_DISABLE(hcryp);
540
541 /* Change state */
542 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
543 hcryp->State = HAL_CRYP_STATE_READY;
544
545 /* Process unlocked */
546 __HAL_UNLOCK(hcryp);
547 return HAL_ERROR;
548 }
549
550 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR,
551 SAES_CR_KEYSEL | SAES_CR_KMOD | SAES_CR_DATATYPE | SAES_CR_KEYSIZE | SAES_CR_CHMOD,
552 hcryp->Init.KeySelect | hcryp->Init.KeyMode | SAES_CONV_DATATYPE(hcryp->Init.DataType) | \
553 SAES_CONV_KEYSIZE(hcryp->Init.KeySize) | CRYP_SAES_AlgoConversion(hcryp->Init.Algorithm,
554 ALGOMODE_CRYP_TO_CHMOD_SAES));
555 }
556 #endif /* USE_HAL_CRYP_ONLY */
557
558 /* Read Device ID to indicate CRYP1 IP Version */
559 hcryp->Version = HAL_GetREVID();
560
561 /* Reset Error Code field */
562 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
563
564 /* Reset peripheral Key and IV configuration flag */
565 hcryp->KeyIVConfig = 0U;
566
567 /* Change the CRYP state */
568 hcryp->State = HAL_CRYP_STATE_READY;
569
570 /* Set the default CRYP phase */
571 hcryp->Phase = CRYP_PHASE_READY;
572
573 /* Return function status */
574 return HAL_OK;
575 }
576
577 /**
578 * @brief De-Initializes the CRYP peripheral.
579 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
580 * the configuration information for CRYP module
581 * @retval HAL status
582 */
HAL_CRYP_DeInit(CRYP_HandleTypeDef * hcryp)583 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
584 {
585 /* Check the CRYP handle allocation */
586 if (hcryp == NULL)
587 {
588 return HAL_ERROR;
589 }
590
591 #if ((USE_HAL_CRYP_ONLY == 1) && (USE_HAL_SAES_ONLY == 0))
592 if (IS_SAES_INSTANCE(hcryp->Instance))
593 {
594 return HAL_ERROR;
595 }
596 #endif /* USE_HAL_CRYP_ONLY */
597
598 #if ((USE_HAL_CRYP_ONLY == 0) && (USE_HAL_SAES_ONLY == 1))
599 if (IS_CRYP_INSTANCE(hcryp->Instance))
600 {
601 return HAL_ERROR;
602 }
603 #endif /* USE_HAL_SAES_ONLY */
604
605 /* Set the default CRYP phase */
606 hcryp->Phase = CRYP_PHASE_READY;
607
608 /* Reset CrypInCount and CrypOutCount */
609 hcryp->CrypInCount = 0;
610 hcryp->CrypOutCount = 0;
611 hcryp->CrypHeaderCount = 0;
612
613 /* Disable the CRYP peripheral clock */
614 __HAL_CRYP_DISABLE(hcryp);
615
616 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
617 if (hcryp->MspDeInitCallback == NULL)
618 {
619 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy MspDeInit */
620 }
621 /* DeInit the low level hardware */
622 hcryp->MspDeInitCallback(hcryp);
623
624 #else
625 /* DeInit the low level hardware: CLOCK, NVIC.*/
626 HAL_CRYP_MspDeInit(hcryp);
627 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
628
629 /* Change the CRYP state */
630 hcryp->State = HAL_CRYP_STATE_RESET;
631
632 /* Release Lock */
633 __HAL_UNLOCK(hcryp);
634
635 /* Return function status */
636 return HAL_OK;
637 }
638
639 /**
640 * @brief Configure the CRYP according to the specified
641 * parameters in the CRYP_ConfigTypeDef
642 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
643 * @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains
644 * the configuration information for CRYP module
645 * @retval HAL status
646 */
HAL_CRYP_SetConfig(CRYP_HandleTypeDef * hcryp,CRYP_ConfigTypeDef * pConf)647 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
648 {
649 /* Check the CRYP handle allocation */
650 if ((hcryp == NULL) || (pConf == NULL))
651 {
652 return HAL_ERROR;
653 }
654
655 /* Check parameters */
656 #ifdef USE_FULL_ASSERT
657 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
658 if (IS_CRYP_INSTANCE(hcryp->Instance))
659 {
660 assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
661 assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
662 assert_param(IS_CRYP_KEYMODE(pConf->KeyMode));
663 if (pConf->HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
664 {
665 return HAL_ERROR; /* CRYP does not support BYTE as header width unit */
666 }
667 }
668 #endif /* USE_HAL_CRYP_ONLY */
669 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
670 if (IS_SAES_INSTANCE(hcryp->Instance))
671 {
672 assert_param(IS_SAES_KEYSIZE(pConf->KeySize));
673 assert_param(IS_SAES_ALGORITHM(pConf->Algorithm));
674 assert_param(IS_SAES_KEYMODE(pConf->KeyMode));
675 assert_param(IS_SAES_KEYSEL(pConf->KeySelect));
676 }
677 #endif /* USE_HAL_SAES_ONLY */
678 assert_param(IS_CRYP_DATATYPE(pConf->DataType));
679 assert_param(IS_CRYP_INIT(pConf->KeyIVConfigSkip));
680 #endif /* USE_FULL_ASSERT */
681
682
683 if (hcryp->State == HAL_CRYP_STATE_READY)
684 {
685 /* Change the CRYP state */
686 hcryp->State = HAL_CRYP_STATE_BUSY;
687
688 /* Process locked */
689 __HAL_LOCK(hcryp);
690
691 /* Set CRYP parameters */
692 hcryp->Init.DataType = pConf->DataType;
693 hcryp->Init.pKey = pConf->pKey;
694 hcryp->Init.Algorithm = pConf->Algorithm;
695 hcryp->Init.KeySize = pConf->KeySize;
696 hcryp->Init.pInitVect = pConf->pInitVect;
697 hcryp->Init.Header = pConf->Header;
698 hcryp->Init.HeaderSize = pConf->HeaderSize;
699 hcryp->Init.B0 = pConf->B0;
700 hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
701 hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
702 hcryp->Init.KeyMode = pConf->KeyMode;
703 hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
704 hcryp->Init.KeySelect = pConf->KeySelect;
705
706 /* Set the key size, data type, algo Mode and operating mode*/
707 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
708 if (IS_CRYP_INSTANCE(hcryp->Instance))
709 {
710 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
711 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
712 }
713 #endif /* USE_HAL_CRYP_ONLY */
714 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
715 if (IS_SAES_INSTANCE(hcryp->Instance))
716 {
717 /*in case of HSW, HW, SW or AHK key selection, we should specify Key mode selection (SAES_CR_KMOD) */
718 if ((hcryp->Init.KeySelect != CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_WRAPPED))
719 {
720 /* Set key mode selection (Normal, Wrapped or Shared key )*/
721 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_WRAPPED);
722 }
723
724 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, \
725 SAES_CR_KEYSEL | SAES_CR_KMOD | SAES_CR_DATATYPE | SAES_CR_KEYSIZE | SAES_CR_CHMOD,
726 hcryp->Init.KeySelect | hcryp->Init.KeyMode | SAES_CONV_DATATYPE(hcryp->Init.DataType) | \
727 SAES_CONV_KEYSIZE(hcryp->Init.KeySize) | CRYP_SAES_AlgoConversion(hcryp->Init.Algorithm,
728 ALGOMODE_CRYP_TO_CHMOD_SAES));
729 }
730 #endif /* USE_HAL_SAES_ONLY */
731
732 /* Process Unlocked */
733 __HAL_UNLOCK(hcryp);
734
735 /* Reset Error Code field */
736 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
737
738 /* Change the CRYP state */
739 hcryp->State = HAL_CRYP_STATE_READY;
740
741 /* Set the default CRYP phase */
742 hcryp->Phase = CRYP_PHASE_READY;
743
744 /* Return function status */
745 return HAL_OK;
746 }
747 else
748 {
749 /* Process Unlocked */
750 __HAL_UNLOCK(hcryp);
751
752 /* Busy error code field */
753 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
754 return HAL_ERROR;
755 }
756 }
757
758 /**
759 * @brief Get CRYP Configuration parameters in associated handle.
760 * @param pConf: pointer to a CRYP_ConfigTypeDef structure
761 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
762 * the configuration information for CRYP module
763 * @retval HAL status
764 */
HAL_CRYP_GetConfig(CRYP_HandleTypeDef * hcryp,CRYP_ConfigTypeDef * pConf)765 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
766 {
767 /* Check the CRYP handle allocation */
768 if ((hcryp == NULL) || (pConf == NULL))
769 {
770 return HAL_ERROR;
771 }
772
773 if (hcryp->State == HAL_CRYP_STATE_READY)
774 {
775 /* Change the CRYP state */
776 hcryp->State = HAL_CRYP_STATE_BUSY;
777
778 /* Process locked */
779 __HAL_LOCK(hcryp);
780
781 /* Get CRYP parameters */
782 pConf->DataType = hcryp->Init.DataType;
783 pConf->pKey = hcryp->Init.pKey;
784 pConf->Algorithm = hcryp->Init.Algorithm;
785 pConf->KeySize = hcryp->Init.KeySize ;
786 pConf->pInitVect = hcryp->Init.pInitVect;
787 pConf->Header = hcryp->Init.Header ;
788 pConf->HeaderSize = hcryp->Init.HeaderSize;
789 pConf->B0 = hcryp->Init.B0;
790 pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
791 pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
792 pConf->KeyMode = hcryp->Init.KeyMode;
793 pConf->KeySelect = hcryp->Init.KeySelect;
794 pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
795
796 /* Process Unlocked */
797 __HAL_UNLOCK(hcryp);
798
799 /* Change the CRYP state */
800 hcryp->State = HAL_CRYP_STATE_READY;
801
802 /* Return function status */
803 return HAL_OK;
804 }
805 else
806 {
807 /* Process Unlocked */
808 __HAL_UNLOCK(hcryp);
809
810 /* Busy error code field */
811 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
812 return HAL_ERROR;
813 }
814 }
815 /**
816 * @brief Initializes the CRYP MSP.
817 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
818 * the configuration information for CRYP module
819 * @retval None
820 */
HAL_CRYP_MspInit(CRYP_HandleTypeDef * hcryp)821 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
822 {
823 /* Prevent unused argument(s) compilation warning */
824 UNUSED(hcryp);
825
826 /* NOTE : This function Should not be modified, when the callback is needed,
827 the HAL_CRYP_MspInit could be implemented in the user file
828 */
829 }
830
831 /**
832 * @brief DeInitializes CRYP MSP.
833 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
834 * the configuration information for CRYP module
835 * @retval None
836 */
HAL_CRYP_MspDeInit(CRYP_HandleTypeDef * hcryp)837 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
838 {
839 /* Prevent unused argument(s) compilation warning */
840 UNUSED(hcryp);
841
842 /* NOTE : This function Should not be modified, when the callback is needed,
843 the HAL_CRYP_MspDeInit could be implemented in the user file
844 */
845 }
846
847 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
848 /**
849 * @brief Register a User CRYP Callback
850 * To be used instead of the weak predefined callback
851 * @param hcryp cryp handle
852 * @param CallbackID ID of the callback to be registered
853 * This parameter can be one of the following values:
854 * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
855 * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
856 * @arg @ref HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID
857 * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
858 * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
859 * @param pCallback pointer to the Callback function
860 * @retval status
861 */
HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef * hcryp,HAL_CRYP_CallbackIDTypeDef CallbackID,pCRYP_CallbackTypeDef pCallback)862 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
863 pCRYP_CallbackTypeDef pCallback)
864 {
865 HAL_StatusTypeDef status = HAL_OK;
866
867 if (pCallback == NULL)
868 {
869 /* Update the error code */
870 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
871
872 return HAL_ERROR;
873 }
874 /* Process locked */
875 __HAL_LOCK(hcryp);
876
877 if (hcryp->State == HAL_CRYP_STATE_READY)
878 {
879 switch (CallbackID)
880 {
881 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
882 hcryp->InCpltCallback = pCallback;
883 break;
884
885 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
886 hcryp->OutCpltCallback = pCallback;
887 break;
888
889 case HAL_CRYP_ERROR_CB_ID :
890 hcryp->ErrorCallback = pCallback;
891 break;
892
893 case HAL_CRYP_MSPINIT_CB_ID :
894 hcryp->MspInitCallback = pCallback;
895 break;
896
897 case HAL_CRYP_MSPDEINIT_CB_ID :
898 hcryp->MspDeInitCallback = pCallback;
899 break;
900
901 default :
902 /* Update the error code */
903 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
904 /* Return error status */
905 status = HAL_ERROR;
906 break;
907 }
908 }
909 else if (hcryp->State == HAL_CRYP_STATE_RESET)
910 {
911 switch (CallbackID)
912 {
913 case HAL_CRYP_MSPINIT_CB_ID :
914 hcryp->MspInitCallback = pCallback;
915 break;
916
917 case HAL_CRYP_MSPDEINIT_CB_ID :
918 hcryp->MspDeInitCallback = pCallback;
919 break;
920
921 default :
922 /* Update the error code */
923 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
924 /* Return error status */
925 status = HAL_ERROR;
926 break;
927 }
928 }
929 else
930 {
931 /* Update the error code */
932 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
933 /* Return error status */
934 status = HAL_ERROR;
935 }
936
937 /* Release Lock */
938 __HAL_UNLOCK(hcryp);
939
940 return status;
941 }
942
943 /**
944 * @brief Unregister an CRYP Callback
945 * CRYP callback is redirected to the weak predefined callback
946 * @param hcryp cryp handle
947 * @param CallbackID ID of the callback to be unregistered
948 * This parameter can be one of the following values:
949 * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
950 * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
951 * @arg @ref HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID
952 * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
953 * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
954 * @retval status
955 */
HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef * hcryp,HAL_CRYP_CallbackIDTypeDef CallbackID)956 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
957 {
958 HAL_StatusTypeDef status = HAL_OK;
959
960 /* Process locked */
961 __HAL_LOCK(hcryp);
962
963 if (hcryp->State == HAL_CRYP_STATE_READY)
964 {
965 switch (CallbackID)
966 {
967 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
968 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy InCpltCallback */
969 break;
970
971 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
972 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy OutCpltCallback */
973 break;
974
975 case HAL_CRYP_ERROR_CB_ID :
976 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy ErrorCallback */
977 break;
978
979 case HAL_CRYP_MSPINIT_CB_ID :
980 hcryp->MspInitCallback = HAL_CRYP_MspInit;
981 break;
982
983 case HAL_CRYP_MSPDEINIT_CB_ID :
984 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
985 break;
986
987 default :
988 /* Update the error code */
989 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
990 /* Return error status */
991 status = HAL_ERROR;
992 break;
993 }
994 }
995 else if (hcryp->State == HAL_CRYP_STATE_RESET)
996 {
997 switch (CallbackID)
998 {
999 case HAL_CRYP_MSPINIT_CB_ID :
1000 hcryp->MspInitCallback = HAL_CRYP_MspInit;
1001 break;
1002
1003 case HAL_CRYP_MSPDEINIT_CB_ID :
1004 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
1005 break;
1006
1007 default :
1008 /* Update the error code */
1009 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
1010 /* Return error status */
1011 status = HAL_ERROR;
1012 break;
1013 }
1014 }
1015 else
1016 {
1017 /* Update the error code */
1018 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;;
1019 /* Return error status */
1020 status = HAL_ERROR;
1021 }
1022
1023 /* Release Lock */
1024 __HAL_UNLOCK(hcryp);
1025
1026 return status;
1027 }
1028 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
1029
1030
1031 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
1032 /**
1033 * @brief Request CRYP processing suspension when in interruption mode.
1034 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1035 * the configuration information for CRYP module.
1036 * @note Set the handle field SuspendRequest to the appropriate value so that
1037 * the on-going CRYP processing is suspended as soon as the required
1038 * conditions are met.
1039 * @note HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done
1040 * in non-blocking interrupt mode.
1041 * @retval None
1042 */
HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef * hcryp)1043 void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp)
1044 {
1045 /* Set Handle SuspendRequest field */
1046 hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
1047 }
1048
1049 /**
1050 * @brief Request CRYP processing suspension when in DMA mode.
1051 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1052 * the configuration information for CRYP module.
1053 * @note Set the handle field SuspendRequest to the appropriate value so that
1054 * the on-going CRYP processing is suspended as soon as the required
1055 * conditions are met.
1056 * @note HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done
1057 * in non-blocking DMA mode.
1058 * @retval None
1059 */
HAL_CRYP_DMAProcessSuspend(CRYP_HandleTypeDef * hcryp)1060 HAL_StatusTypeDef HAL_CRYP_DMAProcessSuspend(CRYP_HandleTypeDef *hcryp)
1061 {
1062 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1063 uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
1064 #endif /* USE_HAL_SAES_ONLY */
1065 uint32_t tmp_remaining_DMATransferSize_inWords;
1066 uint32_t tmp_initial_DMATransferSize_inWords;
1067
1068 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1069 if (IS_CRYP_INSTANCE(hcryp->Instance))
1070 {
1071 /* Stop the DMA transfers to the IN FIFO by clearing to 0 the DIEN bit in
1072 the CRYP_DMACR register */
1073 ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (~CRYP_DMACR_DIEN);
1074
1075 /* Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the
1076 CRYP_SR) and the BUSY bit is cleared */
1077 while (((((CRYP_TypeDef *)(hcryp->Instance))->SR) & (CRYP_SR_IFEM | CRYP_SR_OFNE | CRYP_SR_BUSY)) != CRYP_SR_IFEM)
1078 {
1079 /* nothing todo */
1080 }
1081
1082 /* Stop the DMA transfers from the OUT FIFO by clearing to 0 the DOEN
1083 bit in the CRYP_DMACR register */
1084 ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (~CRYP_DMACR_DOEN);
1085
1086 /* Disable the CRYP peripheral */
1087 __HAL_CRYP_DISABLE(hcryp);
1088 }
1089 #endif /* USE_HAL_CRYP_ONLY */
1090 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1091 if (IS_SAES_INSTANCE(hcryp->Instance))
1092 {
1093 /* Stop the DMA transfer to the IN FIFO by clearing the DMAINEN bit of the SAES_CR register */
1094 (((SAES_TypeDef *)(hcryp->Instance)))->CR &= (~SAES_CR_DMAINEN);
1095
1096 /* Wait for CCF flag to be raised */
1097 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
1098 {
1099 /* Disable the CRYP peripheral clock */
1100 __HAL_CRYP_DISABLE(hcryp);
1101
1102 /* Change state */
1103 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
1104 hcryp->State = HAL_CRYP_STATE_READY;
1105
1106 /* Process unlocked */
1107 __HAL_UNLOCK(hcryp);
1108 /*Call registered error callback*/
1109 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
1110 hcryp->ErrorCallback(hcryp);
1111 #else
1112 /*Call legacy error callback*/
1113 HAL_CRYP_ErrorCallback(hcryp);
1114 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
1115 }
1116
1117 /* Stop the DMA transfer from the OUT FIFO by clearing the DMAOUTEN bit of the SAES_CR register */
1118 ((SAES_TypeDef *)(hcryp->Instance))->CR &= (~SAES_CR_DMAOUTEN);
1119
1120 /* Clear the CCF flag by setting the CCF bit of the SAES_ICR register */
1121 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
1122 }
1123 #endif /* USE_HAL_SAES_ONLY */
1124
1125 /* At this point, DMA interface is disabled and no transfer is on-going */
1126 /* Retrieve from the DMA handle how many words remain to be read and written */
1127 /* DMA3 used, DMA_CBR1_BNDT in bytes, DMA_CSR_FIFOL in words */
1128 tmp_remaining_DMATransferSize_inWords = ((((DMA_Channel_TypeDef *)hcryp->hdmain->Instance)->CBR1) & \
1129 DMA_CBR1_BNDT) / 4U;
1130 tmp_remaining_DMATransferSize_inWords += ((((DMA_Channel_TypeDef *)hcryp->hdmain->Instance)->CSR) & \
1131 DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos;
1132
1133 /* Disable DMA channels */
1134 /* Note that the Abort function will
1135 - Clear the transfer error flags
1136 - Unlock
1137 - Set the State
1138 */
1139 if (HAL_DMA_Abort(hcryp->hdmain) != HAL_OK)
1140 {
1141 return HAL_ERROR;
1142 }
1143 if (HAL_DMA_Abort(hcryp->hdmaout) != HAL_OK)
1144 {
1145 return HAL_ERROR;
1146 }
1147
1148 /* Compute how many words were supposed to be transferred by DMA */
1149 /* hcryp->CrypInCount is in bytes, must be a multiple of 4 (no padding handled for ECB or CBC) */
1150 tmp_initial_DMATransferSize_inWords = ((uint32_t) hcryp->Size / 4U);
1151
1152 /* Accordingly, update the input and output pointers that points at the next word to be
1153 transferred to the Peripheral by DMA or read from the Peripheral by the DMA */
1154 hcryp->pCrypInBuffPtr += (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
1155 hcryp->pCrypOutBuffPtr += (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
1156
1157 /* And store in CrypInCount the remaining size to transfer (in words) */
1158 hcryp->CrypInCount = (uint16_t)tmp_remaining_DMATransferSize_inWords;
1159 hcryp->CrypOutCount = (uint16_t)tmp_remaining_DMATransferSize_inWords;
1160 hcryp->State = HAL_CRYP_STATE_SUSPENDED;
1161
1162 return HAL_OK;
1163
1164 }
1165
1166
1167 /**
1168 * @brief CRYP processing suspension and peripheral internal parameters storage.
1169 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1170 * the configuration information for CRYP module
1171 * @note peripheral internal parameters are stored to be readily available when
1172 * suspended processing is resumed later on.
1173 * @retval HAL status
1174 */
HAL_CRYP_Suspend(CRYP_HandleTypeDef * hcryp)1175 HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
1176 {
1177 HAL_CRYP_STATETypeDef state;
1178 uint32_t tmp_SAES_CR_DMAIN_bit;
1179
1180 /* Request suspension */
1181 /* Check whether the processing is in DMA mode or not */
1182 tmp_SAES_CR_DMAIN_bit = (((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_DMAINEN);
1183 if ((((((CRYP_TypeDef *)(hcryp->Instance))->DMACR & CRYP_DMACR_DIEN) == CRYP_DMACR_DIEN) \
1184 && (IS_CRYP_INSTANCE(hcryp->Instance))) || \
1185 ((tmp_SAES_CR_DMAIN_bit == SAES_CR_DMAINEN) && (IS_SAES_INSTANCE(hcryp->Instance))))
1186 {
1187 if (HAL_CRYP_DMAProcessSuspend(hcryp) != HAL_OK)
1188 {
1189 return HAL_ERROR;
1190 }
1191 hcryp->SuspendedProcessing = DMA_SUSPENDED;
1192 }
1193 else
1194 {
1195 HAL_CRYP_ProcessSuspend(hcryp);
1196 hcryp->SuspendedProcessing = IT_SUSPENDED;
1197 }
1198
1199 do
1200 {
1201 state = HAL_CRYP_GetState(hcryp);
1202 } while ((state != HAL_CRYP_STATE_SUSPENDED) && (state != HAL_CRYP_STATE_READY));
1203
1204 /* Make sure there is no unwanted suspension */
1205 hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
1206
1207 if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY)
1208 {
1209 /* Processing was already over or was about to end. No suspension done */
1210 return HAL_ERROR;
1211 }
1212 else
1213 {
1214 if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
1215 (hcryp->Init.Algorithm == CRYP_AES_CTR) || \
1216 (hcryp->Init.Algorithm == CRYP_AES_GCM) || \
1217 (hcryp->Init.Algorithm == CRYP_AES_CCM))
1218 {
1219 /* Save Initialisation Vector registers */
1220 CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
1221 }
1222
1223 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1224 if (IS_CRYP_INSTANCE(hcryp->Instance))
1225 {
1226 /* Save Control register */
1227 hcryp->CR_saved = ((CRYP_TypeDef *)(hcryp->Instance))->CR;
1228
1229 /* Save context swap registers */
1230 if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
1231 {
1232 CRYP_Read_ContextSwapRegisters(hcryp, hcryp->SUSPxR_saved, hcryp->Init.Algorithm);
1233 }
1234 }
1235 #endif /* USE_HAL_CRYP_ONLY */
1236 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1237 if (IS_SAES_INSTANCE(hcryp->Instance))
1238 {
1239 /* Disable AES */
1240 __HAL_CRYP_DISABLE(hcryp);
1241
1242 /* Clear keys */
1243 ((SAES_TypeDef *)(hcryp->Instance))->KEYR7 = 0x0U;
1244 ((SAES_TypeDef *)(hcryp->Instance))->KEYR6 = 0x0U;
1245 ((SAES_TypeDef *)(hcryp->Instance))->KEYR5 = 0x0U;
1246 ((SAES_TypeDef *)(hcryp->Instance))->KEYR4 = 0x0U;
1247 ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = 0x0U;
1248 ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = 0x0U;
1249 ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = 0x0U;
1250 ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = 0x0U;
1251
1252 /* Save Control register */
1253 hcryp->CR_saved = ((SAES_TypeDef *)(hcryp->Instance))->CR;
1254 }
1255 #endif /* USE_HAL_SAES_ONLY */
1256
1257 /* Save low-priority block CRYP handle parameters */
1258 hcryp->Init_saved = hcryp->Init;
1259 hcryp->pCrypInBuffPtr_saved = hcryp->pCrypInBuffPtr;
1260 hcryp->pCrypOutBuffPtr_saved = hcryp->pCrypOutBuffPtr;
1261 hcryp->CrypInCount_saved = hcryp->CrypInCount;
1262 hcryp->CrypOutCount_saved = hcryp->CrypOutCount;
1263 hcryp->Phase_saved = hcryp->Phase;
1264 hcryp->State_saved = hcryp->State;
1265 hcryp->Size_saved = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? \
1266 (hcryp->Size / 4U) : hcryp->Size);
1267 hcryp->SizesSum_saved = hcryp->SizesSum;
1268 hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount;
1269 hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
1270 }
1271 return HAL_OK;
1272 }
1273
1274
1275 /**
1276 * @brief CRYP processing resumption.
1277 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
1278 * the configuration information for CRYP module
1279 * @note Processing restarts at the exact point where it was suspended, based
1280 * on the parameters saved at suspension time.
1281 * @retval HAL status
1282 */
HAL_CRYP_Resume(CRYP_HandleTypeDef * hcryp)1283 HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
1284 {
1285 /* Check the CRYP handle allocation */
1286 if (hcryp == NULL)
1287 {
1288 return HAL_ERROR;
1289 }
1290
1291 if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED)
1292 {
1293 /* CRYP was not suspended */
1294 return HAL_ERROR;
1295 }
1296 else
1297 {
1298 /* Restore low-priority block CRYP handle parameters */
1299 hcryp->Init = hcryp->Init_saved;
1300 hcryp->State = hcryp->State_saved;
1301 hcryp->Phase = hcryp->Phase_saved;
1302 hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved;
1303
1304 /* Restore low-priority block CRYP handle parameters */
1305 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1306 {
1307 hcryp->Init.pInitVect = hcryp->IV_saved;
1308 }
1309 /* Set State to reset to trigger a HAL_CRYP_MspInit() call in HAL_CRYP_Init() */
1310 __HAL_CRYP_RESET_HANDLE_STATE(hcryp);
1311 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1312 if (IS_CRYP_INSTANCE(hcryp->Instance))
1313 {
1314 ((CRYP_TypeDef *)(hcryp->Instance))->CR |= CRYP_CR_IPRST;
1315 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= (~CRYP_CR_IPRST);
1316 }
1317 #endif /* USE_HAL_CRYP_ONLY */
1318 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1319 if (IS_SAES_INSTANCE(hcryp->Instance))
1320 {
1321 ((SAES_TypeDef *)(hcryp->Instance))->CR |= SAES_CR_IPRST;
1322 ((SAES_TypeDef *)(hcryp->Instance))->CR &= (~SAES_CR_IPRST);
1323 }
1324 #endif /* USE_HAL_SAES_ONLY */
1325
1326 /* Peripheral must be disabled */
1327 __HAL_CRYP_DISABLE(hcryp);
1328
1329 if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || \
1330 (hcryp->Init.Algorithm == CRYP_AES_CBC) || \
1331 (hcryp->Init.Algorithm == CRYP_AES_CTR))
1332 {
1333 (void) HAL_CRYP_Init(hcryp);
1334 }
1335 else
1336 {
1337 /* The following lines are applicable to CRYP peripheral only */
1338
1339 /* Configure again the cryptographic processor with the initial setting in CRYP_CR */
1340 ((CRYP_TypeDef *)(hcryp->Instance))->CR = hcryp->CR_saved;
1341
1342 /* Configure again the key registers */
1343 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1344
1345 /* Restore context swap registers */
1346 CRYP_Write_ContextSwapRegisters(hcryp, hcryp->SUSPxR_saved, hcryp->Init.Algorithm);
1347
1348 /* Restore IV registers */
1349 CRYP_Write_IVRegisters(hcryp, hcryp->IV_saved);
1350
1351 /* At the same time, set handle state back to READY to be able to resume the AES calculations
1352 without the processing APIs returning HAL_BUSY when called. */
1353 hcryp->State = HAL_CRYP_STATE_READY;
1354 }
1355
1356 if (hcryp->SuspendedProcessing == DMA_SUSPENDED)
1357 {
1358 if (((IS_CRYP_INSTANCE(hcryp->Instance)) && \
1359 (READ_BIT(hcryp->CR_saved, CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)) || \
1360 ((IS_SAES_INSTANCE(hcryp->Instance)) && \
1361 (READ_BIT(hcryp->CR_saved, SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)))
1362 {
1363 if (HAL_CRYP_Encrypt_DMA(hcryp, hcryp->pCrypInBuffPtr_saved, (uint16_t) hcryp->CrypInCount_saved,
1364 hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
1365 {
1366 return HAL_ERROR;
1367 }
1368 }
1369 else
1370 {
1371 if (HAL_CRYP_Decrypt_DMA(hcryp, hcryp->pCrypInBuffPtr_saved, (uint16_t) hcryp->CrypInCount_saved,
1372 hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
1373 {
1374 return HAL_ERROR;
1375 }
1376 }
1377 }
1378 else
1379 {
1380 /* Resume low-priority block processing under IT */
1381 hcryp->ResumingFlag = 1U;
1382
1383 if (((IS_CRYP_INSTANCE(hcryp->Instance)) &&
1384 (READ_BIT(hcryp->CR_saved, CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)) || \
1385 ((IS_SAES_INSTANCE(hcryp->Instance)) && \
1386 (READ_BIT(hcryp->CR_saved, SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)))
1387 {
1388 if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved,
1389 hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
1390 {
1391 return HAL_ERROR;
1392 }
1393 }
1394 else
1395 {
1396 if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved,
1397 hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
1398 {
1399 return HAL_ERROR;
1400 }
1401 }
1402 }
1403 }
1404 return HAL_OK;
1405 }
1406 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
1407
1408 /**
1409 * @}
1410 */
1411
1412 /** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
1413 * @brief CRYP processing functions.
1414 *
1415 @verbatim
1416 ==============================================================================
1417 ##### Encrypt Decrypt functions #####
1418 ==============================================================================
1419 [..] This section provides API allowing to Encrypt/Decrypt Data following
1420 Standard AES algorithm configured by the user:
1421
1422 (+) Standard AES supported by CRYP1 IP, list of Algorithm supported:
1423 (++) Electronic Code Book(ECB)
1424 (++) Cipher Block Chaining (CBC)
1425 (++) Counter mode (CTR)
1426 (++) Cipher Block Chaining (CBC)
1427 (++) Counter mode (CTR)
1428 (++) Galois/counter mode (GCM)
1429 (++) Counter with Cipher Block Chaining-Message(CCM)
1430 [..] Three processing functions are available:
1431 (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
1432 (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
1433 (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
1434
1435 @endverbatim
1436 * @{
1437 */
1438
1439
1440 /**
1441 * @brief Encryption mode.
1442 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1443 * the configuration information for CRYP module
1444 * @param Input: Pointer to the input buffer (plaintext)
1445 * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit.
1446 * @param Output: Pointer to the output buffer(ciphertext)
1447 * @param Timeout: Specify Timeout value
1448 * @retval HAL status
1449 */
HAL_CRYP_Encrypt(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output,uint32_t Timeout)1450 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
1451 uint32_t Timeout)
1452 {
1453 uint32_t algo = 0U;
1454 HAL_StatusTypeDef status;
1455
1456 if (hcryp->State == HAL_CRYP_STATE_READY)
1457 {
1458 /* Change state Busy */
1459 hcryp->State = HAL_CRYP_STATE_BUSY;
1460
1461 /* Process locked */
1462 __HAL_LOCK(hcryp);
1463
1464 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1465 hcryp->CrypInCount = 0U;
1466 hcryp->CrypOutCount = 0U;
1467 hcryp->pCrypInBuffPtr = Input;
1468 hcryp->pCrypOutBuffPtr = Output;
1469
1470 /* Calculate Size parameter in Byte*/
1471 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1472 {
1473 hcryp->Size = Size * 4U;
1474 }
1475 else
1476 {
1477 hcryp->Size = Size;
1478 }
1479
1480 /* Set Encryption operating mode*/
1481 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1482 if (IS_CRYP_INSTANCE(hcryp->Instance))
1483 {
1484 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1485
1486 /* algo get algorithm selected */
1487 algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
1488 }
1489 #endif /* USE_HAL_CRYP_ONLY */
1490 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1491 if (IS_SAES_INSTANCE(hcryp->Instance))
1492 {
1493 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_ENCRYPT);
1494
1495 /* algo get algorithm selected */
1496 algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
1497 ALGOMODE_SAES_TO_CHMOD_CRYP);
1498 }
1499 #endif /* USE_HAL_SAES_ONLY */
1500
1501 switch (algo)
1502 {
1503 case CRYP_AES_ECB:
1504 case CRYP_AES_CBC:
1505 case CRYP_AES_CTR:
1506
1507 /* AES encryption */
1508 status = CRYP_AES_Encrypt(hcryp, Timeout);
1509 break;
1510
1511 case CRYP_AES_GCM:
1512
1513 /* AES GCM encryption */
1514 status = CRYP_AESGCM_Process(hcryp, Timeout);
1515 break;
1516
1517 case CRYP_AES_CCM:
1518
1519 /* AES CCM encryption */
1520 status = CRYP_AESCCM_Process(hcryp, Timeout);
1521 break;
1522
1523 default:
1524 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1525 status = HAL_ERROR;
1526 break;
1527 }
1528
1529 if (status == HAL_OK)
1530 {
1531 /* Change the CRYP peripheral state */
1532 hcryp->State = HAL_CRYP_STATE_READY;
1533
1534 /* Process unlocked */
1535 __HAL_UNLOCK(hcryp);
1536 }
1537 }
1538 else
1539 {
1540 /* Process unlocked */
1541 __HAL_UNLOCK(hcryp);
1542
1543 /* Busy error code field */
1544 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1545 status = HAL_ERROR;
1546 }
1547
1548 /* Return function status */
1549 return status ;
1550 }
1551
1552 /**
1553 * @brief Decryption mode.
1554 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1555 * the configuration information for CRYP module
1556 * @param Input: Pointer to the input buffer (ciphertext )
1557 * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
1558 * @param Output: Pointer to the output buffer(plaintext)
1559 * @param Timeout: Specify Timeout value
1560 * @retval HAL status
1561 */
HAL_CRYP_Decrypt(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output,uint32_t Timeout)1562 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
1563 uint32_t Timeout)
1564 {
1565 HAL_StatusTypeDef status;
1566 uint32_t algo = 0U;
1567
1568 if (hcryp->State == HAL_CRYP_STATE_READY)
1569 {
1570 /* Change state Busy */
1571 hcryp->State = HAL_CRYP_STATE_BUSY;
1572
1573 /* Process locked */
1574 __HAL_LOCK(hcryp);
1575
1576 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1577 hcryp->CrypInCount = 0U;
1578 hcryp->CrypOutCount = 0U;
1579 hcryp->pCrypInBuffPtr = Input;
1580 hcryp->pCrypOutBuffPtr = Output;
1581
1582 /* Calculate Size parameter in Byte*/
1583 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1584 {
1585 hcryp->Size = Size * 4U;
1586 }
1587 else
1588 {
1589 hcryp->Size = Size;
1590 }
1591
1592 /* Set Decryption operating mode*/
1593 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1594 if (IS_CRYP_INSTANCE(hcryp->Instance))
1595 {
1596 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1597
1598 /* algo get algorithm selected */
1599 algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
1600 }
1601 #endif /* USE_HAL_CRYP_ONLY */
1602 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1603 if (IS_SAES_INSTANCE(hcryp->Instance))
1604 {
1605 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
1606
1607 /* algo get algorithm selected */
1608 algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
1609 ALGOMODE_SAES_TO_CHMOD_CRYP);
1610 }
1611 #endif /* USE_HAL_SAES_ONLY */
1612
1613 switch (algo)
1614 {
1615 case CRYP_AES_ECB:
1616 case CRYP_AES_CBC:
1617 case CRYP_AES_CTR:
1618
1619 /* AES decryption */
1620 status = CRYP_AES_Decrypt(hcryp, Timeout);
1621 break;
1622
1623 case CRYP_AES_GCM:
1624
1625 /* AES GCM decryption */
1626 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1627 break;
1628
1629 case CRYP_AES_CCM:
1630
1631 /* AES CCM decryption */
1632 status = CRYP_AESCCM_Process(hcryp, Timeout);
1633 break;
1634
1635 default:
1636 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1637 status = HAL_ERROR;
1638 break;
1639 }
1640
1641 if (status == HAL_OK)
1642 {
1643 /* Change the CRYP peripheral state */
1644 hcryp->State = HAL_CRYP_STATE_READY;
1645
1646 /* Process unlocked */
1647 __HAL_UNLOCK(hcryp);
1648 }
1649 }
1650 else
1651 {
1652 /* Process unlocked */
1653 __HAL_UNLOCK(hcryp);
1654
1655 /* Busy error code field */
1656 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1657 status = HAL_ERROR;
1658 }
1659
1660 /* Return function status */
1661 return status;
1662 }
1663
1664 /**
1665 * @brief Encryption in interrupt mode.
1666 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1667 * the configuration information for CRYP module
1668 * @param Input: Pointer to the input buffer (plaintext)
1669 * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
1670 * @param Output: Pointer to the output buffer(ciphertext)
1671 * @retval HAL status
1672 */
HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1673 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1674 {
1675 uint32_t algo = 0U;
1676 HAL_StatusTypeDef status;
1677
1678 if (hcryp->State == HAL_CRYP_STATE_READY)
1679 {
1680 /* Change state Busy */
1681 hcryp->State = HAL_CRYP_STATE_BUSY;
1682
1683 /* Process locked */
1684 __HAL_LOCK(hcryp);
1685
1686 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1687 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
1688 if (hcryp->ResumingFlag == 1U)
1689 {
1690 hcryp->ResumingFlag = 0U;
1691 hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
1692 hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
1693 }
1694 else
1695 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
1696 {
1697 hcryp->CrypInCount = 0U;
1698 hcryp->CrypOutCount = 0U;
1699 }
1700
1701 hcryp->pCrypInBuffPtr = Input;
1702 hcryp->pCrypOutBuffPtr = Output;
1703
1704 /* Calculate Size parameter in Byte*/
1705 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1706 {
1707 hcryp->Size = Size * 4U;
1708 }
1709 else
1710 {
1711 hcryp->Size = Size;
1712 }
1713
1714 /* Set encryption operating mode*/
1715 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1716 if (IS_CRYP_INSTANCE(hcryp->Instance))
1717 {
1718 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1719
1720 /* algo get algorithm selected */
1721 algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
1722 }
1723 #endif /* USE_HAL_CRYP_ONLY */
1724 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1725 if (IS_SAES_INSTANCE(hcryp->Instance))
1726 {
1727 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_ENCRYPT);
1728
1729 /* algo get algorithm selected */
1730 algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
1731 ALGOMODE_SAES_TO_CHMOD_CRYP);
1732 }
1733 #endif /* USE_HAL_SAES_ONLY */
1734
1735 switch (algo)
1736 {
1737 case CRYP_AES_ECB:
1738 case CRYP_AES_CBC:
1739 case CRYP_AES_CTR:
1740
1741 status = CRYP_AES_Encrypt_IT(hcryp);
1742 break;
1743
1744 case CRYP_AES_GCM:
1745
1746 status = CRYP_AESGCM_Process_IT(hcryp) ;
1747 break;
1748
1749 case CRYP_AES_CCM:
1750
1751 status = CRYP_AESCCM_Process_IT(hcryp);
1752 break;
1753
1754 default:
1755 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1756 status = HAL_ERROR;
1757 break;
1758 }
1759 }
1760 else
1761 {
1762 /* Busy error code field */
1763 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1764 status = HAL_ERROR;
1765 }
1766
1767 /* Return function status */
1768 return status ;
1769 }
1770
1771 /**
1772 * @brief Decryption in interrupt mode.
1773 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1774 * the configuration information for CRYP module
1775 * @param Input: Pointer to the input buffer (ciphertext )
1776 * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
1777 * @param Output: Pointer to the output buffer(plaintext)
1778 * @retval HAL status
1779 */
HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1780 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1781 {
1782 uint32_t algo = 0U;
1783 HAL_StatusTypeDef status;
1784
1785 if (hcryp->State == HAL_CRYP_STATE_READY)
1786 {
1787 /* Change state Busy */
1788 hcryp->State = HAL_CRYP_STATE_BUSY;
1789
1790 /* Process locked */
1791 __HAL_LOCK(hcryp);
1792
1793 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1794 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
1795 if (hcryp->ResumingFlag == 1U)
1796 {
1797 hcryp->ResumingFlag = 0U;
1798 hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
1799 hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
1800 }
1801 else
1802 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
1803 {
1804 hcryp->CrypInCount = 0U;
1805 hcryp->CrypOutCount = 0U;
1806 }
1807 hcryp->pCrypInBuffPtr = Input;
1808 hcryp->pCrypOutBuffPtr = Output;
1809
1810 /* Calculate Size parameter in Byte*/
1811 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1812 {
1813 hcryp->Size = Size * 4U;
1814 }
1815 else
1816 {
1817 hcryp->Size = Size;
1818 }
1819
1820 /* Set decryption operating mode*/
1821 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1822 if (IS_CRYP_INSTANCE(hcryp->Instance))
1823 {
1824 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1825
1826 /* algo get algorithm selected */
1827 algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
1828 }
1829 #endif /* USE_HAL_CRYP_ONLY */
1830 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1831 if (IS_SAES_INSTANCE(hcryp->Instance))
1832 {
1833 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
1834
1835 /* algo get algorithm selected */
1836 algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
1837 ALGOMODE_SAES_TO_CHMOD_CRYP);
1838 }
1839 #endif /* USE_HAL_SAES_ONLY */
1840
1841 switch (algo)
1842 {
1843 case CRYP_AES_ECB:
1844 case CRYP_AES_CBC:
1845 case CRYP_AES_CTR:
1846
1847 /* AES decryption */
1848 status = CRYP_AES_Decrypt_IT(hcryp);
1849 break;
1850
1851 case CRYP_AES_GCM:
1852
1853 /* AES GCM decryption */
1854 status = CRYP_AESGCM_Process_IT(hcryp) ;
1855 break;
1856
1857 case CRYP_AES_CCM:
1858
1859 /* AES CCMdecryption */
1860 status = CRYP_AESCCM_Process_IT(hcryp);
1861 break;
1862
1863 default:
1864 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1865 status = HAL_ERROR;
1866 break;
1867 }
1868 }
1869 else
1870 {
1871 /* Busy error code field */
1872 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1873 status = HAL_ERROR;
1874 }
1875
1876 /* Return function status */
1877 return status;
1878 }
1879
1880 /**
1881 * @brief Encryption in DMA mode.
1882 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1883 * the configuration information for CRYP module
1884 * @param Input: Pointer to the input buffer (plaintext)
1885 * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
1886 * @param Output: Pointer to the output buffer(ciphertext)
1887 * @retval HAL status
1888 */
HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1889 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1890 {
1891 HAL_StatusTypeDef status = HAL_OK;
1892 uint32_t algo = 0U;
1893 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
1894 uint32_t tickstart;
1895
1896 if (hcryp->State == HAL_CRYP_STATE_READY)
1897 {
1898 /* Change state Busy */
1899 hcryp->State = HAL_CRYP_STATE_BUSY;
1900
1901 /* Process locked */
1902 __HAL_LOCK(hcryp);
1903
1904 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1905 hcryp->CrypInCount = 0U;
1906 hcryp->CrypOutCount = 0U;
1907 hcryp->pCrypInBuffPtr = Input;
1908 hcryp->pCrypOutBuffPtr = Output;
1909
1910 /* Calculate Size parameter in Byte*/
1911 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1912 {
1913 hcryp->Size = Size * 4U;
1914 }
1915 else
1916 {
1917 hcryp->Size = Size;
1918 }
1919
1920 /* Set Encryption operating mode*/
1921 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1922 if (IS_CRYP_INSTANCE(hcryp->Instance))
1923 {
1924 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1925
1926 /* algo get algorithm selected */
1927 algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
1928 }
1929 #endif /* USE_HAL_CRYP_ONLY */
1930 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
1931 if (IS_SAES_INSTANCE(hcryp->Instance))
1932 {
1933 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_ENCRYPT);
1934
1935 /* algo get algorithm selected */
1936 algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
1937 ALGOMODE_SAES_TO_CHMOD_CRYP);
1938 }
1939 #endif /* USE_HAL_SAES_ONLY */
1940
1941 switch (algo)
1942 {
1943 case CRYP_AES_ECB:
1944 case CRYP_AES_CBC:
1945 case CRYP_AES_CTR:
1946
1947 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1948 {
1949 if (hcryp->KeyIVConfig == 1U)
1950 {
1951 /* If the Key and IV configuration has to be done only once
1952 and if it has already been done, skip it */
1953 DoKeyIVConfig = 0U;
1954 }
1955 else
1956 {
1957 /* If the Key and IV configuration has to be done only once
1958 and if it has not been done already, do it and set KeyIVConfig
1959 to keep track it won't have to be done again next time */
1960 hcryp->KeyIVConfig = 1U;
1961 }
1962 }
1963
1964 if (DoKeyIVConfig == 1U)
1965 {
1966 /* Set the Key */
1967 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
1968 {
1969 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1970 }
1971
1972 /* Get tick */
1973 tickstart = HAL_GetTick();
1974
1975 while (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEYVALID) == 0x0U)
1976 {
1977 /* Check for the Timeout */
1978 if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT)
1979 {
1980 /* Disable the CRYP peripheral clock */
1981 __HAL_CRYP_DISABLE(hcryp);
1982
1983 /* Change state */
1984 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
1985 hcryp->State = HAL_CRYP_STATE_READY;
1986
1987 /* Process unlocked */
1988 __HAL_UNLOCK(hcryp);
1989 return HAL_ERROR;
1990 }
1991 }
1992
1993 /* Set the Initialization Vector*/
1994 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1995 {
1996 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
1997 if (IS_CRYP_INSTANCE(hcryp->Instance))
1998 {
1999 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2000 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2001 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2002 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2003 }
2004 #endif /* USE_HAL_CRYP_ONLY */
2005 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2006 if (IS_SAES_INSTANCE(hcryp->Instance))
2007 {
2008 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2009 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2010 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2011 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2012 }
2013 #endif /* USE_HAL_SAES_ONLY */
2014 }
2015
2016 } /* if (DoKeyIVConfig == 1U) */
2017
2018 /* Set the phase */
2019 hcryp->Phase = CRYP_PHASE_PROCESS;
2020
2021 /* Start DMA process transfer for AES */
2022 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size, (uint32_t)(hcryp->pCrypOutBuffPtr));
2023 break;
2024
2025 case CRYP_AES_GCM:
2026
2027 /* AES GCM encryption */
2028 status = CRYP_AESGCM_Process_DMA(hcryp);
2029 break;
2030
2031 case CRYP_AES_CCM:
2032
2033 /* AES CCM encryption */
2034 status = CRYP_AESCCM_Process_DMA(hcryp);
2035 break;
2036
2037 default:
2038 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
2039 status = HAL_ERROR;
2040 break;
2041 }
2042 }
2043 else
2044 {
2045 /* Busy error code field */
2046 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
2047 status = HAL_ERROR;
2048 }
2049
2050 /* Return function status */
2051 return status;
2052 }
2053
2054 /**
2055 * @brief Decryption in DMA mode.
2056 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2057 * the configuration information for CRYP module
2058 * @param Input: Pointer to the input buffer (ciphertext )
2059 * @param Size: Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
2060 * @param Output: Pointer to the output buffer(plaintext)
2061 * @retval HAL status
2062 */
HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)2063 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
2064 {
2065 uint32_t algo = 0U;
2066 HAL_StatusTypeDef status;
2067
2068 if (hcryp->State == HAL_CRYP_STATE_READY)
2069 {
2070 /* Change state Busy */
2071 hcryp->State = HAL_CRYP_STATE_BUSY;
2072
2073 /* Process locked */
2074 __HAL_LOCK(hcryp);
2075
2076 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
2077 hcryp->CrypInCount = 0U;
2078 hcryp->CrypOutCount = 0U;
2079 hcryp->pCrypInBuffPtr = Input;
2080 hcryp->pCrypOutBuffPtr = Output;
2081
2082 /* Calculate Size parameter in Byte*/
2083 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
2084 {
2085 hcryp->Size = Size * 4U;
2086 }
2087 else
2088 {
2089 hcryp->Size = Size;
2090 }
2091
2092 /* Set decryption operating mode*/
2093 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2094 if (IS_CRYP_INSTANCE(hcryp->Instance))
2095 {
2096 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
2097
2098 /* algo get algorithm selected */
2099 algo = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGOMODE;
2100 }
2101 #endif /* USE_HAL_CRYP_ONLY */
2102 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2103 if (IS_SAES_INSTANCE(hcryp->Instance))
2104 {
2105 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
2106
2107 /* algo get algorithm selected */
2108 algo = CRYP_SAES_AlgoConversion((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_CHMOD),
2109 ALGOMODE_SAES_TO_CHMOD_CRYP);
2110 }
2111 #endif /* USE_HAL_SAES_ONLY */
2112
2113 switch (algo)
2114 {
2115 case CRYP_AES_ECB:
2116 case CRYP_AES_CBC:
2117 case CRYP_AES_CTR:
2118
2119 /* AES decryption */
2120 status = CRYP_AES_Decrypt_DMA(hcryp);
2121 break;
2122
2123 case CRYP_AES_GCM:
2124
2125 /* AES GCM decryption */
2126 status = CRYP_AESGCM_Process_DMA(hcryp);
2127
2128 break;
2129
2130 case CRYP_AES_CCM:
2131
2132 /* AES CCM decryption */
2133 status = CRYP_AESCCM_Process_DMA(hcryp);
2134 break;
2135
2136 default:
2137 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
2138 status = HAL_ERROR;
2139 break;
2140 }
2141 }
2142 else
2143 {
2144 /* Busy error code field */
2145 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
2146 status = HAL_ERROR;
2147 }
2148
2149 /* Return function status */
2150 return status;
2151 }
2152
2153 /**
2154 * @}
2155 */
2156
2157 /** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
2158 * @brief CRYP IRQ handler.
2159 *
2160 @verbatim
2161 ==============================================================================
2162 ##### CRYP IRQ handler management #####
2163 ==============================================================================
2164 [..] This section provides CRYP IRQ handler and callback functions.
2165 (+) HAL_CRYP_IRQHandler CRYP interrupt request
2166 (+) HAL_CRYP_InCpltCallback input data transfer complete callback
2167 (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
2168 (+) HAL_CRYP_ErrorCallback CRYP error callback
2169 (+) HAL_CRYP_GetState return the CRYP state
2170 (+) HAL_CRYP_GetError return the CRYP error code
2171 @endverbatim
2172 * @{
2173 */
2174
2175 /**
2176 * @brief This function handles cryptographic interrupt request.
2177 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2178 * the configuration information for CRYP module
2179 * @retval None
2180 */
HAL_CRYP_IRQHandler(CRYP_HandleTypeDef * hcryp)2181 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
2182 {
2183 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2184 if (IS_CRYP_INSTANCE(hcryp->Instance))
2185 {
2186 uint32_t itstatus = ((CRYP_TypeDef *)(hcryp->Instance))->MISR;
2187
2188 if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U)
2189 {
2190 if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC)
2191 || (hcryp->Init.Algorithm == CRYP_AES_CTR))
2192 {
2193 CRYP_AES_IT(hcryp); /*AES*/
2194 }
2195
2196 else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
2197 {
2198 /* if header phase */
2199 if ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
2200 {
2201 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2202 }
2203 else /* if payload phase */
2204 {
2205 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2206 }
2207 }
2208 else
2209 {
2210 /* Nothing to do */
2211 }
2212 }
2213 }
2214 #endif /* USE_HAL_CRYP_ONLY */
2215 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2216 if (IS_SAES_INSTANCE(hcryp->Instance))
2217 {
2218 /* Check if Read or write error occurred */
2219 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RWEIE) != RESET)
2220 {
2221 /* If write Error occurred */
2222 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_WRERR) != RESET)
2223 {
2224 hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
2225 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
2226 }
2227 /* If read Error occurred */
2228 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RDERR) != RESET)
2229 {
2230 hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
2231 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
2232 }
2233 /*Call error callback*/
2234 HAL_CRYP_ErrorCallback(hcryp);
2235 }
2236 /* Check if Key error occurred */
2237 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_KEIE) != RESET)
2238 {
2239 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEIF) != RESET)
2240 {
2241 hcryp->ErrorCode |= HAL_CRYP_ERROR_KEY;
2242 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_KEIF);
2243 /*Call error callback*/
2244 HAL_CRYP_ErrorCallback(hcryp);
2245 }
2246 }
2247 /* Check if RNG error occurred */
2248 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RNGEIE) != RESET)
2249 {
2250 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RNGEIF) != RESET)
2251 {
2252 hcryp->ErrorCode |= HAL_CRYP_ERROR_RNG;
2253 /*Call error callback*/
2254 HAL_CRYP_ErrorCallback(hcryp);
2255 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RNGEIF);
2256 }
2257 }
2258 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET)
2259 {
2260 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
2261 {
2262 /* Clear computation complete flag */
2263 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
2264
2265 if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
2266 {
2267 /* if header phase */
2268 if ((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_PHASE_HEADER) == SAES_PHASE_HEADER)
2269 {
2270 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2271 }
2272 else /* if payload phase */
2273 {
2274 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2275 }
2276 }
2277 else /* AES Algorithm ECB,CBC or CTR*/
2278 {
2279 CRYP_AES_IT(hcryp);
2280 }
2281 }
2282 }
2283 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
2284 #endif /* USE_HAL_SAES_ONLY */
2285 }
2286
2287 /**
2288 * @brief Return the CRYP error code.
2289 * @param hcryp : pointer to a CRYP_HandleTypeDef structure that contains
2290 * the configuration information for the CRYP IP
2291 * @retval CRYP error code
2292 */
HAL_CRYP_GetError(const CRYP_HandleTypeDef * hcryp)2293 uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp)
2294 {
2295 return hcryp->ErrorCode;
2296 }
2297
2298 /**
2299 * @brief Returns the CRYP state.
2300 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2301 * the configuration information for CRYP module.
2302 * @retval HAL state
2303 */
HAL_CRYP_GetState(const CRYP_HandleTypeDef * hcryp)2304 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp)
2305 {
2306 return hcryp->State;
2307 }
2308
2309 /**
2310 * @brief Input FIFO transfer completed callback.
2311 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2312 * the configuration information for CRYP module.
2313 * @retval None
2314 */
HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef * hcryp)2315 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
2316 {
2317 /* Prevent unused argument(s) compilation warning */
2318 UNUSED(hcryp);
2319
2320 /* NOTE : This function Should not be modified, when the callback is needed,
2321 the HAL_CRYP_InCpltCallback could be implemented in the user file
2322 */
2323 }
2324
2325 /**
2326 * @brief Output FIFO transfer completed callback.
2327 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2328 * the configuration information for CRYP module.
2329 * @retval None
2330 */
HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef * hcryp)2331 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
2332 {
2333 /* Prevent unused argument(s) compilation warning */
2334 UNUSED(hcryp);
2335
2336 /* NOTE : This function Should not be modified, when the callback is needed,
2337 the HAL_CRYP_OutCpltCallback could be implemented in the user file
2338 */
2339 }
2340
2341 /**
2342 * @brief CRYP error callback.
2343 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2344 * the configuration information for CRYP module.
2345 * @retval None
2346 */
HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef * hcryp)2347 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
2348 {
2349 /* Prevent unused argument(s) compilation warning */
2350 UNUSED(hcryp);
2351
2352 /* NOTE : This function Should not be modified, when the callback is needed,
2353 the HAL_CRYP_ErrorCallback could be implemented in the user file
2354 */
2355 }
2356 /**
2357 * @}
2358 */
2359
2360 /* Private functions ---------------------------------------------------------*/
2361 /** @addtogroup CRYP_Private_Functions
2362 * @{
2363 */
2364
2365
2366 /**
2367 * @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
2368 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
2369 * @param Timeout: specify Timeout value
2370 * @retval HAL status
2371 */
CRYP_AES_Encrypt(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2372 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2373 {
2374 uint16_t outcount; /* Temporary CrypOutCount Value */
2375 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2376 uint32_t tickstart;
2377
2378 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2379 {
2380 if (hcryp->KeyIVConfig == 1U)
2381 {
2382 /* If the Key and IV configuration has to be done only once
2383 and if it has already been done, skip it */
2384 DoKeyIVConfig = 0U;
2385 }
2386 else
2387 {
2388 /* If the Key and IV configuration has to be done only once
2389 and if it has not been done already, do it and set KeyIVConfig
2390 to keep track it won't have to be done again next time */
2391 hcryp->KeyIVConfig = 1U;
2392 }
2393 }
2394
2395 if (DoKeyIVConfig == 1U)
2396 {
2397 /* Set the Key */
2398 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
2399 {
2400 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2401 }
2402
2403 /* Get tick */
2404 tickstart = HAL_GetTick();
2405
2406 while (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEYVALID) == 0x0U)
2407 {
2408 /* Check for the Timeout */
2409 if (Timeout != HAL_MAX_DELAY)
2410 {
2411 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
2412 {
2413 /* Disable the CRYP peripheral clock */
2414 __HAL_CRYP_DISABLE(hcryp);
2415
2416 /* Change state */
2417 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2418 hcryp->State = HAL_CRYP_STATE_READY;
2419
2420 /* Process unlocked */
2421 __HAL_UNLOCK(hcryp);
2422 return HAL_ERROR;
2423 }
2424 }
2425 }
2426
2427 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2428 if (IS_CRYP_INSTANCE(hcryp->Instance))
2429 {
2430 if (hcryp->Init.KeyMode == CRYP_KEYMODE_SHARED)
2431 {
2432 /* As KEYVALID is set, the key share target peripheral is initialized with a valid, shared key.
2433 The application can proceed with the processing of data, setting KMOD[1:0]to 00 */
2434 CLEAR_BIT(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_KMOD);
2435 }
2436 }
2437 #endif /* USE_HAL_CRYP_ONLY */
2438
2439 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2440 {
2441 /* Set the Initialization Vector*/
2442 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2443 if (IS_CRYP_INSTANCE(hcryp->Instance))
2444 {
2445 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2446 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2447 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2448 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2449 }
2450 #endif /* USE_HAL_CRYP_ONLY */
2451 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2452 if (IS_SAES_INSTANCE(hcryp->Instance))
2453 {
2454 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2455 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2456 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2457 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2458 }
2459 #endif /* USE_HAL_SAES_ONLY */
2460 }
2461 } /* if (DoKeyIVConfig == 1U) */
2462
2463 /* Set the phase */
2464 hcryp->Phase = CRYP_PHASE_PROCESS;
2465
2466 /* Enable CRYP */
2467 __HAL_CRYP_ENABLE(hcryp);
2468 /*Temporary CrypOutCount Value */
2469 outcount = hcryp->CrypOutCount;
2470
2471 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2472 {
2473 /* Write plain Ddta and get cipher data */
2474 CRYP_AES_ProcessData(hcryp, Timeout);
2475 /*Temporary CrypOutCount Value */
2476 outcount = hcryp->CrypOutCount;
2477 }
2478
2479 /* Disable CRYP */
2480 __HAL_CRYP_DISABLE(hcryp);
2481
2482 /* Change the CRYP state */
2483 hcryp->State = HAL_CRYP_STATE_READY;
2484
2485 /* Return function status */
2486 return HAL_OK;
2487 }
2488
2489 /**
2490 * @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2491 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2492 * the configuration information for CRYP module
2493 * @retval HAL status
2494 */
CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef * hcryp)2495 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
2496 {
2497 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2498 uint32_t tickstart;
2499
2500 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2501 {
2502 if (hcryp->KeyIVConfig == 1U)
2503 {
2504 /* If the Key and IV configuration has to be done only once
2505 and if it has already been done, skip it */
2506 DoKeyIVConfig = 0U;
2507 }
2508 else
2509 {
2510 /* If the Key and IV configuration has to be done only once
2511 and if it has not been done already, do it and set KeyIVConfig
2512 to keep track it won't have to be done again next time */
2513 hcryp->KeyIVConfig = 1U;
2514 }
2515 }
2516
2517 if (DoKeyIVConfig == 1U)
2518 {
2519 /* Set the Key */
2520 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
2521 {
2522 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2523 }
2524
2525 /* Get tick */
2526 tickstart = HAL_GetTick();
2527
2528 while (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEYVALID) == 0x0U)
2529 {
2530 /* Check for the Timeout */
2531 if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT)
2532 {
2533 /* Disable the CRYP peripheral clock */
2534 __HAL_CRYP_DISABLE(hcryp);
2535
2536 /* Change state */
2537 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2538 hcryp->State = HAL_CRYP_STATE_READY;
2539
2540 /* Process unlocked */
2541 __HAL_UNLOCK(hcryp);
2542 return HAL_ERROR;
2543 }
2544 }
2545
2546 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2547 if (IS_CRYP_INSTANCE(hcryp->Instance))
2548 {
2549 if (hcryp->Init.KeyMode == CRYP_KEYMODE_SHARED)
2550 {
2551 /* As KEYVALID is set, the key share target peripheral is initialized with a valid, shared key.
2552 The application can proceed with the processing of data, setting KMOD[1:0]to 00 */
2553 CLEAR_BIT(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_KMOD);
2554 }
2555 }
2556 #endif /* USE_HAL_CRYP_ONLY */
2557
2558 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2559 {
2560 /* Set the Initialization Vector*/
2561 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2562 if (IS_CRYP_INSTANCE(hcryp->Instance))
2563 {
2564 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2565 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2566 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2567 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2568 }
2569 #endif /* USE_HAL_CRYP_ONLY */
2570 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2571 if (IS_SAES_INSTANCE(hcryp->Instance))
2572 {
2573 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2574 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2575 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2576 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2577 }
2578 #endif /* USE_HAL_SAES_ONLY */
2579 }
2580 } /* if (DoKeyIVConfig == 1U) */
2581
2582 /* Set the phase */
2583 hcryp->Phase = CRYP_PHASE_PROCESS;
2584
2585 if (hcryp->Size != 0U)
2586 {
2587 /* Enable CRYP */
2588 __HAL_CRYP_ENABLE(hcryp);
2589
2590 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2591 if (IS_SAES_INSTANCE(hcryp->Instance))
2592 {
2593 /* Write the input block in the IN FIFO */
2594 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2595 hcryp->CrypInCount++;
2596 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2597 hcryp->CrypInCount++;
2598 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2599 hcryp->CrypInCount++;
2600 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2601 hcryp->CrypInCount++;
2602 }
2603 #endif /* USE_HAL_SAES_ONLY */
2604
2605 /* Enable interrupts */
2606 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2607 if (IS_CRYP_INSTANCE(hcryp->Instance))
2608 {
2609 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2610 }
2611 #endif /* USE_HAL_CRYP_ONLY */
2612 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2613 if (IS_SAES_INSTANCE(hcryp->Instance))
2614 {
2615 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE | CRYP_IT_RNGEIE);
2616 }
2617 #endif /* USE_HAL_SAES_ONLY */
2618 }
2619 else
2620 {
2621 /* Change the CRYP state */
2622 hcryp->State = HAL_CRYP_STATE_READY;
2623
2624 /* Process unlocked */
2625 __HAL_UNLOCK(hcryp);
2626 }
2627
2628 /* Return function status */
2629 return HAL_OK;
2630 }
2631
2632 /**
2633 * @brief Decryption in ECB/CBC & CTR mode with AES Standard
2634 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
2635 * @param Timeout: Specify Timeout value
2636 * @retval HAL status
2637 */
CRYP_AES_Decrypt(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2638 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2639 {
2640 uint16_t outcount; /* Temporary CrypOutCount Value */
2641 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2642
2643 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2644 {
2645 if (hcryp->KeyIVConfig == 1U)
2646 {
2647 /* If the Key and IV configuration has to be done only once
2648 and if it has already been done, skip it */
2649 DoKeyIVConfig = 0U;
2650 }
2651 else
2652 {
2653 /* If the Key and IV configuration has to be done only once
2654 and if it has not been done already, do it and set KeyIVConfig
2655 to keep track it won't have to be done again next time */
2656 hcryp->KeyIVConfig = 1U;
2657 }
2658 }
2659
2660 if (DoKeyIVConfig == 1U)
2661 {
2662 /* Key preparation for ECB/CBC */
2663 if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/
2664 {
2665 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2666 if (IS_CRYP_INSTANCE(hcryp->Instance))
2667 {
2668 /* change ALGOMODE to key preparation for decryption*/
2669 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, CRYP_AES_KEY);
2670
2671 /* Set the Key */
2672 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
2673 {
2674 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
2675 {
2676 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2677 }
2678 }
2679
2680 /* Enable CRYP */
2681 __HAL_CRYP_ENABLE(hcryp);
2682
2683 /* Wait for BUSY flag go to 0 */
2684 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
2685 {
2686 /* Disable the CRYP peripheral clock */
2687 __HAL_CRYP_DISABLE(hcryp);
2688
2689 /* Change state */
2690 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2691 hcryp->State = HAL_CRYP_STATE_READY;
2692
2693 /* Process unlocked */
2694 __HAL_UNLOCK(hcryp);
2695 return HAL_ERROR;
2696 }
2697 /* Turn back to ALGOMODE of the configuration */
2698 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2699 }
2700 #endif /* USE_HAL_CRYP_ONLY */
2701 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2702 if (IS_SAES_INSTANCE(hcryp->Instance))
2703 {
2704 /* When KMOD[1:0] = 01 (wrapped key) or KMOD[1:0] = 01 (shared key)
2705 and MODE[1:0] = 10 (decryption), then a read access to
2706 SAES_DOUTR register triggers a read error (RDERR). So, clear KMOD for the upcoming deciphering */
2707 if (((((SAES_TypeDef *)(hcryp->Instance))->CR) & (CRYP_KEYMODE_WRAPPED | CRYP_KEYMODE_SHARED)) != 0U)
2708 {
2709 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_NORMAL);
2710 }
2711 /* key preparation for decryption, operating mode 2*/
2712 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_KEY_DERIVATION);
2713
2714 /* we should re-write Key, in the case where we change key after first operation*/
2715 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
2716 {
2717 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
2718 {
2719 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2720 }
2721 }
2722
2723 /* Enable SAES */
2724 __HAL_CRYP_ENABLE(hcryp);
2725
2726 /* Wait for CCF flag to be raised */
2727 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
2728 {
2729 /* Disable the CRYP peripheral clock */
2730 __HAL_CRYP_DISABLE(hcryp);
2731
2732 /* Change state & update error code */
2733 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2734 hcryp->State = HAL_CRYP_STATE_READY;
2735
2736 /* Process unlocked */
2737 __HAL_UNLOCK(hcryp);
2738 return HAL_ERROR;
2739 }
2740 /* Clear CCF Flag */
2741 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
2742
2743 /* End of Key preparation for ECB/CBC */
2744 /* Return to decryption operating mode(Mode 3)*/
2745 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
2746 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
2747 #endif /* USE_HAL_SAES_ONLY */
2748 }
2749 else /*Algorithm CTR */
2750 {
2751 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2752 if (IS_CRYP_INSTANCE(hcryp->Instance))
2753 {
2754 /* Set the Key */
2755 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
2756 {
2757 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
2758 {
2759 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2760 }
2761 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
2762 {
2763 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
2764 }
2765 }
2766 }
2767 #endif /* USE_HAL_CRYP_ONLY */
2768 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2769 if (IS_SAES_INSTANCE(hcryp->Instance))
2770 {
2771 /* Set the Key */
2772 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2773 }
2774 #endif /* USE_HAL_SAES_ONLY */
2775 }
2776
2777 /* Set IV */
2778 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2779 {
2780 /* Set the Initialization Vector*/
2781 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2782 if (IS_CRYP_INSTANCE(hcryp->Instance))
2783 {
2784 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2785 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2786 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2787 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2788 }
2789 #endif /* USE_HAL_CRYP_ONLY */
2790 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2791 if (IS_SAES_INSTANCE(hcryp->Instance))
2792 {
2793 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2794 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2795 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2796 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2797 }
2798 #endif /* USE_HAL_SAES_ONLY */
2799 }
2800 } /* if (DoKeyIVConfig == 1U) */
2801
2802 /* Set the phase */
2803 hcryp->Phase = CRYP_PHASE_PROCESS;
2804
2805 /* Enable CRYP */
2806 __HAL_CRYP_ENABLE(hcryp);
2807
2808 /*Temporary CrypOutCount Value */
2809 outcount = hcryp->CrypOutCount;
2810
2811 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2812 {
2813 /* Write plain data and get cipher data */
2814 CRYP_AES_ProcessData(hcryp, Timeout);
2815 /*Temporary CrypOutCount Value */
2816 outcount = hcryp->CrypOutCount;
2817 }
2818
2819 /* Disable CRYP */
2820 __HAL_CRYP_DISABLE(hcryp);
2821
2822 /* Change the CRYP state */
2823 hcryp->State = HAL_CRYP_STATE_READY;
2824
2825 /* Return function status */
2826 return HAL_OK;
2827 }
2828 /**
2829 * @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2830 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2831 * the configuration information for CRYP module
2832 * @retval HAL status
2833 */
CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef * hcryp)2834 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
2835 {
2836 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2837 uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
2838
2839 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2840 {
2841 if (hcryp->KeyIVConfig == 1U)
2842 {
2843 /* If the Key and IV configuration has to be done only once
2844 and if it has already been done, skip it */
2845 DoKeyIVConfig = 0U;
2846 }
2847 else
2848 {
2849 /* If the Key and IV configuration has to be done only once
2850 and if it has not been done already, do it and set KeyIVConfig
2851 to keep track it won't have to be done again next time */
2852 hcryp->KeyIVConfig = 1U;
2853 }
2854 }
2855
2856 if (DoKeyIVConfig == 1U)
2857 {
2858 /* Key preparation for ECB/CBC */
2859 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2860 {
2861 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2862 if (IS_CRYP_INSTANCE(hcryp->Instance))
2863 {
2864 /* change ALGOMODE to key preparation for decryption*/
2865 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, CRYP_AES_KEY);
2866
2867 /* Set the Key */
2868 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
2869 {
2870 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
2871 {
2872 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2873 }
2874 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
2875 {
2876 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
2877 }
2878 }
2879
2880 /* Enable CRYP */
2881 __HAL_CRYP_ENABLE(hcryp);
2882
2883 /* Wait for BUSY flag go to 0 */
2884 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
2885 {
2886 /* Disable the CRYP peripheral clock */
2887 __HAL_CRYP_DISABLE(hcryp);
2888
2889 /* Change state */
2890 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2891 hcryp->State = HAL_CRYP_STATE_READY;
2892
2893 /* Process unlocked */
2894 __HAL_UNLOCK(hcryp);
2895 return HAL_ERROR;
2896 }
2897
2898 /* Turn back to ALGOMODE of the configuration */
2899 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2900 }
2901 #endif /* USE_HAL_CRYP_ONLY */
2902 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2903 if (IS_SAES_INSTANCE(hcryp->Instance))
2904 {
2905 /* When KMOD[1:0] = 01 (wrapped key) or KMOD[1:0] = 01 (shared key)
2906 and MODE[1:0] = 10 (decryption), then a read access to
2907 SAES_DOUTR register triggers a read error (RDERR). So, clear KMOD for the upcoming deciphering */
2908 if (((((SAES_TypeDef *)(hcryp->Instance))->CR) & (CRYP_KEYMODE_WRAPPED | CRYP_KEYMODE_SHARED)) != 0U)
2909 {
2910 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_NORMAL);
2911 }
2912 /* key preparation for decryption, operating mode 2*/
2913 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_KEY_DERIVATION);
2914
2915 /* we should re-write Key, in the case where we change key after first operation*/
2916 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
2917 {
2918 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
2919 {
2920 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2921 }
2922 }
2923
2924 /* Enable SAES */
2925 __HAL_CRYP_ENABLE(hcryp);
2926
2927 /* Wait for CCF flag to be raised */
2928 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
2929 {
2930 /* Disable the CRYP peripheral clock */
2931 __HAL_CRYP_DISABLE(hcryp);
2932
2933 /* Change state & update error code */
2934 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2935 hcryp->State = HAL_CRYP_STATE_READY;
2936
2937 /* Process unlocked */
2938 __HAL_UNLOCK(hcryp);
2939 return HAL_ERROR;
2940 }
2941 /* Clear CCF Flag */
2942 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
2943
2944 /* End of Key preparation for ECB/CBC */
2945 /* Return to decryption operating mode(Mode 3)*/
2946 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
2947 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
2948 #endif /* USE_HAL_SAES_ONLY */
2949 }
2950 else /*Algorithm CTR */
2951 {
2952 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2953 if (IS_CRYP_INSTANCE(hcryp->Instance))
2954 {
2955 /* Set the Key */
2956 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
2957 {
2958 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
2959 {
2960 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2961 }
2962 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
2963 {
2964 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
2965 }
2966 }
2967 }
2968 #endif /* USE_HAL_CRYP_ONLY */
2969 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2970 if (IS_SAES_INSTANCE(hcryp->Instance))
2971 {
2972 /* Set the Key */
2973 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2974 }
2975 #endif /* USE_HAL_SAES_ONLY */
2976 } /* if (hcryp->Init.Algorithm != CRYP_AES_CTR) */
2977
2978 /* Set IV */
2979 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2980 {
2981 /* Set the Initialization Vector*/
2982 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
2983 if (IS_CRYP_INSTANCE(hcryp->Instance))
2984 {
2985 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2986 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2987 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2988 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2989 }
2990 #endif /* USE_HAL_CRYP_ONLY */
2991 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
2992 if (IS_SAES_INSTANCE(hcryp->Instance))
2993 {
2994 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2995 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2996 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2997 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2998 }
2999 #endif /* USE_HAL_SAES_ONLY */
3000 }
3001 } /* if (DoKeyIVConfig == 1U) */
3002
3003 /* Set the phase */
3004 hcryp->Phase = CRYP_PHASE_PROCESS;
3005 if (hcryp->Size != 0U)
3006 {
3007 /* Enable CRYP */
3008 __HAL_CRYP_ENABLE(hcryp);
3009
3010 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3011 if (IS_SAES_INSTANCE(hcryp->Instance))
3012 {
3013 /* Write the input block in the IN FIFO */
3014 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3015 hcryp->CrypInCount++;
3016 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3017 hcryp->CrypInCount++;
3018 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3019 hcryp->CrypInCount++;
3020 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3021 hcryp->CrypInCount++;
3022 }
3023 #endif /* USE_HAL_SAES_ONLY */
3024
3025 /* Enable interrupts */
3026 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3027 if (IS_CRYP_INSTANCE(hcryp->Instance))
3028 {
3029 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
3030 }
3031 #endif /* USE_HAL_CRYP_ONLY */
3032 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3033 if (IS_SAES_INSTANCE(hcryp->Instance))
3034 {
3035 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE | CRYP_IT_RNGEIE);
3036 }
3037 #endif /* USE_HAL_SAES_ONLY */
3038 }
3039 else
3040 {
3041 /* Process locked */
3042 __HAL_UNLOCK(hcryp);
3043
3044 /* Change the CRYP state */
3045 hcryp->State = HAL_CRYP_STATE_READY;
3046 }
3047 /* Return function status */
3048 return HAL_OK;
3049 }
3050
3051 /**
3052 * @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
3053 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3054 * the configuration information for CRYP module
3055 * @retval HAL status
3056 */
CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef * hcryp)3057 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
3058 {
3059 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3060 uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
3061
3062 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3063 {
3064 if (hcryp->KeyIVConfig == 1U)
3065 {
3066 /* If the Key and IV configuration has to be done only once
3067 and if it has already been done, skip it */
3068 DoKeyIVConfig = 0U;
3069 }
3070 else
3071 {
3072 /* If the Key and IV configuration has to be done only once
3073 and if it has not been done already, do it and set KeyIVConfig
3074 to keep track it won't have to be done again next time */
3075 hcryp->KeyIVConfig = 1U;
3076 }
3077 }
3078
3079 if (DoKeyIVConfig == 1U)
3080 {
3081 if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/
3082 {
3083 /* Key preparation for ECB/CBC */
3084 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3085 if (IS_CRYP_INSTANCE(hcryp->Instance))
3086 {
3087 /* change ALGOMODE to key preparation for decryption*/
3088 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, CRYP_AES_KEY);
3089
3090 /* Set the Key */
3091 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
3092 {
3093 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
3094 {
3095 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3096 }
3097 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
3098 {
3099 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
3100 }
3101 }
3102
3103 /* Enable CRYP */
3104 __HAL_CRYP_ENABLE(hcryp);
3105
3106 /* Wait for BUSY flag go to 0 */
3107 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
3108 {
3109 /* Disable the CRYP peripheral clock */
3110 __HAL_CRYP_DISABLE(hcryp);
3111
3112 /* Change state */
3113 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3114 hcryp->State = HAL_CRYP_STATE_READY;
3115
3116 /* Process unlocked */
3117 __HAL_UNLOCK(hcryp);
3118 return HAL_ERROR;
3119 }
3120 /* Turn back to ALGOMODE of the configuration */
3121 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
3122 }
3123 #endif /* USE_HAL_CRYP_ONLY */
3124 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3125 if (IS_SAES_INSTANCE(hcryp->Instance))
3126 {
3127 /* When KMOD[1:0] = 01 (wrapped key) or KMOD[1:0] = 01 (shared key)
3128 and MODE[1:0] = 10 (decryption), then a read access to
3129 SAES_DOUTR register triggers a read error (RDERR). So, clear KMOD for the upcoming deciphering */
3130 if (((((SAES_TypeDef *)(hcryp->Instance))->CR) & (CRYP_KEYMODE_WRAPPED | CRYP_KEYMODE_SHARED)) != 0U)
3131 {
3132 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_KMOD, CRYP_KEYMODE_NORMAL);
3133 }
3134 /* key preparation for decryption, operating mode 2*/
3135 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_KEY_DERIVATION);
3136
3137 /* we should re-write Key, in the case where we change key after first operation*/
3138 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
3139 {
3140 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
3141 {
3142 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3143 }
3144 }
3145
3146 /* Enable SAES */
3147 __HAL_CRYP_ENABLE(hcryp);
3148
3149 /* Wait for CCF flag to be raised */
3150 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3151 {
3152 /* Disable the CRYP peripheral clock */
3153 __HAL_CRYP_DISABLE(hcryp);
3154
3155 /* Change state & update error code */
3156 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3157 hcryp->State = HAL_CRYP_STATE_READY;
3158
3159 /* Process unlocked */
3160 __HAL_UNLOCK(hcryp);
3161 return HAL_ERROR;
3162 }
3163 /* Clear CCF Flag */
3164 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
3165
3166 /* End of Key preparation for ECB/CBC */
3167 /* Return to decryption operating mode(Mode 3) */
3168 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_MODE, CRYP_MODE_DECRYPT);
3169
3170 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
3171 #endif /* USE_HAL_SAES_ONLY */
3172 }
3173 else /*Algorithm CTR */
3174 {
3175 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3176 if (IS_CRYP_INSTANCE(hcryp->Instance))
3177 {
3178 /* Set the Key */
3179 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
3180 {
3181 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
3182 {
3183 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3184 }
3185 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
3186 {
3187 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
3188 }
3189 }
3190 }
3191 #endif /* USE_HAL_CRYP_ONLY */
3192 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3193 if (IS_SAES_INSTANCE(hcryp->Instance))
3194 {
3195 /* Set the Key */
3196 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3197 }
3198 #endif /* USE_HAL_SAES_ONLY */
3199 }
3200
3201 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
3202 {
3203 /* Set the Initialization Vector*/
3204 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3205 if (IS_CRYP_INSTANCE(hcryp->Instance))
3206 {
3207 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3208 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
3209 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
3210 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
3211 }
3212 #endif /* USE_HAL_CRYP_ONLY */
3213 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3214 if (IS_SAES_INSTANCE(hcryp->Instance))
3215 {
3216 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3217 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
3218 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
3219 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
3220 }
3221 #endif /* IS_SAES_INSTANCE */
3222 }
3223 } /* if (DoKeyIVConfig == 1U) */
3224
3225 /* Set the phase */
3226 hcryp->Phase = CRYP_PHASE_PROCESS;
3227
3228 if (hcryp->Size != 0U)
3229 {
3230 /* Start DMA process transfer for AES */
3231 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size, (uint32_t)(hcryp->pCrypOutBuffPtr));
3232 }
3233 else
3234 {
3235 /* Process unlocked */
3236 __HAL_UNLOCK(hcryp);
3237
3238 /* Change the CRYP state */
3239 hcryp->State = HAL_CRYP_STATE_READY;
3240 }
3241
3242 /* Return function status */
3243 return HAL_OK;
3244 }
3245
3246 /**
3247 * @brief DMA CRYP input data process complete callback.
3248 * @param hdma: DMA handle
3249 * @retval None
3250 */
CRYP_DMAInCplt(DMA_HandleTypeDef * hdma)3251 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
3252 {
3253 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3254
3255 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3256 if (IS_CRYP_INSTANCE(hcryp->Instance))
3257 {
3258 /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
3259 in the DMACR register */
3260 ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
3261 }
3262 #endif /* USE_HAL_CRYP_ONLY */
3263 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3264 if (IS_SAES_INSTANCE(hcryp->Instance))
3265 {
3266 /* Disable the DMA transfer for input FIFO request by resetting the DMAINEN bit
3267 in the CR register */
3268 ((SAES_TypeDef *)(hcryp->Instance))->CR &= (uint32_t)(~SAES_CR_DMAINEN);
3269 }
3270 #endif /* USE_HAL_SAES_ONLY */
3271
3272 /* Call input data transfer complete callback */
3273 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3274 /*Call registered Input complete callback*/
3275 hcryp->InCpltCallback(hcryp);
3276 #else
3277 /*Call legacy Input complete callback*/
3278 HAL_CRYP_InCpltCallback(hcryp);
3279 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3280 }
3281
3282
3283 /**
3284 * @brief DMA CRYP output data process complete callback.
3285 * @param hdma: DMA handle
3286 * @retval None
3287 */
CRYP_DMAOutCplt(DMA_HandleTypeDef * hdma)3288 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
3289 {
3290 uint32_t count;
3291 uint32_t npblb;
3292 uint32_t lastwordsize;
3293 uint32_t temp; /* Temporary CrypOutBuff */
3294 uint32_t mode;
3295
3296 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3297
3298
3299 /* Disable the DMA transfer for output FIFO */
3300 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3301 if (IS_CRYP_INSTANCE(hcryp->Instance))
3302 {
3303 ((CRYP_TypeDef *)(hcryp->Instance))->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
3304 }
3305 #endif /* USE_HAL_CRYP_ONLY */
3306 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3307 if (IS_SAES_INSTANCE(hcryp->Instance))
3308 {
3309 ((SAES_TypeDef *)(hcryp->Instance))->CR &= (uint32_t)(~SAES_CR_DMAOUTEN);
3310
3311 /* Disable the DMA transfer for output FIFO request by resetting
3312 the DOEN bit in the DMACR register */
3313 CLEAR_BIT(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_DMAOUTEN);
3314 }
3315 #endif /* USE_HAL_SAES_ONLY */
3316
3317 /* Last block transfer in case of GCM or CCM with Size not %16 */
3318 /* Applicable to CRYP peripheral only */
3319 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3320 if (IS_CRYP_INSTANCE(hcryp->Instance))
3321 {
3322 if (((hcryp->Size) % 16U) != 0U)
3323 {
3324 /* set CrypInCount and CrypOutCount to exact number of word already computed via DMA */
3325 hcryp->CrypInCount = (hcryp->Size / 16U) * 4U;
3326 hcryp->CrypOutCount = hcryp->CrypInCount;
3327
3328 /* Compute the number of padding bytes in last block of payload */
3329 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
3330
3331 /* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */
3332 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
3333 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
3334 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
3335 {
3336 /* Disable the CRYP */
3337 __HAL_CRYP_DISABLE(hcryp);
3338
3339 /* Specify the number of non-valid bytes using NPBLB register*/
3340 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
3341
3342 /* Enable CRYP to start the final phase */
3343 __HAL_CRYP_ENABLE(hcryp);
3344 }
3345
3346 /* Number of valid words (lastwordsize) in last block */
3347 if ((npblb % 4U) == 0U)
3348 {
3349 lastwordsize = (16U - npblb) / 4U;
3350 }
3351 else
3352 {
3353 lastwordsize = ((16U - npblb) / 4U) + 1U;
3354 }
3355 /* Write the last input block in the IN FIFO */
3356 for (count = 0U; count < lastwordsize; count ++)
3357 {
3358 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3359 hcryp->CrypInCount++;
3360 }
3361 /* Pad the data with zeros to have a complete block */
3362 while (count < 4U)
3363 {
3364 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
3365 count++;
3366 }
3367 /* Wait for OFNE flag to be raised */
3368 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
3369 do
3370 {
3371 count-- ;
3372 if (count == 0U)
3373 {
3374 /* Disable the CRYP peripheral clock */
3375 __HAL_CRYP_DISABLE(hcryp);
3376
3377 /* Change state */
3378 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3379 hcryp->State = HAL_CRYP_STATE_READY;
3380
3381 /* Process unlocked */
3382 __HAL_UNLOCK(hcryp);
3383 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3384 /*Call registered error callback*/
3385 hcryp->ErrorCallback(hcryp);
3386 #else
3387 /*Call legacy error callback*/
3388 HAL_CRYP_ErrorCallback(hcryp);
3389 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3390 }
3391 } while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_OFNE));
3392
3393 /*Read the output block from the output FIFO */
3394 for (count = 0U; count < 4U; count++)
3395 {
3396 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
3397 temporary buffer */
3398 temp = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
3399
3400 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
3401 hcryp->CrypOutCount++;
3402 }
3403 } /*End of last block transfer in case of GCM or CCM */
3404 }
3405 #endif /* USE_HAL_CRYP_ONLY */
3406 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3407 if (IS_SAES_INSTANCE(hcryp->Instance))
3408 {
3409 temp = 0;
3410 /* Last block transfer in case of GCM or CCM with Size not %16*/
3411 if (((hcryp->Size) % 16U) != 0U)
3412 {
3413 /* set CrypInCount and CrypOutCount to exact number of words already computed via DMA */
3414 hcryp->CrypInCount = (hcryp->Size / 16U) * 4U;
3415 hcryp->CrypOutCount = hcryp->CrypInCount;
3416
3417 /* Compute the number of padding bytes in last block of payload */
3418 npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
3419
3420 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
3421 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
3422 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
3423 {
3424 /* Specify the number of non-valid bytes using NPBLB register*/
3425 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
3426 }
3427
3428 /* Number of valid words (lastwordsize) in last block */
3429 if ((npblb % 4U) == 0U)
3430 {
3431 lastwordsize = (16U - npblb) / 4U;
3432 }
3433 else
3434 {
3435 lastwordsize = ((16U - npblb) / 4U) + 1U;
3436 }
3437
3438 /* Last block optionally pad the data with zeros*/
3439 for (count = 0U; count < lastwordsize; count++)
3440 {
3441 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3442 hcryp->CrypInCount++;
3443 }
3444 while (count < 4U)
3445 {
3446 /* Pad the data with zeros to have a complete block */
3447 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
3448 count++;
3449 }
3450
3451 /* Clear CCF flag */
3452 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
3453
3454 /*Read the output block from the output FIFO */
3455 for (count = 0U; count < 4U; count++)
3456 {
3457 /* Read the output block from the output FIFO and put them in temporary buffer
3458 then get CrypOutBuff from temporary buffer */
3459 temp = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
3460 }
3461
3462 count = 0U;
3463 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U))
3464 {
3465 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
3466 hcryp->CrypOutCount++;
3467 count++;
3468 }
3469 }
3470 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
3471 #endif /* USE_HAL_SAES_ONLY */
3472
3473 if (((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
3474 && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
3475 {
3476 /* Disable CRYP (not allowed in GCM) */
3477 __HAL_CRYP_DISABLE(hcryp);
3478 }
3479
3480 /* Change the CRYP state to ready */
3481 hcryp->State = HAL_CRYP_STATE_READY;
3482
3483 /* Process unlocked */
3484 __HAL_UNLOCK(hcryp);
3485
3486 /* Call output data transfer complete callback */
3487 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3488 /*Call registered Output complete callback*/
3489 hcryp->OutCpltCallback(hcryp);
3490 #else
3491 /*Call legacy Output complete callback*/
3492 HAL_CRYP_OutCpltCallback(hcryp);
3493 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3494 }
3495
3496 /**
3497 * @brief DMA CRYP communication error callback.
3498 * @param hdma: DMA handle
3499 * @retval None
3500 */
CRYP_DMAError(DMA_HandleTypeDef * hdma)3501 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
3502 {
3503 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3504
3505 /* Change the CRYP peripheral state */
3506 hcryp->State = HAL_CRYP_STATE_READY;
3507
3508 /* DMA error code field */
3509 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3510
3511 /* Call error callback */
3512 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3513 /*Call registered error callback*/
3514 hcryp->ErrorCallback(hcryp);
3515 #else
3516 /*Call legacy error callback*/
3517 HAL_CRYP_ErrorCallback(hcryp);
3518 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3519 }
3520
3521 /**
3522 * @brief Set the DMA configuration and start the DMA transfer
3523 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3524 * the configuration information for CRYP module
3525 * @param inputaddr: address of the input buffer
3526 * @param Size: size of the input buffer, must be a multiple of 16.
3527 * @param outputaddr: address of the output buffer
3528 * @retval None
3529 */
CRYP_SetDMAConfig(CRYP_HandleTypeDef * hcryp,uint32_t inputaddr,uint16_t Size,uint32_t outputaddr)3530 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
3531 {
3532 HAL_StatusTypeDef status;
3533 uint32_t peripheral_in_address = 0U;
3534 uint32_t peripheral_out_address = 0U;
3535
3536 /* Set the CRYP DMA transfer complete callback */
3537 hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
3538
3539 /* Set the DMA input error callback */
3540 hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
3541
3542 /* Set the CRYP DMA transfer complete callback */
3543 hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
3544
3545 /* Set the DMA output error callback */
3546 hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
3547
3548 /* Enable CRYP */
3549 __HAL_CRYP_ENABLE(hcryp);
3550
3551 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3552 if (IS_CRYP_INSTANCE(hcryp->Instance))
3553 {
3554 peripheral_in_address = (uint32_t) &((CRYP_TypeDef *)(hcryp->Instance))->DIN;
3555 peripheral_out_address = (uint32_t) &((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
3556 }
3557 #endif /* USE_HAL_CRYP_ONLY */
3558 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3559 if (IS_SAES_INSTANCE(hcryp->Instance))
3560 {
3561 peripheral_in_address = (uint32_t) &((SAES_TypeDef *)(hcryp->Instance))->DINR;
3562 peripheral_out_address = (uint32_t) &((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
3563 }
3564 #endif /* USE_HAL_SAES_ONLY */
3565
3566 /* Enable the DMA input channel */
3567 if ((hcryp->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3568 {
3569 if ((hcryp->hdmain->LinkedListQueue != NULL) && (hcryp->hdmain->LinkedListQueue->Head != NULL))
3570 {
3571 /* Enable the DMA channel */
3572 hcryp->hdmain->LinkedListQueue->Head->\
3573 LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size; /* Set DMA data size */
3574 hcryp->hdmain->LinkedListQueue->Head->\
3575 LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = inputaddr; /* Set DMA source address */
3576 hcryp->hdmain->LinkedListQueue->Head->\
3577 LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = peripheral_in_address; /* Set DMA destination address */
3578
3579 status = HAL_DMAEx_List_Start_IT(hcryp->hdmain);
3580 }
3581 else
3582 {
3583 /* Return error status */
3584 status = HAL_ERROR;
3585 }
3586 }
3587 else
3588 {
3589 status = HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, peripheral_in_address, Size);
3590 }
3591
3592 if (status != HAL_OK)
3593 {
3594 /* DMA error code field */
3595 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3596
3597 /* Call error callback */
3598 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3599 /*Call registered error callback*/
3600 hcryp->ErrorCallback(hcryp);
3601 #else
3602 /*Call legacy error callback*/
3603 HAL_CRYP_ErrorCallback(hcryp);
3604 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3605 }
3606
3607 /* Enable the DMA output channel */
3608 if ((hcryp->hdmaout->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3609 {
3610 if ((hcryp->hdmaout->LinkedListQueue != NULL) && (hcryp->hdmaout->LinkedListQueue->Head != NULL))
3611 {
3612 /* Enable the DMA channel */
3613 hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = \
3614 Size; /* Set DMA data size */
3615 hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
3616 peripheral_out_address; /* Set DMA source address */
3617 hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = \
3618 outputaddr; /* Set DMA destination address */
3619
3620 status = HAL_DMAEx_List_Start_IT(hcryp->hdmaout);
3621 }
3622 else
3623 {
3624 /* Return error status */
3625 status = HAL_ERROR;
3626 }
3627 }
3628 else
3629 {
3630 status = HAL_DMA_Start_IT(hcryp->hdmaout, peripheral_out_address, outputaddr, Size);
3631 }
3632
3633 if (status != HAL_OK)
3634 {
3635 /* DMA error code field */
3636 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3637
3638 /* Call error callback */
3639 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3640 /*Call registered error callback*/
3641 hcryp->ErrorCallback(hcryp);
3642 #else
3643 /*Call legacy error callback*/
3644 HAL_CRYP_ErrorCallback(hcryp);
3645 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3646 }
3647
3648 /* Enable In/Out DMA request */
3649 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3650 if (IS_CRYP_INSTANCE(hcryp->Instance))
3651 {
3652 ((CRYP_TypeDef *)(hcryp->Instance))->DMACR = (CRYP_DMACR_DOEN | CRYP_DMACR_DIEN);
3653 }
3654 #endif /* USE_HAL_CRYP_ONLY */
3655 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3656 if (IS_SAES_INSTANCE(hcryp->Instance))
3657 {
3658 ((SAES_TypeDef *)(hcryp->Instance))->CR |= (SAES_CR_DMAINEN | SAES_CR_DMAOUTEN);
3659 }
3660 #endif /* USE_HAL_SAES_ONLY */
3661 }
3662
3663 /**
3664 * @brief Process Data: Write Input data in polling mode and used in AES functions.
3665 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3666 * the configuration information for CRYP module
3667 * @param Timeout: Specify Timeout value
3668 * @retval None
3669 */
CRYP_AES_ProcessData(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)3670 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3671 {
3672
3673 uint32_t temp[4]; /* Temporary CrypOutBuff */
3674 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3675 uint16_t incount; /* Temporary CrypInCount Value */
3676 uint16_t outcount; /* Temporary CrypOutCount Value */
3677 #endif /* USE_HAL_CRYP_ONLY */
3678 uint32_t i;
3679
3680 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3681 if (IS_CRYP_INSTANCE(hcryp->Instance))
3682 {
3683 /*Temporary CrypOutCount Value */
3684 incount = hcryp->CrypInCount;
3685
3686 if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < ((hcryp->Size) / 4U)))
3687 {
3688 /* Write the input block in the IN FIFO */
3689 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3690 hcryp->CrypInCount++;
3691 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3692 hcryp->CrypInCount++;
3693 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3694 hcryp->CrypInCount++;
3695 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3696 hcryp->CrypInCount++;
3697 }
3698
3699 /* Wait for OFNE flag to be raised */
3700 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
3701 {
3702 /* Disable the CRYP peripheral clock */
3703 __HAL_CRYP_DISABLE(hcryp);
3704
3705 /* Change state & update error code */
3706 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3707 hcryp->State = HAL_CRYP_STATE_READY;
3708
3709 /* Process unlocked */
3710 __HAL_UNLOCK(hcryp);
3711 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3712 /*Call registered error callback*/
3713 hcryp->ErrorCallback(hcryp);
3714 #else
3715 /*Call legacy error callback*/
3716 HAL_CRYP_ErrorCallback(hcryp);
3717 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3718 }
3719 /*Temporary CrypOutCount Value */
3720 outcount = hcryp->CrypOutCount;
3721
3722 if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < ((hcryp->Size) / 4U)))
3723 {
3724 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from
3725 temporary buffer */
3726 for (i = 0U; i < 4U; i++)
3727 {
3728 temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
3729 }
3730 i = 0U;
3731 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3732 {
3733 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3734 hcryp->CrypOutCount++;
3735 i++;
3736 }
3737 }
3738 }
3739 #endif /* USE_HAL_CRYP_ONLY */
3740 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3741 if (IS_SAES_INSTANCE(hcryp->Instance))
3742 {
3743 /* Write the input block in the IN FIFO */
3744 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3745 hcryp->CrypInCount++;
3746 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3747 hcryp->CrypInCount++;
3748 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3749 hcryp->CrypInCount++;
3750 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3751 hcryp->CrypInCount++;
3752
3753 /* Wait for CCF flag to be raised */
3754 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3755 {
3756 /* Disable the CRYP peripheral clock */
3757 __HAL_CRYP_DISABLE(hcryp);
3758
3759 /* Change state */
3760 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3761 hcryp->State = HAL_CRYP_STATE_READY;
3762
3763 /* Process unlocked */
3764 __HAL_UNLOCK(hcryp);
3765 /*Call registered error callback*/
3766 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3767 hcryp->ErrorCallback(hcryp);
3768 #else
3769 /*Call legacy error callback*/
3770 HAL_CRYP_ErrorCallback(hcryp);
3771 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3772 }
3773
3774 /* Clear CCF Flag */
3775 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
3776
3777 /* Read the output block from the output FIFO and put them in temporary buffer then
3778 get CrypOutBuff from temporary buffer*/
3779 for (i = 0U; i < 4U; i++)
3780 {
3781 temp[i] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
3782 }
3783 i = 0U;
3784 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3785 {
3786 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3787 hcryp->CrypOutCount++;
3788 i++;
3789 }
3790 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
3791 #endif /* USE_HAL_SAES_ONLY */
3792 }
3793
3794 /**
3795 * @brief Handle CRYP block input/output data handling under interruption.
3796 * @note The function is called under interruption only, once
3797 * interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
3798 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3799 * the configuration information for CRYP module.
3800 * @retval HAL status
3801 */
CRYP_AES_IT(CRYP_HandleTypeDef * hcryp)3802 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
3803 {
3804 uint32_t temp[4]; /* Temporary CrypOutBuff */
3805 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3806 uint16_t incount; /* Temporary CrypInCount Value */
3807 uint16_t outcount; /* Temporary CrypOutCount Value */
3808 #endif /* USE_HAL_CRYP_ONLY */
3809 uint32_t i;
3810
3811 if (hcryp->State == HAL_CRYP_STATE_BUSY)
3812 {
3813 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
3814 if (IS_CRYP_INSTANCE(hcryp->Instance))
3815 {
3816 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
3817 /* If suspension flag has been raised, suspend processing
3818 only if not already at the end of the payload */
3819 if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
3820 {
3821 /* Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the
3822 CRYP_SR) and the BUSY bit is cleared */
3823 while (((((CRYP_TypeDef *)(hcryp->Instance))->SR) & (CRYP_SR_IFEM | CRYP_SR_OFNE | \
3824 CRYP_SR_BUSY)) != CRYP_SR_IFEM)
3825 {
3826 /* Nothing to do */
3827 }
3828
3829 /* Disable interrupts */
3830 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
3831
3832 /* Disable CRYP */
3833 __HAL_CRYP_DISABLE(hcryp);
3834
3835 /* reset SuspendRequest */
3836 hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
3837
3838 /* Change the CRYP state */
3839 hcryp->State = HAL_CRYP_STATE_SUSPENDED;
3840
3841 /* Process Unlocked */
3842 __HAL_UNLOCK(hcryp);
3843 }
3844 else
3845 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
3846 {
3847 /*Temporary CrypOutCount Value */
3848 incount = hcryp->CrypInCount;
3849
3850 if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3851 {
3852 /* Write the input block in the IN FIFO */
3853 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3854 hcryp->CrypInCount++;
3855 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3856 hcryp->CrypInCount++;
3857 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3858 hcryp->CrypInCount++;
3859 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3860 hcryp->CrypInCount++;
3861 if (hcryp->CrypInCount == (hcryp->Size / 4U))
3862 {
3863 /* Disable interrupts */
3864 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
3865
3866 /* Call the input data transfer complete callback */
3867 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3868 /*Call registered Input complete callback*/
3869 hcryp->InCpltCallback(hcryp);
3870 #else
3871 /*Call legacy Input complete callback*/
3872 HAL_CRYP_InCpltCallback(hcryp);
3873 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3874 }
3875 }
3876
3877 /*Temporary CrypOutCount Value */
3878 outcount = hcryp->CrypOutCount;
3879
3880 if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3881 {
3882 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
3883 temporary buffer */
3884 for (i = 0U; i < 4U; i++)
3885 {
3886 temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
3887 }
3888 i = 0U;
3889 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3890 {
3891 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3892 hcryp->CrypOutCount++;
3893 i++;
3894 }
3895 if (hcryp->CrypOutCount == (hcryp->Size / 4U))
3896 {
3897 /* Disable interrupts */
3898 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
3899
3900 /* Change the CRYP state */
3901 hcryp->State = HAL_CRYP_STATE_READY;
3902
3903 /* Disable CRYP */
3904 __HAL_CRYP_DISABLE(hcryp);
3905
3906 /* Process unlocked */
3907 __HAL_UNLOCK(hcryp);
3908
3909 /* Call output transfer complete callback */
3910 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3911 /*Call registered Output complete callback*/
3912 hcryp->OutCpltCallback(hcryp);
3913 #else
3914 /*Call legacy Output complete callback*/
3915 HAL_CRYP_OutCpltCallback(hcryp);
3916 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3917 }
3918 }
3919 } /* if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) */
3920 }
3921 #endif /* USE_HAL_CRYP_ONLY */
3922 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
3923 if (IS_SAES_INSTANCE(hcryp->Instance))
3924 {
3925 /* Read the output block from the output FIFO and put them in temporary buffer then
3926 get CrypOutBuff from temporary buffer*/
3927 for (i = 0U; i < 4U; i++)
3928 {
3929 temp[i] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
3930 }
3931 i = 0U;
3932 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3933 {
3934 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3935 hcryp->CrypOutCount++;
3936 i++;
3937 }
3938 if (hcryp->CrypOutCount == (hcryp->Size / 4U))
3939 {
3940 /* Disable Computation Complete flag and errors interrupts */
3941 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
3942
3943 /* Change the CRYP state */
3944 hcryp->State = HAL_CRYP_STATE_READY;
3945
3946 /* Disable CRYP */
3947 __HAL_CRYP_DISABLE(hcryp);
3948 __HAL_UNLOCK(hcryp);
3949
3950 /* Call Output transfer complete callback */
3951 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3952 /*Call registered Output complete callback*/
3953 hcryp->OutCpltCallback(hcryp);
3954 #else
3955 /*Call legacy Output complete callback*/
3956 HAL_CRYP_OutCpltCallback(hcryp);
3957 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3958 }
3959 else
3960 {
3961 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
3962 /* If suspension flag has been raised, suspend processing
3963 only if not already at the end of the payload */
3964 if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
3965 {
3966 /* Clear CCF Flag */
3967 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
3968
3969 /* reset SuspendRequest */
3970 hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
3971
3972 /* Disable Computation Complete Flag and Errors Interrupts */
3973 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
3974
3975 /* Change the CRYP state */
3976 hcryp->State = HAL_CRYP_STATE_SUSPENDED;
3977
3978 /* Mark that the payload phase is suspended */
3979 hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
3980
3981 __HAL_UNLOCK(hcryp);
3982 }
3983 else
3984 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
3985 {
3986 /* Write the input block in the IN FIFO */
3987 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3988 hcryp->CrypInCount++;
3989 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3990 hcryp->CrypInCount++;
3991 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3992 hcryp->CrypInCount++;
3993 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3994 hcryp->CrypInCount++;
3995
3996 if (hcryp->CrypInCount == (hcryp->Size / 4U))
3997 {
3998 /* Call Input transfer complete callback */
3999 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4000 /*Call registered Input complete callback*/
4001 hcryp->InCpltCallback(hcryp);
4002 #else
4003 /*Call legacy Input complete callback*/
4004 HAL_CRYP_InCpltCallback(hcryp);
4005 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4006 }
4007 }
4008 } /* if (hcryp->CrypOutCount == (hcryp->Size / 4U)) */
4009 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
4010 #endif /* USE_HAL_SAES_ONLY */
4011 }
4012 else
4013 {
4014 /* Process unlocked */
4015 __HAL_UNLOCK(hcryp);
4016 /* Busy error code field */
4017 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
4018 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4019 /*Call registered error callback*/
4020 hcryp->ErrorCallback(hcryp);
4021 #else
4022 /*Call legacy error callback*/
4023 HAL_CRYP_ErrorCallback(hcryp);
4024 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4025 }
4026 }
4027
4028 /**
4029 * @brief Writes Key in Key registers.
4030 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4031 * the configuration information for CRYP module
4032 * @param KeySize: Size of Key
4033 * @retval None
4034 */
CRYP_SetKey(CRYP_HandleTypeDef * hcryp,uint32_t KeySize)4035 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
4036 {
4037 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4038 if (IS_CRYP_INSTANCE(hcryp->Instance))
4039 {
4040 switch (KeySize)
4041 {
4042 case CRYP_KEYSIZE_256B:
4043 ((CRYP_TypeDef *)(hcryp->Instance))->K0LR = *(uint32_t *)(hcryp->Init.pKey);
4044 ((CRYP_TypeDef *)(hcryp->Instance))->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1);
4045 ((CRYP_TypeDef *)(hcryp->Instance))->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2);
4046 ((CRYP_TypeDef *)(hcryp->Instance))->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3);
4047 ((CRYP_TypeDef *)(hcryp->Instance))->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4);
4048 ((CRYP_TypeDef *)(hcryp->Instance))->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5);
4049 ((CRYP_TypeDef *)(hcryp->Instance))->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6);
4050 ((CRYP_TypeDef *)(hcryp->Instance))->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7);
4051 break;
4052
4053 case CRYP_KEYSIZE_192B:
4054 ((CRYP_TypeDef *)(hcryp->Instance))->K1LR = *(uint32_t *)(hcryp->Init.pKey);
4055 ((CRYP_TypeDef *)(hcryp->Instance))->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
4056 ((CRYP_TypeDef *)(hcryp->Instance))->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
4057 ((CRYP_TypeDef *)(hcryp->Instance))->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
4058 ((CRYP_TypeDef *)(hcryp->Instance))->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
4059 ((CRYP_TypeDef *)(hcryp->Instance))->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
4060 break;
4061
4062 case CRYP_KEYSIZE_128B:
4063 ((CRYP_TypeDef *)(hcryp->Instance))->K2LR = *(uint32_t *)(hcryp->Init.pKey);
4064 ((CRYP_TypeDef *)(hcryp->Instance))->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1);
4065 ((CRYP_TypeDef *)(hcryp->Instance))->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2);
4066 ((CRYP_TypeDef *)(hcryp->Instance))->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3);
4067 break;
4068
4069 default:
4070 break;
4071 }
4072 }
4073 #endif /* USE_HAL_CRYP_ONLY */
4074 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4075 if (IS_SAES_INSTANCE(hcryp->Instance))
4076 {
4077 if (hcryp->Init.pKey != NULL)
4078 {
4079 switch (KeySize)
4080 {
4081 case CRYP_KEYSIZE_256B:
4082 ((SAES_TypeDef *)(hcryp->Instance))->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
4083 ((SAES_TypeDef *)(hcryp->Instance))->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U);
4084 ((SAES_TypeDef *)(hcryp->Instance))->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U);
4085 ((SAES_TypeDef *)(hcryp->Instance))->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U);
4086 ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U);
4087 ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U);
4088 ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U);
4089 ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U);
4090 break;
4091 case CRYP_KEYSIZE_128B:
4092 ((SAES_TypeDef *)(hcryp->Instance))->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
4093 ((SAES_TypeDef *)(hcryp->Instance))->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U);
4094 ((SAES_TypeDef *)(hcryp->Instance))->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U);
4095 ((SAES_TypeDef *)(hcryp->Instance))->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U);
4096
4097 break;
4098 default:
4099 break;
4100 }
4101 } /* if (hcryp->Init.pKey != NULL) */
4102 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
4103 #endif /* USE_HAL_SAES_ONLY */
4104 }
4105
4106 /**
4107 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
4108 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4109 * the configuration information for CRYP module
4110 * @param Timeout: Timeout duration
4111 * @retval HAL status
4112 */
CRYP_AESGCM_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)4113 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
4114 {
4115 uint32_t tickstart;
4116 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
4117 uint32_t npblb ;
4118 uint32_t temp[4]; /* Temporary CrypOutBuff */
4119 uint32_t index ;
4120 uint32_t lastwordsize ;
4121 uint32_t outcount; /* Temporary CrypOutCount Value */
4122 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4123 uint32_t mode;
4124
4125 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4126 {
4127 if (hcryp->KeyIVConfig == 1U)
4128 {
4129 /* If the Key and IV configuration has to be done only once
4130 and if it has already been done, skip it */
4131 DoKeyIVConfig = 0U;
4132 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4133 }
4134 else
4135 {
4136 /* If the Key and IV configuration has to be done only once
4137 and if it has not been done already, do it and set KeyIVConfig
4138 to keep track it won't have to be done again next time */
4139 hcryp->KeyIVConfig = 1U;
4140 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4141 }
4142 }
4143 else
4144 {
4145 hcryp->SizesSum = hcryp->Size;
4146 }
4147
4148 if (DoKeyIVConfig == 1U)
4149 {
4150 /* Reset CrypHeaderCount */
4151 hcryp->CrypHeaderCount = 0U;
4152
4153 /****************************** Init phase **********************************/
4154 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4155 if (IS_CRYP_INSTANCE(hcryp->Instance))
4156 {
4157 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4158
4159 /* Set the Key */
4160 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
4161 {
4162 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
4163 {
4164 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4165 }
4166 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
4167 {
4168 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
4169 }
4170 }
4171
4172 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4173 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
4174 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4175 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4176 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4177
4178 /* Enable the CRYP peripheral */
4179 __HAL_CRYP_ENABLE(hcryp);
4180
4181 /* Get tick */
4182 tickstart = HAL_GetTick();
4183
4184 /*Wait for the CRYPEN bit to be cleared*/
4185 while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
4186 {
4187 /* Check for the Timeout */
4188 if (Timeout != HAL_MAX_DELAY)
4189 {
4190 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4191 {
4192 /* Disable the CRYP peripheral clock */
4193 __HAL_CRYP_DISABLE(hcryp);
4194
4195 /* Change state */
4196 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4197 hcryp->State = HAL_CRYP_STATE_READY;
4198
4199 /* Process unlocked */
4200 __HAL_UNLOCK(hcryp);
4201 return HAL_ERROR;
4202 }
4203 }
4204 }
4205 }
4206 #endif /* USE_HAL_CRYP_ONLY */
4207 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4208 if (IS_SAES_INSTANCE(hcryp->Instance))
4209 {
4210 SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
4211
4212 /* We should re-write Key, in the case where we change key after first operation */
4213 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
4214 {
4215 /* Set the Key */
4216 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4217 }
4218
4219 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4220 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
4221 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4222 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4223 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4224
4225 /* Enable the CRYP peripheral */
4226 __HAL_CRYP_ENABLE(hcryp);
4227
4228 /* just wait for hash computation */
4229 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4230 {
4231 /* Disable the CRYP peripheral clock */
4232 __HAL_CRYP_DISABLE(hcryp);
4233
4234 /* Change state */
4235 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4236 hcryp->State = HAL_CRYP_STATE_READY;
4237
4238 /* Process unlocked */
4239 __HAL_UNLOCK(hcryp);
4240 return HAL_ERROR;
4241 }
4242 /* Clear CCF flag */
4243 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
4244 }
4245 #endif /* USE_HAL_SAES_ONLY */
4246
4247 /************************ Header phase *************************************/
4248
4249 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
4250 {
4251 return HAL_ERROR;
4252 }
4253
4254 /*************************Payload phase ************************************/
4255
4256 /* Set the phase */
4257 hcryp->Phase = CRYP_PHASE_PROCESS;
4258
4259 /* Select payload phase once the header phase is performed */
4260 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4261 if (IS_CRYP_INSTANCE(hcryp->Instance))
4262 {
4263 /* Disable the CRYP peripheral */
4264 __HAL_CRYP_DISABLE(hcryp);
4265
4266 /* Select payload phase once the header phase is performed */
4267 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4268
4269 /* Set to 0 the number of non-valid bytes using NPBLB register*/
4270 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
4271
4272 /* Enable the CRYP peripheral */
4273 __HAL_CRYP_ENABLE(hcryp);
4274 }
4275 #endif /* USE_HAL_CRYP_ONLY */
4276 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4277 if (IS_SAES_INSTANCE(hcryp->Instance))
4278 {
4279 /* Select payload phase once the header phase is performed */
4280 SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
4281
4282 /* Set to 0 the number of non-valid bytes using NPBLB register*/
4283 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
4284 }
4285 #endif /* USE_HAL_SAES_ONLY */
4286
4287 } /* if (DoKeyIVConfig == 1U) */
4288
4289 if ((hcryp->Size % 16U) != 0U)
4290 {
4291 /* recalculate wordsize */
4292 wordsize = ((wordsize / 4U) * 4U) ;
4293 }
4294
4295 /* Get tick */
4296 tickstart = HAL_GetTick();
4297
4298 /*Temporary CrypOutCount Value */
4299 outcount = hcryp->CrypOutCount;
4300 /* Write input data and get output data */
4301 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4302 {
4303 /* Write plain data and get cipher data */
4304 CRYP_AES_ProcessData(hcryp, Timeout);
4305
4306 /*Temporary CrypOutCount Value */
4307 outcount = hcryp->CrypOutCount;
4308
4309 /* Check for the Timeout */
4310 if (Timeout != HAL_MAX_DELAY)
4311 {
4312 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4313 {
4314 /* Disable the CRYP peripheral clock */
4315 __HAL_CRYP_DISABLE(hcryp);
4316
4317 /* Change state */
4318 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4319 hcryp->State = HAL_CRYP_STATE_READY;
4320
4321 /* Process unlocked */
4322 __HAL_UNLOCK(hcryp);
4323 return HAL_ERROR;
4324 }
4325 }
4326 }
4327
4328 if ((hcryp->Size % 16U) != 0U)
4329 {
4330 /* Compute the number of padding bytes in last block of payload */
4331 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
4332
4333 /* Set Npblb in case of AES GCM payload encryption to get right tag */
4334 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4335 if (IS_CRYP_INSTANCE(hcryp->Instance))
4336 {
4337 mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
4338 if (mode == CRYP_OPERATINGMODE_ENCRYPT)
4339 {
4340 /* Disable the CRYP */
4341 __HAL_CRYP_DISABLE(hcryp);
4342
4343 /* Specify the number of non-valid bytes using NPBLB register */
4344 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20U);
4345
4346 /* Enable CRYP to start the final phase */
4347 __HAL_CRYP_ENABLE(hcryp);
4348 }
4349 }
4350 #endif /* USE_HAL_CRYP_ONLY */
4351 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4352 if (IS_SAES_INSTANCE(hcryp->Instance))
4353 {
4354 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
4355 if (mode == CRYP_OPERATINGMODE_ENCRYPT)
4356 {
4357 /* Specify the number of non-valid bytes using NPBLB register */
4358 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20U);
4359 }
4360 }
4361 #endif /* USE_HAL_SAES_ONLY */
4362
4363 /* Number of valid words (lastwordsize) in last block */
4364 if ((npblb % 4U) == 0U)
4365 {
4366 lastwordsize = (16U - npblb) / 4U;
4367 }
4368 else
4369 {
4370 lastwordsize = ((16U - npblb) / 4U) + 1U;
4371 }
4372 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4373 if (IS_CRYP_INSTANCE(hcryp->Instance))
4374 {
4375 /* Write the last input block in the IN FIFO */
4376 for (index = 0U; index < lastwordsize; index ++)
4377 {
4378 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4379 hcryp->CrypInCount++;
4380 }
4381
4382 /* Pad the data with zeros to have a complete block */
4383 while (index < 4U)
4384 {
4385 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
4386 index++;
4387 }
4388
4389 /* Wait for OFNE flag to be raised */
4390 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
4391 {
4392 /* Disable the CRYP peripheral clock */
4393 __HAL_CRYP_DISABLE(hcryp);
4394
4395 /* Change state */
4396 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4397 hcryp->State = HAL_CRYP_STATE_READY;
4398
4399 /* Process Unlocked */
4400 __HAL_UNLOCK(hcryp);
4401 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4402 /*Call registered error callback*/
4403 hcryp->ErrorCallback(hcryp);
4404 #else
4405 /*Call legacy error callback*/
4406 HAL_CRYP_ErrorCallback(hcryp);
4407 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4408 }
4409
4410 /*Read the output block from the output FIFO */
4411 if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U)
4412 {
4413 for (index = 0U; index < 4U; index++)
4414 {
4415 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
4416 temporary buffer */
4417 temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
4418 }
4419 }
4420 else
4421 {
4422 /* Disable the CRYP peripheral clock */
4423 __HAL_CRYP_DISABLE(hcryp);
4424
4425 /* Change state */
4426 hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
4427 hcryp->State = HAL_CRYP_STATE_READY;
4428
4429 /* Process unlocked */
4430 __HAL_UNLOCK(hcryp);
4431 return HAL_ERROR;
4432 }
4433 }
4434 #endif /* USE_HAL_CRYP_ONLY */
4435 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4436 if (IS_SAES_INSTANCE(hcryp->Instance))
4437 {
4438 /* Write the last input block in the IN FIFO */
4439 for (index = 0U; index < lastwordsize; index ++)
4440 {
4441 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4442 hcryp->CrypInCount++;
4443 }
4444 while (index < 4U)
4445 {
4446 /* pad the data with zeros to have a complete block */
4447 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U;
4448 index++;
4449 }
4450 /* Wait for CCF flag to be raised */
4451 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4452 {
4453 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4454 /*Call registered error callback*/
4455 hcryp->ErrorCallback(hcryp);
4456 #else
4457 /*Call legacy error callback*/
4458 HAL_CRYP_ErrorCallback(hcryp);
4459 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4460 }
4461
4462 /* Clear CCF Flag */
4463 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
4464
4465 /*Read the output block from the output FIFO */
4466 for (index = 0U; index < 4U; index++)
4467 {
4468 /* Read the output block from the output FIFO and put them in temporary buffer then
4469 get CrypOutBuff from temporary buffer */
4470 temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
4471 }
4472 }
4473 #endif /* USE_HAL_SAES_ONLY */
4474 for (index = 0U; index < lastwordsize; index++)
4475 {
4476 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
4477 hcryp->CrypOutCount++;
4478 }
4479 }
4480
4481 /* Return function status */
4482 return HAL_OK;
4483 }
4484
4485 /**
4486 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
4487 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4488 * the configuration information for CRYP module
4489 * @retval HAL status
4490 */
CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef * hcryp)4491 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
4492 {
4493 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4494 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4495 uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
4496 uint32_t tickstart;
4497 #endif /* USE_HAL_CRYP_ONLY */
4498 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4499 uint32_t count;
4500 uint32_t loopcounter;
4501 uint32_t lastwordsize;
4502 uint32_t headersize_in_bytes;
4503 uint32_t tmp;
4504 uint32_t npblb;
4505 const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
4506 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
4507 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
4508 }; /* 8-bit data type */
4509 #endif /* USE_HAL_SAES_ONLY */
4510
4511 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
4512 if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
4513 {
4514 CRYP_PhaseProcessingResume(hcryp);
4515 return HAL_OK;
4516 }
4517 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
4518
4519 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4520 /* Manage header size given in bytes to handle cases where
4521 header size is not a multiple of 4 bytes */
4522 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
4523 {
4524 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
4525 }
4526 else
4527 {
4528 headersize_in_bytes = hcryp->Init.HeaderSize;
4529 }
4530 #endif /* USE_HAL_SAES_ONLY */
4531
4532 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4533 {
4534 if (hcryp->KeyIVConfig == 1U)
4535 {
4536 /* If the Key and IV configuration has to be done only once
4537 and if it has already been done, skip it */
4538 DoKeyIVConfig = 0U;
4539 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4540 }
4541 else
4542 {
4543 /* If the Key and IV configuration has to be done only once
4544 and if it has not been done already, do it and set KeyIVConfig
4545 to keep track it won't have to be done again next time */
4546 hcryp->KeyIVConfig = 1U;
4547 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4548 }
4549 }
4550 else
4551 {
4552 hcryp->SizesSum = hcryp->Size;
4553 }
4554
4555 /* Configure Key, IV and process message (header and payload) */
4556 if (DoKeyIVConfig == 1U)
4557 {
4558 /* Reset CrypHeaderCount */
4559 hcryp->CrypHeaderCount = 0U;
4560
4561 /******************************* Init phase *********************************/
4562 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4563 if (IS_CRYP_INSTANCE(hcryp->Instance))
4564 {
4565 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4566
4567 /* Set the Key */
4568 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
4569 {
4570 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
4571 {
4572 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4573 }
4574 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
4575 {
4576 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
4577 }
4578 }
4579 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4580 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
4581 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4582 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4583 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4584
4585 /* Enable the CRYP peripheral */
4586 __HAL_CRYP_ENABLE(hcryp);
4587
4588 /* Get tick */
4589 tickstart = HAL_GetTick();
4590 /*Wait for the CRYPEN bit to be cleared */
4591 while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
4592 {
4593 /* Check for the Timeout */
4594 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4595 {
4596 /* Disable the CRYP peripheral clock */
4597 __HAL_CRYP_DISABLE(hcryp);
4598
4599 /* Change state */
4600 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4601 hcryp->State = HAL_CRYP_STATE_READY;
4602
4603 /* Process unlocked */
4604 __HAL_UNLOCK(hcryp);
4605 return HAL_ERROR;
4606 }
4607 }
4608 }
4609 #endif /* USE_HAL_CRYP_ONLY */
4610 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4611 if (IS_SAES_INSTANCE(hcryp->Instance))
4612 {
4613 SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
4614
4615 /* We should re-write Key, in the case where we change key after first operation */
4616 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
4617 {
4618 /* Set the Key */
4619 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4620 }
4621 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
4622 {
4623 ((SAES_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
4624 }
4625
4626 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4627 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
4628 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4629 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4630 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4631
4632 /* Enable the CRYP peripheral */
4633 __HAL_CRYP_ENABLE(hcryp);
4634
4635 /* Wait for KEYVALID flag to be set */
4636 count = CRYP_TIMEOUT_KEYPREPARATION;
4637 do
4638 {
4639 count--;
4640 if (count == 0U)
4641 {
4642 /* Disable the SAES peripheral clock */
4643 __HAL_CRYP_DISABLE(hcryp);
4644
4645 /* Change state */
4646 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4647 hcryp->State = HAL_CRYP_STATE_READY;
4648 __HAL_UNLOCK(hcryp);
4649 return HAL_ERROR;
4650 }
4651 } while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_KEYVALID));
4652
4653 /* just wait for hash computation */
4654 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4655 do
4656 {
4657 count--;
4658 if (count == 0U)
4659 {
4660 /* Disable the CRYP peripheral clock */
4661 __HAL_CRYP_DISABLE(hcryp);
4662
4663 /* Change state */
4664 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4665 hcryp->State = HAL_CRYP_STATE_READY;
4666 __HAL_UNLOCK(hcryp);
4667 return HAL_ERROR;
4668 }
4669 } while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF));
4670
4671 /* Clear CCF flag */
4672 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
4673 }
4674 #endif /* USE_HAL_SAES_ONLY */
4675
4676 /***************************** Header phase *********************************/
4677
4678 /* Select header phase */
4679 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4680 if (IS_CRYP_INSTANCE(hcryp->Instance))
4681 {
4682 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4683 }
4684 #endif /* USE_HAL_CRYP_ONLY */
4685 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4686 if (IS_SAES_INSTANCE(hcryp->Instance))
4687 {
4688 SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
4689
4690 /* Enable computation complete flag and error interrupts */
4691 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
4692
4693 /* Enable the CRYP peripheral */
4694 __HAL_CRYP_ENABLE(hcryp);
4695
4696 if (headersize_in_bytes == 0U) /*header phase is skipped*/
4697 {
4698 /* Set the phase */
4699 hcryp->Phase = CRYP_PHASE_PROCESS;
4700
4701 /* Select payload phase once the header phase is performed */
4702 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_GCMPH, SAES_PHASE_PAYLOAD);
4703
4704 /* Set to 0 the number of non-valid bytes using NPBLB register*/
4705 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
4706
4707 /* Write the payload Input block in the IN FIFO */
4708 if (hcryp->Size == 0U)
4709 {
4710 /* Disable interrupts */
4711 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
4712
4713 /* Change the CRYP state */
4714 hcryp->State = HAL_CRYP_STATE_READY;
4715 __HAL_UNLOCK(hcryp);
4716 }
4717 else if (hcryp->Size >= 16U)
4718 {
4719 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4720 hcryp->CrypInCount++;
4721 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4722 hcryp->CrypInCount++;
4723 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4724 hcryp->CrypInCount++;
4725 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4726 hcryp->CrypInCount++;
4727 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
4728 {
4729 /* Call Input transfer complete callback */
4730 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4731 /*Call registered Input complete callback*/
4732 hcryp->InCpltCallback(hcryp);
4733 #else
4734 /*Call legacy Input complete callback*/
4735 HAL_CRYP_InCpltCallback(hcryp);
4736 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4737 }
4738 }
4739 else /* Size < 16Bytes : first block is the last block*/
4740 {
4741 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4742 Workaround is implemented in polling mode, so if last block of
4743 payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
4744
4745
4746 /* Compute the number of padding bytes in last block of payload */
4747 npblb = 16U - ((uint32_t)hcryp->Size);
4748
4749 if ((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
4750 {
4751 /* Set to 0 the number of non-valid bytes using NPBLB register*/
4752 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
4753 }
4754
4755 /* Number of valid words (lastwordsize) in last block */
4756 if ((npblb % 4U) == 0U)
4757 {
4758 lastwordsize = (16U - npblb) / 4U;
4759 }
4760 else
4761 {
4762 lastwordsize = ((16U - npblb) / 4U) + 1U;
4763 }
4764
4765 /* last block optionally pad the data with zeros*/
4766 for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
4767 {
4768 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4769 hcryp->CrypInCount++;
4770 }
4771 while (loopcounter < 4U)
4772 {
4773 /* pad the data with zeros to have a complete block */
4774 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
4775 loopcounter++;
4776 }
4777 /* Call Input transfer complete callback */
4778 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4779 /*Call registered Input complete callback*/
4780 hcryp->InCpltCallback(hcryp);
4781 #else
4782 /*Call legacy Input complete callback*/
4783 HAL_CRYP_InCpltCallback(hcryp);
4784 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4785 }
4786 }
4787 /* Enter header data */
4788 /* Cher first whether header length is small enough to enter the full header in one shot */
4789 else if (headersize_in_bytes <= 16U)
4790 {
4791 /* Write header data, padded with zeros if need be */
4792 for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
4793 {
4794 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4795 hcryp->CrypHeaderCount++ ;
4796 }
4797 /* If the header size is a multiple of words */
4798 if ((headersize_in_bytes % 4U) == 0U)
4799 {
4800 /* Pad the data with zeros to have a complete block */
4801 while (loopcounter < 4U)
4802 {
4803 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
4804 loopcounter++;
4805 hcryp->CrypHeaderCount++;
4806 }
4807 }
4808 else
4809 {
4810 /* Enter last bytes, padded with zeros */
4811 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4812 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
4813 ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
4814 loopcounter++;
4815 hcryp->CrypHeaderCount++ ;
4816 /* Pad the data with zeros to have a complete block */
4817 while (loopcounter < 4U)
4818 {
4819 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
4820 loopcounter++;
4821 hcryp->CrypHeaderCount++;
4822 }
4823 }
4824 /* Call Input transfer complete callback */
4825 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4826 /*Call registered Input complete callback*/
4827 hcryp->InCpltCallback(hcryp);
4828 #else
4829 /*Call legacy Input complete callback*/
4830 HAL_CRYP_InCpltCallback(hcryp);
4831 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4832 }
4833 else
4834 {
4835 /* Write the first input header block in the Input FIFO,
4836 the following header data will be fed after interrupt occurrence */
4837 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4838 hcryp->CrypHeaderCount++;
4839 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4840 hcryp->CrypHeaderCount++;
4841 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4842 hcryp->CrypHeaderCount++;
4843 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4844 hcryp->CrypHeaderCount++;
4845 }
4846 }
4847 #endif /* USE_HAL_SAES_ONLY */
4848 } /* end of if (DoKeyIVConfig == 1U) */
4849 else /* Key and IV have already been configured,
4850 header has already been processed;
4851 only process here message payload */
4852 {
4853 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
4854 if (IS_SAES_INSTANCE(hcryp->Instance))
4855 {
4856 /* Enable computation complete flag and error interrupts */
4857 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
4858
4859 /* Set to 0 the number of non-valid bytes using NPBLB register*/
4860 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
4861
4862 /* Write the payload Input block in the IN FIFO */
4863 if (hcryp->Size == 0U)
4864 {
4865 /* Disable interrupts */
4866 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
4867
4868 /* Change the CRYP state */
4869 hcryp->State = HAL_CRYP_STATE_READY;
4870 __HAL_UNLOCK(hcryp);
4871 }
4872 else if (hcryp->Size >= 16U)
4873 {
4874 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4875 hcryp->CrypInCount++;
4876 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4877 hcryp->CrypInCount++;
4878 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4879 hcryp->CrypInCount++;
4880 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4881 hcryp->CrypInCount++;
4882 if (hcryp->CrypInCount == (hcryp->Size / 4U))
4883 {
4884 /* Call Input transfer complete callback */
4885 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4886 /*Call registered Input complete callback*/
4887 hcryp->InCpltCallback(hcryp);
4888 #else
4889 /*Call legacy Input complete callback*/
4890 HAL_CRYP_InCpltCallback(hcryp);
4891 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4892 }
4893 }
4894 else /* Size < 16Bytes : first block is the last block*/
4895 {
4896 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4897 Workaround is implemented in polling mode, so if last block of
4898 payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
4899
4900 /* Compute the number of padding bytes in last block of payload */
4901 npblb = 16U - ((uint32_t)hcryp->Size);
4902
4903 if ((((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
4904 {
4905 /* Set to 0 the number of non-valid bytes using NPBLB register*/
4906 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
4907 }
4908
4909 /* Number of valid words (lastwordsize) in last block */
4910 if ((npblb % 4U) == 0U)
4911 {
4912 lastwordsize = (16U - npblb) / 4U;
4913 }
4914 else
4915 {
4916 lastwordsize = ((16U - npblb) / 4U) + 1U;
4917 }
4918
4919 /* last block optionally pad the data with zeros*/
4920 for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
4921 {
4922 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4923 hcryp->CrypInCount++;
4924 }
4925 while (loopcounter < 4U)
4926 {
4927 /* pad the data with zeros to have a complete block */
4928 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
4929 loopcounter++;
4930 }
4931 }
4932 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
4933 #endif /* USE_HAL_SAES_ONLY */
4934 } /* if (DoKeyIVConfig != 1U) */
4935
4936 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4937 if (IS_CRYP_INSTANCE(hcryp->Instance))
4938 {
4939 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4940
4941 /* Enable interrupts */
4942 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
4943
4944 /* Enable CRYP */
4945 __HAL_CRYP_ENABLE(hcryp);
4946 }
4947 #endif /* USE_HAL_CRYP_ONLY */
4948
4949 /* Return function status */
4950 return HAL_OK;
4951 }
4952
4953 /**
4954 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
4955 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4956 * the configuration information for CRYP module
4957 * @retval HAL status
4958 */
CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef * hcryp)4959 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4960 {
4961 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4962 __IO uint32_t count = 0U;
4963 #endif /* USE_HAL_CRYP_ONLY */
4964 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
4965 uint32_t index;
4966 uint32_t npblb;
4967 uint32_t lastwordsize = 0U;
4968 uint32_t temp[4]; /* Temporary CrypOutBuff */
4969 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4970 uint32_t mode;
4971 uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
4972 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
4973 uint32_t tickstart;
4974 #endif /* USE_HAL_CRYP_ONLY */
4975
4976 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4977 {
4978 if (hcryp->KeyIVConfig == 1U)
4979 {
4980 /* If the Key and IV configuration has to be done only once
4981 and if it has already been done, skip it */
4982 DoKeyIVConfig = 0U;
4983 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4984 }
4985 else
4986 {
4987 /* If the Key and IV configuration has to be done only once
4988 and if it has not been done already, do it and set KeyIVConfig
4989 to keep track it won't have to be done again next time */
4990 hcryp->KeyIVConfig = 1U;
4991 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4992 }
4993 }
4994 else
4995 {
4996 hcryp->SizesSum = hcryp->Size;
4997 }
4998
4999 if (DoKeyIVConfig == 1U)
5000 {
5001 /* Reset CrypHeaderCount */
5002 hcryp->CrypHeaderCount = 0U;
5003
5004 /*************************** Init phase ************************************/
5005 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5006 if (IS_CRYP_INSTANCE(hcryp->Instance))
5007 {
5008 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
5009
5010 /* Set the Key */
5011 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
5012 {
5013 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
5014 {
5015 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5016 }
5017 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
5018 {
5019 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
5020 }
5021 }
5022
5023 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
5024 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
5025 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
5026 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
5027 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
5028
5029 /* Enable the CRYP peripheral */
5030 __HAL_CRYP_ENABLE(hcryp);
5031
5032 /* Get tick */
5033 tickstart = HAL_GetTick();
5034 /*Wait for the CRYPEN bit to be cleared */
5035 while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
5036 {
5037 /* Check for the Timeout */
5038 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
5039 {
5040 /* Disable the CRYP peripheral clock */
5041 __HAL_CRYP_DISABLE(hcryp);
5042
5043 /* Change state */
5044 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5045 hcryp->State = HAL_CRYP_STATE_READY;
5046
5047 /* Process unlocked */
5048 __HAL_UNLOCK(hcryp);
5049 }
5050 }
5051 }
5052 #endif /* USE_HAL_CRYP_ONLY */
5053 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5054 if (IS_SAES_INSTANCE(hcryp->Instance))
5055 {
5056 SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
5057
5058 /* Set the Key */
5059 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5060
5061 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
5062 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
5063 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
5064 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
5065 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
5066
5067 /* Enable the CRYP peripheral */
5068 __HAL_CRYP_ENABLE(hcryp);
5069
5070 /* Wait for CCF to be raised */
5071 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5072 {
5073 /* Disable the CRYP peripheral clock */
5074 __HAL_CRYP_DISABLE(hcryp);
5075
5076 /* Change state */
5077 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5078 hcryp->State = HAL_CRYP_STATE_READY;
5079
5080 /* Process unlocked */
5081 __HAL_UNLOCK(hcryp);
5082 return HAL_ERROR;
5083 }
5084 /* Clear CCF flag */
5085 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
5086 }
5087 #endif /* USE_HAL_SAES_ONLY */
5088 /************************ Header phase *************************************/
5089
5090 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
5091 {
5092 return HAL_ERROR;
5093 }
5094
5095 /************************ Payload phase ************************************/
5096
5097 /* Set the phase */
5098 hcryp->Phase = CRYP_PHASE_PROCESS;
5099
5100 /* Select payload phase once the header phase is performed */
5101 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5102 if (IS_CRYP_INSTANCE(hcryp->Instance))
5103 {
5104 /* Disable the CRYP peripheral */
5105 __HAL_CRYP_DISABLE(hcryp);
5106
5107 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
5108
5109 /* Set to 0 the number of non-valid bytes using NPBLB register*/
5110 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
5111
5112 /* Enable the CRYP peripheral */
5113 __HAL_CRYP_ENABLE(hcryp);
5114 }
5115 #endif /* USE_HAL_CRYP_ONLY */
5116 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5117 if (IS_SAES_INSTANCE(hcryp->Instance))
5118 {
5119 SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
5120
5121 /* Set to 0 the number of non-valid bytes using NPBLB register*/
5122 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
5123 }
5124 #endif /* USE_HAL_SAES_ONLY */
5125
5126 } /* if (DoKeyIVConfig == 1U) */
5127
5128 if (hcryp->Size == 0U)
5129 {
5130 /* Process unLocked */
5131 __HAL_UNLOCK(hcryp);
5132
5133 /* Change the CRYP state and phase */
5134 hcryp->State = HAL_CRYP_STATE_READY;
5135 }
5136 else if (hcryp->Size >= 16U)
5137 {
5138 /* DMA transfer must not include the last block in case of Size is not %16 */
5139 wordsize = wordsize - (wordsize % 4U);
5140
5141 /* DMA transfer */
5142 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize * 4U,
5143 (uint32_t)(hcryp->pCrypOutBuffPtr));
5144 }
5145 else /* length of input data is < 16 */
5146 {
5147 /* Compute the number of padding bytes in last block of payload */
5148 npblb = 16U - (uint32_t)hcryp->Size;
5149
5150 /* Set Npblb in case of AES GCM payload encryption to get right tag*/
5151 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5152 if (IS_CRYP_INSTANCE(hcryp->Instance))
5153 {
5154 mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
5155
5156 if (mode == CRYP_OPERATINGMODE_ENCRYPT)
5157 {
5158 /* Specify the number of non-valid bytes using NPBLB register*/
5159 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
5160 }
5161
5162 /* Enable CRYP to start the final phase */
5163 __HAL_CRYP_ENABLE(hcryp);
5164
5165 /* Number of valid words (lastwordsize) in last block */
5166 if ((npblb % 4U) == 0U)
5167 {
5168 lastwordsize = (16U - npblb) / 4U;
5169 }
5170 else
5171 {
5172 lastwordsize = ((16U - npblb) / 4U) + 1U;
5173 }
5174
5175 /* Write the last input block in the IN FIFO */
5176 for (index = 0; index < lastwordsize; index ++)
5177 {
5178 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5179 hcryp->CrypInCount++;
5180 }
5181
5182 /* Pad the data with zeros to have a complete block */
5183 while (index < 4U)
5184 {
5185 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
5186 index++;
5187 }
5188
5189 /* Wait for OFNE flag to be raised */
5190 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5191 do
5192 {
5193 count-- ;
5194 if (count == 0U)
5195 {
5196 /* Disable the CRYP peripheral clock */
5197 __HAL_CRYP_DISABLE(hcryp);
5198
5199 /* Change state */
5200 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5201 hcryp->State = HAL_CRYP_STATE_READY;
5202
5203 /* Process unlocked */
5204 __HAL_UNLOCK(hcryp);
5205 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5206 /*Call registered error callback*/
5207 hcryp->ErrorCallback(hcryp);
5208 #else
5209 /*Call legacy error callback*/
5210 HAL_CRYP_ErrorCallback(hcryp);
5211 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5212 }
5213 } while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_OFNE));
5214
5215 /*Read the output block from the output FIFO */
5216 for (index = 0U; index < 4U; index++)
5217 {
5218 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
5219 temporary buffer */
5220 temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
5221 }
5222 }
5223 #endif /* USE_HAL_CRYP_ONLY */
5224 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5225 if (IS_SAES_INSTANCE(hcryp->Instance))
5226 {
5227
5228 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
5229 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
5230 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
5231 {
5232 /* Specify the number of non-valid bytes using NPBLB register*/
5233 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20);
5234 }
5235
5236 /* Number of valid words (lastwordsize) in last block */
5237 if ((npblb % 4U) == 0U)
5238 {
5239 lastwordsize = (16U - npblb) / 4U;
5240 }
5241 else
5242 {
5243 lastwordsize = ((16U - npblb) / 4U) + 1U;
5244 }
5245
5246 /* Write the last input block in the IN FIFO */
5247 for (index = 0; index < lastwordsize; index ++)
5248 {
5249 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5250 hcryp->CrypInCount++;
5251 }
5252
5253 /* Pad the data with zeros to have a complete block */
5254 while (index < 4U)
5255 {
5256 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U;
5257 index++;
5258 }
5259
5260 /* Wait for CCF flag to be raised */
5261 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5262 {
5263 /* Disable the CRYP peripheral clock */
5264 __HAL_CRYP_DISABLE(hcryp);
5265
5266 /* Change state */
5267 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5268 hcryp->State = HAL_CRYP_STATE_READY;
5269
5270 /* Process unlocked */
5271 __HAL_UNLOCK(hcryp);
5272 /*Call registered error callback*/
5273 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5274 hcryp->ErrorCallback(hcryp);
5275 #else
5276 /*Call legacy error callback*/
5277 HAL_CRYP_ErrorCallback(hcryp);
5278 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5279 }
5280 /* Clear the CCF flag by setting the CCF bit of the SAES_ICR register */
5281 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
5282
5283 /*Read the output block from the output FIFO */
5284 for (index = 0U; index < 4U; index++)
5285 {
5286 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
5287 temporary buffer */
5288 temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
5289 }
5290 }
5291 #endif /* USE_HAL_SAES_ONLY */
5292
5293 for (index = 0; index < lastwordsize; index++)
5294 {
5295 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
5296 hcryp->CrypOutCount++;
5297 }
5298
5299 /* Change the CRYP state to ready */
5300 hcryp->State = HAL_CRYP_STATE_READY;
5301
5302 /* Process unlocked */
5303 __HAL_UNLOCK(hcryp);
5304 }
5305
5306 /* Return function status */
5307 return HAL_OK;
5308 }
5309
5310
5311 /**
5312 * @brief AES CCM encryption/decryption processing in polling mode
5313 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5314 * the configuration information for CRYP module
5315 * @param Timeout: Timeout duration
5316 * @retval HAL status
5317 */
CRYP_AESCCM_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)5318 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
5319 {
5320 uint32_t tickstart;
5321 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
5322 uint32_t npblb ;
5323 uint32_t lastwordsize ;
5324 uint32_t temp[4] ; /* Temporary CrypOutBuff */
5325 uint32_t index ;
5326 uint32_t outcount; /* Temporary CrypOutCount Value */
5327 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
5328 uint32_t mode;
5329
5330 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
5331 {
5332 if (hcryp->KeyIVConfig == 1U)
5333 {
5334 /* If the Key and IV configuration has to be done only once
5335 and if it has already been done, skip it */
5336 DoKeyIVConfig = 0U;
5337 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
5338 }
5339 else
5340 {
5341 /* If the Key and IV configuration has to be done only once
5342 and if it has not been done already, do it and set KeyIVConfig
5343 to keep track it won't have to be done again next time */
5344 hcryp->KeyIVConfig = 1U;
5345 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
5346 }
5347 }
5348 else
5349 {
5350 hcryp->SizesSum = hcryp->Size;
5351 }
5352
5353 if (DoKeyIVConfig == 1U)
5354 {
5355 /* Reset CrypHeaderCount */
5356 hcryp->CrypHeaderCount = 0U;
5357
5358 /********************** Init phase ******************************************/
5359 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5360 if (IS_CRYP_INSTANCE(hcryp->Instance))
5361 {
5362 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
5363
5364 /* Set the Key */
5365 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
5366 {
5367 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
5368 {
5369 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5370 }
5371 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
5372 {
5373 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
5374 }
5375 }
5376 /* Set the initialization vector (IV) with CTR1 information */
5377 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
5378 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = hcryp->Init.B0[1];
5379 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = hcryp->Init.B0[2];
5380 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
5381
5382 /* Enable the CRYP peripheral */
5383 __HAL_CRYP_ENABLE(hcryp);
5384
5385 /* Set the initialization vector (IV) with B0 */
5386 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0);
5387 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
5388 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
5389 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
5390
5391 /* Get tick */
5392 tickstart = HAL_GetTick();
5393
5394 /*Wait for the CRYPEN bit to be cleared*/
5395 while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
5396 {
5397 /* Check for the Timeout */
5398 if (Timeout != HAL_MAX_DELAY)
5399 {
5400 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
5401 {
5402 /* Disable the CRYP peripheral clock */
5403 __HAL_CRYP_DISABLE(hcryp);
5404
5405 /* Change state */
5406 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5407 hcryp->State = HAL_CRYP_STATE_READY;
5408
5409 /* Process unlocked */
5410 __HAL_UNLOCK(hcryp);
5411 return HAL_ERROR;
5412 }
5413 }
5414 }
5415 }
5416 #endif /* USE_HAL_CRYP_ONLY */
5417 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5418 if (IS_SAES_INSTANCE(hcryp->Instance))
5419 {
5420 SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
5421
5422 /* We should re-write Key, in the case where we change key after first operation */
5423 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
5424 {
5425 /* Set the Key */
5426 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5427 }
5428
5429 /* Set the initialization vector (IV) with B0 */
5430 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.B0);
5431 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
5432 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
5433 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
5434
5435 /* Enable the CRYP peripheral */
5436 __HAL_CRYP_ENABLE(hcryp);
5437
5438 /* just wait for hash computation */
5439 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5440 {
5441 /* Disable the CRYP peripheral clock */
5442 __HAL_CRYP_DISABLE(hcryp);
5443
5444 /* Change state */
5445 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5446 hcryp->State = HAL_CRYP_STATE_READY;
5447
5448 /* Process unlocked */
5449 __HAL_UNLOCK(hcryp);
5450 return HAL_ERROR;
5451 }
5452 /* Clear CCF flag */
5453 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
5454 }
5455 #endif /* USE_HAL_SAES_ONLY */
5456
5457 /************************* Header phase *************************************/
5458 /* Header block(B1) : associated data length expressed in bytes concatenated
5459 with Associated Data (A)*/
5460
5461 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
5462 {
5463 return HAL_ERROR;
5464 }
5465 /********************** Payload phase ***************************************/
5466
5467 /* Set the phase */
5468 hcryp->Phase = CRYP_PHASE_PROCESS;
5469
5470 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5471 /* Select payload phase once the header phase is performed */
5472 if (IS_CRYP_INSTANCE(hcryp->Instance))
5473 {
5474 /* Disable the CRYP peripheral */
5475 __HAL_CRYP_DISABLE(hcryp);
5476
5477 /* Set to 0 the number of non-valid bytes using NPBLB register*/
5478 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
5479
5480 /* Select payload phase once the header phase is performed */
5481 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
5482
5483 /* Enable the CRYP peripheral */
5484 __HAL_CRYP_ENABLE(hcryp);
5485 }
5486 #endif /* USE_HAL_CRYP_ONLY */
5487 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5488 if (IS_SAES_INSTANCE(hcryp->Instance))
5489 {
5490 /* Set to 0 the number of non-valid bytes using NPBLB register*/
5491 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
5492
5493 /* Select payload phase once the header phase is performed */
5494 SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
5495 }
5496 #endif /* USE_HAL_SAES_ONLY */
5497
5498 } /* if (DoKeyIVConfig == 1U) */
5499
5500 if ((hcryp->Size % 16U) != 0U)
5501 {
5502 /* recalculate wordsize */
5503 wordsize = ((wordsize / 4U) * 4U) ;
5504 }
5505 /* Get tick */
5506 tickstart = HAL_GetTick();
5507
5508 /*Temporary CrypOutCount Value */
5509 outcount = hcryp->CrypOutCount;
5510 /* Write input data and get output data */
5511 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
5512 {
5513 /* Write plain data and get cipher data */
5514 CRYP_AES_ProcessData(hcryp, Timeout);
5515
5516 /*Temporary CrypOutCount Value */
5517 outcount = hcryp->CrypOutCount;
5518
5519 /* Check for the Timeout */
5520 if (Timeout != HAL_MAX_DELAY)
5521 {
5522 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
5523 {
5524 /* Disable the CRYP peripheral clock */
5525 __HAL_CRYP_DISABLE(hcryp);
5526
5527 /* Change state */
5528 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5529 hcryp->State = HAL_CRYP_STATE_READY;
5530
5531 /* Process unlocked */
5532 __HAL_UNLOCK(hcryp);
5533 return HAL_ERROR;
5534 }
5535 }
5536 }
5537
5538 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5539 if (IS_CRYP_INSTANCE(hcryp->Instance))
5540 {
5541 if ((hcryp->Size % 16U) != 0U)
5542 {
5543 /* Compute the number of padding bytes in last block of payload */
5544 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5545
5546 mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
5547 if (mode == CRYP_OPERATINGMODE_DECRYPT)
5548 {
5549 /* Disable the CRYP */
5550 __HAL_CRYP_DISABLE(hcryp);
5551
5552 /* Set Npblb in case of AES CCM payload decryption to get right tag */
5553 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
5554
5555 /* Enable CRYP to start the final phase */
5556 __HAL_CRYP_ENABLE(hcryp);
5557 }
5558
5559 /* Number of valid words (lastwordsize) in last block */
5560 if ((npblb % 4U) == 0U)
5561 {
5562 lastwordsize = (16U - npblb) / 4U;
5563 }
5564 else
5565 {
5566 lastwordsize = ((16U - npblb) / 4U) + 1U;
5567 }
5568
5569 /* Write the last input block in the IN FIFO */
5570 for (index = 0U; index < lastwordsize; index ++)
5571 {
5572 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5573 hcryp->CrypInCount++;
5574 }
5575
5576 /* Pad the data with zeros to have a complete block */
5577 while (index < 4U)
5578 {
5579 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
5580 index++;
5581 }
5582
5583 /* Wait for OFNE flag to be raised */
5584 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
5585 {
5586 /* Disable the CRYP peripheral clock */
5587 __HAL_CRYP_DISABLE(hcryp);
5588
5589 /* Change state */
5590 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5591 hcryp->State = HAL_CRYP_STATE_READY;
5592
5593 /* Process Unlocked */
5594 __HAL_UNLOCK(hcryp);
5595 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5596 /*Call registered error callback*/
5597 hcryp->ErrorCallback(hcryp);
5598 #else
5599 /*Call legacy error callback*/
5600 HAL_CRYP_ErrorCallback(hcryp);
5601 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5602 }
5603
5604 /*Read the output block from the output FIFO */
5605 if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U)
5606 {
5607 for (index = 0U; index < 4U; index++)
5608 {
5609 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
5610 temporary buffer */
5611 temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
5612 }
5613 for (index = 0; index < lastwordsize; index++)
5614 {
5615 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
5616 hcryp->CrypOutCount++;
5617 }
5618 }
5619 }
5620 }
5621 #endif /* USE_HAL_CRYP_ONLY */
5622 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5623 if (IS_SAES_INSTANCE(hcryp->Instance))
5624 {
5625
5626 if ((hcryp->Size % 16U) != 0U)
5627 {
5628 /* Compute the number of padding bytes in last block of payload */
5629 npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
5630
5631 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
5632 if (mode == CRYP_OPERATINGMODE_DECRYPT)
5633 {
5634 /* Set Npblb in case of AES CCM payload decryption to get right tag */
5635 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20);
5636 }
5637 /* Number of valid words (lastwordsize) in last block */
5638 if ((npblb % 4U) == 0U)
5639 {
5640 lastwordsize = (16U - npblb) / 4U;
5641 }
5642 else
5643 {
5644 lastwordsize = ((16U - npblb) / 4U) + 1U;
5645 }
5646
5647 /* Write the last input block in the IN FIFO */
5648 for (index = 0U; index < lastwordsize; index ++)
5649 {
5650 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5651 hcryp->CrypInCount++;
5652 }
5653
5654 /* Pad the data with zeros to have a complete block */
5655 while (index < 4U)
5656 {
5657 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U;
5658 index++;
5659 }
5660 /* just wait for hash computation */
5661 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5662 {
5663 /* Disable the CRYP peripheral clock */
5664 __HAL_CRYP_DISABLE(hcryp);
5665
5666 /* Change state */
5667 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5668 hcryp->State = HAL_CRYP_STATE_READY;
5669
5670 /* Process Unlocked */
5671 __HAL_UNLOCK(hcryp);
5672 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5673 /*Call registered error callback*/
5674 hcryp->ErrorCallback(hcryp);
5675 #else
5676 /*Call legacy error callback*/
5677 HAL_CRYP_ErrorCallback(hcryp);
5678 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5679 }
5680 /* Clear CCF flag */
5681 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
5682
5683 for (index = 0U; index < 4U; index++)
5684 {
5685 /* Read the output block from the output FIFO and put them in temporary buffer then
5686 get CrypOutBuff from temporary buffer */
5687 temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
5688 }
5689 for (index = 0U; index < lastwordsize; index++)
5690 {
5691 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
5692 hcryp->CrypOutCount++;
5693 }
5694 }
5695 }
5696 #endif /* USE_HAL_SAES_ONLY */
5697 /* Wait until the complete message has been processed */
5698 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
5699 {
5700 /* Disable the CRYP peripheral clock */
5701 __HAL_CRYP_DISABLE(hcryp);
5702
5703 /* Change state */
5704 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5705 hcryp->State = HAL_CRYP_STATE_READY;
5706
5707 /* Process unlocked & return error */
5708 __HAL_UNLOCK(hcryp);
5709 return HAL_ERROR;
5710 }
5711
5712 /* Return function status */
5713 return HAL_OK;
5714 }
5715
5716 /**
5717 * @brief AES CCM encryption/decryption process in interrupt mode
5718 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5719 * the configuration information for CRYP module
5720 * @retval HAL status
5721 */
CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef * hcryp)5722 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
5723 {
5724 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
5725 uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
5726 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5727 uint32_t tickstart;
5728 #endif /* USE_HAL_CRYP_ONLY */
5729 uint32_t loopcounter;
5730 uint32_t lastwordsize;
5731 uint32_t npblb;
5732 uint32_t mode;
5733 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5734 uint32_t headersize_in_bytes;
5735 uint32_t tmp;
5736 const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
5737 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
5738 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
5739 }; /* 8-bit data type */
5740 #endif /* USE_HAL_SAES_ONLY */
5741
5742 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
5743 if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
5744 {
5745 CRYP_PhaseProcessingResume(hcryp);
5746 return HAL_OK;
5747 }
5748 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
5749
5750 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
5751 {
5752 if (hcryp->KeyIVConfig == 1U)
5753 {
5754 /* If the Key and IV configuration has to be done only once
5755 and if it has already been done, skip it */
5756 DoKeyIVConfig = 0U;
5757 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
5758 }
5759 else
5760 {
5761 /* If the Key and IV configuration has to be done only once
5762 and if it has not been done already, do it and set KeyIVConfig
5763 to keep track it won't have to be done again next time */
5764 hcryp->KeyIVConfig = 1U;
5765 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
5766 }
5767 }
5768 else
5769 {
5770 hcryp->SizesSum = hcryp->Size;
5771 }
5772
5773 /* Configure Key, IV and process message (header and payload) */
5774 if (DoKeyIVConfig == 1U)
5775 {
5776 /* Reset CrypHeaderCount */
5777 hcryp->CrypHeaderCount = 0U;
5778
5779 /************ Init phase ************/
5780 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5781 if (IS_CRYP_INSTANCE(hcryp->Instance))
5782 {
5783 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
5784
5785 /* Set the Key */
5786 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
5787 {
5788 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
5789 {
5790 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5791 }
5792 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
5793 {
5794 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
5795 }
5796 }
5797
5798 /* Set the initialization vector (IV) with CTR1 information */
5799 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
5800 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = hcryp->Init.B0[1];
5801 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = hcryp->Init.B0[2];
5802 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
5803
5804 /* Enable the CRYP peripheral */
5805 __HAL_CRYP_ENABLE(hcryp);
5806
5807 /*Write the B0 packet into CRYP_DR*/
5808 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0);
5809 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
5810 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
5811 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
5812
5813 /* Get tick */
5814 tickstart = HAL_GetTick();
5815
5816 /*Wait for the CRYPEN bit to be cleared */
5817 while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
5818 {
5819 /* Check for the Timeout */
5820 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
5821 {
5822 /* Disable the CRYP peripheral clock */
5823 __HAL_CRYP_DISABLE(hcryp);
5824
5825 /* Change state */
5826 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5827 hcryp->State = HAL_CRYP_STATE_READY;
5828
5829 /* Process unlocked */
5830 __HAL_UNLOCK(hcryp);
5831 return HAL_ERROR;
5832 }
5833 }
5834 }
5835 #endif /* USE_HAL_CRYP_ONLY */
5836 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5837 if (IS_SAES_INSTANCE(hcryp->Instance))
5838 {
5839 SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
5840
5841 /* We should re-write Key, in the case where we change key after first operation */
5842 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
5843 {
5844 /* Set the Key */
5845 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5846 }
5847
5848 /* Set the initialization vector (IV) with B0 */
5849 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.B0);
5850 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
5851 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
5852 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
5853
5854 /* Enable the CRYP peripheral */
5855 __HAL_CRYP_ENABLE(hcryp);
5856
5857 /* just wait for hash computation */
5858 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5859 {
5860 /* Disable the CRYP peripheral clock */
5861 __HAL_CRYP_DISABLE(hcryp);
5862
5863 /* Change state */
5864 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5865 hcryp->State = HAL_CRYP_STATE_READY;
5866
5867 /* Process unlocked */
5868 __HAL_UNLOCK(hcryp);
5869 return HAL_ERROR;
5870 }
5871 /* Clear CCF flag */
5872 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
5873 }
5874 #endif /* USE_HAL_SAES_ONLY */
5875
5876 /***************************** Header phase *********************************/
5877
5878 /* Select header phase */
5879 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
5880 if (IS_CRYP_INSTANCE(hcryp->Instance))
5881 {
5882 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5883
5884 /* Enable interrupts */
5885 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
5886
5887 /* Enable CRYP */
5888 __HAL_CRYP_ENABLE(hcryp);
5889 }
5890 #endif /* USE_HAL_CRYP_ONLY */
5891 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
5892 if (IS_SAES_INSTANCE(hcryp->Instance))
5893 {
5894 /* Select header phase */
5895 SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
5896
5897 /* Enable computation complete flag and error interrupts */
5898 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
5899
5900 /* Enable the CRYP peripheral */
5901 __HAL_CRYP_ENABLE(hcryp);
5902
5903 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
5904 if (headersize_in_bytes == 0U) /* Header phase is skipped */
5905 {
5906 /* Set the phase */
5907 hcryp->Phase = CRYP_PHASE_PROCESS;
5908
5909 /* Select payload phase once the header phase is performed */
5910 SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
5911
5912 /* Set to 0 the number of non-valid bytes using NPBLB register*/
5913 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
5914
5915 if (hcryp->Init.Algorithm == CRYP_AES_CCM)
5916 {
5917 /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
5918 hcryp->CrypHeaderCount++;
5919 }
5920 /* Write the payload Input block in the IN FIFO */
5921 if (hcryp->Size == 0U)
5922 {
5923 /* Disable interrupts */
5924 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
5925
5926 /* Change the CRYP state */
5927 hcryp->State = HAL_CRYP_STATE_READY;
5928 __HAL_UNLOCK(hcryp);
5929 }
5930 else if (hcryp->Size >= 16U)
5931 {
5932 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5933 hcryp->CrypInCount++;
5934 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5935 hcryp->CrypInCount++;
5936 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5937 hcryp->CrypInCount++;
5938 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5939 hcryp->CrypInCount++;
5940
5941 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
5942 {
5943 /* Call Input transfer complete callback */
5944 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5945 /*Call registered Input complete callback*/
5946 hcryp->InCpltCallback(hcryp);
5947 #else
5948 /*Call legacy Input complete callback*/
5949 HAL_CRYP_InCpltCallback(hcryp);
5950 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5951 }
5952 }
5953 else /* Size < 4 words : first block is the last block*/
5954 {
5955 /* Compute the number of padding bytes in last block of payload */
5956 npblb = 16U - (uint32_t)hcryp->Size;
5957
5958 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
5959 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
5960 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
5961 {
5962 /* Specify the number of non-valid bytes using NPBLB register*/
5963 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
5964 }
5965
5966 /* Number of valid words (lastwordsize) in last block */
5967 if ((npblb % 4U) == 0U)
5968 {
5969 lastwordsize = (16U - npblb) / 4U;
5970 }
5971 else
5972 {
5973 lastwordsize = ((16U - npblb) / 4U) + 1U;
5974 }
5975
5976 /* Last block optionally pad the data with zeros*/
5977 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5978 {
5979 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5980 hcryp->CrypInCount++;
5981 }
5982 while (loopcounter < 4U)
5983 {
5984 /* Pad the data with zeros to have a complete block */
5985 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
5986 loopcounter++;
5987 }
5988 /* Call Input transfer complete callback */
5989 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5990 /*Call registered Input complete callback*/
5991 hcryp->InCpltCallback(hcryp);
5992 #else
5993 /*Call legacy Input complete callback*/
5994 HAL_CRYP_InCpltCallback(hcryp);
5995 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5996 }
5997 }
5998 /* Enter header data */
5999 /* Check first whether header length is small enough to enter the full header in one shot */
6000 else if (headersize_in_bytes <= 16U)
6001 {
6002 for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
6003 {
6004 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6005 hcryp->CrypHeaderCount++;
6006 }
6007 /* If the header size is a multiple of words */
6008 if ((headersize_in_bytes % 4U) == 0U)
6009 {
6010 /* Pad the data with zeros to have a complete block */
6011 while (loopcounter < 4U)
6012 {
6013 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
6014 loopcounter++;
6015 }
6016 }
6017 else
6018 {
6019 /* Enter last bytes, padded with zeros */
6020 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6021 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6022 ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
6023 hcryp->CrypHeaderCount++;
6024 loopcounter++;
6025 /* Pad the data with zeros to have a complete block */
6026 while (loopcounter < 4U)
6027 {
6028 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
6029 loopcounter++;
6030 }
6031 }
6032 /* Call Input transfer complete callback */
6033 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6034 /*Call registered Input complete callback*/
6035 hcryp->InCpltCallback(hcryp);
6036 #else
6037 /*Call legacy Input complete callback*/
6038 HAL_CRYP_InCpltCallback(hcryp);
6039 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6040 }
6041 else
6042 {
6043 /* Write the first input header block in the Input FIFO,
6044 the following header data will be fed after interrupt occurrence */
6045 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6046 hcryp->CrypHeaderCount++;
6047 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6048 hcryp->CrypHeaderCount++;
6049 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6050 hcryp->CrypHeaderCount++;
6051 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6052 hcryp->CrypHeaderCount++;
6053 } /* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/
6054 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
6055 #endif /* USE_HAL_SAES_ONLY */
6056 } /* end of if (dokeyivconfig == 1U) */
6057 else /* Key and IV have already been configured,
6058 header has already been processed;
6059 only process here message payload */
6060 {
6061 /* Write the payload Input block in the IN FIFO */
6062 if (hcryp->Size == 0U)
6063 {
6064 /* Disable interrupts */
6065 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
6066
6067 /* Change the CRYP state */
6068 hcryp->State = HAL_CRYP_STATE_READY;
6069 __HAL_UNLOCK(hcryp);
6070 }
6071 else if (hcryp->Size >= 16U)
6072 {
6073 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6074 hcryp->CrypInCount++;
6075 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6076 hcryp->CrypInCount++;
6077 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6078 hcryp->CrypInCount++;
6079 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6080 hcryp->CrypInCount++;
6081
6082 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
6083 {
6084 /* Call Input transfer complete callback */
6085 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6086 /*Call registered Input complete callback*/
6087 hcryp->InCpltCallback(hcryp);
6088 #else
6089 /*Call legacy Input complete callback*/
6090 HAL_CRYP_InCpltCallback(hcryp);
6091 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6092 }
6093 }
6094 else /* Size < 4 words : first block is the last block*/
6095 {
6096 /* Compute the number of padding bytes in last block of payload */
6097 npblb = 16U - (uint32_t)hcryp->Size;
6098
6099 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
6100 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
6101 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
6102 {
6103 /* Specify the number of non-valid bytes using NPBLB register*/
6104 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
6105 }
6106
6107 /* Number of valid words (lastwordsize) in last block */
6108 if ((npblb % 4U) == 0U)
6109 {
6110 lastwordsize = (16U - npblb) / 4U;
6111 }
6112 else
6113 {
6114 lastwordsize = ((16U - npblb) / 4U) + 1U;
6115 }
6116
6117 /* Last block optionally pad the data with zeros*/
6118 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
6119 {
6120 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6121 hcryp->CrypInCount++;
6122 }
6123 while (loopcounter < 4U)
6124 {
6125 /* Pad the data with zeros to have a complete block */
6126 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
6127 loopcounter++;
6128 }
6129 /* Call Input transfer complete callback */
6130 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6131 /*Call registered Input complete callback*/
6132 hcryp->InCpltCallback(hcryp);
6133 #else
6134 /*Call legacy Input complete callback*/
6135 HAL_CRYP_InCpltCallback(hcryp);
6136 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6137 }
6138 } /* end of if (DoKeyIVConfig == 1U) */
6139
6140 /* Return function status */
6141 return HAL_OK;
6142 }
6143
6144
6145 /**
6146 * @brief AES CCM encryption/decryption process in DMA mode
6147 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6148 * the configuration information for CRYP module
6149 * @retval HAL status
6150 */
CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef * hcryp)6151 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
6152 {
6153 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
6154 uint32_t index;
6155 uint32_t npblb;
6156 uint32_t lastwordsize = 0U;
6157 uint32_t temp[4]; /* Temporary CrypOutBuff */
6158 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
6159 uint32_t mode;
6160 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
6161 uint32_t tickstart;
6162 #endif /* USE_HAL_CRYP_ONLY */
6163
6164 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
6165 {
6166 if (hcryp->KeyIVConfig == 1U)
6167 {
6168 /* If the Key and IV configuration has to be done only once
6169 and if it has already been done, skip it */
6170 DoKeyIVConfig = 0U;
6171 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
6172 }
6173 else
6174 {
6175 /* If the Key and IV configuration has to be done only once
6176 and if it has not been done already, do it and set KeyIVConfig
6177 to keep track it won't have to be done again next time */
6178 hcryp->KeyIVConfig = 1U;
6179 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
6180 }
6181 }
6182 else
6183 {
6184 hcryp->SizesSum = hcryp->Size;
6185 }
6186
6187 if (DoKeyIVConfig == 1U)
6188 {
6189 /* Reset CrypHeaderCount */
6190 hcryp->CrypHeaderCount = 0U;
6191
6192 /************************** Init phase **************************************/
6193 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
6194 if (IS_CRYP_INSTANCE(hcryp->Instance))
6195 {
6196 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
6197
6198 /* Set the Key */
6199 if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
6200 {
6201 if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
6202 {
6203 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
6204 }
6205 else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
6206 {
6207 ((CRYP_TypeDef *)(hcryp->Instance))->CR &= ~CRYP_KEYMODE_SHARED;
6208 }
6209 }
6210 /* Set the initialization vector (IV) with CTR1 information */
6211 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
6212 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = hcryp->Init.B0[1];
6213 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = hcryp->Init.B0[2];
6214 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
6215
6216 /* Enable the CRYP peripheral */
6217 __HAL_CRYP_ENABLE(hcryp);
6218
6219 /*Write the B0 packet into CRYP_DR*/
6220 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0);
6221 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
6222 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
6223 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
6224
6225 /* Get tick */
6226 tickstart = HAL_GetTick();
6227
6228 /*Wait for the CRYPEN bit to be cleared*/
6229 while ((((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
6230 {
6231 /* Check for the Timeout */
6232 if ((HAL_GetTick() - tickstart) > CRYP_TIMEOUT_GCMCCMINITPHASE)
6233 {
6234 /* Disable the CRYP peripheral clock */
6235 __HAL_CRYP_DISABLE(hcryp);
6236
6237 /* Change state */
6238 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6239 hcryp->State = HAL_CRYP_STATE_READY;
6240
6241 /* Process unlocked */
6242 __HAL_UNLOCK(hcryp);
6243 return HAL_ERROR;
6244 }
6245 }
6246 }
6247 #endif /* USE_HAL_CRYP_ONLY */
6248 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
6249 if (IS_SAES_INSTANCE(hcryp->Instance))
6250 {
6251 SAES_SET_PHASE(hcryp, SAES_PHASE_INIT);
6252
6253 /* We should re-write Key, in the case where we change key after first operation */
6254 if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
6255 {
6256 /* Set the Key */
6257 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
6258 };
6259
6260 /* Set the initialization vector (IV) with B0 */
6261 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(hcryp->Init.B0);
6262 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
6263 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
6264 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
6265
6266 /* Enable the CRYP peripheral */
6267 __HAL_CRYP_ENABLE(hcryp);
6268
6269 /* just wait for hash computation */
6270 if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMINITPHASE) != HAL_OK)
6271 {
6272 /* Disable the CRYP peripheral clock */
6273 __HAL_CRYP_DISABLE(hcryp);
6274
6275 /* Change state */
6276 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6277 hcryp->State = HAL_CRYP_STATE_READY;
6278
6279 /* Process unlocked */
6280 __HAL_UNLOCK(hcryp);
6281 return HAL_ERROR;
6282 }
6283 /* Clear CCF flag */
6284 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
6285 }
6286 #endif /* USE_HAL_SAES_ONLY */
6287
6288 /********************* Header phase *****************************************/
6289
6290 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
6291 {
6292 return HAL_ERROR;
6293 }
6294
6295 /******************** Payload phase *****************************************/
6296
6297 /* Set the phase */
6298 hcryp->Phase = CRYP_PHASE_PROCESS;
6299
6300 /* Select payload phase once the header phase is performed */
6301 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
6302 if (IS_CRYP_INSTANCE(hcryp->Instance))
6303 {
6304 /* Disable the CRYP peripheral */
6305 __HAL_CRYP_DISABLE(hcryp);
6306
6307 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
6308
6309 /* Set to 0 the number of non-valid bytes using NPBLB register*/
6310 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
6311
6312 /* Enable the CRYP peripheral */
6313 __HAL_CRYP_ENABLE(hcryp);
6314 }
6315 #endif /* USE_HAL_CRYP_ONLY */
6316 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
6317 if (IS_SAES_INSTANCE(hcryp->Instance))
6318 {
6319 SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
6320
6321 /* Set to 0 the number of non-valid bytes using NPBLB register*/
6322 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
6323 }
6324 #endif /* USE_CRYP_INSTANCE */
6325 } /* if (DoKeyIVConfig == 1U) */
6326
6327 if (hcryp->Size == 0U)
6328 {
6329 /* Process unLocked */
6330 __HAL_UNLOCK(hcryp);
6331
6332 /* Change the CRYP state and phase */
6333 hcryp->State = HAL_CRYP_STATE_READY;
6334 }
6335 else if (hcryp->Size >= 16U)
6336 {
6337 wordsize = wordsize - (wordsize % 4U);
6338 /* DMA transfer */
6339 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t) wordsize * 4U,
6340 (uint32_t)(hcryp->pCrypOutBuffPtr));
6341 }
6342 else /* length of input data is < 16U */
6343 {
6344 /* Compute the number of padding bytes in last block of payload */
6345 npblb = 16U - (uint32_t)(hcryp->Size);
6346
6347 /* Set Npblb in case of AES CCM payload decryption to get right tag*/
6348 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
6349 if (IS_CRYP_INSTANCE(hcryp->Instance))
6350 {
6351 mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
6352
6353 if (mode == CRYP_OPERATINGMODE_DECRYPT)
6354 {
6355 /* Specify the number of non-valid bytes using NPBLB register*/
6356 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
6357 }
6358
6359 /* Enable CRYP to start the final phase */
6360 __HAL_CRYP_ENABLE(hcryp);
6361
6362 /* Number of valid words (lastwordsize) in last block */
6363 if ((npblb % 4U) == 0U)
6364 {
6365 lastwordsize = (16U - npblb) / 4U;
6366 }
6367 else
6368 {
6369 lastwordsize = ((16U - npblb) / 4U) + 1U;
6370 }
6371
6372 /* Write the last input block in the IN FIFO */
6373 for (index = 0U; index < lastwordsize; index ++)
6374 {
6375 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6376 hcryp->CrypInCount++;
6377 }
6378
6379 /* Pad the data with zeros to have a complete block */
6380 while (index < 4U)
6381 {
6382 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
6383 index++;
6384 }
6385
6386 /* Wait for OFNE flag to be raised */
6387 if (CRYP_WaitOnOFNEFlag(hcryp, CRYP_TIMEOUT_GCMCCMINITPHASE) != HAL_OK)
6388 {
6389 /* Disable the CRYP peripheral clock */
6390 __HAL_CRYP_DISABLE(hcryp);
6391
6392 /* Change state & update error code */
6393 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6394 hcryp->State = HAL_CRYP_STATE_READY;
6395
6396 /* Process unlocked */
6397 __HAL_UNLOCK(hcryp);
6398 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6399 /*Call registered error callback*/
6400 hcryp->ErrorCallback(hcryp);
6401 #else
6402 /*Call legacy error callback*/
6403 HAL_CRYP_ErrorCallback(hcryp);
6404 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6405 }
6406
6407 /*Read the output block from the output FIFO */
6408 for (index = 0U; index < 4U; index++)
6409 {
6410 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
6411 temporary buffer */
6412 temp[index] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
6413 }
6414 } /* SAES peripheral */
6415 #endif /* USE_HAL_CRYP_ONLY */
6416 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
6417 if (IS_SAES_INSTANCE(hcryp->Instance))
6418 {
6419 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
6420
6421 if (mode == CRYP_OPERATINGMODE_DECRYPT)
6422 {
6423 /* Specify the number of non-valid bytes using NPBLB register*/
6424 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20);
6425 }
6426
6427 /* Number of valid words (lastwordsize) in last block */
6428 if ((npblb % 4U) == 0U)
6429 {
6430 lastwordsize = (16U - npblb) / 4U;
6431 }
6432 else
6433 {
6434 lastwordsize = ((16U - npblb) / 4U) + 1U;
6435 }
6436
6437 /* Write the last input block in the IN FIFO */
6438 for (index = 0U; index < lastwordsize; index ++)
6439 {
6440 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6441 hcryp->CrypInCount++;
6442 }
6443
6444 /* Pad the data with zeros to have a complete block */
6445 while (index < 4U)
6446 {
6447 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0U;
6448 index++;
6449 }
6450 /* just wait for hash computation */
6451 if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMINITPHASE) != HAL_OK)
6452 {
6453 /* Disable the CRYP peripheral clock */
6454 __HAL_CRYP_DISABLE(hcryp);
6455
6456 /* Change state & update error code */
6457 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6458 hcryp->State = HAL_CRYP_STATE_READY;
6459
6460 /* Process unlocked */
6461 __HAL_UNLOCK(hcryp);
6462 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6463 /*Call registered error callback*/
6464 hcryp->ErrorCallback(hcryp);
6465 #else
6466 /*Call legacy error callback*/
6467 HAL_CRYP_ErrorCallback(hcryp);
6468 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6469 }
6470 /* Clear CCF flag */
6471 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
6472
6473 /*Read the output block from the output FIFO */
6474 for (index = 0U; index < 4U; index++)
6475 {
6476 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from
6477 temporary buffer */
6478 temp[index] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
6479 }
6480 }
6481 #endif /* USE_HAL_SAES_ONLY */
6482
6483 for (index = 0; index < lastwordsize; index++)
6484 {
6485 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
6486 hcryp->CrypOutCount++;
6487 }
6488
6489 /* Change the CRYP state to ready */
6490 hcryp->State = HAL_CRYP_STATE_READY;
6491
6492 /* Process unlocked */
6493 __HAL_UNLOCK(hcryp);
6494 }
6495
6496 /* Return function status */
6497 return HAL_OK;
6498 }
6499
6500 /**
6501 * @brief Sets the payload phase in interrupt mode
6502 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6503 * the configuration information for CRYP module
6504 * @retval state
6505 */
CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef * hcryp)6506 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
6507 {
6508 uint32_t loopcounter;
6509 uint32_t temp[4]; /* Temporary CrypOutBuff */
6510 uint32_t lastwordsize;
6511 uint32_t npblb;
6512 uint32_t mode;
6513 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
6514 uint8_t negative = 0U;
6515 #endif /* USE_HAL_CRYP_ONLY */
6516 uint32_t i;
6517
6518 /***************************** Payload phase *******************************/
6519 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
6520 if (IS_CRYP_INSTANCE(hcryp->Instance))
6521 {
6522 if ((hcryp->Size / 4U) < hcryp->CrypInCount)
6523 {
6524 negative = 1U;
6525 }
6526
6527 if (hcryp->Size == 0U)
6528 {
6529 /* Disable interrupts */
6530 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
6531
6532 /* Process unlocked */
6533 __HAL_UNLOCK(hcryp);
6534
6535 /* Change the CRYP state */
6536 hcryp->State = HAL_CRYP_STATE_READY;
6537 }
6538
6539 else if ((((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) &&
6540 (negative == 0U))
6541 {
6542 if ((((CRYP_TypeDef *)(hcryp->Instance))->IMSCR & CRYP_IMSCR_INIM) != 0x0U)
6543 {
6544
6545 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
6546 /* If suspension flag has been raised, suspend processing
6547 only if not already at the end of the payload */
6548 if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
6549 {
6550 /* Wait until both the IN and the OUT FIFOs are empty (IFEM=1 and OFNE=0 in the
6551 CRYP_SR) and the BUSY bit is cleared */
6552 while (((((CRYP_TypeDef *)(hcryp->Instance))->SR) & (CRYP_SR_IFEM | CRYP_SR_OFNE | \
6553 CRYP_SR_BUSY)) != CRYP_SR_IFEM)
6554 {
6555 /* Nothing to do */
6556 }
6557
6558 /* Disable interrupts */
6559 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
6560
6561 /* Disable CRYP */
6562 __HAL_CRYP_DISABLE(hcryp);
6563
6564 /* reset SuspendRequest */
6565 hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
6566
6567 /* Change the CRYP state */
6568 hcryp->State = HAL_CRYP_STATE_SUSPENDED;
6569
6570 /* Mark that the payload phase is suspended */
6571 hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
6572
6573 /* Process Unlocked */
6574 __HAL_UNLOCK(hcryp);
6575 }
6576 else
6577 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
6578 {
6579 /* Write the input block in the IN FIFO */
6580 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6581 hcryp->CrypInCount++;
6582 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6583 hcryp->CrypInCount++;
6584 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6585 hcryp->CrypInCount++;
6586 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6587 hcryp->CrypInCount++;
6588 if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U))
6589 {
6590 /* Disable interrupts */
6591 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
6592 /* Call the input data transfer complete callback */
6593 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6594 /*Call registered Input complete callback*/
6595 hcryp->InCpltCallback(hcryp);
6596 #else
6597 /*Call legacy Input complete callback*/
6598 HAL_CRYP_InCpltCallback(hcryp);
6599 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6600 }
6601
6602 if (hcryp->CrypOutCount < (hcryp->Size / 4U))
6603 {
6604 if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U)
6605 {
6606 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from
6607 temporary buffer */
6608 for (i = 0U; i < 4U; i++)
6609 {
6610 temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
6611 }
6612 i = 0U;
6613 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
6614 {
6615 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
6616 hcryp->CrypOutCount++;
6617 i++;
6618 }
6619 if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
6620 {
6621 /* Disable interrupts */
6622 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
6623
6624 /* Change the CRYP state */
6625 hcryp->State = HAL_CRYP_STATE_READY;
6626
6627 /* Disable CRYP */
6628 __HAL_CRYP_DISABLE(hcryp);
6629
6630 /* Process unlocked */
6631 __HAL_UNLOCK(hcryp);
6632
6633 /* Call output transfer complete callback */
6634 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6635 /*Call registered Output complete callback*/
6636 hcryp->OutCpltCallback(hcryp);
6637 #else
6638 /*Call legacy Output complete callback*/
6639 HAL_CRYP_OutCpltCallback(hcryp);
6640 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6641 }
6642 }
6643 }
6644 } /* if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) */
6645 }
6646 }
6647 else if ((hcryp->Size % 16U) != 0U)
6648 {
6649 /* Set padding only in case of input fifo interrupt */
6650 if ((((CRYP_TypeDef *)(hcryp->Instance))->IMSCR & CRYP_IMSCR_INIM) != 0x0U)
6651 {
6652 /* Compute the number of padding bytes in last block of payload */
6653 npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
6654
6655 mode = ((CRYP_TypeDef *)(hcryp->Instance))->CR & CRYP_CR_ALGODIR;
6656 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
6657 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
6658 {
6659 /* Disable the CRYP */
6660 __HAL_CRYP_DISABLE(hcryp);
6661
6662 /* Specify the number of non-valid bytes using NPBLB register*/
6663 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, npblb << 20);
6664
6665 /* Enable CRYP to start the final phase */
6666 __HAL_CRYP_ENABLE(hcryp);
6667 }
6668
6669
6670 /* Number of valid words (lastwordsize) in last block */
6671 if ((npblb % 4U) == 0U)
6672 {
6673 lastwordsize = (16U - npblb) / 4U;
6674 }
6675 else
6676 {
6677 lastwordsize = ((16U - npblb) / 4U) + 1U;
6678 }
6679
6680 /* Write the last input block in the IN FIFO */
6681 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
6682 {
6683 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6684 hcryp->CrypInCount++;
6685 }
6686 /* Pad the data with zeros to have a complete block */
6687 while (loopcounter < 4U)
6688 {
6689 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0U;
6690 loopcounter++;
6691 }
6692
6693 /* Disable the input FIFO Interrupt */
6694 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
6695 }
6696
6697 /*Read the output block from the output FIFO */
6698 if ((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U)
6699 {
6700 for (i = 0U; i < 4U; i++)
6701 {
6702 temp[i] = ((CRYP_TypeDef *)(hcryp->Instance))->DOUT;
6703 }
6704 if (((hcryp->Size) / 4U) == 0U)
6705 {
6706 for (i = 0U; (uint16_t)i < ((hcryp->Size) % 4U); i++)
6707 {
6708 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
6709 hcryp->CrypOutCount++;
6710 }
6711 }
6712 i = 0U;
6713 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
6714 {
6715 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
6716 hcryp->CrypOutCount++;
6717 i++;
6718 }
6719 }
6720
6721 /* Disable the output FIFO Interrupt */
6722 if (hcryp->CrypOutCount >= ((hcryp->Size) / 4U))
6723 {
6724 /* Disable interrupts */
6725 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);
6726
6727 /* Change the CRYP peripheral state */
6728 hcryp->State = HAL_CRYP_STATE_READY;
6729
6730 /* Process unlocked */
6731 __HAL_UNLOCK(hcryp);
6732
6733 /* Call output transfer complete callback */
6734 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6735 /*Call registered Output complete callback*/
6736 hcryp->OutCpltCallback(hcryp);
6737 #else
6738 /*Call legacy Output complete callback*/
6739 HAL_CRYP_OutCpltCallback(hcryp);
6740 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6741 }
6742 }
6743 else
6744 {
6745 /* Nothing to do */
6746 }
6747 }
6748 #endif /* USE_HAL_CRYP_ONLY */
6749 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
6750 if (IS_SAES_INSTANCE(hcryp->Instance))
6751 {
6752 uint32_t incount;
6753 uint32_t outcount;
6754
6755 /* Read the output block from the output FIFO and put them in temporary buffer then
6756 get CrypOutBuff from temporary buffer*/
6757 for (i = 0U; i < 4U; i++)
6758 {
6759 temp[i] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR;
6760 }
6761 i = 0U;
6762 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
6763 {
6764 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
6765 hcryp->CrypOutCount++;
6766 i++;
6767 }
6768 incount = hcryp->CrypInCount;
6769 outcount = hcryp->CrypOutCount;
6770 if ((outcount >= ((uint32_t)(hcryp->Size) / 4U)) && ((incount * 4U) >= (uint32_t)(hcryp->Size)))
6771 {
6772
6773 /* When in CCM with Key and IV configuration skipped, don't disable interruptions */
6774 if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U)))
6775 {
6776 /* Disable computation complete flag and errors interrupts */
6777 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
6778 }
6779
6780 /* Change the CRYP state */
6781 hcryp->State = HAL_CRYP_STATE_READY;
6782 __HAL_UNLOCK(hcryp);
6783
6784 /* Call output transfer complete callback */
6785 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6786 /*Call registered Output complete callback*/
6787 hcryp->OutCpltCallback(hcryp);
6788 #else
6789 /*Call legacy Output complete callback*/
6790 HAL_CRYP_OutCpltCallback(hcryp);
6791 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6792 }
6793
6794 else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
6795 {
6796
6797 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
6798 /* If suspension flag has been raised, suspend processing
6799 only if not already at the end of the payload */
6800 if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
6801 {
6802 /* Clear CCF Flag */
6803 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
6804
6805 /* reset SuspendRequest */
6806 hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
6807 /* Disable Computation Complete Flag and Errors Interrupts */
6808 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
6809 /* Change the CRYP state */
6810 hcryp->State = HAL_CRYP_STATE_SUSPENDED;
6811 /* Mark that the payload phase is suspended */
6812 hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
6813 __HAL_UNLOCK(hcryp);
6814 }
6815 else
6816 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
6817 {
6818 /* Write the input block in the IN FIFO */
6819 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6820 hcryp->CrypInCount++;
6821 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6822 hcryp->CrypInCount++;
6823 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6824 hcryp->CrypInCount++;
6825 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6826 hcryp->CrypInCount++;
6827 if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM))
6828 {
6829 /* Call output transfer complete callback */
6830 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6831 /*Call registered Input complete callback*/
6832 hcryp->InCpltCallback(hcryp);
6833 #else
6834 /*Call legacy Input complete callback*/
6835 HAL_CRYP_InCpltCallback(hcryp);
6836 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6837 }
6838 }
6839 }
6840 else /* Last block of payload < 128bit*/
6841 {
6842 /* Compute the number of padding bytes in last block of payload */
6843 npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
6844
6845 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
6846 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
6847 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
6848 {
6849 /* Specify the number of non-valid bytes using NPBLB register*/
6850 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20);
6851 }
6852
6853 /* Number of valid words (lastwordsize) in last block */
6854 if ((npblb % 4U) == 0U)
6855 {
6856 lastwordsize = (16U - npblb) / 4U;
6857 }
6858 else
6859 {
6860 lastwordsize = ((16U - npblb) / 4U) + 1U;
6861 }
6862
6863 /* Last block optionally pad the data with zeros*/
6864 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
6865 {
6866 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6867 hcryp->CrypInCount++;
6868 }
6869 while (loopcounter < 4U)
6870 {
6871 /* pad the data with zeros to have a complete block */
6872 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
6873 loopcounter++;
6874 }
6875 }
6876 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
6877 #endif /* USE_HAL_SAES_ONLY */
6878 }
6879
6880
6881 /**
6882 * @brief Sets the header phase in polling mode
6883 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6884 * the configuration information for CRYP module(Header & HeaderSize)
6885 * @param Timeout: Timeout value
6886 * @retval state
6887 */
CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)6888 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6889 {
6890 uint32_t loopcounter;
6891 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
6892 uint32_t headersize_in_bytes;
6893 uint32_t tmp;
6894 const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
6895 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
6896 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
6897 }; /* 8-bit data type */
6898 #endif /* USE_HAL_SAES_ONLY */
6899
6900 /***************************** Header phase for GCM/GMAC or CCM *********************************/
6901
6902 /* Select header phase */
6903 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
6904 if (IS_CRYP_INSTANCE(hcryp->Instance))
6905 {
6906 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
6907 /* Enable the CRYP peripheral */
6908 __HAL_CRYP_ENABLE(hcryp);
6909
6910 if ((hcryp->Init.HeaderSize % 4U) == 0U)
6911 {
6912 /* HeaderSize %4, no padding */
6913 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
6914 {
6915 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6916 hcryp->CrypHeaderCount++ ;
6917 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6918 hcryp->CrypHeaderCount++ ;
6919 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6920 hcryp->CrypHeaderCount++ ;
6921 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6922 hcryp->CrypHeaderCount++ ;
6923
6924 /* Wait for IFEM to be raised */
6925 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
6926 {
6927 /* Disable the CRYP peripheral clock */
6928 __HAL_CRYP_DISABLE(hcryp);
6929
6930 /* Change state */
6931 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6932 hcryp->State = HAL_CRYP_STATE_READY;
6933
6934 /* Process unlocked */
6935 __HAL_UNLOCK(hcryp);
6936 return HAL_ERROR;
6937 }
6938 }
6939 }
6940 else
6941 {
6942 /*Write header block in the IN FIFO without last block */
6943 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U)));
6944 loopcounter += 4U)
6945 {
6946 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6947 hcryp->CrypHeaderCount++ ;
6948 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6949 hcryp->CrypHeaderCount++ ;
6950 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6951 hcryp->CrypHeaderCount++ ;
6952 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6953 hcryp->CrypHeaderCount++ ;
6954
6955 /* Wait for IFEM to be raised */
6956 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
6957 {
6958 /* Disable the CRYP peripheral clock */
6959 __HAL_CRYP_DISABLE(hcryp);
6960
6961 /* Change state */
6962 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6963 hcryp->State = HAL_CRYP_STATE_READY;
6964
6965 /* Process unlocked */
6966 __HAL_UNLOCK(hcryp);
6967 return HAL_ERROR;
6968 }
6969 }
6970 /* Last block optionally pad the data with zeros*/
6971 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
6972 {
6973 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6974 hcryp->CrypHeaderCount++ ;
6975 }
6976 while (loopcounter < 4U)
6977 {
6978 /* pad the data with zeros to have a complete block */
6979 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0x0U;
6980 loopcounter++;
6981 }
6982 /* Wait for IFEM to be raised */
6983 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
6984 {
6985 /* Disable the CRYP peripheral clock */
6986 __HAL_CRYP_DISABLE(hcryp);
6987
6988 /* Change state */
6989 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6990 hcryp->State = HAL_CRYP_STATE_READY;
6991
6992 /* Process unlocked */
6993 __HAL_UNLOCK(hcryp);
6994 return HAL_ERROR;
6995 }
6996 }
6997 }
6998 #endif /* USE_HAL_CRYP_ONLY */
6999 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7000 if (IS_SAES_INSTANCE(hcryp->Instance))
7001 {
7002 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
7003 {
7004 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
7005 }
7006 else
7007 {
7008 headersize_in_bytes = hcryp->Init.HeaderSize;
7009 }
7010
7011 /* Set Header phase */
7012 SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
7013
7014 /* Enable the CRYP peripheral */
7015 __HAL_CRYP_ENABLE(hcryp);
7016
7017 if ((headersize_in_bytes % 16U) == 0U)
7018 {
7019 /* HeaderSize %4, no padding */
7020 for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
7021 {
7022 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7023 hcryp->CrypHeaderCount++ ;
7024 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7025 hcryp->CrypHeaderCount++ ;
7026 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7027 hcryp->CrypHeaderCount++ ;
7028 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7029 hcryp->CrypHeaderCount++ ;
7030
7031 /* Wait for CCF to be raised */
7032 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
7033 {
7034 /* Disable the CRYP peripheral clock */
7035 __HAL_CRYP_DISABLE(hcryp);
7036
7037 /* Change state */
7038 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7039 hcryp->State = HAL_CRYP_STATE_READY;
7040
7041 /* Process unlocked */
7042 __HAL_UNLOCK(hcryp);
7043 return HAL_ERROR;
7044 }
7045 /* Clear CCF flag */
7046 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
7047 }
7048 }
7049 else
7050 {
7051 /*Write header block in the IN FIFO without last block */
7052 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
7053 {
7054 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7055 hcryp->CrypHeaderCount++ ;
7056 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7057 hcryp->CrypHeaderCount++ ;
7058 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7059 hcryp->CrypHeaderCount++ ;
7060 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7061 hcryp->CrypHeaderCount++ ;
7062
7063 /* Wait for CCF to be raised */
7064 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
7065 {
7066 /* Disable the CRYP peripheral clock */
7067 __HAL_CRYP_DISABLE(hcryp);
7068
7069 /* Change state */
7070 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7071 hcryp->State = HAL_CRYP_STATE_READY;
7072
7073 /* Process unlocked */
7074 __HAL_UNLOCK(hcryp);
7075 return HAL_ERROR;
7076 }
7077 /* Clear CCF flag */
7078 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
7079 }
7080 /* Write last complete words */
7081 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
7082 {
7083 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7084 hcryp->CrypHeaderCount++ ;
7085 }
7086 /* If the header size is a multiple of words */
7087 if ((headersize_in_bytes % 4U) == 0U)
7088 {
7089 /* Pad the data with zeros to have a complete block */
7090 while (loopcounter < 4U)
7091 {
7092 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
7093 loopcounter++;
7094 }
7095 }
7096 else
7097 {
7098 /* Enter last bytes, padded with zeros */
7099 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7100 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
7101 ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
7102 loopcounter++;
7103 /* Pad the data with zeros to have a complete block */
7104 while (loopcounter < 4U)
7105 {
7106 /* pad the data with zeros to have a complete block */
7107 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
7108 loopcounter++;
7109 }
7110 }
7111
7112 /* Wait for CCF to be raised */
7113 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
7114 {
7115 /* Disable the CRYP peripheral clock */
7116 __HAL_CRYP_DISABLE(hcryp);
7117
7118 /* Change state */
7119 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7120 hcryp->State = HAL_CRYP_STATE_READY;
7121
7122 /* Process unlocked */
7123 __HAL_UNLOCK(hcryp);
7124 return HAL_ERROR;
7125 }
7126 /* Clear CCF flag */
7127 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
7128 }
7129 }
7130 #endif /* USE_HAL_SAES_ONLY */
7131 /* Wait until the complete message has been processed */
7132 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
7133 {
7134 /* Disable the CRYP peripheral clock */
7135 __HAL_CRYP_DISABLE(hcryp);
7136
7137 /* Change state */
7138 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7139 hcryp->State = HAL_CRYP_STATE_READY;
7140
7141 /* Process unlocked & return error */
7142 __HAL_UNLOCK(hcryp);
7143 return HAL_ERROR;
7144 }
7145 /* Return function status */
7146 return HAL_OK;
7147 }
7148
7149
7150 /**
7151 * @brief Sets the header phase when using DMA in process
7152 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7153 * the configuration information for CRYP module(Header & HeaderSize)
7154 * @retval None
7155 */
CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef * hcryp)7156 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
7157 {
7158 uint32_t loopcounter;
7159 uint32_t Timeout = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
7160 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7161 uint32_t headersize_in_bytes;
7162 uint32_t tmp;
7163 const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
7164 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
7165 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
7166 }; /* 8-bit data type */
7167 #endif /* USE_HAL_SAES_ONLY */
7168
7169 /***************************** Header phase for GCM/GMAC or CCM *********************************/
7170 if ((hcryp->Init.HeaderSize != 0U))
7171 {
7172 /* Select header phase */
7173 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7174 if (IS_CRYP_INSTANCE(hcryp->Instance))
7175 {
7176 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
7177 /* Enable the CRYP peripheral */
7178 __HAL_CRYP_ENABLE(hcryp);
7179
7180 if ((hcryp->Init.HeaderSize % 4U) == 0U)
7181 {
7182 /* HeaderSize %4, no padding */
7183 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
7184 {
7185 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7186 hcryp->CrypHeaderCount++ ;
7187 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7188 hcryp->CrypHeaderCount++ ;
7189 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7190 hcryp->CrypHeaderCount++ ;
7191 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7192 hcryp->CrypHeaderCount++ ;
7193
7194 /* Wait for IFEM to be raised */
7195 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
7196 {
7197 /* Disable the CRYP peripheral clock */
7198 __HAL_CRYP_DISABLE(hcryp);
7199
7200 /* Change state */
7201 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7202 hcryp->State = HAL_CRYP_STATE_READY;
7203
7204 /* Process unlocked */
7205 __HAL_UNLOCK(hcryp);
7206 return HAL_ERROR;
7207 }
7208 }
7209 }
7210 else
7211 {
7212 /*Write header block in the IN FIFO without last block */
7213 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U)));
7214 loopcounter += 4U)
7215 {
7216 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7217 hcryp->CrypHeaderCount++ ;
7218 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7219 hcryp->CrypHeaderCount++ ;
7220 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7221 hcryp->CrypHeaderCount++ ;
7222 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7223 hcryp->CrypHeaderCount++ ;
7224
7225 /* Wait for IFEM to be raised */
7226 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
7227 {
7228 /* Disable the CRYP peripheral clock */
7229 __HAL_CRYP_DISABLE(hcryp);
7230
7231 /* Change state */
7232 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7233 hcryp->State = HAL_CRYP_STATE_READY;
7234
7235 /* Process unlocked */
7236 __HAL_UNLOCK(hcryp);
7237 return HAL_ERROR;
7238 }
7239 }
7240 /* Last block optionally pad the data with zeros*/
7241 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
7242 {
7243 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7244 hcryp->CrypHeaderCount++ ;
7245 }
7246 while (loopcounter < 4U)
7247 {
7248 /* Pad the data with zeros to have a complete block */
7249 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0x0U;
7250 loopcounter++;
7251 }
7252
7253 /* Wait for IFEM to be raised */
7254 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
7255 {
7256 /* Disable the CRYP peripheral clock */
7257 __HAL_CRYP_DISABLE(hcryp);
7258
7259 /* Change state */
7260 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7261 hcryp->State = HAL_CRYP_STATE_READY;
7262
7263 /* Process unlocked */
7264 __HAL_UNLOCK(hcryp);
7265 return HAL_ERROR;
7266 }
7267 }
7268 }
7269 #endif /* USE_HAL_CRYP_ONLY */
7270 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7271 if (IS_SAES_INSTANCE(hcryp->Instance))
7272 {
7273 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
7274 {
7275 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
7276 }
7277 else
7278 {
7279 headersize_in_bytes = hcryp->Init.HeaderSize;
7280 }
7281 /* Set header phase*/
7282 SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
7283
7284 /* Enable the CRYP peripheral */
7285 __HAL_CRYP_ENABLE(hcryp);
7286
7287 if ((headersize_in_bytes % 16U) == 0U)
7288 {
7289 /* HeaderSize %4, no padding */
7290 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
7291 {
7292 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7293 hcryp->CrypHeaderCount++ ;
7294 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7295 hcryp->CrypHeaderCount++ ;
7296 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7297 hcryp->CrypHeaderCount++ ;
7298 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7299 hcryp->CrypHeaderCount++ ;
7300
7301 /* Wait for CCF to be raised */
7302 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
7303 {
7304 /* Disable the CRYP peripheral clock */
7305 __HAL_CRYP_DISABLE(hcryp);
7306
7307 /* Change state */
7308 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7309 hcryp->State = HAL_CRYP_STATE_READY;
7310
7311 /* Process unlocked */
7312 __HAL_UNLOCK(hcryp);
7313 return HAL_ERROR;
7314 }
7315 }
7316 }
7317 else
7318 {
7319 /*Write header block in the IN FIFO without last block */
7320 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
7321 {
7322 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7323 hcryp->CrypHeaderCount++ ;
7324 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7325 hcryp->CrypHeaderCount++ ;
7326 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7327 hcryp->CrypHeaderCount++ ;
7328 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7329 hcryp->CrypHeaderCount++ ;
7330
7331 /* Wait for CCF to be raised */
7332 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
7333 {
7334 /* Disable the CRYP peripheral clock */
7335 __HAL_CRYP_DISABLE(hcryp);
7336
7337 /* Change state */
7338 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7339 hcryp->State = HAL_CRYP_STATE_READY;
7340
7341 /* Process unlocked */
7342 __HAL_UNLOCK(hcryp);
7343 return HAL_ERROR;
7344 }
7345 }
7346 /* Write last complete words */
7347 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
7348 {
7349 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7350 hcryp->CrypHeaderCount++;
7351 }
7352 /* If the header size is a multiple of words */
7353 if ((headersize_in_bytes % 4U) == 0U)
7354 {
7355 /* Pad the data with zeros to have a complete block */
7356 while (loopcounter < 4U)
7357 {
7358 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
7359 loopcounter++;
7360 }
7361 }
7362 else
7363 {
7364 /* Enter last bytes, padded with zeros */
7365 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7366 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
7367 ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
7368 loopcounter++;
7369 /* Pad the data with zeros to have a complete block */
7370 while (loopcounter < 4U)
7371 {
7372 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
7373 loopcounter++;
7374 }
7375 }
7376
7377 /* Wait for CCF to be raised */
7378 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
7379 {
7380 /* Disable the CRYP peripheral clock */
7381 __HAL_CRYP_DISABLE(hcryp);
7382
7383 /* Change state */
7384 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7385 hcryp->State = HAL_CRYP_STATE_READY;
7386
7387 /* Process unlocked */
7388 __HAL_UNLOCK(hcryp);
7389 return HAL_ERROR;
7390 }
7391 }
7392 }
7393 #endif /* USE_HAL_SAES_ONLY */
7394 /* Wait until the complete message has been processed */
7395 Timeout = CRYP_GENERAL_TIMEOUT;
7396 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
7397 {
7398 /* Disable the CRYP peripheral clock */
7399 __HAL_CRYP_DISABLE(hcryp);
7400
7401 /* Change state */
7402 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
7403 hcryp->State = HAL_CRYP_STATE_READY;
7404
7405 /* Process unlocked */
7406 __HAL_UNLOCK(hcryp);
7407 return HAL_ERROR;
7408 }
7409 }
7410
7411 /* Return function status */
7412 return HAL_OK;
7413 }
7414
7415 /**
7416 * @brief Sets the header phase in interrupt mode
7417 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7418 * the configuration information for CRYP module(Header & HeaderSize)
7419 * @retval None
7420 */
CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef * hcryp)7421 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
7422 {
7423 uint32_t loopcounter;
7424 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7425 uint32_t lastwordsize;
7426 uint32_t npblb;
7427 uint32_t mode;
7428 uint32_t headersize_in_bytes;
7429 uint32_t tmp;
7430 const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
7431 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
7432 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
7433 }; /* 8-bit data type */
7434 #endif /* USE_HAL_SAES_ONLY */
7435
7436 /***************************** Header phase *********************************/
7437 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7438 if (IS_CRYP_INSTANCE(hcryp->Instance))
7439 {
7440 if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
7441 {
7442 /* Disable interrupts */
7443 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
7444
7445 /* Disable the CRYP peripheral */
7446 __HAL_CRYP_DISABLE(hcryp);
7447
7448 /* Set to 0 the number of non-valid bytes using NPBLB register*/
7449 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, CRYP_CR_NPBLB, 0U);
7450
7451 /* Set the phase */
7452 hcryp->Phase = CRYP_PHASE_PROCESS;
7453
7454 /* Select payload phase once the header phase is performed */
7455 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
7456
7457 /* Enable Interrupts */
7458 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
7459
7460 /* Enable the CRYP peripheral */
7461 __HAL_CRYP_ENABLE(hcryp);
7462 }
7463 else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
7464
7465 {
7466 /* HeaderSize %4, no padding */
7467 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7468 hcryp->CrypHeaderCount++ ;
7469 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7470 hcryp->CrypHeaderCount++ ;
7471 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7472 hcryp->CrypHeaderCount++ ;
7473 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7474 hcryp->CrypHeaderCount++ ;
7475 }
7476 else
7477 {
7478 /* Last block optionally pad the data with zeros*/
7479 for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
7480 {
7481 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7482 hcryp->CrypHeaderCount++ ;
7483 }
7484 while (loopcounter < 4U)
7485 {
7486 /* Pad the data with zeros to have a complete block */
7487 ((CRYP_TypeDef *)(hcryp->Instance))->DIN = 0x0U;
7488 loopcounter++ ;
7489 }
7490 }
7491 }
7492 #endif /* USE_HAL_CRYP_ONLY */
7493 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7494 if (IS_SAES_INSTANCE(hcryp->Instance))
7495 {
7496 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
7497 {
7498 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
7499 }
7500 else
7501 {
7502 headersize_in_bytes = hcryp->Init.HeaderSize;
7503 }
7504 /***************************** Header phase *********************************/
7505 /* Test whether or not the header phase is over.
7506 If the test below is true, move to payload phase */
7507 if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
7508 {
7509 /* Set the phase */
7510 hcryp->Phase = CRYP_PHASE_PROCESS;
7511 /* Select payload phase */
7512 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_GCMPH, SAES_PHASE_PAYLOAD);
7513 /* Set to 0 the number of non-valid bytes using NPBLB register*/
7514 MODIFY_REG(((SAES_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, 0U);
7515
7516 if (hcryp->Init.Algorithm == CRYP_AES_CCM)
7517 {
7518 /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
7519 hcryp->CrypHeaderCount++;
7520 }
7521 /* Write the payload Input block in the IN FIFO */
7522 if (hcryp->Size == 0U)
7523 {
7524 /* Disable interrupts */
7525 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
7526
7527 /* Change the CRYP state */
7528 hcryp->State = HAL_CRYP_STATE_READY;
7529 __HAL_UNLOCK(hcryp);
7530 }
7531 else if (hcryp->Size >= 16U)
7532 {
7533 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
7534 hcryp->CrypInCount++;
7535 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
7536 hcryp->CrypInCount++;
7537 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
7538 hcryp->CrypInCount++;
7539 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
7540 hcryp->CrypInCount++;
7541
7542 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
7543 {
7544 /* Call the input data transfer complete callback */
7545 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
7546 /*Call registered Input complete callback*/
7547 hcryp->InCpltCallback(hcryp);
7548 #else
7549 /*Call legacy Input complete callback*/
7550 HAL_CRYP_InCpltCallback(hcryp);
7551 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
7552 }
7553 }
7554 else /* Size < 4 words : first block is the last block*/
7555 {
7556 /* Compute the number of padding bytes in last block of payload */
7557 npblb = 16U - ((uint32_t)hcryp->Size);
7558 mode = CRYP_CONV_ALGODIR(((SAES_TypeDef *)(hcryp->Instance))->CR & SAES_CR_MODE);
7559 if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
7560 ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
7561 {
7562 /* Specify the number of non-valid bytes using NPBLB register*/
7563 MODIFY_REG(((CRYP_TypeDef *)(hcryp->Instance))->CR, SAES_CR_NPBLB, npblb << 20U);
7564 }
7565
7566 /* Number of valid words (lastwordsize) in last block */
7567 if ((npblb % 4U) == 0U)
7568 {
7569 lastwordsize = (16U - npblb) / 4U;
7570 }
7571 else
7572 {
7573 lastwordsize = ((16U - npblb) / 4U) + 1U;
7574 }
7575
7576 /* Last block optionally pad the data with zeros*/
7577 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
7578 {
7579 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
7580 hcryp->CrypInCount++;
7581 }
7582 while (loopcounter < 4U)
7583 {
7584 /* Pad the data with zeros to have a complete block */
7585 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
7586 loopcounter++;
7587 }
7588 /* Call the input data transfer complete callback */
7589 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
7590 /*Call registered Input complete callback*/
7591 hcryp->InCpltCallback(hcryp);
7592 #else
7593 /*Call legacy Input complete callback*/
7594 HAL_CRYP_InCpltCallback(hcryp);
7595 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
7596 }
7597 }
7598 else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U))
7599 {
7600 /* Can enter full 4 header words */
7601 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
7602 /* If suspension flag has been raised, suspend processing
7603 only if not already at the end of the header */
7604 if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
7605 {
7606 /* Clear CCF Flag */
7607 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
7608
7609 /* reset SuspendRequest */
7610 hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
7611 /* Disable Computation Complete Flag and Errors Interrupts */
7612 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
7613 /* Change the CRYP state */
7614 hcryp->State = HAL_CRYP_STATE_SUSPENDED;
7615 /* Mark that the payload phase is suspended */
7616 hcryp->Phase = CRYP_PHASE_HEADER_SUSPENDED;
7617 __HAL_UNLOCK(hcryp);
7618 }
7619 else
7620 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
7621 {
7622 /* Write the input block in the IN FIFO */
7623 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7624 hcryp->CrypHeaderCount++;
7625 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7626 hcryp->CrypHeaderCount++;
7627 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7628 hcryp->CrypHeaderCount++;
7629 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7630 hcryp->CrypHeaderCount++;
7631 }
7632 }
7633 else /* Write last header block (4 words), padded with zeros if needed */
7634 {
7635 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
7636 {
7637 ((SAES_TypeDef *)(hcryp->Instance))->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7638 hcryp->CrypHeaderCount++ ;
7639 }
7640 /* If the header size is a multiple of words */
7641 if ((headersize_in_bytes % 4U) == 0U)
7642 {
7643 /* Pad the data with zeros to have a complete block */
7644 while (loopcounter < 4U)
7645 {
7646 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
7647 loopcounter++;
7648 hcryp->CrypHeaderCount++;
7649 }
7650 }
7651 else
7652 {
7653 /* Enter last bytes, padded with zeros */
7654 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
7655 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
7656 ((SAES_TypeDef *)(hcryp->Instance))->DINR = tmp;
7657 loopcounter++;
7658 hcryp->CrypHeaderCount++;
7659 /* Pad the data with zeros to have a complete block */
7660 while (loopcounter < 4U)
7661 {
7662 ((SAES_TypeDef *)(hcryp->Instance))->DINR = 0x0U;
7663 loopcounter++;
7664 hcryp->CrypHeaderCount++;
7665 }
7666 }
7667 }
7668 } /* if (IS_SAES_INSTANCE(hcryp->Instance)) */
7669 #endif /* USE_HAL_SAES_ONLY */
7670 }
7671
7672 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7673 /**
7674 * @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
7675 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7676 * the configuration information for CRYP module.
7677 * @param Timeout: Timeout duration.
7678 * @retval HAL status
7679 */
CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef * hcryp,uint32_t Timeout)7680 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7681 {
7682 uint32_t tickstart;
7683
7684 /* Get timeout */
7685 tickstart = HAL_GetTick();
7686
7687 while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_IFEM))
7688 {
7689 /* Check for the Timeout */
7690 if (Timeout != HAL_MAX_DELAY)
7691 {
7692 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7693 {
7694 return HAL_ERROR;
7695 }
7696 }
7697 }
7698 return HAL_OK;
7699 }
7700 #endif /* USE_HAL_CRYP_ONLY */
7701
7702 /**
7703 * @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
7704 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7705 * the configuration information for CRYP module.
7706 * @param Timeout: Timeout duration.
7707 * @retval HAL status
7708 */
CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef * hcryp,uint32_t Timeout)7709 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7710 {
7711 uint32_t tickstart;
7712 uint32_t flag_busy = 0U;
7713
7714 /* Get timeout */
7715 tickstart = HAL_GetTick();
7716
7717 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7718 if (IS_CRYP_INSTANCE(hcryp->Instance))
7719 {
7720 flag_busy = CRYP_FLAG_BUSY;
7721 }
7722 #endif /* USE_HAL_CRYP_ONLY */
7723 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7724 if (IS_SAES_INSTANCE(hcryp->Instance))
7725 {
7726 flag_busy = SAES_FLAG_BUSY;
7727 }
7728 #endif /* USE_HAL_SAES_ONLY */
7729 while (HAL_IS_BIT_SET(((CRYP_TypeDef *)(hcryp->Instance))->SR, flag_busy))
7730 {
7731 /* Check for the Timeout */
7732 if (Timeout != HAL_MAX_DELAY)
7733 {
7734 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7735 {
7736 return HAL_ERROR;
7737 }
7738 }
7739 }
7740 return HAL_OK;
7741 }
7742
7743 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7744 /**
7745 * @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
7746 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7747 * the configuration information for CRYP module.
7748 * @param Timeout: Timeout duration.
7749 * @retval HAL status
7750 */
CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef * hcryp,uint32_t Timeout)7751 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7752 {
7753 uint32_t tickstart;
7754
7755 /* Get timeout */
7756 tickstart = HAL_GetTick();
7757
7758 while (HAL_IS_BIT_CLR(((CRYP_TypeDef *)(hcryp->Instance))->SR, CRYP_FLAG_OFNE))
7759 {
7760 /* Check for the Timeout */
7761 if (Timeout != HAL_MAX_DELAY)
7762 {
7763 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7764 {
7765 return HAL_ERROR;
7766 }
7767 }
7768 }
7769 return HAL_OK;
7770 }
7771 #endif /* USE_HAL_CRYP_ONLY */
7772
7773 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7774 /**
7775 * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
7776 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
7777 * the configuration information for CRYP module.
7778 * @param Timeout Timeout duration.
7779 * @retval HAL status
7780 */
CRYP_WaitOnCCFlag(const CRYP_HandleTypeDef * hcryp,uint32_t Timeout)7781 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7782 {
7783 uint32_t tickstart;
7784
7785 /* Get timeout */
7786 tickstart = HAL_GetTick();
7787
7788 while (HAL_IS_BIT_CLR(((SAES_TypeDef *)(hcryp->Instance))->SR, SAES_SR_CCF))
7789 {
7790 /* Check for the Timeout */
7791 if (Timeout != HAL_MAX_DELAY)
7792 {
7793 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7794 {
7795 return HAL_ERROR;
7796 }
7797 }
7798 }
7799 return HAL_OK;
7800 }
7801 #endif /* USE_HAL_SAES_ONLY */
7802
7803 #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
7804 /**
7805 * @brief In case of message processing suspension, read the Initialization Vector.
7806 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
7807 * the configuration information for CRYP module.
7808 * @param Output Pointer to the buffer containing the saved Initialization Vector.
7809 * @note This value has to be stored for reuse by writing the AES_IVRx registers
7810 * as soon as the suspended processing has to be resumed.
7811 * @retval None
7812 */
CRYP_Read_IVRegisters(CRYP_HandleTypeDef * hcryp,uint32_t * Output)7813 static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output)
7814 {
7815 uint32_t outputaddr = (uint32_t)Output;
7816
7817 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7818 if (IS_CRYP_INSTANCE(hcryp->Instance))
7819 {
7820 *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR;
7821 outputaddr += 4U;
7822 *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR;
7823 outputaddr += 4U;
7824 *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR;
7825 outputaddr += 4U;
7826 *(uint32_t *)(outputaddr) = ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR;
7827 }
7828 #endif /* USE_HAL_CRYP_ONLY */
7829 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7830 if (IS_SAES_INSTANCE(hcryp->Instance))
7831 {
7832 *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR3;
7833 outputaddr += 4U;
7834 *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR2;
7835 outputaddr += 4U;
7836 *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR1;
7837 outputaddr += 4U;
7838 *(uint32_t *)(outputaddr) = ((SAES_TypeDef *)(hcryp->Instance))->IVR0;
7839 }
7840 #endif /* USE_HAL_SAES_ONLY */
7841 }
7842
7843 /**
7844 * @brief In case of GCM/GMAC/CCM processing resumption, rewrite the Initialization
7845 * Vector in the SAES_IVx registers.
7846 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
7847 * the configuration information for CRYP module.
7848 * @param Input Pointer to the buffer containing the saved Initialization Vector to
7849 * write back in the CRYP hardware block.
7850 * @note Applicable only to CRYP peripheral
7851 * @note CRYP must be disabled when reconfiguring the IV values.
7852 * @retval None
7853 */
CRYP_Write_IVRegisters(CRYP_HandleTypeDef * hcryp,uint32_t * Input)7854 static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input)
7855 {
7856 uint32_t ivaddr = (uint32_t)Input;
7857 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7858 if (IS_CRYP_INSTANCE(hcryp->Instance))
7859 {
7860 ((CRYP_TypeDef *)(hcryp->Instance))->IV0LR = *(uint32_t *)(ivaddr);
7861 ivaddr += 4U;
7862 ((CRYP_TypeDef *)(hcryp->Instance))->IV0RR = *(uint32_t *)(ivaddr);
7863 ivaddr += 4U;
7864 ((CRYP_TypeDef *)(hcryp->Instance))->IV1LR = *(uint32_t *)(ivaddr);
7865 ivaddr += 4U;
7866 ((CRYP_TypeDef *)(hcryp->Instance))->IV1RR = *(uint32_t *)(ivaddr);
7867 }
7868 #endif /* USE_HAL_CRYP_ONLY */
7869 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7870 if (IS_SAES_INSTANCE(hcryp->Instance))
7871 {
7872 ((SAES_TypeDef *)(hcryp->Instance))->IVR3 = *(uint32_t *)(ivaddr);
7873 ivaddr += 4U;
7874 ((SAES_TypeDef *)(hcryp->Instance))->IVR2 = *(uint32_t *)(ivaddr);
7875 ivaddr += 4U;
7876 ((SAES_TypeDef *)(hcryp->Instance))->IVR1 = *(uint32_t *)(ivaddr);
7877 ivaddr += 4U;
7878 ((SAES_TypeDef *)(hcryp->Instance))->IVR0 = *(uint32_t *)(ivaddr);
7879 }
7880 #endif /* USE_HAL_SAES_ONLY */
7881 }
7882
7883 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7884 /**
7885 * @brief In case of message GCM/GMAC/CCM processing suspension,
7886 * read the context swap Registers.
7887 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
7888 * the configuration information for CRYP module.
7889 * @param Output Pointer to the buffer containing the saved Suspend Registers.
7890 * @param Algorithm specifies whether CCM or GCM/GMAC is suspended.
7891 * @note These values have to be stored for reuse by writing back the CRYP_CSGCMCCMxR CRYP_CSGCMxR registers
7892 * as soon as the suspended processing has to be resumed.
7893 * @retval None
7894 */
CRYP_Read_ContextSwapRegisters(CRYP_HandleTypeDef * hcryp,uint32_t * Output,uint32_t Algorithm)7895 static void CRYP_Read_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Output, uint32_t Algorithm)
7896 {
7897 uint32_t outputaddr = (uint32_t)Output;
7898 uint32_t inputaddr = (uint32_t)(&((CRYP_TypeDef *)(hcryp->Instance))->CSGCMCCM0R);
7899 uint32_t i;
7900
7901 for (i = 0; i < 8U; i++)
7902 {
7903 *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr);
7904 outputaddr += 4U;
7905 inputaddr += 4U;
7906 }
7907 if (Algorithm == CRYP_AES_GCM)
7908 {
7909 for (i = 0; i < 8U; i++)
7910 {
7911 *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr);
7912 outputaddr += 4U;
7913 inputaddr += 4U;
7914 }
7915 }
7916 }
7917 #endif /* USE_HAL_CRYP_ONLY */
7918
7919 /**
7920 * @brief In case of message GCM/GMAC/CCM processing resumption, rewrite the context swap registers.
7921 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
7922 * the configuration information for CRYP module.
7923 * @param Input Pointer to the buffer containing the saved suspend registers to
7924 * write back in the CRYP hardware block.
7925 * @param Algorithm specifies whether CCM or GCM/GMAC is suspended.
7926 * @note AES must be disabled when reconfiguring the suspend registers.
7927 * @retval None
7928 */
CRYP_Write_ContextSwapRegisters(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint32_t Algorithm)7929 static void CRYP_Write_ContextSwapRegisters(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint32_t Algorithm)
7930 {
7931 uint32_t inputaddr = (uint32_t)Input;
7932 uint32_t outputaddr = (uint32_t)(&((CRYP_TypeDef *)(hcryp->Instance))->CSGCMCCM0R);
7933 uint32_t i;
7934
7935 for (i = 0; i < 8U; i++)
7936 {
7937 *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr);
7938 outputaddr += 4U;
7939 inputaddr += 4U;
7940 }
7941 if (Algorithm == CRYP_AES_GCM)
7942 {
7943 for (i = 0; i < 8U; i++)
7944 {
7945 *(uint32_t *)(outputaddr) = *(uint32_t *)(inputaddr);
7946 outputaddr += 4U;
7947 inputaddr += 4U;
7948 }
7949 }
7950 }
7951
7952 /**
7953 * @brief Authentication phase resumption in case of GCM/GMAC/CCM process in interrupt mode
7954 * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
7955 * the configuration information for CRYP module(Header & HeaderSize)
7956 * @retval None
7957 */
CRYP_PhaseProcessingResume(CRYP_HandleTypeDef * hcryp)7958 static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
7959 {
7960 /* Case of header phase resumption =================================================*/
7961 if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED)
7962 {
7963 /* Set the phase */
7964 hcryp->Phase = CRYP_PHASE_PROCESS;
7965
7966 /* Select header phase */
7967 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7968 if (IS_CRYP_INSTANCE(hcryp->Instance))
7969 {
7970 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
7971 }
7972 #endif /* USE_HAL_CRYP_ONLY */
7973 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
7974 if (IS_SAES_INSTANCE(hcryp->Instance))
7975 {
7976 SAES_SET_PHASE(hcryp, SAES_PHASE_HEADER);
7977 }
7978 #endif /* USE_HAL_SAES_ONLY */
7979
7980 /* Enable interrupts */
7981 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
7982
7983 /* Enable CRYP */
7984 __HAL_CRYP_ENABLE(hcryp);
7985
7986 }
7987 /* Case of payload phase resumption =================================================*/
7988 else
7989 {
7990 /* Set the phase */
7991 hcryp->Phase = CRYP_PHASE_PROCESS;
7992
7993 /* Select payload phase once the header phase is performed */
7994 #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1)
7995 if (IS_CRYP_INSTANCE(hcryp->Instance))
7996 {
7997 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
7998 }
7999 #endif /* USE_HAL_CRYP_ONLY */
8000 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
8001 if (IS_SAES_INSTANCE(hcryp->Instance))
8002 {
8003 SAES_SET_PHASE(hcryp, SAES_PHASE_PAYLOAD);
8004 }
8005 #endif /* USE_HAL_SAES_ONLY */
8006
8007 /* Enable Interrupts */
8008 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
8009
8010 /* Enable the CRYP peripheral */
8011 __HAL_CRYP_ENABLE(hcryp);
8012
8013 }
8014 }
8015
8016 #endif /* USE_HAL_CRYP_SUSPEND_RESUME */
8017
8018 #if !defined(USE_HAL_SAES_ONLY) || (USE_HAL_SAES_ONLY == 1)
8019 /*
8020 * @brief Adaptation needed do differentiate between CRYP and SAES CR_CHMOD fields
8021 * @param algo: corresponds to the algorithm to set
8022 * order: determines if conversion is done from CRYP to SAES and vice versa
8023 order = ALGOMODE_CRYP_TO_CHMOD_SAES means from algomode CRYP to chmod SAES
8024 order = ALGOMODE_SAES_TO_CHMOD_CRYP means from algomode SAES to chmod CRYP
8025 * @retval new_algo: correspond to the CR_CHMOD setting applied
8026 */
CRYP_SAES_AlgoConversion(uint32_t algo,uint32_t order)8027 static uint32_t CRYP_SAES_AlgoConversion(uint32_t algo, uint32_t order)
8028 {
8029 uint32_t new_algo = 0x0;
8030
8031 if (order == 0U) /* from algomode CRYP to chmod SAES */
8032 {
8033 switch (algo)
8034 {
8035 case CRYP_AES_ECB :
8036 new_algo = SAES_CR_CHMOD_AES_ECB;
8037 break;
8038 case CRYP_AES_CBC :
8039 new_algo = SAES_CR_CHMOD_AES_CBC;
8040 break;
8041 case CRYP_AES_CTR :
8042 new_algo = SAES_CR_CHMOD_AES_CTR;
8043 break;
8044 case CRYP_AES_GCM :
8045 new_algo = SAES_CR_CHMOD_AES_GCM;
8046 break;
8047 case CRYP_AES_CCM :
8048 new_algo = SAES_CR_CHMOD_AES_CCM;
8049 break;
8050 default :
8051 break;
8052 }
8053
8054 }
8055 else /* order == 1 , from chmod SAES to algomode CRYP */
8056 {
8057 switch (algo)
8058 {
8059 case SAES_CR_CHMOD_AES_ECB :
8060 new_algo = CRYP_AES_ECB;
8061 break;
8062 case SAES_CR_CHMOD_AES_CBC :
8063 new_algo = CRYP_AES_CBC;
8064 break;
8065 case SAES_CR_CHMOD_AES_CTR :
8066 new_algo = CRYP_AES_CTR;
8067 break;
8068 case SAES_CR_CHMOD_AES_GCM :
8069 new_algo = CRYP_AES_GCM;
8070 break;
8071 case SAES_CR_CHMOD_AES_CCM :
8072 new_algo = CRYP_AES_CCM;
8073 break;
8074 default :
8075 break;
8076 }
8077 }
8078
8079 return new_algo;
8080 }
8081 #endif /* USE_HAL_SAES_ONLY */
8082
8083 /**
8084 * @}
8085 */
8086
8087 /**
8088 * @}
8089 */
8090
8091 #endif /* HAL_CRYP_MODULE_ENABLED */
8092
8093
8094 /**
8095 * @}
8096 */
8097 #endif /* CRYP */
8098 /**
8099 * @}
8100 */
8101
