1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and Configuration functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2022 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ==============================================================================
24 ##### How to use this driver #####
25 ==============================================================================
26
27 [..]
28 *** How to configure Interrupts using CORTEX HAL driver ***
29 ===========================================================
30 [..]
31 This section provides functions allowing to configure the NVIC interrupts (IRQ).
32 The Cortex-M7 exceptions are managed by CMSIS functions.
33
34 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
35 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
36 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
37
38 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
39 The pending IRQ priority will be managed only by the sub priority.
40
41 -@- IRQ priority order (sorted by highest to lowest priority):
42 (+@) Lowest pre-emption priority
43 (+@) Lowest sub priority
44 (+@) Lowest hardware priority (IRQ number)
45
46 [..]
47 *** How to configure SysTick using CORTEX HAL driver ***
48 ========================================================
49 [..]
50 Setup SysTick Timer for time base.
51
52 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
53 is a CMSIS function that:
54 (++) Configures the SysTick Reload register with value passed as function parameter.
55 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
56 (++) Resets the SysTick Counter register.
57 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
58 (++) Enables the SysTick Interrupt.
59 (++) Starts the SysTick Counter.
60
61 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
62 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
63 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
64 inside the stm32h7rsxx_hal_cortex.h file.
65
66 (+) You can change the SysTick IRQ priority by calling the
67 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
68 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
69
70 (+) To adjust the SysTick time base, use the following formula:
71
72 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
73 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
74 (++) Reload Value should not exceed 0xFFFFFF
75
76 @endverbatim
77 ******************************************************************************
78
79 The table below gives the allowed values of the pre-emption priority and subpriority according
80 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
81
82 ==========================================================================================================================
83 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
84 ==========================================================================================================================
85 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
86 | | | 4 bits for subpriority
87 --------------------------------------------------------------------------------------------------------------------------
88 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
89 | | | 3 bits for subpriority
90 --------------------------------------------------------------------------------------------------------------------------
91 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
92 | | | 2 bits for subpriority
93 --------------------------------------------------------------------------------------------------------------------------
94 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
95 | | | 1 bit for subpriority
96 --------------------------------------------------------------------------------------------------------------------------
97 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
98 | | | 0 bit for subpriority
99 ==========================================================================================================================
100 */
101
102 /* Includes ------------------------------------------------------------------*/
103 #include "stm32h7rsxx_hal.h"
104
105 /** @addtogroup STM32H7RSxx_HAL_Driver
106 * @{
107 */
108
109 /** @addtogroup CORTEX
110 * @brief CORTEX HAL module driver
111 * @{
112 */
113
114 #ifdef HAL_CORTEX_MODULE_ENABLED
115
116 /* Private types -------------------------------------------------------------*/
117 /* Private variables ---------------------------------------------------------*/
118 /* Private constants ---------------------------------------------------------*/
119 /* Private macros ------------------------------------------------------------*/
120 /* Private functions ---------------------------------------------------------*/
121 /* Exported functions --------------------------------------------------------*/
122
123 /** @addtogroup CORTEX_Exported_Functions
124 * @{
125 */
126
127
128 /** @addtogroup CORTEX_Exported_Functions_Group1
129 * @brief Initialization and Configuration functions
130 *
131 @verbatim
132 ==============================================================================
133 ##### Initialization and Configuration functions #####
134 ==============================================================================
135 [..]
136 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
137 SysTick functionalities
138
139 @endverbatim
140 * @{
141 */
142
143
144 /**
145 * @brief Set the priority grouping field (pre-emption priority and subpriority)
146 * using the required unlock sequence.
147 * @param PriorityGroup The priority grouping bits length.
148 * This parameter can be one of the following values:
149 * @arg NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority,
150 * 4 bits for subpriority
151 * @arg NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority,
152 * 3 bits for subpriority
153 * @arg NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority,
154 * 2 bits for subpriority
155 * @arg NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority,
156 * 1 bit for subpriority
157 * @arg NVIC_PRIORITYGROUP_4 4 bits for pre-emption priority,
158 * 0 bit for subpriority
159 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
160 * The pending IRQ priority will be managed only by the subpriority.
161 * @retval None
162 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)163 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
164 {
165 /* Check the parameters */
166 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
167
168 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
169 NVIC_SetPriorityGrouping(PriorityGroup);
170 }
171
172 /**
173 * @brief Set the priority of an interrupt.
174 * @param IRQn External interrupt number.
175 * This parameter can be an enumerator of IRQn_Type enumeration
176 * (For the complete STM32 Devices IRQ Channels list, please refer
177 * to the appropriate CMSIS device file (stm32h7rsxxxx.h))
178 * @param PreemptPriority The pre-emption priority for the IRQn channel.
179 * This parameter can be a value between 0 and 15
180 * A lower priority value indicates a higher priority
181 * @param SubPriority the subpriority level for the IRQ channel.
182 * This parameter can be a value between 0 and 15
183 * A lower priority value indicates a higher priority.
184 * @retval None
185 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)186 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
187 {
188 uint32_t prioritygroup;
189
190 /* Check the parameters */
191 assert_param(IS_NVIC_PRIO_INTERRUPT(IRQn));
192 prioritygroup = NVIC_GetPriorityGrouping();
193 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority, prioritygroup));
194 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority, prioritygroup));
195
196 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
197 }
198
199 /**
200 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
201 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
202 * function should be called before.
203 * @param IRQn External interrupt number.
204 * This parameter can be an enumerator of IRQn_Type enumeration
205 * (For the complete STM32 Devices IRQ Channels list, please refer
206 * to the appropriate CMSIS device file (stm32h7rsxxxx.h))
207 * @retval None
208 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)209 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
210 {
211 /* Check the parameters */
212 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
213
214 /* Enable interrupt */
215 NVIC_EnableIRQ(IRQn);
216 }
217
218 /**
219 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
220 * @param IRQn External interrupt number.
221 * This parameter can be an enumerator of IRQn_Type enumeration
222 * (For the complete STM32 Devices IRQ Channels list, please refer
223 * to the appropriate CMSIS device file (stm32h7rsxxxx.h))
224 * @retval None
225 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)226 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
227 {
228 /* Check the parameters */
229 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
230
231 /* Disable interrupt */
232 NVIC_DisableIRQ(IRQn);
233 }
234
235 /**
236 * @brief Initiate a system reset request to reset the MCU.
237 * @retval None
238 */
HAL_NVIC_SystemReset(void)239 void HAL_NVIC_SystemReset(void)
240 {
241 /* System Reset */
242 NVIC_SystemReset();
243 }
244
245 /**
246 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
247 * Counter is in free running mode to generate periodic interrupts.
248 * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
249 * @retval status: - 0 Function succeeded.
250 * - 1 Function failed.
251 */
HAL_SYSTICK_Config(uint32_t TicksNumb)252 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
253 {
254 return SysTick_Config(TicksNumb);
255 }
256 /**
257 * @}
258 */
259
260 /** @addtogroup CORTEX_Exported_Functions_Group2
261 * @brief Cortex control functions
262 *
263 @verbatim
264 ==============================================================================
265 ##### Peripheral Control functions #####
266 ==============================================================================
267 [..]
268 This subsection provides a set of functions allowing to control the CORTEX
269 (NVIC, SYSTICK, MPU) functionalities.
270
271
272 @endverbatim
273 * @{
274 */
275
276 /**
277 * @brief Get the priority grouping field from the NVIC Interrupt Controller.
278 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
279 */
HAL_NVIC_GetPriorityGrouping(void)280 uint32_t HAL_NVIC_GetPriorityGrouping(void)
281 {
282 /* Get the PRIGROUP[10:8] field value */
283 return NVIC_GetPriorityGrouping();
284 }
285
286 /**
287 * @brief Get the priority of an interrupt.
288 * @param IRQn External interrupt number.
289 * This parameter can be an enumerator of IRQn_Type enumeration
290 * (For the complete STM32 Devices IRQ Channels list, please refer
291 * to the appropriate CMSIS device file (stm32h7rsxxxx.h))
292 * @param PriorityGroup the priority grouping bits length.
293 * This parameter can be one of the following values:
294 * @arg NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority,
295 * 4 bits for subpriority
296 * @arg NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority,
297 * 3 bits for subpriority
298 * @arg NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority,
299 * 2 bits for subpriority
300 * @arg NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority,
301 * 1 bit for subpriority
302 * @arg NVIC_PRIORITYGROUP_4 4 bits for pre-emption priority,
303 * 0 bit for subpriority
304 * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
305 * @param pSubPriority Pointer on the Subpriority value (starting from 0).
306 * @retval None
307 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)308 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
309 {
310 /* Check the parameters */
311 assert_param(IS_NVIC_PRIO_INTERRUPT(IRQn));
312 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
313
314 /* Get priority for Cortex-M system or device specific interrupts */
315 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
316 }
317
318 /**
319 * @brief Set Pending bit of an external interrupt.
320 * @param IRQn External interrupt number
321 * This parameter can be an enumerator of IRQn_Type enumeration
322 * (For the complete STM32 Devices IRQ Channels list, please refer
323 * to the appropriate CMSIS device file (stm32h7rsxxxx.h))
324 * @retval None
325 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)326 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
327 {
328 /* Check the parameters */
329 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
330
331 /* Set interrupt pending */
332 NVIC_SetPendingIRQ(IRQn);
333 }
334
335 /**
336 * @brief Get Pending Interrupt (read the pending register in the NVIC
337 * and return the pending bit for the specified interrupt).
338 * @param IRQn External interrupt number.
339 * This parameter can be an enumerator of IRQn_Type enumeration
340 * (For the complete STM32 Devices IRQ Channels list, please refer
341 * to the appropriate CMSIS device file (stm32h7rsxxxx.h))
342 * @retval status: - 0 Interrupt status is not pending.
343 * - 1 Interrupt status is pending.
344 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)345 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
346 {
347 /* Check the parameters */
348 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
349
350 /* Return 1 if pending else 0 */
351 return NVIC_GetPendingIRQ(IRQn);
352 }
353
354 /**
355 * @brief Clear the pending bit of an external interrupt.
356 * @param IRQn External interrupt number.
357 * This parameter can be an enumerator of IRQn_Type enumeration
358 * (For the complete STM32 Devices IRQ Channels list, please refer
359 * to the appropriate CMSIS device file (stm32h7rsxxxx.h))
360 * @retval None
361 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)362 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
363 {
364 /* Check the parameters */
365 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
366
367 /* Clear pending interrupt */
368 NVIC_ClearPendingIRQ(IRQn);
369 }
370
371 /**
372 * @brief Get active interrupt (read the active register in NVIC and return the active bit).
373 * @param IRQn External interrupt number
374 * This parameter can be an enumerator of IRQn_Type enumeration
375 * (For the complete STM32 Devices IRQ Channels list, please refer
376 * to the appropriate CMSIS device file (stm32h7rsxxxx.h))
377 * @retval status: - 0 Interrupt status is not pending.
378 * - 1 Interrupt status is pending.
379 */
HAL_NVIC_GetActive(IRQn_Type IRQn)380 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
381 {
382 /* Return 1 if active else 0 */
383 return NVIC_GetActive(IRQn);
384 }
385
386 /**
387 * @brief Configure the SysTick clock source.
388 * @param CLKSource specifies the SysTick clock source.
389 * This parameter can be one of the following values:
390 * @arg SYSTICK_CLKSOURCE_HCLK AHB clock selected as SysTick clock source.
391 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8 AHB clock divided by 8 selected as SysTick clock source.
392 * @retval None
393 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)394 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
395 {
396 /* Check the parameters */
397 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
398
399 MODIFY_REG(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk, CLKSource);
400 }
401
402 /**
403 * @brief Handle SYSTICK interrupt request.
404 * @retval None
405 */
HAL_SYSTICK_IRQHandler(void)406 void HAL_SYSTICK_IRQHandler(void)
407 {
408 HAL_SYSTICK_Callback();
409 }
410
411 /**
412 * @brief SYSTICK callback.
413 * @retval None
414 */
HAL_SYSTICK_Callback(void)415 __weak void HAL_SYSTICK_Callback(void)
416 {
417 /* NOTE : This function should not be modified, when the callback is needed,
418 the HAL_SYSTICK_Callback could be implemented in the user file
419 */
420 }
421
422 /**
423 * @brief Enable the MPU.
424 * @param MPU_Control Specifies the control mode of the MPU during hard fault,
425 * NMI, FAULTMASK and privileged access to the default memory
426 * This parameter can be one of the following values:
427 * @arg MPU_HFNMI_PRIVDEF_NONE
428 * @arg MPU_HARDFAULT_NMI
429 * @arg MPU_PRIVILEGED_DEFAULT
430 * @arg MPU_HFNMI_PRIVDEF
431 * @retval None
432 */
HAL_MPU_Enable(uint32_t MPU_Control)433 void HAL_MPU_Enable(uint32_t MPU_Control)
434 {
435 /* Force any outstanding transfers to complete before enabling MPU */
436 __DMB();
437
438 /* Enable the MPU */
439 MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
440
441 /* Enable fault exceptions */
442 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
443
444 /* Ensure MPU setting take effects */
445 __DSB();
446 __ISB();
447 }
448
449 /**
450 * @brief Disable the MPU.
451 * @retval None
452 */
HAL_MPU_Disable(void)453 void HAL_MPU_Disable(void)
454 {
455 /* Force any outstanding transfers to complete before disabling MPU */
456 __DMB();
457
458 /* Disable fault exceptions */
459 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
460
461 /* Disable the MPU and clear the control register */
462 MPU->CTRL = 0U;
463
464 /* Ensure MPU setting take effects */
465 __DSB();
466 __ISB();
467 }
468
469 /**
470 * @brief Enable the MPU Region.
471 * @retval None
472 */
HAL_MPU_EnableRegion(uint32_t RegionNumber)473 void HAL_MPU_EnableRegion(uint32_t RegionNumber)
474 {
475 /* Check the parameters */
476 assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
477
478 /* Set the Region number */
479 MPU->RNR = RegionNumber;
480
481 /* Enable the Region */
482 SET_BIT(MPU->RASR,MPU_RASR_ENABLE_Msk);
483 }
484
485 /**
486 * @brief Disable the MPU Region.
487 * @retval None
488 */
HAL_MPU_DisableRegion(uint32_t RegionNumber)489 void HAL_MPU_DisableRegion(uint32_t RegionNumber)
490 {
491 /* Check the parameters */
492 assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
493
494 /* Set the Region number */
495 MPU->RNR = RegionNumber;
496
497 /* Disable the Region */
498 CLEAR_BIT(MPU->RASR,MPU_RASR_ENABLE_Msk);
499 }
500
501 /**
502 * @brief Initialize and configure the Region and the memory to be protected.
503 * @param pMPU_RegionInit Pointer to a MPU_Region_InitTypeDef structure that contains
504 * the initialization and configuration information.
505 * @note The region base address must be aligned to the size of the region.
506 * @retval None
507 */
HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef * pMPU_RegionInit)508 void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *pMPU_RegionInit)
509 {
510 /* Check the parameters */
511 assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number));
512 assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable));
513
514 /* Set the Region number */
515 MPU->RNR = pMPU_RegionInit->Number;
516
517 /* Check the parameters */
518 assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec));
519 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission));
520 assert_param(IS_MPU_TEX_LEVEL(pMPU_RegionInit->TypeExtField));
521 assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable));
522 assert_param(IS_MPU_ACCESS_CACHEABLE(pMPU_RegionInit->IsCacheable));
523 assert_param(IS_MPU_ACCESS_BUFFERABLE(pMPU_RegionInit->IsBufferable));
524 assert_param(IS_MPU_SUB_REGION_DISABLE(pMPU_RegionInit->SubRegionDisable));
525 assert_param(IS_MPU_REGION_SIZE(pMPU_RegionInit->Size));
526 assert_param(IS_MPU_ADDRESS_MULTIPLE_SIZE(pMPU_RegionInit->BaseAddress, pMPU_RegionInit->Size));
527
528 /* Disable the Region */
529 CLEAR_BIT(MPU->RASR,MPU_RASR_ENABLE_Msk);
530
531 /* Disable the Region */
532 CLEAR_BIT(MPU->RASR,MPU_RASR_ENABLE_Msk);
533 MPU->RBAR = pMPU_RegionInit->BaseAddress;
534 MPU->RASR = ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RASR_XN_Pos) |
535 ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RASR_AP_Pos) |
536 ((uint32_t)pMPU_RegionInit->TypeExtField << MPU_RASR_TEX_Pos) |
537 ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RASR_S_Pos) |
538 ((uint32_t)pMPU_RegionInit->IsCacheable << MPU_RASR_C_Pos) |
539 ((uint32_t)pMPU_RegionInit->IsBufferable << MPU_RASR_B_Pos) |
540 ((uint32_t)pMPU_RegionInit->SubRegionDisable << MPU_RASR_SRD_Pos) |
541 ((uint32_t)pMPU_RegionInit->Size << MPU_RASR_SIZE_Pos) |
542 ((uint32_t)pMPU_RegionInit->Enable << MPU_RASR_ENABLE_Pos);
543 }
544
545 /**
546 * @brief Clear pending events.
547 * @retval None
548 */
HAL_CORTEX_ClearEvent(void)549 void HAL_CORTEX_ClearEvent(void)
550 {
551 __SEV();
552 __WFE();
553 }
554 /**
555 * @}
556 */
557
558 /**
559 * @}
560 */
561
562 #endif /* HAL_CORTEX_MODULE_ENABLED */
563 /**
564 * @}
565 */
566
567 /**
568 * @}
569 */
570
