1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_hal_adc_ex.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Converter (ADC)
7 * peripheral:
8 * + Peripheral Control functions
9 * Other functions (generic functions) are available in file
10 * "stm32h7rsxx_hal_adc.c".
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2022 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 [..]
25 (@) Sections "ADC peripheral features" and "How to use this driver" are
26 available in file of generic functions "stm32h7rsxx_hal_adc.c".
27 [..]
28 @endverbatim
29 ******************************************************************************
30 */
31
32 /* Includes ------------------------------------------------------------------*/
33 #include "stm32h7rsxx_hal.h"
34
35 /** @addtogroup STM32H7RSxx_HAL_Driver
36 * @{
37 */
38
39 /** @defgroup ADCEx ADCEx
40 * @brief ADC Extended HAL module driver
41 * @{
42 */
43
44 #ifdef HAL_ADC_MODULE_ENABLED
45
46 /* Private typedef -----------------------------------------------------------*/
47 /* Private define ------------------------------------------------------------*/
48
49 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
50 * @{
51 */
52
53 #define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
54 ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
55 ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can
56 be updated anytime once the ADC is enabled */
57
58 /* Fixed timeout value for ADC calibration. */
59 /* Fixed timeout value for ADC calibration. */
60 /* Values defined to be higher than worst cases: low clock frequency, */
61 /* maximum prescalers. */
62 /* Ex of profile low frequency : f_ADC at 0.125 Mhz (minimum value */
63 /* according to Data sheet), calibration_time MAX = 165010 / f_ADC */
64 /* 165010 / 125000 = 1.32s */
65 /* At maximum CPU speed (480 MHz), this means */
66 /* 1.32 * 480 MHz = 633600000 CPU cycles */
67 #define ADC_CALIBRATION_TIMEOUT (633600000UL) /*!< ADC calibration time-out value */
68
69 /**
70 * @}
71 */
72
73 /* Private macro -------------------------------------------------------------*/
74 /* Private variables ---------------------------------------------------------*/
75 /* Private function prototypes -----------------------------------------------*/
76 /* Exported functions --------------------------------------------------------*/
77
78 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
79 * @{
80 */
81
82 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
83 * @brief Extended IO operation functions
84 *
85 @verbatim
86 ===============================================================================
87 ##### IO operation functions #####
88 ===============================================================================
89 [..] This section provides functions allowing to:
90
91 (+) Perform the ADC self-calibration for single or differential ending.
92 (+) Get calibration factors for single or differential ending.
93 (+) Set calibration factors for single or differential ending.
94
95 (+) Start conversion of ADC group injected.
96 (+) Stop conversion of ADC group injected.
97 (+) Poll for conversion complete on ADC group injected.
98 (+) Get result of ADC group injected channel conversion.
99 (+) Start conversion of ADC group injected and enable interruptions.
100 (+) Stop conversion of ADC group injected and disable interruptions.
101
102 (+) When multimode feature is available, start multimode and enable DMA transfer.
103 (+) Stop multimode and disable ADC DMA transfer.
104 (+) Get result of multimode conversion.
105
106 @endverbatim
107 * @{
108 */
109
110 /**
111 * @brief Perform an ADC automatic self-calibration
112 * Calibration prerequisite: ADC must be disabled (execute this
113 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
114 * @param hadc ADC handle
115 * @param SingleDiff Selection of single-ended or differential input
116 * This parameter can be one of the following values:
117 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
118 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
119 * @retval HAL status
120 */
HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef * hadc,uint32_t SingleDiff)121 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
122 {
123 HAL_StatusTypeDef tmp_hal_status;
124 __IO uint32_t wait_loop_index = 0UL;
125
126 /* Check the parameters */
127 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
128 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
129
130 /* Process locked */
131 __HAL_LOCK(hadc);
132
133 /* Calibration prerequisite: ADC must be disabled. */
134
135 /* Disable the ADC (if not already disabled) */
136 tmp_hal_status = ADC_Disable(hadc);
137
138 /* Check if ADC is effectively disabled */
139 if (tmp_hal_status == HAL_OK)
140 {
141 /* Set ADC state */
142 ADC_STATE_CLR_SET(hadc->State,
143 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
144 HAL_ADC_STATE_BUSY_INTERNAL);
145
146 /* Start ADC calibration in mode single-ended or differential */
147 LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
148
149 /* Wait for calibration completion */
150 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
151 {
152 wait_loop_index++;
153 if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
154 {
155 /* Update ADC state machine to error */
156 ADC_STATE_CLR_SET(hadc->State,
157 HAL_ADC_STATE_BUSY_INTERNAL,
158 HAL_ADC_STATE_ERROR_INTERNAL);
159
160 /* Process unlocked */
161 __HAL_UNLOCK(hadc);
162
163 return HAL_ERROR;
164 }
165 }
166
167 /* Set ADC state */
168 ADC_STATE_CLR_SET(hadc->State,
169 HAL_ADC_STATE_BUSY_INTERNAL,
170 HAL_ADC_STATE_READY);
171 }
172 else
173 {
174 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
175
176 /* Note: No need to update variable "tmp_hal_status" here: already set */
177 /* to state "HAL_ERROR" by function disabling the ADC. */
178 }
179
180 /* Process unlocked */
181 __HAL_UNLOCK(hadc);
182
183 /* Return function status */
184 return tmp_hal_status;
185 }
186
187 /**
188 * @brief Get the calibration factor.
189 * @param hadc ADC handle.
190 * @param SingleDiff This parameter can be only:
191 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
192 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
193 * @retval Calibration value.
194 */
HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef * hadc,uint32_t SingleDiff)195 uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
196 {
197 /* Check the parameters */
198 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
199 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
200
201 /* Return the selected ADC calibration value */
202 return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
203 }
204
205 /**
206 * @brief Set the calibration factor to overwrite automatic conversion result.
207 * ADC must be enabled and no conversion is ongoing.
208 * @param hadc ADC handle
209 * @param SingleDiff This parameter can be only:
210 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
211 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
212 * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
213 * @retval HAL state
214 */
HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef * hadc,uint32_t SingleDiff,uint32_t CalibrationFactor)215 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
216 uint32_t CalibrationFactor)
217 {
218 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
219 uint32_t tmp_adc_is_conversion_on_going_regular;
220 uint32_t tmp_adc_is_conversion_on_going_injected;
221
222 /* Check the parameters */
223 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
224 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
225 assert_param(IS_ADC_CALFACT(CalibrationFactor));
226
227 /* Process locked */
228 __HAL_LOCK(hadc);
229
230 /* Verification of hardware constraints before modifying the calibration */
231 /* factors register: ADC must be enabled, no conversion on going. */
232 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
233 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
234
235 if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
236 && (tmp_adc_is_conversion_on_going_regular == 0UL)
237 && (tmp_adc_is_conversion_on_going_injected == 0UL)
238 )
239 {
240 /* Set the selected ADC calibration value */
241 LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
242 }
243 else
244 {
245 /* Update ADC state machine */
246 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
247 /* Update ADC error code */
248 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
249
250 /* Update ADC state machine to error */
251 tmp_hal_status = HAL_ERROR;
252 }
253
254 /* Process unlocked */
255 __HAL_UNLOCK(hadc);
256
257 /* Return function status */
258 return tmp_hal_status;
259 }
260
261 /**
262 * @brief Enable ADC, start conversion of injected group.
263 * @note Interruptions enabled in this function: None.
264 * @note Case of multimode enabled when multimode feature is available:
265 * HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
266 * then for ADC master.
267 * For ADC slave, ADC is enabled only (conversion is not started).
268 * For ADC master, ADC is enabled and multimode conversion is started.
269 * @param hadc ADC handle.
270 * @retval HAL status
271 */
HAL_ADCEx_InjectedStart(ADC_HandleTypeDef * hadc)272 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
273 {
274 HAL_StatusTypeDef tmp_hal_status;
275 uint32_t tmp_config_injected_queue;
276 #if defined(ADC_MULTIMODE_SUPPORT)
277 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
278 #endif /* ADC_MULTIMODE_SUPPORT */
279
280 /* Check the parameters */
281 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
282
283 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
284 {
285 return HAL_BUSY;
286 }
287 else
288 {
289 /* In case of software trigger detection enabled, JQDIS must be set
290 (which can be done only if ADSTART and JADSTART are both cleared).
291 If JQDIS is not set at that point, returns an error
292 - since software trigger detection is disabled. User needs to
293 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
294 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
295 the queue is empty */
296 tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
297
298 if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
299 && (tmp_config_injected_queue == 0UL)
300 )
301 {
302 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
303 return HAL_ERROR;
304 }
305
306 /* Process locked */
307 __HAL_LOCK(hadc);
308
309 /* Enable the ADC peripheral */
310 tmp_hal_status = ADC_Enable(hadc);
311
312 /* Start conversion if ADC is effectively enabled */
313 if (tmp_hal_status == HAL_OK)
314 {
315 /* Check if a regular conversion is ongoing */
316 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
317 {
318 /* Reset ADC error code field related to injected conversions only */
319 CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
320 }
321 else
322 {
323 /* Set ADC error code to none */
324 ADC_CLEAR_ERRORCODE(hadc);
325 }
326
327 /* Set ADC state */
328 /* - Clear state bitfield related to injected group conversion results */
329 /* - Set state bitfield related to injected operation */
330 ADC_STATE_CLR_SET(hadc->State,
331 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
332 HAL_ADC_STATE_INJ_BUSY);
333
334 #if defined(ADC_MULTIMODE_SUPPORT)
335 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
336 - if ADC instance is master or if multimode feature is not available
337 - if multimode setting is disabled (ADC instance slave in independent mode) */
338 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
339 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
340 )
341 {
342 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
343 }
344 #endif /* ADC_MULTIMODE_SUPPORT */
345
346 /* Clear ADC group injected group conversion flag */
347 /* (To ensure of no unknown state from potential previous ADC operations) */
348 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
349
350 /* Process unlocked */
351 /* Unlock before starting ADC conversions: in case of potential */
352 /* interruption, to let the process to ADC IRQ Handler. */
353 __HAL_UNLOCK(hadc);
354
355 /* Enable conversion of injected group, if automatic injected conversion */
356 /* is disabled. */
357 /* If software start has been selected, conversion starts immediately. */
358 /* If external trigger has been selected, conversion will start at next */
359 /* trigger event. */
360 /* Case of multimode enabled (when multimode feature is available): */
361 /* if ADC is slave, */
362 /* - ADC is enabled only (conversion is not started), */
363 /* - if multimode only concerns regular conversion, ADC is enabled */
364 /* and conversion is started. */
365 /* If ADC is master or independent, */
366 /* - ADC is enabled and conversion is started. */
367 #if defined(ADC_MULTIMODE_SUPPORT)
368 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
369 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
370 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
371 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
372 )
373 {
374 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
375 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
376 {
377 LL_ADC_INJ_StartConversion(hadc->Instance);
378 }
379 }
380 else
381 {
382 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
383 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
384 }
385 #else
386 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
387 {
388 /* Start ADC group injected conversion */
389 LL_ADC_INJ_StartConversion(hadc->Instance);
390 }
391 #endif /* ADC_MULTIMODE_SUPPORT */
392
393 }
394 else
395 {
396 /* Process unlocked */
397 __HAL_UNLOCK(hadc);
398 }
399
400 /* Return function status */
401 return tmp_hal_status;
402 }
403 }
404
405 /**
406 * @brief Stop conversion of injected channels. Disable ADC peripheral if
407 * no regular conversion is on going.
408 * @note If ADC must be disabled and if conversion is on going on
409 * regular group, function HAL_ADC_Stop must be used to stop both
410 * injected and regular groups, and disable the ADC.
411 * @note If injected group mode auto-injection is enabled,
412 * function HAL_ADC_Stop must be used.
413 * @note In case of multimode enabled (when multimode feature is available),
414 * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
415 * For ADC master, conversion is stopped and ADC is disabled.
416 * For ADC slave, ADC is disabled only (conversion stop of ADC master
417 * has already stopped conversion of ADC slave).
418 * @param hadc ADC handle.
419 * @retval HAL status
420 */
HAL_ADCEx_InjectedStop(ADC_HandleTypeDef * hadc)421 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
422 {
423 HAL_StatusTypeDef tmp_hal_status;
424
425 /* Check the parameters */
426 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
427
428 /* Process locked */
429 __HAL_LOCK(hadc);
430
431 /* 1. Stop potential conversion on going on injected group only. */
432 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
433
434 /* Disable ADC peripheral if injected conversions are effectively stopped */
435 /* and if no conversion on regular group is on-going */
436 if (tmp_hal_status == HAL_OK)
437 {
438 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
439 {
440 /* 2. Disable the ADC peripheral */
441 tmp_hal_status = ADC_Disable(hadc);
442
443 /* Check if ADC is effectively disabled */
444 if (tmp_hal_status == HAL_OK)
445 {
446 /* Set ADC state */
447 ADC_STATE_CLR_SET(hadc->State,
448 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
449 HAL_ADC_STATE_READY);
450 }
451 }
452 /* Conversion on injected group is stopped, but ADC not disabled since */
453 /* conversion on regular group is still running. */
454 else
455 {
456 /* Set ADC state */
457 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
458 }
459 }
460
461 /* Process unlocked */
462 __HAL_UNLOCK(hadc);
463
464 /* Return function status */
465 return tmp_hal_status;
466 }
467
468 /**
469 * @brief Wait for injected group conversion to be completed.
470 * @param hadc ADC handle
471 * @param Timeout Timeout value in millisecond.
472 * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
473 * checked and cleared depending on AUTDLY bit status.
474 * @retval HAL status
475 */
HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)476 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
477 {
478 uint32_t tickstart;
479 uint32_t tmp_flag_end;
480 uint32_t tmp_adc_inj_is_trigger_source_sw_start;
481 uint32_t tmp_adc_reg_is_trigger_source_sw_start;
482 uint32_t tmp_cfgr;
483 #if defined(ADC_MULTIMODE_SUPPORT)
484 const ADC_TypeDef *tmpADC_Master;
485 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
486 #endif /* ADC_MULTIMODE_SUPPORT */
487
488 /* Check the parameters */
489 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
490
491 /* If end of sequence selected */
492 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
493 {
494 tmp_flag_end = ADC_FLAG_JEOS;
495 }
496 else /* end of conversion selected */
497 {
498 tmp_flag_end = ADC_FLAG_JEOC;
499 }
500
501 /* Get timeout */
502 tickstart = HAL_GetTick();
503
504 /* Wait until End of Conversion or Sequence flag is raised */
505 while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
506 {
507 /* Check if timeout is disabled (set to infinite wait) */
508 if (Timeout != HAL_MAX_DELAY)
509 {
510 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
511 {
512 /* New check to avoid false timeout detection in case of preemption */
513 if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
514 {
515 /* Update ADC state machine to timeout */
516 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
517
518 /* Process unlocked */
519 __HAL_UNLOCK(hadc);
520
521 return HAL_TIMEOUT;
522 }
523 }
524 }
525 }
526
527 /* Retrieve ADC configuration */
528 tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
529 tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
530 /* Get relevant register CFGR in ADC instance of ADC master or slave */
531 /* in function of multimode state (for devices with multimode */
532 /* available). */
533 #if defined(ADC_MULTIMODE_SUPPORT)
534 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
535 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
536 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
537 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
538 )
539 {
540 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
541 }
542 else
543 {
544 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
545 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
546 }
547 #else
548 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
549 #endif /* ADC_MULTIMODE_SUPPORT */
550
551 /* Update ADC state machine */
552 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
553
554 /* Determine whether any further conversion upcoming on group injected */
555 /* by external trigger or by automatic injected conversion */
556 /* from group regular. */
557 if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
558 ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
559 ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
560 (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
561 {
562 /* Check whether end of sequence is reached */
563 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
564 {
565 /* Particular case if injected contexts queue is enabled: */
566 /* when the last context has been fully processed, JSQR is reset */
567 /* by the hardware. Even if no injected conversion is planned to come */
568 /* (queue empty, triggers are ignored), it can start again */
569 /* immediately after setting a new context (JADSTART is still set). */
570 /* Therefore, state of HAL ADC injected group is kept to busy. */
571 if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
572 {
573 /* Set ADC state */
574 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
575
576 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
577 {
578 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
579 }
580 }
581 }
582 }
583
584 /* Clear polled flag */
585 if (tmp_flag_end == ADC_FLAG_JEOS)
586 {
587 /* Clear end of sequence JEOS flag of injected group if low power feature */
588 /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
589 /* For injected groups, no new conversion will start before JEOS is */
590 /* cleared. */
591 if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
592 {
593 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
594 }
595 }
596 else
597 {
598 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
599 }
600
601 /* Return API HAL status */
602 return HAL_OK;
603 }
604
605 /**
606 * @brief Enable ADC, start conversion of injected group with interruption.
607 * @note Interruptions enabled in this function according to initialization
608 * setting : JEOC (end of conversion) or JEOS (end of sequence)
609 * @note Case of multimode enabled (when multimode feature is enabled):
610 * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
611 * then for ADC master.
612 * For ADC slave, ADC is enabled only (conversion is not started).
613 * For ADC master, ADC is enabled and multimode conversion is started.
614 * @param hadc ADC handle.
615 * @retval HAL status.
616 */
HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef * hadc)617 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
618 {
619 HAL_StatusTypeDef tmp_hal_status;
620 uint32_t tmp_config_injected_queue;
621 #if defined(ADC_MULTIMODE_SUPPORT)
622 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
623 #endif /* ADC_MULTIMODE_SUPPORT */
624
625 /* Check the parameters */
626 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
627
628 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
629 {
630 return HAL_BUSY;
631 }
632 else
633 {
634 /* In case of software trigger detection enabled, JQDIS must be set
635 (which can be done only if ADSTART and JADSTART are both cleared).
636 If JQDIS is not set at that point, returns an error
637 - since software trigger detection is disabled. User needs to
638 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
639 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
640 the queue is empty */
641 tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
642
643 if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
644 && (tmp_config_injected_queue == 0UL)
645 )
646 {
647 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
648 return HAL_ERROR;
649 }
650
651 /* Process locked */
652 __HAL_LOCK(hadc);
653
654 /* Enable the ADC peripheral */
655 tmp_hal_status = ADC_Enable(hadc);
656
657 /* Start conversion if ADC is effectively enabled */
658 if (tmp_hal_status == HAL_OK)
659 {
660 /* Check if a regular conversion is ongoing */
661 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
662 {
663 /* Reset ADC error code field related to injected conversions only */
664 CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
665 }
666 else
667 {
668 /* Set ADC error code to none */
669 ADC_CLEAR_ERRORCODE(hadc);
670 }
671
672 /* Set ADC state */
673 /* - Clear state bitfield related to injected group conversion results */
674 /* - Set state bitfield related to injected operation */
675 ADC_STATE_CLR_SET(hadc->State,
676 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
677 HAL_ADC_STATE_INJ_BUSY);
678
679 #if defined(ADC_MULTIMODE_SUPPORT)
680 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
681 - if ADC instance is master or if multimode feature is not available
682 - if multimode setting is disabled (ADC instance slave in independent mode) */
683 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
684 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
685 )
686 {
687 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
688 }
689 #endif /* ADC_MULTIMODE_SUPPORT */
690
691 /* Clear ADC group injected group conversion flag */
692 /* (To ensure of no unknown state from potential previous ADC operations) */
693 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
694
695 /* Process unlocked */
696 /* Unlock before starting ADC conversions: in case of potential */
697 /* interruption, to let the process to ADC IRQ Handler. */
698 __HAL_UNLOCK(hadc);
699
700 /* Enable ADC Injected context queue overflow interrupt if this feature */
701 /* is enabled. */
702 if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL)
703 {
704 __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
705 }
706
707 /* Enable ADC end of conversion interrupt */
708 switch (hadc->Init.EOCSelection)
709 {
710 case ADC_EOC_SEQ_CONV:
711 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
712 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
713 break;
714 /* case ADC_EOC_SINGLE_CONV */
715 default:
716 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
717 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
718 break;
719 }
720
721 /* Enable conversion of injected group, if automatic injected conversion */
722 /* is disabled. */
723 /* If software start has been selected, conversion starts immediately. */
724 /* If external trigger has been selected, conversion will start at next */
725 /* trigger event. */
726 /* Case of multimode enabled (when multimode feature is available): */
727 /* if ADC is slave, */
728 /* - ADC is enabled only (conversion is not started), */
729 /* - if multimode only concerns regular conversion, ADC is enabled */
730 /* and conversion is started. */
731 /* If ADC is master or independent, */
732 /* - ADC is enabled and conversion is started. */
733 #if defined(ADC_MULTIMODE_SUPPORT)
734 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
735 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
736 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
737 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
738 )
739 {
740 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
741 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
742 {
743 LL_ADC_INJ_StartConversion(hadc->Instance);
744 }
745 }
746 else
747 {
748 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
749 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
750 }
751 #else
752 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
753 {
754 /* Start ADC group injected conversion */
755 LL_ADC_INJ_StartConversion(hadc->Instance);
756 }
757 #endif /* ADC_MULTIMODE_SUPPORT */
758
759 }
760 else
761 {
762 /* Process unlocked */
763 __HAL_UNLOCK(hadc);
764 }
765
766 /* Return function status */
767 return tmp_hal_status;
768 }
769 }
770
771 /**
772 * @brief Stop conversion of injected channels, disable interruption of
773 * end-of-conversion. Disable ADC peripheral if no regular conversion
774 * is on going.
775 * @note If ADC must be disabled and if conversion is on going on
776 * regular group, function HAL_ADC_Stop must be used to stop both
777 * injected and regular groups, and disable the ADC.
778 * @note If injected group mode auto-injection is enabled,
779 * function HAL_ADC_Stop must be used.
780 * @note Case of multimode enabled (when multimode feature is available):
781 * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
782 * then for ADC slave.
783 * For ADC master, conversion is stopped and ADC is disabled.
784 * For ADC slave, ADC is disabled only (conversion stop of ADC master
785 * has already stopped conversion of ADC slave).
786 * @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
787 * @param hadc ADC handle
788 * @retval HAL status
789 */
HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef * hadc)790 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
791 {
792 HAL_StatusTypeDef tmp_hal_status;
793
794 /* Check the parameters */
795 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
796
797 /* Process locked */
798 __HAL_LOCK(hadc);
799
800 /* 1. Stop potential conversion on going on injected group only. */
801 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
802
803 /* Disable ADC peripheral if injected conversions are effectively stopped */
804 /* and if no conversion on the other group (regular group) is intended to */
805 /* continue. */
806 if (tmp_hal_status == HAL_OK)
807 {
808 /* Disable ADC end of conversion interrupt for injected channels */
809 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
810
811 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
812 {
813 /* 2. Disable the ADC peripheral */
814 tmp_hal_status = ADC_Disable(hadc);
815
816 /* Check if ADC is effectively disabled */
817 if (tmp_hal_status == HAL_OK)
818 {
819 /* Set ADC state */
820 ADC_STATE_CLR_SET(hadc->State,
821 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
822 HAL_ADC_STATE_READY);
823 }
824 }
825 /* Conversion on injected group is stopped, but ADC not disabled since */
826 /* conversion on regular group is still running. */
827 else
828 {
829 /* Set ADC state */
830 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
831 }
832 }
833
834 /* Process unlocked */
835 __HAL_UNLOCK(hadc);
836
837 /* Return function status */
838 return tmp_hal_status;
839 }
840
841 #if defined(ADC_MULTIMODE_SUPPORT)
842 /**
843 * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
844 * @note Multimode must have been previously configured using
845 * HAL_ADCEx_MultiModeConfigChannel() function.
846 * Interruptions enabled in this function:
847 * overrun, DMA half transfer, DMA transfer complete.
848 * Each of these interruptions has its dedicated callback function.
849 * @note State field of Slave ADC handle is not updated in this configuration:
850 * user should not rely on it for information related to Slave regular
851 * conversions.
852 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
853 * @param pData Destination Buffer address.
854 * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
855 * @retval HAL status
856 */
HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)857 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
858 {
859 HAL_StatusTypeDef tmp_hal_status;
860 ADC_HandleTypeDef tmp_hadc_slave;
861 ADC_Common_TypeDef *tmpADC_Common;
862 uint32_t length_bytes;
863 DMA_NodeConfTypeDef node_conf;
864
865 /* Check the parameters */
866 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
867 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
868 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
869
870 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
871 {
872 return HAL_BUSY;
873 }
874 else
875 {
876 /* Process locked */
877 __HAL_LOCK(hadc);
878
879 /* Temporary handle minimum initialization */
880 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
881 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
882
883 /* Set a temporary handle of the ADC slave associated to the ADC master */
884 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
885
886 if (tmp_hadc_slave.Instance == NULL)
887 {
888 /* Set ADC state */
889 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
890
891 /* Process unlocked */
892 __HAL_UNLOCK(hadc);
893
894 return HAL_ERROR;
895 }
896
897 /* Enable the ADC peripherals: master and slave (in case if not already */
898 /* enabled previously) */
899 tmp_hal_status = ADC_Enable(hadc);
900 if (tmp_hal_status == HAL_OK)
901 {
902 tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
903 }
904
905 /* Start multimode conversion of ADCs pair */
906 if (tmp_hal_status == HAL_OK)
907 {
908 /* Set ADC state */
909 ADC_STATE_CLR_SET(hadc->State,
910 (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
911 HAL_ADC_STATE_REG_BUSY);
912
913 /* Set ADC error code to none */
914 ADC_CLEAR_ERRORCODE(hadc);
915
916 /* Set the DMA transfer complete callback */
917 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
918
919 /* Set the DMA half transfer complete callback */
920 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
921
922 /* Set the DMA error callback */
923 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
924
925 /* Pointer to the common control register */
926 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
927
928 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
929 /* start (in case of SW start): */
930
931 /* Clear regular group conversion flag and overrun flag */
932 /* (To ensure of no unknown state from potential previous ADC operations) */
933 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
934
935 /* Process unlocked */
936 /* Unlock before starting ADC conversions: in case of potential */
937 /* interruption, to let the process to ADC IRQ Handler. */
938 __HAL_UNLOCK(hadc);
939
940 /* Enable ADC overrun interrupt */
941 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
942
943 /* Check linkedlist mode */
944 if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
945 {
946 if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
947 {
948 /* Length should be converted to number of bytes */
949 if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK)
950 {
951 return HAL_ERROR;
952 }
953
954 /* Length should be converted to number of bytes */
955 if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
956 {
957 /* Word -> Bytes */
958 length_bytes = Length * 4U;
959 }
960 else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
961 {
962 /* Halfword -> Bytes */
963 length_bytes = Length * 2U;
964 }
965 else /* Bytes */
966 {
967 /* Same size already expressed in Bytes */
968 length_bytes = Length;
969 }
970
971 hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)length_bytes;
972 hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
973 (uint32_t)&tmpADC_Common->CDR;
974 hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
975 tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
976 }
977 else
978 {
979 return HAL_ERROR;
980 }
981 }
982 else
983 {
984 /* Length should be converted to number of bytes */
985 if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
986 {
987 /* Word -> Bytes */
988 length_bytes = Length * 4U;
989 }
990 else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
991 {
992 /* Halfword -> Bytes */
993 length_bytes = Length * 2U;
994 }
995 else /* Bytes */
996 {
997 /* Same size already expressed in Bytes */
998 length_bytes = Length;
999 }
1000
1001 /* Start the DMA channel */
1002 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, \
1003 length_bytes);
1004 }
1005
1006 /* Enable conversion of regular group. */
1007 /* If software start has been selected, conversion starts immediately. */
1008 /* If external trigger has been selected, conversion will start at next */
1009 /* trigger event. */
1010 /* Start ADC group regular conversion */
1011 LL_ADC_REG_StartConversion(hadc->Instance);
1012 }
1013 else
1014 {
1015 /* Process unlocked */
1016 __HAL_UNLOCK(hadc);
1017 }
1018
1019 /* Return function status */
1020 return tmp_hal_status;
1021 }
1022 }
1023
1024 /**
1025 * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
1026 * @note Multimode is kept enabled after this function. MultiMode DMA bits
1027 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
1028 * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
1029 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
1030 * resort to HAL_ADCEx_DisableMultiMode() API.
1031 * @note In case of DMA configured in circular mode, function
1032 * HAL_ADC_Stop_DMA() must be called after this function with handle of
1033 * ADC slave, to properly disable the DMA channel.
1034 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
1035 * @retval HAL status
1036 */
HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef * hadc)1037 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
1038 {
1039 HAL_StatusTypeDef tmp_hal_status;
1040 uint32_t tickstart;
1041 ADC_HandleTypeDef tmp_hadc_slave;
1042 uint32_t tmp_hadc_slave_conversion_on_going;
1043 HAL_StatusTypeDef tmp_hadc_slave_disable_status;
1044
1045 /* Check the parameters */
1046 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1047
1048 /* Process locked */
1049 __HAL_LOCK(hadc);
1050
1051 /* 1. Stop potential multimode conversion on going, on regular and injected groups */
1052 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1053
1054 /* Disable ADC peripheral if conversions are effectively stopped */
1055 if (tmp_hal_status == HAL_OK)
1056 {
1057 /* Temporary handle minimum initialization */
1058 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
1059 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
1060
1061 /* Set a temporary handle of the ADC slave associated to the ADC master */
1062 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
1063
1064 if (tmp_hadc_slave.Instance == NULL)
1065 {
1066 /* Update ADC state machine to error */
1067 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1068
1069 /* Process unlocked */
1070 __HAL_UNLOCK(hadc);
1071
1072 return HAL_ERROR;
1073 }
1074
1075 /* Procedure to disable the ADC peripheral: wait for conversions */
1076 /* effectively stopped (ADC master and ADC slave), then disable ADC */
1077
1078 /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
1079 tickstart = HAL_GetTick();
1080
1081 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1082 while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1083 || (tmp_hadc_slave_conversion_on_going == 1UL)
1084 )
1085 {
1086 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
1087 {
1088 /* New check to avoid false timeout detection in case of preemption */
1089 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1090 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1091 || (tmp_hadc_slave_conversion_on_going == 1UL)
1092 )
1093 {
1094 /* Update ADC state machine to error */
1095 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1096
1097 /* Process unlocked */
1098 __HAL_UNLOCK(hadc);
1099
1100 return HAL_ERROR;
1101 }
1102 }
1103
1104 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1105 }
1106
1107 /* Disable the DMA channel (in case of DMA in circular mode or stop */
1108 /* while DMA transfer is on going) */
1109 /* Note: DMA channel of ADC slave should be stopped after this function */
1110 /* with HAL_ADC_Stop_DMA() API. */
1111 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1112
1113 /* Check if DMA channel effectively disabled */
1114 if (tmp_hal_status == HAL_ERROR)
1115 {
1116 /* Update ADC state machine to error */
1117 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1118 }
1119
1120 /* Disable ADC overrun interrupt */
1121 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1122
1123 /* 2. Disable the ADC peripherals: master and slave */
1124 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
1125 /* memory a potential failing status. */
1126 if (tmp_hal_status == HAL_OK)
1127 {
1128 tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave);
1129 if ((ADC_Disable(hadc) == HAL_OK) &&
1130 (tmp_hadc_slave_disable_status == HAL_OK))
1131 {
1132 tmp_hal_status = HAL_OK;
1133 }
1134 }
1135 else
1136 {
1137 /* In case of error, attempt to disable ADC master and slave without status assert */
1138 (void) ADC_Disable(hadc);
1139 (void) ADC_Disable(&tmp_hadc_slave);
1140 }
1141
1142 /* Set ADC state (ADC master) */
1143 ADC_STATE_CLR_SET(hadc->State,
1144 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1145 HAL_ADC_STATE_READY);
1146 }
1147
1148 /* Process unlocked */
1149 __HAL_UNLOCK(hadc);
1150
1151 /* Return function status */
1152 return tmp_hal_status;
1153 }
1154
1155 /**
1156 * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
1157 * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
1158 * @retval The converted data values.
1159 */
HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef * hadc)1160 uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc)
1161 {
1162 const ADC_Common_TypeDef *tmpADC_Common;
1163
1164 /* Check the parameters */
1165 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1166
1167 /* Prevent unused argument(s) compilation warning if no assert_param check */
1168 /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
1169 UNUSED(hadc);
1170
1171 /* Pointer to the common control register */
1172 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
1173
1174 /* Return the multi mode conversion value */
1175 return tmpADC_Common->CDR;
1176 }
1177 #endif /* ADC_MULTIMODE_SUPPORT */
1178
1179 /**
1180 * @brief Get ADC injected group conversion result.
1181 * @note Reading register JDRx automatically clears ADC flag JEOC
1182 * (ADC group injected end of unitary conversion).
1183 * @note This function does not clear ADC flag JEOS
1184 * (ADC group injected end of sequence conversion)
1185 * Occurrence of flag JEOS rising:
1186 * - If sequencer is composed of 1 rank, flag JEOS is equivalent
1187 * to flag JEOC.
1188 * - If sequencer is composed of several ranks, during the scan
1189 * sequence flag JEOC only is raised, at the end of the scan sequence
1190 * both flags JEOC and EOS are raised.
1191 * Flag JEOS must not be cleared by this function because
1192 * it would not be compliant with low power features
1193 * (feature low power auto-wait, not available on all STM32 series).
1194 * To clear this flag, either use function:
1195 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
1196 * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
1197 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
1198 * @param hadc ADC handle
1199 * @param InjectedRank the converted ADC injected rank.
1200 * This parameter can be one of the following values:
1201 * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
1202 * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
1203 * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
1204 * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
1205 * @retval ADC group injected conversion data
1206 */
HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef * hadc,uint32_t InjectedRank)1207 uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
1208 {
1209 uint32_t tmp_jdr;
1210
1211 /* Check the parameters */
1212 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1213 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
1214
1215 /* Get ADC converted value */
1216 switch (InjectedRank)
1217 {
1218 case ADC_INJECTED_RANK_4:
1219 tmp_jdr = hadc->Instance->JDR4;
1220 break;
1221 case ADC_INJECTED_RANK_3:
1222 tmp_jdr = hadc->Instance->JDR3;
1223 break;
1224 case ADC_INJECTED_RANK_2:
1225 tmp_jdr = hadc->Instance->JDR2;
1226 break;
1227 case ADC_INJECTED_RANK_1:
1228 default:
1229 tmp_jdr = hadc->Instance->JDR1;
1230 break;
1231 }
1232
1233 /* Return ADC converted value */
1234 return tmp_jdr;
1235 }
1236
1237 /**
1238 * @brief Injected conversion complete callback in non-blocking mode.
1239 * @param hadc ADC handle
1240 * @retval None
1241 */
HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef * hadc)1242 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
1243 {
1244 /* Prevent unused argument(s) compilation warning */
1245 UNUSED(hadc);
1246
1247 /* NOTE : This function should not be modified. When the callback is needed,
1248 function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
1249 */
1250 }
1251
1252 /**
1253 * @brief Injected context queue overflow callback.
1254 * @note This callback is called if injected context queue is enabled
1255 (parameter "QueueInjectedContext" in injected channel configuration)
1256 and if a new injected context is set when queue is full (maximum 2
1257 contexts).
1258 * @param hadc ADC handle
1259 * @retval None
1260 */
HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef * hadc)1261 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
1262 {
1263 /* Prevent unused argument(s) compilation warning */
1264 UNUSED(hadc);
1265
1266 /* NOTE : This function should not be modified. When the callback is needed,
1267 function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
1268 */
1269 }
1270
1271 /**
1272 * @brief Analog watchdog 2 callback in non-blocking mode.
1273 * @param hadc ADC handle
1274 * @retval None
1275 */
HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef * hadc)1276 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
1277 {
1278 /* Prevent unused argument(s) compilation warning */
1279 UNUSED(hadc);
1280
1281 /* NOTE : This function should not be modified. When the callback is needed,
1282 function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
1283 */
1284 }
1285
1286 /**
1287 * @brief Analog watchdog 3 callback in non-blocking mode.
1288 * @param hadc ADC handle
1289 * @retval None
1290 */
HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef * hadc)1291 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
1292 {
1293 /* Prevent unused argument(s) compilation warning */
1294 UNUSED(hadc);
1295
1296 /* NOTE : This function should not be modified. When the callback is needed,
1297 function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
1298 */
1299 }
1300
1301
1302 /**
1303 * @brief End Of Sampling callback in non-blocking mode.
1304 * @param hadc ADC handle
1305 * @retval None
1306 */
HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef * hadc)1307 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
1308 {
1309 /* Prevent unused argument(s) compilation warning */
1310 UNUSED(hadc);
1311
1312 /* NOTE : This function should not be modified. When the callback is needed,
1313 function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
1314 */
1315 }
1316
1317 /**
1318 * @brief Stop ADC conversion of regular group (and injected channels in
1319 * case of auto_injection mode), disable ADC peripheral if no
1320 * conversion is on going on injected group.
1321 * @param hadc ADC handle
1322 * @retval HAL status.
1323 */
HAL_ADCEx_RegularStop(ADC_HandleTypeDef * hadc)1324 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
1325 {
1326 HAL_StatusTypeDef tmp_hal_status;
1327
1328 /* Check the parameters */
1329 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1330
1331 /* Process locked */
1332 __HAL_LOCK(hadc);
1333
1334 /* 1. Stop potential regular conversion on going */
1335 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1336
1337 /* Disable ADC peripheral if regular conversions are effectively stopped
1338 and if no injected conversions are on-going */
1339 if (tmp_hal_status == HAL_OK)
1340 {
1341 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1342 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1343
1344 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1345 {
1346 /* 2. Disable the ADC peripheral */
1347 tmp_hal_status = ADC_Disable(hadc);
1348
1349 /* Check if ADC is effectively disabled */
1350 if (tmp_hal_status == HAL_OK)
1351 {
1352 /* Set ADC state */
1353 ADC_STATE_CLR_SET(hadc->State,
1354 HAL_ADC_STATE_INJ_BUSY,
1355 HAL_ADC_STATE_READY);
1356 }
1357 }
1358 /* Conversion on injected group is stopped, but ADC not disabled since */
1359 /* conversion on regular group is still running. */
1360 else
1361 {
1362 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1363 }
1364 }
1365
1366 /* Process unlocked */
1367 __HAL_UNLOCK(hadc);
1368
1369 /* Return function status */
1370 return tmp_hal_status;
1371 }
1372
1373
1374 /**
1375 * @brief Stop ADC conversion of ADC groups regular and injected,
1376 * disable interrution of end-of-conversion,
1377 * disable ADC peripheral if no conversion is on going
1378 * on injected group.
1379 * @param hadc ADC handle
1380 * @retval HAL status.
1381 */
HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef * hadc)1382 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
1383 {
1384 HAL_StatusTypeDef tmp_hal_status;
1385
1386 /* Check the parameters */
1387 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1388
1389 /* Process locked */
1390 __HAL_LOCK(hadc);
1391
1392 /* 1. Stop potential regular conversion on going */
1393 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1394
1395 /* Disable ADC peripheral if conversions are effectively stopped
1396 and if no injected conversion is on-going */
1397 if (tmp_hal_status == HAL_OK)
1398 {
1399 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1400 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1401
1402 /* Disable all regular-related interrupts */
1403 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1404
1405 /* 2. Disable ADC peripheral if no injected conversions are on-going */
1406 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1407 {
1408 tmp_hal_status = ADC_Disable(hadc);
1409 /* if no issue reported */
1410 if (tmp_hal_status == HAL_OK)
1411 {
1412 /* Set ADC state */
1413 ADC_STATE_CLR_SET(hadc->State,
1414 HAL_ADC_STATE_INJ_BUSY,
1415 HAL_ADC_STATE_READY);
1416 }
1417 }
1418 else
1419 {
1420 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1421 }
1422 }
1423
1424 /* Process unlocked */
1425 __HAL_UNLOCK(hadc);
1426
1427 /* Return function status */
1428 return tmp_hal_status;
1429 }
1430
1431 /**
1432 * @brief Stop ADC conversion of regular group (and injected group in
1433 * case of auto_injection mode), disable ADC DMA transfer, disable
1434 * ADC peripheral if no conversion is on going
1435 * on injected group.
1436 * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
1437 * For multimode (when multimode feature is available),
1438 * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
1439 * @param hadc ADC handle
1440 * @retval HAL status.
1441 */
HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef * hadc)1442 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
1443 {
1444 HAL_StatusTypeDef tmp_hal_status;
1445
1446 /* Check the parameters */
1447 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1448
1449 /* Process locked */
1450 __HAL_LOCK(hadc);
1451
1452 /* 1. Stop potential regular conversion on going */
1453 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1454
1455 /* Disable ADC peripheral if conversions are effectively stopped
1456 and if no injected conversion is on-going */
1457 if (tmp_hal_status == HAL_OK)
1458 {
1459 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1460 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1461
1462 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
1463 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
1464
1465 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
1466 /* while DMA transfer is on going) */
1467 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1468
1469 /* Check if DMA channel effectively disabled */
1470 if (tmp_hal_status != HAL_OK)
1471 {
1472 /* Update ADC state machine to error */
1473 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1474 }
1475
1476 /* Disable ADC overrun interrupt */
1477 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1478
1479 /* 2. Disable the ADC peripheral */
1480 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
1481 /* to keep in memory a potential failing status. */
1482 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1483 {
1484 if (tmp_hal_status == HAL_OK)
1485 {
1486 tmp_hal_status = ADC_Disable(hadc);
1487 }
1488 else
1489 {
1490 (void)ADC_Disable(hadc);
1491 }
1492
1493 /* Check if ADC is effectively disabled */
1494 if (tmp_hal_status == HAL_OK)
1495 {
1496 /* Set ADC state */
1497 ADC_STATE_CLR_SET(hadc->State,
1498 HAL_ADC_STATE_INJ_BUSY,
1499 HAL_ADC_STATE_READY);
1500 }
1501 }
1502 else
1503 {
1504 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1505 }
1506 }
1507
1508 /* Process unlocked */
1509 __HAL_UNLOCK(hadc);
1510
1511 /* Return function status */
1512 return tmp_hal_status;
1513 }
1514
1515 #if defined(ADC_MULTIMODE_SUPPORT)
1516 /**
1517 * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected
1518 * conversion is on-going.
1519 * @note Multimode is kept enabled after this function. Multimode DMA bits
1520 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
1521 * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
1522 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
1523 * resort to HAL_ADCEx_DisableMultiMode() API.
1524 * @note In case of DMA configured in circular mode, function
1525 * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
1526 * ADC slave, to properly disable the DMA channel.
1527 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
1528 * @retval HAL status
1529 */
HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef * hadc)1530 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
1531 {
1532 HAL_StatusTypeDef tmp_hal_status;
1533 uint32_t tickstart;
1534 ADC_HandleTypeDef tmp_hadc_slave;
1535 uint32_t tmp_hadc_slave_conversion_on_going;
1536
1537 /* Check the parameters */
1538 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1539
1540 /* Process locked */
1541 __HAL_LOCK(hadc);
1542
1543
1544 /* 1. Stop potential multimode conversion on going, on regular groups */
1545 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1546
1547 /* Disable ADC peripheral if conversions are effectively stopped */
1548 if (tmp_hal_status == HAL_OK)
1549 {
1550 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1551 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1552
1553 /* Temporary handle minimum initialization */
1554 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
1555 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
1556
1557 /* Set a temporary handle of the ADC slave associated to the ADC master */
1558 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
1559
1560 if (tmp_hadc_slave.Instance == NULL)
1561 {
1562 /* Update ADC state machine to error */
1563 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1564
1565 /* Process unlocked */
1566 __HAL_UNLOCK(hadc);
1567
1568 return HAL_ERROR;
1569 }
1570
1571 /* Procedure to disable the ADC peripheral: wait for conversions */
1572 /* effectively stopped (ADC master and ADC slave), then disable ADC */
1573
1574 /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
1575 tickstart = HAL_GetTick();
1576
1577 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1578 while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1579 || (tmp_hadc_slave_conversion_on_going == 1UL)
1580 )
1581 {
1582 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
1583 {
1584 /* New check to avoid false timeout detection in case of preemption */
1585 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1586 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1587 || (tmp_hadc_slave_conversion_on_going == 1UL)
1588 )
1589 {
1590 /* Update ADC state machine to error */
1591 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1592
1593 /* Process unlocked */
1594 __HAL_UNLOCK(hadc);
1595
1596 return HAL_ERROR;
1597 }
1598 }
1599
1600 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1601 }
1602
1603 /* Disable the DMA channel (in case of DMA in circular mode or stop */
1604 /* while DMA transfer is on going) */
1605 /* Note: DMA channel of ADC slave should be stopped after this function */
1606 /* with HAL_ADCEx_RegularStop_DMA() API. */
1607 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1608
1609 /* Check if DMA channel effectively disabled */
1610 if (tmp_hal_status != HAL_OK)
1611 {
1612 /* Update ADC state machine to error */
1613 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1614 }
1615
1616 /* Disable ADC overrun interrupt */
1617 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1618
1619 /* 2. Disable the ADC peripherals: master and slave if no injected */
1620 /* conversion is on-going. */
1621 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
1622 /* memory a potential failing status. */
1623 if (tmp_hal_status == HAL_OK)
1624 {
1625 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1626 {
1627 tmp_hal_status = ADC_Disable(hadc);
1628 if (tmp_hal_status == HAL_OK)
1629 {
1630 if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) == 0UL)
1631 {
1632 tmp_hal_status = ADC_Disable(&tmp_hadc_slave);
1633 }
1634 }
1635 }
1636
1637 if (tmp_hal_status == HAL_OK)
1638 {
1639 /* Both Master and Slave ADC's could be disabled. Update Master State */
1640 /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
1641 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
1642 }
1643 else
1644 {
1645 /* injected (Master or Slave) conversions are still on-going,
1646 no Master State change */
1647 }
1648 }
1649 }
1650
1651 /* Process unlocked */
1652 __HAL_UNLOCK(hadc);
1653
1654 /* Return function status */
1655 return tmp_hal_status;
1656 }
1657 #endif /* ADC_MULTIMODE_SUPPORT */
1658
1659 /**
1660 * @}
1661 */
1662
1663 /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
1664 * @brief ADC Extended Peripheral Control functions
1665 *
1666 @verbatim
1667 ===============================================================================
1668 ##### Peripheral Control functions #####
1669 ===============================================================================
1670 [..] This section provides functions allowing to:
1671 (+) Configure channels on injected group
1672 (+) Configure multimode when multimode feature is available
1673 (+) Enable or Disable Injected Queue
1674 (+) Disable ADC voltage regulator
1675 (+) Enter ADC deep-power-down mode
1676
1677 @endverbatim
1678 * @{
1679 */
1680
1681 /**
1682 * @brief Configure a channel to be assigned to ADC group injected.
1683 * @note Possibility to update parameters on the fly:
1684 * This function initializes injected group, following calls to this
1685 * function can be used to reconfigure some parameters of structure
1686 * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
1687 * The setting of these parameters is conditioned to ADC state:
1688 * Refer to comments of structure "ADC_InjectionConfTypeDef".
1689 * @note In case of usage of internal measurement channels:
1690 * Vbat/VrefInt/TempSensor.
1691 * These internal paths can be disabled using function
1692 * HAL_ADC_DeInit().
1693 * @note Caution: For Injected Context Queue use, a context must be fully
1694 * defined before start of injected conversion. All channels are configured
1695 * consecutively for the same ADC instance. Therefore, the number of calls to
1696 * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
1697 * InjectedNbrOfConversion for each context.
1698 * - Example 1: If 1 context is intended to be used (or if there is no use of the
1699 * Injected Queue Context feature) and if the context contains 3 injected ranks
1700 * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
1701 * called once for each channel (i.e. 3 times) before starting a conversion.
1702 * This function must not be called to configure a 4th injected channel:
1703 * it would start a new context into context queue.
1704 * - Example 2: If 2 contexts are intended to be used and each of them contains
1705 * 3 injected ranks (InjectedNbrOfConversion = 3),
1706 * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
1707 * for each context (3 channels x 2 contexts = 6 calls). Conversion can
1708 * start once the 1st context is set, that is after the first three
1709 * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
1710 * @param hadc ADC handle
1711 * @param pConfigInjected Structure of ADC injected group and ADC channel for
1712 * injected group.
1713 * @retval HAL status
1714 */
HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef * hadc,const ADC_InjectionConfTypeDef * pConfigInjected)1715 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
1716 const ADC_InjectionConfTypeDef *pConfigInjected)
1717 {
1718 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1719 uint32_t tmp_offset_shifted;
1720 uint32_t tmp_config_internal_channel;
1721 uint32_t tmp_adc_is_conversion_on_going_regular;
1722 uint32_t tmp_adc_is_conversion_on_going_injected;
1723 __IO uint32_t wait_loop_index = 0;
1724
1725 uint32_t tmp_jsqr_context_queue_being_built = 0U;
1726
1727 /* Check the parameters */
1728 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1729 assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime));
1730 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff));
1731 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv));
1732 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->QueueInjectedContext));
1733 assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge));
1734 assert_param(IS_ADC_EXTTRIGINJEC(pConfigInjected->ExternalTrigInjecConv));
1735 assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber));
1736 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
1737 assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign));
1738 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedOffsetSaturation));
1739 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode));
1740
1741 if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
1742 {
1743 assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank));
1744 assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion));
1745 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode));
1746 }
1747
1748
1749 /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
1750 ignored (considered as reset) */
1751 assert_param(!((pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
1752 && (pConfigInjected->InjecOversamplingMode == ENABLE)));
1753
1754 /* JDISCEN and JAUTO bits can't be set at the same time */
1755 assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
1756 && (pConfigInjected->AutoInjectedConv == ENABLE)));
1757
1758 /* DISCEN and JAUTO bits can't be set at the same time */
1759 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE)));
1760
1761 /* Verification of channel number */
1762 if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
1763 {
1764 assert_param(IS_ADC_CHANNEL(hadc, pConfigInjected->InjectedChannel));
1765 }
1766 else
1767 {
1768 assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfigInjected->InjectedChannel));
1769 }
1770
1771 /* Process locked */
1772 __HAL_LOCK(hadc);
1773
1774 /* Configuration of injected group sequencer: */
1775 /* Hardware constraint: Must fully define injected context register JSQR */
1776 /* before make it entering into injected sequencer queue. */
1777 /* */
1778 /* - if scan mode is disabled: */
1779 /* * Injected channels sequence length is set to 0x00: 1 channel */
1780 /* converted (channel on injected rank 1) */
1781 /* Parameter "InjectedNbrOfConversion" is discarded. */
1782 /* * Injected context register JSQR setting is simple: register is fully */
1783 /* defined on one call of this function (for injected rank 1) and can */
1784 /* be entered into queue directly. */
1785 /* - if scan mode is enabled: */
1786 /* * Injected channels sequence length is set to parameter */
1787 /* "InjectedNbrOfConversion". */
1788 /* * Injected context register JSQR setting more complex: register is */
1789 /* fully defined over successive calls of this function, for each */
1790 /* injected channel rank. It is entered into queue only when all */
1791 /* injected ranks have been set. */
1792 /* Note: Scan mode is not present by hardware on this device, but used */
1793 /* by software for alignment over all STM32 devices. */
1794
1795 if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
1796 (pConfigInjected->InjectedNbrOfConversion == 1U))
1797 {
1798 /* Configuration of context register JSQR: */
1799 /* - number of ranks in injected group sequencer: fixed to 1st rank */
1800 /* (scan mode disabled, only rank 1 used) */
1801 /* - external trigger to start conversion */
1802 /* - external trigger polarity */
1803 /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
1804
1805 if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
1806 {
1807 /* Enable external trigger if trigger selection is different of */
1808 /* software start. */
1809 /* Note: This configuration keeps the hardware feature of parameter */
1810 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
1811 /* software start. */
1812 if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
1813 {
1814 tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
1815 | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
1816 | pConfigInjected->ExternalTrigInjecConvEdge
1817 );
1818 }
1819 else
1820 {
1821 tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
1822 }
1823
1824 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_jsqr_context_queue_being_built);
1825 /* For debug and informative reasons, hadc handle saves JSQR setting */
1826 hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built;
1827
1828 }
1829 }
1830 else
1831 {
1832 /* Case of scan mode enabled, several channels to set into injected group */
1833 /* sequencer. */
1834 /* */
1835 /* Procedure to define injected context register JSQR over successive */
1836 /* calls of this function, for each injected channel rank: */
1837 /* 1. Start new context and set parameters related to all injected */
1838 /* channels: injected sequence length and trigger. */
1839
1840 /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
1841 /* call of the context under setting */
1842 if (hadc->InjectionConfig.ChannelCount == 0U)
1843 {
1844 /* Initialize number of channels that will be configured on the context */
1845 /* being built */
1846 hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion;
1847 /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
1848 call, this context will be written in JSQR register at the last call.
1849 At this point, the context is merely reset */
1850 hadc->InjectionConfig.ContextQueue = 0x00000000U;
1851
1852 /* Configuration of context register JSQR: */
1853 /* - number of ranks in injected group sequencer */
1854 /* - external trigger to start conversion */
1855 /* - external trigger polarity */
1856
1857 /* Enable external trigger if trigger selection is different of */
1858 /* software start. */
1859 /* Note: This configuration keeps the hardware feature of parameter */
1860 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
1861 /* software start. */
1862 if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
1863 {
1864 tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U)
1865 | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
1866 | pConfigInjected->ExternalTrigInjecConvEdge
1867 );
1868 }
1869 else
1870 {
1871 tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U));
1872 }
1873
1874 }
1875
1876 /* 2. Continue setting of context under definition with parameter */
1877 /* related to each channel: channel rank sequence */
1878 /* Clear the old JSQx bits for the selected rank */
1879 tmp_jsqr_context_queue_being_built &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank);
1880
1881 /* Set the JSQx bits for the selected rank */
1882 tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank);
1883
1884 /* Decrease channel count */
1885 hadc->InjectionConfig.ChannelCount--;
1886
1887 /* 3. tmp_jsqr_context_queue_being_built is fully built for this HAL_ADCEx_InjectedConfigChannel()
1888 call, aggregate the setting to those already built during the previous
1889 HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
1890 hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built;
1891
1892 /* 4. End of context setting: if this is the last channel set, then write context
1893 into register JSQR and make it enter into queue */
1894 if (hadc->InjectionConfig.ChannelCount == 0U)
1895 {
1896 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
1897 }
1898 }
1899
1900 /* Parameters update conditioned to ADC state: */
1901 /* Parameters that can be updated when ADC is disabled or enabled without */
1902 /* conversion on going on injected group: */
1903 /* - Injected context queue: Queue disable (active context is kept) or */
1904 /* enable (context decremented, up to 2 contexts queued) */
1905 /* - Injected discontinuous mode: can be enabled only if auto-injected */
1906 /* mode is disabled. */
1907 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1908 {
1909 /* If auto-injected mode is disabled: no constraint */
1910 if (pConfigInjected->AutoInjectedConv == DISABLE)
1911 {
1912 MODIFY_REG(hadc->Instance->CFGR,
1913 ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
1914 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext) |
1915 ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
1916 }
1917 /* If auto-injected mode is enabled: Injected discontinuous setting is */
1918 /* discarded. */
1919 else
1920 {
1921 MODIFY_REG(hadc->Instance->CFGR,
1922 ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
1923 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext));
1924 }
1925
1926 }
1927
1928 /* Parameters update conditioned to ADC state: */
1929 /* Parameters that can be updated when ADC is disabled or enabled without */
1930 /* conversion on going on regular and injected groups: */
1931 /* - Automatic injected conversion: can be enabled if injected group */
1932 /* external triggers are disabled. */
1933 /* - Channel sampling time */
1934 /* - Channel offset */
1935 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
1936 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
1937
1938 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
1939 && (tmp_adc_is_conversion_on_going_injected == 0UL)
1940 )
1941 {
1942 /* If injected group external triggers are disabled (set to injected */
1943 /* software start): no constraint */
1944 if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
1945 || (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
1946 {
1947 if (pConfigInjected->AutoInjectedConv == ENABLE)
1948 {
1949 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
1950 }
1951 else
1952 {
1953 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
1954 }
1955 }
1956 /* If Automatic injected conversion was intended to be set and could not */
1957 /* due to injected group external triggers enabled, error is reported. */
1958 else
1959 {
1960 if (pConfigInjected->AutoInjectedConv == ENABLE)
1961 {
1962 /* Update ADC state machine to error */
1963 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1964
1965 tmp_hal_status = HAL_ERROR;
1966 }
1967 else
1968 {
1969 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
1970 }
1971 }
1972
1973 if (pConfigInjected->InjecOversamplingMode == ENABLE)
1974 {
1975 assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
1976 assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
1977
1978 /* JOVSE must be reset in case of triggered regular mode */
1979 assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)
1980 == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
1981
1982 /* Configuration of Injected Oversampler: */
1983 /* - Oversampling Ratio */
1984 /* - Right bit shift */
1985
1986 /* Enable OverSampling mode */
1987 MODIFY_REG(hadc->Instance->CFGR2,
1988 ADC_CFGR2_JOVSE |
1989 ADC_CFGR2_OVSR |
1990 ADC_CFGR2_OVSS,
1991 ADC_CFGR2_JOVSE |
1992 pConfigInjected->InjecOversampling.Ratio |
1993 pConfigInjected->InjecOversampling.RightBitShift
1994 );
1995 }
1996 else
1997 {
1998 /* Disable Regular OverSampling */
1999 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
2000 }
2001
2002 /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
2003 if (pConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
2004 {
2005 /* Set sampling time of the selected ADC channel */
2006 LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
2007
2008 /* Set ADC sampling time common configuration */
2009 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
2010 }
2011 else
2012 {
2013 /* Set sampling time of the selected ADC channel */
2014 LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
2015 pConfigInjected->InjectedSamplingTime);
2016
2017 /* Set ADC sampling time common configuration */
2018 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
2019 }
2020
2021 /* Configure the offset: offset enable/disable, channel, offset value */
2022
2023 /* Shift the offset with respect to the selected ADC resolution. */
2024 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
2025 tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset);
2026
2027 if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
2028 {
2029 /* Set ADC selected offset number */
2030 LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel,
2031 tmp_offset_shifted);
2032
2033 /* Set ADC selected offset sign & saturation */
2034 LL_ADC_SetOffsetSign(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedOffsetSign);
2035 LL_ADC_SetOffsetSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
2036 (pConfigInjected->InjectedOffsetSaturation == ENABLE) ?
2037 LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
2038 }
2039 else
2040 {
2041 /* Scan each offset register to check if the selected channel is targeted. */
2042 /* If this is the case, the corresponding offset number is disabled. */
2043 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
2044 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
2045 {
2046 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
2047 }
2048 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
2049 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
2050 {
2051 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
2052 }
2053 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
2054 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
2055 {
2056 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
2057 }
2058 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
2059 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
2060 {
2061 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
2062 }
2063 }
2064
2065 }
2066
2067 /* Parameters update conditioned to ADC state: */
2068 /* Parameters that can be updated only when ADC is disabled: */
2069 /* - Single or differential mode */
2070 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2071 {
2072 /* Set mode single-ended or differential input of the selected ADC channel */
2073 LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff);
2074
2075 /* Configuration of differential mode */
2076 /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
2077 if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
2078 {
2079 /* Set sampling time of the selected ADC channel */
2080 LL_ADC_SetChannelSamplingTime(hadc->Instance,
2081 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
2082 (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
2083 (uint32_t)pConfigInjected->InjectedChannel)
2084 + 1UL) & 0x1FUL)),
2085 pConfigInjected->InjectedSamplingTime);
2086 }
2087
2088 }
2089
2090 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
2091 /* internal measurement paths enable: If internal channel selected, */
2092 /* enable dedicated internal buffers and path. */
2093 /* Note: these internal measurement paths can be disabled using */
2094 /* HAL_ADC_DeInit(). */
2095
2096 if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel))
2097 {
2098 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2099
2100 /* If the requested internal measurement path has already been enabled, */
2101 /* bypass the configuration processing. */
2102 if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
2103 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
2104 {
2105 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
2106 {
2107 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2108 LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
2109
2110 /* Delay for temperature sensor stabilization time */
2111 /* Wait loop initialization and execution */
2112 /* Note: Variable divided by 2 to compensate partially */
2113 /* CPU processing cycles, scaling in us split to not */
2114 /* exceed 32 bits register capacity and handle low frequency. */
2115 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL)
2116 * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
2117 while (wait_loop_index != 0UL)
2118 {
2119 wait_loop_index--;
2120 }
2121 }
2122 }
2123 else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
2124 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
2125 {
2126 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
2127 {
2128 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2129 LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
2130 }
2131 }
2132 else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
2133 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
2134 {
2135 if (ADC_VREFINT_INSTANCE(hadc))
2136 {
2137 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2138 LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
2139 }
2140 }
2141 else if (pConfigInjected->InjectedChannel == ADC_CHANNEL_VDDCORE)
2142 {
2143 if (ADC_VDDCORE_INSTANCE(hadc))
2144 {
2145 LL_ADC_SetPathInternalChAdd(hadc->Instance, LL_ADC_PATH_INTERNAL_VDDCORE);
2146 }
2147 }
2148 else
2149 {
2150 /* nothing to do */
2151 }
2152 }
2153
2154 /* Process unlocked */
2155 __HAL_UNLOCK(hadc);
2156
2157 /* Return function status */
2158 return tmp_hal_status;
2159 }
2160
2161 #if defined(ADC_MULTIMODE_SUPPORT)
2162 /**
2163 * @brief Enable ADC multimode and configure multimode parameters
2164 * @note Possibility to update parameters on the fly:
2165 * This function initializes multimode parameters, following
2166 * calls to this function can be used to reconfigure some parameters
2167 * of structure "ADC_MultiModeTypeDef" on the fly, without resetting
2168 * the ADCs.
2169 * The setting of these parameters is conditioned to ADC state.
2170 * For parameters constraints, see comments of structure
2171 * "ADC_MultiModeTypeDef".
2172 * @note To move back configuration from multimode to single mode, ADC must
2173 * be reset (using function HAL_ADC_Init() ).
2174 * @param hadc Master ADC handle
2175 * @param pMultimode Structure of ADC multimode configuration
2176 * @retval HAL status
2177 */
HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef * hadc,const ADC_MultiModeTypeDef * pMultimode)2178 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
2179 {
2180 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2181 ADC_Common_TypeDef *tmpADC_Common;
2182 ADC_HandleTypeDef tmp_hadc_slave;
2183 uint32_t tmp_hadc_slave_conversion_on_going;
2184
2185 /* Check the parameters */
2186 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
2187 assert_param(IS_ADC_MULTIMODE(pMultimode->Mode));
2188 if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
2189 {
2190 assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
2191 assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
2192 }
2193
2194 /* Process locked */
2195 __HAL_LOCK(hadc);
2196
2197 /* Temporary handle minimum initialization */
2198 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
2199 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
2200
2201 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
2202
2203 if (tmp_hadc_slave.Instance == NULL)
2204 {
2205 /* Update ADC state machine to error */
2206 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2207
2208 /* Process unlocked */
2209 __HAL_UNLOCK(hadc);
2210
2211 return HAL_ERROR;
2212 }
2213
2214 /* Parameters update conditioned to ADC state: */
2215 /* Parameters that can be updated when ADC is disabled or enabled without */
2216 /* conversion on going on regular group: */
2217 /* - Multimode DMA configuration */
2218 /* - Multimode DMA mode */
2219 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
2220 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2221 && (tmp_hadc_slave_conversion_on_going == 0UL))
2222 {
2223 /* Pointer to the common control register */
2224 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
2225
2226 /* If multimode is selected, configure all multimode parameters. */
2227 /* Otherwise, reset multimode parameters (can be used in case of */
2228 /* transition from multimode to independent mode). */
2229 if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
2230 {
2231 MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
2232 pMultimode->DMAAccessMode |
2233 ADC_CCR_MULTI_DMACONTREQ((hadc->Init.ConversionDataManagement & ADC_CFGR_DMACFG)
2234 >> ADC_CFGR_DMACFG_Pos));
2235
2236 /* Parameters that can be updated only when ADC is disabled: */
2237 /* - Multimode mode selection */
2238 /* - Multimode delay */
2239 /* Note: Delay range depends on selected resolution: */
2240 /* from 1 to 12 clock cycles for 12 bits */
2241 /* from 1 to 10 clock cycles for 10 bits, */
2242 /* from 1 to 8 clock cycles for 8 bits */
2243 /* from 1 to 6 clock cycles for 6 bits */
2244 /* If a higher delay is selected, it will be clipped to maximum delay */
2245 /* range */
2246 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2247 {
2248 MODIFY_REG(tmpADC_Common->CCR,
2249 ADC_CCR_DUAL |
2250 ADC_CCR_DELAY,
2251 pMultimode->Mode |
2252 pMultimode->TwoSamplingDelay
2253 );
2254 }
2255 }
2256 else /* ADC_MODE_INDEPENDENT */
2257 {
2258 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
2259
2260 /* Parameters that can be updated only when ADC is disabled: */
2261 /* - Multimode mode selection */
2262 /* - Multimode delay */
2263 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2264 {
2265 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
2266 }
2267 }
2268 }
2269 /* If one of the ADC sharing the same common group is enabled, no update */
2270 /* could be done on neither of the multimode structure parameters. */
2271 else
2272 {
2273 /* Update ADC state machine to error */
2274 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2275
2276 tmp_hal_status = HAL_ERROR;
2277 }
2278
2279 /* Process unlocked */
2280 __HAL_UNLOCK(hadc);
2281
2282 /* Return function status */
2283 return tmp_hal_status;
2284 }
2285 #endif /* ADC_MULTIMODE_SUPPORT */
2286
2287 /**
2288 * @brief Enable Injected Queue
2289 * @note This function resets CFGR register JQDIS bit in order to enable the
2290 * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
2291 * are both equal to 0 to ensure that no regular nor injected
2292 * conversion is ongoing.
2293 * @param hadc ADC handle
2294 * @retval HAL status
2295 */
HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef * hadc)2296 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
2297 {
2298 HAL_StatusTypeDef tmp_hal_status;
2299 uint32_t tmp_adc_is_conversion_on_going_regular;
2300 uint32_t tmp_adc_is_conversion_on_going_injected;
2301
2302 /* Check the parameters */
2303 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2304
2305 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2306 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2307
2308 /* Parameter can be set only if no conversion is on-going */
2309 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2310 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2311 )
2312 {
2313 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
2314
2315 /* Update state, clear previous result related to injected queue overflow */
2316 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
2317
2318 tmp_hal_status = HAL_OK;
2319 }
2320 else
2321 {
2322 tmp_hal_status = HAL_ERROR;
2323 }
2324
2325 return tmp_hal_status;
2326 }
2327
2328 /**
2329 * @brief Disable Injected Queue
2330 * @note This function sets CFGR register JQDIS bit in order to disable the
2331 * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
2332 * are both equal to 0 to ensure that no regular nor injected
2333 * conversion is ongoing.
2334 * @param hadc ADC handle
2335 * @retval HAL status
2336 */
HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef * hadc)2337 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
2338 {
2339 HAL_StatusTypeDef tmp_hal_status;
2340 uint32_t tmp_adc_is_conversion_on_going_regular;
2341 uint32_t tmp_adc_is_conversion_on_going_injected;
2342
2343 /* Check the parameters */
2344 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2345
2346 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2347 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2348
2349 /* Parameter can be set only if no conversion is on-going */
2350 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2351 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2352 )
2353 {
2354 LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
2355 tmp_hal_status = HAL_OK;
2356 }
2357 else
2358 {
2359 tmp_hal_status = HAL_ERROR;
2360 }
2361
2362 return tmp_hal_status;
2363 }
2364
2365 /**
2366 * @brief Disable ADC voltage regulator.
2367 * @note Disabling voltage regulator allows to save power. This operation can
2368 * be carried out only when ADC is disabled.
2369 * @note To enable again the voltage regulator, the user is expected to
2370 * resort to HAL_ADC_Init() API.
2371 * @param hadc ADC handle
2372 * @retval HAL status
2373 */
HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef * hadc)2374 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
2375 {
2376 HAL_StatusTypeDef tmp_hal_status;
2377
2378 /* Check the parameters */
2379 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2380
2381 /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
2382 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2383 {
2384 LL_ADC_DisableInternalRegulator(hadc->Instance);
2385 tmp_hal_status = HAL_OK;
2386 }
2387 else
2388 {
2389 tmp_hal_status = HAL_ERROR;
2390 }
2391
2392 return tmp_hal_status;
2393 }
2394
2395 /**
2396 * @brief Enter ADC deep-power-down mode
2397 * @note This mode is achieved in setting DEEPPWD bit and allows to save power
2398 * in reducing leakage currents. It is particularly interesting before
2399 * entering stop modes.
2400 * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
2401 * ADC voltage regulator. This means that this API encompasses
2402 * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
2403 * calibration is lost.
2404 * @note To exit the ADC deep-power-down mode, the user is expected to
2405 * resort to HAL_ADC_Init() API as well as to relaunch a calibration
2406 * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
2407 * saved calibration factor.
2408 * @param hadc ADC handle
2409 * @retval HAL status
2410 */
HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef * hadc)2411 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
2412 {
2413 HAL_StatusTypeDef tmp_hal_status;
2414
2415 /* Check the parameters */
2416 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2417
2418 /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
2419 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2420 {
2421 LL_ADC_EnableDeepPowerDown(hadc->Instance);
2422 tmp_hal_status = HAL_OK;
2423 }
2424 else
2425 {
2426 tmp_hal_status = HAL_ERROR;
2427 }
2428
2429 return tmp_hal_status;
2430 }
2431
2432 /**
2433 * @}
2434 */
2435
2436 /**
2437 * @}
2438 */
2439
2440 #endif /* HAL_ADC_MODULE_ENABLED */
2441 /**
2442 * @}
2443 */
2444
2445 /**
2446 * @}
2447 */
2448
